From cb2d4423b682b38c05f4f675044761ef16ccca94 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Fri, 16 Jan 2015 10:49:38 +0000
Subject: [PATCH] -Removed diag_lib -Changed all ddr3 references to io_ddr
-Renamed and removed some portnames -CHanged the ouptut definition of address
and burstsize
---
.../reorder/src/vhdl/reorder_sequencer.vhd | 81 +++++++++----------
1 file changed, 38 insertions(+), 43 deletions(-)
diff --git a/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd b/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
index bc87974019..39042c2a84 100644
--- a/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
@@ -18,18 +18,17 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-LIBRARY IEEE, common_lib, diag_lib;
+LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE diag_lib.diag_pkg.ALL;
-USE work.ddr3_pkg.ALL;
+USE work.reorder_pkg.ALL;
-ENTITY ddr3_seq IS
+ENTITY reorder_sequencer IS
GENERIC (
- g_ddr3_seq : t_ddr3_seq := c_ddr3_seq;
- g_ddr : t_c_ddr3_phy
- );
+ g_reorder_seq : t_reorder_seq := c_reorder_seq;
+ g_data_w_ratio : POSITIVE := 4 -- (256/64) Ratio between datawidth at the output of the write fifo and the input of the writefifo.
+ ); -- Used to determine the c_address_w.
PORT (
-- Clocks and reset
dp_rst : IN STD_LOGIC; -- reset synchronous with st_clk
@@ -38,25 +37,24 @@ ENTITY ddr3_seq IS
en_evt : OUT STD_LOGIC;
wr_not_rd : OUT STD_LOGIC;
- start_addr : OUT t_ddr3_addr;
- end_addr : OUT t_ddr3_addr;
+ address : OUT STD_LOGIC_VECTOR;
+ burstsize : OUT STD_LOGIC_VECTOR;
done : IN STD_LOGIC;
- init_done : IN STD_LOGIC;
- ctlr_rdy : IN STD_LOGIC;
sync_ok_in : IN STD_LOGIC;
sync_ok_out : OUT STD_LOGIC
);
-END ddr3_seq;
+END reorder_sequencer;
-ARCHITECTURE rtl OF ddr3_seq IS
+ARCHITECTURE rtl OF reorder_sequencer IS
- CONSTANT c_blocksize : POSITIVE := g_ddr3_seq.wr_nof_chunks * (g_ddr3_seq.wr_chunksize + g_ddr3_seq.gapsize);
- CONSTANT c_page_size : POSITIVE := c_blocksize * g_ddr3_seq.nof_blocks;
- CONSTANT c_nof_wr_access : POSITIVE := g_ddr3_seq.wr_nof_chunks * g_ddr3_seq.nof_blocks;
- CONSTANT c_address_w : POSITIVE := sel_a_b(ceil_log2(2*c_page_size) > g_ddr.a_col_w, ceil_log2(2*c_page_size), g_ddr.a_col_w);
+ CONSTANT c_blocksize : POSITIVE := g_reorder_seq.wr_nof_chunks * (g_reorder_seq.wr_chunksize + g_reorder_seq.gapsize);
+ CONSTANT c_page_size : POSITIVE := c_blocksize * g_reorder_seq.nof_blocks;
+ CONSTANT c_nof_wr_access : POSITIVE := g_reorder_seq.wr_nof_chunks * g_reorder_seq.nof_blocks;
+ CONSTANT c_address_w : POSITIVE := ceil_log2(2*c_page_size);
+ CONSTANT c_address_shift_w : POSITIVE := ceil_log2(g_data_w_ratio);
TYPE state_type is (s_idle, s_write, s_first_write, s_wait_wr, s_read, s_wait_rd);
@@ -79,6 +77,7 @@ ARCHITECTURE rtl OF ddr3_seq IS
sync_ok_out : STD_LOGIC;
start_addr : STD_LOGIC_VECTOR(c_address_w - 1 DOWNTO 0);
end_addr : STD_LOGIC_VECTOR(c_address_w - 1 DOWNTO 0);
+ burstsize : STD_LOGIC_VECTOR(c_address_w - 1 DOWNTO 0);
state : state_type; -- The state machine.
END RECORD;
@@ -89,9 +88,9 @@ BEGIN
---------------------------------------------------------------
-- CHECK IF PROVIDED GENERICS ARE ALLOWED.
---------------------------------------------------------------
- ASSERT NOT((g_ddr3_seq.wr_nof_chunks*g_ddr3_seq.wr_chunksize) /= (g_ddr3_seq.rd_nof_chunks*g_ddr3_seq.rd_chunksize) AND rising_edge(dp_clk)) REPORT "Total write configuration is different from total read configuration!!!" SEVERITY FAILURE;
+ ASSERT NOT((g_reorder_seq.wr_nof_chunks*g_reorder_seq.wr_chunksize) /= (g_reorder_seq.rd_nof_chunks*g_reorder_seq.rd_chunksize) AND rising_edge(dp_clk)) REPORT "Total write configuration is different from total read configuration!!!" SEVERITY FAILURE;
- p_comb : PROCESS(r, dp_rst, init_done, done, ctlr_rdy, sync_ok_in)
+ p_comb : PROCESS(r, dp_rst, done, sync_ok_in)
VARIABLE v : reg_type;
BEGIN
@@ -100,7 +99,7 @@ BEGIN
CASE r.state IS
WHEN s_idle =>
- IF(init_done = '1' AND sync_ok_in = '1') THEN
+ IF(done = '1' AND sync_ok_in = '1') THEN
v.first_write := '1';
v.sync_ok_out := sync_ok_in;
v.state := s_first_write;
@@ -110,32 +109,34 @@ BEGIN
v.wr_not_rd := '1';
v.ddr3_en := '1';
v.start_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset + r.wr_chunks_offset, c_address_w);
- v.end_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset + r.wr_chunks_offset + g_ddr3_seq.wr_chunksize-4, c_address_w);
+ v.burstsize := TO_UVEC(g_reorder_seq.wr_chunksize, c_address_w);
+ v.end_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset + r.wr_chunks_offset + g_reorder_seq.wr_chunksize-4, c_address_w);
v.switch_cnt := r.switch_cnt + 1;
v.state := s_wait_wr;
WHEN s_write =>
- IF(done = '1' AND ctlr_rdy = '1') THEN
+ IF(done = '1') THEN
v.wr_not_rd := '1';
IF(sync_ok_in = '1') THEN -- Only write when good sync pattern on the input.
v.ddr3_en := '1';
END IF;
v.start_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset + r.wr_chunks_offset, c_address_w);
- v.end_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset + r.wr_chunks_offset + g_ddr3_seq.wr_chunksize-4, c_address_w);
+ v.burstsize := TO_UVEC(g_reorder_seq.wr_chunksize, c_address_w);
+ v.end_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset + r.wr_chunks_offset + g_reorder_seq.wr_chunksize-4, c_address_w);
v.switch_cnt := r.switch_cnt + 1;
v.state := s_wait_wr;
END IF;
WHEN s_wait_wr =>
v.page_cnt := r.page_cnt + 1;
- IF(r.wr_block_cnt = g_ddr3_seq.nof_blocks-1 AND r.wr_chunks_cnt = g_ddr3_seq.wr_nof_chunks-1) THEN
+ IF(r.wr_block_cnt = g_reorder_seq.nof_blocks-1 AND r.wr_chunks_cnt = g_reorder_seq.wr_nof_chunks-1) THEN
v.wr_block_offset := 0;
v.wr_chunks_offset := 0;
v.wr_block_cnt := 0;
v.wr_chunks_cnt := 0;
- ELSIF(r.wr_block_cnt = g_ddr3_seq.nof_blocks-1) THEN
+ ELSIF(r.wr_block_cnt = g_reorder_seq.nof_blocks-1) THEN
v.wr_block_offset := 0;
- v.wr_chunks_offset := r.wr_chunks_offset + g_ddr3_seq.wr_chunksize;
+ v.wr_chunks_offset := r.wr_chunks_offset + g_reorder_seq.wr_chunksize;
v.wr_block_cnt := 0;
v.wr_chunks_cnt := r.wr_chunks_cnt + 1;
ELSE
@@ -143,7 +144,7 @@ BEGIN
v.wr_block_cnt := r.wr_block_cnt + 1;
END IF;
- IF(r.switch_cnt = g_ddr3_seq.wr_nof_chunks) THEN
+ IF(r.switch_cnt = g_reorder_seq.wr_nof_chunks) THEN
v.switch_cnt := 0;
v.state := s_read;
ELSE
@@ -151,27 +152,28 @@ BEGIN
END IF;
WHEN s_read =>
- IF(done = '1' AND ctlr_rdy = '1') THEN
+ IF(done = '1') THEN
v.wr_not_rd := '0';
IF( r.first_write = '0') THEN
v.ddr3_en := '1';
END IF;
v.start_addr := TO_UVEC(r.rd_page_offset + r.rd_block_offset + r.rd_chunks_offset, c_address_w);
- v.end_addr := TO_UVEC(r.rd_page_offset + r.rd_block_offset + r.rd_chunks_offset + g_ddr3_seq.rd_chunksize-4, c_address_w);
+ v.burstsize := TO_UVEC(g_reorder_seq.rd_chunksize, c_address_w);
+ v.end_addr := TO_UVEC(r.rd_page_offset + r.rd_block_offset + r.rd_chunks_offset + g_reorder_seq.rd_chunksize-4, c_address_w);
v.switch_cnt := r.switch_cnt + 1;
v.state := s_wait_rd;
v.sync_ok_out := sync_ok_in;
END IF;
WHEN s_wait_rd =>
- IF(r.switch_cnt = g_ddr3_seq.rd_nof_chunks) THEN
+ IF(r.switch_cnt = g_reorder_seq.rd_nof_chunks) THEN
v.switch_cnt := 0;
v.state := s_write;
ELSE
v.state := s_read;
END IF;
- IF(r.rd_block_cnt = g_ddr3_seq.nof_blocks-1 AND r.rd_chunks_cnt = g_ddr3_seq.rd_nof_chunks-1) THEN
+ IF(r.rd_block_cnt = g_reorder_seq.nof_blocks-1 AND r.rd_chunks_cnt = g_reorder_seq.rd_nof_chunks-1) THEN
v.rd_block_offset := 0;
v.rd_chunks_offset := 0;
v.rd_block_cnt := 0;
@@ -185,9 +187,9 @@ BEGIN
v.state := s_idle;
END IF;
END IF;
- ELSIF(r.rd_block_cnt = g_ddr3_seq.nof_blocks-1) THEN
+ ELSIF(r.rd_block_cnt = g_reorder_seq.nof_blocks-1) THEN
v.rd_block_offset := 0;
- v.rd_chunks_offset := r.rd_chunks_offset + g_ddr3_seq.rd_chunksize;
+ v.rd_chunks_offset := r.rd_chunks_offset + g_reorder_seq.rd_chunksize;
v.rd_block_cnt := 0;
v.rd_chunks_cnt := r.rd_chunks_cnt + 1;
ELSE
@@ -217,6 +219,7 @@ BEGIN
v.rd_chunks_cnt := 0;
v.sync_ok_out := '0';
v.start_addr := (OTHERS => '0');
+ v.burstsize := (OTHERS => '0');
v.end_addr := (OTHERS => '0');
v.first_write := '1';
v.state := s_idle;
@@ -236,16 +239,8 @@ BEGIN
en_evt <= r.ddr3_en;
wr_not_rd <= r.wr_not_rd;
sync_ok_out <= r.sync_ok_out;
-
- address : PROCESS(r)
- BEGIN
- start_addr <= c_ddr3_addr_lo;
- end_addr <= c_ddr3_addr_lo;
- start_addr.column <= r.start_addr(c_ddr3_phy.a_col_w-1 DOWNTO 0);
- end_addr.column <= r.end_addr(c_ddr3_phy.a_col_w-1 DOWNTO 0);
- start_addr.row(c_address_w-c_ddr3_phy.a_col_w-1 DOWNTO 0) <= r.start_addr(c_address_w-1 DOWNTO c_ddr3_phy.a_col_w);
- end_addr.row(c_address_w-c_ddr3_phy.a_col_w-1 DOWNTO 0) <= r.end_addr(c_address_w-1 DOWNTO c_ddr3_phy.a_col_w);
- END PROCESS;
+ address <= RESIZE_UVEC(r.start_addr(c_address_w-1 DOWNTO c_address_shift_w), address'LENGTH);
+ burstsize <= RESIZE_UVEC(r.burstsize(c_address_w-1 DOWNTO c_address_shift_w), burstsize'LENGTH);
END rtl;
--
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