From caca34b7f5d70d63ebfd5604279c9face11001ea Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Tue, 6 Apr 2021 11:05:08 +0200
Subject: [PATCH] Updated sdp station qsys and added revisions + Cleaned up
files
---
.../quartus/qsys_lofar2_unb2b_adc.qsys | 60 +-
.../lofar2_unb2b_sdp_station/hdllib.cfg | 2 -
.../qsys_lofar2_unb2b_sdp_station_cpu_0.ip | 14 +-
...lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip} | 48 +-
...nb2b_sdp_station_ram_diag_data_buf_jesd.ip | 1447 ------
...b_sdp_station_ram_diag_data_buffer_bsn.ip} | 44 +-
...lofar2_unb2b_sdp_station_reg_bsn_source.ip | 18 +-
...nb2b_sdp_station_reg_diag_data_buf_jesd.ip | 1447 ------
...b_sdp_station_reg_diag_data_buffer_bsn.ip} | 26 +-
...far2_unb2b_sdp_station_reg_nw_10gbe_mac.ip | 4 +-
.../qsys_lofar2_unb2b_sdp_station.qsys | 4452 ++++++-----------
.../hdllib.cfg | 98 -
.../lofar2_unb2b_sdp_station_adc/hdllib.cfg | 93 +
.../lofar2_unb2b_sdp_station_adc.vhd | 163 +
.../tb_lofar2_unb2b_sdp_station_adc.vhd | 301 ++
.../lofar2_unb2b_sdp_station_bf/hdllib.cfg | 99 +
.../lofar2_unb2b_sdp_station_bf.vhd} | 18 +-
.../tb_lofar2_unb2b_sdp_station_bf.vhd} | 30 +-
.../lofar2_unb2b_sdp_station_fsub/hdllib.cfg | 98 +
.../lofar2_unb2b_sdp_station_fsub.vhd | 162 +
.../tb_lofar2_unb2b_sdp_station_fsub.vhd | 359 ++
.../src/vhdl/lofar2_unb2b_sdp_station.vhd | 515 +-
.../src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd | 23 +-
.../src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd | 83 +-
.../qsys_lofar2_unb2b_sdp_station_pkg.vhd | 619 ++-
.../lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd | 3 +-
26 files changed, 3534 insertions(+), 6692 deletions(-)
rename applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/{qsys_lofar2_unb2b_sdp_station_ram_aduh_monitor.ip => qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip} (97%)
delete mode 100644 applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buf_jesd.ip
rename applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/{qsys_lofar2_unb2b_sdp_station_ram_diag_data_buf_bsn.ip => qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip} (97%)
delete mode 100644 applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buf_jesd.ip
rename applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/{qsys_lofar2_unb2b_sdp_station_reg_diag_data_buf_bsn.ip => qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip} (98%)
delete mode 100644 applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_beamformer_one_node/hdllib.cfg
create mode 100644 applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
create mode 100644 applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
create mode 100644 applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
create mode 100644 applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
rename applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/{lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd => lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd} (89%)
rename applications/lofar2/designs/lofar2_unb2b_sdp_station/{tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd => revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd} (95%)
create mode 100644 applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
create mode 100644 applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
create mode 100644 applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys
index 5a371bd905..b19ec48cc9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys
@@ -3161,7 +3161,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -3397,7 +3397,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -5492,7 +5492,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -6048,7 +6048,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
@@ -6495,7 +6495,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
@@ -7208,7 +7208,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_2.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_2.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -7824,7 +7824,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -8440,7 +8440,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -8991,7 +8991,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
@@ -9684,7 +9684,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -10916,7 +10916,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -11532,7 +11532,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -12148,7 +12148,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -12764,7 +12764,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -13380,7 +13380,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -14612,7 +14612,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -15228,7 +15228,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -15844,7 +15844,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -16460,7 +16460,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -17076,7 +17076,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -17692,7 +17692,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -18308,7 +18308,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -18924,7 +18924,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -19540,7 +19540,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -20156,7 +20156,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -20772,7 +20772,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -21388,7 +21388,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -22004,7 +22004,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -22620,7 +22620,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -23291,7 +23291,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../../../../hdl/build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip</parameter>
+ <parameter name="logicalView">../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
index 8d41a5ccb6..eb210374c4 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
@@ -19,10 +19,8 @@ synth_files =
src/vhdl/lofar2_unb2b_sdp_station.vhd
test_bench_files =
- tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
regression_test_vhdl =
- tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
[modelsim_project_file]
modelsim_copy_files =
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
index 5e30052de0..408325eb93 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
@@ -1018,7 +1018,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>19</spirit:right>
+ <spirit:right>23</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -2153,7 +2153,7 @@
<spirit:parameter>
<spirit:name>dataAddrWidth</spirit:name>
<spirit:displayName>dataAddrWidth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="dataAddrWidth">20</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="dataAddrWidth">24</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0AddrWidth</spirit:name>
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3440' end='0x3480' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_epcs.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_remu.mem' start='0x34C0' end='0x34E0' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x34E0' end='0x34F0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x34F0' end='0x3500' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x3500' end='0x3510' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x3510' end='0x3520' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3520' end='0x3528' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3528' end='0x3530' datawidth='32' /><slave name='reg_si.mem' start='0x3530' end='0x3538' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3538' end='0x3540' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3540' end='0x3548' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3548' end='0x3550' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3550' end='0x3558' datawidth='32' /><slave name='pio_pps.mem' start='0x3558' end='0x3560' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3560' end='0x3568' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_wg.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xA0000' end='0xA8000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0xA8000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0xB4000' end='0xB6000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0xB6000' end='0xB7000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3440' end='0x3480' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_epcs.mem' start='0x34C0' end='0x34E0' datawidth='32' /><slave name='reg_remu.mem' start='0x34E0' end='0x3500' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3500' end='0x3510' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x3510' end='0x3520' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x3520' end='0x3528' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3528' end='0x3530' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3530' end='0x3538' datawidth='32' /><slave name='reg_si.mem' start='0x3538' end='0x3540' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3540' end='0x3548' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3548' end='0x3550' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3550' end='0x3558' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3558' end='0x3560' datawidth='32' /><slave name='pio_pps.mem' start='0x3560' end='0x3568' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3568' end='0x3570' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_wg.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x90000' end='0x98000' datawidth='32' /><slave name='jesd204b.mem' start='0x98000' end='0x9C000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x9C000' end='0x9D000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -2368,7 +2368,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.DATA_ADDR_WIDTH</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DATA_ADDR_WIDTH">20</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DATA_ADDR_WIDTH">24</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.DCACHE_LINE_SIZE</spirit:name>
@@ -2668,7 +2668,7 @@
<name>d_address</name>
<role>address</role>
<direction>Output</direction>
- <width>20</width>
+ <width>24</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -3489,11 +3489,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3440' end='0x3480' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_epcs.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_remu.mem' start='0x34C0' end='0x34E0' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x34E0' end='0x34F0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x34F0' end='0x3500' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x3500' end='0x3510' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x3510' end='0x3520' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3520' end='0x3528' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3528' end='0x3530' datawidth='32' /><slave name='reg_si.mem' start='0x3530' end='0x3538' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3538' end='0x3540' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3540' end='0x3548' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3548' end='0x3550' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3550' end='0x3558' datawidth='32' /><slave name='pio_pps.mem' start='0x3558' end='0x3560' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3560' end='0x3568' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_wg.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xA0000' end='0xA8000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0xA8000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0xB4000' end='0xB6000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0xB6000' end='0xB7000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3440' end='0x3480' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_epcs.mem' start='0x34C0' end='0x34E0' datawidth='32' /><slave name='reg_remu.mem' start='0x34E0' end='0x3500' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3500' end='0x3510' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x3510' end='0x3520' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x3520' end='0x3528' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3528' end='0x3530' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3530' end='0x3538' datawidth='32' /><slave name='reg_si.mem' start='0x3538' end='0x3540' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3540' end='0x3548' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3548' end='0x3550' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3550' end='0x3558' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3558' end='0x3560' datawidth='32' /><slave name='pio_pps.mem' start='0x3560' end='0x3568' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3568' end='0x3570' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_wg.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x90000' end='0x98000' datawidth='32' /><slave name='jesd204b.mem' start='0x98000' end='0x9C000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x9C000' end='0x9D000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>20</value>
+ <value>24</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_aduh_monitor.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_aduh_monitor.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
index dad1b7eee5..bd44acd464 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_aduh_monitor.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_ram_aduh_monitor</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_filterbank_ram_aduh_monitor</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">32768</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -605,10 +605,6 @@
<spirit:name>avs_mem_address</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>12</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -701,10 +697,6 @@
<spirit:name>coe_address_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>12</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -774,7 +766,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_ram_aduh_monitor</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -783,7 +775,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">13</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +838,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +902,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +971,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1366,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1406,38 +1398,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buf_jesd.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buf_jesd.ip
deleted file mode 100644
index a399b2dfc7..0000000000
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buf_jesd.ip
+++ /dev/null
@@ -1,1447 +0,0 @@
-<?xml version="1.0" ?>
-<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
- <spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buf_jesd</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>address</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_address_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>clk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_clk_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>mem</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>address</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_address</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>write</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_write</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>writedata</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_writedata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>read</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_read</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>readdata</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_readdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>addressAlignment</spirit:name>
- <spirit:displayName>Slave addressing</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressGroup</spirit:name>
- <spirit:displayName>Address group</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressSpan</spirit:name>
- <spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">8192</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressUnits</spirit:name>
- <spirit:displayName>Address units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>alwaysBurstMaxBurst</spirit:name>
- <spirit:displayName>Always burst maximum burst</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>Associated reset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bitsPerSymbol</spirit:name>
- <spirit:displayName>Bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bridgedAddressOffset</spirit:name>
- <spirit:displayName>Bridged Address Offset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bridgesToMaster</spirit:name>
- <spirit:displayName>Bridges to master</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
- <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>burstcountUnits</spirit:name>
- <spirit:displayName>Burstcount units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>constantBurstBehavior</spirit:name>
- <spirit:displayName>Constant burst behavior</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>explicitAddressSpan</spirit:name>
- <spirit:displayName>Explicit address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>holdTime</spirit:name>
- <spirit:displayName>Hold</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>interleaveBursts</spirit:name>
- <spirit:displayName>Interleave bursts</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isBigEndian</spirit:name>
- <spirit:displayName>Big endian</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isFlash</spirit:name>
- <spirit:displayName>Flash memory</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isMemoryDevice</spirit:name>
- <spirit:displayName>Memory device</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isNonVolatileStorage</spirit:name>
- <spirit:displayName>Non-volatile storage</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>linewrapBursts</spirit:name>
- <spirit:displayName>Linewrap bursts</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maximumPendingReadTransactions</spirit:name>
- <spirit:displayName>Maximum pending read transactions</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maximumPendingWriteTransactions</spirit:name>
- <spirit:displayName>Maximum pending write transactions</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumReadLatency</spirit:name>
- <spirit:displayName>minimumReadLatency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumResponseLatency</spirit:name>
- <spirit:displayName>Minimum response latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumUninterruptedRunLength</spirit:name>
- <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>printableDevice</spirit:name>
- <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readLatency</spirit:name>
- <spirit:displayName>Read latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readWaitStates</spirit:name>
- <spirit:displayName>Read wait states</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readWaitTime</spirit:name>
- <spirit:displayName>Read wait</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>registerIncomingSignals</spirit:name>
- <spirit:displayName>Register incoming signals</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>registerOutgoingSignals</spirit:name>
- <spirit:displayName>Register outgoing signals</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>setupTime</spirit:name>
- <spirit:displayName>Setup</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>timingUnits</spirit:name>
- <spirit:displayName>Timing units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>transparentBridge</spirit:name>
- <spirit:displayName>Transparent bridge</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>waitrequestAllowance</spirit:name>
- <spirit:displayName>Waitrequest allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>wellBehavedWaitrequest</spirit:name>
- <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeLatency</spirit:name>
- <spirit:displayName>Write latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeWaitStates</spirit:name>
- <spirit:displayName>Write wait states</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeWaitTime</spirit:name>
- <spirit:displayName>Write wait</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <altera:altera_assignments>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_assignments>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>read</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_read_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>readdata</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_readdata_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_reset_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>system</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>clk</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>csi_system_clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>clockRate</spirit:name>
- <spirit:displayName>Clock rate</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>externallyDriven</spirit:name>
- <spirit:displayName>Externally driven</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ptfSchematicName</spirit:name>
- <spirit:displayName>PTF schematic name</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>system_reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>reset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>csi_system_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>synchronousEdges</spirit:name>
- <spirit:displayName>Synchronous edges</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>write</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_write_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>writedata</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_writedata_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- </spirit:busInterfaces>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>QUARTUS_SYNTH</spirit:name>
- <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
- <spirit:modelName>avs_common_mm</spirit:modelName>
- <spirit:fileSetRef>
- <spirit:localName>QUARTUS_SYNTH</spirit:localName>
- </spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>csi_system_clk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>csi_system_reset</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_address</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>10</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_write</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_writedata</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_read</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_readdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_reset_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_clk_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_address_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>10</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_write_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_writedata_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_read_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_readdata_export</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- </spirit:model>
- <spirit:vendorExtensions>
- <altera:entity_info>
- <spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buf_jesd</spirit:library>
- <spirit:name>avs_common_mm</spirit:name>
- <spirit:version>1.0</spirit:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>g_adr_w</spirit:name>
- <spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">11</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>g_dat_w</spirit:name>
- <spirit:displayName>g_dat_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
- <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>device</spirit:name>
- <spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceFamily</spirit:name>
- <spirit:displayName>Device family</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceSpeedGrade</spirit:name>
- <spirit:displayName>Device Speed Grade</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>generationId</spirit:name>
- <spirit:displayName>Generation Id</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bonusData</spirit:name>
- <spirit:displayName>bonusData</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
-{
-}
-</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>hideFromIPCatalog</spirit:name>
- <spirit:displayName>Hide from IP Catalog</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>lockedInterfaceDefinition</spirit:name>
- <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>11</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>11</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8192</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>systemInfos</spirit:name>
- <spirit:displayName>systemInfos</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x2000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>13</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition>]]></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.address" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.clk" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.mem" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.read" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.readdata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.reset" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.system" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.system_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.write" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.writedata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </spirit:vendorExtensions>
-</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buf_bsn.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buf_bsn.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
index bfde4f8c7d..55bee56584 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buf_bsn.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buf_bsn</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">65536</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">8388608</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>13</spirit:right>
+ <spirit:right>20</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>13</spirit:right>
+ <spirit:right>20</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buf_bsn</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">14</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">21</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>8388608</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x800000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>23</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1406,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip
index 6e9df14925..813749edd2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">16</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">32</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>1</spirit:right>
+ <spirit:right>2</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>1</spirit:right>
+ <spirit:right>2</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">2</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">3</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buf_jesd.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buf_jesd.ip
deleted file mode 100644
index 2ace3e3bfd..0000000000
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buf_jesd.ip
+++ /dev/null
@@ -1,1447 +0,0 @@
-<?xml version="1.0" ?>
-<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
- <spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buf_jesd</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>address</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_address_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>clk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_clk_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>mem</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>address</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_address</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>write</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_write</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>writedata</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_writedata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>read</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_read</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>readdata</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_readdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>addressAlignment</spirit:name>
- <spirit:displayName>Slave addressing</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressGroup</spirit:name>
- <spirit:displayName>Address group</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressSpan</spirit:name>
- <spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">16</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressUnits</spirit:name>
- <spirit:displayName>Address units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>alwaysBurstMaxBurst</spirit:name>
- <spirit:displayName>Always burst maximum burst</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>Associated reset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bitsPerSymbol</spirit:name>
- <spirit:displayName>Bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bridgedAddressOffset</spirit:name>
- <spirit:displayName>Bridged Address Offset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bridgesToMaster</spirit:name>
- <spirit:displayName>Bridges to master</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
- <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>burstcountUnits</spirit:name>
- <spirit:displayName>Burstcount units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>constantBurstBehavior</spirit:name>
- <spirit:displayName>Constant burst behavior</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>explicitAddressSpan</spirit:name>
- <spirit:displayName>Explicit address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>holdTime</spirit:name>
- <spirit:displayName>Hold</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>interleaveBursts</spirit:name>
- <spirit:displayName>Interleave bursts</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isBigEndian</spirit:name>
- <spirit:displayName>Big endian</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isFlash</spirit:name>
- <spirit:displayName>Flash memory</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isMemoryDevice</spirit:name>
- <spirit:displayName>Memory device</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isNonVolatileStorage</spirit:name>
- <spirit:displayName>Non-volatile storage</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>linewrapBursts</spirit:name>
- <spirit:displayName>Linewrap bursts</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maximumPendingReadTransactions</spirit:name>
- <spirit:displayName>Maximum pending read transactions</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maximumPendingWriteTransactions</spirit:name>
- <spirit:displayName>Maximum pending write transactions</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumReadLatency</spirit:name>
- <spirit:displayName>minimumReadLatency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumResponseLatency</spirit:name>
- <spirit:displayName>Minimum response latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumUninterruptedRunLength</spirit:name>
- <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>printableDevice</spirit:name>
- <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readLatency</spirit:name>
- <spirit:displayName>Read latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readWaitStates</spirit:name>
- <spirit:displayName>Read wait states</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readWaitTime</spirit:name>
- <spirit:displayName>Read wait</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>registerIncomingSignals</spirit:name>
- <spirit:displayName>Register incoming signals</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>registerOutgoingSignals</spirit:name>
- <spirit:displayName>Register outgoing signals</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>setupTime</spirit:name>
- <spirit:displayName>Setup</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>timingUnits</spirit:name>
- <spirit:displayName>Timing units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>transparentBridge</spirit:name>
- <spirit:displayName>Transparent bridge</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>waitrequestAllowance</spirit:name>
- <spirit:displayName>Waitrequest allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>wellBehavedWaitrequest</spirit:name>
- <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeLatency</spirit:name>
- <spirit:displayName>Write latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeWaitStates</spirit:name>
- <spirit:displayName>Write wait states</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeWaitTime</spirit:name>
- <spirit:displayName>Write wait</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <altera:altera_assignments>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_assignments>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>read</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_read_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>readdata</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_readdata_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_reset_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>system</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>clk</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>csi_system_clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>clockRate</spirit:name>
- <spirit:displayName>Clock rate</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>externallyDriven</spirit:name>
- <spirit:displayName>Externally driven</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ptfSchematicName</spirit:name>
- <spirit:displayName>PTF schematic name</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>system_reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>reset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>csi_system_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>synchronousEdges</spirit:name>
- <spirit:displayName>Synchronous edges</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>write</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_write_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>writedata</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_writedata_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- </spirit:busInterfaces>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>QUARTUS_SYNTH</spirit:name>
- <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
- <spirit:modelName>avs_common_mm</spirit:modelName>
- <spirit:fileSetRef>
- <spirit:localName>QUARTUS_SYNTH</spirit:localName>
- </spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>csi_system_clk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>csi_system_reset</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_address</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>1</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_write</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_writedata</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_read</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_readdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_reset_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_clk_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_address_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>1</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_write_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_writedata_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_read_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_readdata_export</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- </spirit:model>
- <spirit:vendorExtensions>
- <altera:entity_info>
- <spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buf_jesd</spirit:library>
- <spirit:name>avs_common_mm</spirit:name>
- <spirit:version>1.0</spirit:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>g_adr_w</spirit:name>
- <spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">2</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>g_dat_w</spirit:name>
- <spirit:displayName>g_dat_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
- <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>device</spirit:name>
- <spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceFamily</spirit:name>
- <spirit:displayName>Device family</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceSpeedGrade</spirit:name>
- <spirit:displayName>Device Speed Grade</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>generationId</spirit:name>
- <spirit:displayName>Generation Id</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bonusData</spirit:name>
- <spirit:displayName>bonusData</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
-{
-}
-</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>hideFromIPCatalog</spirit:name>
- <spirit:displayName>Hide from IP Catalog</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>lockedInterfaceDefinition</spirit:name>
- <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>2</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>2</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>16</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>systemInfos</spirit:name>
- <spirit:displayName>systemInfos</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>4</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition>]]></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.address" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.clk" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.mem" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.read" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.readdata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.reset" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.system" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.system_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.write" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.writedata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </spirit:vendorExtensions>
-</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buf_bsn.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
similarity index 98%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buf_bsn.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
index ea9a2661f5..7730cf438e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buf_bsn.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buf_bsn</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buf_bsn</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -1406,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
index 7c91133578..cd9a570b77 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
@@ -793,7 +793,7 @@
<spirit:parameter>
<spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
<spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">-1</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
</spirit:parameter>
</spirit:parameters>
</altera:altera_module_parameters>
@@ -1394,7 +1394,7 @@
<suppliedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
- <value>-1</value>
+ <value>100000000</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index bc239bff77..b545c1e43c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
-<system name="qsys_lofar2_unb2b_beamformer">
+<system name="qsys_lofar2_unb2b_sdp_station">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
@@ -22,7 +22,7 @@
{
datum baseAddress
{
- value = "745472";
+ value = "638976";
type = "String";
}
}
@@ -83,7 +83,7 @@
{
datum baseAddress
{
- value = "720896";
+ value = "622592";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "13664";
+ value = "13672";
type = "String";
}
}
@@ -132,6 +132,22 @@
type = "String";
}
}
+ element pio_jesd_ctrl
+ {
+ datum _sortIndex
+ {
+ value = "46";
+ type = "int";
+ }
+ }
+ element pio_jesd_ctrl.mem
+ {
+ datum baseAddress
+ {
+ value = "12296";
+ type = "String";
+ }
+ }
element pio_pps
{
datum _sortIndex
@@ -149,7 +165,7 @@
{
datum baseAddress
{
- value = "13656";
+ value = "13664";
type = "String";
}
}
@@ -190,27 +206,11 @@
type = "String";
}
}
- element ram_aduh_monitor
- {
- datum _sortIndex
- {
- value = "31";
- type = "int";
- }
- }
- element ram_aduh_monitor.mem
- {
- datum baseAddress
- {
- value = "688128";
- type = "String";
- }
- }
element ram_bf_weights
{
datum _sortIndex
{
- value = "41";
+ value = "36";
type = "int";
}
}
@@ -222,35 +222,19 @@
type = "String";
}
}
- element ram_diag_data_buf_bsn
- {
- datum _sortIndex
- {
- value = "29";
- type = "int";
- }
- }
- element ram_diag_data_buf_bsn.mem
- {
- datum baseAddress
- {
- value = "458752";
- type = "String";
- }
- }
- element ram_diag_data_buf_jesd
+ element ram_diag_data_buffer_bsn
{
datum _sortIndex
{
- value = "33";
+ value = "45";
type = "int";
}
}
- element ram_diag_data_buf_jesd.mem
+ element ram_diag_data_buffer_bsn.mem
{
datum baseAddress
{
- value = "737280";
+ value = "8388608";
type = "String";
}
}
@@ -258,7 +242,7 @@
{
datum _sortIndex
{
- value = "39";
+ value = "34";
type = "int";
}
}
@@ -266,7 +250,7 @@
{
datum baseAddress
{
- value = "655360";
+ value = "589824";
type = "String";
}
}
@@ -274,7 +258,7 @@
{
datum _sortIndex
{
- value = "36";
+ value = "31";
type = "int";
}
}
@@ -282,7 +266,7 @@
{
datum baseAddress
{
- value = "524288";
+ value = "458752";
type = "String";
}
}
@@ -290,7 +274,7 @@
{
datum _sortIndex
{
- value = "37";
+ value = "32";
type = "int";
}
}
@@ -306,7 +290,7 @@
{
datum _sortIndex
{
- value = "40";
+ value = "35";
type = "int";
}
}
@@ -322,7 +306,7 @@
{
datum _sortIndex
{
- value = "45";
+ value = "40";
type = "int";
}
}
@@ -338,7 +322,7 @@
{
datum _sortIndex
{
- value = "34";
+ value = "29";
type = "int";
}
}
@@ -346,7 +330,7 @@
{
datum baseAddress
{
- value = "589824";
+ value = "524288";
type = "String";
}
}
@@ -370,7 +354,7 @@
{
datum _sortIndex
{
- value = "30";
+ value = "28";
type = "int";
}
}
@@ -386,7 +370,7 @@
{
datum _sortIndex
{
- value = "42";
+ value = "37";
type = "int";
}
}
@@ -394,7 +378,7 @@
{
datum baseAddress
{
- value = "13552";
+ value = "13584";
type = "String";
}
}
@@ -426,7 +410,7 @@
{
datum baseAddress
{
- value = "13608";
+ value = "13616";
type = "String";
}
}
@@ -442,39 +426,23 @@
{
datum baseAddress
{
- value = "13568";
- type = "String";
- }
- }
- element reg_diag_data_buf_bsn
- {
- datum _sortIndex
- {
- value = "28";
- type = "int";
- }
- }
- element reg_diag_data_buf_bsn.mem
- {
- datum baseAddress
- {
- value = "12416";
+ value = "13440";
type = "String";
}
}
- element reg_diag_data_buf_jesd
+ element reg_diag_data_buffer_bsn
{
datum _sortIndex
{
- value = "32";
+ value = "44";
type = "int";
}
}
- element reg_diag_data_buf_jesd.mem
+ element reg_diag_data_buffer_bsn.mem
{
datum baseAddress
{
- value = "13584";
+ value = "128";
type = "String";
}
}
@@ -482,7 +450,7 @@
{
datum _sortIndex
{
- value = "38";
+ value = "33";
type = "int";
}
}
@@ -490,7 +458,7 @@
{
datum baseAddress
{
- value = "13600";
+ value = "13608";
type = "String";
}
}
@@ -506,7 +474,7 @@
{
datum baseAddress
{
- value = "128";
+ value = "12416";
type = "String";
}
}
@@ -514,7 +482,7 @@
{
datum _sortIndex
{
- value = "44";
+ value = "39";
type = "int";
}
}
@@ -522,7 +490,7 @@
{
datum baseAddress
{
- value = "13536";
+ value = "13568";
type = "String";
}
}
@@ -543,7 +511,7 @@
{
datum baseAddress
{
- value = "13648";
+ value = "13656";
type = "String";
}
}
@@ -564,7 +532,7 @@
{
datum baseAddress
{
- value = "13640";
+ value = "13648";
type = "String";
}
}
@@ -585,7 +553,7 @@
{
datum baseAddress
{
- value = "13472";
+ value = "13504";
type = "String";
}
}
@@ -601,7 +569,7 @@
{
datum baseAddress
{
- value = "13440";
+ value = "13472";
type = "String";
}
}
@@ -630,7 +598,7 @@
{
datum _sortIndex
{
- value = "43";
+ value = "38";
type = "int";
}
}
@@ -659,7 +627,7 @@
{
datum baseAddress
{
- value = "13632";
+ value = "13640";
type = "String";
}
}
@@ -680,7 +648,7 @@
{
datum baseAddress
{
- value = "13624";
+ value = "13632";
type = "String";
}
}
@@ -688,7 +656,7 @@
{
datum _sortIndex
{
- value = "47";
+ value = "42";
type = "int";
}
}
@@ -696,7 +664,7 @@
{
datum baseAddress
{
- value = "12296";
+ value = "13600";
type = "String";
}
}
@@ -704,7 +672,7 @@
{
datum _sortIndex
{
- value = "48";
+ value = "43";
type = "int";
}
}
@@ -733,7 +701,7 @@
{
datum baseAddress
{
- value = "13504";
+ value = "13536";
type = "String";
}
}
@@ -741,7 +709,7 @@
{
datum _sortIndex
{
- value = "46";
+ value = "41";
type = "int";
}
}
@@ -757,7 +725,7 @@
{
datum _sortIndex
{
- value = "35";
+ value = "30";
type = "int";
}
}
@@ -765,7 +733,7 @@
{
datum baseAddress
{
- value = "13616";
+ value = "13624";
type = "String";
}
}
@@ -1061,6 +1029,41 @@
internal="jesd204b.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="pio_jesd_ctrl_address"
+ internal="pio_jesd_ctrl.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_jesd_ctrl_clk"
+ internal="pio_jesd_ctrl.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_jesd_ctrl_read"
+ internal="pio_jesd_ctrl.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_jesd_ctrl_readdata"
+ internal="pio_jesd_ctrl.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_jesd_ctrl_reset"
+ internal="pio_jesd_ctrl.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_jesd_ctrl_write"
+ internal="pio_jesd_ctrl.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_jesd_ctrl_writedata"
+ internal="pio_jesd_ctrl.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="pio_pps_address"
internal="pio_pps.address"
@@ -1128,41 +1131,6 @@
internal="pio_wdi.external_connection"
type="conduit"
dir="end" />
- <interface
- name="ram_aduh_monitor_address"
- internal="ram_aduh_monitor.address"
- type="conduit"
- dir="end" />
- <interface
- name="ram_aduh_monitor_clk"
- internal="ram_aduh_monitor.clk"
- type="conduit"
- dir="end" />
- <interface
- name="ram_aduh_monitor_read"
- internal="ram_aduh_monitor.read"
- type="conduit"
- dir="end" />
- <interface
- name="ram_aduh_monitor_readdata"
- internal="ram_aduh_monitor.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="ram_aduh_monitor_reset"
- internal="ram_aduh_monitor.reset"
- type="conduit"
- dir="end" />
- <interface
- name="ram_aduh_monitor_write"
- internal="ram_aduh_monitor.write"
- type="conduit"
- dir="end" />
- <interface
- name="ram_aduh_monitor_writedata"
- internal="ram_aduh_monitor.writedata"
- type="conduit"
- dir="end" />
<interface
name="ram_bf_weights_address"
internal="ram_bf_weights.address"
@@ -1199,73 +1167,38 @@
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buf_bsn_address"
- internal="ram_diag_data_buf_bsn.address"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_data_buf_bsn_clk"
- internal="ram_diag_data_buf_bsn.clk"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_data_buf_bsn_read"
- internal="ram_diag_data_buf_bsn.read"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_data_buf_bsn_readdata"
- internal="ram_diag_data_buf_bsn.readdata"
+ name="ram_diag_data_buffer_bsn_address"
+ internal="ram_diag_data_buffer_bsn.address"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buf_bsn_reset"
- internal="ram_diag_data_buf_bsn.reset"
+ name="ram_diag_data_buffer_bsn_clk"
+ internal="ram_diag_data_buffer_bsn.clk"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buf_bsn_write"
- internal="ram_diag_data_buf_bsn.write"
+ name="ram_diag_data_buffer_bsn_read"
+ internal="ram_diag_data_buffer_bsn.read"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buf_bsn_writedata"
- internal="ram_diag_data_buf_bsn.writedata"
+ name="ram_diag_data_buffer_bsn_readdata"
+ internal="ram_diag_data_buffer_bsn.readdata"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buf_jesd_address"
- internal="ram_diag_data_buf_jesd.address"
+ name="ram_diag_data_buffer_bsn_reset"
+ internal="ram_diag_data_buffer_bsn.reset"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buf_jesd_clk"
- internal="ram_diag_data_buf_jesd.clk"
+ name="ram_diag_data_buffer_bsn_write"
+ internal="ram_diag_data_buffer_bsn.write"
type="conduit"
dir="end" />
<interface
- name="ram_diag_data_buf_jesd_read"
- internal="ram_diag_data_buf_jesd.read"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_data_buf_jesd_readdata"
- internal="ram_diag_data_buf_jesd.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_data_buf_jesd_reset"
- internal="ram_diag_data_buf_jesd.reset"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_data_buf_jesd_write"
- internal="ram_diag_data_buf_jesd.write"
- type="conduit"
- dir="end" />
- <interface
- name="ram_diag_data_buf_jesd_writedata"
- internal="ram_diag_data_buf_jesd.writedata"
+ name="ram_diag_data_buffer_bsn_writedata"
+ internal="ram_diag_data_buffer_bsn.writedata"
type="conduit"
dir="end" />
<interface
@@ -1673,73 +1606,38 @@
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buf_bsn_address"
- internal="reg_diag_data_buf_bsn.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_data_buf_bsn_clk"
- internal="reg_diag_data_buf_bsn.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_data_buf_bsn_read"
- internal="reg_diag_data_buf_bsn.read"
+ name="reg_diag_data_buffer_bsn_address"
+ internal="reg_diag_data_buffer_bsn.address"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buf_bsn_readdata"
- internal="reg_diag_data_buf_bsn.readdata"
+ name="reg_diag_data_buffer_bsn_clk"
+ internal="reg_diag_data_buffer_bsn.clk"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buf_bsn_reset"
- internal="reg_diag_data_buf_bsn.reset"
+ name="reg_diag_data_buffer_bsn_read"
+ internal="reg_diag_data_buffer_bsn.read"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buf_bsn_write"
- internal="reg_diag_data_buf_bsn.write"
+ name="reg_diag_data_buffer_bsn_readdata"
+ internal="reg_diag_data_buffer_bsn.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buf_bsn_writedata"
- internal="reg_diag_data_buf_bsn.writedata"
+ name="reg_diag_data_buffer_bsn_reset"
+ internal="reg_diag_data_buffer_bsn.reset"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buf_jesd_address"
- internal="reg_diag_data_buf_jesd.address"
+ name="reg_diag_data_buffer_bsn_write"
+ internal="reg_diag_data_buffer_bsn.write"
type="conduit"
dir="end" />
<interface
- name="reg_diag_data_buf_jesd_clk"
- internal="reg_diag_data_buf_jesd.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_data_buf_jesd_read"
- internal="reg_diag_data_buf_jesd.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_data_buf_jesd_readdata"
- internal="reg_diag_data_buf_jesd.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_data_buf_jesd_reset"
- internal="reg_diag_data_buf_jesd.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_data_buf_jesd_write"
- internal="reg_diag_data_buf_jesd.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_diag_data_buf_jesd_writedata"
- internal="reg_diag_data_buf_jesd.writedata"
+ name="reg_diag_data_buffer_bsn_writedata"
+ internal="reg_diag_data_buffer_bsn.writedata"
type="conduit"
dir="end" />
<interface
@@ -3943,30 +3841,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_avs_eth_0</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_avs_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_avs_eth_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_avs_eth_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_avs_eth_0</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_avs_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_avs_eth_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_avs_eth_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_avs_eth_0</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_avs_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_avs_eth_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_avs_eth_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_avs_eth_0</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_avs_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_eth_0.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -4179,30 +4077,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_clk_0</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_clk_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_clk_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_clk_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_clk_0</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_clk_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_clk_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_clk_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_clk_0</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_clk_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_clk_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_clk_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_clk_0</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_clk_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_clk_0.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -4305,12 +4203,20 @@
<isStart>true</isStart>
<ports>
<port>
- <name>d_address</name>
- <role>address</role>
+ <name>debug_mem_slave_debugaccess_to_roms</name>
+ <role>debugaccess</role>
<direction>Output</direction>
- <width>20</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>d_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
<name>d_byteenable</name>
@@ -4321,25 +4227,17 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>d_read</name>
- <role>read</role>
+ <name>d_address</name>
+ <role>address</role>
<direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>d_readdata</name>
- <role>readdata</role>
- <direction>Input</direction>
- <width>32</width>
+ <width>24</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>d_waitrequest</name>
- <role>waitrequest</role>
- <direction>Input</direction>
+ <name>d_read</name>
+ <role>read</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -4361,12 +4259,12 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>debug_mem_slave_debugaccess_to_roms</name>
- <role>debugaccess</role>
- <direction>Output</direction>
- <width>1</width>
+ <name>d_readdata</name>
+ <role>readdata</role>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -4530,6 +4428,14 @@
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
+ <port>
+ <name>debug_mem_slave_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
<port>
<name>debug_mem_slave_byteenable</name>
<role>byteenable</role>
@@ -4539,16 +4445,16 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>debug_mem_slave_debugaccess</name>
- <role>debugaccess</role>
- <direction>Input</direction>
+ <name>debug_mem_slave_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>debug_mem_slave_read</name>
- <role>read</role>
+ <name>debug_mem_slave_write</name>
+ <role>write</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -4563,16 +4469,8 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>debug_mem_slave_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_write</name>
- <role>write</role>
+ <name>debug_mem_slave_debugaccess</name>
+ <role>debugaccess</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -4825,6 +4723,14 @@
<type>avalon</type>
<isStart>true</isStart>
<ports>
+ <port>
+ <name>i_read</name>
+ <role>read</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
<port>
<name>i_address</name>
<role>address</role>
@@ -4834,9 +4740,9 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>i_read</name>
- <role>read</role>
- <direction>Output</direction>
+ <name>i_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -4849,14 +4755,6 @@
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
- <port>
- <name>i_waitrequest</name>
- <role>waitrequest</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
</ports>
<assignments>
<assignmentValueMap/>
@@ -5048,16 +4946,16 @@
<isStart>false</isStart>
<ports>
<port>
- <name>reset_n</name>
- <role>reset_n</role>
+ <name>reset_req</name>
+ <role>reset_req</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>reset_req</name>
- <role>reset_req</role>
+ <name>reset_n</name>
+ <role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -5397,11 +5295,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3440' end='0x3480' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_epcs.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_remu.mem' start='0x34C0' end='0x34E0' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x34E0' end='0x34F0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x34F0' end='0x3500' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x3500' end='0x3510' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x3510' end='0x3520' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3520' end='0x3528' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3528' end='0x3530' datawidth='32' /><slave name='reg_si.mem' start='0x3530' end='0x3538' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3538' end='0x3540' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3540' end='0x3548' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3548' end='0x3550' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3550' end='0x3558' datawidth='32' /><slave name='pio_pps.mem' start='0x3558' end='0x3560' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3560' end='0x3568' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_wg.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xA0000' end='0xA8000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0xA8000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0xB4000' end='0xB6000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0xB6000' end='0xB7000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3440' end='0x3480' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_epcs.mem' start='0x34C0' end='0x34E0' datawidth='32' /><slave name='reg_remu.mem' start='0x34E0' end='0x3500' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3500' end='0x3510' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x3510' end='0x3520' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x3520' end='0x3528' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3528' end='0x3530' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3530' end='0x3538' datawidth='32' /><slave name='reg_si.mem' start='0x3538' end='0x3540' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3540' end='0x3548' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3548' end='0x3550' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3550' end='0x3558' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3558' end='0x3560' datawidth='32' /><slave name='pio_pps.mem' start='0x3560' end='0x3568' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3568' end='0x3570' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_wg.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x90000' end='0x98000' datawidth='32' /><slave name='jesd204b.mem' start='0x98000' end='0x9C000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x9C000' end='0x9D000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>20</value>
+ <value>24</value>
</entry>
</consumedSystemInfos>
</value>
@@ -5461,30 +5359,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_cpu_0</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_cpu_0</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_cpu_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_cpu_0</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_cpu_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_cpu_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_cpu_0</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_cpu_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_cpu_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_cpu_0</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_cpu_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_cpu_0.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
@@ -5521,7 +5419,7 @@
</entry>
<entry>
<key>embeddedsw.CMacro.DATA_ADDR_WIDTH</key>
- <value>20</value>
+ <value>24</value>
</entry>
<entry>
<key>embeddedsw.CMacro.DCACHE_LINE_SIZE</key>
@@ -6278,30 +6176,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_jesd204b</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_jesd204b</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_jesd204b</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_jesd204b</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_jesd204b</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_jesd204b</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_jesd204b</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_jesd204b</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_jesd204b</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_jesd204b</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_jesd204b</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jesd204b.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -6834,30 +6732,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_jtag_uart_0</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_jtag_uart_0</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_jtag_uart_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_jtag_uart_0</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_jtag_uart_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_jtag_uart_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_jtag_uart_0</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_jtag_uart_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_jtag_uart_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_jtag_uart_0</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_jtag_uart_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jtag_uart_0.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
@@ -7281,30 +7179,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_onchip_memory2_0</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_onchip_memory2_0</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_onchip_memory2_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_onchip_memory2_0</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_onchip_memory2_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_onchip_memory2_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_onchip_memory2_0</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_onchip_memory2_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_onchip_memory2_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_onchip_memory2_0</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_onchip_memory2_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_onchip_memory2_0.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
@@ -7408,7 +7306,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="pio_pps"
+ name="pio_jesd_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -7994,37 +7892,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_pio_pps</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_pio_pps</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_pio_pps</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_pio_pps</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_pps.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="pio_system_info"
+ name="pio_pps"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -8040,7 +7938,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -8104,7 +8002,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -8173,7 +8071,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -8579,11 +8477,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -8610,52 +8508,84 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_pio_system_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_pio_pps</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_pio_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_pps</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_pio_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_pps</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_pio_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_pps</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_system_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="pio_wdi"
+ name="pio_system_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
<parameter name="componentDefinition"><![CDATA[<componentDefinition>
<boundary>
<interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>clk</name>
- <type>clock</type>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -8667,26 +8597,610 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
- <key>externallyDriven</key>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>128</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>external_connection</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>out_port</name>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>7</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_pio_system_info</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_system_info</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_system_info</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_system_info</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="pio_wdi"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>external_connection</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>out_port</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -9161,30 +9675,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_pio_wdi</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_pio_wdi</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_pio_wdi</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_wdi</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_pio_wdi</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_wdi</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_pio_wdi</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_wdi</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_wdi.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
@@ -9268,7 +9782,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_aduh_monitor"
+ name="ram_bf_weights"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -9284,7 +9798,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -9348,7 +9862,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -9417,7 +9931,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -9823,1859 +10337,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>15</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_ram_aduh_monitor</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_aduh_monitor</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_aduh_monitor</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_aduh_monitor</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_aduh_monitor.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="ram_bf_weights"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>15</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>15</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>131072</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>17</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_ram_bf_weights</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_bf_weights</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_bf_weights</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_bf_weights</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_bf_weights</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_bf_weights</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_bf_weights</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_bf_weights.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="ram_diag_data_buf_bsn"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>14</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>14</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>65536</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>16</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="ram_diag_data_buf_jesd"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>11</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
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- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>11</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8192</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x2000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>13</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -11702,37 +10368,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_bf_weights</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_bf_weights</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_bf_weights</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_equalizer_gains"
+ name="ram_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -11748,7 +10414,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -11812,7 +10478,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -11881,7 +10547,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8388608</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -12287,11 +10953,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x800000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>23</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -12318,37 +10984,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_ram_equalizer_gains</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_equalizer_gains.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_fil_coefs"
+ name="ram_equalizer_gains"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -12364,7 +11030,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12428,7 +11094,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12497,7 +11163,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -12903,11 +11569,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -12934,37 +11600,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_ram_fil_coefs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_fil_coefs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_scrap"
+ name="ram_fil_coefs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -12980,7 +11646,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>9</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13044,7 +11710,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>9</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13113,7 +11779,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>2048</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -13334,292 +12000,292 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>11</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_ram_scrap</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_scrap</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_scrap</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_scrap</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_scrap.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="ram_ss_ss_wide"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>14</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="ram_scrap"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
<name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
@@ -13660,7 +12326,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13729,7 +12395,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>2048</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -14135,11 +12801,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>11</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -14166,37 +12832,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_scrap</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_bst"
+ name="ram_ss_ss_wide"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14212,7 +12878,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>12</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14276,7 +12942,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>12</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14345,7 +13011,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16384</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -14751,11 +13417,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>14</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -14782,37 +13448,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_ram_st_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_sst"
+ name="ram_st_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14828,7 +13494,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14892,7 +13558,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14961,7 +13627,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>16384</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15367,11 +14033,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>14</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15398,37 +14064,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_ram_st_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_wg"
+ name="ram_st_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16014,37 +14680,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_ram_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_aduh_monitor"
+ name="ram_wg"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16060,7 +14726,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16124,7 +14790,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16193,7 +14859,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -16599,11 +15265,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -16630,37 +15296,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_aduh_monitor</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bf_scale"
+ name="reg_aduh_monitor"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16676,7 +15342,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16740,7 +15406,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16809,7 +15475,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17215,11 +15881,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17246,37 +15912,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_bf_scale</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bf_scale.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_input"
+ name="reg_bf_scale"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17292,7 +15958,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17356,7 +16022,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17425,7 +16091,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17831,11 +16497,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17862,37 +16528,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_bsn_monitor_input"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17908,7 +16574,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17972,7 +16638,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18041,7 +16707,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18447,11 +17113,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18478,37 +17144,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_source"
+ name="reg_bsn_scheduler"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18524,7 +17190,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18588,7 +17254,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18657,7 +17323,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -19063,11 +17729,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19094,37 +17760,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_bsn_source</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_source.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buf_bsn"
+ name="reg_bsn_source"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19140,7 +17806,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19204,7 +17870,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19273,7 +17939,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -19679,11 +18345,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19710,37 +18376,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buf_jesd"
+ name="reg_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19756,7 +18422,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19820,7 +18486,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19889,7 +18555,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20295,11 +18961,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20326,30 +18992,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -20942,30 +19608,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_dp_selector</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dp_selector</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dp_selector</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dp_selector</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_selector.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -21558,30 +20224,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_dp_shiftram</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dp_shiftram</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dp_shiftram</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dp_shiftram</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_shiftram.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -22174,30 +20840,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_dp_xonoff</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dp_xonoff</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dp_xonoff</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dp_xonoff</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_xonoff.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -22790,30 +21456,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -23406,30 +22072,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dpmm_data</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dpmm_data</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_dpmm_data</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -24022,30 +22688,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_epcs</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_epcs</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_epcs</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_epcs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -24638,30 +23304,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -25254,30 +23920,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -25870,30 +24536,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_hdr_dat</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_hdr_dat</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_hdr_dat</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_hdr_dat</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_hdr_dat.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -26486,30 +25152,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -27102,30 +25768,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_mmdp_data</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_mmdp_data</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_mmdp_data</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -27718,30 +26384,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -28279,12 +26945,20 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>avs_common_mm_0</className>
+ <className>avs_common_mm</className>
<version>1.0</version>
- <displayName>avs_common_mm_0</displayName>
+ <displayName>avs_common_mm</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
- <descriptors/>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
@@ -28317,7 +26991,7 @@
<consumedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
- <value>-1</value>
+ <value>100000000</value>
</entry>
</consumedSystemInfos>
</value>
@@ -28326,30 +27000,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -28942,30 +27616,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_remu</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_remu</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_remu</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_remu.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -29558,30 +28232,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_sdp_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_sdp_info</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_sdp_info</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_sdp_info</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_sdp_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -30174,30 +28848,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_si</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_si</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_si</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_si</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_si.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -30790,30 +29464,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_unb_pmbus</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_unb_pmbus</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_unb_pmbus</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_unb_pmbus</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_pmbus.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -31406,30 +30080,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_unb_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_unb_sens</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_unb_sens</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_unb_sens</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -32022,30 +30696,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_wdi</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wdi</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_wdi</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_wdi</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_wdi</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wdi.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -32638,30 +31312,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_reg_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wg</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_wg</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_wg</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_beamformer_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_reg_wg</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -33254,30 +31928,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_rom_system_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_rom_system_info</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_rom_system_info</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_rom_system_info</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_rom_system_info</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_rom_system_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -33925,30 +32599,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_beamformer_timer_0</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_timer_0</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_timer_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_timer_0</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_timer_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_timer_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_timer_0</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_timer_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>qsys_lofar2_unb2b_filterbank_timer_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_beamformer_timer_0</fileSetFixedName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_timer_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_timer_0.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
@@ -34012,7 +32686,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x3560" />
+ <parameter name="baseAddress" value="0x3568" />
</connection>
<connection
kind="avalon"
@@ -34047,7 +32721,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x3558" />
+ <parameter name="baseAddress" value="0x3560" />
</connection>
<connection
kind="avalon"
@@ -34061,49 +32735,49 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x34c0" />
+ <parameter name="baseAddress" value="0x34e0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x34a0" />
+ <parameter name="baseAddress" value="0x34c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x3550" />
+ <parameter name="baseAddress" value="0x3558" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x3548" />
+ <parameter name="baseAddress" value="0x3550" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x3540" />
+ <parameter name="baseAddress" value="0x3548" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x3538" />
+ <parameter name="baseAddress" value="0x3540" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x3480" />
+ <parameter name="baseAddress" value="0x34a0" />
</connection>
<connection
kind="avalon"
@@ -34124,21 +32798,21 @@
version="18.0"
start="cpu_0.data_master"
end="ram_st_sst.mem">
- <parameter name="baseAddress" value="0x00090000" />
+ <parameter name="baseAddress" value="0x00080000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x3530" />
+ <parameter name="baseAddress" value="0x3538" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_fil_coefs.mem">
- <parameter name="baseAddress" value="0x00080000" />
+ <parameter name="baseAddress" value="0x00070000" />
</connection>
<connection
kind="avalon"
@@ -34147,27 +32821,6 @@
end="ram_scrap.mem">
<parameter name="baseAddress" value="0x0800" />
</connection>
- <connection
- kind="avalon"
- version="18.0"
- start="cpu_0.data_master"
- end="ram_diag_data_buf_jesd.mem">
- <parameter name="baseAddress" value="0x000b4000" />
- </connection>
- <connection
- kind="avalon"
- version="18.0"
- start="cpu_0.data_master"
- end="reg_diag_data_buf_jesd.mem">
- <parameter name="baseAddress" value="0x3510" />
- </connection>
- <connection
- kind="avalon"
- version="18.0"
- start="cpu_0.data_master"
- end="ram_aduh_monitor.mem">
- <parameter name="baseAddress" value="0x000a8000" />
- </connection>
<connection
kind="avalon"
version="18.0"
@@ -34175,20 +32828,6 @@
end="reg_aduh_monitor.mem">
<parameter name="baseAddress" value="0x3100" />
</connection>
- <connection
- kind="avalon"
- version="18.0"
- start="cpu_0.data_master"
- end="ram_diag_data_buf_bsn.mem">
- <parameter name="baseAddress" value="0x00070000" />
- </connection>
- <connection
- kind="avalon"
- version="18.0"
- start="cpu_0.data_master"
- end="reg_diag_data_buf_bsn.mem">
- <parameter name="baseAddress" value="0x3080" />
- </connection>
<connection
kind="avalon"
version="18.0"
@@ -34201,21 +32840,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_shiftram.mem">
- <parameter name="baseAddress" value="0x0080" />
+ <parameter name="baseAddress" value="0x3080" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x3528" />
+ <parameter name="baseAddress" value="0x3530" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_source.mem">
- <parameter name="baseAddress" value="0x3500" />
+ <parameter name="baseAddress" value="0x3480" />
</connection>
<connection
kind="avalon"
@@ -34236,21 +32875,21 @@
version="18.0"
start="cpu_0.data_master"
end="jesd204b.mem">
- <parameter name="baseAddress" value="0x000b0000" />
+ <parameter name="baseAddress" value="0x00098000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x3520" />
+ <parameter name="baseAddress" value="0x3528" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_equalizer_gains.mem">
- <parameter name="baseAddress" value="0x000a0000" />
+ <parameter name="baseAddress" value="0x00090000" />
</connection>
<connection
kind="avalon"
@@ -34271,7 +32910,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bf_scale.mem">
- <parameter name="baseAddress" value="0x34f0" />
+ <parameter name="baseAddress" value="0x3510" />
</connection>
<connection
kind="avalon"
@@ -34285,7 +32924,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
- <parameter name="baseAddress" value="0x34e0" />
+ <parameter name="baseAddress" value="0x3500" />
</connection>
<connection
kind="avalon"
@@ -34306,7 +32945,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x3008" />
+ <parameter name="baseAddress" value="0x3520" />
</connection>
<connection
kind="avalon"
@@ -34315,12 +32954,33 @@
end="reg_nw_10gbe_mac.mem">
<parameter name="baseAddress" value="0x8000" />
</connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_diag_data_buffer_bsn.mem">
+ <parameter name="baseAddress" value="0x0080" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="ram_diag_data_buffer_bsn.mem">
+ <parameter name="baseAddress" value="0x00800000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="pio_jesd_ctrl.mem">
+ <parameter name="baseAddress" value="0x3008" />
+ </connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="avs_eth_0.mms_ram">
- <parameter name="baseAddress" value="0x000b6000" />
+ <parameter name="baseAddress" value="0x0009c000" />
</connection>
<connection
kind="avalon"
@@ -34443,36 +33103,11 @@
start="clk_0.clk"
end="ram_fil_coefs.system" />
<connection kind="clock" version="18.0" start="clk_0.clk" end="ram_scrap.system" />
- <connection
- kind="clock"
- version="18.0"
- start="clk_0.clk"
- end="ram_diag_data_buf_jesd.system" />
- <connection
- kind="clock"
- version="18.0"
- start="clk_0.clk"
- end="reg_diag_data_buf_jesd.system" />
- <connection
- kind="clock"
- version="18.0"
- start="clk_0.clk"
- end="ram_aduh_monitor.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
end="reg_aduh_monitor.system" />
- <connection
- kind="clock"
- version="18.0"
- start="clk_0.clk"
- end="ram_diag_data_buf_bsn.system" />
- <connection
- kind="clock"
- version="18.0"
- start="clk_0.clk"
- end="reg_diag_data_buf_bsn.system" />
<connection kind="clock" version="18.0" start="clk_0.clk" end="ram_wg.system" />
<connection
kind="clock"
@@ -34547,6 +33182,21 @@
version="18.0"
start="clk_0.clk"
end="reg_nw_10gbe_mac.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_diag_data_buffer_bsn.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="ram_diag_data_buffer_bsn.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="pio_jesd_ctrl.system" />
<connection
kind="interrupt"
version="18.0"
@@ -34678,36 +33328,11 @@
version="18.0"
start="clk_0.clk_reset"
end="ram_scrap.system_reset" />
- <connection
- kind="reset"
- version="18.0"
- start="clk_0.clk_reset"
- end="ram_diag_data_buf_jesd.system_reset" />
- <connection
- kind="reset"
- version="18.0"
- start="clk_0.clk_reset"
- end="reg_diag_data_buf_jesd.system_reset" />
- <connection
- kind="reset"
- version="18.0"
- start="clk_0.clk_reset"
- end="ram_aduh_monitor.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
end="reg_aduh_monitor.system_reset" />
- <connection
- kind="reset"
- version="18.0"
- start="clk_0.clk_reset"
- end="ram_diag_data_buf_bsn.system_reset" />
- <connection
- kind="reset"
- version="18.0"
- start="clk_0.clk_reset"
- end="reg_diag_data_buf_bsn.system_reset" />
<connection
kind="reset"
version="18.0"
@@ -34798,6 +33423,21 @@
version="18.0"
start="clk_0.clk_reset"
end="reg_nw_10gbe_mac.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_diag_data_buffer_bsn.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="ram_diag_data_buffer_bsn.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="pio_jesd_ctrl.system_reset" />
<connection
kind="reset"
version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_beamformer_one_node/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_beamformer_one_node/hdllib.cfg
deleted file mode 100644
index 2a794ca3f2..0000000000
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_beamformer_one_node/hdllib.cfg
+++ /dev/null
@@ -1,98 +0,0 @@
-hdl_lib_name = lofar2_unb2b_beamformer_one_node
-hdl_library_clause_name = lofar2_unb2b_beamformer_one_node_lib
-hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_beamformer
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
-
- synth_files =
- lofar2_unb2b_beamformer_one_node.vhd
-
-test_bench_files =
-
-regression_test_vhdl =
-
-
-[modelsim_project_file]
-modelsim_copy_files =
-
-
-[quartus_project_file]
-synth_top_level_entity =
-
-quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
- ../../quartus .
- ../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
-
-quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
-
-# use lofar2_unb2b_beamformer.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
-quartus_sdc_files =
- ../../quartus/lofar2_unb2b_beamformer.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
-
-quartus_tcl_files =
- ../../quartus/lofar2_unb2b_beamformer_pins.tcl
-
-quartus_vhdl_files =
-
-quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer_one_node/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer.qip
-
-quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_xonoff.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_timer_0.ip
-
-
-nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
new file mode 100644
index 0000000000..0fec6f1d88
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
@@ -0,0 +1,93 @@
+hdl_lib_name = lofar2_unb2b_sdp_station_adc
+hdl_library_clause_name = lofar2_unb2b_sdp_station_adc_lib
+hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+ synth_files =
+ lofar2_unb2b_sdp_station_adc.vhd
+
+test_bench_files =
+ tb_lofar2_unb2b_sdp_station_adc.vhd
+
+regression_test_vhdl =
+ tb_lofar2_unb2b_sdp_station_adc.vhd
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/data data
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus .
+ ../../src/data data
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_files =
+ ../../quartus/lofar2_unb2b_sdp_station.sdc
+
+quartus_tcl_files =
+ ../../quartus/lofar2_unb2b_sdp_station_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_adc/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
new file mode 100644
index 0000000000..9d15869925
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
@@ -0,0 +1,163 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : J Hargreaves, R vd Walle
+-- Purpose:
+-- Wrapper for Lofar2 SDP Station adc design
+-- Description:
+-- Unb2b version for lab testing
+-- Contains complete AIT input stage with 12 ADC streams
+
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY lofar2_unb2b_sdp_station_adc IS
+ GENERIC (
+ g_design_name : STRING := "lofar2_unb2b_sdp_station_adc";
+ g_design_note : STRING := "Lofar2 SDP station adc design";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- back transceivers (note only 6 are used in unb2b)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b);
+ BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
+
+ -- jesd204b syncronization signals (2 syncs)
+ JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
+ );
+END lofar2_unb2b_sdp_station_adc;
+
+ARCHITECTURE str OF lofar2_unb2b_sdp_station_adc IS
+
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC;
+
+
+BEGIN
+
+ -- Mapping between JESD signal names and UNB2B pin/schematic names
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
+ JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
+ JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
+ JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
+ JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
+ JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
+ JESD204B_SERIAL_DATA(6) <= '0';
+ JESD204B_SERIAL_DATA(7) <= '0';
+ JESD204B_SERIAL_DATA(8) <= '0';
+ JESD204B_SERIAL_DATA(9) <= '0';
+ JESD204B_SERIAL_DATA(10) <= '0';
+ JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+
+
+ u_revision : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
new file mode 100644
index 0000000000..7f0682d13b
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
@@ -0,0 +1,301 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_sdp_station_adc using WG data.
+--
+-- Description:
+-- MM control actions:
+--
+-- 1) Enable calc mode for WG via reg_diag_wg with:
+-- freq = 19.921875MHz
+-- ampl = 0.5 * 2**13
+--
+-- 2) Read current BSN from reg_bsn_scheduler_wg and write reg_bsn_scheduler_wg
+-- to trigger start of WG at BSN.
+--
+-- 3) Read ADUH monitor power sum for via reg_aduh_mon and verify with
+-- c_exp_wg_power_sp_0.
+-- View sp_power_sum in Wave window
+--
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- > run -a
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_sdp_station_adc IS
+END tb_lofar2_unb2b_sdp_station_adc;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_adc IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+ CONSTANT c_pps_period : NATURAL := 1000;
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+
+ CONSTANT c_nof_block_per_sync : NATURAL := 16;
+
+ CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
+ CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
+ CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
+
+ -- WG
+ CONSTANT c_full_scale_ampl : REAL := REAL(2**(14-1)-1); -- = full scale of WG
+ CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/2; -- in number of lsb
+ CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+ CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
+ CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
+ CONSTANT c_exp_wg_power_sp_0 : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_sdp_N_fft*c_nof_block_per_sync);
+
+ -- ADUH
+ CONSTANT c_mon_buffer_nof_samples : NATURAL := 512; --samples per stream
+
+ -- MM
+ CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
+ CONSTANT c_mm_file_reg_bsn_source : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE";
+ CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+ CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+ CONSTANT c_mm_file_reg_aduh_mon : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_ADUH_MONITOR";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+
+ -- WG
+ SIGNAL dbg_c_exp_wg_power_sp_0 : REAL := c_exp_wg_power_sp_0;
+ SIGNAL sp_samples : t_integer_arr(0 TO c_mon_buffer_nof_samples-1) := (OTHERS=>0);
+ SIGNAL sp_sample : INTEGER := 0;
+ SIGNAL sp_power_sum : STD_LOGIC_VECTOR(63 DOWNTO 0);
+ SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ -- back transceivers
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
+
+ -- jesd204b syncronization signals
+ SIGNAL jesd204b_sysref : STD_LOGIC;
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
+ jesd204b_sysref <= pps;
+ ext_pps <= pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_lofar_unb2b_sdp_station_adc : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2b_sdp_station_adc",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_scope_selected_subband => NATURAL(c_subband_sp_0)
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
+
+ ------------------------------------------------------------------------------
+ -- MM slave accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ VARIABLE v_bsn : NATURAL;
+ VARIABLE v_sp_power_sum_0 : REAL;
+ VARIABLE v_sp_subband_power : REAL;
+ VARIABLE v_W, v_T, v_U, v_S, v_B : NATURAL; -- array indicies
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+
+ ----------------------------------------------------------------------------
+ -- Enable BS
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 0, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+
+ ----------------------------------------------------------------------------
+ -- Enable WG
+ ----------------------------------------------------------------------------
+ -- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3)
+ -- nof_samples[31:16] --> <= c_ram_wg_size=1024
+ -- 1 : phase[15:0]
+ -- 2 : freq[30:0]
+ -- 3 : ampl[16:0]
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER((c_subband_sp_0+c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, INTEGER(REAL(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl
+
+ -- Read current BSN
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ -- Write scheduler BSN to trigger start of WG at next block
+ v_bsn := TO_UINT(current_bsn_wg) + 2;
+ ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
+ v_bsn := c_bsn_start_wg;
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+
+ -- Wait for enough WG data and start of sync interval
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync*3, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
+
+ ---------------------------------------------------------------------------
+ -- Read ADUH monitor power sum
+ ---------------------------------------------------------------------------
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk); -- read low part
+ sp_power_sum(31 DOWNTO 0) <= rd_data;
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk); -- read high part
+ sp_power_sum(63 DOWNTO 32) <= rd_data;
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ ---------------------------------------------------------------------------
+ -- Verify sp_power_sum
+ ---------------------------------------------------------------------------
+ -- Convert STD_LOGIC_VECTOR sp_power_sum to REAL
+ v_sp_power_sum_0 := REAL(REAL(TO_UINT(sp_power_sum(61 DOWNTO 30)))*REAL(2**30) + REAL(TO_UINT(sp_power_sum(29 DOWNTO 0))));
+
+ ASSERT v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0 REPORT "Wrong SP power for SP 0" SEVERITY ERROR;
+ ASSERT v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0 REPORT "Wrong SP power for SP 0" SEVERITY ERROR;
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+ WAIT;
+ END PROCESS;
+
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
new file mode 100644
index 0000000000..8b78dac6c7
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
@@ -0,0 +1,99 @@
+hdl_lib_name = lofar2_unb2b_sdp_station_bf
+hdl_library_clause_name = lofar2_unb2b_sdp_station_bf_lib
+hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+ synth_files =
+ lofar2_unb2b_sdp_station_bf.vhd
+
+test_bench_files =
+ tb_lofar2_unb2b_sdp_station_bf.vhd
+
+regression_test_vhdl =
+ tb_lofar2_unb2b_sdp_station_bf.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ # Overwrite bf weights with sim data
+ ../../tb/data data
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ ../../quartus .
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
+quartus_sdc_files =
+ ../../quartus/lofar2_unb2b_sdp_station.sdc
+ #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+ ../../quartus/lofar2_unb2b_sdp_station_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_bf/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
similarity index 89%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
index f81831264c..47649378aa 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright 2020
+-- Copyright 2021
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
@@ -20,13 +20,13 @@
-- Author : R. van der Walle
-- Purpose:
--- Wrapper for one node beamformer test design
+-- Wrapper for Lofar2 SDP Station beamformer design
-- Description:
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -36,10 +36,10 @@ USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-ENTITY lofar2_unb2b_beamformer_one_node IS
+ENTITY lofar2_unb2b_sdp_station_bf IS
GENERIC (
- g_design_name : STRING := "lofar2_unb2b_beamformer_one_node";
- g_design_note : STRING := "Lofar2 beamformer one node design with all streams";
+ g_design_name : STRING := "lofar2_unb2b_sdp_station_bf";
+ g_design_note : STRING := "Lofar2 SDP station beamformer design";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
@@ -91,9 +91,9 @@ ENTITY lofar2_unb2b_beamformer_one_node IS
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
);
-END lofar2_unb2b_beamformer_one_node;
+END lofar2_unb2b_sdp_station_bf;
-ARCHITECTURE str OF lofar2_unb2b_beamformer_one_node IS
+ARCHITECTURE str OF lofar2_unb2b_sdp_station_bf IS
SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
@@ -119,7 +119,7 @@ BEGIN
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
- u_revision : ENTITY lofar2_unb2b_beamformer_lib.lofar2_unb2b_beamformer
+ u_revision : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
GENERIC MAP (
g_design_name => g_design_name,
g_design_note => g_design_note,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
similarity index 95%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
index 35219e5e29..212ea5a0ce 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
--
-- Author: R. van der Walle
--- Purpose: Self-checking testbench for simulating lofar2_unb2b_sdp_station using WG data.
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_sdp_station_bf using WG data.
--
-- Description:
-- MM control actions:
@@ -48,7 +48,7 @@
-- > run -a
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, lofar2_unb2b_sdp_station_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.MATH_REAL.ALL;
@@ -64,10 +64,10 @@ USE wpfb_lib.wpfb_pkg.ALL;
USE lofar2_sdp_lib.sdp_pkg.ALL;
USE tech_pll_lib.tech_pll_component_pkg.ALL;
-ENTITY tb_lofar2_unb2b_sdp_station IS
-END tb_lofar2_unb2b_sdp_station;
+ENTITY tb_lofar2_unb2b_sdp_station_bf IS
+END tb_lofar2_unb2b_sdp_station_bf;
-ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station IS
+ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_bf IS
CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
@@ -83,7 +83,6 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station IS
CONSTANT c_pps_period : NATURAL := 1000;
CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
- CONSTANT c_cable_delay : TIME := 12 ns;
CONSTANT c_nof_block_per_sync : NATURAL := 16;
CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
@@ -111,17 +110,11 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station IS
TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL;
TyPE t_slv_64_subbands_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_S_sub_bf);
- -- ADUH
- CONSTANT c_mon_buffer_nof_samples : NATURAL := 512; --samples per stream
- CONSTANT c_mon_buffer_nof_words : NATURAL := c_mon_buffer_nof_samples;
-
-- MM
CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
CONSTANT c_mm_file_reg_bsn_source : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE";
CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
- CONSTANT c_mm_file_reg_aduh_mon : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_ADUH_MONITOR";
- CONSTANT c_mm_file_ram_aduh_mon : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ADUH_MONITOR";
CONSTANT c_mm_file_ram_st_bst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_BST";
CONSTANT c_mm_file_reg_dp_xonoff : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF";
CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
@@ -133,10 +126,6 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station IS
SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
-- WG
- SIGNAL dbg_c_exp_wg_power_sp_0 : REAL := c_exp_wg_power_sp_0;
- SIGNAL sp_samples : t_integer_arr(0 TO c_mon_buffer_nof_samples-1) := (OTHERS=>0);
- SIGNAL sp_sample : INTEGER := 0;
- SIGNAL sp_power_sum : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
-- WPFB
@@ -222,9 +211,9 @@ BEGIN
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
- u_lofar_unb2b_beamformer : ENTITY work.lofar2_unb2b_sdp_station
+ u_lofar_unb2b_sdp_station_bf : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
GENERIC MAP (
- g_design_name => "lofar2_unb2b_sdp_station_full",
+ g_design_name => "lofar2_unb2b_sdp_station_bf",
g_design_note => "",
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
@@ -322,7 +311,6 @@ BEGIN
p_mm_stimuli : PROCESS
VARIABLE v_bsn : NATURAL;
- VARIABLE v_sp_power_sum_0 : REAL;
VARIABLE v_sp_beamlet_power : REAL;
VARIABLE v_sp_subband_power : REAL;
VARIABLE v_W, v_T, v_U, v_S, v_B : NATURAL; -- array indicies
@@ -519,12 +507,12 @@ BEGIN
IF sp_beamlet_power_sum_0>0.0 THEN ASSERT sp_beamlet_power_0 < c_hi_factor * c_exp_beamlet_power_sp_0 REPORT "Wrong beamlet power for SP 0" SEVERITY ERROR; END IF;
-- view c_exp_sp_beamlet_power_ratio in Wave window
- IF sp_beamlet_power_sum_0>0.0 THEN sp_beamlet_power_ratio_0 <= sp_beamlet_power_0/v_sp_power_sum_0; END IF;
+ IF sp_beamlet_power_sum_0>0.0 THEN sp_beamlet_power_ratio_0 <= sp_beamlet_power_0/sp_beamlet_power_sum_0; END IF;
-- view c_exp_sp_beamlet_power_sum_ratio in Wave window
-- The sp_beamlet_power_sum_ratio show similar information as sp_beamlet_power_leakage_sum, because when
-- sp_beamlet_power_leakage_sum is small then sp_beamlet_power_sum_ratio ~= sp_beamlet_power_ratio.
- IF sp_beamlet_power_sum_0>0.0 THEN sp_beamlet_power_sum_ratio_0 <= sp_beamlet_power_sum_0/v_sp_power_sum_0; END IF;
+ IF sp_beamlet_power_sum_0>0.0 THEN sp_beamlet_power_sum_ratio_0 <= sp_beamlet_power_sum_0/sp_beamlet_power_0; END IF;
-- View sp_beamlet_power_leakage_sum in Wave window
IF sp_beamlet_power_sum_0>0.0 THEN sp_beamlet_power_leakage_sum_0 <= sp_beamlet_power_sum_0 - sp_beamlet_power_0; END IF;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
new file mode 100644
index 0000000000..8cd4f41a0d
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
@@ -0,0 +1,98 @@
+hdl_lib_name = lofar2_unb2b_sdp_station_fsub
+hdl_library_clause_name = lofar2_unb2b_sdp_station_fsub_lib
+hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+ synth_files =
+ lofar2_unb2b_sdp_station_fsub.vhd
+
+test_bench_files =
+ tb_lofar2_unb2b_sdp_station_fsub.vhd
+
+regression_test_vhdl =
+ tb_lofar2_unb2b_sdp_station_fsub.vhd
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ ../../quartus .
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
+quartus_sdc_files =
+ ../../quartus/lofar2_unb2b_sdp_station.sdc
+ #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+ ../../quartus/lofar2_unb2b_sdp_station_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_fsub/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
new file mode 100644
index 0000000000..400fe27233
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
@@ -0,0 +1,162 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : R. van der Walle
+-- Purpose:
+-- Wrapper for Lofar2 SDP Station filterbank design
+-- Description:
+-- Unb2b version for lab testing
+-- Contains complete AIT input stage with 12 ADC streams and FSUB
+
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY lofar2_unb2b_sdp_station_fsub IS
+ GENERIC (
+ g_design_name : STRING := "lofar2_unb2b_sdp_station_fsub";
+ g_design_note : STRING := "Lofar2 SDP station filterbank design";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- back transceivers (note only 6 are used in unb2b)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b);
+ BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
+
+ -- jesd204b syncronization signals (2 syncs)
+ JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
+ );
+END lofar2_unb2b_sdp_station_fsub;
+
+ARCHITECTURE str OF lofar2_unb2b_sdp_station_fsub IS
+
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC;
+
+BEGIN
+
+ -- Mapping between JESD signal names and UNB2B pin/schematic names
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
+ JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
+ JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
+ JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
+ JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
+ JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
+ JESD204B_SERIAL_DATA(6) <= '0';
+ JESD204B_SERIAL_DATA(7) <= '0';
+ JESD204B_SERIAL_DATA(8) <= '0';
+ JESD204B_SERIAL_DATA(9) <= '0';
+ JESD204B_SERIAL_DATA(10) <= '0';
+ JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+
+
+ u_revision : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
new file mode 100644
index 0000000000..f760f1cff6
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
@@ -0,0 +1,359 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_sdp_station_fsub using WG data.
+--
+-- Description:
+-- MM control actions:
+--
+-- 1) Enable calc mode for WG via reg_diag_wg with:
+-- freq = 19.921875MHz
+-- ampl = 0.5 * 2**13
+--
+-- 2) Read current BSN from reg_bsn_scheduler_wg and write reg_bsn_scheduler_wg
+-- to trigger start of WG at BSN.
+--
+-- 3) Read subband statistics (SST) via ram_st_sst and verify with
+-- c_exp_subband_power_sp_0 at c_subband_sp_0.
+-- View sp_subband_power_0 in Wave window
+--
+--
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- > run -a
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_sdp_station_fsub IS
+END tb_lofar2_unb2b_sdp_station_fsub;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+ CONSTANT c_pps_period : NATURAL := 1000;
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+
+ CONSTANT c_nof_block_per_sync : NATURAL := 16;
+ CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+
+ CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
+ CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
+ CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
+
+ -- WG
+ CONSTANT c_full_scale_ampl : REAL := REAL(2**(14-1)-1); -- = full scale of WG
+ CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/2; -- in number of lsb
+ CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+ CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
+ CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
+ CONSTANT c_exp_wg_power_sp_0 : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_sdp_N_fft*c_nof_block_per_sync);
+
+ -- WPFB
+ CONSTANT c_nof_pfb : NATURAL := 1; -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
+ CONSTANT c_wb_leakage_bin : NATURAL := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor; -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
+ CONSTANT c_exp_sp_subband_power_ratio : REAL := 1.0/8.0; -- depends on internal WPFB quantization and FIR coefficients
+ CONSTANT c_exp_sp_subband_power_sum_ratio : REAL := c_exp_sp_subband_power_ratio; -- because all sinus power is expected in one subband
+ CONSTANT c_exp_subband_power_sp_0 : REAL := c_exp_wg_power_sp_0 * c_exp_sp_subband_power_ratio;
+
+ TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL;
+ TyPE t_slv_64_subbands_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_N_sub);
+
+ -- MM
+ CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
+ CONSTANT c_mm_file_reg_bsn_source : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE";
+ CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+ CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+ CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+
+ -- WG
+ SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+ -- WPFB
+ SIGNAL sp_subband_powers_arr2 : t_slv_64_subbands_arr(c_nof_pfb*c_nof_complex-1 DOWNTO 0); -- [sp][sub]
+ SIGNAL sp_subband_power_0 : REAL;
+ SIGNAL sp_subband_power_sum : t_real_arr(c_nof_pfb*c_nof_complex-1 DOWNTO 0) := (OTHERS=>0.0);
+ SIGNAL sp_subband_power_sum_0 : REAL;
+ SIGNAL sp_subband_power_ratio_0 : REAL;
+ SIGNAL sp_subband_power_sum_ratio_0 : REAL;
+ SIGNAL sp_subband_power_leakage_sum_0 : REAL;
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ -- back transceivers
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
+
+ -- jesd204b syncronization signals
+ SIGNAL jesd204b_sysref : STD_LOGIC;
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
+ jesd204b_sysref <= pps;
+ ext_pps <= pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_lofar_unb2b_sdp_station_fsub : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2b_sdp_station_fsub",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_scope_selected_subband => NATURAL(c_subband_sp_0)
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
+
+ ------------------------------------------------------------------------------
+ -- MM slave accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ VARIABLE v_bsn : NATURAL;
+ VARIABLE v_sp_subband_power : REAL;
+ VARIABLE v_W, v_T, v_U, v_S, v_B : NATURAL; -- array indicies
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+
+ ----------------------------------------------------------------------------
+ -- Enable BS
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 0, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+
+ ----------------------------------------------------------------------------
+ -- Enable WG
+ ----------------------------------------------------------------------------
+ -- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3)
+ -- nof_samples[31:16] --> <= c_ram_wg_size=1024
+ -- 1 : phase[15:0]
+ -- 2 : freq[30:0]
+ -- 3 : ampl[16:0]
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER((c_subband_sp_0+c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, INTEGER(REAL(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl
+
+ -- Read current BSN
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ -- Write scheduler BSN to trigger start of WG at next block
+ v_bsn := TO_UINT(current_bsn_wg) + 2;
+ ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
+ v_bsn := c_bsn_start_wg;
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+
+ -- Wait for enough WG data and start of sync interval
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync*3, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
+
+ ---------------------------------------------------------------------------
+ -- Read subband statistics
+ ---------------------------------------------------------------------------
+ -- . the subband statistics are c_wpfb_sim.stat_data_sz = 2 word power values.
+ -- . there are c_sdp_N_sub = 512 subbands per signal path
+ -- . one complex WPFB can process two real inputs A, B
+ -- . the subbands are output alternately so A0 B0 A1 B1 ... A511 B511 for input A, B
+ -- . the subband statistics multiple WPFB units appear in order in the ram_st_sst address map
+ -- . the subband statistics are stored first lo word 0 then hi word 1
+
+ FOR I IN 0 TO c_nof_pfb*c_nof_complex*c_sdp_N_sub*c_wpfb_sim.stat_data_sz-1 LOOP
+ v_W := I MOD c_wpfb_sim.stat_data_sz;
+ v_T := (I / c_wpfb_sim.stat_data_sz) MOD c_nof_complex;
+ v_U := I / (c_nof_complex*c_wpfb_sim.stat_data_sz*c_sdp_N_sub);
+ v_S := v_T + v_U * c_nof_complex;
+ v_B := (I / (c_nof_complex*c_wpfb_sim.stat_data_sz)) MOD c_sdp_N_sub;
+ IF v_W=0 THEN
+ -- low part
+ mmf_mm_bus_rd(c_mm_file_ram_st_sst, I, rd_data, tb_clk);
+ sp_subband_powers_arr2(v_S)(v_B)(31 DOWNTO 0) <= rd_data;
+ ELSE
+ -- high part
+ mmf_mm_bus_rd(c_mm_file_ram_st_sst, I, rd_data, tb_clk);
+ sp_subband_powers_arr2(v_S)(v_B)(63 DOWNTO 32) <= rd_data;
+
+ -- Convert STD_LOGIC_VECTOR to REAL
+ v_sp_subband_power := REAL(TO_UINT(rd_data(29 DOWNTO 0) &
+ sp_subband_powers_arr2(v_S)(v_B)(31 DOWNTO 30)))*2.0**30 +
+ REAL(TO_UINT(sp_subband_powers_arr2(v_S)(v_B)(29 DOWNTO 0)));
+ -- sum
+ sp_subband_power_sum(v_S) <= sp_subband_power_sum(v_S) + v_sp_subband_power;
+ END IF;
+ END LOOP;
+
+ -- sp_subband_power_sum is the sum of all subband powers per SP, this value will be close to sp_subband_power
+ -- because the input is a sinus, so most power will be in 1 subband. The sp_subband_power_leakage_sum shows
+ -- how much power from the input sinus at a specific subband has leaked into the 511 other subbands.
+ sp_subband_power_0 <= REAL(TO_UINT(sp_subband_powers_arr2(0)(INTEGER(ROUND(c_subband_sp_0)))(61 DOWNTO 30)))*2.0**30 +
+ REAL(TO_UINT(sp_subband_powers_arr2(0)(INTEGER(ROUND(c_subband_sp_0)))(29 DOWNTO 0)));
+
+ sp_subband_power_sum_0 <= sp_subband_power_sum(0);
+
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ ---------------------------------------------------------------------------
+ -- Verify subband statistics
+ ---------------------------------------------------------------------------
+ -- verify expected subband power based on WG power
+ IF sp_subband_power_sum_0>0.0 THEN ASSERT sp_subband_power_0 > c_lo_factor * c_exp_subband_power_sp_0 REPORT "Wrong subband power for SP 0" SEVERITY ERROR; END IF;
+ IF sp_subband_power_sum_0>0.0 THEN ASSERT sp_subband_power_0 < c_hi_factor * c_exp_subband_power_sp_0 REPORT "Wrong subband power for SP 0" SEVERITY ERROR; END IF;
+
+ -- view c_exp_sp_subband_power_ratio in Wave window
+ IF sp_subband_power_sum_0>0.0 THEN sp_subband_power_ratio_0 <= sp_subband_power_0/sp_subband_power_sum_0; END IF;
+
+ -- view c_exp_sp_subband_power_sum_ratio in Wave window
+ -- The sp_subband_power_sum_ratio show similar information as sp_subband_power_leakage_sum, because when
+ -- sp_subband_power_leakage_sum is small then sp_subband_power_sum_ratio ~= sp_subband_power_ratio.
+ IF sp_subband_power_sum_0>0.0 THEN sp_subband_power_sum_ratio_0 <= sp_subband_power_sum_0/sp_subband_power_0; END IF;
+
+ -- View sp_subband_power_leakage_sum in Wave window
+ IF sp_subband_power_sum_0>0.0 THEN sp_subband_power_leakage_sum_0 <= sp_subband_power_sum_0 - sp_subband_power_0; END IF;
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+ WAIT;
+ END PROCESS;
+
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 575fcb8482..bf5f1e8b2f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -47,7 +47,6 @@ ENTITY lofar2_unb2b_sdp_station IS
g_design_name : STRING := "lofar2_unb2b_sdp_station";
g_design_note : STRING := "UNUSED";
g_technology : NATURAL := c_tech_arria10_e1sg;
- g_buf_nof_data : NATURAL := 1024;
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
@@ -109,8 +108,6 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
-- Revision parameters
CONSTANT c_revision_select : t_lofar2_unb2b_sdp_station_config := func_sel_revision_rec(g_design_name);
- CONSTANT c_nof_streams : NATURAL := c_revision_select.nof_streams_input; -- Streams actually passed through for processing
- CONSTANT c_dp_clk_freq : NATURAL := c_revision_select.dp_clk_freq;
-- Firmware version x.y
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
@@ -226,6 +223,10 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL jesd204b_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL jesd204b_miso : t_mem_miso := c_mem_miso_rst;
+ -- JESD control
+ SIGNAL jesd_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL jesd_ctrl_miso : t_mem_miso := c_mem_miso_rst;
+
-- Shiftram (applies per-antenna delay)
SIGNAL reg_dp_shiftram_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_dp_shiftram_miso : t_mem_miso := c_mem_miso_rst;
@@ -248,12 +249,6 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL reg_bsn_monitor_input_mosi : t_mem_mosi;
SIGNAL reg_bsn_monitor_input_miso : t_mem_miso;
- -- Data buffer raw
- SIGNAL ram_diag_data_buf_jesd_mosi: t_mem_mosi;
- SIGNAL ram_diag_data_buf_jesd_miso: t_mem_miso;
- SIGNAL reg_diag_data_buf_jesd_mosi: t_mem_mosi;
- SIGNAL reg_diag_data_buf_jesd_miso: t_mem_miso;
-
-- Data buffer bsn
SIGNAL ram_diag_data_buf_bsn_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_bsn_miso : t_mem_miso;
@@ -261,8 +256,6 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL reg_diag_data_buf_bsn_miso : t_mem_miso;
-- Aduh statistics monitor
- SIGNAL ram_aduh_monitor_mosi : t_mem_mosi;
- SIGNAL ram_aduh_monitor_miso : t_mem_miso;
SIGNAL reg_aduh_monitor_mosi : t_mem_mosi;
SIGNAL reg_aduh_monitor_miso : t_mem_miso;
@@ -342,16 +335,16 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL reg_nw_10GbE_eth10g_mosi : t_mem_mosi;
SIGNAL reg_nw_10GbE_eth10g_miso : t_mem_miso;
-
+
----------------------------------------------
- SIGNAL ait_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
- SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ SIGNAL ait_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
+ SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
- SIGNAL bf_udp_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
- SIGNAL bf_udp_siso_arr : t_dp_siso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
- SIGNAL bf_10GbE_hdr_fields_out_arr: t_slv_1024_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL bf_udp_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL bf_udp_siso_arr : t_dp_siso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL bf_10GbE_hdr_fields_out_arr : t_slv_1024_arr(c_sdp_N_beamsets-1 DOWNTO 0);
-- 10GbE
SIGNAL tr_ref_clk_312 : STD_LOGIC;
@@ -380,7 +373,6 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL sdp_info : t_sdp_info := c_sdp_info_rst;
-
-- QSFP LEDS
SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
@@ -389,8 +381,6 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL unb2_board_qsfp_leds_snk_out_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL unb2_board_qsfp_leds_src_out_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-
-
BEGIN
-----------------------------------------------------------------------------
@@ -411,7 +401,7 @@ BEGIN
g_aux => c_unb2b_board_aux,
g_factory_image => g_factory_image,
g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_dp_clk_freq,
+ g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
g_dp_clk_use_pll => FALSE
)
PORT MAP (
@@ -577,6 +567,8 @@ BEGIN
-- Jesd ip status/control
jesd204b_mosi => jesd204b_mosi,
jesd204b_miso => jesd204b_miso,
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
reg_dp_shiftram_miso => reg_dp_shiftram_miso,
reg_bsn_source_mosi => reg_bsn_source_mosi,
@@ -589,16 +581,10 @@ BEGIN
ram_wg_miso => ram_wg_miso,
reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
ram_st_sst_mosi => ram_st_sst_mosi,
@@ -633,16 +619,45 @@ BEGIN
ram_scrap_miso => ram_scrap_miso
);
-
+ -----------------------------------------------------------------------------
+ -- SDP Info register
+ -----------------------------------------------------------------------------
+ gn_index <= TO_UINT(ID(c_sdp_W_gn_id-1 DOWNTO 0));
+ -- derive MAC, IP and UDP Port from ID
+ id_backplane <= RESIZE_UVEC(ID(c_sdp_W_gn_id-1 DOWNTO 2), c_byte_w);
+ id_eth <= RESIZE_UVEC(ID(1 DOWNTO 0) & TO_UVEC(0, 2), c_byte_w);
+ eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & id_backplane & INCR_UVEC(id_eth, 0); -- Interface id = 0
+ ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & id_backplane & INCR_UVEC(id_eth, 1); -- Interface id = 0
+ udp_src_port <= c_sdp_cep_udp_src_port_15_8 & ID;
+
+ u_sdp_info : ENTITY lofar2_sdp_lib.sdp_info
+ PORT MAP(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
+
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
+
+ -- sdp info
+ sdp_info => sdp_info
+ );
+
-----------------------------------------------------------------------------
-- node_adc_input_and_timing (AIT)
-- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
-----------------------------------------------------------------------------
- u_ait: ENTITY lofar2_sdp_lib.node_adc_input_and_timing
+ u_ait: ENTITY lofar2_sdp_lib.node_sdp_adc_input_and_timing
GENERIC MAP(
g_technology => g_technology,
- g_nof_streams => c_sdp_S_pn,
- g_buf_nof_data => c_sdp_ait_buf_nof_data_bsn,
g_sim => g_sim
)
PORT MAP(
@@ -653,7 +668,8 @@ BEGIN
dp_rst => dp_rst,
-- mm control buses
- jesd_ctrl_mosi => c_mem_mosi_rst,
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
jesd204b_mosi => jesd204b_mosi,
jesd204b_miso => jesd204b_miso,
reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
@@ -668,16 +684,10 @@ BEGIN
ram_wg_miso => ram_wg_miso,
reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
@@ -691,234 +701,197 @@ BEGIN
out_sosi_arr => ait_sosi_arr
);
-
-----------------------------------------------------------------------------
-- node_sdp_filterbank (FSUB)
-----------------------------------------------------------------------------
- u_fsub : ENTITY lofar2_sdp_lib.node_sdp_filterbank
- GENERIC MAP(
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso,
-
- sdp_info => sdp_info,
- gn_id => ID(c_sdp_W_gn_id-1 DOWNTO 0),
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port
- );
-
-
-
- -----------------------------------------------------------------------------
- -- SDP Info register
- -----------------------------------------------------------------------------
- gn_index <= TO_UINT(ID(c_sdp_W_gn_id-1 DOWNTO 0));
-
- u_sdp_info : ENTITY lofar2_sdp_lib.sdp_info
- PORT MAP(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
-
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
-
- -- inputs from other blocks
- gn_index => gn_index,
- f_adc => c_f_adc,
- fsub_type => c_fsub_type,
-
- -- sdp info
- sdp_info => sdp_info
- );
-
- -----------------------------------------------------------------------------
- -- nof beamsets node_sdp_beamformers (BF)
- -----------------------------------------------------------------------------
- -- derive MAC, IP and UDP Port from ID
- id_backplane <= RESIZE_UVEC(ID(c_sdp_W_gn_id-1 DOWNTO 2), c_byte_w);
- id_eth <= RESIZE_UVEC(ID(1 DOWNTO 0) & TO_UVEC(0, 2), c_byte_w);
- eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & id_backplane & INCR_UVEC(id_eth, 0); -- Interface id = 0
- ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & id_backplane & INCR_UVEC(id_eth, 1); -- Interface id = 0
- udp_src_port <= c_sdp_cep_udp_src_port_15_8 & ID;
-
- -- Beamformers
- gen_bf : FOR beamset_id IN 0 TO c_sdp_N_beamsets-1 GENERATE
- u_bf : ENTITY lofar2_sdp_lib.node_sdp_beamformer
+ gen_use_fsub : IF c_revision_select.use_fsub GENERATE
+ u_fsub : ENTITY lofar2_sdp_lib.node_sdp_filterbank
GENERIC MAP(
- g_sim => g_sim,
- g_beamset_id => beamset_id,
- g_scope_selected_beamlet => g_scope_selected_subband
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
)
PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_sosi_arr,
- bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
- bf_udp_siso => bf_udp_siso_arr(beamset_id),
- bst_udp_sosi => OPEN,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
- ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
- ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
- reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
- reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
- reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
- reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
- reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
- ram_st_sst_mosi => ram_st_bst_mosi_arr(beamset_id),
- ram_st_sst_miso => ram_st_bst_miso_arr(beamset_id),
-
- sdp_info => sdp_info,
- gn_id => ID(c_sdp_W_gn_id-1 DOWNTO 0),
-
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port,
-
- hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso,
+
+ sdp_info => sdp_info,
+ gn_id => ID(c_sdp_W_gn_id-1 DOWNTO 0),
+ eth_src_mac => eth_src_mac,
+ ip_src_addr => ip_src_addr,
+ udp_src_port => udp_src_port
);
-
END GENERATE;
- -- MM multiplexing
- u_mem_mux_ram_ss_ss_wide : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_ss_ss_wide
- )
- PORT MAP (
- mosi => ram_ss_ss_wide_mosi,
- miso => ram_ss_ss_wide_miso,
- mosi_arr => ram_ss_ss_wide_mosi_arr,
- miso_arr => ram_ss_ss_wide_miso_arr
- );
-
- u_mem_mux_ram_bf_weights : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_bf_weights
- )
- PORT MAP (
- mosi => ram_bf_weights_mosi,
- miso => ram_bf_weights_miso,
- mosi_arr => ram_bf_weights_mosi_arr,
- miso_arr => ram_bf_weights_miso_arr
- );
-
- u_mem_mux_reg_bf_scale : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bf_scale
- )
- PORT MAP (
- mosi => reg_bf_scale_mosi,
- miso => reg_bf_scale_miso,
- mosi_arr => reg_bf_scale_mosi_arr,
- miso_arr => reg_bf_scale_miso_arr
- );
-
- u_mem_mux_reg_hdr_dat : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_hdr_dat
- )
- PORT MAP (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
-
- u_mem_mux_reg_dp_xonoff : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_dp_xonoff
- )
- PORT MAP (
- mosi => reg_dp_xonoff_mosi,
- miso => reg_dp_xonoff_miso,
- mosi_arr => reg_dp_xonoff_mosi_arr,
- miso_arr => reg_dp_xonoff_miso_arr
- );
-
- u_mem_mux_ram_st_bst : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_st_bst
- )
- PORT MAP (
- mosi => ram_st_bst_mosi,
- miso => ram_st_bst_miso,
- mosi_arr => ram_st_bst_mosi_arr,
- miso_arr => ram_st_bst_miso_arr
- );
-
-
-
-----------------------------------------------------------------------------
- -- DP MUX
+ -- nof beamsets node_sdp_beamformers (BF)
-----------------------------------------------------------------------------
- -- Assign hdr_fields to nw_10GbE for ARP/PING functionality. Only the fields:
- -- eth_src_mac, ip_src_addr and ip_dst_addr are used. Which are identical for
- -- both beamsets.
- nw_10GbE_hdr_fields_in_arr(0) <= bf_10GbE_hdr_fields_out_arr(0);
-
- u_dp_mux : ENTITY dp_lib.dp_mux
- GENERIC MAP (
- g_nof_input => c_sdp_N_beamsets,
- g_sel_ctrl_invert => TRUE,
- g_fifo_size => array_init(0,c_sdp_N_beamsets), --no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_sdp_N_beamsets) --no FIFO used but must match g_nof_input
- )
- PORT MAP (
- clk => dp_clk,
- rst => dp_rst,
-
- snk_in_arr => bf_udp_sosi_arr,
- snk_out_arr => bf_udp_siso_arr,
+ gen_use_bf : IF c_revision_select.use_bf GENERATE
+ -- Beamformers
+ gen_bf : FOR beamset_id IN 0 TO c_sdp_N_beamsets-1 GENERATE
+ u_bf : ENTITY lofar2_sdp_lib.node_sdp_beamformer
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_beamset_id => beamset_id,
+ g_scope_selected_beamlet => g_scope_selected_subband
+ )
+ PORT MAP(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_sosi_arr,
+ bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
+ bf_udp_siso => bf_udp_siso_arr(beamset_id),
+ bst_udp_sosi => OPEN,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
+ ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
+ ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
+ reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
+ reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
+ reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
+ ram_st_sst_mosi => ram_st_bst_mosi_arr(beamset_id),
+ ram_st_sst_miso => ram_st_bst_miso_arr(beamset_id),
+
+ sdp_info => sdp_info,
+ gn_id => ID(c_sdp_W_gn_id-1 DOWNTO 0),
+
+ eth_src_mac => eth_src_mac,
+ ip_src_addr => ip_src_addr,
+ udp_src_port => udp_src_port,
+
+ hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
+ );
- src_out => nw_10gbe_snk_in_arr(0),
- src_in => nw_10gbe_snk_out_arr(0)
- );
-
-
- -----------------------------------------------------------------------------
- -- Interface : 10GbE
- -----------------------------------------------------------------------------
-
+ END GENERATE;
+
+ -- MM multiplexing
+ u_mem_mux_ram_ss_ss_wide : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_ss_ss_wide
+ )
+ PORT MAP (
+ mosi => ram_ss_ss_wide_mosi,
+ miso => ram_ss_ss_wide_miso,
+ mosi_arr => ram_ss_ss_wide_mosi_arr,
+ miso_arr => ram_ss_ss_wide_miso_arr
+ );
+
+ u_mem_mux_ram_bf_weights : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_bf_weights
+ )
+ PORT MAP (
+ mosi => ram_bf_weights_mosi,
+ miso => ram_bf_weights_miso,
+ mosi_arr => ram_bf_weights_mosi_arr,
+ miso_arr => ram_bf_weights_miso_arr
+ );
+
+ u_mem_mux_reg_bf_scale : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bf_scale
+ )
+ PORT MAP (
+ mosi => reg_bf_scale_mosi,
+ miso => reg_bf_scale_miso,
+ mosi_arr => reg_bf_scale_mosi_arr,
+ miso_arr => reg_bf_scale_miso_arr
+ );
+
+ u_mem_mux_reg_hdr_dat : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_hdr_dat
+ )
+ PORT MAP (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
+
+ u_mem_mux_reg_dp_xonoff : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_dp_xonoff
+ )
+ PORT MAP (
+ mosi => reg_dp_xonoff_mosi,
+ miso => reg_dp_xonoff_miso,
+ mosi_arr => reg_dp_xonoff_mosi_arr,
+ miso_arr => reg_dp_xonoff_miso_arr
+ );
+
+ u_mem_mux_ram_st_bst : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_st_bst
+ )
+ PORT MAP (
+ mosi => ram_st_bst_mosi,
+ miso => ram_st_bst_miso,
+ mosi_arr => ram_st_bst_mosi_arr,
+ miso_arr => ram_st_bst_miso_arr
+ );
+
+ -----------------------------------------------------------------------------
+ -- DP MUX
+ -----------------------------------------------------------------------------
+ -- Assign hdr_fields to nw_10GbE for ARP/PING functionality. Only the fields:
+ -- eth_src_mac, ip_src_addr and ip_dst_addr are used. Which are identical for
+ -- both beamsets.
+ nw_10GbE_hdr_fields_in_arr(0) <= bf_10GbE_hdr_fields_out_arr(0);
+
+ u_dp_mux : ENTITY dp_lib.dp_mux
+ GENERIC MAP (
+ g_nof_input => c_sdp_N_beamsets,
+ g_sel_ctrl_invert => TRUE,
+ g_fifo_size => array_init(0,c_sdp_N_beamsets), --no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0,c_sdp_N_beamsets) --no FIFO used but must match g_nof_input
+ )
+ PORT MAP (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in_arr => bf_udp_sosi_arr,
+ snk_out_arr => bf_udp_siso_arr,
+
+ src_out => nw_10gbe_snk_in_arr(0),
+ src_in => nw_10gbe_snk_out_arr(0)
+ );
+
+ -----------------------------------------------------------------------------
+ -- Interface : 10GbE
+ -----------------------------------------------------------------------------
-- put the QSFP_TX/RX ports into arrays
i_QSFP_RX(0) <= QSFP_1_RX;
QSFP_1_TX <= i_QSFP_TX(0);
@@ -932,17 +905,16 @@ BEGIN
PORT MAP (
serial_tx_arr => unb2_board_front_io_serial_tx_arr,
serial_rx_arr => unb2_board_front_io_serial_rx_arr,
-
+
green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
-
+
QSFP_RX => i_QSFP_RX,
QSFP_TX => i_QSFP_TX,
-
+
QSFP_LED => QSFP_LED
);
-
-
+
---------
-- PLL
---------
@@ -958,8 +930,7 @@ BEGIN
rst_156 => tr_ref_rst_156,
rst_312 => OPEN
);
-
-
+
---------------
-- nw_10GbE
---------------
@@ -973,7 +944,7 @@ BEGIN
g_tx_fifo_fill => c_fifo_tx_fill,
g_tx_fifo_size => c_fifo_tx_size,
g_ip_hdr_field_arr => c_sdp_cep_hdr_field_arr
-
+
)
PORT MAP (
-- Transceiver PLL reference clock
@@ -981,33 +952,33 @@ BEGIN
tr_ref_clk_312 => tr_ref_clk_312,
tr_ref_clk_156 => tr_ref_clk_156,
tr_ref_rst_156 => tr_ref_rst_156,
-
+
-- MM interface
mm_rst => mm_rst,
mm_clk => mm_clk,
-
+
reg_mac_mosi => reg_nw_10GbE_mac_mosi,
reg_mac_miso => reg_nw_10GbE_mac_miso,
-
+
reg_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
reg_eth10g_miso => reg_nw_10GbE_eth10g_miso,
-
+
-- DP interface
dp_rst => dp_rst,
dp_clk => dp_clk,
dp_pps => dp_pps,
-
+
src_out_arr => nw_10gbe_src_out_arr,
src_in_arr => nw_10gbe_src_in_arr,
-
+
snk_out_arr => nw_10gbe_snk_out_arr,
snk_in_arr => nw_10gbe_snk_in_arr,
-
+
-- Serial IO
serial_tx_arr => unb2_board_front_io_serial_tx_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
serial_rx_arr => unb2_board_front_io_serial_rx_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
-
+
hdr_fields_in_arr => nw_10GbE_hdr_fields_in_arr
);
-
+ END GENERATE;
END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
index c2655c4817..339ec50a03 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
@@ -32,16 +32,16 @@ PACKAGE lofar2_unb2b_sdp_station_pkg IS
-----------------------------------------------------------------------------
TYPE t_lofar2_unb2b_sdp_station_config IS RECORD
- nof_streams_jesd204b : NATURAL;
- nof_streams_db : NATURAL;
- nof_streams_input : NATURAL;
- dp_clk_freq : NATURAL;
+ no_jesd : BOOLEAN;
+ use_fsub : BOOLEAN;
+ use_bf : BOOLEAN;
END RECORD;
- -- nofjesd, nofdb, nofinput
- CONSTANT c_one_node : t_lofar2_unb2b_sdp_station_config := ( 12, 2, 12, c_unb2b_board_ext_clk_freq_200M );
- CONSTANT c_one_node_256MHz : t_lofar2_unb2b_sdp_station_config := ( 12, 2, 12, c_unb2b_board_ext_clk_freq_256M );
-
+ CONSTANT c_ait : t_lofar2_unb2b_sdp_station_config := (FALSE, FALSE, FALSE);
+ CONSTANT c_fsub : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE);
+ CONSTANT c_bf : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE);
+ CONSTANT c_full : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE);
+
-- Function to select the revision configuration.
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_sdp_station_config;
@@ -53,9 +53,10 @@ PACKAGE BODY lofar2_unb2b_sdp_station_pkg IS
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_sdp_station_config IS
BEGIN
- IF g_design_name = "lofar2_unb2b_sdp_station_one_node" THEN RETURN c_one_node;
- ELSIF g_design_name = "lofar2_unb2b_sdp_station_one_node_256MHz" THEN RETURN c_one_node_256MHz;
- ELSE RETURN c_one_node;
+ IF g_design_name = "lofar2_unb2b_sdp_station_adc" THEN RETURN c_ait;
+ ELSIF g_design_name = "lofar2_unb2b_sdp_station_fsub" THEN RETURN c_fsub;
+ ELSIF g_design_name = "lofar2_unb2b_sdp_station_bf" THEN RETURN c_bf;
+ ELSE RETURN c_full;
END IF;
END;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index 71fd8f26e5..e194d9412f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -124,12 +124,6 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
ram_wg_mosi : OUT t_mem_mosi;
ram_wg_miso : IN t_mem_miso;
- -- JESD databuffer
- ram_diag_data_buf_jesd_mosi : OUT t_mem_mosi;
- ram_diag_data_buf_jesd_miso : IN t_mem_miso;
- reg_diag_data_buf_jesd_mosi : OUT t_mem_mosi;
- reg_diag_data_buf_jesd_miso : IN t_mem_miso;
-
-- Bsn databuffer
ram_diag_data_buf_bsn_mosi : OUT t_mem_mosi;
ram_diag_data_buf_bsn_miso : IN t_mem_miso;
@@ -137,8 +131,6 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
reg_diag_data_buf_bsn_miso : IN t_mem_miso;
-- Aduh
- ram_aduh_monitor_mosi : OUT t_mem_mosi;
- ram_aduh_monitor_miso : IN t_mem_miso;
reg_aduh_monitor_mosi : OUT t_mem_mosi;
reg_aduh_monitor_miso : IN t_mem_miso;
@@ -198,9 +190,13 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
reg_nw_10GbE_eth10g_mosi : OUT t_mem_mosi;
reg_nw_10GbE_eth10g_miso : IN t_mem_miso;
- -- Scrap ram
- ram_scrap_mosi : OUT t_mem_mosi;
- ram_scrap_miso : IN t_mem_miso
+ -- Scrap ram
+ ram_scrap_mosi : OUT t_mem_mosi;
+ ram_scrap_miso : IN t_mem_miso;
+
+ -- Jesd reset control
+ jesd_ctrl_mosi : OUT t_mem_mosi;
+ jesd_ctrl_miso : IN t_mem_miso
);
END mmm_lofar2_unb2b_sdp_station;
@@ -267,18 +263,11 @@ BEGIN
u_mm_file_ram_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
PORT MAP(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
- u_mm_file_ram_diag_data_buf_jesd : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
- PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
- u_mm_file_reg_diag_data_buf_jesd : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
- PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
-
- u_mm_file_ram_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
+ u_mm_file_ram_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
- u_mm_file_reg_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
+ u_mm_file_reg_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
- u_mm_file_ram_aduh_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
- PORT MAP(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
u_mm_file_reg_aduh_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
@@ -452,6 +441,14 @@ BEGIN
jesd204b_read_export => jesd204b_mosi.rd,
jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_jesd_ctrl_reset_export => OPEN,
+ pio_jesd_ctrl_clk_export => OPEN,
+ pio_jesd_ctrl_address_export => jesd_ctrl_mosi.address(c_sdp_jesd_ctrl_addr_w-1 DOWNTO 0),
+ pio_jesd_ctrl_write_export => jesd_ctrl_mosi.wr,
+ pio_jesd_ctrl_writedata_export => jesd_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_jesd_ctrl_read_export => jesd_ctrl_mosi.rd,
+ pio_jesd_ctrl_readdata_export => jesd_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+
reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(c_sdp_reg_bsn_monitor_input_addr_w-1 DOWNTO 0),
reg_bsn_monitor_input_clk_export => OPEN,
reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
@@ -542,37 +539,21 @@ BEGIN
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_diag_data_buf_bsn_clk_export => OPEN,
- ram_diag_data_buf_bsn_reset_export => OPEN,
- ram_diag_data_buf_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(c_sdp_ram_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
- ram_diag_data_buf_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
- ram_diag_data_buf_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_diag_data_buf_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
- ram_diag_data_buf_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
-
- reg_diag_data_buf_bsn_reset_export => OPEN,
- reg_diag_data_buf_bsn_clk_export => OPEN,
- reg_diag_data_buf_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(c_sdp_reg_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
- reg_diag_data_buf_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
- reg_diag_data_buf_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_diag_data_buf_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
- reg_diag_data_buf_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
-
- ram_diag_data_buf_jesd_clk_export => OPEN,
- ram_diag_data_buf_jesd_reset_export => OPEN,
- ram_diag_data_buf_jesd_address_export => ram_diag_data_buf_jesd_mosi.address(c_sdp_ram_diag_data_buf_jesd_addr_w-1 DOWNTO 0),
- ram_diag_data_buf_jesd_write_export => ram_diag_data_buf_jesd_mosi.wr,
- ram_diag_data_buf_jesd_writedata_export => ram_diag_data_buf_jesd_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_diag_data_buf_jesd_read_export => ram_diag_data_buf_jesd_mosi.rd,
- ram_diag_data_buf_jesd_readdata_export => ram_diag_data_buf_jesd_miso.rddata(c_word_w-1 DOWNTO 0),
-
- reg_diag_data_buf_jesd_reset_export => OPEN,
- reg_diag_data_buf_jesd_clk_export => OPEN,
- reg_diag_data_buf_jesd_address_export => reg_diag_data_buf_jesd_mosi.address(c_sdp_reg_diag_data_buf_jesd_addr_w-1 DOWNTO 0),
- reg_diag_data_buf_jesd_write_export => reg_diag_data_buf_jesd_mosi.wr,
- reg_diag_data_buf_jesd_writedata_export => reg_diag_data_buf_jesd_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_diag_data_buf_jesd_read_export => reg_diag_data_buf_jesd_mosi.rd,
- reg_diag_data_buf_jesd_readdata_export => reg_diag_data_buf_jesd_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_clk_export => OPEN,
+ ram_diag_data_buffer_bsn_reset_export => OPEN,
+ ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(c_sdp_ram_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
+ ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
+ ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_diag_data_buffer_bsn_reset_export => OPEN,
+ reg_diag_data_buffer_bsn_clk_export => OPEN,
+ reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(c_sdp_reg_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
+ reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
+ reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
reg_aduh_monitor_reset_export => OPEN,
reg_aduh_monitor_clk_export => OPEN,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 0d16d3b338..7a30524578 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -28,323 +28,310 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
-----------------------------------------------------------------------------
component qsys_lofar2_unb2b_sdp_station is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buf_bsn_read_export : out std_logic; -- export
- ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buf_bsn_write_export : out std_logic; -- export
- ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buf_bsn_read_export : out std_logic; -- export
- reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buf_bsn_write_export : out std_logic; -- export
- reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bf_weights_clk_export : out std_logic; -- export
+ ram_bf_weights_read_export : out std_logic; -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_bf_weights_reset_export : out std_logic; -- export
+ ram_bf_weights_write_export : out std_logic; -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_st_bst_clk_export : out std_logic; -- export
+ ram_st_bst_read_export : out std_logic; -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_bst_reset_export : out std_logic; -- export
+ ram_st_bst_write_export : out std_logic; -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bf_scale_clk_export : out std_logic; -- export
+ reg_bf_scale_read_export : out std_logic; -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bf_scale_reset_export : out std_logic; -- export
+ reg_bf_scale_write_export : out std_logic; -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_xonoff_clk_export : out std_logic; -- export
+ reg_dp_xonoff_read_export : out std_logic; -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_reset_export : out std_logic; -- export
+ reg_dp_xonoff_write_export : out std_logic; -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_clk_export : out std_logic; -- export
+ reg_hdr_dat_read_export : out std_logic; -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_reset_export : out std_logic; -- export
+ reg_hdr_dat_write_export : out std_logic; -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic; -- export
+ reg_nw_10gbe_mac_read_export : out std_logic; -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic; -- export
+ reg_nw_10gbe_mac_write_export : out std_logic; -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2b_sdp_station;
+
END qsys_lofar2_unb2b_sdp_station_pkg;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 416841b96e..dee35dd346 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -141,11 +141,12 @@ PACKAGE sdp_pkg is
-- AIT MM address widths
CONSTANT c_sdp_jesd204b_addr_w : NATURAL := 8 + ceil_log2(c_sdp_S_pn);
+ CONSTANT c_sdp_jesd_ctrl_addr_w : NATURAL := 1;
CONSTANT c_sdp_reg_bsn_monitor_input_addr_w : NATURAL := 8;
CONSTANT c_sdp_reg_wg_addr_w : NATURAL := 2 + ceil_log2(c_sdp_S_pn);
CONSTANT c_sdp_ram_wg_addr_w : NATURAL := 10 + ceil_log2(c_sdp_S_pn);
CONSTANT c_sdp_reg_dp_shiftram_addr_w : NATURAL := 1 + ceil_log2(c_sdp_S_pn);
- CONSTANT c_sdp_reg_bsn_source_addr_w : NATURAL := 2;
+ CONSTANT c_sdp_reg_bsn_source_addr_w : NATURAL := 3;
CONSTANT c_sdp_reg_bsn_scheduler_addr_w : NATURAL := 1;
CONSTANT c_sdp_ram_diag_data_buf_bsn_addr_w : NATURAL := ceil_log2(c_sdp_S_pn*c_sdp_V_si_db_large); -- Dimension DB address range for largest DB, so that both the large and the default small DB fit.
CONSTANT c_sdp_reg_diag_data_buf_bsn_addr_w : NATURAL := 1 + ceil_log2(c_sdp_S_pn);
--
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