diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index bde1e5b94e23ef02f8694e5b9065afe70dd5358e..12048d88a88fb9a49145f04cfdac7201eb79bea1 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -74,6 +74,7 @@ synth_files =
src/vhdl/dp_block_gen.vhd
src/vhdl/dp_block_gen_valid_arr.vhd
src/vhdl/dp_bsn_source.vhd
+ src/vhdl/dp_bsn_source_v2.vhd
src/vhdl/dp_bsn_source_reg.vhd
src/vhdl/mms_dp_bsn_source.vhd
src/vhdl/dp_bsn_scheduler.vhd
@@ -183,8 +184,9 @@ test_bench_files =
tb/vhdl/tb_dp_bsn_align.vhd
tb/vhdl/tb_mms_dp_bsn_align.vhd
tb/vhdl/tb_dp_bsn_monitor.vhd
- tb/vhdl/tb_dp_bsn_source.vhd
+ tb/vhdl/tb_dp_bsn_source_v2.vhd
tb/vhdl/tb_mms_dp_bsn_source.vhd
+ tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
tb/vhdl/tb_dp_demux.vhd
tb/vhdl/tb2_dp_demux.vhd
tb/vhdl/tb3_dp_demux.vhd
@@ -302,7 +304,9 @@ regression_test_vhdl =
tb/vhdl/tb_dp_latency_adapter.vhd
tb/vhdl/tb_dp_shiftreg.vhd
tb/vhdl/tb_dp_bsn_source.vhd
+ tb/vhdl/tb_dp_bsn_source_v2.vhd
tb/vhdl/tb_mms_dp_bsn_source.vhd
+ tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
tb/vhdl/tb_tb_dp_block_select.vhd
tb/vhdl/tb_tb_dp_block_reshape.vhd
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5f2acfa1818b97d86048ad16e9466ef55ab7b3cb
--- /dev/null
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
@@ -0,0 +1,183 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose :
+-- Start a periodic block sync interval and maintain a block sequence
+-- number
+-- Description:
+-- When dp_on is low then all outputs are low. When dp_on is high, the
+-- output sync starts pulsing with a period of g_block_size number of clk
+-- cycles and the output valid, sop and eop will be active.
+-- Alternatively, one can assert dp_on while dp_on_pps is high to
+-- start the data path on the next PPS.
+-- Remarks:
+-- Starting the data path is only possible from the dp_off state, so one
+-- has to disable (dp_on='0') the data path before restarting it.
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+ENTITY dp_bsn_source_v2 IS
+ GENERIC (
+ g_block_size : NATURAL := 256;
+ g_nof_block_per_sync : NATURAL := 8;
+ g_bsn_w : NATURAL := 48
+ );
+ PORT (
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ pps : IN STD_LOGIC := '1';
+
+ dp_on : IN STD_LOGIC;
+ dp_on_pps : IN STD_LOGIC;
+
+ dp_on_status : OUT STD_LOGIC;
+
+ init_bsn : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+ nof_block_per_sync : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_block_per_sync, c_word_w);
+
+ src_out : OUT t_dp_sosi -- only uses sync, bsn[], valid, sop and eop
+ );
+END dp_bsn_source_v2;
+
+
+ARCHITECTURE rtl OF dp_bsn_source_v2 IS
+
+ CONSTANT c_block_size_cnt_w : NATURAL := ceil_log2(g_block_size);
+ CONSTANT c_block_cnt_zero : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS => '0');
+
+ TYPE t_state_enum IS (s_init, s_dp_off, s_dp_on_sop, s_dp_on, s_dp_on_eop);
+
+ SIGNAL state : t_state_enum;
+ SIGNAL nxt_state : t_state_enum;
+ SIGNAL prev_state : t_state_enum;
+
+ SIGNAL block_size_cnt : STD_LOGIC_VECTOR(c_block_size_cnt_w-1 DOWNTO 0);
+ SIGNAL nxt_block_size_cnt : STD_LOGIC_VECTOR(c_block_size_cnt_w-1 DOWNTO 0);
+
+ SIGNAL block_cnt : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ SIGNAL nxt_block_cnt : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+
+ SIGNAL i_src_out : t_dp_sosi := c_dp_sosi_init;
+ SIGNAL nxt_src_out : t_dp_sosi;
+
+ SIGNAL nxt_dp_on_status : STD_LOGIC;
+ SIGNAL i_dp_on_status : STD_LOGIC;
+
+BEGIN
+
+ src_out <= i_src_out;
+ dp_on_status <= i_dp_on_status;
+
+ p_state : PROCESS(state, prev_state, dp_on, dp_on_pps, pps, block_size_cnt, block_cnt, nof_block_per_sync, init_bsn, i_src_out, i_dp_on_status)
+ BEGIN
+ nxt_state <= state;
+ nxt_src_out <= i_src_out;
+ nxt_src_out.sync <= '0';
+ nxt_src_out.valid <= '0';
+ nxt_src_out.sop <= '0';
+ nxt_src_out.eop <= '0';
+ nxt_block_size_cnt <= block_size_cnt;
+ nxt_block_cnt <= block_cnt;
+ nxt_dp_on_status <= i_dp_on_status;
+
+ CASE state IS
+
+ WHEN s_dp_on_eop =>
+ nxt_src_out.eop <= '1';
+ nxt_src_out.valid <= '1';
+ nxt_state <= s_dp_on_sop;
+ nxt_block_size_cnt <= INCR_UVEC(block_size_cnt, 1);
+ IF UNSIGNED(block_cnt) = UNSIGNED(nof_block_per_sync) -1 THEN
+ nxt_block_cnt <= (OTHERS=>'0');
+ ELSE
+ nxt_block_cnt <= INCR_UVEC(block_cnt, 1);
+ END IF;
+ IF dp_on = '0' THEN
+ nxt_state <= s_dp_off;
+ END IF;
+
+ WHEN s_dp_on =>
+ nxt_src_out.valid <= '1';
+ nxt_block_size_cnt <= INCR_UVEC(block_size_cnt, 1);
+ IF UNSIGNED(block_size_cnt) = g_block_size -3 THEN
+ nxt_state <= s_dp_on_eop;
+ END IF;
+
+ WHEN s_dp_on_sop =>
+ nxt_dp_on_status <= '1';
+ nxt_src_out.sop <= '1';
+ nxt_src_out.valid <= '1';
+ nxt_state <= s_dp_on;
+ nxt_block_size_cnt <= (OTHERS=>'0');
+ IF prev_state = s_dp_on_eop THEN
+ nxt_src_out.bsn(g_bsn_w-1 DOWNTO 0) <= INCR_UVEC(i_src_out.bsn(g_bsn_w-1 DOWNTO 0), 1);
+ END IF;
+ IF UNSIGNED(block_cnt) = UNSIGNED(c_block_cnt_zero) THEN
+ nxt_src_out.sync <= '1';
+ END IF;
+
+ WHEN s_dp_off =>
+ nxt_dp_on_status <= '0';
+ nxt_block_cnt <= (OTHERS=>'0');
+ nxt_src_out.bsn <= RESIZE_DP_BSN(init_bsn);
+ IF dp_on = '1' THEN
+ IF dp_on_pps = '1' THEN
+ IF pps = '1' THEN
+ nxt_state <= s_dp_on_sop;
+ END IF;
+ ELSE
+ nxt_state <= s_dp_on_sop;
+ END IF;
+ END IF;
+
+ WHEN OTHERS => -- s_init
+ nxt_state <= s_dp_off;
+
+ END CASE;
+ END PROCESS;
+
+
+ p_clk : PROCESS(rst, clk)
+ BEGIN
+ IF rst='1' THEN
+ prev_state <= s_init;
+ state <= s_init;
+ i_src_out <= c_dp_sosi_rst;
+ block_cnt <= (OTHERS=>'0');
+ block_size_cnt <= (OTHERS=>'0');
+ i_dp_on_status <= '0';
+ ELSIF rising_edge(clk) THEN
+ prev_state <= state;
+ state <= nxt_state;
+ i_src_out <= nxt_src_out;
+ block_cnt <= nxt_block_cnt;
+ block_size_cnt <= nxt_block_size_cnt;
+ i_dp_on_status <= nxt_dp_on_status;
+ END IF;
+ END PROCESS;
+
+END rtl;
+
+
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bcfaab3c2317d308a54c569f6fe1467cf129062c
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
@@ -0,0 +1,180 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Usage:
+-- > as 10
+-- > run -all
+-- . sop, eop are verified automatically
+-- . sync and bsn are verified automatically
+-- and then manually verify on/off in Wave window
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE dp_lib.tb_dp_pkg.ALL;
+
+ENTITY tb_dp_bsn_source_v2 IS
+END tb_dp_bsn_source_v2;
+
+ARCHITECTURE tb OF tb_dp_bsn_source_v2 IS
+
+ CONSTANT c_clk_period : TIME := 10 ns;
+
+ CONSTANT c_block_size : NATURAL := 31;
+ --CONSTANT c_block_size : NATURAL := 32;
+ CONSTANT c_bsn_w : NATURAL := 16;
+ CONSTANT c_sync_period : NATURAL := 7;
+ CONSTANT c_sync_offset : NATURAL := 3; -- must be < c_sync_period for proc_dp_verify_sync
+
+ -- The state name tells what kind of test is being done
+ TYPE t_state_enum IS (
+ s_disable,
+ s_start,
+ s_pps_start
+ );
+
+ SIGNAL tb_state : t_state_enum;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL rst : STD_LOGIC := '1';
+ SIGNAL clk : STD_LOGIC := '1';
+ SIGNAL pps : STD_LOGIC;
+
+ -- DUT
+ SIGNAL dp_on : STD_LOGIC := '0';
+ SIGNAL dp_on_pps : STD_LOGIC := '0';
+ SIGNAL init_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL bs_sosi : t_dp_sosi;
+
+ -- Verify
+ SIGNAL verify_sync : STD_LOGIC := '1';
+ SIGNAL hold_bs_sop : STD_LOGIC;
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- Stimuli
+ -----------------------------------------------------------------------------
+ rst <= '1', '0' AFTER c_clk_period*7;
+ clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
+
+ -- MM control
+ p_mm : PROCESS
+ BEGIN
+ tb_end <= '0';
+ tb_state <= s_disable;
+ pps <= '0';
+
+ dp_on <= '0';
+ dp_on_pps <= '0';
+ init_bsn <= TO_UVEC(c_sync_offset, c_bsn_w);
+
+ -- Get synchronous to clk
+ proc_common_wait_until_low(clk, rst);
+ proc_common_wait_some_cycles(clk, 500);
+
+ -- Start by making dp_on high
+ tb_state <= s_start;
+ dp_on <= '1';
+ proc_common_wait_some_cycles(clk, 2000);
+
+ -- Stop by making dp_on low
+ tb_state <= s_disable;
+ dp_on <= '0';
+ proc_common_wait_some_cycles(clk, 1000);
+
+ -- Now start on PPS
+ tb_state <= s_pps_start;
+ dp_on_pps <= '1';
+ dp_on <= '1';
+ proc_common_wait_some_cycles(clk, 10);
+ pps <= '1';
+ proc_common_wait_some_cycles(clk, 1);
+ pps <= '0';
+ proc_common_wait_some_cycles(clk, 1000);
+
+ -- Stop by making dp_on low
+ tb_state <= s_disable;
+ dp_on <= '0';
+ dp_on_pps <= '0'; --No PPS trigger next time
+ proc_common_wait_some_cycles(clk, 1000);
+
+ -- Start by making dp_on high
+ tb_state <= s_start;
+ dp_on <= '1';
+ proc_common_wait_some_cycles(clk, 2500);
+
+ -- Stop by making dp_on low
+ tb_state <= s_disable;
+ dp_on <= '0';
+ dp_on_pps <= '0';
+ proc_common_wait_some_cycles(clk, 1000);
+
+ -- Now start on next PPS and continue forever
+ init_bsn <= TO_UVEC(c_sync_offset, c_bsn_w);
+ tb_state <= s_pps_start;
+ dp_on_pps <= '1';
+ dp_on <= '1';
+ proc_common_wait_some_cycles(clk, 20);
+ pps <= '1';
+ proc_common_wait_some_cycles(clk, 1);
+ pps <= '0';
+
+
+ proc_common_wait_some_cycles(clk, 10000);
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+
+ -----------------------------------------------------------------------------
+ -- Verification
+ -----------------------------------------------------------------------------
+ proc_dp_verify_sop_and_eop(clk, bs_sosi.valid, bs_sosi.sop, bs_sosi.eop, hold_bs_sop); -- Verify that sop and eop come in pairs
+ proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_sync, bs_sosi.sync, bs_sosi.sop, bs_sosi.bsn); -- Verify sync at sop and at expected BSN
+
+ -----------------------------------------------------------------------------
+ -- DUT: dp_bsn_source_v2
+ -----------------------------------------------------------------------------
+
+ dut : ENTITY work.dp_bsn_source_v2
+ GENERIC MAP (
+ g_block_size => c_block_size,
+ g_nof_block_per_sync => c_sync_period,
+ g_bsn_w => c_bsn_w
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ pps => pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+ init_bsn => init_bsn,
+ -- Streaming
+ src_out => bs_sosi
+ );
+
+END tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3f4d4428377c192461759f9c0c14aaf9e4938772
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
@@ -0,0 +1,184 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+-- Purpose:
+-- . Test bench for mms_dp_bsn_source
+-- Description:
+-- . Verify DP on, off via MM
+-- . Verify captured BSN via MM during a sync interval
+--
+-- Usage:
+-- > as 10
+-- > run -all
+-- > view expanded bs_sosi in Wave window
+
+LIBRARY IEEE, common_lib, mm_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE work.tb_dp_pkg.ALL;
+
+ENTITY tb_mms_dp_bsn_source_v2 IS
+END tb_mms_dp_bsn_source_v2;
+
+ARCHITECTURE tb OF tb_mms_dp_bsn_source_v2 IS
+
+ CONSTANT c_clk_period : TIME := 10 ns;
+
+ CONSTANT c_pps_interval : NATURAL := 1000;
+ CONSTANT c_cross_clock_domain_latency : NATURAL := 20;
+
+ CONSTANT c_block_size : NATURAL := 100;
+ CONSTANT c_nof_block_per_sync : NATURAL := 15;
+ CONSTANT c_sync_interval : NATURAL := c_nof_block_per_sync * c_block_size;
+ CONSTANT c_init_bsn : NATURAL := c_nof_block_per_sync;
+
+ CONSTANT c_mm_addr_dp_on : NATURAL := 0;
+ CONSTANT c_mm_addr_nof_block_per_sync : NATURAL := 1;
+ CONSTANT c_mm_addr_bsn_lo : NATURAL := 2;
+ CONSTANT c_mm_addr_bsn_hi : NATURAL := 3;
+
+ CONSTANT c_mm_dp_off : NATURAL := 0; -- DP off after finishing current block
+ CONSTANT c_mm_dp_on_immediate : NATURAL := 1; -- DP on immediate by setting bit 0
+ CONSTANT c_mm_dp_on_at_pps : NATURAL := 3; -- DP on at next PPS by setting bits 1,0
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL clk : STD_LOGIC := '1';
+ SIGNAL rst : STD_LOGIC := '1';
+ SIGNAL pps : STD_LOGIC := '0';
+
+ SIGNAL bs_sosi : t_dp_sosi;
+
+ SIGNAL mm_dp_on_status : NATURAL;
+ SIGNAL mm_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL mm_bsn_prev : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL mm_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL mm_miso : t_mem_miso;
+
+BEGIN
+
+ clk <= (NOT clk) OR tb_end AFTER clk_period/2;
+ rst <= '1', '0' AFTER clk_period*7;
+
+ proc_common_gen_pulse(1, c_pps_interval, '1', rst, clk, pps);
+
+ p_mm_stimuli : PROCESS
+ BEGIN
+ WAIT UNTIL rst='0';
+ proc_common_wait_some_cycles(clk, 10);
+
+ -- Write initial BSN and number of block per sync interval
+ proc_mem_mm_bus_wr(c_mm_addr_bsn_lo, c_init_bsn, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_wr(c_mm_addr_bsn_hi, 0, clk, mm_miso, mm_mosi); -- must also write hi part to trigger transfer accross clock domain
+ proc_mem_mm_bus_wr(c_mm_addr_nof_block_per_sync, c_nof_block_per_sync, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
+
+ --------------------------------------------------------------------------
+ -- DP on immediate
+ --------------------------------------------------------------------------
+
+ -- Wait until after PPS
+ proc_common_wait_until_hi_lo(clk, pps);
+
+ -- Write DP on immediate
+ proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_on_immediate, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
+
+ -- Read dp on status
+ proc_mem_mm_bus_rd(c_mm_addr_dp_on, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 DOWNTO 0));
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT mm_dp_on_status=c_mm_dp_on_immediate REPORT "Wrong DP on status, expected DP on immediate." SEVERITY ERROR;
+
+ -- Read BSN twice in same PPS interval
+ proc_common_wait_some_cycles(clk, 3*c_block_size);
+
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(c_word_w-1 DOWNTO 0) <= mm_miso.rddata(c_word_w-1 DOWNTO 0);
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(2*c_word_w-1 DOWNTO c_word_w) <= mm_miso.rddata(c_word_w-1 DOWNTO 0);
+
+ proc_common_wait_some_cycles(clk, c_block_size);
+
+ mm_bsn_prev <= mm_bsn;
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(c_word_w-1 DOWNTO 0) <= mm_miso.rddata(c_word_w-1 DOWNTO 0);
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(2*c_word_w-1 DOWNTO c_word_w) <= mm_miso.rddata(c_word_w-1 DOWNTO 0);
+ proc_common_wait_some_cycles(clk, 1);
+
+ -- Uncomment appropriate assert line dependent on fixed code for capture_bsn in mms_dp_bsn_source:
+ --ASSERT mm_bsn_prev<mm_bsn REPORT "Wrong BSN, expected incrementing BSN during PPS or sync interval." SEVERITY ERROR;
+ ASSERT mm_bsn_prev=mm_bsn REPORT "Wrong BSN, expected constant BSN during PPS or sync interval." SEVERITY ERROR;
+
+ -- Run few sync intervals
+ proc_common_wait_some_cycles(clk, 3*c_sync_interval);
+
+ -- Write DP off
+ proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_off, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, c_block_size);
+
+ -- Read dp on status
+ proc_mem_mm_bus_rd(c_mm_addr_dp_on, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 DOWNTO 0));
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT mm_dp_on_status=c_mm_dp_off REPORT "Wrong DP on status, expected DP off." SEVERITY ERROR;
+
+ proc_common_wait_some_cycles(clk, c_sync_interval);
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ u_dut : ENTITY work.mms_dp_bsn_source
+ GENERIC MAP (
+ g_cross_clock_domain => TRUE, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_block_size => c_block_size,
+ g_nof_block_per_sync => 1, -- overrule via MM write
+ g_bsn_w => c_dp_stream_bsn_w
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+ dp_pps => pps,
+
+ -- Memory-mapped clock domain
+ reg_mosi => mm_mosi, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
+ reg_miso => mm_miso, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi
+ );
+
+END tb;
+