From ca379b66fd3e49fbc4044d4b83eec2523e410f0e Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 1 Oct 2014 09:15:49 +0000
Subject: [PATCH] Made tb self checking and self ending.
---
.../phy_xaui/tb_ip_stratixiv_phy_xaui.vhd | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd b/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
index cfe838a725..8050482ff1 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
+++ b/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
@@ -23,7 +23,7 @@
-- Purpose: Test bench for the MegaWizard-generated ip_stratixiv_phy_xaui_0.
-- Usage:
-- > do wave_tb_ip_stratixiv_phy_xaui.do
--- > run 3 us
+-- > run -all
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -67,6 +67,14 @@ ARCHITECTURE str of tb_ip_stratixiv_phy_xaui IS
BEGIN
+ -- Duration
+ p_tb_end : PROCESS
+ BEGIN
+ WAIT FOR 3 us;
+ ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
+ WAIT;
+ END PROCESS;
+
tr_clk <= NOT tr_clk AFTER c_tr_clk_per/2;
tx_clk <= NOT tx_clk AFTER c_tx_clk_per/2;
mm_clk <= NOT mm_clk AFTER c_mm_clk_per/2;
@@ -95,6 +103,13 @@ BEGIN
WAIT;
END PROCESS;
+ p_xgmii_data_verify : PROCESS
+ BEGIN
+ WAIT FOR 2 us;
+ ASSERT xgmii_rx_d = c_xgmii_d_test REPORT "tb_ip_stratixiv_phy_xaui : Wrong xgmii_rx_d result value" SEVERITY ERROR;
+ WAIT;
+ END PROCESS;
+
-- Combine data and control into XGMII
xgmii_tx_dc <= xgmii_dc(xgmii_tx_d, xgmii_tx_c);
--
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