diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 6af5fab043102e74303bf063f837676da6f99846..ef794a959189c434e132772f00fd16c772b5f3c9 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -87,6 +87,7 @@ ARCHITECTURE str OF ddrctrl IS
CONSTANT c_io_ddr_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- 576
CONSTANT c_wr_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
CONSTANT c_rd_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ CONSTANT c_wr_fifo_uw_w : NATURAL := ceil_log2(c_wr_fifo_depth*(func_tech_ddr_ctlr_data_w(g_tech_ddr)/c_io_ddr_data_w));
CONSTANT c_rd_fifo_uw_w : NATURAL := ceil_log2(c_rd_fifo_depth*(func_tech_ddr_ctlr_data_w(g_tech_ddr)/c_io_ddr_data_w));
CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w(g_tech_ddr); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
@@ -122,10 +123,11 @@ ARCHITECTURE str OF ddrctrl IS
SIGNAL rd_siso : t_dp_siso := c_dp_siso_rst;
SIGNAL rd_sosi : t_dp_sosi := c_dp_sosi_init;
SIGNAL stop : STD_LOGIC;
+ SIGNAL wr_fifo_usedw : STD_LOGIC_VECTOR(c_wr_fifo_uw_w-1 DOWNTO 0);
SIGNAL rd_fifo_usedw : STD_LOGIC_VECTOR(c_rd_fifo_uw_w-1 DOWNTO 0);
SIGNAL rd_ready : STD_LOGIC;
SIGNAL inp_bsn_adr : NATURAL;
- SIGNAL outp_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+ SIGNAL bsn_co : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
SIGNAL data_stopped : STD_LOGIC;
BEGIN
@@ -203,7 +205,7 @@ BEGIN
wr_clk => clk,
wr_rst => rst,
- wr_fifo_usedw => open,
+ wr_fifo_usedw => wr_fifo_usedw,
wr_sosi => wr_sosi,
wr_siso => open,
@@ -244,6 +246,7 @@ BEGIN
rst => rst,
in_sosi => rd_sosi,
+ in_bsn => bsn_co,
out_sosi_arr => out_sosi_arr,
out_ready => rd_ready
@@ -260,6 +263,7 @@ BEGIN
g_rd_fifo_depth => c_rd_fifo_depth,
g_rd_data_w => c_io_ddr_data_w,
g_block_size => g_block_size,
+ g_wr_fifo_uw_w => c_wr_fifo_uw_w,
g_rd_fifo_uw_w => c_rd_fifo_uw_w,
g_max_adr => c_nof_adr,
g_burstsize => g_burstsize,
@@ -283,8 +287,12 @@ BEGIN
dvr_mosi => dvr_mosi,
dvr_miso => dvr_miso,
wr_sosi => wr_sosi,
+ wr_fifo_usedw => wr_fifo_usedw,
rd_fifo_usedw => rd_fifo_usedw,
+ -- ddrctrl_output
+ outp_bsn => bsn_co,
+
-- ddrctrl_controller
stop_in => stop_in,
stop_out => stop
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 3a2b66fd63d8e87508770d7d5902ebff4ec8ae7b..6bb5a508908316af7538db8337fb7635f5522069 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -46,6 +46,7 @@ ENTITY ddrctrl_controller IS
g_rd_fifo_depth : NATURAL; -- 256
g_rd_data_w : NATURAL; -- 256
g_block_size : NATURAL; -- 1024
+ g_wr_fifo_uw_w : NATURAL; -- 8
g_rd_fifo_uw_w : NATURAL; -- 8
g_max_adr : NATURAL; -- 16128
g_burstsize : NATURAL; -- 64
@@ -69,6 +70,7 @@ ENTITY ddrctrl_controller IS
dvr_mosi : OUT t_mem_ctlr_mosi;
dvr_miso : IN t_mem_ctlr_miso;
wr_sosi : OUT t_dp_sosi;
+ wr_fifo_usedw : IN STD_LOGIC_VECTOR(g_wr_fifo_uw_w-1 DOWNTO 0);
rd_fifo_usedw : IN STD_LOGIC_VECTOR(g_rd_fifo_uw_w-1 DOWNTO 0);
-- ddrctrl_output
@@ -93,11 +95,10 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
CONSTANT c_rd_data_w : NATURAL := g_nof_streams*g_out_data_w; -- 168
CONSTANT c_rest : NATURAL := c_rd_data_w-(g_wr_data_w mod c_rd_data_w); -- 96
- CONSTANT c_max_read_cnt : NATURAL := (g_max_adr+1)/g_burstsize; -- 256
CONSTANT c_io_ddr_data_w : NATURAL := func_tech_ddr_ctlr_data_w(g_tech_ddr); -- 576
-- type for statemachine
- TYPE t_state IS (RESET, WRITING, SET_STOP, STOP_WRITING, LAST_WRITE_BURST, START_READING, READING, STOP_READING, IDLE);
+ TYPE t_state IS (RESET, WAIT_FOR_SOP, START_WRITING, WRITING, SET_STOP, STOP_WRITING, LAST_WRITE_BURST, START_READING, READING, STOP_READING, IDLE);
-- record for readability
TYPE t_reg IS RECORD
@@ -114,11 +115,11 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
rst_ddrctrl_input : STD_LOGIC;
-- writing signals
- need_burst : STD_LOGIC;
+ wr_burst_en : STD_LOGIC;
-- reading signals
outp_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
- read_cnt : NATURAL;
+ read_adr : NATURAL;
rd_burst_en : STD_LOGIC;
-- output
@@ -146,7 +147,8 @@ BEGIN
BEGIN
- v := q_reg;
+ v := q_reg;
+ v.wr_sosi := inp_sosi;
CASE q_reg.state IS
@@ -155,18 +157,49 @@ BEGIN
v.dvr_mosi.burstbegin := '1';
v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := (OTHERS => '0');
v.dvr_mosi.wr := '1';
+ v.wr_sosi.valid := '1';
+ WHEN WAIT_FOR_SOP =>
+ v.rst_ddrctrl_input := '0';
+ IF q_reg.started = '0' AND inp_sosi.eop = '1' THEN
+ v.wr_sosi.valid := '1';
+ ELSIF inp_sosi.sop = '1' THEN
+ v.state := WRITING; --START_WRITING;
+ ELSE
+ v.wr_sosi.valid := '0';
+ v.state := WAIT_FOR_SOP;
+ END IF;
+
+
+
+ WHEN START_WRITING =>
+ IF TO_UINT(wr_fifo_usedw) > g_burstsize AND dvr_miso.done = '1' AND v.wr_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
+ v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+q_reg.stop_burstsize, c_adr_w);
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := TO_UVEC(g_burstsize-q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.wr_burst_en := '0';
+ ELSE
+ v.dvr_mosi.burstbegin := '0';
+ END IF;
+
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ IF dvr_miso.done = '0' AND q_reg.wr_burst_en = '0' THEN
+ v.wr_burst_en := '1';
+ v.state := WRITING;
+ ELSE
+ v.state := START_WRITING;
+ END IF;
+
WHEN WRITING =>
-- if adr mod g_burstsize = 0
-- this makes sure that only ones every 64 writes a writeburst is started.
- IF TO_UVEC(inp_adr, c_adr_w)(c_bitshift_w-1 DOWNTO 0) = c_zeros AND q_reg.dvr_mosi.burstbegin = '0'THEN
- v.need_burst := '1';
- END IF;
- IF dvr_miso.done = '1' AND q_reg.need_burst = '1' THEN
+ IF TO_UINT(wr_fifo_usedw) > g_burstsize AND dvr_miso.done = '1' AND q_reg.wr_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
v.dvr_mosi.burstbegin := '1';
- v.need_burst := '0';
+ v.wr_burst_en := '0';
IF inp_adr < g_burstsize-1 THEN
v.dvr_mosi.address := TO_UVEC(g_max_adr-g_last_burstsize, dvr_mosi.address'length);
v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
@@ -180,7 +213,22 @@ BEGIN
END IF;
v.dvr_mosi.wr := '1';
v.dvr_mosi.rd := '0';
- v.wr_sosi := inp_sosi;
+
+ IF TO_UVEC(inp_adr, c_adr_w)(c_bitshift_w-1 DOWNTO 0) = c_zeros AND q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ END IF;
+
+ IF stop_in = '1' THEN
+ v.ready_for_set_stop := '1';
+ END IF;
+
+ IF q_reg.ready_for_set_stop = '1' AND inp_sosi.eop = '1' THEN
+ v.state := SET_STOP;
+ ELSIF q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND q_reg.stopped = '0' THEN
+ v.state := STOP_WRITING;
+ ELSE
+ v.state := WRITING;
+ END IF;
WHEN SET_STOP =>
@@ -190,20 +238,20 @@ BEGIN
ELSE
v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr+c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO 0);
END IF;
- v.ready_for_set_stop := '0';
+ v.ready_for_set_stop := '0';
v.last_adr_to_write_to(c_adr_w-1 DOWNTO c_bitshift_w) := v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_w);
v.last_adr_to_write_to(c_bitshift_w-1 DOWNTO 0) := (OTHERS => '0');
- v.stop_burstsize := TO_UINT(v.stop_adr(c_adr_w-1 DOWNTO 0))-TO_UINT(v.last_adr_to_write_to);
+ v.stop_burstsize := TO_UINT(v.stop_adr(c_adr_w-1 DOWNTO 0))-TO_UINT(v.last_adr_to_write_to)+1;
-- still a write cyle
-- if adr mod g_burstsize = 0
-- this makes sure that only ones every 64 writes a writeburst is started.
IF TO_UVEC(inp_adr, c_adr_w)(c_bitshift_w-1 DOWNTO 0) = c_zeros AND q_reg.dvr_mosi.burstbegin = '0'THEN
- v.need_burst := '1';
+ v.wr_burst_en := '1';
END IF;
- IF dvr_miso.done = '1' AND q_reg.need_burst = '1' THEN
+ IF dvr_miso.done = '1' AND q_reg.wr_burst_en = '1' THEN
v.dvr_mosi.burstbegin := '1';
- v.need_burst := '0';
+ v.wr_burst_en := '0';
IF inp_adr < g_burstsize-1 THEN
v.dvr_mosi.address := TO_UVEC(g_max_adr-g_last_burstsize, dvr_mosi.address'length);
v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
@@ -217,20 +265,26 @@ BEGIN
END IF;
v.dvr_mosi.wr := '1';
v.dvr_mosi.rd := '0';
- v.wr_sosi := inp_sosi;
+
+ IF q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND q_reg.stopped = '0' THEN
+ v.state := STOP_WRITING;
+ ELSE
+ v.state := WRITING;
+ END IF;
+
WHEN STOP_WRITING =>
+ v.wr_sosi.valid := '0';
v.dvr_mosi.burstbegin := '0';
v.stopped := '1';
-- wait until the write burst is finished
IF inp_data_stopped = '0' THEN
v.state := STOP_WRITING;
- ELSIF dvr_miso.done = '1' AND q_reg.dvr_mosi.burstbegin = '0' AND q_reg.need_burst = '0' THEN
- v.wr_sosi.valid := '0';
- v.state := LAST_WRITE_BURST;
+ ELSIF dvr_miso.done = '1' AND q_reg.dvr_mosi.burstbegin = '0' AND q_reg.wr_burst_en = '0' THEN
+ v.state := LAST_WRITE_BURST;
ELSE
- v.state := STOP_WRITING;
+ v.state := STOP_WRITING;
END IF;
@@ -238,11 +292,11 @@ BEGIN
-- if adr mod g_burstsize = 0
-- this makes sure that only ones every 64 writes a writeburst is started.
IF TO_UVEC(inp_adr, c_adr_w)(c_bitshift_w-1 DOWNTO 0) = c_zeros AND q_reg.dvr_mosi.burstbegin = '0'THEN
- v.need_burst := '1';
+ v.wr_burst_en := '1';
END IF;
- IF dvr_miso.done = '1' AND q_reg.need_burst = '1' THEN
+ IF dvr_miso.done = '1' AND q_reg.wr_burst_en = '1' THEN
v.dvr_mosi.burstbegin := '1';
- v.need_burst := '0';
+ v.wr_burst_en := '0';
IF inp_adr < g_burstsize-1 THEN
v.dvr_mosi.address := TO_UVEC(g_max_adr-g_last_burstsize, dvr_mosi.address'length);
v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
@@ -256,7 +310,6 @@ BEGIN
END IF;
v.dvr_mosi.wr := '1';
v.dvr_mosi.rd := '0';
- v.wr_sosi := inp_sosi;
WHEN LAST_WRITE_BURST =>
@@ -266,6 +319,7 @@ BEGIN
v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0);
v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
v.state := START_READING;
+ v.rd_burst_en := '1';
ELSE
v.dvr_mosi.burstbegin := '0';
v.state := LAST_WRITE_BURST;
@@ -277,27 +331,43 @@ BEGIN
WHEN START_READING =>
v.dvr_mosi.burstbegin := '0';
- v.rd_burst_en := '1';
- v.read_cnt := 0;
v.outp_bsn := TO_UVEC(TO_UINT(inp_sosi.bsn)-g_bim, c_dp_stream_bsn_w);
- v.state := READING;
+
+ IF dvr_miso.done = '1' AND v.rd_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := TO_UVEC(g_burstsize-q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+q_reg.stop_burstsize, c_adr_w);
+ v.rd_burst_en := '0';
+ v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+g_burstsize;
+ END IF;
+
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ IF dvr_miso.done = '0' AND q_reg.rd_burst_en = '0' THEN
+ v.rd_burst_en := '1';
+ v.state := READING;
+ ELSE
+ v.state := START_READING;
+ END IF;
WHEN READING =>
-- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
IF TO_UINT(rd_fifo_usedw) <= g_burstsize AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' THEN
- v.dvr_mosi.burstbegin := '0';
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
- IF TO_UINT(q_reg.stop_adr(c_adr_w-1 DOWNTO 0))+g_burstsize*q_reg.read_cnt >= g_max_adr THEN
- v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC((TO_UINT(q_reg.stop_adr(c_adr_w-1 DOWNTO 0))+g_burstsize*q_reg.read_cnt)-g_max_adr-1, c_adr_w);
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.dvr_mosi.burstbegin := '1';
+ v.rd_burst_en := '0';
+ IF q_reg.read_adr > g_max_adr-g_burstsize THEN
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := 0;
ELSE
- v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC(TO_UINT(q_reg.stop_adr(c_adr_w-1 DOWNTO 0))+g_burstsize*q_reg.read_cnt, c_adr_w);
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := q_reg.read_adr+g_burstsize;
END IF;
- v.dvr_mosi.burstbegin := '1';
- v.read_cnt := v.read_cnt+1;
- v.rd_burst_en := '0';
ELSE
v.dvr_mosi.burstbegin := '0';
END IF;
@@ -307,7 +377,8 @@ BEGIN
v.rd_burst_en := '1';
END IF;
- IF q_reg.read_cnt >= c_max_read_cnt THEN
+ -- goes to STOP_reading when this read burst was from the burstblock before q_reg.stop_adr
+ IF q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0) = TO_UVEC(q_reg.read_adr, c_adr_w) THEN
v.state := STOP_READING;
ELSE
v.state := READING;
@@ -316,19 +387,33 @@ BEGIN
WHEN STOP_READING =>
- IF dvr_miso.done = '1' THEN
- v.rst_ddrctrl_input := '0';
- v.stopped := '0';
- v.state := IDLE;
- ELSE
- v.state := STOP_READING;
- END IF;
+ IF TO_UINT(rd_fifo_usedw) <= g_burstsize AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' THEN
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0);
+ v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.stopped := '0';
+ v.wr_sosi.valid := '0';
+ v.state := WAIT_FOR_SOP;
+ v.wr_burst_en := '1';
+ v.rst_ddrctrl_input := '1';
+ ELSE
+ v.dvr_mosi.burstbegin := '0';
+ v.state := STOP_READING;
+ END IF;
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+
+ IF dvr_miso.done = '0' THEN
+ v.rd_burst_en := '1';
+ END IF;
WHEN IDLE =>
- v.wr_sosi.valid := '0';
+ IF q_reg.started = '0' THEN
+ v.wr_sosi.valid := '0';
+ END IF;
-- the statemachine goes to Idle when its finished or when its waiting on other components.
WHEN OTHERS =>
@@ -338,16 +423,17 @@ BEGIN
END CASE;
- IF q_reg.state = RESET OR q_reg.state = WRITING OR q_reg.state = SET_STOP OR q_reg.state = IDLE THEN
+ IF q_reg.state = RESET OR q_reg.state = IDLE THEN
IF stop_in = '1' THEN
v.ready_for_set_stop := '1';
ELSIF q_reg.ready_for_set_stop = '1' AND inp_sosi.eop = '1' THEN
v.state := SET_STOP;
- ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND q_reg.stopped = '0' THEN
+ ELSIF q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND q_reg.stopped = '0' THEN
v.state := STOP_WRITING;
- ELSIF v.stopped = '0' AND inp_sosi.valid = '1' AND q_reg.started = '1' THEN
+ --ELSIF v.stopped = '0' AND inp_sosi.sop = '1' AND q_reg.started = '1' THEN
+ --v.state := START_WRITING;
+ ELSIF v.stopped = '0' AND inp_sosi.valid = '1' AND q_reg.started = '1' THEN
v.state := WRITING;
- v.wr_sosi := inp_sosi;
ELSIF q_reg.stopped = '1' THEN
v.state := STOP_READING;
ELSE
@@ -362,7 +448,6 @@ BEGIN
IF inp_sosi.eop = '1' THEN
v.started := '1';
- v.wr_sosi.valid := '1';
END IF;
d_reg <= v;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
index 1fa66ab59c981b7249f3568a099cde1d3d4c1ba4..874e81e5ea1a12a4dd40c0247d77818f41208549 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
@@ -105,7 +105,7 @@ BEGIN
CASE q_reg.state IS
WHEN RESET =>
- v.s_adr := 0;
+ v := c_t_reg_init;
IF q_reg.s_in_sosi.sop = '1' THEN
v.out_bsn_adr := v.s_adr;
@@ -130,7 +130,7 @@ BEGIN
WHEN IDLE =>
-- after a reset skip the first data block so the ddr memory can initialize.
- IF NOT(q_reg.s_in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN
+ IF in_sosi.sop = '1' THEN
v.bsn_passed := '1';
END IF;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
index 0a429f473357cbb9bc9b43743d335455e1427949..402f27165fff715b993311c756b8a338b95ab917 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
@@ -122,7 +122,7 @@ BEGIN
v.state := FILL_VECTOR;
END IF;
- IF NOT (q_reg.q_bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN
+ IF in_sosi.sop = '1' THEN
v.s_input_cnt := 0;
v.state := BSN;
END IF;
@@ -151,7 +151,7 @@ BEGIN
v.state := FILL_VECTOR;
END IF;
- IF NOT (q_reg.q_bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN
+ IF in_sosi.sop = '1' THEN
v.s_input_cnt := 0;
v.state := BSN;
END IF;
@@ -182,7 +182,7 @@ BEGIN
v.state := FILL_VECTOR;
END IF;
- IF NOT (q_reg.q_bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN
+ IF in_sosi.sop = '1' THEN
v.s_input_cnt := 0;
v.state := BSN;
END IF;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
index edc789a36a3372b9f4a910beb8ecad45f95ef6d2..5bef382784b11c0051abe598b9f594191e3fbab2 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
@@ -52,6 +52,7 @@ ENTITY ddrctrl_output IS
clk : IN STD_LOGIC := '0';
rst : IN STD_LOGIC;
in_sosi : IN t_dp_sosi := c_dp_sosi_init; -- input data
+ in_bsn : IN STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init); -- output data
out_ready : OUT STD_LOGIC
);
@@ -80,6 +81,7 @@ BEGIN
clk => clk,
rst => rst,
in_sosi => in_sosi, -- input data
+ in_bsn => in_bsn,
out_sosi => sosi, -- output data
out_ready => out_ready
);
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
index 9c8555f3ea8561de24a5de65de0aeaf88bd57c69..fd2a2c43425cc68e36961da24a6ec62f21b62065 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
@@ -50,9 +50,11 @@ BEGIN
-- putting the data from the stream into different streams.
gen_repack_data : FOR I IN 0 TO g_nof_streams-1 GENERATE
- out_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= in_sosi.data(g_data_w*(I+1)-1 DOWNTO g_data_w*I);
- out_sosi_arr(I).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
- out_sosi_arr(I).valid <= in_sosi.valid;
+ out_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= in_sosi.data(g_data_w*(I+1)-1 DOWNTO g_data_w*I);
+ out_sosi_arr(I).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
+ out_sosi_arr(I).valid <= in_sosi.valid;
+ out_sosi_arr(I).sop <= in_sosi.sop;
+ out_sosi_arr(I).eop <= in_sosi.eop;
END GENERATE;
END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
index 0951666e6b72fe130b415f6a4226727c7b74df60..64d6caf13618fb20bde78e16fbb0157b899eec0a 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
@@ -48,6 +48,7 @@ ENTITY ddrctrl_output_unpack IS
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
in_sosi : IN t_dp_sosi := c_dp_sosi_init;
+ in_bsn : IN STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
out_sosi : OUT t_dp_sosi := c_dp_sosi_init;
out_ready : OUT STD_LOGIC := '0'
);
@@ -163,7 +164,7 @@ BEGIN
v.dd_fresh := '0';
v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := v.c_v(g_out_data_w+v.a_of-1 DOWNTO v.a_of);
v.out_sosi.valid := '1';
- v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
+ v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := in_bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
IF in_sosi.valid = '1' THEN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 9c0675b7390f6d6e061a3cfd3804a8ad65f9a817..130720661eb7da7403696fe2eeb2bb5e3bfa62c7 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -176,7 +176,7 @@ BEGIN
-- wr fifo has delay of 4 clockcylces after reset
-- filling the input data vectors with the corresponding numbers
- run_multiple_times : FOR K in 0 TO 1 LOOP
+ run_multiple_times : FOR K in 0 TO 2 LOOP
make_data : FOR J IN 0 TO c_bim*g_block_size-1 LOOP
in_data_cnt <= in_data_cnt+1;
fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP