diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_0.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_0.ip
index 88ee131e76d3701461cfe7fa14afedb969fc2d8f..9d833c9bbd75cf233518f1b689f16e57d5500d6c 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_0.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_0.ip
@@ -2125,6 +2125,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_1.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_1.ip
index 2d4e1c0d1340190beb1adf9f8c69f5a3da6de56c..9bcd723f36b325478e699527a5b205027a634d68 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_1.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_1.ip
@@ -2125,6 +2125,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_clk_0.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_clk_0.ip
index a72b58718cac993f98a41be01dcb2605a20f1650..56eac2b8201b6c6a1cb2509d75ea9b8be911f6a9 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_clk_0.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_clk_0.ip
@@ -274,6 +274,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_cpu_0.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_cpu_0.ip
index dea41b38bc641b718fac1d2bbb6205f0567bcf96..ac3313f55aeef617f1f1617096d6c164243bd13f 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_cpu_0.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_cpu_0.ip
@@ -506,7 +506,7 @@
<spirit:parameter>
<spirit:name>isMemoryDevice</spirit:name>
<spirit:displayName>Memory device</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">true</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>isNonVolatileStorage</spirit:name>
@@ -632,7 +632,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
@@ -2208,7 +2208,7 @@
<spirit:parameter>
<spirit:name>instSlaveMapParam</spirit:name>
<spirit:displayName>instSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' type='null.null' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>faSlaveMapParam</spirit:name>
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' type='null.null' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x80' end='0x100' type='null.null' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' type='null.null' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x200' end='0x400' type='null.null' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x400' end='0x500' type='null.null' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x500' end='0x600' type='null.null' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x600' end='0x700' type='null.null' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x700' end='0x800' type='null.null' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' type='null.null' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' type='null.null' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' type='null.null' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' type='null.null' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' type='null.null' datawidth='16' /><slave name='avs_eth_1.mms_reg' start='0x3040' end='0x3080' type='null.null' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x3080' end='0x3100' type='null.null' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x3100' end='0x3180' type='null.null' datawidth='32' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x3180' end='0x3200' type='null.null' datawidth='32' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3200' end='0x3280' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x3280' end='0x32C0' type='null.null' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x32C0' end='0x3300' type='null.null' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3300' end='0x3340' type='null.null' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3340' end='0x3360' type='null.null' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x3360' end='0x3380' type='null.null' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x3380' end='0x33A0' type='null.null' datawidth='32' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x33A0' end='0x33C0' type='null.null' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x33C0' end='0x33E0' type='null.null' datawidth='32' /><slave name='reg_diag_bg_1gbe.mem' start='0x33E0' end='0x3400' type='null.null' datawidth='32' /><slave name='reg_epcs.mem' start='0x3400' end='0x3420' type='null.null' datawidth='32' /><slave name='reg_remu.mem' start='0x3420' end='0x3440' type='null.null' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x3440' end='0x3450' type='null.null' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x3450' end='0x3460' type='null.null' datawidth='32' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x3460' end='0x3470' type='null.null' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3470' end='0x3478' type='null.null' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3478' end='0x3480' type='null.null' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3480' end='0x3488' type='null.null' datawidth='32' /><slave name='pio_pps.mem' start='0x3488' end='0x3490' type='null.null' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3490' end='0x3498' type='null.null' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' type='null.null' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0x4000' end='0x6000' type='null.null' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x6000' end='0x8000' type='null.null' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0x8000' end='0xA000' type='null.null' datawidth='32' /><slave name='ram_diag_bg_1gbe.mem' start='0xA000' end='0xC000' type='null.null' datawidth='32' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0xC000' end='0xE000' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0xE000' end='0xF000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0xF000' end='0x10000' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x10000' end='0x11000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' type='null.null' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' type='null.null' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' type='null.null' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' type='null.null' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' type='null.null' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' type='null.null' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' type='null.null' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' type='null.null' datawidth='32' /><slave name='reg_10gbase_r_24.mem' start='0x5C0000' end='0x5E0000' type='null.null' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x400' end='0x500' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x500' end='0x600' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x600' end='0x700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x700' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x3100' end='0x3180' datawidth='32' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x3180' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3200' end='0x3280' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x3280' end='0x32C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x32C0' end='0x3300' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3300' end='0x3340' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3340' end='0x3360' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x3360' end='0x3380' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x3380' end='0x33A0' datawidth='32' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x33A0' end='0x33C0' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x33C0' end='0x33E0' datawidth='32' /><slave name='reg_diag_bg_1gbe.mem' start='0x33E0' end='0x3400' datawidth='32' /><slave name='reg_epcs.mem' start='0x3400' end='0x3420' datawidth='32' /><slave name='reg_remu.mem' start='0x3420' end='0x3440' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x3440' end='0x3450' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x3450' end='0x3460' datawidth='32' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x3460' end='0x3470' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3470' end='0x3478' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3478' end='0x3480' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3480' end='0x3488' datawidth='32' /><slave name='pio_pps.mem' start='0x3488' end='0x3490' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3490' end='0x3498' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0x4000' end='0x6000' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x6000' end='0x8000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0x8000' end='0xA000' datawidth='32' /><slave name='ram_diag_bg_1gbe.mem' start='0xA000' end='0xC000' datawidth='32' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0xC000' end='0xE000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0xE000' end='0xF000' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0xF000' end='0x10000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x10000' end='0x11000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -2288,27 +2288,27 @@
<spirit:parameter>
<spirit:name>customInstSlavesSystemInfo</spirit:name>
<spirit:displayName>customInstSlavesSystemInfo</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="customInstSlavesSystemInfo"><![CDATA[<info/>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="customInstSlavesSystemInfo"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customInstSlavesSystemInfo_nios_a</spirit:name>
<spirit:displayName>customInstSlavesSystemInfo_nios_a</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="customInstSlavesSystemInfo_nios_a"><![CDATA[<info/>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="customInstSlavesSystemInfo_nios_a"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customInstSlavesSystemInfo_nios_b</spirit:name>
<spirit:displayName>customInstSlavesSystemInfo_nios_b</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="customInstSlavesSystemInfo_nios_b"><![CDATA[<info/>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="customInstSlavesSystemInfo_nios_b"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>customInstSlavesSystemInfo_nios_c</spirit:name>
<spirit:displayName>customInstSlavesSystemInfo_nios_c</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="customInstSlavesSystemInfo_nios_c"><![CDATA[<info/>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="customInstSlavesSystemInfo_nios_c"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFeaturesSystemInfo</spirit:name>
<spirit:displayName>deviceFeaturesSystemInfo</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ALLOW_DIFF_SUFFIX_MIGRATION 0 ASSERT_TIMING_ROUTING_DELAYS_HAS_ALL_EXPECTED_DATA 0 ASSERT_TIMING_ROUTING_DELAYS_NO_AUTOFILL 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DISABLE_CRC_ERROR_DETECTION 0 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_HIGH_SPEED_HSSI 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_BLOCK 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MISSING_PAD_INFO 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QHD_INCREMENTAL_TIMING_CLOSURE_SUPPORT 1 HAS_QHD_IP_REUSE_INTEGRATION_SUPPORT 1 HAS_QHD_PARTITIONS_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_REVC_IO 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMPLIFIED_PARTIAL_RECONFIG_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SIP_TILE_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_DQS_IN_BUFFER_REDUCTION 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 IS_SDM_LITE 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LUTRAM_DATA_IN_FF_MUST_BE_HIPI 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MAC_NEGATE_SUPPORT_DISABLED 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_CLOCK_REGION 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PCF 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 PINTABLE_OPTIONAL 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_PW0 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_MIN_CORNER_DMF_GENERATION 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_TIMING_CLOSURE_CORNERS 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORT_UIB 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 U2B2_SUPPORT_NOT_READY 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DETAILED_REDTAX_WITH_DSPF_ROUTING_MODELS 0 USES_DEV 1 USES_DSPF_ROUTING_MODELS 0 USES_DSP_FROM_PREVIOUS_FAMILY 0 USES_ESTIMATED_TIMING 0 USES_EXTRACTION_CORNERS_WITH_DSPF_ROUTING_MODELS 0 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PARASITIC_LOADS_WITH_DSPF_ROUTING_MODELS 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_RAM_FROM_PREVIOUS_FAMILY 0 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_TIMING_ROUTING_DELAYS 0 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SDM_CONFIGURATION 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WORKS_AROUND_MISSING_RED_FLAGS_IN_DSPF_ROUTING_MODELS 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>AUTO_DEVICE</spirit:name>
@@ -2553,6 +2553,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
@@ -2954,7 +2959,7 @@
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
@@ -3045,7 +3050,7 @@
</entry>
<entry>
<key>isMemoryDevice</key>
- <value>false</value>
+ <value>true</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
@@ -3471,7 +3476,7 @@
<suppliedSystemInfos>
<entry>
<key>CUSTOM_INSTRUCTION_SLAVES</key>
- <value><info/></value>
+ <value></value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
@@ -3484,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x400' end='0x500' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x500' end='0x600' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x600' end='0x700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x700' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x3100' end='0x3180' datawidth='32' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x3180' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3200' end='0x3280' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x3280' end='0x32C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x32C0' end='0x3300' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3300' end='0x3340' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3340' end='0x3360' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x3360' end='0x3380' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x3380' end='0x33A0' datawidth='32' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x33A0' end='0x33C0' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x33C0' end='0x33E0' datawidth='32' /><slave name='reg_diag_bg_1gbe.mem' start='0x33E0' end='0x3400' datawidth='32' /><slave name='reg_epcs.mem' start='0x3400' end='0x3420' datawidth='32' /><slave name='reg_remu.mem' start='0x3420' end='0x3440' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x3440' end='0x3450' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x3450' end='0x3460' datawidth='32' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x3460' end='0x3470' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3470' end='0x3478' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3478' end='0x3480' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3480' end='0x3488' datawidth='32' /><slave name='pio_pps.mem' start='0x3488' end='0x3490' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3490' end='0x3498' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0x4000' end='0x6000' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x6000' end='0x8000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0x8000' end='0xA000' datawidth='32' /><slave name='ram_diag_bg_1gbe.mem' start='0xA000' end='0xC000' datawidth='32' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0xC000' end='0xE000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0xE000' end='0xF000' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0xF000' end='0x10000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x10000' end='0x11000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /><slave name='reg_10gbase_r_24.mem' start='0x5C0000' end='0x5E0000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x400' end='0x500' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x500' end='0x600' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x600' end='0x700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x700' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x3100' end='0x3180' datawidth='32' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x3180' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3200' end='0x3280' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x3280' end='0x32C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x32C0' end='0x3300' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3300' end='0x3340' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3340' end='0x3360' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x3360' end='0x3380' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x3380' end='0x33A0' datawidth='32' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x33A0' end='0x33C0' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x33C0' end='0x33E0' datawidth='32' /><slave name='reg_diag_bg_1gbe.mem' start='0x33E0' end='0x3400' datawidth='32' /><slave name='reg_epcs.mem' start='0x3400' end='0x3420' datawidth='32' /><slave name='reg_remu.mem' start='0x3420' end='0x3440' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x3440' end='0x3450' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x3450' end='0x3460' datawidth='32' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x3460' end='0x3470' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3470' end='0x3478' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3478' end='0x3480' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3480' end='0x3488' datawidth='32' /><slave name='pio_pps.mem' start='0x3488' end='0x3490' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3490' end='0x3498' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0x4000' end='0x6000' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x6000' end='0x8000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0x8000' end='0xA000' datawidth='32' /><slave name='ram_diag_bg_1gbe.mem' start='0xA000' end='0xC000' datawidth='32' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0xC000' end='0xE000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0xE000' end='0xF000' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0xF000' end='0x10000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x10000' end='0x11000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_jtag_uart_0.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_jtag_uart_0.ip
index 4dc9cb2a0e6047d66bb4e58103c1cfde7d59c618..d8583bc15e0636ef9b87af8b2daa85ee6ff6c4f8 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_jtag_uart_0.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_jtag_uart_0.ip
@@ -690,6 +690,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_onchip_memory2_0.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_onchip_memory2_0.ip
index 823cfa4db1a0fd997069e4548742792da24127f5..e7f597e5f2e46eb79f45a912d651d9d834d11b66 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_onchip_memory2_0.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_onchip_memory2_0.ip
@@ -662,7 +662,7 @@
<spirit:parameter>
<spirit:name>deviceFeatures</spirit:name>
<spirit:displayName>deviceFeatures</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ALLOW_DIFF_SUFFIX_MIGRATION 0 ASSERT_TIMING_ROUTING_DELAYS_HAS_ALL_EXPECTED_DATA 0 ASSERT_TIMING_ROUTING_DELAYS_NO_AUTOFILL 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DISABLE_CRC_ERROR_DETECTION 0 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_HIGH_SPEED_HSSI 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_BLOCK 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MISSING_PAD_INFO 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QHD_INCREMENTAL_TIMING_CLOSURE_SUPPORT 1 HAS_QHD_IP_REUSE_INTEGRATION_SUPPORT 1 HAS_QHD_PARTITIONS_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_REVC_IO 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMPLIFIED_PARTIAL_RECONFIG_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SIP_TILE_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_DQS_IN_BUFFER_REDUCTION 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 IS_SDM_LITE 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LUTRAM_DATA_IN_FF_MUST_BE_HIPI 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MAC_NEGATE_SUPPORT_DISABLED 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_CLOCK_REGION 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PCF 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 PINTABLE_OPTIONAL 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_PW0 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_MIN_CORNER_DMF_GENERATION 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_TIMING_CLOSURE_CORNERS 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORT_UIB 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 U2B2_SUPPORT_NOT_READY 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DETAILED_REDTAX_WITH_DSPF_ROUTING_MODELS 0 USES_DEV 1 USES_DSPF_ROUTING_MODELS 0 USES_DSP_FROM_PREVIOUS_FAMILY 0 USES_ESTIMATED_TIMING 0 USES_EXTRACTION_CORNERS_WITH_DSPF_ROUTING_MODELS 0 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PARASITIC_LOADS_WITH_DSPF_ROUTING_MODELS 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_RAM_FROM_PREVIOUS_FAMILY 0 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_TIMING_ROUTING_DELAYS 0 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SDM_CONFIGURATION 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WORKS_AROUND_MISSING_RED_FLAGS_IN_DSPF_ROUTING_MODELS 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>derived_set_addr_width</spirit:name>
@@ -818,6 +818,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_pio_pps.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_pio_pps.ip
index a57f49a2e617418a93892b9376c336e705c5ca21..61a13d68b6686d9e4c55440de7e717e0b087275c 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_pio_pps.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_pio_pps.ip
@@ -806,6 +806,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_pio_system_info.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_pio_system_info.ip
index 7aa8b3f2eab5d008e8437478e9b91ede108e476b..120a3d814ada8fca71c2b06fa72845474231feeb 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_pio_system_info.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_pio_system_info.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_pio_wdi.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_pio_wdi.ip
index da19d28baa462249711ffac0b2a14dda814f15ba..41b8fcc985d7146ef6b2e06a360f723f8ae6456a 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_pio_wdi.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_pio_wdi.ip
@@ -703,6 +703,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_10gbe.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_10gbe.ip
index aeb50161109580fdd8cfdbddaea6627dc8146935..61fd6d325b96c701e9afe65ea57f6e31c9d88023 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_10gbe.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_10gbe.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_1gbe.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_1gbe.ip
index 5add2952f9d3ce78ddf7ac94448868dcba1e686b..f6be3b7b4bd061fda9df286a7544f05a5b20a865 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_1gbe.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_1gbe.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_10gbe.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_10gbe.ip
index f9ad205117c03bda238332e8681b762c64520f0c..6d6e7f011abd7850165e8884dc28fa102be942dd 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_10gbe.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_10gbe.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_1gbe.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_1gbe.ip
index ca60364930bc74aa3f80bd99ef16034b88a9ca65..f1c3baffaea033bbe7c283e06705673b012766bc 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_1gbe.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_1gbe.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_I.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_I.ip
index 0481df068ef6e479afd130dab55e1e176452aeb8..19525e32995228c9cf3336239770dedc94277cc6 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_I.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_I.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_II.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_II.ip
index 647012e38be88e0ad55cdab76cd2646267dfdfcd..27bc9235c6c3d277f607c60118dfcbf82a6a86d4 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_II.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_II.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_10GbE.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_10GbE.ip
index 2c85e993312331dd38f2b06f14342928b1b206eb..ca45bb9ee3dee8011659cb24db6365ae26461c44 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_10GbE.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_10GbE.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_1GbE.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_1GbE.ip
index 6235f41e9b37f0a09add96476a3b3e02d4f9972a..c9d2f5ee95fbb38a43848b5e5eeff14cb50b6f4a 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_1GbE.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_1GbE.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_10gbe.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_10gbe.ip
index b90824c8c22fa87bef14bae4dd4424e344c45a9a..3e0903efbd45269ba853853745e9cbacc6537f20 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_10gbe.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_10gbe.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_1gbe.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_1gbe.ip
index e8c5f9c02ac43c86ff2c5e7778c662a5c89d5003..41e1c10ff462111ec12a8d0ee2a6a2abe060c59c 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_1gbe.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_1gbe.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_10gbe.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_10gbe.ip
index 892555c8887a65bae352873ad3f167c936743dc5..6ef3d8717f7b78d960548b0bdc0a8e6b49e65e9d 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_10gbe.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_10gbe.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_1gbe.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_1gbe.ip
index d0d8775619c781394baa8cdb2d479fdba9ba707f..f549be34a2bb4272056b7664f62de5c4c8a111e9 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_1gbe.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_1gbe.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I.ip
index 653bc4e5262217bf325d9e751ceb64ce78cbb053..936e9538e3747e32109a386d39dac5cf5a8df95e 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II.ip
index ff8afd6265ec9908f729354e370db644e551dc1b..f883ac3d33914e6f7fde6f4e3615939038071373 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_10gbe.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_10gbe.ip
index e8af12da7d6562136bcb45466cc44a1496412cca..8c5b7f05caed9bc15f2d3ac8ee5dd9259db72d48 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_10gbe.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_10gbe.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_1gbe.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_1gbe.ip
index a02406163b4dea24f352e281ffef6c9837abe1db..b1bddf43c9a62010af7a5f7dad10ae6a8c711c2c 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_1gbe.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_1gbe.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I.ip
index 709053c4ed0bcc4858de269fd79eb5c09a2fff93..60ddf9dc602e6eb4cca741d0bbce1e5a73c22521 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II.ip
index bf442cd0022abc34dec01da972a3f4d6c964f0a4..ee504ce8159d78fbe96ab1c2029628527000fdf1 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_10gbe.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_10gbe.ip
index ad6e1f27662723acecdc45e1c7821de8d40d76d4..da84bcf9f78eede7f87ab1b8b86b2bd306f71893 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_10gbe.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_10gbe.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_1gbe.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_1gbe.ip
index 34b62a5693e6d87f4953243ade5ef0d84bcc8b11..e25c707a521fec0a2bbb7a2ee026f3fdcdc6fe56 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_1gbe.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_1gbe.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I.ip
index 8a6196dc94e7b4223d001146afb62d5262e45be1..a73c120cb5aa2c762459495047ebdbc6bfd7562a 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II.ip
index de52f77058ef825967e2e9f539f50ff5b6965c05..23a0a85be5ad21c70daa336142ed533225d46f07 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_ctrl.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_ctrl.ip
index 56d417a008e0a61f47a1560021b50cf8b7202667..55744f9cf1280e80e0f2eb07136df3d9d8f52c9b 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_ctrl.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_ctrl.ip
@@ -806,6 +806,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_data.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_data.ip
index be4da6e7dc671ebd291fae5e2a200ddb3ecb124f..60e8060ffe6705b8d66dd8a271b0ecdc3f4a8239 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_data.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_data.ip
@@ -806,6 +806,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_epcs.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_epcs.ip
index 36e3af0cba3eaa151860c2df53f00cf5a295f2b2..ae1cff3cff4513cd9e068eba7ef514ae411ce108 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_epcs.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_epcs.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back0.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back0.ip
index 055eefdeded821f3ae0e33f442743816bd7a607a..6390363d8b1196eb0d24c100eb2b37357fc40e49 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back0.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back0.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back1.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back1.ip
index 705c0486a1ccd0f325039a3b48ef6bb04ee6599d..53fad72b556b54e6ef571858e4046ed9f9982819 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back1.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back1.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_qsfp_ring.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_qsfp_ring.ip
index d3e27e841d0e52e49d38bb6e4654db2e4dd11309..50fcdc610786cfab1fa2da52eb74940d4f84dc1d 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_qsfp_ring.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_qsfp_ring.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_temp_sens.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_temp_sens.ip
index 6cc6189a17616e34fc22b635dfdc5eb214c18ec2..d410dc8a907e3bc8fc413a3732d67f9f9a40f48d 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_temp_sens.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_temp_sens.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_voltage_sens.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_voltage_sens.ip
index abce99fce5534742e1a11b5080fc784fdf4fd025..46dbabec01bebdd76f83402f79977ae03708d0c4 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_voltage_sens.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_voltage_sens.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_I.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_I.ip
index 3d496821ee2f6823d6ed15da24ca2ca7cf01868f..14baa8909cf1664fb377f12b5244c7210937d4a1 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_I.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_I.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_II.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_II.ip
index 29cefe3e389c389bf0a2e08d65f14711f2d6a931..e4643c3c483100fd395bbf5e1cabe3448e95234c 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_II.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_II.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
deleted file mode 100644
index fe5ee80b5d657b85bb014251aabcf4362b35e3b6..0000000000000000000000000000000000000000
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
+++ /dev/null
@@ -1,1550 +0,0 @@
-<?xml version="1.0" ?>
-<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
- <spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2b_test_reg_ip_arria10_e1sg_phy_10gbase_r_24</spirit:library>
- <spirit:name>reg_ip_arria10_e3sge3_phy_10gbase_r_24</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>address</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_address_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>clk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_clk_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>mem</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>address</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_address</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>write</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_write</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>writedata</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_writedata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>read</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_read</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>readdata</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_readdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>waitrequest</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_waitrequest</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>addressAlignment</spirit:name>
- <spirit:displayName>Slave addressing</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressGroup</spirit:name>
- <spirit:displayName>Address group</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressSpan</spirit:name>
- <spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">131072</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressUnits</spirit:name>
- <spirit:displayName>Address units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>alwaysBurstMaxBurst</spirit:name>
- <spirit:displayName>Always burst maximum burst</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>Associated reset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bitsPerSymbol</spirit:name>
- <spirit:displayName>Bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bridgedAddressOffset</spirit:name>
- <spirit:displayName>Bridged Address Offset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bridgesToMaster</spirit:name>
- <spirit:displayName>Bridges to master</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
- <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>burstcountUnits</spirit:name>
- <spirit:displayName>Burstcount units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>constantBurstBehavior</spirit:name>
- <spirit:displayName>Constant burst behavior</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>explicitAddressSpan</spirit:name>
- <spirit:displayName>Explicit address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>holdTime</spirit:name>
- <spirit:displayName>Hold</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>interleaveBursts</spirit:name>
- <spirit:displayName>Interleave bursts</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isBigEndian</spirit:name>
- <spirit:displayName>Big endian</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isFlash</spirit:name>
- <spirit:displayName>Flash memory</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isMemoryDevice</spirit:name>
- <spirit:displayName>Memory device</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isNonVolatileStorage</spirit:name>
- <spirit:displayName>Non-volatile storage</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>linewrapBursts</spirit:name>
- <spirit:displayName>Linewrap bursts</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maximumPendingReadTransactions</spirit:name>
- <spirit:displayName>Maximum pending read transactions</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maximumPendingWriteTransactions</spirit:name>
- <spirit:displayName>Maximum pending write transactions</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumReadLatency</spirit:name>
- <spirit:displayName>minimumReadLatency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumResponseLatency</spirit:name>
- <spirit:displayName>Minimum response latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumUninterruptedRunLength</spirit:name>
- <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>printableDevice</spirit:name>
- <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readLatency</spirit:name>
- <spirit:displayName>Read latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readWaitStates</spirit:name>
- <spirit:displayName>Read wait states</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readWaitStates">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readWaitTime</spirit:name>
- <spirit:displayName>Read wait</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>registerIncomingSignals</spirit:name>
- <spirit:displayName>Register incoming signals</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>registerOutgoingSignals</spirit:name>
- <spirit:displayName>Register outgoing signals</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>setupTime</spirit:name>
- <spirit:displayName>Setup</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>timingUnits</spirit:name>
- <spirit:displayName>Timing units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>transparentBridge</spirit:name>
- <spirit:displayName>Transparent bridge</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>waitrequestAllowance</spirit:name>
- <spirit:displayName>Waitrequest allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>wellBehavedWaitrequest</spirit:name>
- <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeLatency</spirit:name>
- <spirit:displayName>Write latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeWaitStates</spirit:name>
- <spirit:displayName>Write wait states</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeWaitTime</spirit:name>
- <spirit:displayName>Write wait</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <altera:altera_assignments>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_assignments>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>read</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_read_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>readdata</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_readdata_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_reset_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>system</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>clk</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>csi_system_clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>clockRate</spirit:name>
- <spirit:displayName>Clock rate</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>externallyDriven</spirit:name>
- <spirit:displayName>Externally driven</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ptfSchematicName</spirit:name>
- <spirit:displayName>PTF schematic name</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>system_reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>reset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>csi_system_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>synchronousEdges</spirit:name>
- <spirit:displayName>Synchronous edges</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>waitrequest</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_waitrequest_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>write</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_write_export</spirit:name>
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- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
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- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>writedata</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_writedata_export</spirit:name>
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- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
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- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
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- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
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- <spirit:name>QUARTUS_SYNTH</spirit:name>
- <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
- <spirit:modelName>avs_common_mm_readlatency0</spirit:modelName>
- <spirit:fileSetRef>
- <spirit:localName>QUARTUS_SYNTH</spirit:localName>
- </spirit:fileSetRef>
- </spirit:view>
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- <spirit:ports>
- <spirit:port>
- <spirit:name>csi_system_clk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
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- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
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- <spirit:name>csi_system_reset</spirit:name>
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- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
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- <spirit:port>
- <spirit:name>avs_mem_address</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
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- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
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- <spirit:name>avs_mem_write</spirit:name>
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- <spirit:name>avs_mem_writedata</spirit:name>
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- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
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- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
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- <spirit:name>avs_mem_readdata</spirit:name>
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- <spirit:port>
- <spirit:name>coe_address_export</spirit:name>
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- <spirit:left>0</spirit:left>
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- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
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- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
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- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_read_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_readdata_export</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_waitrequest_export</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- </spirit:model>
- <spirit:vendorExtensions>
- <altera:entity_info>
- <spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_unb2b_test_reg_ip_arria10_e1sg_phy_10gbase_r_24</spirit:library>
- <spirit:name>avs_common_mm_readlatency0</spirit:name>
- <spirit:version>1.0</spirit:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>g_adr_w</spirit:name>
- <spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">15</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>g_dat_w</spirit:name>
- <spirit:displayName>g_dat_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
- <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">125000000</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>device</spirit:name>
- <spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceFamily</spirit:name>
- <spirit:displayName>Device family</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceSpeedGrade</spirit:name>
- <spirit:displayName>Device Speed Grade</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bonusData</spirit:name>
- <spirit:displayName>bonusData</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
-{
-}
-</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>hideFromIPCatalog</spirit:name>
- <spirit:displayName>Hide from IP Catalog</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>lockedInterfaceDefinition</spirit:name>
- <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>15</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>15</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>131072</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>waitrequest</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_waitrequest_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>systemInfos</spirit:name>
- <spirit:displayName>systemInfos</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>17</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>125000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition>]]></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="reg_ip_arria10_e3sge3_phy_10gbase_r_24.address" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="reg_ip_arria10_e3sge3_phy_10gbase_r_24.clk" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="reg_ip_arria10_e3sge3_phy_10gbase_r_24.mem" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_waitrequest" altera:internal="avs_mem_waitrequest"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="reg_ip_arria10_e3sge3_phy_10gbase_r_24.read" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="reg_ip_arria10_e3sge3_phy_10gbase_r_24.readdata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="reg_ip_arria10_e3sge3_phy_10gbase_r_24.reset" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="reg_ip_arria10_e3sge3_phy_10gbase_r_24.system" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="reg_ip_arria10_e3sge3_phy_10gbase_r_24.system_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="waitrequest" altera:internal="reg_ip_arria10_e3sge3_phy_10gbase_r_24.waitrequest" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_waitrequest_export" altera:internal="coe_waitrequest_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="reg_ip_arria10_e3sge3_phy_10gbase_r_24.write" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="reg_ip_arria10_e3sge3_phy_10gbase_r_24.writedata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </spirit:vendorExtensions>
-</spirit:component>
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_ctrl.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_ctrl.ip
index 83846cb12295e07a5502cbc322711940a52a77ed..df81b777c113206294180c040858f3184ce96161 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_ctrl.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_ctrl.ip
@@ -806,6 +806,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_data.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_data.ip
index 7e344b2358dbc792b6402eceec040d7d8fafb8c2..33c4a5d944b82a4d89a16d40f9b8f02c79e0fa7d 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_data.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_data.ip
@@ -806,6 +806,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_remu.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_remu.ip
index d361821ea1390061439bb1595509e47da642c34b..20a782f36ee391307944b07c127f1c08f5884683 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_remu.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_remu.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back0.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back0.ip
index 9f49b1c9393c9e6643a3aa8c9f48087f25adf561..f449861f3d79d109b15166858db8e55c1cc50804 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back0.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back0.ip
@@ -878,6 +878,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back1.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back1.ip
index 515f3a6327eee734ef1e0d4312313e6b86ad7c92..38c0671a8194e8e0b2b1f2eaa6e555b6c4257f86 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back1.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back1.ip
@@ -878,6 +878,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_qsfp_ring.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_qsfp_ring.ip
index 272fe13b4f1efc377e84363e4a5bc67715a821ae..2ab98aedb94eee22740a4f693efa3cfacec83eaa 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_qsfp_ring.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_qsfp_ring.ip
@@ -878,6 +878,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_pmbus.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_pmbus.ip
index 251c44223915b795003044638b3ec32879d30d1c..b3ce8291ff41b4256c843506461626ca251c43ba 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_pmbus.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_pmbus.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_sens.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_sens.ip
index 139cadc2b1f1771ee6ed0efc7641800f7c6baf66..dce3574d76987e24a464b1e846336a55be4bc56b 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_sens.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_sens.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_wdi.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_wdi.ip
index 2edeacd0d0453c27ecc9caddbe73620dc1105dc4..4d58047ed7a9b1f0415278fb68a3e12a154b7693 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_wdi.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_reg_wdi.ip
@@ -806,6 +806,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_rom_system_info.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_rom_system_info.ip
index 4a419b6b0f9aa4ebc6aea81605c1e929c54f73f4..513555582b79a3d5d0b991f2baf1c6c6cf2f8930 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_rom_system_info.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_rom_system_info.ip
@@ -814,6 +814,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_timer_0.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_timer_0.ip
index 06caf60416b7b34b0cc99733605c25aadbbe42b7..56cdd88e306b512f656e1dcbcd0d00fba0323532 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_timer_0.ip
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/qsys_unb2b_test_timer_0.ip
@@ -683,6 +683,11 @@
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/reg_10gbase_r_24.ip b/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/reg_10gbase_r_24.ip
deleted file mode 100644
index ca830213547ce49bab58f4db789b2553ce048b3f..0000000000000000000000000000000000000000
--- a/boards/uniboard2b/designs/unb2b_test/quartus/ip/qsys_unb2b_test/reg_10gbase_r_24.ip
+++ /dev/null
@@ -1,1550 +0,0 @@
-<?xml version="1.0" ?>
-<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
- <spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>reg_10gbase_r_24</spirit:library>
- <spirit:name>reg_10gbase_r_24</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>address</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_address_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>clk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_clk_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>mem</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>address</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_address</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>write</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_write</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>writedata</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_writedata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>read</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_read</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>readdata</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_readdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>waitrequest</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_waitrequest</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>addressAlignment</spirit:name>
- <spirit:displayName>Slave addressing</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressGroup</spirit:name>
- <spirit:displayName>Address group</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressSpan</spirit:name>
- <spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">131072</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressUnits</spirit:name>
- <spirit:displayName>Address units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>alwaysBurstMaxBurst</spirit:name>
- <spirit:displayName>Always burst maximum burst</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>Associated reset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bitsPerSymbol</spirit:name>
- <spirit:displayName>Bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bridgedAddressOffset</spirit:name>
- <spirit:displayName>Bridged Address Offset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bridgesToMaster</spirit:name>
- <spirit:displayName>Bridges to master</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
- <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>burstcountUnits</spirit:name>
- <spirit:displayName>Burstcount units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>constantBurstBehavior</spirit:name>
- <spirit:displayName>Constant burst behavior</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>explicitAddressSpan</spirit:name>
- <spirit:displayName>Explicit address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>holdTime</spirit:name>
- <spirit:displayName>Hold</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>interleaveBursts</spirit:name>
- <spirit:displayName>Interleave bursts</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isBigEndian</spirit:name>
- <spirit:displayName>Big endian</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isFlash</spirit:name>
- <spirit:displayName>Flash memory</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isMemoryDevice</spirit:name>
- <spirit:displayName>Memory device</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isNonVolatileStorage</spirit:name>
- <spirit:displayName>Non-volatile storage</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>linewrapBursts</spirit:name>
- <spirit:displayName>Linewrap bursts</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maximumPendingReadTransactions</spirit:name>
- <spirit:displayName>Maximum pending read transactions</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maximumPendingWriteTransactions</spirit:name>
- <spirit:displayName>Maximum pending write transactions</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumReadLatency</spirit:name>
- <spirit:displayName>minimumReadLatency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumResponseLatency</spirit:name>
- <spirit:displayName>Minimum response latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumUninterruptedRunLength</spirit:name>
- <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>printableDevice</spirit:name>
- <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readLatency</spirit:name>
- <spirit:displayName>Read latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readWaitStates</spirit:name>
- <spirit:displayName>Read wait states</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readWaitStates">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readWaitTime</spirit:name>
- <spirit:displayName>Read wait</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>registerIncomingSignals</spirit:name>
- <spirit:displayName>Register incoming signals</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>registerOutgoingSignals</spirit:name>
- <spirit:displayName>Register outgoing signals</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>setupTime</spirit:name>
- <spirit:displayName>Setup</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>timingUnits</spirit:name>
- <spirit:displayName>Timing units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>transparentBridge</spirit:name>
- <spirit:displayName>Transparent bridge</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>waitrequestAllowance</spirit:name>
- <spirit:displayName>Waitrequest allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>wellBehavedWaitrequest</spirit:name>
- <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeLatency</spirit:name>
- <spirit:displayName>Write latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeWaitStates</spirit:name>
- <spirit:displayName>Write wait states</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeWaitTime</spirit:name>
- <spirit:displayName>Write wait</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <altera:altera_assignments>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_assignments>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>read</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_read_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>readdata</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_readdata_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_reset_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>system</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>clk</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>csi_system_clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>clockRate</spirit:name>
- <spirit:displayName>Clock rate</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>externallyDriven</spirit:name>
- <spirit:displayName>Externally driven</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ptfSchematicName</spirit:name>
- <spirit:displayName>PTF schematic name</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>system_reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>reset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>csi_system_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>synchronousEdges</spirit:name>
- <spirit:displayName>Synchronous edges</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>waitrequest</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_waitrequest_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>write</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_write_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>writedata</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_writedata_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- </spirit:busInterfaces>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>QUARTUS_SYNTH</spirit:name>
- <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
- <spirit:modelName>avs_common_mm_readlatency0</spirit:modelName>
- <spirit:fileSetRef>
- <spirit:localName>QUARTUS_SYNTH</spirit:localName>
- </spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>csi_system_clk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>csi_system_reset</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_address</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>14</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_write</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_writedata</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_read</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_readdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_waitrequest</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_reset_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_clk_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_address_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>14</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_write_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_writedata_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_read_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_readdata_export</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_waitrequest_export</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- </spirit:model>
- <spirit:vendorExtensions>
- <altera:entity_info>
- <spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>reg_10gbase_r_24</spirit:library>
- <spirit:name>avs_common_mm_readlatency0</spirit:name>
- <spirit:version>1.0</spirit:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>g_adr_w</spirit:name>
- <spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">15</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>g_dat_w</spirit:name>
- <spirit:displayName>g_dat_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
- <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">125000000</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>device</spirit:name>
- <spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceFamily</spirit:name>
- <spirit:displayName>Device family</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceSpeedGrade</spirit:name>
- <spirit:displayName>Device Speed Grade</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bonusData</spirit:name>
- <spirit:displayName>bonusData</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
-{
-}
-</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>hideFromIPCatalog</spirit:name>
- <spirit:displayName>Hide from IP Catalog</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>lockedInterfaceDefinition</spirit:name>
- <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>15</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>15</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>131072</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>1</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>waitrequest</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_waitrequest_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>systemInfos</spirit:name>
- <spirit:displayName>systemInfos</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>17</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>125000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition>]]></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="reg_10gbase_r_24.address" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="reg_10gbase_r_24.clk" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="reg_10gbase_r_24.mem" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_waitrequest" altera:internal="avs_mem_waitrequest"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="reg_10gbase_r_24.read" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="reg_10gbase_r_24.readdata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="reg_10gbase_r_24.reset" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="reg_10gbase_r_24.system" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="reg_10gbase_r_24.system_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="waitrequest" altera:internal="reg_10gbase_r_24.waitrequest" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_waitrequest_export" altera:internal="coe_waitrequest_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="reg_10gbase_r_24.write" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="reg_10gbase_r_24.writedata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </spirit:vendorExtensions>
-</spirit:component>
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/qsys_unb2b_test.qsys b/boards/uniboard2b/designs/unb2b_test/quartus/qsys_unb2b_test.qsys
index 80942e540909a367ecc7fad2e013c7c933582bad..b8574aaeed6143f89421a4b07b3f805fbc2901bf 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/qsys_unb2b_test.qsys
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/qsys_unb2b_test.qsys
@@ -303,22 +303,6 @@
type = "String";
}
}
- element reg_10gbase_r_24
- {
- datum _sortIndex
- {
- value = "52";
- type = "int";
- }
- }
- element reg_10gbase_r_24.mem
- {
- datum baseAddress
- {
- value = "6029312";
- type = "String";
- }
- }
element reg_bsn_monitor_10GbE
{
datum _sortIndex
@@ -1438,46 +1422,6 @@
internal="ram_diag_data_buffer_ddr_MB_II.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_10gbase_r_24_address"
- internal="reg_10gbase_r_24.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_10gbase_r_24_clk"
- internal="reg_10gbase_r_24.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_10gbase_r_24_read"
- internal="reg_10gbase_r_24.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_10gbase_r_24_readdata"
- internal="reg_10gbase_r_24.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_10gbase_r_24_reset"
- internal="reg_10gbase_r_24.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_10gbase_r_24_waitrequest"
- internal="reg_10gbase_r_24.waitrequest"
- type="conduit"
- dir="end" />
- <interface
- name="reg_10gbase_r_24_write"
- internal="reg_10gbase_r_24.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_10gbase_r_24_writedata"
- internal="reg_10gbase_r_24.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_bsn_monitor_10gbe_address"
internal="reg_bsn_monitor_10GbE.address"
@@ -4278,6 +4222,7 @@
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="avs_eth_1"
@@ -5819,6 +5764,7 @@
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="clk_0"
@@ -6054,6 +6000,7 @@
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="cpu_0"
@@ -6446,7 +6393,7 @@
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
@@ -6537,7 +6484,7 @@
</entry>
<entry>
<key>isMemoryDevice</key>
- <value>false</value>
+ <value>true</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
@@ -7231,7 +7178,7 @@
<consumedSystemInfos>
<entry>
<key>CUSTOM_INSTRUCTION_SLAVES</key>
- <value><info/></value>
+ <value></value>
</entry>
</consumedSystemInfos>
</value>
@@ -7244,7 +7191,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x400' end='0x500' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x500' end='0x600' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x600' end='0x700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x700' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x3100' end='0x3180' datawidth='32' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x3180' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3200' end='0x3280' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x3280' end='0x32C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x32C0' end='0x3300' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3300' end='0x3340' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3340' end='0x3360' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x3360' end='0x3380' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x3380' end='0x33A0' datawidth='32' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x33A0' end='0x33C0' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x33C0' end='0x33E0' datawidth='32' /><slave name='reg_diag_bg_1gbe.mem' start='0x33E0' end='0x3400' datawidth='32' /><slave name='reg_epcs.mem' start='0x3400' end='0x3420' datawidth='32' /><slave name='reg_remu.mem' start='0x3420' end='0x3440' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x3440' end='0x3450' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x3450' end='0x3460' datawidth='32' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x3460' end='0x3470' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3470' end='0x3478' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3478' end='0x3480' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3480' end='0x3488' datawidth='32' /><slave name='pio_pps.mem' start='0x3488' end='0x3490' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3490' end='0x3498' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0x4000' end='0x6000' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x6000' end='0x8000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0x8000' end='0xA000' datawidth='32' /><slave name='ram_diag_bg_1gbe.mem' start='0xA000' end='0xC000' datawidth='32' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0xC000' end='0xE000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0xE000' end='0xF000' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0xF000' end='0x10000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x10000' end='0x11000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /><slave name='reg_10gbase_r_24.mem' start='0x5C0000' end='0x5E0000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x400' end='0x500' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x500' end='0x600' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x600' end='0x700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x700' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x3100' end='0x3180' datawidth='32' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x3180' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3200' end='0x3280' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x3280' end='0x32C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x32C0' end='0x3300' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3300' end='0x3340' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3340' end='0x3360' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x3360' end='0x3380' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x3380' end='0x33A0' datawidth='32' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x33A0' end='0x33C0' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x33C0' end='0x33E0' datawidth='32' /><slave name='reg_diag_bg_1gbe.mem' start='0x33E0' end='0x3400' datawidth='32' /><slave name='reg_epcs.mem' start='0x3400' end='0x3420' datawidth='32' /><slave name='reg_remu.mem' start='0x3420' end='0x3440' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x3440' end='0x3450' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x3450' end='0x3460' datawidth='32' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x3460' end='0x3470' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3470' end='0x3478' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3478' end='0x3480' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3480' end='0x3488' datawidth='32' /><slave name='pio_pps.mem' start='0x3488' end='0x3490' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3490' end='0x3498' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0x4000' end='0x6000' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x6000' end='0x8000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0x8000' end='0xA000' datawidth='32' /><slave name='ram_diag_bg_1gbe.mem' start='0xA000' end='0xC000' datawidth='32' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0xC000' end='0xE000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0xE000' end='0xF000' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0xF000' end='0x10000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x10000' end='0x11000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -7536,6 +7483,7 @@
</entry>
</assignmentValueMap>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="jtag_uart_0"
@@ -8005,7 +7953,7 @@
<originalModuleInfo>
<className>altera_avalon_jtag_uart</className>
<version>18.0</version>
- <displayName>JTAG UART</displayName>
+ <displayName>JTAG UART Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -8124,6 +8072,7 @@
</entry>
</assignmentValueMap>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="onchip_memory2_0"
@@ -8459,7 +8408,7 @@
<originalModuleInfo>
<className>altera_avalon_onchip_memory2</className>
<version>18.0</version>
- <displayName>On-Chip Memory (RAM or ROM)</displayName>
+ <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -8634,6 +8583,7 @@
</entry>
</assignmentValueMap>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="pio_pps"
@@ -9249,6 +9199,7 @@
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="pio_system_info"
@@ -9864,6 +9815,7 @@
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="pio_wdi"
@@ -10334,7 +10286,7 @@
<originalModuleInfo>
<className>altera_avalon_pio</className>
<version>18.0</version>
- <displayName>PIO (Parallel I/O)</displayName>
+ <displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -10491,6 +10443,7 @@
</entry>
</assignmentValueMap>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="ram_diag_bg_10gbe"
@@ -11106,6 +11059,7 @@
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="ram_diag_bg_1gbe"
@@ -11721,6 +11675,7 @@
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="ram_diag_data_buffer_10gbe"
@@ -12336,6 +12291,7 @@
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="ram_diag_data_buffer_1gbe"
@@ -12951,6 +12907,7 @@
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="ram_diag_data_buffer_ddr_MB_I"
@@ -13566,6 +13523,7 @@
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="ram_diag_data_buffer_ddr_MB_II"
@@ -14181,9 +14139,10 @@
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_10gbase_r_24"
+ name="reg_bsn_monitor_10GbE"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14199,7 +14158,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>15</width>
+ <width>11</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14263,7 +14222,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>15</width>
+ <width>11</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14299,14 +14258,6 @@
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
- <port>
- <name>avs_mem_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
</ports>
<assignments>
<assignmentValueMap>
@@ -14340,7 +14291,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>131072</value>
+ <value>8192</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -14443,15 +14394,15 @@
</entry>
<entry>
<key>readLatency</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>readWaitStates</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>readWaitTime</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
@@ -14655,38 +14606,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>waitrequest</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_waitrequest_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
<interface>
<name>write</name>
<type>conduit</type>
@@ -14754,9 +14673,9 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>avs_common_mm_readlatency0</className>
+ <className>avs_common_mm</className>
<version>1.0</version>
- <displayName>avs_common_mm_readlatency0</displayName>
+ <displayName>avs_common_mm</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -14778,11 +14697,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x2000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>17</value>
+ <value>13</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -14809,36 +14728,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>reg_10gbase_r_24</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_bsn_monitor_10GbE</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>reg_10gbase_r_24</fileSetName>
- <fileSetFixedName>reg_10gbase_r_24</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_bsn_monitor_10GbE</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_bsn_monitor_10GbE</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>reg_10gbase_r_24</fileSetName>
- <fileSetFixedName>reg_10gbase_r_24</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_bsn_monitor_10GbE</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_bsn_monitor_10GbE</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>reg_10gbase_r_24</fileSetName>
- <fileSetFixedName>reg_10gbase_r_24</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_bsn_monitor_10GbE</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_bsn_monitor_10GbE</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/reg_10gbase_r_24.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_10GbE.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_10GbE"
+ name="reg_bsn_monitor_1GbE"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14854,7 +14774,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>11</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14918,7 +14838,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>11</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14987,7 +14907,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8192</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15393,11 +15313,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x2000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>13</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15424,36 +15344,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_bsn_monitor_10GbE</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_bsn_monitor_1GbE</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_bsn_monitor_10GbE</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_bsn_monitor_10GbE</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_bsn_monitor_1GbE</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_bsn_monitor_1GbE</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_bsn_monitor_10GbE</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_bsn_monitor_10GbE</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_bsn_monitor_1GbE</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_bsn_monitor_1GbE</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_bsn_monitor_10GbE</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_bsn_monitor_10GbE</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_bsn_monitor_1GbE</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_bsn_monitor_1GbE</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_10GbE.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_1GbE.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_1GbE"
+ name="reg_diag_bg_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15469,7 +15390,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15533,7 +15454,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15602,7 +15523,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -16008,11 +15929,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -16039,36 +15960,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_bsn_monitor_1GbE</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_diag_bg_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_bsn_monitor_1GbE</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_bsn_monitor_1GbE</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_bg_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_bg_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_bsn_monitor_1GbE</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_bsn_monitor_1GbE</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_bg_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_bg_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_bsn_monitor_1GbE</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_bsn_monitor_1GbE</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_bg_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_bg_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_1GbE.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_bg_10gbe"
+ name="reg_diag_bg_1gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16654,36 +16576,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_diag_bg_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_diag_bg_1gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_bg_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_bg_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_bg_1gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_bg_1gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_bg_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_bg_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_bg_1gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_bg_1gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_bg_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_bg_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_bg_1gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_bg_1gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_1gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_bg_1gbe"
+ name="reg_diag_data_buffer_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16699,7 +16622,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16763,7 +16686,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16832,7 +16755,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17238,11 +17161,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17269,36 +17192,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_diag_bg_1gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_diag_data_buffer_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_bg_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_bg_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_bg_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_bg_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_bg_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_bg_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_1gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_10gbe"
+ name="reg_diag_data_buffer_1gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17314,7 +17238,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17378,7 +17302,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17447,7 +17371,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17853,11 +17777,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17884,36 +17808,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_diag_data_buffer_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_diag_data_buffer_1gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_1gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_1gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_1gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_1gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_1gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_1gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_1gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_1gbe"
+ name="reg_diag_data_buffer_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18499,36 +18424,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_diag_data_buffer_1gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_1gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_ddr_MB_I"
+ name="reg_diag_data_buffer_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19114,36 +19040,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_ddr_MB_II"
+ name="reg_diag_rx_seq_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19729,36 +19656,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_diag_rx_seq_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_rx_seq_10gbe"
+ name="reg_diag_rx_seq_1gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19774,7 +19702,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19838,7 +19766,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19907,7 +19835,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20313,11 +20241,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20344,36 +20272,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_diag_rx_seq_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_diag_rx_seq_1gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_1gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_1gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_1gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_1gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_1gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_1gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_1gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_rx_seq_1gbe"
+ name="reg_diag_rx_seq_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20959,36 +20888,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_diag_rx_seq_1gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_1gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_rx_seq_ddr_MB_I"
+ name="reg_diag_rx_seq_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21574,36 +21504,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_rx_seq_ddr_MB_II"
+ name="reg_diag_tx_seq_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21619,7 +21550,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21683,7 +21614,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21752,7 +21683,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -22158,11 +22089,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22189,36 +22120,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_diag_tx_seq_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_tx_seq_10gbe"
+ name="reg_diag_tx_seq_1gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22234,7 +22166,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22298,7 +22230,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22367,7 +22299,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -22773,11 +22705,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22804,36 +22736,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_diag_tx_seq_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_diag_tx_seq_1gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_1gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_1gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_1gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_1gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_1gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_1gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_1gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_tx_seq_1gbe"
+ name="reg_diag_tx_seq_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23419,36 +23352,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_diag_tx_seq_1gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_1gbe</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_1gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_1gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_tx_seq_ddr_MB_I"
+ name="reg_diag_tx_seq_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -24034,36 +23968,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_tx_seq_ddr_MB_II"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -24079,7 +24014,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24143,7 +24078,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24212,7 +24147,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24618,11 +24553,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24649,36 +24584,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -25264,36 +25200,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -25309,7 +25246,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25373,7 +25310,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25442,7 +25379,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -25848,11 +25785,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -25879,36 +25816,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_eth10g_back0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -25924,7 +25862,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25988,7 +25926,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26057,7 +25995,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26463,11 +26401,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26494,36 +26432,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_eth10g_back0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_eth10g_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_eth10g_back0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_eth10g_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_eth10g_back0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_eth10g_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_eth10g_back0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_epcs.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth10g_back0"
+ name="reg_eth10g_back1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27109,36 +27048,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_eth10g_back0</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_eth10g_back1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_eth10g_back0</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_eth10g_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_eth10g_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_eth10g_back1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_eth10g_back0</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_eth10g_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_eth10g_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_eth10g_back1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_eth10g_back0</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_eth10g_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_eth10g_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_eth10g_back1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth10g_back1"
+ name="reg_eth10g_qsfp_ring"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27154,7 +27094,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27218,7 +27158,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27287,7 +27227,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27693,11 +27633,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27724,36 +27664,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_eth10g_back1</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_eth10g_qsfp_ring</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_eth10g_back1</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_eth10g_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_eth10g_back1</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_eth10g_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_eth10g_back1</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_eth10g_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back1.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_qsfp_ring.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth10g_qsfp_ring"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27769,7 +27710,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27833,7 +27774,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27902,7 +27843,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28308,11 +28249,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28339,36 +28280,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_eth10g_qsfp_ring</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_eth10g_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_eth10g_qsfp_ring</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_eth10g_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_eth10g_qsfp_ring</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_eth10g_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_eth10g_qsfp_ring</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_qsfp_ring.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -28384,7 +28326,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28448,7 +28390,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28517,7 +28459,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28923,11 +28865,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28954,36 +28896,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_io_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -28999,7 +28942,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29063,7 +29006,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29132,7 +29075,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29538,11 +29481,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>18</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -29569,36 +29512,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_io_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_io_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_io_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_io_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_io_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_io_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_io_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_io_ddr_MB_I"
+ name="reg_io_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30184,36 +30128,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_io_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_io_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_io_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_io_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_io_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_io_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_io_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_io_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_io_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_io_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_io_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_io_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_io_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_io_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_io_ddr_MB_II"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30229,7 +30174,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30293,7 +30238,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>16</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30362,7 +30307,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>262144</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30768,11 +30713,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>18</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -30799,36 +30744,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_io_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_io_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_io_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_io_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_io_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_io_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_io_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -31414,36 +31360,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -31459,7 +31406,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31523,7 +31470,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31592,7 +31539,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31998,11 +31945,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -32029,36 +31976,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_tr_10GbE_back0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -32074,7 +32022,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>18</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32138,7 +32086,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>18</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32174,6 +32122,14 @@
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
+ <port>
+ <name>avs_mem_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
</ports>
<assignments>
<assignmentValueMap>
@@ -32207,7 +32163,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>1048576</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32310,15 +32266,15 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
@@ -32522,6 +32478,38 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>waitrequest</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_waitrequest_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>write</name>
<type>conduit</type>
@@ -32589,9 +32577,9 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>avs_common_mm</className>
+ <className>avs_common_mm_readlatency0</className>
<version>1.0</version>
- <displayName>avs_common_mm</displayName>
+ <displayName>avs_common_mm_readlatency0</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -32613,11 +32601,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>20</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -32644,36 +32632,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_tr_10GbE_back0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_tr_10GbE_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_back0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_tr_10GbE_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_back0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_tr_10GbE_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_back0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_remu.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_tr_10GbE_back0"
+ name="reg_tr_10GbE_back1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33299,36 +33288,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_tr_10GbE_back0</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_tr_10GbE_back1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_tr_10GbE_back0</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_tr_10GbE_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_back1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_tr_10GbE_back0</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_tr_10GbE_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_back1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_tr_10GbE_back0</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_tr_10GbE_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_back1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_tr_10GbE_back1"
+ name="reg_tr_10GbE_qsfp_ring"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33344,7 +33334,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>18</width>
+ <width>19</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33408,7 +33398,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>18</width>
+ <width>19</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33485,7 +33475,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1048576</value>
+ <value>2097152</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -33923,11 +33913,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>20</value>
+ <value>21</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -33954,36 +33944,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_tr_10GbE_back1</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_tr_10GbE_qsfp_ring</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_tr_10GbE_back1</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_tr_10GbE_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_qsfp_ring</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_tr_10GbE_back1</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_tr_10GbE_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_qsfp_ring</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_tr_10GbE_back1</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_tr_10GbE_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_qsfp_ring</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back1.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_qsfp_ring.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_tr_10GbE_qsfp_ring"
+ name="reg_unb_pmbus"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33999,7 +33990,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>19</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34063,7 +34054,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>19</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34099,14 +34090,6 @@
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
- <port>
- <name>avs_mem_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
</ports>
<assignments>
<assignmentValueMap>
@@ -34140,7 +34123,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>2097152</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34243,15 +34226,15 @@
</entry>
<entry>
<key>readLatency</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>readWaitStates</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>readWaitTime</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
@@ -34456,14 +34439,14 @@
</parameters>
</interface>
<interface>
- <name>waitrequest</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_waitrequest_export</name>
+ <name>coe_write_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -34488,202 +34471,171 @@
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm_readlatency0</className>
- <version>1.0</version>
- <displayName>avs_common_mm_readlatency0</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>21</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>125000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_tr_10GbE_qsfp_ring</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>qsys_unb2b_test_reg_tr_10GbE_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_qsfp_ring</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_unb2b_test_reg_tr_10GbE_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_qsfp_ring</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_unb2b_test_reg_tr_10GbE_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_tr_10GbE_qsfp_ring</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_qsfp_ring.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
- </module>
- <module
- name="reg_unb_pmbus"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>6</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_unb2b_test_reg_unb_pmbus</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_unb2b_test_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_unb_pmbus</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2b_test_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_unb_pmbus</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2b_test_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_unb_pmbus</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_pmbus.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_unb_sens"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -35224,36 +35176,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_unb_pmbus</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_unb_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_unb_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_unb_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_unb_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_pmbus.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_unb_sens"
+ name="reg_wdi"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -35269,7 +35222,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35333,7 +35286,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35402,7 +35355,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35808,11 +35761,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -35839,36 +35792,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_unb_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_reg_wdi</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_unb_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_wdi</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_unb_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_unb_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_sens.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_wdi.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_wdi"
+ name="rom_system_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -35884,7 +35838,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35948,7 +35902,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36017,7 +35971,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36423,11 +36377,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>12</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -36454,36 +36408,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_reg_wdi</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_test_rom_system_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_rom_system_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_rom_system_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_test_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_unb2b_test_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_unb2b_test_rom_system_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_reg_wdi.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_rom_system_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="rom_system_info"
+ name="timer_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -36491,17 +36446,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>clk</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>10</width>
+ <name>clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -36510,26 +36465,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>irq</name>
+ <type>interrupt</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
+ <name>irq</name>
+ <role>irq</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -36541,63 +36497,106 @@
</assignments>
<parameters>
<parameterValueMap>
+ <entry>
+ <key>associatedAddressablePoint</key>
+ <value>timer_0.s1</value>
+ </entry>
<entry>
<key>associatedClock</key>
+ <value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
+ <value>reset</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>bridgedReceiverOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToReceiver</key>
+ </entry>
+ <entry>
+ <key>irqScheme</key>
+ <value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>mem</name>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>s1</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
- <name>avs_mem_address</name>
+ <name>address</name>
<role>address</role>
<direction>Input</direction>
- <width>10</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>avs_mem_write</name>
- <role>write</role>
+ <name>writedata</name>
+ <role>writedata</role>
<direction>Input</direction>
- <width>1</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
+ <name>readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>avs_mem_read</name>
- <role>read</role>
+ <name>chipselect</name>
+ <role>chipselect</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>write_n</name>
+ <role>write_n</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -36618,13 +36617,17 @@
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
+ <entry>
+ <key>embeddedsw.configuration.isTimerDevice</key>
+ <value>1</value>
+ </entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
- <value>DYNAMIC</value>
+ <value>NATIVE</value>
</entry>
<entry>
<key>addressGroup</key>
@@ -36632,7 +36635,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>4096</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36644,674 +36647,11 @@
</entry>
<entry>
<key>associatedClock</key>
- <value>system</value>
+ <value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>12</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>125000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_test_rom_system_info</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>qsys_unb2b_test_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_rom_system_info</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_unb2b_test_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_rom_system_info</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_unb2b_test_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_unb2b_test_rom_system_info</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_test/qsys_unb2b_test_rom_system_info.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
- </module>
- <module
- name="timer_0"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>irq</name>
- <type>interrupt</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>irq</name>
- <role>irq</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- <value>timer_0.s1</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bridgedReceiverOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToReceiver</key>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>s1</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>16</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>16</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>chipselect</name>
- <role>chipselect</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>write_n</name>
- <role>write_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isTimerDevice</key>
- <value>1</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>NATIVE</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>reset</value>
+ <value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
@@ -37686,7 +37026,7 @@
<originalModuleInfo>
<className>altera_avalon_timer</className>
<version>18.0</version>
- <displayName>Interval Timer</displayName>
+ <displayName>Interval Timer Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -37819,6 +37159,7 @@
</entry>
</assignmentValueMap>
</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
</module>
<connection
kind="avalon"
@@ -38142,13 +37483,6 @@
end="reg_fpga_temp_sens.mem">
<parameter name="baseAddress" value="0x3340" />
</connection>
- <connection
- kind="avalon"
- version="18.0"
- start="cpu_0.data_master"
- end="reg_10gbase_r_24.mem">
- <parameter name="baseAddress" value="0x005c0000" />
- </connection>
<connection
kind="avalon"
version="18.0"
@@ -38441,11 +37775,6 @@
version="18.0"
start="clk_0.clk"
end="reg_fpga_temp_sens.system" />
- <connection
- kind="clock"
- version="18.0"
- start="clk_0.clk"
- end="reg_10gbase_r_24.system" />
<connection
kind="interrupt"
version="18.0"
@@ -38719,11 +38048,6 @@
version="18.0"
start="clk_0.clk_reset"
end="reg_fpga_temp_sens.system_reset" />
- <connection
- kind="reset"
- version="18.0"
- start="clk_0.clk_reset"
- end="reg_10gbase_r_24.system_reset" />
<connection
kind="reset"
version="18.0"
@@ -38979,11 +38303,6 @@
version="18.0"
start="cpu_0.debug_reset_request"
end="reg_fpga_temp_sens.system_reset" />
- <connection
- kind="reset"
- version="18.0"
- start="cpu_0.debug_reset_request"
- end="reg_10gbase_r_24.system_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/README.txt b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e1c39def67277b45091d181a9352cabea14a5489
--- /dev/null
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/README.txt
@@ -0,0 +1,42 @@
+
+
+Simulation
+----------
+-> Read ../../doc/README first until step 3
+Modelsim instructions:
+
+ # in Modelsim do:
+ lp unb2a_test_ddr_MB_I_II
+ mk all
+ # now double click on testbench file
+ as 10
+ run 500us
+
+
+ # while the simulation runs... in another terminal/bash session do:
+ cd unb2a_test/tb/python
+
+ # To read out the design_name; do:
+ python tc_unb2_test.py --sim --unb 0 --fn 3 --seq INFO
+
+ # To test the ddr4 modules; do:
+ python tc_unb2_test_ddr.py --sim --unb 0 --fn 3 -v 5 -s I,II --rep 1 -n 1000
+
+ # to end simulation in Modelsim do:
+ quit -sim
+
+
+
+Testing on hardware
+-------------------
+-> Read ../../doc/README first until step 5
+
+# (assume that the Uniboard is --unb 1 -> check the dipswitches or backpanel-slotnumber)
+
+# To read out the design_name; do:
+python tc_unb2_test.py --unb 1 --fn 0:3 --seq REGMAP,INFO
+
+# To test the ddr4 modules:
+python tc_unb2_test_ddr.py --unb 1 --fn 0:3 -v 5 -s I,II --rep 1 -n 10000000
+# --rep N (N is number of runs. If N=-1 run continuously and break with ctrl-c key)
+
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..c016fc4ec9b69ec7a190cc2e1facc56efc26b3ab
--- /dev/null
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/hdllib.cfg
@@ -0,0 +1,99 @@
+hdl_lib_name = unb2b_test_ddr_MB_I_II
+hdl_library_clause_name = unb2b_test_ddr_MB_I_II_lib
+hdl_lib_uses_synth = common mm technology unb2b_board unb2b_test
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_include_ip =
+ # Comment all IP that is not used in this design
+ # DDR memory
+ ip_arria10_e1sg_ddr4_8g_1600
+synth_files =
+ unb2b_test_ddr_MB_I_II.vhd
+
+test_bench_files =
+ tb_unb2b_test_ddr_MB_I_II.vhd
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus/ .
+ ../../src/hex hex
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/qsys_unb2b_test/qsys_unb2b_test.qip
+
+quartus_tcl_files =
+ quartus/unb2b_test_ddr_MB_I_II_pins.tcl
+
+quartus_sdc_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_10GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_1GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/quartus/unb2b_test_ddr_MB_I_II_pins.tcl b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/quartus/unb2b_test_ddr_MB_I_II_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..aeb8fe68eb623924631547feac91c3f4b6adc796
--- /dev/null
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/quartus/unb2b_test_ddr_MB_I_II_pins.tcl
@@ -0,0 +1,23 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_ddr_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b5248d03885170312faae54144dca327a54f2f09
--- /dev/null
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
@@ -0,0 +1,41 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+
+
+LIBRARY IEEE, unb2b_test_lib;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_unb2b_test_ddr_MB_I_II IS
+END tb_unb2b_test_ddr_MB_I_II;
+
+
+ARCHITECTURE tb OF tb_unb2b_test_ddr_MB_I_II IS
+BEGIN
+ u_tb_unb2b_test : ENTITY unb2b_test_lib.tb_unb2b_test
+ GENERIC MAP (
+ g_design_name => "unb2b_test_ddr_MB_I_II",
+ g_sim_model_ddr => FALSE
+ );
+END tb;
+
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ca8f99606e2dad190868f6e1f985575354405fcb
--- /dev/null
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
@@ -0,0 +1,144 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_test_lib, technology_lib, tech_ddr_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+
+
+ENTITY unb2b_test_ddr_MB_I_II IS
+ GENERIC (
+ g_design_name : STRING := "unb2b_test_ddr_MB_I_II";
+ g_design_note : STRING := "Test design with ddr4";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+ -- DDR reference clocks
+ MB_I_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_I
+ MB_II_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_II
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN : IN t_tech_ddr4_phy_in;
+ MB_I_IO : INOUT t_tech_ddr4_phy_io;
+ MB_I_OU : OUT t_tech_ddr4_phy_ou;
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN : IN t_tech_ddr4_phy_in;
+ MB_II_IO : INOUT t_tech_ddr4_phy_io;
+ MB_II_OU : OUT t_tech_ddr4_phy_ou;
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2b_test_ddr_MB_I_II;
+
+
+ARCHITECTURE str OF unb2b_test_ddr_MB_I_II IS
+
+BEGIN
+ u_revision : ENTITY unb2b_test_lib.unb2b_test
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
+END str;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index 842561e71fc06414b7f1c7a7bdb8fadccd5cb7a6..2f1b37763ab87fe92d8dcccc35243e9248245f2f 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -175,8 +175,6 @@ ENTITY mmm_unb2b_test IS
reg_diag_rx_seq_10GbE_miso : IN t_mem_miso;
-- 10GbE
- reg_10gbase_r_24_mosi : OUT t_mem_mosi;
- reg_10gbase_r_24_miso : IN t_mem_miso;
reg_tr_10GbE_qsfp_ring_mosi : OUT t_mem_mosi;
reg_tr_10GbE_qsfp_ring_miso : IN t_mem_miso;
reg_tr_10GbE_back0_mosi : OUT t_mem_mosi;
@@ -388,9 +386,6 @@ BEGIN
u_mm_file_reg_eth1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
PORT MAP(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
- u_mm_file_reg_10gbase_r_24 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_10GBASE_R_24")
- PORT MAP(mm_rst, mm_clk, reg_10gbase_r_24_mosi, reg_10gbase_r_24_miso);
-
u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
u_mm_file_reg_tr_10GbE_back0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
@@ -610,15 +605,6 @@ BEGIN
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_10gbase_r_24_reset_export => OPEN,
- reg_10gbase_r_24_clk_export => OPEN,
- reg_10gbase_r_24_address_export => reg_10gbase_r_24_mosi.address(14 DOWNTO 0),
- reg_10gbase_r_24_write_export => reg_10gbase_r_24_mosi.wr,
- reg_10gbase_r_24_writedata_export => reg_10gbase_r_24_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_10gbase_r_24_read_export => reg_10gbase_r_24_mosi.rd,
- reg_10gbase_r_24_readdata_export => reg_10gbase_r_24_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_10gbase_r_24_waitrequest_export => reg_10gbase_r_24_miso.waitrequest,
-
reg_tr_10gbe_qsfp_ring_reset_export => OPEN,
reg_tr_10gbe_qsfp_ring_clk_export => OPEN,
reg_tr_10gbe_qsfp_ring_address_export => reg_tr_10GbE_qsfp_ring_mosi.address(c_reg_tr_10GbE_qsfp_ring_multi_adr_w-1 DOWNTO 0),
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
index d6154e79bb6d6b413468eb5d2524e00f2a5bc960..fd2eb8444522bd7663aa95f1aa2caa6ac144037a 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
@@ -309,14 +309,6 @@ PACKAGE qsys_unb2b_test_pkg IS
reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
- reg_10gbase_r_24_address_export : out std_logic_vector(14 downto 0); -- reg_10gbase_r_24_address.export
- reg_10gbase_r_24_clk_export : out std_logic; -- reg_10gbase_r_24_clk.export
- reg_10gbase_r_24_read_export : out std_logic; -- reg_10gbase_r_24_read.export
- reg_10gbase_r_24_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_10gbase_r_24_readdata.export
- reg_10gbase_r_24_reset_export : out std_logic; -- reg_10gbase_r_24_reset.export
- reg_10gbase_r_24_waitrequest_export : in std_logic := '0'; -- reg_10gbase_r_24_waitrequest.export
- reg_10gbase_r_24_write_export : out std_logic; -- reg_10gbase_r_24_write.export
- reg_10gbase_r_24_writedata_export : out std_logic_vector(31 downto 0); -- reg_10gbase_r_24_writedata.export
reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
index 7e05761310a47e575255a49c44f258175e9852d2..754e8ab1f55e6cfc69abbc869e46bd6a536298b2 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
@@ -49,7 +49,7 @@ ENTITY unb2b_test IS
g_sim_model_ddr : BOOLEAN := FALSE;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
+ g_revision_id : STRING := ""; -- revision ID -- set by QSF
g_factory_image : BOOLEAN := FALSE
);
PORT (
@@ -328,9 +328,6 @@ ARCHITECTURE str OF unb2b_test IS
SIGNAL serial_10G_tx_back_arr : STD_LOGIC_VECTOR(c_nof_streams_back0+c_nof_streams_back1-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_back_arr : STD_LOGIC_VECTOR(c_nof_streams_back0+c_nof_streams_back1-1 DOWNTO 0);
- SIGNAL reg_10gbase_r_24_mosi : t_mem_mosi;
- SIGNAL reg_10gbase_r_24_miso : t_mem_miso;
-
SIGNAL reg_tr_10GbE_qsfp_ring_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_qsfp_ring_miso : t_mem_miso;
SIGNAL reg_tr_10GbE_back0_mosi : t_mem_mosi;
@@ -451,7 +448,7 @@ BEGIN
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
+ g_revision_id => g_revision_id,
g_fw_version => c_fw_version,
g_mm_clk_freq => sel_a_b(g_sim,c_unb2b_board_mm_clk_freq_25M,c_unb2b_board_mm_clk_freq_125M),
g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
@@ -717,9 +714,6 @@ BEGIN
-- 10GbE
- reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
-
reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
@@ -910,8 +904,6 @@ BEGIN
reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
- reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
dp_rst => dp_rst,
dp_clk => dp_clk,
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys
index a252c4e3053ef132c7d6468c8fd85b4d79d59ee5..6032763f974a8b2a34952bc23a718feaed4d2e7a 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys
@@ -5,14 +5,11 @@
displayName="$${FILENAME}"
version="1.0"
description=""
- tags="INTERNAL_COMPONENT=true"
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
categories="System"
- tool="QsysStandard" />
+ tool="QsysPro" />
<parameter name="bonusData"><![CDATA[bonusData
{
- element $system
- {
- }
element emif_0
{
datum _sortIndex
@@ -24,7 +21,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="device" value="10AX115U2F45E1SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="1" />
<parameter name="fabricMode" value="QSYS" />
@@ -39,6 +36,19 @@
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos>
+ <entry>
+ <key>cal_debug_out_clk</key>
+ <value>
+ <connectionPointName>cal_debug_out_clk</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>0</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
<entry>
<key>ctrl_amm_0</key>
<value>
@@ -89,7 +99,7 @@
<consumedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
- <value>200000000</value>
+ <value>175000000</value>
</entry>
</consumedSystemInfos>
</value>
@@ -101,6 +111,36 @@
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
+ <interface
+ name="cal_debug_out"
+ internal="emif_0.cal_debug_out"
+ type="avalon"
+ dir="start">
+ <port name="cal_debug_out_addr" internal="cal_debug_out_addr" />
+ <port name="cal_debug_out_byteenable" internal="cal_debug_out_byteenable" />
+ <port name="cal_debug_out_read" internal="cal_debug_out_read" />
+ <port name="cal_debug_out_read_data" internal="cal_debug_out_read_data" />
+ <port
+ name="cal_debug_out_read_data_valid"
+ internal="cal_debug_out_read_data_valid" />
+ <port name="cal_debug_out_waitrequest" internal="cal_debug_out_waitrequest" />
+ <port name="cal_debug_out_write" internal="cal_debug_out_write" />
+ <port name="cal_debug_out_write_data" internal="cal_debug_out_write_data" />
+ </interface>
+ <interface
+ name="cal_debug_out_clk"
+ internal="emif_0.cal_debug_out_clk"
+ type="clock"
+ dir="start">
+ <port name="cal_debug_out_clk" internal="cal_debug_out_clk" />
+ </interface>
+ <interface
+ name="cal_debug_out_reset_n"
+ internal="emif_0.cal_debug_out_reset_n"
+ type="reset"
+ dir="start">
+ <port name="cal_debug_out_reset_n" internal="cal_debug_out_reset_n" />
+ </interface>
<interface
name="ctrl_amm_0"
internal="emif_0.ctrl_amm_0"
@@ -189,7 +229,7 @@
<module
name="emif_0"
kind="altera_emif"
- version="17.0"
+ version="18.0"
enabled="1"
autoexport="1">
<parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
@@ -217,29 +257,29 @@
<parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
<parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
<parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
- <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="5.0E-4" />
- <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.0055" />
- <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.006" />
- <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="-0.2285" />
+ <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="-0.003125" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.103" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.006008328" />
+ <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.0425" />
<parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
<parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
- <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.231" />
- <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.291" />
+ <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.215" />
+ <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.323" />
<parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
<parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.072" />
<parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.0" />
- <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.137" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.176" />
<parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.0" />
- <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="1.16" />
- <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="2.43" />
+ <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
<parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.0" />
- <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="3.7" />
+ <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="8.0" />
<parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.0" />
- <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="2.2" />
+ <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
<parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.0" />
- <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="3.7" />
+ <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="4.0" />
<parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.0" />
- <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.16" />
+ <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
<parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
<parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="false" />
<parameter name="BOARD_LPDDR3_AC_TO_CK_SKEW_NS" value="0.0" />
@@ -404,6 +444,7 @@
<parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
<parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
<parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC" value="4" />
<parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
<parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
<parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
@@ -419,8 +460,10 @@
<parameter name="DIAG_DDR3_CAL_ENABLE_MICRON_AP" value="false" />
<parameter name="DIAG_DDR3_CAL_ENABLE_NON_DES" value="false" />
<parameter name="DIAG_DDR3_CAL_FULL_CAL_ON_RESET" value="true" />
+ <parameter name="DIAG_DDR3_CA_DESKEW_EN" value="false" />
<parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
<parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
<parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
<parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR3_EX_DESIGN_ISSP_EN" value="true" />
@@ -430,6 +473,7 @@
<parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
<parameter name="DIAG_DDR3_SEPARATE_READ_WRITE_ITFS" value="false" />
<parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR3_SIM_VERBOSE" value="true" />
<parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
@@ -443,7 +487,8 @@
<parameter name="DIAG_DDR4_CAL_ENABLE_NON_DES" value="false" />
<parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
<parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
- <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_JTAG</parameter>
<parameter name="DIAG_DDR4_EX_DESIGN_ISSP_EN" value="true" />
<parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
@@ -452,9 +497,10 @@
<parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
<parameter name="DIAG_DDR4_SEPARATE_READ_WRITE_ITFS" value="false" />
<parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR4_SIM_VERBOSE" value="true" />
<parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
<parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
- <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
+ <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="false" />
<parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
@@ -471,12 +517,14 @@
<parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
<parameter name="DIAG_EX_DESIGN_SEPARATE_RESETS" value="false" />
<parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+ <parameter name="DIAG_HMC_HRC" value="auto" />
<parameter name="DIAG_LPDDR3_ABSTRACT_PHY" value="false" />
<parameter name="DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN" value="false" />
<parameter name="DIAG_LPDDR3_BYPASS_REPEAT_STAGE" value="true" />
<parameter name="DIAG_LPDDR3_BYPASS_STRESS_STAGE" value="true" />
<parameter name="DIAG_LPDDR3_BYPASS_USER_STAGE" value="true" />
<parameter name="DIAG_LPDDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
<parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
<parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_LPDDR3_EX_DESIGN_ISSP_EN" value="true" />
@@ -486,6 +534,7 @@
<parameter name="DIAG_LPDDR3_INTERFACE_ID" value="0" />
<parameter name="DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS" value="false" />
<parameter name="DIAG_LPDDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_LPDDR3_SIM_VERBOSE" value="true" />
<parameter name="DIAG_LPDDR3_SKIP_CA_DESKEW" value="false" />
<parameter name="DIAG_LPDDR3_SKIP_CA_LEVEL" value="false" />
<parameter name="DIAG_LPDDR3_TG_BE_PATTERN_LENGTH" value="8" />
@@ -497,6 +546,7 @@
<parameter name="DIAG_QDR2_BYPASS_STRESS_STAGE" value="true" />
<parameter name="DIAG_QDR2_BYPASS_USER_STAGE" value="true" />
<parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
<parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="false" />
<parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR2_EX_DESIGN_ISSP_EN" value="true" />
@@ -506,6 +556,7 @@
<parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
<parameter name="DIAG_QDR2_SEPARATE_READ_WRITE_ITFS" value="false" />
<parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR2_SIM_VERBOSE" value="true" />
<parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
@@ -515,6 +566,7 @@
<parameter name="DIAG_QDR4_BYPASS_STRESS_STAGE" value="true" />
<parameter name="DIAG_QDR4_BYPASS_USER_STAGE" value="true" />
<parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
<parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
<parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR4_EX_DESIGN_ISSP_EN" value="true" />
@@ -524,6 +576,7 @@
<parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
<parameter name="DIAG_QDR4_SEPARATE_READ_WRITE_ITFS" value="false" />
<parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR4_SIM_VERBOSE" value="true" />
<parameter name="DIAG_QDR4_SKIP_VREF_CAL" value="false" />
<parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
@@ -534,6 +587,7 @@
<parameter name="DIAG_RLD2_BYPASS_STRESS_STAGE" value="true" />
<parameter name="DIAG_RLD2_BYPASS_USER_STAGE" value="true" />
<parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
<parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="false" />
<parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD2_EX_DESIGN_ISSP_EN" value="true" />
@@ -543,6 +597,7 @@
<parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
<parameter name="DIAG_RLD2_SEPARATE_READ_WRITE_ITFS" value="false" />
<parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD2_SIM_VERBOSE" value="true" />
<parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
@@ -551,7 +606,10 @@
<parameter name="DIAG_RLD3_BYPASS_REPEAT_STAGE" value="true" />
<parameter name="DIAG_RLD3_BYPASS_STRESS_STAGE" value="true" />
<parameter name="DIAG_RLD3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_CA_DESKEW_EN" value="false" />
+ <parameter name="DIAG_RLD3_CA_LEVEL_EN" value="false" />
<parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
<parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="false" />
<parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD3_EX_DESIGN_ISSP_EN" value="true" />
@@ -561,6 +619,7 @@
<parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
<parameter name="DIAG_RLD3_SEPARATE_READ_WRITE_ITFS" value="false" />
<parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD3_SIM_VERBOSE" value="true" />
<parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
@@ -629,6 +688,8 @@
<parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
<parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
<parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR3_CFG_GEN_DBE" value="false" />
+ <parameter name="MEM_DDR3_CFG_GEN_SBE" value="false" />
<parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
<parameter name="MEM_DDR3_CK_WIDTH" value="1" />
<parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
@@ -724,6 +785,8 @@
<parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
<parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
<parameter name="MEM_DDR4_CAL_MODE" value="0" />
+ <parameter name="MEM_DDR4_CFG_GEN_DBE" value="false" />
+ <parameter name="MEM_DDR4_CFG_GEN_SBE" value="false" />
<parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
<parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
<parameter name="MEM_DDR4_CK_WIDTH" value="2" />
@@ -732,7 +795,7 @@
<parameter name="MEM_DDR4_DB_RTT_NOM_ENUM">DDR4_DB_RTT_NOM_ODT_DISABLED</parameter>
<parameter name="MEM_DDR4_DB_RTT_PARK_ENUM">DDR4_DB_RTT_PARK_ODT_DISABLED</parameter>
<parameter name="MEM_DDR4_DB_RTT_WR_ENUM">DDR4_DB_RTT_WR_RZQ_3</parameter>
- <parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="false" />
+ <parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="true" />
<parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
<parameter name="MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN" value="false" />
<parameter name="MEM_DDR4_DLL_EN" value="true" />
@@ -763,7 +826,7 @@
<parameter name="MEM_DDR4_READ_PREAMBLE" value="2" />
<parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
<parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
- <parameter name="MEM_DDR4_RTT_NOM_ENUM" value="DDR4_RTT_NOM_RZQ_4" />
+ <parameter name="MEM_DDR4_RTT_NOM_ENUM" value="DDR4_RTT_NOM_RZQ_5" />
<parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
<parameter name="MEM_DDR4_RTT_WR_ENUM">DDR4_RTT_WR_ODT_DISABLED</parameter>
<parameter name="MEM_DDR4_R_ODT0_1X1" value="on" />
@@ -796,23 +859,23 @@
<parameter name="MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM" value="20" />
<parameter name="MEM_DDR4_SPD_152_DRAM_RTT_PARK" value="39" />
<parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2133" />
- <parameter name="MEM_DDR4_TCCD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TCCD_L_CYC" value="4" />
<parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
- <parameter name="MEM_DDR4_TCL" value="11" />
+ <parameter name="MEM_DDR4_TCL" value="12" />
<parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
- <parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.1" />
+ <parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.2" />
<parameter name="MEM_DDR4_TDQSCK_PS" value="170" />
<parameter name="MEM_DDR4_TDQSQ_PS" value="66" />
<parameter name="MEM_DDR4_TDQSQ_UI" value="0.16" />
<parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
<parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
<parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
- <parameter name="MEM_DDR4_TDVWP_UI" value="0.72" />
+ <parameter name="MEM_DDR4_TDVWP_UI" value="0.69" />
<parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
<parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
<parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
<parameter name="MEM_DDR4_TFAW_DLR_CYC" value="16" />
- <parameter name="MEM_DDR4_TFAW_NS" value="21.0" />
+ <parameter name="MEM_DDR4_TFAW_NS" value="28.57" />
<parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
<parameter name="MEM_DDR4_TIH_PS" value="105" />
<parameter name="MEM_DDR4_TINIT_US" value="500" />
@@ -829,14 +892,16 @@
<parameter name="MEM_DDR4_TRFC_NS" value="260.0" />
<parameter name="MEM_DDR4_TRP_NS" value="14.06" />
<parameter name="MEM_DDR4_TRRD_DLR_CYC" value="4" />
- <parameter name="MEM_DDR4_TRRD_L_CYC" value="5" />
- <parameter name="MEM_DDR4_TRRD_S_CYC" value="3" />
- <parameter name="MEM_DDR4_TWLH_PS" value="185.7" />
- <parameter name="MEM_DDR4_TWLS_PS" value="185.7" />
+ <parameter name="MEM_DDR4_TRRD_L_CYC" value="4" />
+ <parameter name="MEM_DDR4_TRRD_S_CYC" value="4" />
+ <parameter name="MEM_DDR4_TWLH_CYC" value="0.13" />
+ <parameter name="MEM_DDR4_TWLH_PS" value="0.0" />
+ <parameter name="MEM_DDR4_TWLS_CYC" value="0.13" />
+ <parameter name="MEM_DDR4_TWLS_PS" value="0.0" />
<parameter name="MEM_DDR4_TWR_NS" value="15.0" />
<parameter name="MEM_DDR4_TWTR_L_CYC" value="6" />
<parameter name="MEM_DDR4_TWTR_S_CYC" value="2" />
- <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_0</parameter>
<parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="68.0" />
<parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="false" />
<parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
@@ -944,8 +1009,10 @@
<parameter name="MEM_QDR4_DATA_INV_ENA" value="false" />
<parameter name="MEM_QDR4_DATA_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
<parameter name="MEM_QDR4_DQ_PER_PORT_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR4_MEM_TYPE_ENUM" value="MEM_XP" />
<parameter name="MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
<parameter name="MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_SKIP_ODT_SWEEPING" value="true" />
<parameter name="MEM_QDR4_SPEEDBIN_ENUM" value="QDR4_SPEEDBIN_2133" />
<parameter name="MEM_QDR4_TASH_PS" value="170" />
<parameter name="MEM_QDR4_TCKDK_MAX_PS" value="150" />
@@ -1010,6 +1077,7 @@
<parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
<parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
<parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
<parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
<parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="true" />
<parameter name="PHY_DDR3_HPS_ENABLE_EARLY_RELEASE" value="false" />
@@ -1035,11 +1103,12 @@
<parameter name="PHY_DDR3_USER_STARTING_VREFIN" value="70.0" />
<parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
<parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
<parameter name="PHY_DDR4_DEFAULT_IO" value="false" />
<parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
<parameter name="PHY_DDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
<parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
- <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="800.0" />
+ <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="700.0" />
<parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
<parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="IO_STD_SSTL_12" />
@@ -1049,7 +1118,7 @@
<parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="IO_STD_SSTL_12" />
<parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="OUT_OCT_40_CAL" />
<parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
- <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="IN_OCT_60_CAL" />
+ <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="IN_OCT_48_CAL" />
<parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="IO_STD_POD_12" />
<parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="OUT_OCT_34_CAL" />
<parameter name="PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
@@ -1057,9 +1126,10 @@
<parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="IO_STD_CMOS_12" />
<parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="25.0" />
<parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="IO_STD_CMOS_12" />
- <parameter name="PHY_DDR4_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_DDR4_USER_STARTING_VREFIN" value="60.0" />
<parameter name="PHY_LPDDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
<parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
<parameter name="PHY_LPDDR3_DEFAULT_IO" value="true" />
<parameter name="PHY_LPDDR3_DEFAULT_REF_CLK_FREQ" value="true" />
<parameter name="PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE" value="false" />
@@ -1085,6 +1155,7 @@
<parameter name="PHY_LPDDR3_USER_STARTING_VREFIN" value="70.0" />
<parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
<parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
<parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
<parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
<parameter name="PHY_QDR2_HPS_ENABLE_EARLY_RELEASE" value="false" />
@@ -1110,6 +1181,7 @@
<parameter name="PHY_QDR2_USER_STARTING_VREFIN" value="70.0" />
<parameter name="PHY_QDR4_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
<parameter name="PHY_QDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
<parameter name="PHY_QDR4_DEFAULT_IO" value="true" />
<parameter name="PHY_QDR4_DEFAULT_REF_CLK_FREQ" value="true" />
<parameter name="PHY_QDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
@@ -1135,6 +1207,7 @@
<parameter name="PHY_QDR4_USER_STARTING_VREFIN" value="70.0" />
<parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
<parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
<parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
<parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
<parameter name="PHY_RLD2_HPS_ENABLE_EARLY_RELEASE" value="false" />
@@ -1160,6 +1233,7 @@
<parameter name="PHY_RLD2_USER_STARTING_VREFIN" value="70.0" />
<parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
<parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
<parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
<parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
<parameter name="PHY_RLD3_HPS_ENABLE_EARLY_RELEASE" value="false" />
@@ -1268,7 +1342,8 @@
<parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
<parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
<parameter name="SHORT_QSYS_INTERFACE_NAMES" value="true" />
- <parameter name="SYS_INFO_DEVICE" value="10AX115S2F45E1SG" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115U2F45E1SG" />
+ <parameter name="SYS_INFO_DEVICE_DIE_REVISIONS" value="" />
<parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
<parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="1" />
<parameter name="SYS_INFO_UNIQUE_ID">ip_arria10_e1sg_ddr4_8g_1600_emif_0</parameter>