From c80abada8b5abcf2aa6d48bb4aa91f47ff90731b Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Sat, 29 Aug 2015 10:46:37 +0000
Subject: [PATCH] moved to ATXPLL driving 12 PHY's instead of 24

---
 .../ip_arria10/phy_10gbase_r/compile_ip.tcl   |   4 +-
 .../ip_arria10_phy_10gbase_r.qsys             |  45 +-
 .../phy_10gbase_r_12/compile_ip.tcl           |   4 +-
 .../ip_arria10_phy_10gbase_r_12.qsys          |  86 ++-
 .../ip_arria10/phy_10gbase_r_24/README.txt    |   4 -
 .../phy_10gbase_r_24/compile_ip.tcl           |  56 --
 .../phy_10gbase_r_24/generate_ip.sh           |  44 --
 .../ip_arria10/phy_10gbase_r_24/hdllib.cfg    |  16 -
 .../ip_arria10_phy_10gbase_r_24.qsys          | 534 ------------------
 .../ip_arria10_transceiver_pll_10g.qsys       |  50 +-
 ...rria10_transceiver_reset_controller_1.qsys |  10 +-
 ...ria10_transceiver_reset_controller_12.qsys |  10 +-
 .../compile_ip.tcl                            |  43 --
 .../generate_ip.sh                            |  44 --
 .../hdllib.cfg                                |  16 -
 ...ria10_transceiver_reset_controller_24.qsys | 178 ------
 ...ria10_transceiver_reset_controller_48.qsys | 178 ------
 .../transceiver_reset_controller_48.qsys      | 178 ------
 18 files changed, 159 insertions(+), 1341 deletions(-)
 delete mode 100644 libraries/technology/ip_arria10/phy_10gbase_r_24/README.txt
 delete mode 100644 libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
 delete mode 100755 libraries/technology/ip_arria10/phy_10gbase_r_24/generate_ip.sh
 delete mode 100644 libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
 delete mode 100644 libraries/technology/ip_arria10/phy_10gbase_r_24/ip_arria10_phy_10gbase_r_24.qsys
 delete mode 100644 libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
 delete mode 100755 libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh
 delete mode 100644 libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
 delete mode 100644 libraries/technology/ip_arria10/transceiver_reset_controller_24/ip_arria10_transceiver_reset_controller_24.qsys
 delete mode 100644 libraries/technology/ip_arria10/transceiver_reset_controller_48/ip_arria10_transceiver_reset_controller_48.qsys
 delete mode 100644 libraries/technology/ip_arria10/transceiver_reset_controller_48/transceiver_reset_controller_48.qsys

diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
index 1380dd059e..2783be2053 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
@@ -51,6 +51,6 @@ vmap ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150 ./work/
   vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_prbs_accum.sv"                                  -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150
   vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_odi_accel.sv"                                   -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150
   vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_rcfg_arb.sv"                                    -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150_3iyq5ha.sv" -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_rcfg_opt_logic_3iyq5ha.sv"                      -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150
+  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150_vst4egi.sv" -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150
+  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_rcfg_opt_logic_vst4egi.sv"                      -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150
   vcom     "$IP_DIR/ip_arria10_phy_10gbase_r.vhd"                                                                                                                                                           
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys b/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys
index 0d8d12dd3a..4df502a979 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys
@@ -46,6 +46,9 @@
  <parameter name="timeStamp" value="0" />
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
+ <interface name="reconfig_avmm" internal="xcvr_native_a10_0.reconfig_avmm" />
+ <interface name="reconfig_clk" internal="xcvr_native_a10_0.reconfig_clk" />
+ <interface name="reconfig_reset" internal="xcvr_native_a10_0.reconfig_reset" />
  <interface
    name="rx_analogreset"
    internal="xcvr_native_a10_0.rx_analogreset"
@@ -165,6 +168,27 @@
    dir="end">
   <port name="rx_parallel_data" internal="rx_parallel_data" />
  </interface>
+ <interface
+   name="rx_prbs_done"
+   internal="xcvr_native_a10_0.rx_prbs_done"
+   type="conduit"
+   dir="end">
+  <port name="rx_prbs_done" internal="rx_prbs_done" />
+ </interface>
+ <interface
+   name="rx_prbs_err"
+   internal="xcvr_native_a10_0.rx_prbs_err"
+   type="conduit"
+   dir="end">
+  <port name="rx_prbs_err" internal="rx_prbs_err" />
+ </interface>
+ <interface
+   name="rx_prbs_err_clr"
+   internal="xcvr_native_a10_0.rx_prbs_err_clr"
+   type="conduit"
+   dir="end">
+  <port name="rx_prbs_err_clr" internal="rx_prbs_err_clr" />
+ </interface>
  <interface
    name="rx_serial_data"
    internal="xcvr_native_a10_0.rx_serial_data"
@@ -172,6 +196,13 @@
    dir="end">
   <port name="rx_serial_data" internal="rx_serial_data" />
  </interface>
+ <interface
+   name="rx_seriallpbken"
+   internal="xcvr_native_a10_0.rx_seriallpbken"
+   type="conduit"
+   dir="end">
+  <port name="rx_seriallpbken" internal="rx_seriallpbken" />
+ </interface>
  <interface
    name="tx_analogreset"
    internal="xcvr_native_a10_0.tx_analogreset"
@@ -266,11 +297,7 @@
  <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
  <interface
    name="tx_pma_div_clkout"
-   internal="xcvr_native_a10_0.tx_pma_div_clkout"
-   type="conduit"
-   dir="end">
-  <port name="tx_pma_div_clkout" internal="tx_pma_div_clkout" />
- </interface>
+   internal="xcvr_native_a10_0.tx_pma_div_clkout" />
  <interface
    name="tx_serial_clk0"
    internal="xcvr_native_a10_0.tx_serial_clk0"
@@ -363,8 +390,8 @@
   <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
   <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
   <parameter name="enable_port_rx_polinv" value="0" />
-  <parameter name="enable_port_rx_seriallpbken" value="0" />
-  <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
+  <parameter name="enable_port_rx_seriallpbken" value="1" />
+  <parameter name="enable_port_rx_seriallpbken_tx" value="1" />
   <parameter name="enable_port_rx_signaldetect" value="0" />
   <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
   <parameter name="enable_port_rx_std_bitslip" value="0" />
@@ -387,7 +414,7 @@
   <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
   <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
   <parameter name="enable_port_tx_pma_clkout" value="0" />
-  <parameter name="enable_port_tx_pma_div_clkout" value="1" />
+  <parameter name="enable_port_tx_pma_div_clkout" value="0" />
   <parameter name="enable_port_tx_pma_elecidle" value="0" />
   <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
   <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
@@ -405,7 +432,7 @@
   <parameter name="enable_ports_pipe_sw" value="0" />
   <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
   <parameter name="enable_ports_rx_manual_ppm" value="0" />
-  <parameter name="enable_ports_rx_prbs" value="0" />
+  <parameter name="enable_ports_rx_prbs" value="1" />
   <parameter name="enable_rx_pma_floatingtap" value="0" />
   <parameter name="enable_simple_interface" value="1" />
   <parameter name="enable_split_interface" value="0" />
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
index 15d0d22dae..907ffbb15b 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
@@ -51,6 +51,6 @@ vmap ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150 ./work/
   vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_prbs_accum.sv"                                     -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150
   vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_odi_accel.sv"                                      -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150
   vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_rcfg_arb.sv"                                       -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150_ctgdjgy.sv" -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_rcfg_opt_logic_ctgdjgy.sv"                         -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150
+  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150_jpk6hka.sv" -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150
+  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_rcfg_opt_logic_jpk6hka.sv"                         -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150
   vcom     "$IP_DIR/ip_arria10_phy_10gbase_r_12.vhd"                                                                                                                                                           
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/ip_arria10_phy_10gbase_r_12.qsys b/libraries/technology/ip_arria10/phy_10gbase_r_12/ip_arria10_phy_10gbase_r_12.qsys
index e074402ae2..7bb84ec23b 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/ip_arria10_phy_10gbase_r_12.qsys
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/ip_arria10_phy_10gbase_r_12.qsys
@@ -46,6 +46,32 @@
  <parameter name="timeStamp" value="0" />
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
+ <interface
+   name="reconfig_avmm"
+   internal="xcvr_native_a10_0.reconfig_avmm"
+   type="conduit"
+   dir="end">
+  <port name="reconfig_write" internal="reconfig_write" />
+  <port name="reconfig_read" internal="reconfig_read" />
+  <port name="reconfig_address" internal="reconfig_address" />
+  <port name="reconfig_writedata" internal="reconfig_writedata" />
+  <port name="reconfig_readdata" internal="reconfig_readdata" />
+  <port name="reconfig_waitrequest" internal="reconfig_waitrequest" />
+ </interface>
+ <interface
+   name="reconfig_clk"
+   internal="xcvr_native_a10_0.reconfig_clk"
+   type="conduit"
+   dir="end">
+  <port name="reconfig_clk" internal="reconfig_clk" />
+ </interface>
+ <interface
+   name="reconfig_reset"
+   internal="xcvr_native_a10_0.reconfig_reset"
+   type="conduit"
+   dir="end">
+  <port name="reconfig_reset" internal="reconfig_reset" />
+ </interface>
  <interface
    name="rx_analogreset"
    internal="xcvr_native_a10_0.rx_analogreset"
@@ -165,6 +191,27 @@
    dir="end">
   <port name="rx_parallel_data" internal="rx_parallel_data" />
  </interface>
+ <interface
+   name="rx_prbs_done"
+   internal="xcvr_native_a10_0.rx_prbs_done"
+   type="conduit"
+   dir="end">
+  <port name="rx_prbs_done" internal="rx_prbs_done" />
+ </interface>
+ <interface
+   name="rx_prbs_err"
+   internal="xcvr_native_a10_0.rx_prbs_err"
+   type="conduit"
+   dir="end">
+  <port name="rx_prbs_err" internal="rx_prbs_err" />
+ </interface>
+ <interface
+   name="rx_prbs_err_clr"
+   internal="xcvr_native_a10_0.rx_prbs_err_clr"
+   type="conduit"
+   dir="end">
+  <port name="rx_prbs_err_clr" internal="rx_prbs_err_clr" />
+ </interface>
  <interface
    name="rx_serial_data"
    internal="xcvr_native_a10_0.rx_serial_data"
@@ -172,6 +219,13 @@
    dir="end">
   <port name="rx_serial_data" internal="rx_serial_data" />
  </interface>
+ <interface
+   name="rx_seriallpbken"
+   internal="xcvr_native_a10_0.rx_seriallpbken"
+   type="conduit"
+   dir="end">
+  <port name="rx_seriallpbken" internal="rx_seriallpbken" />
+ </interface>
  <interface
    name="tx_analogreset"
    internal="xcvr_native_a10_0.tx_analogreset"
@@ -266,11 +320,7 @@
  <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
  <interface
    name="tx_pma_div_clkout"
-   internal="xcvr_native_a10_0.tx_pma_div_clkout"
-   type="conduit"
-   dir="end">
-  <port name="tx_pma_div_clkout" internal="tx_pma_div_clkout" />
- </interface>
+   internal="xcvr_native_a10_0.tx_pma_div_clkout" />
  <interface
    name="tx_serial_clk0"
    internal="xcvr_native_a10_0.tx_serial_clk0"
@@ -363,8 +413,8 @@
   <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
   <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
   <parameter name="enable_port_rx_polinv" value="0" />
-  <parameter name="enable_port_rx_seriallpbken" value="0" />
-  <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
+  <parameter name="enable_port_rx_seriallpbken" value="1" />
+  <parameter name="enable_port_rx_seriallpbken_tx" value="1" />
   <parameter name="enable_port_rx_signaldetect" value="0" />
   <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
   <parameter name="enable_port_rx_std_bitslip" value="0" />
@@ -387,7 +437,7 @@
   <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
   <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
   <parameter name="enable_port_tx_pma_clkout" value="0" />
-  <parameter name="enable_port_tx_pma_div_clkout" value="1" />
+  <parameter name="enable_port_tx_pma_div_clkout" value="0" />
   <parameter name="enable_port_tx_pma_elecidle" value="0" />
   <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
   <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
@@ -405,7 +455,7 @@
   <parameter name="enable_ports_pipe_sw" value="0" />
   <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
   <parameter name="enable_ports_rx_manual_ppm" value="0" />
-  <parameter name="enable_ports_rx_prbs" value="0" />
+  <parameter name="enable_ports_rx_prbs" value="1" />
   <parameter name="enable_rx_pma_floatingtap" value="0" />
   <parameter name="enable_simple_interface" value="1" />
   <parameter name="enable_split_interface" value="0" />
@@ -459,12 +509,12 @@
   <parameter name="pma_mode" value="basic" />
   <parameter name="protocol_mode" value="teng_baser_mode" />
   <parameter name="rapid_validate" value="0" />
-  <parameter name="rcfg_enable" value="0" />
+  <parameter name="rcfg_enable" value="1" />
   <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
-  <parameter name="rcfg_h_file_enable" value="0" />
+  <parameter name="rcfg_h_file_enable" value="1" />
   <parameter name="rcfg_iface_enable" value="0" />
-  <parameter name="rcfg_jtag_enable" value="0" />
-  <parameter name="rcfg_mif_file_enable" value="0" />
+  <parameter name="rcfg_jtag_enable" value="1" />
+  <parameter name="rcfg_mif_file_enable" value="1" />
   <parameter name="rcfg_multi_enable" value="0" />
   <parameter name="rcfg_profile_cnt" value="2" />
   <parameter name="rcfg_profile_data0" value="" />
@@ -477,23 +527,23 @@
   <parameter name="rcfg_profile_data7" value="" />
   <parameter name="rcfg_profile_select" value="1" />
   <parameter name="rcfg_reduced_files_enable" value="0" />
-  <parameter name="rcfg_shared" value="0" />
-  <parameter name="rcfg_sv_file_enable" value="0" />
+  <parameter name="rcfg_shared" value="1" />
+  <parameter name="rcfg_sv_file_enable" value="1" />
   <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
   <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
   <parameter name="rx_pma_dfe_fixed_taps" value="3" />
   <parameter name="rx_pma_div_clkout_divider" value="0" />
   <parameter name="rx_ppm_detect_threshold" value="1000" />
-  <parameter name="set_capability_reg_enable" value="0" />
+  <parameter name="set_capability_reg_enable" value="1" />
   <parameter name="set_cdr_refclk_freq" value="644.531250" />
-  <parameter name="set_csr_soft_logic_enable" value="0" />
+  <parameter name="set_csr_soft_logic_enable" value="1" />
   <parameter name="set_data_rate" value="10312.5" />
   <parameter name="set_embedded_debug_enable" value="0" />
   <parameter name="set_enable_calibration" value="0" />
   <parameter name="set_hip_cal_en" value="0" />
   <parameter name="set_odi_soft_logic_enable" value="0" />
   <parameter name="set_pcs_bonding_master" value="Auto" />
-  <parameter name="set_prbs_soft_logic_enable" value="0" />
+  <parameter name="set_prbs_soft_logic_enable" value="1" />
   <parameter name="set_rcfg_emb_strm_enable" value="0" />
   <parameter name="set_user_identifier" value="0" />
   <parameter name="std_low_latency_bypass_enable" value="0" />
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/README.txt b/libraries/technology/ip_arria10/phy_10gbase_r_24/README.txt
deleted file mode 100644
index 6585604593..0000000000
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/README.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-README.txt for $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_24
-
-This ip_arria10_phy_10gbase_r_24.qsys generates a component with 24 10GBASE_R transceivers. For more info see README for phy_10gbase_r.
- 
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
deleted file mode 100644
index 8ce14c7306..0000000000
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
+++ /dev/null
@@ -1,56 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2014
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/phy_10gbase_r_24/generated/sim"
-
-#vlib ./work/         ;# Assume library work already exists
-
-vmap altera_common_sv_packages                              ./work/                            
-vmap ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150 ./work/
-
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/altera_xcvr_native_a10_functions_h.sv"                                                          -work altera_common_sv_packages                             
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_resync.sv"                                                -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_arbiter.sv"                                               -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/mentor/alt_xcvr_resync.sv"                                         -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/mentor/alt_xcvr_arbiter.sv"                                        -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/twentynm_pcs.sv"                                                   -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/twentynm_pma.sv"                                                   -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/twentynm_xcvr_avmm.sv"                                             -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/twentynm_xcvr_native.sv"                                           -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/mentor/twentynm_pcs.sv"                                            -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/mentor/twentynm_pma.sv"                                            -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/mentor/twentynm_xcvr_avmm.sv"                                      -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/mentor/twentynm_xcvr_native.sv"                                    -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/a10_avmm_h.sv"                                                     -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_avmm_csr.sv"                                       -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_prbs_accum.sv"                                     -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_odi_accel.sv"                                      -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_rcfg_arb.sv"                                       -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150_znwfybq.sv" -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vlog -sv "$IP_DIR/../altera_xcvr_native_a10_150/sim/alt_xcvr_native_rcfg_opt_logic_znwfybq.sv"                         -L altera_common_sv_packages -work ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-  vcom     "$IP_DIR/ip_arria10_phy_10gbase_r_24.vhd"                                                                                                                                                              
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/generate_ip.sh b/libraries/technology/ip_arria10/phy_10gbase_r_24/generate_ip.sh
deleted file mode 100755
index c37e0da555..0000000000
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/generate_ip.sh
+++ /dev/null
@@ -1,44 +0,0 @@
-#!/bin/bash
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2015
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>           
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands                             
-#                                                                           
-# This program is free software: you can redistribute it and/or modify      
-# it under the terms of the GNU General Public License as published by      
-# the Free Software Foundation, either version 3 of the License, or         
-# (at your option) any later version.                                       
-#                                                                           
-# This program is distributed in the hope that it will be useful,           
-# but WITHOUT ANY WARRANTY; without even the implied warranty of            
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             
-# GNU General Public License for more details.                              
-#                                                                           
-# You should have received a copy of the GNU General Public License         
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.     
-#
-# -------------------------------------------------------------------------- #
-#
-# Purpose: Generate IP with Qsys
-# Description:
-#   Generate the IP in a separate generated/ subdirectory.
-#
-# Usage:
-#
-#   ./generate_ip.sh
-#
-
-# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
-
-#qsys-generate --help
-
-# Only generate the source IP
-# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
-qsys-generate ip_arria10_phy_10gbase_r_24.qsys \
-              --synthesis=VHDL \
-              --simulation=VHDL \
-              --output-directory=generated \
-              --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
deleted file mode 100644
index 121778e158..0000000000
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_phy_10gbase_r_24
-hdl_library_clause_name = ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
-hdl_lib_uses_synth = 
-hdl_lib_uses_sim = 
-
-hdl_lib_technology = ip_arria10
-
-modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
-
-synth_files =
-    
-test_bench_files = 
-
-quartus_qip_files =
-    generated/ip_arria10_phy_10gbase_r_24.qip
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/ip_arria10_phy_10gbase_r_24.qsys b/libraries/technology/ip_arria10/phy_10gbase_r_24/ip_arria10_phy_10gbase_r_24.qsys
deleted file mode 100644
index b720586fcb..0000000000
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/ip_arria10_phy_10gbase_r_24.qsys
+++ /dev/null
@@ -1,534 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags="INTERNAL_COMPONENT=true"
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element xcvr_native_a10_0
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U4F45I3SGES" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="3" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="true" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="rx_analogreset"
-   internal="xcvr_native_a10_0.rx_analogreset"
-   type="conduit"
-   dir="end">
-  <port name="rx_analogreset" internal="rx_analogreset" />
- </interface>
- <interface
-   name="rx_cal_busy"
-   internal="xcvr_native_a10_0.rx_cal_busy"
-   type="conduit"
-   dir="end">
-  <port name="rx_cal_busy" internal="rx_cal_busy" />
- </interface>
- <interface
-   name="rx_cdr_refclk0"
-   internal="xcvr_native_a10_0.rx_cdr_refclk0"
-   type="conduit"
-   dir="end">
-  <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
- </interface>
- <interface
-   name="rx_clkout"
-   internal="xcvr_native_a10_0.rx_clkout"
-   type="conduit"
-   dir="end">
-  <port name="rx_clkout" internal="rx_clkout" />
- </interface>
- <interface
-   name="rx_control"
-   internal="xcvr_native_a10_0.rx_control"
-   type="conduit"
-   dir="end">
-  <port name="rx_control" internal="rx_control" />
- </interface>
- <interface
-   name="rx_coreclkin"
-   internal="xcvr_native_a10_0.rx_coreclkin"
-   type="conduit"
-   dir="end">
-  <port name="rx_coreclkin" internal="rx_coreclkin" />
- </interface>
- <interface
-   name="rx_digitalreset"
-   internal="xcvr_native_a10_0.rx_digitalreset"
-   type="conduit"
-   dir="end">
-  <port name="rx_digitalreset" internal="rx_digitalreset" />
- </interface>
- <interface
-   name="rx_enh_blk_lock"
-   internal="xcvr_native_a10_0.rx_enh_blk_lock"
-   type="conduit"
-   dir="end">
-  <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
- </interface>
- <interface
-   name="rx_enh_data_valid"
-   internal="xcvr_native_a10_0.rx_enh_data_valid"
-   type="conduit"
-   dir="end">
-  <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
- </interface>
- <interface
-   name="rx_enh_fifo_del"
-   internal="xcvr_native_a10_0.rx_enh_fifo_del"
-   type="conduit"
-   dir="end">
-  <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
- </interface>
- <interface
-   name="rx_enh_fifo_empty"
-   internal="xcvr_native_a10_0.rx_enh_fifo_empty"
-   type="conduit"
-   dir="end">
-  <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
- </interface>
- <interface
-   name="rx_enh_fifo_full"
-   internal="xcvr_native_a10_0.rx_enh_fifo_full"
-   type="conduit"
-   dir="end">
-  <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
- </interface>
- <interface
-   name="rx_enh_fifo_insert"
-   internal="xcvr_native_a10_0.rx_enh_fifo_insert"
-   type="conduit"
-   dir="end">
-  <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
- </interface>
- <interface
-   name="rx_enh_highber"
-   internal="xcvr_native_a10_0.rx_enh_highber"
-   type="conduit"
-   dir="end">
-  <port name="rx_enh_highber" internal="rx_enh_highber" />
- </interface>
- <interface
-   name="rx_is_lockedtodata"
-   internal="xcvr_native_a10_0.rx_is_lockedtodata"
-   type="conduit"
-   dir="end">
-  <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
- </interface>
- <interface
-   name="rx_is_lockedtoref"
-   internal="xcvr_native_a10_0.rx_is_lockedtoref"
-   type="conduit"
-   dir="end">
-  <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
- </interface>
- <interface
-   name="rx_parallel_data"
-   internal="xcvr_native_a10_0.rx_parallel_data"
-   type="conduit"
-   dir="end">
-  <port name="rx_parallel_data" internal="rx_parallel_data" />
- </interface>
- <interface
-   name="rx_serial_data"
-   internal="xcvr_native_a10_0.rx_serial_data"
-   type="conduit"
-   dir="end">
-  <port name="rx_serial_data" internal="rx_serial_data" />
- </interface>
- <interface
-   name="tx_analogreset"
-   internal="xcvr_native_a10_0.tx_analogreset"
-   type="conduit"
-   dir="end">
-  <port name="tx_analogreset" internal="tx_analogreset" />
- </interface>
- <interface
-   name="tx_cal_busy"
-   internal="xcvr_native_a10_0.tx_cal_busy"
-   type="conduit"
-   dir="end">
-  <port name="tx_cal_busy" internal="tx_cal_busy" />
- </interface>
- <interface
-   name="tx_clkout"
-   internal="xcvr_native_a10_0.tx_clkout"
-   type="conduit"
-   dir="end">
-  <port name="tx_clkout" internal="tx_clkout" />
- </interface>
- <interface
-   name="tx_control"
-   internal="xcvr_native_a10_0.tx_control"
-   type="conduit"
-   dir="end">
-  <port name="tx_control" internal="tx_control" />
- </interface>
- <interface
-   name="tx_coreclkin"
-   internal="xcvr_native_a10_0.tx_coreclkin"
-   type="conduit"
-   dir="end">
-  <port name="tx_coreclkin" internal="tx_coreclkin" />
- </interface>
- <interface
-   name="tx_digitalreset"
-   internal="xcvr_native_a10_0.tx_digitalreset"
-   type="conduit"
-   dir="end">
-  <port name="tx_digitalreset" internal="tx_digitalreset" />
- </interface>
- <interface
-   name="tx_enh_data_valid"
-   internal="xcvr_native_a10_0.tx_enh_data_valid"
-   type="conduit"
-   dir="end">
-  <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
- </interface>
- <interface
-   name="tx_enh_fifo_empty"
-   internal="xcvr_native_a10_0.tx_enh_fifo_empty"
-   type="conduit"
-   dir="end">
-  <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
- </interface>
- <interface
-   name="tx_enh_fifo_full"
-   internal="xcvr_native_a10_0.tx_enh_fifo_full"
-   type="conduit"
-   dir="end">
-  <port name="tx_enh_fifo_full" internal="tx_enh_fifo_full" />
- </interface>
- <interface
-   name="tx_enh_fifo_pempty"
-   internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
-   type="conduit"
-   dir="end">
-  <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
- </interface>
- <interface
-   name="tx_enh_fifo_pfull"
-   internal="xcvr_native_a10_0.tx_enh_fifo_pfull"
-   type="conduit"
-   dir="end">
-  <port name="tx_enh_fifo_pfull" internal="tx_enh_fifo_pfull" />
- </interface>
- <interface
-   name="tx_err_ins"
-   internal="xcvr_native_a10_0.tx_err_ins"
-   type="conduit"
-   dir="end">
-  <port name="tx_err_ins" internal="tx_err_ins" />
- </interface>
- <interface
-   name="tx_parallel_data"
-   internal="xcvr_native_a10_0.tx_parallel_data"
-   type="conduit"
-   dir="end">
-  <port name="tx_parallel_data" internal="tx_parallel_data" />
- </interface>
- <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
- <interface
-   name="tx_pma_div_clkout"
-   internal="xcvr_native_a10_0.tx_pma_div_clkout"
-   type="conduit"
-   dir="end">
-  <port name="tx_pma_div_clkout" internal="tx_pma_div_clkout" />
- </interface>
- <interface
-   name="tx_serial_clk0"
-   internal="xcvr_native_a10_0.tx_serial_clk0"
-   type="conduit"
-   dir="end">
-  <port name="tx_serial_clk0" internal="tx_serial_clk0" />
- </interface>
- <interface
-   name="tx_serial_data"
-   internal="xcvr_native_a10_0.tx_serial_data"
-   type="conduit"
-   dir="end">
-  <port name="tx_serial_data" internal="tx_serial_data" />
- </interface>
- <interface
-   name="unused_rx_control"
-   internal="xcvr_native_a10_0.unused_rx_control"
-   type="conduit"
-   dir="end">
-  <port name="unused_rx_control" internal="unused_rx_control" />
- </interface>
- <interface
-   name="unused_rx_parallel_data"
-   internal="xcvr_native_a10_0.unused_rx_parallel_data"
-   type="conduit"
-   dir="end">
-  <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
- </interface>
- <interface
-   name="unused_tx_control"
-   internal="xcvr_native_a10_0.unused_tx_control"
-   type="conduit"
-   dir="end">
-  <port name="unused_tx_control" internal="unused_tx_control" />
- </interface>
- <interface
-   name="unused_tx_parallel_data"
-   internal="xcvr_native_a10_0.unused_tx_parallel_data"
-   type="conduit"
-   dir="end">
-  <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
- </interface>
- <module
-   name="xcvr_native_a10_0"
-   kind="altera_xcvr_native_a10"
-   version="15.0"
-   enabled="1"
-   autoexport="1">
-  <parameter name="base_device" value="NIGHTFURY5ES" />
-  <parameter name="bonded_mode" value="not_bonded" />
-  <parameter name="cdr_refclk_cnt" value="1" />
-  <parameter name="cdr_refclk_select" value="0" />
-  <parameter name="channels" value="24" />
-  <parameter name="design_environment" value="NATIVE" />
-  <parameter name="device" value="10AX115U4F45I3SGES" />
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="duplex_mode" value="duplex" />
-  <parameter name="enable_hard_reset" value="0" />
-  <parameter name="enable_hip" value="0" />
-  <parameter name="enable_parallel_loopback" value="0" />
-  <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
-  <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
-  <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
-  <parameter name="enable_port_pipe_rx_polarity" value="0" />
-  <parameter name="enable_port_rx_enh_bitslip" value="0" />
-  <parameter name="enable_port_rx_enh_blk_lock" value="1" />
-  <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
-  <parameter name="enable_port_rx_enh_crc32_err" value="0" />
-  <parameter name="enable_port_rx_enh_data_valid" value="1" />
-  <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
-  <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
-  <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
-  <parameter name="enable_port_rx_enh_fifo_del" value="1" />
-  <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
-  <parameter name="enable_port_rx_enh_fifo_full" value="1" />
-  <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
-  <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
-  <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
-  <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
-  <parameter name="enable_port_rx_enh_frame" value="0" />
-  <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
-  <parameter name="enable_port_rx_enh_frame_lock" value="0" />
-  <parameter name="enable_port_rx_enh_highber" value="1" />
-  <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
-  <parameter name="enable_port_rx_is_lockedtodata" value="1" />
-  <parameter name="enable_port_rx_is_lockedtoref" value="1" />
-  <parameter name="enable_port_rx_pma_clkout" value="0" />
-  <parameter name="enable_port_rx_pma_clkslip" value="0" />
-  <parameter name="enable_port_rx_pma_div_clkout" value="0" />
-  <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
-  <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
-  <parameter name="enable_port_rx_polinv" value="0" />
-  <parameter name="enable_port_rx_seriallpbken" value="0" />
-  <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
-  <parameter name="enable_port_rx_signaldetect" value="0" />
-  <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
-  <parameter name="enable_port_rx_std_bitslip" value="0" />
-  <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
-  <parameter name="enable_port_rx_std_byterev_ena" value="0" />
-  <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
-  <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
-  <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
-  <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
-  <parameter name="enable_port_rx_std_signaldetect" value="0" />
-  <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
-  <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
-  <parameter name="enable_port_tx_enh_bitslip" value="0" />
-  <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
-  <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
-  <parameter name="enable_port_tx_enh_fifo_full" value="1" />
-  <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
-  <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
-  <parameter name="enable_port_tx_enh_frame" value="0" />
-  <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
-  <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
-  <parameter name="enable_port_tx_pma_clkout" value="0" />
-  <parameter name="enable_port_tx_pma_div_clkout" value="1" />
-  <parameter name="enable_port_tx_pma_elecidle" value="0" />
-  <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
-  <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
-  <parameter name="enable_port_tx_pma_qpipullup" value="0" />
-  <parameter name="enable_port_tx_pma_rxfound" value="0" />
-  <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
-  <parameter name="enable_port_tx_polinv" value="0" />
-  <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
-  <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
-  <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
-  <parameter name="enable_ports_adaptation" value="0" />
-  <parameter name="enable_ports_pipe_g3_analog" value="0" />
-  <parameter name="enable_ports_pipe_hclk" value="0" />
-  <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
-  <parameter name="enable_ports_pipe_sw" value="0" />
-  <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
-  <parameter name="enable_ports_rx_manual_ppm" value="0" />
-  <parameter name="enable_ports_rx_prbs" value="0" />
-  <parameter name="enable_rx_pma_floatingtap" value="0" />
-  <parameter name="enable_simple_interface" value="1" />
-  <parameter name="enable_split_interface" value="0" />
-  <parameter name="enable_transparent_pcs" value="0" />
-  <parameter name="enh_low_latency_enable" value="0" />
-  <parameter name="enh_pcs_pma_width" value="32" />
-  <parameter name="enh_pld_pcs_width" value="66" />
-  <parameter name="enh_rx_64b66b_enable" value="1" />
-  <parameter name="enh_rx_bitslip_enable" value="0" />
-  <parameter name="enh_rx_blksync_enable" value="1" />
-  <parameter name="enh_rx_crcchk_enable" value="0" />
-  <parameter name="enh_rx_descram_enable" value="1" />
-  <parameter name="enh_rx_dispchk_enable" value="0" />
-  <parameter name="enh_rx_frmsync_enable" value="0" />
-  <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
-  <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
-  <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
-  <parameter name="enh_rx_polinv_enable" value="0" />
-  <parameter name="enh_rxfifo_align_del" value="0" />
-  <parameter name="enh_rxfifo_control_del" value="0" />
-  <parameter name="enh_rxfifo_mode" value="10GBase-R" />
-  <parameter name="enh_rxfifo_pempty" value="2" />
-  <parameter name="enh_rxfifo_pfull" value="23" />
-  <parameter name="enh_rxtxfifo_double_width" value="0" />
-  <parameter name="enh_tx_64b66b_enable" value="1" />
-  <parameter name="enh_tx_bitslip_enable" value="0" />
-  <parameter name="enh_tx_crcerr_enable" value="0" />
-  <parameter name="enh_tx_crcgen_enable" value="0" />
-  <parameter name="enh_tx_dispgen_enable" value="0" />
-  <parameter name="enh_tx_frmgen_burst_enable" value="0" />
-  <parameter name="enh_tx_frmgen_enable" value="0" />
-  <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
-  <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
-  <parameter name="enh_tx_krfec_burst_err_len" value="1" />
-  <parameter name="enh_tx_polinv_enable" value="0" />
-  <parameter name="enh_tx_randomdispbit_enable" value="0" />
-  <parameter name="enh_tx_scram_enable" value="1" />
-  <parameter name="enh_tx_scram_seed" value="288230376151711743" />
-  <parameter name="enh_tx_sh_err" value="0" />
-  <parameter name="enh_txfifo_mode" value="Phase compensation" />
-  <parameter name="enh_txfifo_pempty" value="2" />
-  <parameter name="enh_txfifo_pfull" value="11" />
-  <parameter name="generate_add_hdl_instance_example" value="0" />
-  <parameter name="generate_docs" value="1" />
-  <parameter name="message_level" value="error" />
-  <parameter name="number_physical_bonding_clocks" value="1" />
-  <parameter name="pcie_rate_match" value="Bypass" />
-  <parameter name="pcs_direct_width" value="8" />
-  <parameter name="pll_select" value="0" />
-  <parameter name="plls" value="1" />
-  <parameter name="pma_mode" value="basic" />
-  <parameter name="protocol_mode" value="teng_baser_mode" />
-  <parameter name="rapid_validate" value="0" />
-  <parameter name="rcfg_enable" value="0" />
-  <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
-  <parameter name="rcfg_h_file_enable" value="0" />
-  <parameter name="rcfg_iface_enable" value="0" />
-  <parameter name="rcfg_jtag_enable" value="0" />
-  <parameter name="rcfg_mif_file_enable" value="0" />
-  <parameter name="rcfg_multi_enable" value="0" />
-  <parameter name="rcfg_profile_cnt" value="2" />
-  <parameter name="rcfg_profile_data0" value="" />
-  <parameter name="rcfg_profile_data1" value="" />
-  <parameter name="rcfg_profile_data2" value="" />
-  <parameter name="rcfg_profile_data3" value="" />
-  <parameter name="rcfg_profile_data4" value="" />
-  <parameter name="rcfg_profile_data5" value="" />
-  <parameter name="rcfg_profile_data6" value="" />
-  <parameter name="rcfg_profile_data7" value="" />
-  <parameter name="rcfg_profile_select" value="1" />
-  <parameter name="rcfg_reduced_files_enable" value="0" />
-  <parameter name="rcfg_shared" value="0" />
-  <parameter name="rcfg_sv_file_enable" value="0" />
-  <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
-  <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
-  <parameter name="rx_pma_dfe_fixed_taps" value="3" />
-  <parameter name="rx_pma_div_clkout_divider" value="0" />
-  <parameter name="rx_ppm_detect_threshold" value="1000" />
-  <parameter name="set_capability_reg_enable" value="0" />
-  <parameter name="set_cdr_refclk_freq" value="644.531250" />
-  <parameter name="set_csr_soft_logic_enable" value="0" />
-  <parameter name="set_data_rate" value="10312.5" />
-  <parameter name="set_embedded_debug_enable" value="0" />
-  <parameter name="set_enable_calibration" value="0" />
-  <parameter name="set_hip_cal_en" value="0" />
-  <parameter name="set_odi_soft_logic_enable" value="0" />
-  <parameter name="set_pcs_bonding_master" value="Auto" />
-  <parameter name="set_prbs_soft_logic_enable" value="0" />
-  <parameter name="set_rcfg_emb_strm_enable" value="0" />
-  <parameter name="set_user_identifier" value="0" />
-  <parameter name="std_low_latency_bypass_enable" value="0" />
-  <parameter name="std_pcs_pma_width" value="10" />
-  <parameter name="std_rx_8b10b_enable" value="0" />
-  <parameter name="std_rx_bitrev_enable" value="0" />
-  <parameter name="std_rx_byte_deser_mode" value="Disabled" />
-  <parameter name="std_rx_byterev_enable" value="0" />
-  <parameter name="std_rx_pcfifo_mode" value="low_latency" />
-  <parameter name="std_rx_polinv_enable" value="0" />
-  <parameter name="std_rx_rmfifo_mode" value="disabled" />
-  <parameter name="std_rx_rmfifo_pattern_n" value="0" />
-  <parameter name="std_rx_rmfifo_pattern_p" value="0" />
-  <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
-  <parameter name="std_rx_word_aligner_mode" value="bitslip" />
-  <parameter name="std_rx_word_aligner_pattern" value="0" />
-  <parameter name="std_rx_word_aligner_pattern_len" value="7" />
-  <parameter name="std_rx_word_aligner_renumber" value="3" />
-  <parameter name="std_rx_word_aligner_rgnumber" value="3" />
-  <parameter name="std_rx_word_aligner_rknumber" value="3" />
-  <parameter name="std_rx_word_aligner_rvnumber" value="0" />
-  <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
-  <parameter name="std_tx_8b10b_enable" value="0" />
-  <parameter name="std_tx_bitrev_enable" value="0" />
-  <parameter name="std_tx_bitslip_enable" value="0" />
-  <parameter name="std_tx_byte_ser_mode" value="Disabled" />
-  <parameter name="std_tx_byterev_enable" value="0" />
-  <parameter name="std_tx_pcfifo_mode" value="low_latency" />
-  <parameter name="std_tx_polinv_enable" value="0" />
-  <parameter name="support_mode" value="user_mode" />
-  <parameter name="tx_pma_clk_div" value="1" />
-  <parameter name="tx_pma_div_clkout_divider" value="33" />
-  <parameter name="validation_rule_select" value="" />
- </module>
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
-</system>
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys b/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys
index 1fbc459f9c..3702ad7e74 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys
@@ -88,7 +88,39 @@
    dir="end">
   <port name="pll_refclk0" internal="pll_refclk0" />
  </interface>
- <interface name="tx_serial_clk" internal="xcvr_atx_pll_a10_0.tx_serial_clk" />
+ <interface
+   name="reconfig_avmm0"
+   internal="xcvr_atx_pll_a10_0.reconfig_avmm0"
+   type="avalon"
+   dir="end">
+  <port name="reconfig_write0" internal="reconfig_write0" />
+  <port name="reconfig_read0" internal="reconfig_read0" />
+  <port name="reconfig_address0" internal="reconfig_address0" />
+  <port name="reconfig_writedata0" internal="reconfig_writedata0" />
+  <port name="reconfig_readdata0" internal="reconfig_readdata0" />
+  <port name="reconfig_waitrequest0" internal="reconfig_waitrequest0" />
+ </interface>
+ <interface
+   name="reconfig_clk0"
+   internal="xcvr_atx_pll_a10_0.reconfig_clk0"
+   type="clock"
+   dir="end">
+  <port name="reconfig_clk0" internal="reconfig_clk0" />
+ </interface>
+ <interface
+   name="reconfig_reset0"
+   internal="xcvr_atx_pll_a10_0.reconfig_reset0"
+   type="reset"
+   dir="end">
+  <port name="reconfig_reset0" internal="reconfig_reset0" />
+ </interface>
+ <interface
+   name="tx_serial_clk"
+   internal="xcvr_atx_pll_a10_0.tx_serial_clk"
+   type="hssi_serial_clock"
+   dir="start">
+  <port name="tx_serial_clk" internal="tx_serial_clk" />
+ </interface>
  <module
    name="xcvr_atx_pll_a10_0"
    kind="altera_xcvr_atx_pll_a10"
@@ -100,7 +132,7 @@
   <parameter name="device" value="10AX115U4F45I3SGES" />
   <parameter name="device_family" value="Arria 10" />
   <parameter name="enable_16G_path" value="0" />
-  <parameter name="enable_8G_path" value="0" />
+  <parameter name="enable_8G_path" value="1" />
   <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
   <parameter name="enable_bonding_clks" value="0" />
   <parameter name="enable_cascade_out" value="0" />
@@ -115,7 +147,7 @@
   <parameter name="enable_pcie_clk" value="0" />
   <parameter name="enable_pld_atx_cal_busy_port" value="1" />
   <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
-  <parameter name="enable_pll_reconfig" value="0" />
+  <parameter name="enable_pll_reconfig" value="1" />
   <parameter name="generate_add_hdl_instance_example" value="0" />
   <parameter name="generate_docs" value="1" />
   <parameter name="mcgb_aux_clkin_cnt" value="0" />
@@ -126,23 +158,23 @@
   <parameter name="prot_mode" value="Basic" />
   <parameter name="rcfg_debug" value="0" />
   <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
-  <parameter name="rcfg_h_file_enable" value="0" />
-  <parameter name="rcfg_jtag_enable" value="0" />
-  <parameter name="rcfg_mif_file_enable" value="0" />
+  <parameter name="rcfg_h_file_enable" value="1" />
+  <parameter name="rcfg_jtag_enable" value="1" />
+  <parameter name="rcfg_mif_file_enable" value="1" />
   <parameter name="rcfg_multi_enable" value="0" />
   <parameter name="rcfg_param_vals1" value="" />
   <parameter name="rcfg_param_vals2" value="" />
   <parameter name="rcfg_profile_cnt" value="2" />
   <parameter name="rcfg_profile_select" value="1" />
-  <parameter name="rcfg_sv_file_enable" value="0" />
+  <parameter name="rcfg_sv_file_enable" value="1" />
   <parameter name="rcfg_txt_file_enable" value="0" />
   <parameter name="refclk_cnt" value="1" />
   <parameter name="refclk_index" value="0" />
   <parameter name="select_manual_config" value="false" />
   <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
   <parameter name="set_auto_reference_clock_frequency" value="644.53125" />
-  <parameter name="set_capability_reg_enable" value="0" />
-  <parameter name="set_csr_soft_logic_enable" value="0" />
+  <parameter name="set_capability_reg_enable" value="1" />
+  <parameter name="set_csr_soft_logic_enable" value="1" />
   <parameter name="set_fref_clock_frequency" value="100.0" />
   <parameter name="set_hip_cal_en" value="0" />
   <parameter name="set_k_counter" value="1" />
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1.qsys
index 6fa8aa5113..f6444eb73c 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1.qsys
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1.qsys
@@ -152,25 +152,25 @@
    autoexport="1">
   <parameter name="CHANNELS" value="1" />
   <parameter name="PLLS" value="1" />
-  <parameter name="REDUCED_SIM_TIME" value="0" />
+  <parameter name="REDUCED_SIM_TIME" value="1" />
   <parameter name="RX_ENABLE" value="1" />
-  <parameter name="RX_PER_CHANNEL" value="0" />
+  <parameter name="RX_PER_CHANNEL" value="1" />
   <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
   <parameter name="SYNCHRONIZE_RESET" value="1" />
   <parameter name="SYS_CLK_IN_MHZ" value="156" />
   <parameter name="TX_ENABLE" value="1" />
   <parameter name="TX_PER_CHANNEL" value="0" />
   <parameter name="TX_PLL_ENABLE" value="1" />
-  <parameter name="T_PLL_LOCK_HYST" value="0" />
+  <parameter name="T_PLL_LOCK_HYST" value="100" />
   <parameter name="T_PLL_POWERDOWN" value="1000" />
   <parameter name="T_RX_ANALOGRESET" value="40" />
-  <parameter name="T_RX_DIGITALRESET" value="4000" />
+  <parameter name="T_RX_DIGITALRESET" value="400000" />
   <parameter name="T_TX_DIGITALRESET" value="20" />
   <parameter name="device_family" value="Arria 10" />
   <parameter name="gui_pll_cal_busy" value="0" />
   <parameter name="gui_rx_auto_reset" value="0" />
   <parameter name="gui_split_interfaces" value="0" />
-  <parameter name="gui_tx_auto_reset" value="1" />
+  <parameter name="gui_tx_auto_reset" value="0" />
  </module>
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
  <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/ip_arria10_transceiver_reset_controller_12.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_12/ip_arria10_transceiver_reset_controller_12.qsys
index 9d9271e46a..835693e2b7 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/ip_arria10_transceiver_reset_controller_12.qsys
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/ip_arria10_transceiver_reset_controller_12.qsys
@@ -154,23 +154,23 @@
   <parameter name="PLLS" value="1" />
   <parameter name="REDUCED_SIM_TIME" value="1" />
   <parameter name="RX_ENABLE" value="1" />
-  <parameter name="RX_PER_CHANNEL" value="0" />
+  <parameter name="RX_PER_CHANNEL" value="1" />
   <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
   <parameter name="SYNCHRONIZE_RESET" value="1" />
-  <parameter name="SYS_CLK_IN_MHZ" value="200" />
+  <parameter name="SYS_CLK_IN_MHZ" value="156" />
   <parameter name="TX_ENABLE" value="1" />
   <parameter name="TX_PER_CHANNEL" value="0" />
   <parameter name="TX_PLL_ENABLE" value="1" />
-  <parameter name="T_PLL_LOCK_HYST" value="0" />
+  <parameter name="T_PLL_LOCK_HYST" value="100" />
   <parameter name="T_PLL_POWERDOWN" value="1000" />
   <parameter name="T_RX_ANALOGRESET" value="40" />
-  <parameter name="T_RX_DIGITALRESET" value="4000" />
+  <parameter name="T_RX_DIGITALRESET" value="400000" />
   <parameter name="T_TX_DIGITALRESET" value="20" />
   <parameter name="device_family" value="Arria 10" />
   <parameter name="gui_pll_cal_busy" value="0" />
   <parameter name="gui_rx_auto_reset" value="0" />
   <parameter name="gui_split_interfaces" value="0" />
-  <parameter name="gui_tx_auto_reset" value="1" />
+  <parameter name="gui_tx_auto_reset" value="0" />
  </module>
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
  <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
deleted file mode 100644
index 368d36c564..0000000000
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+++ /dev/null
@@ -1,43 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2015
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_controller_24/generated/sim"
-
-#vlib ./work/         ;# Assume library work already exists
-
-vmap ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150 ./work/
-
-  vlog -sv "$IP_DIR/../altera_xcvr_reset_control_150/sim/altera_xcvr_functions.sv"            -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150
-  vlog -sv "$IP_DIR/../altera_xcvr_reset_control_150/sim/mentor/altera_xcvr_functions.sv"     -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150
-  vlog -sv "$IP_DIR/../altera_xcvr_reset_control_150/sim/alt_xcvr_resync.sv"                  -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150
-  vlog -sv "$IP_DIR/../altera_xcvr_reset_control_150/sim/mentor/alt_xcvr_resync.sv"           -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150
-  vlog -sv "$IP_DIR/../altera_xcvr_reset_control_150/sim/altera_xcvr_reset_control.sv"        -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150
-  vlog -sv "$IP_DIR/../altera_xcvr_reset_control_150/sim/alt_xcvr_reset_counter.sv"           -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150
-  vlog -sv "$IP_DIR/../altera_xcvr_reset_control_150/sim/mentor/altera_xcvr_reset_control.sv" -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150
-  vlog -sv "$IP_DIR/../altera_xcvr_reset_control_150/sim/mentor/alt_xcvr_reset_counter.sv"    -work ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150
-  vcom     "$IP_DIR/ip_arria10_transceiver_reset_controller_24.vhd"                                                                                                         
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh
deleted file mode 100755
index 0b67c011a2..0000000000
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/generate_ip.sh
+++ /dev/null
@@ -1,44 +0,0 @@
-#!/bin/bash
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2015                                                        
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>           
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands                             
-#                                                                           
-# This program is free software: you can redistribute it and/or modify      
-# it under the terms of the GNU General Public License as published by      
-# the Free Software Foundation, either version 3 of the License, or         
-# (at your option) any later version.                                       
-#                                                                           
-# This program is distributed in the hope that it will be useful,           
-# but WITHOUT ANY WARRANTY; without even the implied warranty of            
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             
-# GNU General Public License for more details.                              
-#                                                                           
-# You should have received a copy of the GNU General Public License         
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.     
-#
-# -------------------------------------------------------------------------- #
-#
-# Purpose: Generate IP with Qsys
-# Description:
-#   Generate the IP in a separate generated/ subdirectory.
-#
-# Usage:
-#
-#   ./generate_ip.sh
-#
-
-# Tool settings for selected target "unb2" with arria10
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
-
-#qsys-generate --help
-
-# Only generate the source IP
-# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
-qsys-generate ip_arria10_transceiver_reset_controller_24.qsys \
-              --synthesis=VHDL \
-              --simulation=VHDL \
-              --output-directory=generated \
-              --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
deleted file mode 100644
index 9fb365e911..0000000000
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_arria10_transceiver_reset_controller_24
-hdl_library_clause_name = ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150
-hdl_lib_uses_synth = 
-hdl_lib_uses_sim = 
-
-hdl_lib_technology = ip_arria10
-
-modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
-
-synth_files =
-    
-test_bench_files = 
-
-quartus_qip_files =
-    generated/ip_arria10_transceiver_reset_controller_24.qip
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/ip_arria10_transceiver_reset_controller_24.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_24/ip_arria10_transceiver_reset_controller_24.qsys
deleted file mode 100644
index 3c6d245d5f..0000000000
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/ip_arria10_transceiver_reset_controller_24.qsys
+++ /dev/null
@@ -1,178 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags="INTERNAL_COMPONENT=true"
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element transceiver_reset_controller_inst
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U4F45I3SGES" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="3" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="true" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="clock"
-   internal="transceiver_reset_controller_inst.clock"
-   type="clock"
-   dir="end">
-  <port name="clock" internal="clock" />
- </interface>
- <interface
-   name="pll_locked"
-   internal="transceiver_reset_controller_inst.pll_locked"
-   type="conduit"
-   dir="end">
-  <port name="pll_locked" internal="pll_locked" />
- </interface>
- <interface
-   name="pll_powerdown"
-   internal="transceiver_reset_controller_inst.pll_powerdown"
-   type="conduit"
-   dir="end">
-  <port name="pll_powerdown" internal="pll_powerdown" />
- </interface>
- <interface
-   name="pll_select"
-   internal="transceiver_reset_controller_inst.pll_select"
-   type="conduit"
-   dir="end">
-  <port name="pll_select" internal="pll_select" />
- </interface>
- <interface
-   name="reset"
-   internal="transceiver_reset_controller_inst.reset"
-   type="reset"
-   dir="end">
-  <port name="reset" internal="reset" />
- </interface>
- <interface
-   name="rx_analogreset"
-   internal="transceiver_reset_controller_inst.rx_analogreset"
-   type="conduit"
-   dir="end">
-  <port name="rx_analogreset" internal="rx_analogreset" />
- </interface>
- <interface
-   name="rx_cal_busy"
-   internal="transceiver_reset_controller_inst.rx_cal_busy"
-   type="conduit"
-   dir="end">
-  <port name="rx_cal_busy" internal="rx_cal_busy" />
- </interface>
- <interface
-   name="rx_digitalreset"
-   internal="transceiver_reset_controller_inst.rx_digitalreset"
-   type="conduit"
-   dir="end">
-  <port name="rx_digitalreset" internal="rx_digitalreset" />
- </interface>
- <interface
-   name="rx_is_lockedtodata"
-   internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
-   type="conduit"
-   dir="end">
-  <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
- </interface>
- <interface
-   name="rx_ready"
-   internal="transceiver_reset_controller_inst.rx_ready"
-   type="conduit"
-   dir="end">
-  <port name="rx_ready" internal="rx_ready" />
- </interface>
- <interface
-   name="tx_analogreset"
-   internal="transceiver_reset_controller_inst.tx_analogreset"
-   type="conduit"
-   dir="end">
-  <port name="tx_analogreset" internal="tx_analogreset" />
- </interface>
- <interface
-   name="tx_cal_busy"
-   internal="transceiver_reset_controller_inst.tx_cal_busy"
-   type="conduit"
-   dir="end">
-  <port name="tx_cal_busy" internal="tx_cal_busy" />
- </interface>
- <interface
-   name="tx_digitalreset"
-   internal="transceiver_reset_controller_inst.tx_digitalreset"
-   type="conduit"
-   dir="end">
-  <port name="tx_digitalreset" internal="tx_digitalreset" />
- </interface>
- <interface
-   name="tx_ready"
-   internal="transceiver_reset_controller_inst.tx_ready"
-   type="conduit"
-   dir="end">
-  <port name="tx_ready" internal="tx_ready" />
- </interface>
- <module
-   name="transceiver_reset_controller_inst"
-   kind="altera_xcvr_reset_control"
-   version="15.0"
-   enabled="1"
-   autoexport="1">
-  <parameter name="CHANNELS" value="24" />
-  <parameter name="PLLS" value="1" />
-  <parameter name="REDUCED_SIM_TIME" value="1" />
-  <parameter name="RX_ENABLE" value="1" />
-  <parameter name="RX_PER_CHANNEL" value="0" />
-  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
-  <parameter name="SYNCHRONIZE_RESET" value="1" />
-  <parameter name="SYS_CLK_IN_MHZ" value="200" />
-  <parameter name="TX_ENABLE" value="1" />
-  <parameter name="TX_PER_CHANNEL" value="0" />
-  <parameter name="TX_PLL_ENABLE" value="1" />
-  <parameter name="T_PLL_LOCK_HYST" value="0" />
-  <parameter name="T_PLL_POWERDOWN" value="1000" />
-  <parameter name="T_RX_ANALOGRESET" value="40" />
-  <parameter name="T_RX_DIGITALRESET" value="4000" />
-  <parameter name="T_TX_DIGITALRESET" value="20" />
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="gui_pll_cal_busy" value="0" />
-  <parameter name="gui_rx_auto_reset" value="0" />
-  <parameter name="gui_split_interfaces" value="0" />
-  <parameter name="gui_tx_auto_reset" value="1" />
- </module>
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
-</system>
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/ip_arria10_transceiver_reset_controller_48.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_48/ip_arria10_transceiver_reset_controller_48.qsys
deleted file mode 100644
index 6ec28e46f7..0000000000
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/ip_arria10_transceiver_reset_controller_48.qsys
+++ /dev/null
@@ -1,178 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags="INTERNAL_COMPONENT=true"
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element transceiver_reset_controller_inst
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U4F45I3SGES" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="3" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="true" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="clock"
-   internal="transceiver_reset_controller_inst.clock"
-   type="clock"
-   dir="end">
-  <port name="clock" internal="clock" />
- </interface>
- <interface
-   name="pll_locked"
-   internal="transceiver_reset_controller_inst.pll_locked"
-   type="conduit"
-   dir="end">
-  <port name="pll_locked" internal="pll_locked" />
- </interface>
- <interface
-   name="pll_powerdown"
-   internal="transceiver_reset_controller_inst.pll_powerdown"
-   type="conduit"
-   dir="end">
-  <port name="pll_powerdown" internal="pll_powerdown" />
- </interface>
- <interface
-   name="pll_select"
-   internal="transceiver_reset_controller_inst.pll_select"
-   type="conduit"
-   dir="end">
-  <port name="pll_select" internal="pll_select" />
- </interface>
- <interface
-   name="reset"
-   internal="transceiver_reset_controller_inst.reset"
-   type="reset"
-   dir="end">
-  <port name="reset" internal="reset" />
- </interface>
- <interface
-   name="rx_analogreset"
-   internal="transceiver_reset_controller_inst.rx_analogreset"
-   type="conduit"
-   dir="end">
-  <port name="rx_analogreset" internal="rx_analogreset" />
- </interface>
- <interface
-   name="rx_cal_busy"
-   internal="transceiver_reset_controller_inst.rx_cal_busy"
-   type="conduit"
-   dir="end">
-  <port name="rx_cal_busy" internal="rx_cal_busy" />
- </interface>
- <interface
-   name="rx_digitalreset"
-   internal="transceiver_reset_controller_inst.rx_digitalreset"
-   type="conduit"
-   dir="end">
-  <port name="rx_digitalreset" internal="rx_digitalreset" />
- </interface>
- <interface
-   name="rx_is_lockedtodata"
-   internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
-   type="conduit"
-   dir="end">
-  <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
- </interface>
- <interface
-   name="rx_ready"
-   internal="transceiver_reset_controller_inst.rx_ready"
-   type="conduit"
-   dir="end">
-  <port name="rx_ready" internal="rx_ready" />
- </interface>
- <interface
-   name="tx_analogreset"
-   internal="transceiver_reset_controller_inst.tx_analogreset"
-   type="conduit"
-   dir="end">
-  <port name="tx_analogreset" internal="tx_analogreset" />
- </interface>
- <interface
-   name="tx_cal_busy"
-   internal="transceiver_reset_controller_inst.tx_cal_busy"
-   type="conduit"
-   dir="end">
-  <port name="tx_cal_busy" internal="tx_cal_busy" />
- </interface>
- <interface
-   name="tx_digitalreset"
-   internal="transceiver_reset_controller_inst.tx_digitalreset"
-   type="conduit"
-   dir="end">
-  <port name="tx_digitalreset" internal="tx_digitalreset" />
- </interface>
- <interface
-   name="tx_ready"
-   internal="transceiver_reset_controller_inst.tx_ready"
-   type="conduit"
-   dir="end">
-  <port name="tx_ready" internal="tx_ready" />
- </interface>
- <module
-   name="transceiver_reset_controller_inst"
-   kind="altera_xcvr_reset_control"
-   version="15.0"
-   enabled="1"
-   autoexport="1">
-  <parameter name="CHANNELS" value="48" />
-  <parameter name="PLLS" value="1" />
-  <parameter name="REDUCED_SIM_TIME" value="1" />
-  <parameter name="RX_ENABLE" value="1" />
-  <parameter name="RX_PER_CHANNEL" value="0" />
-  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
-  <parameter name="SYNCHRONIZE_RESET" value="1" />
-  <parameter name="SYS_CLK_IN_MHZ" value="200" />
-  <parameter name="TX_ENABLE" value="1" />
-  <parameter name="TX_PER_CHANNEL" value="0" />
-  <parameter name="TX_PLL_ENABLE" value="1" />
-  <parameter name="T_PLL_LOCK_HYST" value="0" />
-  <parameter name="T_PLL_POWERDOWN" value="1000" />
-  <parameter name="T_RX_ANALOGRESET" value="40" />
-  <parameter name="T_RX_DIGITALRESET" value="4000" />
-  <parameter name="T_TX_DIGITALRESET" value="20" />
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="gui_pll_cal_busy" value="0" />
-  <parameter name="gui_rx_auto_reset" value="0" />
-  <parameter name="gui_split_interfaces" value="0" />
-  <parameter name="gui_tx_auto_reset" value="1" />
- </module>
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
-</system>
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/transceiver_reset_controller_48.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_48/transceiver_reset_controller_48.qsys
deleted file mode 100644
index 6ec28e46f7..0000000000
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/transceiver_reset_controller_48.qsys
+++ /dev/null
@@ -1,178 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags="INTERNAL_COMPONENT=true"
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
-   element transceiver_reset_controller_inst
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U4F45I3SGES" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="3" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="true" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="clock"
-   internal="transceiver_reset_controller_inst.clock"
-   type="clock"
-   dir="end">
-  <port name="clock" internal="clock" />
- </interface>
- <interface
-   name="pll_locked"
-   internal="transceiver_reset_controller_inst.pll_locked"
-   type="conduit"
-   dir="end">
-  <port name="pll_locked" internal="pll_locked" />
- </interface>
- <interface
-   name="pll_powerdown"
-   internal="transceiver_reset_controller_inst.pll_powerdown"
-   type="conduit"
-   dir="end">
-  <port name="pll_powerdown" internal="pll_powerdown" />
- </interface>
- <interface
-   name="pll_select"
-   internal="transceiver_reset_controller_inst.pll_select"
-   type="conduit"
-   dir="end">
-  <port name="pll_select" internal="pll_select" />
- </interface>
- <interface
-   name="reset"
-   internal="transceiver_reset_controller_inst.reset"
-   type="reset"
-   dir="end">
-  <port name="reset" internal="reset" />
- </interface>
- <interface
-   name="rx_analogreset"
-   internal="transceiver_reset_controller_inst.rx_analogreset"
-   type="conduit"
-   dir="end">
-  <port name="rx_analogreset" internal="rx_analogreset" />
- </interface>
- <interface
-   name="rx_cal_busy"
-   internal="transceiver_reset_controller_inst.rx_cal_busy"
-   type="conduit"
-   dir="end">
-  <port name="rx_cal_busy" internal="rx_cal_busy" />
- </interface>
- <interface
-   name="rx_digitalreset"
-   internal="transceiver_reset_controller_inst.rx_digitalreset"
-   type="conduit"
-   dir="end">
-  <port name="rx_digitalreset" internal="rx_digitalreset" />
- </interface>
- <interface
-   name="rx_is_lockedtodata"
-   internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
-   type="conduit"
-   dir="end">
-  <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
- </interface>
- <interface
-   name="rx_ready"
-   internal="transceiver_reset_controller_inst.rx_ready"
-   type="conduit"
-   dir="end">
-  <port name="rx_ready" internal="rx_ready" />
- </interface>
- <interface
-   name="tx_analogreset"
-   internal="transceiver_reset_controller_inst.tx_analogreset"
-   type="conduit"
-   dir="end">
-  <port name="tx_analogreset" internal="tx_analogreset" />
- </interface>
- <interface
-   name="tx_cal_busy"
-   internal="transceiver_reset_controller_inst.tx_cal_busy"
-   type="conduit"
-   dir="end">
-  <port name="tx_cal_busy" internal="tx_cal_busy" />
- </interface>
- <interface
-   name="tx_digitalreset"
-   internal="transceiver_reset_controller_inst.tx_digitalreset"
-   type="conduit"
-   dir="end">
-  <port name="tx_digitalreset" internal="tx_digitalreset" />
- </interface>
- <interface
-   name="tx_ready"
-   internal="transceiver_reset_controller_inst.tx_ready"
-   type="conduit"
-   dir="end">
-  <port name="tx_ready" internal="tx_ready" />
- </interface>
- <module
-   name="transceiver_reset_controller_inst"
-   kind="altera_xcvr_reset_control"
-   version="15.0"
-   enabled="1"
-   autoexport="1">
-  <parameter name="CHANNELS" value="48" />
-  <parameter name="PLLS" value="1" />
-  <parameter name="REDUCED_SIM_TIME" value="1" />
-  <parameter name="RX_ENABLE" value="1" />
-  <parameter name="RX_PER_CHANNEL" value="0" />
-  <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
-  <parameter name="SYNCHRONIZE_RESET" value="1" />
-  <parameter name="SYS_CLK_IN_MHZ" value="200" />
-  <parameter name="TX_ENABLE" value="1" />
-  <parameter name="TX_PER_CHANNEL" value="0" />
-  <parameter name="TX_PLL_ENABLE" value="1" />
-  <parameter name="T_PLL_LOCK_HYST" value="0" />
-  <parameter name="T_PLL_POWERDOWN" value="1000" />
-  <parameter name="T_RX_ANALOGRESET" value="40" />
-  <parameter name="T_RX_DIGITALRESET" value="4000" />
-  <parameter name="T_TX_DIGITALRESET" value="20" />
-  <parameter name="device_family" value="Arria 10" />
-  <parameter name="gui_pll_cal_busy" value="0" />
-  <parameter name="gui_rx_auto_reset" value="0" />
-  <parameter name="gui_split_interfaces" value="0" />
-  <parameter name="gui_tx_auto_reset" value="1" />
- </module>
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
-</system>
-- 
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