diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE.sdc b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..fbcc86fb1bb44ec25f621483883c32ce0ba743e3
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE.sdc
@@ -0,0 +1 @@
+#set_false_path -from [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}] -to [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
index f1c33fdf48950e86fe3c421d5247847ee5bfb3de..5ed2e6172e590aaeb9bce084183f38436254ffdd 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
@@ -31,7 +31,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY unb2_test_10GbE IS
GENERIC (
g_design_name : STRING := "unb2_test_10GbE";
- g_design_note : STRING := "10GbE: 6xQSFP,24xBCK";
+ g_design_note : STRING := "10GbE: 6xQSFP";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
@@ -67,8 +67,8 @@ ENTITY unb2_test_10GbE IS
BCK_REF_CLK : IN STD_LOGIC; -- Clock 10GbE back lower 24 lines
-- back transceivers
- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+-- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+-- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
-- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
-- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
index f3904c6d4458af0edae5f2f59b8d6d522a39d3c4..b0486490e96130f429d63f3fa30b02838dfe559c 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
@@ -2,7 +2,7 @@ hdl_lib_name = unb2_test_all
hdl_library_clause_name = unb2_test_all_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
-hdl_lib_excludes =
+hdl_lib_excludes = ip_arria10_ddr4_8g_2400 ip_arria10_ddr4_4g_1600 ip_arria10_phy_10gbase_r ip_arria10_transceiver_reset_controller_1
hdl_lib_technology = ip_arria10
@@ -19,12 +19,15 @@ synth_top_level_entity =
quartus_copy_files =
../../quartus/qsys_unb2_test.qsys .
+ ../../quartus/quartus.ini .
+ ../../quartus/pm_uc_ES1_ww05p1.hex .
../../src/hex hex
quartus_qsf_files =
$RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_sdc_files =
+ quartus/unb2_test_10GbE.sdc
$RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
quartus_tcl_files =
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_10GbE.sdc b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_10GbE.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..fbcc86fb1bb44ec25f621483883c32ce0ba743e3
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_10GbE.sdc
@@ -0,0 +1 @@
+#set_false_path -from [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}] -to [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
index 383e7956da49c6c8c6c2f0cc8627c03896cd324d..f03ffc9c951490f59f5c76eb9d6839f2c36dea94 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
@@ -32,7 +32,7 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY unb2_test_all IS
GENERIC (
g_design_name : STRING := "unb2_test_all";
- g_design_note : STRING := "Test design with all";
+ g_design_note : STRING := "Test design with: 6xQSFP,DDR4";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
@@ -72,17 +72,17 @@ ENTITY unb2_test_all IS
MB_II_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_II
-- back transceivers
- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+-- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+-- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
-- ring transceivers
- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+-- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+-- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+-- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+-- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : INOUT STD_LOGIC;
PMBUS_SD : INOUT STD_LOGIC;
@@ -165,17 +165,17 @@ BEGIN
MB_II_REF_CLK => MB_II_REF_CLK,
-- back transceivers
- BCK_RX => BCK_RX,
- BCK_TX => BCK_TX,
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
BCK_SDA => BCK_SDA,
BCK_SCL => BCK_SCL,
BCK_ERR => BCK_ERR,
-- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
-- pmbus
PMBUS_SC => PMBUS_SC,
PMBUS_SD => PMBUS_SD,
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 67e0d3e18dbfcf95191fd85c807d68155ae6b81b..5f4dad9d91f88a02d7cee453e5909febf5a8a11d 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -84,8 +84,8 @@ ENTITY unb2_test IS
MB_II_REF_CLK : IN STD_LOGIC := '0'; -- Reference clock for MB_II
-- back transceivers
- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0) := (OTHERS=>'0');
- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ --BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0) := (OTHERS=>'0');
+ --BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
--BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
@@ -147,7 +147,7 @@ ARCHITECTURE str OF unb2_test IS
CONSTANT c_use_10GbE : BOOLEAN := g_design_name="unb2_test_10GbE" OR g_design_name="unb2_test_all";
CONSTANT c_use_10GbE_qsfp : BOOLEAN := c_use_10GbE;
CONSTANT c_use_10GbE_ring : BOOLEAN := FALSE;--c_use_10GbE;
- CONSTANT c_use_10GbE_back0 : BOOLEAN := c_use_10GbE;
+ CONSTANT c_use_10GbE_back0 : BOOLEAN := FALSE;--c_use_10GbE;
CONSTANT c_use_10GbE_back1 : BOOLEAN := FALSE;--c_use_10GbE;
CONSTANT c_use_MB_I : BOOLEAN := g_design_name="unb2_test_ddr_MB_I" OR g_design_name="unb2_test_ddr_MB_I_II" OR g_design_name="unb2_test_all";
CONSTANT c_use_MB_II : BOOLEAN := g_design_name="unb2_test_ddr_MB_II" OR g_design_name="unb2_test_ddr_MB_I_II" OR g_design_name="unb2_test_all";
@@ -155,7 +155,7 @@ ARCHITECTURE str OF unb2_test IS
-- transceivers
CONSTANT c_nof_qsfp : NATURAL := c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
CONSTANT c_nof_ring : NATURAL := 0;--8;--12;--c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
- CONSTANT c_nof_back0 : NATURAL := c_unb2_board_tr_back.bus_w;
+ CONSTANT c_nof_back0 : NATURAL := 0;--c_unb2_board_tr_back.bus_w;
CONSTANT c_nof_back1 : NATURAL := 0;--c_unb2_board_tr_back.bus_w;
-- 1GbE
@@ -307,8 +307,8 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL i_QSFP_RX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
-- SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
-- SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
SIGNAL serial_10G_tx_back_arr : STD_LOGIC_VECTOR(c_nof_streams_back0+c_nof_streams_back1-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_back_arr : STD_LOGIC_VECTOR(c_nof_streams_back0+c_nof_streams_back1-1 DOWNTO 0);
@@ -931,67 +931,67 @@ BEGIN
-- );
- u_tr_10GbE_back: ENTITY unb2_board_lib.unb2_board_10gbe -- BACK lines
- GENERIC MAP (
- g_technology => g_technology,
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_streams_back0,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size*2
- )
- PORT MAP (
- tr_ref_clk => SB_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
- reg_mac_miso => reg_tr_10GbE_back0_miso,
- reg_eth10g_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_miso => reg_eth10g_back0_miso,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
--- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
--- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
--- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
-
- serial_tx_arr => i_serial_10G_tx_back0_arr,
- serial_rx_arr => i_serial_10G_rx_back0_arr
- );
-
- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
- END GENERATE;
- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
- --END GENERATE;
-
- u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
- GENERIC MAP (
- g_nof_back_bus => c_nof_back_bus
- )
- PORT MAP (
- serial_tx_arr => serial_10G_tx_back_arr,
- serial_rx_arr => serial_10G_rx_back_arr,
-
- -- Serial I/O
- -- back transceivers
- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
-
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR
- );
+-- u_tr_10GbE_back: ENTITY unb2_board_lib.unb2_board_10gbe -- BACK lines
+-- GENERIC MAP (
+-- g_technology => g_technology,
+-- g_sim => g_sim,
+-- g_sim_level => 1,
+-- g_nof_macs => c_nof_streams_back0,
+-- g_tx_fifo_fill => c_def_10GbE_block_size,
+-- g_tx_fifo_size => c_def_10GbE_block_size*2
+-- )
+-- PORT MAP (
+-- tr_ref_clk => SB_CLK,
+-- mm_rst => mm_rst,
+-- mm_clk => mm_clk,
+-- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
+-- reg_mac_miso => reg_tr_10GbE_back0_miso,
+-- reg_eth10g_mosi => reg_eth10g_back0_mosi,
+-- reg_eth10g_miso => reg_eth10g_back0_miso,
+-- dp_rst => dp_rst,
+-- dp_clk => dp_clk,
+--
+-- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+-- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+-- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+-- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+---- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+---- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+---- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+---- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+--
+-- serial_tx_arr => i_serial_10G_tx_back0_arr,
+-- serial_rx_arr => i_serial_10G_rx_back0_arr
+-- );
+--
+-- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
+-- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
+-- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
+-- END GENERATE;
+-- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
+-- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
+-- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
+-- --END GENERATE;
+--
+-- u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
+-- GENERIC MAP (
+-- g_nof_back_bus => c_nof_back_bus
+-- )
+-- PORT MAP (
+-- serial_tx_arr => serial_10G_tx_back_arr,
+-- serial_rx_arr => serial_10G_rx_back_arr,
+--
+-- -- Serial I/O
+-- -- back transceivers
+-- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
+-- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
+-- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+-- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+--
+-- BCK_SDA => BCK_SDA,
+-- BCK_SCL => BCK_SCL,
+-- BCK_ERR => BCK_ERR
+-- );