diff --git a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
index 7e61500080ecdcf9914fef4f36789b46790da87b..5ef76ac52c450806a2a2f7ba7bce3f78252df5fd 100644
--- a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
+++ b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
@@ -45,13 +45,16 @@ entity pfb2 is
g_pfs_nof_taps : natural := 16;
g_pfs_in_dat_w : natural := 12;
g_pfs_out_dat_w : natural := 18;
- g_pfs_coef_dat_w : natural := c_pfs_coef_w; -- = 16, should match coefs in g_pfs_coefs_file
- g_pfs_coefs_file : string := c_pfs_coefs_file; -- = "data/pfs_coefsbuf_1024.hex"
+ -- = 16, should match coefs in g_pfs_coefs_file
+ g_pfs_coef_dat_w : natural := c_pfs_coef_w;
+ -- = "data/pfs_coefsbuf_1024.hex"
+ g_pfs_coefs_file : string := c_pfs_coefs_file;
-- pft2
g_pft_mode : PFT_MODE_TYPE := PFT_MODE_REAL2;
g_pft_switch_en : std_logic := '1';
- g_pft_stage_dat_w : natural := c_pft_stage_dat_w; -- c_pft_stage_dat_w = 20 in pft_pkg.vhd
+ -- c_pft_stage_dat_w = 20 in pft_pkg.vhd
+ g_pft_stage_dat_w : natural := c_pft_stage_dat_w;
g_pft_out_dat_w : natural := 18
);
port (
@@ -112,8 +115,10 @@ begin
end generate;
no_pfs : if g_pfs_bypass = true generate
- fil_out_dat_x <= SHIFT_SVEC(RESIZE_SVEC(pfs_in_dat_x, g_pfs_out_dat_w), g_pfs_in_dat_w - g_pfs_out_dat_w); -- < 0 is shift left, > 0 is shift right
- fil_out_dat_y <= SHIFT_SVEC(RESIZE_SVEC(pfs_in_dat_y, g_pfs_out_dat_w), g_pfs_in_dat_w - g_pfs_out_dat_w); -- < 0 is shift left, > 0 is shift right
+ -- < 0 is shift left, > 0 is shift right
+ fil_out_dat_x <= SHIFT_SVEC(RESIZE_SVEC(pfs_in_dat_x, g_pfs_out_dat_w), g_pfs_in_dat_w - g_pfs_out_dat_w);
+ -- < 0 is shift left, > 0 is shift right
+ fil_out_dat_y <= SHIFT_SVEC(RESIZE_SVEC(pfs_in_dat_y, g_pfs_out_dat_w), g_pfs_in_dat_w - g_pfs_out_dat_w);
fil_out_val <= pfs_in_val;
fil_out_sync <= pfs_in_sync;
end generate;
diff --git a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
index 424b49e6e684b57931790f725b8111ca58123d8c..31217a330d77dbb93beb01cbfc2d5eaaf40acbb8 100644
--- a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
+++ b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
@@ -38,7 +38,8 @@ use pft2_lib.pft_pkg.all;
entity pfb2_unit is
generic (
- g_nof_streams : natural := 1; -- number of pfb2 instances, 1 pfb2 per stream
+ -- number of pfb2 instances, 1 pfb2 per stream
+ g_nof_streams : natural := 1;
g_nof_points : natural := 1024;
-- pfs
@@ -46,25 +47,31 @@ entity pfb2_unit is
g_pfs_nof_taps : natural := 16;
g_pfs_in_dat_w : natural := 12;
g_pfs_out_dat_w : natural := 18;
- g_pfs_coef_dat_w : natural := c_pfs_coef_w; -- = 16, should match coefs in g_pfs_coefs_file
- g_pfs_coefs_file : string := c_pfs_coefs_file; -- = "data/pfs_coefsbuf_1024.hex"
+ -- = 16, should match coefs in g_pfs_coefs_file
+ g_pfs_coef_dat_w : natural := c_pfs_coef_w;
+ -- = "data/pfs_coefsbuf_1024.hex"
+ g_pfs_coefs_file : string := c_pfs_coefs_file;
-- pft2
g_pft_mode : PFT_MODE_TYPE := PFT_MODE_REAL2;
g_pft_switch_en : std_logic := '1';
- g_pft_stage_dat_w : natural := c_pft_stage_dat_w; -- c_pft_stage_dat_w = 20 in pft_pkg.vhd
+ -- c_pft_stage_dat_w = 20 in pft_pkg.vhd
+ g_pft_stage_dat_w : natural := c_pft_stage_dat_w;
g_pft_out_dat_w : natural := 18;
-- sst
- g_sst_data_w : natural := 64; -- nof bits for the SST power values
- g_sst_data_sz : natural := 2 -- nof MM 32b words to fit g_sst_data_w
+ -- nof bits for the SST power values
+ g_sst_data_w : natural := 64;
+ -- nof MM 32b words to fit g_sst_data_w
+ g_sst_data_sz : natural := 2
);
port (
dp_rst : in std_logic;
dp_clk : in std_logic;
mm_rst : in std_logic;
mm_clk : in std_logic;
- ram_st_sst_mosi : in t_mem_mosi := c_mem_mosi_rst; -- Subband statistics registers
+ -- Subband statistics registers
+ ram_st_sst_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_st_sst_miso : out t_mem_miso;
in_sosi_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0);
fil_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0);
@@ -73,7 +80,8 @@ entity pfb2_unit is
end pfb2_unit;
architecture str of pfb2_unit is
- constant c_nof_stats : natural := g_nof_points; -- SST X and SST Y are interleaved for PFT_MODE_REAL2
+ -- SST X and SST Y are interleaved for PFT_MODE_REAL2
+ constant c_nof_stats : natural := g_nof_points;
signal ram_st_sst_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal ram_st_sst_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0) := (others => c_mem_miso_rst);
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
index ffdeb470a07fcd58c59d2c230f970b5e9fe0af0f..0dcb3959cfd0d47cbec902e167399d799f223024 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
@@ -34,8 +34,10 @@ entity pfs is
g_nof_taps : natural := 16 * 1024;
g_in_dat_w : natural := 12;
g_out_dat_w : natural := 18;
- g_coef_dat_w : natural := c_pfs_coef_w; -- = 16, should match coefs in g_coefs_file
- g_coefs_file : string := c_pfs_coefs_file -- = "data/pfs_coefsbuf_1024.hex"
+ -- = 16, should match coefs in g_coefs_file
+ g_coef_dat_w : natural := c_pfs_coef_w;
+ -- = "data/pfs_coefsbuf_1024.hex"
+ g_coefs_file : string := c_pfs_coefs_file
);
port (
in_dat_x : in std_logic_vector(g_in_dat_w - 1 downto 0);
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
index 257754314c9c4fb000af3c2034c2080e988d1750..1e62d777b2cf395cce5cc9c9069dd72862838258 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
@@ -7,13 +7,15 @@ architecture str of pfs_coefsbuf is
constant c_coefs_rom : t_c_mem := (latency => 2,
adr_w => g_addr_w,
dat_w => g_data_w,
- nof_dat => g_nof_coefs, -- <= 2**g_addr_w
+ -- <= 2**g_addr_w
+ nof_dat => g_nof_coefs,
init_sl => '0');
begin
rom : entity common_lib.common_rom
generic map (
g_ram => c_coefs_rom,
- g_init_file => "data/pfs_coefsbuf_1024.hex" -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ g_init_file => "data/pfs_coefsbuf_1024.hex"
--g_init_file => "data/pfs_coefsbuf_1024.bin" -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
)
port map (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
index d28621875de50bba54bae8ff7dbb1cbcfd9ce970..cbf9f469966bb6bfcc1b9b71bc3a4d23fe809241 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
@@ -31,7 +31,8 @@ use common_lib.common_mem_pkg.all;
entity pfs_coefsbuf is
generic (
g_data_w : natural;
- g_coefs_file : string := "data/pfs_coefsbuf_1024.hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ g_coefs_file : string := "data/pfs_coefsbuf_1024.hex";
--g_coefs_file : STRING := "data/pfs_coefsbuf_1024.bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
g_nof_coefs : natural;
g_addr_w : natural
@@ -48,7 +49,8 @@ architecture str of pfs_coefsbuf is
constant c_coefs_rom : t_c_mem := (latency => 2,
adr_w => g_addr_w,
dat_w => g_data_w,
- nof_dat => g_nof_coefs, -- <= 2**g_addr_w
+ -- <= 2**g_addr_w
+ nof_dat => g_nof_coefs,
init_sl => '0');
begin
rom : entity common_lib.common_rom
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
index c17e494eb6f07d436f9ae722f90652f4642090fe..27f6674cbe04dd6f9388f12aa15a68dec950caa6 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
@@ -30,7 +30,8 @@ begin
gen : for i in 0 to 7 generate
--MULT_ADD : ENTITY common_lib.common_mult_add(rtl)
--MULT_ADD : ENTITY common_lib.common_mult_add(virtex)
- MULT_ADD : entity common_mult_lib.common_mult_add -- rtl
+ -- rtl
+ MULT_ADD : entity common_mult_lib.common_mult_add
generic map (
g_in_a_w => g_taps_w,
g_in_b_w => g_coef_w,
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
index ba25c7ab38656b7edf7bf6ce78db76ffb66da00d..f2c30569ddbc11397489e85f4474d398ff5f1d45 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
@@ -70,7 +70,8 @@ begin
gen : for i in 0 to 7 generate
--MULT_ADD : ENTITY common_lib.common_mult_add(rtl)
--MULT_ADD : ENTITY common_lib.common_mult_add(virtex)
- MULT_ADD : entity common_mult_lib.common_mult_add -- rtl
+ -- rtl
+ MULT_ADD : entity common_mult_lib.common_mult_add
generic map (
g_in_a_w => g_taps_w,
g_in_b_w => g_coef_w,
diff --git a/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd b/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
index 17cc8b68856ffcc2f6e91ce4279749b0757421ad..918a48b552b26d65651faee9688955affa1513be 100644
--- a/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
+++ b/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
@@ -109,7 +109,8 @@ begin
end loop;
-- continue some more per sync interval
- proc_common_wait_some_cycles(clk, 1024 * 4 - 1); -- -1 to create sync for next sync interval
+ -- -1 to create sync for next sync interval
+ proc_common_wait_some_cycles(clk, 1024 * 4 - 1);
in_sync <= '1';
wait until rising_edge(clk);
in_sync <= '0';
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
index 167561784c506e95549ea815b4773596ec4e747e..e0fcabbc87d475513f1fdb161dae138a83080d29 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
@@ -33,7 +33,8 @@ entity pft is
g_fft_size_w : natural := 10;
g_in_dat_w : natural := 18;
g_out_dat_w : natural := 18;
- g_stage_dat_w : natural := c_pft_stage_dat_w; -- c_pft_stage_dat_w = 20 in pft_pkg.vhd
+ -- c_pft_stage_dat_w = 20 in pft_pkg.vhd
+ g_stage_dat_w : natural := c_pft_stage_dat_w;
g_mode : PFT_MODE_TYPE := PFT_MODE_BITREV
);
port (
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
index 36e8e2a0075c428aee6e6f9a319fd30ec9a899c6..e914681a9bac129b8bcb55c005bf4b3b1626c997 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
@@ -240,10 +240,13 @@ begin
generic map (
g_direction => "ADD",
g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
+ -- 0 or 1
+ g_pipeline_input => 0,
+ -- >= 0
+ g_pipeline_output => c_add_pipeline,
g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ g_out_dat_w => c_dat_w
)
port map (
clk => clk,
@@ -280,10 +283,13 @@ begin
generic map (
g_direction => "SUB",
g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
+ -- 0 or 1
+ g_pipeline_input => 0,
+ -- >= 0
+ g_pipeline_output => c_add_pipeline,
g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ g_out_dat_w => c_dat_w
)
port map (
clk => clk,
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
index 52eebaf095bcdbb3292059b408909b75c15f7ed5..6030af1d23f7a64dcf1227f737032ef343b01351 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
@@ -287,10 +287,13 @@ begin
generic map (
g_direction => "ADD",
g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
+ -- 0 or 1
+ g_pipeline_input => 0,
+ -- >= 0
+ g_pipeline_output => c_add_pipeline,
g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ g_out_dat_w => c_dat_w
)
port map (
clk => clk,
@@ -327,10 +330,13 @@ begin
generic map (
g_direction => "SUB",
g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
+ -- 0 or 1
+ g_pipeline_input => 0,
+ -- >= 0
+ g_pipeline_output => c_add_pipeline,
g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ g_out_dat_w => c_dat_w
)
port map (
clk => clk,
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
index c8467e44759e8f153de12a1fc307f04e6963a553..3d0a3c488512c666a9ef44126f71cf9fcf3cf272 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
@@ -181,10 +181,13 @@ begin
generic map (
g_direction => "BOTH",
g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
+ -- 0 or 1
+ g_pipeline_input => 0,
+ -- >= 0
+ g_pipeline_output => c_add_pipeline,
g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ g_out_dat_w => g_out_dat_w
)
port map (
clk => clk,
@@ -217,10 +220,13 @@ begin
generic map (
g_direction => "BOTH",
g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
+ -- 0 or 1
+ g_pipeline_input => 0,
+ -- >= 0
+ g_pipeline_output => c_add_pipeline,
g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ g_out_dat_w => g_out_dat_w
)
port map (
clk => clk,
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
index f777f5e18d382a71341aaa2c01de40cff0f3f6e2..2af019fd374379d45042325f3e6592b252ed1ede 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
@@ -228,10 +228,13 @@ begin
generic map (
g_direction => "BOTH",
g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
+ -- 0 or 1
+ g_pipeline_input => 0,
+ -- >= 0
+ g_pipeline_output => c_add_pipeline,
g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ g_out_dat_w => g_out_dat_w
)
port map (
clk => clk,
@@ -264,10 +267,13 @@ begin
generic map (
g_direction => "BOTH",
g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
+ -- 0 or 1
+ g_pipeline_input => 0,
+ -- >= 0
+ g_pipeline_output => c_add_pipeline,
g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ g_out_dat_w => g_out_dat_w
)
port map (
clk => clk,
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
index 85ff4fdba8fa3418b4ad97b1822d11048cf95d67..bf1dd8969fb637c5dd4126d7d3c5504130b0f1f8 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
@@ -15,7 +15,8 @@ architecture rtl of pft_buffer is
constant c_ram : t_c_mem := (latency => c_latency,
adr_w => c_adr_w,
dat_w => 2 * g_dat_w,
- nof_dat => c_nof_words, -- <= 2**g_addr_w
+ -- <= 2**g_addr_w
+ nof_dat => c_nof_words,
init_sl => '0');
signal rd_dat : std_logic_vector(2 * g_dat_w - 1 downto 0);
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
index 33f764deb9248f081270a60e9b8f988ee8ba4d68..ff1ecc35fe07f555dff6484d21a4cba41db5ec26 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
@@ -61,7 +61,8 @@ architecture rtl of pft_buffer is
constant c_ram : t_c_mem := (latency => c_latency,
adr_w => c_adr_w,
dat_w => 2 * g_dat_w,
- nof_dat => c_nof_words, -- <= 2**g_addr_w
+ -- <= 2**g_addr_w
+ nof_dat => c_nof_words,
init_sl => '0');
signal rd_dat : std_logic_vector(2 * g_dat_w - 1 downto 0);
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
index 885d8a147e4ce267f05bdcc4e7fbf506db9f85c8..bb650db3cb017fefec1d8d59e67130f818c0f77e 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
@@ -188,10 +188,13 @@ begin
generic map (
g_direction => "ADD",
g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
+ -- 0 or 1
+ g_pipeline_input => 0,
+ -- >= 0
+ g_pipeline_output => c_add_delay - 1,
g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ g_out_dat_w => g_out_dat_w
)
port map (
clk => clk,
@@ -220,10 +223,13 @@ begin
generic map (
g_direction => "SUB",
g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
+ -- 0 or 1
+ g_pipeline_input => 0,
+ -- >= 0
+ g_pipeline_output => c_add_delay - 1,
g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ g_out_dat_w => g_out_dat_w
)
port map (
clk => clk,
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
index 538b57aac83328aa950606c8ec148b4e48c09ae2..f57450a848ff5f69e64dcb868eae402758cecef0 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
@@ -234,10 +234,13 @@ begin
generic map (
g_direction => "ADD",
g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
+ -- 0 or 1
+ g_pipeline_input => 0,
+ -- >= 0
+ g_pipeline_output => c_add_delay - 1,
g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ g_out_dat_w => g_out_dat_w
)
port map (
clk => clk,
@@ -266,10 +269,13 @@ begin
generic map (
g_direction => "SUB",
g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
+ -- 0 or 1
+ g_pipeline_input => 0,
+ -- >= 0
+ g_pipeline_output => c_add_delay - 1,
g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ g_out_dat_w => g_out_dat_w
)
port map (
clk => clk,
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
index fc220fa98cf914dfde56a210489d62a7a3db4f9d..09ca73e03ca617367ffde3cc4ddfa6b362d366fe 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
@@ -38,23 +38,31 @@ architecture rtl of pft_tmult is
constant c_twid_rom : t_c_mem := (latency => 2,
adr_w => c_adr_w,
- dat_w => 2 * c_coeff_w, -- complex
- nof_dat => 3 * c_nof_twids / 4, -- <= 2**g_addr_w
+ -- complex
+ dat_w => 2 * c_coeff_w,
+ -- <= 2**g_addr_w
+ nof_dat => 3 * c_nof_twids / 4,
init_sl => '0');
constant c_twid_file : string :=
"data/twiddle_" & natural'image(c_coeff_w)
- & "_" & natural'image(g_index) & ".hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ & "_" & natural'image(g_index) & ".hex";
--CONSTANT c_twid_file : STRING :=
-- "../../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
-- & "_" & NATURAL'IMAGE(g_index) & ".bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
constant c_read_pipeline : natural := 1;
- constant c_mult_pipeline_input : natural := 1; -- 0 or 1
- constant c_mult_pipeline_product : natural := 0; -- 0 or 1
- constant c_mult_pipeline_adder : natural := 1; -- 0 or 1
- constant c_mult_pipeline_output : natural := 1; -- >= 0
- constant c_mult_pipeline : natural := c_mult_pipeline_input + c_mult_pipeline_product + c_mult_pipeline_adder + c_mult_pipeline_output; -- = 3
+ -- 0 or 1
+ constant c_mult_pipeline_input : natural := 1;
+ -- 0 or 1
+ constant c_mult_pipeline_product : natural := 0;
+ -- 0 or 1
+ constant c_mult_pipeline_adder : natural := 1;
+ -- >= 0
+ constant c_mult_pipeline_output : natural := 1;
+ -- = 3
+ constant c_mult_pipeline : natural := c_mult_pipeline_input + c_mult_pipeline_product + c_mult_pipeline_adder + c_mult_pipeline_output;
constant c_round_pipeline_in : natural := 1;
constant c_round_pipeline_out : natural := 1;
constant c_round_pipeline : natural := c_round_pipeline_in + c_round_pipeline_out;
@@ -163,10 +171,14 @@ begin
g_in_b_w => c_coeff_w,
g_out_p_w => c_mult_out_w,
g_conjugate_b => false,
- g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
- g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
- g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
- g_pipeline_output => c_mult_pipeline_output -- >= 0
+ -- 0 or 1
+ g_pipeline_input => c_mult_pipeline_input,
+ -- 0 or 1
+ g_pipeline_product => c_mult_pipeline_product,
+ -- 0 or 1
+ g_pipeline_adder => c_mult_pipeline_adder,
+ -- >= 0
+ g_pipeline_output => c_mult_pipeline_output
)
port map (
in_ar => mult_in_re,
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
index e6ab7f98a95ffa1977924cc1b3b6c11e64902133..3ffa6f3539a4b6c431dfa6ff2c10de2fdbdcd988 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
@@ -63,23 +63,31 @@ architecture rtl of pft_tmult is
constant c_twid_rom : t_c_mem := (latency => 2,
adr_w => c_adr_w,
- dat_w => 2 * c_coeff_w, -- complex
- nof_dat => 3 * c_nof_twids / 4, -- <= 2**g_addr_w
+ -- complex
+ dat_w => 2 * c_coeff_w,
+ -- <= 2**g_addr_w
+ nof_dat => 3 * c_nof_twids / 4,
init_sl => '0');
constant c_twid_file : string :=
"data/twiddle_" & natural'image(c_coeff_w)
- & "_" & natural'image(g_index) & ".hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ & "_" & natural'image(g_index) & ".hex";
--CONSTANT c_twid_file : STRING :=
-- "../../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
-- & "_" & NATURAL'IMAGE(g_index) & ".bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
constant c_read_pipeline : natural := 1;
- constant c_mult_pipeline_input : natural := 1; -- 0 or 1
- constant c_mult_pipeline_product : natural := 0; -- 0 or 1
- constant c_mult_pipeline_adder : natural := 1; -- 0 or 1
- constant c_mult_pipeline_output : natural := 1; -- >= 0
- constant c_mult_pipeline : natural := c_mult_pipeline_input + c_mult_pipeline_product + c_mult_pipeline_adder + c_mult_pipeline_output; -- = 3
+ -- 0 or 1
+ constant c_mult_pipeline_input : natural := 1;
+ -- 0 or 1
+ constant c_mult_pipeline_product : natural := 0;
+ -- 0 or 1
+ constant c_mult_pipeline_adder : natural := 1;
+ -- >= 0
+ constant c_mult_pipeline_output : natural := 1;
+ -- = 3
+ constant c_mult_pipeline : natural := c_mult_pipeline_input + c_mult_pipeline_product + c_mult_pipeline_adder + c_mult_pipeline_output;
constant c_round_pipeline_in : natural := 1;
constant c_round_pipeline_out : natural := 1;
constant c_round_pipeline : natural := c_round_pipeline_in + c_round_pipeline_out;
@@ -188,10 +196,14 @@ begin
g_in_b_w => c_coeff_w,
g_out_p_w => c_mult_out_w,
g_conjugate_b => false,
- g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
- g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
- g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
- g_pipeline_output => c_mult_pipeline_output -- >= 0
+ -- 0 or 1
+ g_pipeline_input => c_mult_pipeline_input,
+ -- 0 or 1
+ g_pipeline_product => c_mult_pipeline_product,
+ -- 0 or 1
+ g_pipeline_adder => c_mult_pipeline_adder,
+ -- >= 0
+ g_pipeline_output => c_mult_pipeline_output
)
port map (
in_ar => mult_in_re,
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
index 5294b0a66bf24ef523fb548d624319a6b7774459..c8ca9950863fa5e9c1018d9bc83ec152b467837a 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
@@ -61,7 +61,8 @@ begin
en => '1',
out_dat1 => in_x,
out_dat2 => in_y,
- out_val => open -- in_val
+ -- in_val
+ out_val => open
);
in_val <= val;
@@ -69,8 +70,10 @@ begin
pfs : entity pfs_lib.pfs
generic map (
- g_nof_bands => 2**g_fft_size_w, -- 2*g_nof_subbands,
- g_nof_taps => 2**g_fft_size_w * 16, -- 2*16*g_nof_subbands,
+ -- 2*g_nof_subbands,
+ g_nof_bands => 2**g_fft_size_w,
+ -- 2*16*g_nof_subbands,
+ g_nof_taps => 2**g_fft_size_w * 16,
g_in_dat_w => g_in_w,
g_out_dat_w => g_pfs_w,
g_coef_dat_w => g_pfs_coef_w
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
index 7c4aa160e924e499109ada8f001609d5febcfb05..ddff64be553ae09b848090e557b84dd9ad2aeb24 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
@@ -42,7 +42,8 @@ entity tb_pft2 is
generic (
-- >>> PFT settings
g_switch_en : std_logic := '0';
- g_stage_dat_w : natural := c_pft_stage_dat_w; -- c_pft_stage_dat_w = 20 in pft_pkg.vhd
+ -- c_pft_stage_dat_w = 20 in pft_pkg.vhd
+ g_stage_dat_w : natural := c_pft_stage_dat_w;
-- The PFT has 3 modes:
-- . PFT_MODE_BITREV --> DIT output
@@ -80,13 +81,15 @@ entity tb_pft2 is
--g_name_y : STRING := "sinus_13s";
--g_name_y : STRING := "impulse_0";
--g_name_y : STRING := "impulse_1";
- g_name_y : string := "zeros"; -- For PFT_MODE_BITREV and PFT_MODE_COMPLEX select zeros for Y input.
+ -- For PFT_MODE_BITREV and PFT_MODE_COMPLEX select zeros for Y input.
+ g_name_y : string := "zeros";
--g_name_y : STRING := "dc";
--g_name_y : STRING := "block_1";
--g_name_y : STRING := "block_117";
--g_name_y : STRING := "u_noise";
- g_repeat : natural := 2 -- minimal 2 due to PFT latency
+ -- minimal 2 due to PFT latency
+ g_repeat : natural := 2
--g_repeat : NATURAL := 10 -- > c_nof_block_per_sync to view multiple in_sync and out_sync intervals
);
end tb_pft2;
@@ -105,7 +108,8 @@ architecture tb of tb_pft2 is
constant c_tst_data_dir : string := "data/";
-- Maximum quantization error in PFT output
- constant c_diff_max : natural := 20; -- Maximum quantization error in PFT output, as used in tc.tcl
+ -- Maximum quantization error in PFT output, as used in tc.tcl
+ constant c_diff_max : natural := 20;
--CONSTANT c_diff_max : NATURAL := 10; -- value per subband
--CONSTANT c_pdiff_max : NATURAL := 5; -- average power diff over all subbands from TC 5.19
@@ -122,9 +126,12 @@ architecture tb of tb_pft2 is
constant c_fft_size : natural := 2**c_fft_size_w;
- type t_ref_dat is array (0 to c_fft_size ) of integer; -- one extra dummy
- type t_ref_fft_dat is array (0 to c_fft_size-1) of integer; -- PFT_MODE_BITREV, PFT_MODE_COMPLEX scaled and rounded
- type t_ref_real2_dat is array (0 to c_fft_size / 2 - 1) of integer; -- PFT_MODE_REAL2 scaled and rounded
+ -- one extra dummy
+ type t_ref_dat is array (0 to c_fft_size ) of integer;
+ -- PFT_MODE_BITREV, PFT_MODE_COMPLEX scaled and rounded
+ type t_ref_fft_dat is array (0 to c_fft_size-1) of integer;
+ -- PFT_MODE_REAL2 scaled and rounded
+ type t_ref_real2_dat is array (0 to c_fft_size / 2 - 1) of integer;
-- Signals
signal tb_end : std_logic := '0';
@@ -161,10 +168,14 @@ architecture tb of tb_pft2 is
signal nxt_out_x_im : integer;
signal nxt_out_y_re : integer;
signal nxt_out_y_im : integer;
- signal out_x_re : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
- signal out_x_im : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
- signal out_y_re : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
- signal out_y_im : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal out_x_re : integer := 0;
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal out_x_im : integer := 0;
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal out_y_re : integer := 0;
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal out_y_im : integer := 0;
signal out_sync : std_logic;
-- Reference FFT output data from MATLAB generated files
@@ -183,15 +194,18 @@ architecture tb of tb_pft2 is
signal nxt_ref_rdy : std_logic;
signal rd_cnt : natural := 0;
signal nxt_rd_cnt : natural;
- signal rd_dat_x_re : t_ref_dat; -- Keep the ref data in an array
+ -- Keep the ref data in an array
+ signal rd_dat_x_re : t_ref_dat;
signal rd_dat_x_im : t_ref_dat;
signal rd_dat_y_re : t_ref_dat;
signal rd_dat_y_im : t_ref_dat;
-- For PFT_MODE_BITREV, PFT_MODE_COMPLEX
- signal ref_fft_dat_re : t_ref_fft_dat; -- Scaled and rounded ref data array
+ -- Scaled and rounded ref data array
+ signal ref_fft_dat_re : t_ref_fft_dat;
signal ref_fft_dat_im : t_ref_fft_dat;
-- For PFT_MODE_REAL2
- signal ref_real2_dat_x_re : t_ref_real2_dat; -- Scaled and rounded ref data array
+ -- Scaled and rounded ref data array
+ signal ref_real2_dat_x_re : t_ref_real2_dat;
signal ref_real2_dat_x_im : t_ref_real2_dat;
signal ref_real2_dat_y_re : t_ref_real2_dat;
signal ref_real2_dat_y_im : t_ref_real2_dat;
@@ -306,7 +320,8 @@ architecture tb of tb_pft2 is
begin
p_tb_end : process
begin
- proc_common_wait_until_hi_lo(clk, out_val); -- end of test
+ -- end of test
+ proc_common_wait_until_hi_lo(clk, out_val);
proc_common_wait_some_cycles(clk, 100);
tb_end <= '1';
wait;
@@ -319,7 +334,8 @@ begin
in_en <= '0', '1' after c_clk_period * c_rst_period * 2;
in_val <= in_val_x;
- rst_sync <= '1', '0' after c_clk_period * (c_rst_period * 2 - 1); -- start in_sync pulse interval 1 clk cycle before first in_val = '1'
+ -- start in_sync pulse interval 1 clk cycle before first in_val = '1'
+ rst_sync <= '1', '0' after c_clk_period * (c_rst_period * 2 - 1);
proc_common_gen_pulse(1, c_nof_block_per_sync * c_fft_size, '1', rst_sync, clk, in_sync);
-----------------------------------------------------------------------------
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
index cdc09c717a053e14a256d95aaf0a35ef34f2159d..82aaaefa1f2c64358c3ea88a247682dca7b88f6b 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
@@ -16,7 +16,8 @@ architecture tb of tb_pft is
constant g_out_dat_w : natural := 18;
constant g_fft_size : natural := 1024;
constant g_fft_size_w : natural := 10;
- constant g_pps_ps : natural := 2048; -- 8192;
+ -- 8192;
+ constant g_pps_ps : natural := 2048;
signal cnt : std_logic_vector(32 downto 0) := (others => '0');
signal nxt_cnt : std_logic_vector(32 downto 0) := (others => '0');
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
index 48440aff8717881673e5e82c0fa2e71ab61d25f7..97e5fb795d8f72eb84810b8f392d36c7bb333f6e 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
@@ -33,10 +33,13 @@ end tb_tb_pft2;
use work.pft_pkg.all;
architecture tb of tb_tb_pft2 is
- constant c_sw : std_logic := '1'; -- default for g_switch_en
- constant c_dat_w : natural := c_pft_stage_dat_w; -- default for g_stage_dat_w
+ -- default for g_switch_en
+ constant c_sw : std_logic := '1';
+ -- default for g_stage_dat_w
+ constant c_dat_w : natural := c_pft_stage_dat_w;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- >>> PFT settings
--g_switch_en : STD_LOGIC := '0';
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
index 36aaca529eb85f3b060a0b8c60f04698c276d2ec..de27e78c1f1c2d8cc0e3b34254439ef3dc6c7a48 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
@@ -39,20 +39,29 @@ entity lofar2_unb2b_adc_6ch_200MHz is
g_design_name : string := "lofar2_unb2b_adc_6ch_200MHz";
g_design_note : string := "Lofar2 with 6 ADC input streams";
g_jesd_freq : string := "200MHz";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -77,7 +86,8 @@ entity lofar2_unb2b_adc_6ch_200MHz is
-- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
index d1e33a7ff0d788701309206613f646f48f8a0601..3ff690942bb59e5d3eaa1029e196b4fc2a7b8140 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
@@ -39,13 +39,16 @@ end tb_lofar2_unb2b_adc_6ch_200MHz;
architecture tb of tb_lofar2_unb2b_adc_6ch_200MHz is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 0; -- Back node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Back node 3
+ constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -83,17 +86,26 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- bck_ref_clk <= not bck_ref_clk after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ bck_ref_clk <= not bck_ref_clk after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
index 7e46728d34127e2043e52764741dcad8b2cd8b47..05ffa4eb7c487ebb6c9b55c78d765a445c027210 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2b_adc_full is
generic (
g_design_name : string := "lofar2_unb2b_adc_full";
g_design_note : string := "Lofar2 adc with all streams";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -76,7 +85,8 @@ entity lofar2_unb2b_adc_full is
-- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
index 02076e8cc845c1469e638ecf7d10c6e04674db58..ab07727628158d968c6f240d61f9a36f6545b7a5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
@@ -40,13 +40,16 @@ end tb_lofar2_unb2b_adc_full;
architecture tb of tb_lofar2_unb2b_adc_full is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 0; -- Back node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Back node 3
+ constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -84,17 +87,26 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- bck_ref_clk <= not bck_ref_clk after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ bck_ref_clk <= not bck_ref_clk after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
index 88acdb6b718de2b491b79f1c68a0de9a898b422f..18660c43142b776b89e1d0c12d6fb801b5a748ad 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2b_adc_one_node is
generic (
g_design_name : string := "lofar2_unb2b_adc_one_node";
g_design_note : string := "Lofar2 adc with one node";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -76,7 +85,8 @@ entity lofar2_unb2b_adc_one_node is
-- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
index 768efa68b74c1bd9b3245e1b9ec0d5ee58f94def..007278b56da6edacff4d7166912516e99baa655e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
@@ -40,13 +40,16 @@ end tb_lofar2_unb2b_adc_one_node;
architecture tb of tb_lofar2_unb2b_adc_one_node is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 0; -- Back node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Back node 3
+ constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -84,17 +87,26 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- bck_ref_clk <= not bck_ref_clk after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ bck_ref_clk <= not bck_ref_clk after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index f23f05116a5a424ccf0273da9f2827046a750d00..1f398ab2b2f6a68728ae7ee74c42c8aa6461a397 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -42,23 +42,32 @@ entity lofar2_unb2b_adc is
g_design_note : string := "UNUSED";
g_jesd_freq : string := "200MHz";
g_buf_nof_data : natural := 1024;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_sim_model_ddr : boolean := false;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := false;
g_protect_addr_range: boolean := false
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -84,7 +93,8 @@ entity lofar2_unb2b_adc is
-- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
-- Connect to the BCK_RX pins in the top wrapper
- JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
+ -- Connect to BCK_REF_CLK pin in the top level wrapper
+ JESD204B_REFCLK : in std_logic;
-- jesd204b syncronization signals
JESD204B_SYSREF : in std_logic;
@@ -95,7 +105,8 @@ end lofar2_unb2b_adc;
architecture str of lofar2_unb2b_adc is
-- Revision parameters
constant c_revision_select : t_lofar2_unb2b_adc_config := func_sel_revision_rec(g_design_name);
- constant c_nof_streams : natural := c_revision_select.nof_streams_input; -- Streams actually passed through for processing
+ -- Streams actually passed through for processing
+ constant c_nof_streams : natural := c_revision_select.nof_streams_input;
-- Firmware version x.y
constant c_fw_version : t_unb2b_board_fw_version := (1, 1);
@@ -148,12 +159,16 @@ architecture str of lofar2_unb2b_adc is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -254,7 +269,8 @@ begin
mm_rst => mm_rst,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ -- Can be external 200MHz, or PLL generated
+ dp_clk => dp_clk,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
@@ -491,7 +507,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
index daffa485ac9a95f2265164cc80f90ed0bb1062c9..d879ab292bdb347020793135b982cfc453cfb1f6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
@@ -32,7 +32,8 @@ use work.qsys_lofar2_unb2b_adc_pkg.all;
entity mmm_lofar2_unb2b_adc is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
@@ -434,7 +435,8 @@ begin
ram_diag_data_buffer_bsn_clk_export => OPEN,
ram_diag_data_buffer_bsn_reset_export => OPEN,
- ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(21 - 1 downto 0), -- 22 = ceil_log2(12 * 256k), so maximum possible data buffer size is 256 kSamples
+ -- 22 = ceil_log2(12 * 256k), so maximum possible data buffer size is 256 kSamples
+ ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(21 - 1 downto 0),
ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 869b3d932d615a4da5f73c9a8440766d3460d248..fafd7a34999b554006f134485321bc8728b9b719 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -41,11 +41,15 @@ use lofar2_sdp_lib.sdp_pkg.all;
entity node_adc_input_and_timing is
generic (
g_jesd_freq : string := "200MHz";
- g_buf_nof_data : natural := 131072; -- 8192; --1024;
+ -- 8192; --1024;
+ g_buf_nof_data : natural := 131072;
g_nof_streams : natural := 12;
- g_nof_sync_n : natural := 4; -- Three ADCs per RCU share a sync
- g_aduh_buffer_nof_symbols : natural := 512; -- Default 512
- g_bsn_sync_timeout : natural := 200000000; -- Default 200M, overide for short simulation
+ -- Three ADCs per RCU share a sync
+ g_nof_sync_n : natural := 4;
+ -- Default 512
+ g_aduh_buffer_nof_symbols : natural := 512;
+ -- Default 200M, overide for short simulation
+ g_bsn_sync_timeout : natural := 200000000;
g_sim : boolean := false
);
port (
@@ -117,7 +121,8 @@ entity node_adc_input_and_timing is
end node_adc_input_and_timing;
architecture str of node_adc_input_and_timing is
- constant c_nof_streams_jesd204b : natural := 12; -- IP is set up for 12 streams
+ -- IP is set up for 12 streams
+ constant c_nof_streams_jesd204b : natural := 12;
constant c_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
adr_w => 1,
@@ -127,8 +132,10 @@ architecture str of node_adc_input_and_timing is
-- Waveform Generator
constant c_wg_buf_directory : string := "data/";
- constant c_wg_buf_dat_w : natural := 18; -- default value of WG that fits 14 bits of ADC data
- constant c_wg_buf_addr_w : natural := 10; -- default value of WG for 1024 samples;
+ -- default value of WG that fits 14 bits of ADC data
+ constant c_wg_buf_dat_w : natural := 18;
+ -- default value of WG for 1024 samples;
+ constant c_wg_buf_addr_w : natural := 10;
signal wg_out_ovr : std_logic_vector(g_nof_streams - 1 downto 0);
signal wg_out_val : std_logic_vector(g_nof_streams - 1 downto 0);
signal wg_out_data : std_logic_vector(g_nof_streams * c_wg_buf_dat_w - 1 downto 0);
@@ -136,9 +143,11 @@ architecture str of node_adc_input_and_timing is
signal trigger_wg : std_logic;
-- Frame parameters TBC
- constant c_bs_bsn_w : natural := 64; -- 51;
+ -- 51;
+ constant c_bs_bsn_w : natural := 64;
constant c_bs_block_size : natural := 1024;
- constant c_bs_nof_block_per_sync : natural := 390625; -- generate a sync every 2s for testing
+ -- generate a sync every 2s for testing
+ constant c_bs_nof_block_per_sync : natural := 390625;
constant c_dp_shiftram_nof_samples: natural := 4096;
constant c_data_w : natural := 16;
constant c_dp_fifo_dc_size : natural := 64;
@@ -148,7 +157,8 @@ architecture str of node_adc_input_and_timing is
signal qsfp_red_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
-- JESD signals
- signal rx_clk : std_logic; -- formerly jesd204b_frame_clk
+ -- formerly jesd204b_frame_clk
+ signal rx_clk : std_logic;
signal rx_rst : std_logic;
signal rx_sysref : std_logic;
@@ -298,7 +308,8 @@ begin
dp_rst => rx_rst,
dp_clk => rx_clk,
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ -- only uses eop (= block sync), bsn[]
+ snk_in => bs_sosi,
trigger_out => trigger_wg
);
@@ -383,7 +394,8 @@ begin
---------------------------------------------------------------------------------------
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
generic map (
- g_nof_streams => 1, -- They're all the same
+ -- They're all the same
+ g_nof_streams => 1,
g_sync_timeout => g_bsn_sync_timeout,
g_bsn_w => c_bs_bsn_w,
g_log_first_bsn => false
@@ -408,20 +420,27 @@ begin
generic map (
g_cross_clock_domain => true,
g_nof_streams => g_nof_streams,
- g_symbol_w => c_data_w, -- TBD 16?
- g_nof_symbols_per_data => 1, -- Wideband factor is 1
- g_nof_accumulations => 200000512, -- = 195313 blocks * 1024 samples
- g_buffer_nof_symbols => g_aduh_buffer_nof_symbols, -- default 512, larger for full design
- g_buffer_use_sync => true -- True to capture all streams synchronously
+ -- TBD 16?
+ g_symbol_w => c_data_w,
+ -- Wideband factor is 1
+ g_nof_symbols_per_data => 1,
+ -- = 195313 blocks * 1024 samples
+ g_nof_accumulations => 200000512,
+ -- default 512, larger for full design
+ g_buffer_nof_symbols => g_aduh_buffer_nof_symbols,
+ -- True to capture all streams synchronously
+ g_buffer_use_sync => true
)
port map (
-- Memory-mapped clock domain
mm_rst => mm_rst_internal,
mm_clk => mm_clk,
- reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
+ -- read only access to the signal path data mean sum and power sum registers
+ reg_mosi => reg_aduh_monitor_mosi,
reg_miso => reg_aduh_monitor_miso,
- buf_mosi => ram_aduh_monitor_mosi, -- read and overwrite access to the signal path data buffers
+ -- read and overwrite access to the signal path data buffers
+ buf_mosi => ram_aduh_monitor_mosi,
buf_miso => ram_aduh_monitor_miso,
-- Streaming clock domain
@@ -440,7 +459,8 @@ begin
g_nof_streams => g_nof_streams,
g_data_w => c_data_w,
g_buf_nof_data => g_buf_nof_data,
- g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ g_buf_use_sync => true
)
port map (
mm_rst => mm_rst_internal,
@@ -466,7 +486,8 @@ begin
u_dp_fifo_dc : entity dp_lib.dp_fifo_dc
generic map (
g_data_w => c_data_w,
- g_use_empty => false, -- TRUE,
+ -- TRUE,
+ g_use_empty => false,
g_use_ctrl => true,
g_use_sync => true,
g_use_bsn => true,
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
index cd479c2bdbe001e2bd25df14c936a10be5cffdda..d4ecb0c6195ee94318a67a183f63c62171d2a432 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
@@ -30,210 +30,414 @@ package qsys_lofar2_unb2b_adc_pkg is
component qsys_lofar2_unb2b_adc is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(11 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- export
+ jesd204b_address_export : out std_logic_vector(11 downto 0);
+ -- export
+ jesd204b_clk_export : out std_logic;
+ -- export
+ jesd204b_read_export : out std_logic;
+ -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ jesd204b_reset_export : out std_logic;
+ -- export
+ jesd204b_write_export : out std_logic;
+ -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_jesd_ctrl_clk_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_read_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_jesd_ctrl_reset_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_write_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(11 downto 0);
+ -- export
+ ram_aduh_monitor_clk_export : out std_logic;
+ -- export
+ ram_aduh_monitor_read_export : out std_logic;
+ -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_aduh_monitor_reset_export : out std_logic;
+ -- export
+ ram_aduh_monitor_write_export : out std_logic;
+ -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0);
+ -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_wg_clk_export : out std_logic;
+ -- export
+ ram_wg_read_export : out std_logic;
+ -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_wg_reset_export : out std_logic;
+ -- export
+ ram_wg_write_export : out std_logic;
+ -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_aduh_monitor_clk_export : out std_logic;
+ -- export
+ reg_aduh_monitor_read_export : out std_logic;
+ -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_aduh_monitor_reset_export : out std_logic;
+ -- export
+ reg_aduh_monitor_write_export : out std_logic;
+ -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0);
+ -- export
+ reg_bsn_monitor_input_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_input_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_bsn_scheduler_clk_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_read_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_scheduler_reset_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_write_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_bsn_source_clk_export : out std_logic;
+ -- export
+ reg_bsn_source_read_export : out std_logic;
+ -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_source_reset_export : out std_logic;
+ -- export
+ reg_bsn_source_write_export : out std_logic;
+ -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0);
+ -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_dp_shiftram_clk_export : out std_logic;
+ -- export
+ reg_dp_shiftram_read_export : out std_logic;
+ -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_shiftram_reset_export : out std_logic;
+ -- export
+ reg_dp_shiftram_write_export : out std_logic;
+ -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic;
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_wg_clk_export : out std_logic;
+ -- export
+ reg_wg_read_export : out std_logic;
+ -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wg_reset_export : out std_logic;
+ -- export
+ reg_wg_write_export : out std_logic;
+ -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0)
);
end component qsys_lofar2_unb2b_adc;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
index 627ac45ba488fb71a0073ea24bb1a910369afdf6..7e5704ec452a322c9e336d8ee5f98e229d08a164 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
@@ -42,13 +42,16 @@ end tb_lofar2_unb2b_adc;
architecture tb of tb_lofar2_unb2b_adc is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 0; -- Back node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Back node 3
+ constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -86,17 +89,26 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
index 16294442b7b7a21a596125399d2de3cd0c9483c8..7a096ab5f2b031f009f6388898e32a6ce6bd9af3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
@@ -43,22 +43,27 @@ end tb_lofar2_unb2b_adc_multichannel;
architecture tb of tb_lofar2_unb2b_adc_multichannel is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 0; -- Back node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Back node 3
+ constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_jesd204b_sampclk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
constant c_bondingclk_period : time := 10 ns;
- constant c_sysref_period : natural := 10000; -- number of sample clocks between sysref pulses
+ -- number of sample clocks between sysref pulses
+ constant c_sysref_period : natural := 10000;
-- Transport delays
type t_time_arr is array (0 to 11) of time;
- constant c_nof_jesd204b_tx : natural := 3; -- number of jesd204b input sources to instantiate
+ -- number of jesd204b input sources to instantiate
+ constant c_nof_jesd204b_tx : natural := 3;
constant c_delay_data_arr : t_time_arr := (4000 ps,
5000 ps,
6000 ps,
@@ -70,7 +75,8 @@ architecture tb of tb_lofar2_unb2b_adc_multichannel is
5000 ps,
5000 ps,
5000 ps,
- 5000 ps); -- transport delays tx to rx data
+ -- transport delays tx to rx data
+ 5000 ps);
constant c_delay_sysreftoadc_arr : t_time_arr := (4000 ps,
5000 ps,
6000 ps,
@@ -82,7 +88,8 @@ architecture tb of tb_lofar2_unb2b_adc_multichannel is
1000 ps,
1000 ps,
1000 ps,
- 1000 ps); -- transport delays clock source to adc(tx)
+ -- transport delays clock source to adc(tx)
+ 1000 ps);
constant c_delay_sysreftofpga : time := 10200 ps;
-- clocks and resets for the jesd204b tx
@@ -160,16 +167,24 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -255,7 +270,8 @@ begin
csr_hd => OPEN,
csr_k => OPEN,
csr_l => OPEN,
- csr_lane_powerdown => open, -- out
+ -- out
+ csr_lane_powerdown => open,
csr_m => OPEN,
csr_n => OPEN,
csr_np => OPEN,
@@ -265,8 +281,10 @@ begin
csr_tx_testpattern_c => OPEN,
csr_tx_testpattern_d => OPEN,
csr_s => OPEN,
- dev_sync_n => dev_sync_n(i), -- out
- jesd204_tx_avs_chipselect => avs_chipselect(i), -- jesd204b_mosi_arr(i).chipselect,
+ -- out
+ dev_sync_n => dev_sync_n(i),
+ -- jesd204b_mosi_arr(i).chipselect,
+ jesd204_tx_avs_chipselect => avs_chipselect(i),
jesd204_tx_avs_address => avs_address(i),
jesd204_tx_avs_read => avs_read(i),
jesd204_tx_avs_readdata => avs_readdata(i),
@@ -275,19 +293,29 @@ begin
jesd204_tx_avs_writedata => (others => '0'),
jesd204_tx_avs_clk => mm_clk,
jesd204_tx_avs_rst_n => avs_rst_n,
- jesd204_tx_dlb_data => open, -- debug/loopback testing
- jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
+ -- debug/loopback testing
+ jesd204_tx_dlb_data => open,
+ -- debug/loopback testing
+ jesd204_tx_dlb_kchar_data => open,
jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
jesd204_tx_frame_error => '0',
- jesd204_tx_int => OPEN, -- Connected to status IO in example design
- jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), -- in
- jesd204_tx_link_valid => jesd204b_tx_link_valid(i), -- in
- jesd204_tx_link_ready => jesd204b_tx_link_ready(i), -- out
- mdev_sync_n => dev_sync_n(i), -- in
- pll_locked => pll_locked, -- in
- sync_n => jesd204b_sync_n_adc(i), -- in
+ -- Connected to status IO in example design
+ jesd204_tx_int => OPEN,
+ -- in
+ jesd204_tx_link_data => jesd204b_tx_link_data_arr(i),
+ -- in
+ jesd204_tx_link_valid => jesd204b_tx_link_valid(i),
+ -- out
+ jesd204_tx_link_ready => jesd204b_tx_link_ready(i),
+ -- in
+ mdev_sync_n => dev_sync_n(i),
+ -- in
+ pll_locked => pll_locked,
+ -- in
+ sync_n => jesd204b_sync_n_adc(i),
tx_analogreset => tx_analogreset,
- tx_bonding_clocks => tx_bonding_clocks, -- : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ -- : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_bonding_clocks => tx_bonding_clocks,
tx_cal_busy => open,
tx_digitalreset => tx_digitalreset,
tx_serial_data => serial_tx(i downto i),
@@ -377,7 +405,8 @@ begin
tx_bonding_clocks(0) <= transport bonding_clock_0 after 4000 ps;
-- Sample Clock
- jesd204b_sampclk <= not jesd204b_sampclk after c_jesd204b_sampclk_period / 2; -- JESD sample clock (200MHz)
+ -- JESD sample clock (200MHz)
+ jesd204b_sampclk <= not jesd204b_sampclk after c_jesd204b_sampclk_period / 2;
-- clock source process
@@ -416,7 +445,8 @@ begin
wait until avs_rst_n = '1';
while true loop
wait until rising_edge(mm_clk);
- avs_address(0) <= X"14"; -- dll control
+ -- dll control
+ avs_address(0) <= X"14";
avs_chipselect(0) <= '1';
avs_read(0) <= '1';
wait for c_mm_clk_period * 1;
@@ -426,7 +456,8 @@ begin
avs_read(0) <= '0';
wait for c_mm_clk_period * 32;
wait until rising_edge(mm_clk);
- avs_address(0) <= X"15"; -- syncn_sysref control
+ -- syncn_sysref control
+ avs_address(0) <= X"15";
avs_chipselect(0) <= '1';
avs_read(0) <= '1';
wait for c_mm_clk_period * 1;
@@ -437,7 +468,8 @@ begin
wait for c_mm_clk_period * 32;
wait until rising_edge(mm_clk);
- avs_address(0) <= X"18"; -- syncn_sysref control
+ -- syncn_sysref control
+ avs_address(0) <= X"18";
avs_chipselect(0) <= '1';
avs_read(0) <= '1';
wait for c_mm_clk_period * 1;
@@ -447,7 +479,8 @@ begin
avs_read(0) <= '0';
wait for c_mm_clk_period * 32;
wait until rising_edge(mm_clk);
- avs_address(0) <= X"19"; -- syncn_sysref control
+ -- syncn_sysref control
+ avs_address(0) <= X"19";
avs_chipselect(0) <= '1';
avs_read(0) <= '1';
wait for c_mm_clk_period * 1;
@@ -458,7 +491,8 @@ begin
wait for c_mm_clk_period * 32;
wait until rising_edge(mm_clk);
- avs_address(0) <= X"20"; -- tx control0
+ -- tx control0
+ avs_address(0) <= X"20";
avs_chipselect(0) <= '1';
avs_read(0) <= '1';
wait for c_mm_clk_period * 1;
@@ -468,7 +502,8 @@ begin
avs_read(0) <= '0';
wait for c_mm_clk_period * 32;
wait until rising_edge(mm_clk);
- avs_address(0) <= X"26"; -- tx control0
+ -- tx control0
+ avs_address(0) <= X"26";
avs_chipselect(0) <= '1';
avs_read(0) <= '1';
wait for c_mm_clk_period * 1;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
index 470c7ab17576fd1237034c445cf190d39a3004df..c3fc1779f75e5b8a01833a81250bf2f782b5d681 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
@@ -63,29 +63,36 @@ end tb_lofar2_unb2b_adc_wg;
architecture tb of tb_lofar2_unb2b_adc_wg is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_cable_delay : time := 12 ns;
- constant c_sample_freq : natural := c_unb2b_board_ext_clk_freq_200M / 10**6; -- 200 MSps
+ -- 200 MSps
+ constant c_sample_freq : natural := c_unb2b_board_ext_clk_freq_200M / 10**6;
constant c_sample_period : time := (10**6 / c_sample_freq) * 1 ps;
constant c_nof_sync : natural := 5;
constant c_nof_block_per_sync : natural := 16;
- constant c_percentage : real := 0.05; -- percentage that actual value may differ from expected value
- constant c_lo_factor : real := 1.0 - c_percentage; -- lower boundary
- constant c_hi_factor : real := 1.0 + c_percentage; -- higher boundary
+ -- percentage that actual value may differ from expected value
+ constant c_percentage : real := 0.05;
+ -- lower boundary
+ constant c_lo_factor : real := 1.0 - c_percentage;
+ -- higher boundary
+ constant c_hi_factor : real := 1.0 + c_percentage;
constant c_nof_points : natural := 1024;
constant c_nof_taps : natural := 16;
@@ -93,16 +100,23 @@ architecture tb of tb_lofar2_unb2b_adc_wg is
constant c_subband_period : time := c_nof_points * c_sample_period;
-- WG
- constant c_full_scale_ampl : real := real(2**(18 - 1) - 1); -- = full scale of WG
- constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp : natural := 2**(14 - 1) / 2; -- in number of lsb
- constant c_subband_sp : real := 51.2; -- Select subband at index 512/10 = 51.2 = 20 MHz
- constant c_wg_subband_freq_unit : real := c_diag_wg_freq_unit / 512.0; -- subband freq = Fs/512 = 200 MSps/512 = 390625 Hz sinus
- constant c_wg_ampl_lsb : real := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
+ -- = full scale of WG
+ constant c_full_scale_ampl : real := real(2**(18 - 1) - 1);
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := 2;
+ -- in number of lsb
+ constant c_ampl_sp : natural := 2**(14 - 1) / 2;
+ -- Select subband at index 512/10 = 51.2 = 20 MHz
+ constant c_subband_sp : real := 51.2;
+ -- subband freq = Fs/512 = 200 MSps/512 = 390625 Hz sinus
+ constant c_wg_subband_freq_unit : real := c_diag_wg_freq_unit / 512.0;
+ -- amplitude in number of LSbit resolution steps
+ constant c_wg_ampl_lsb : real := c_diag_wg_ampl_unit / c_full_scale_ampl;
constant c_exp_wg_power_sp : real := real(c_ampl_sp**2) / 2.0 * real(c_nof_points * c_nof_block_per_sync);
-- ADUH
- constant c_mon_buffer_nof_samples : natural := 1024; -- samples per stream
+ -- samples per stream
+ constant c_mon_buffer_nof_samples : natural := 1024;
constant c_mon_buffer_nof_words : natural := c_mon_buffer_nof_samples;
-- MM
@@ -156,17 +170,26 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -227,7 +250,8 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
@@ -242,9 +266,12 @@ begin
-- Enable BS
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk);
+ -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk);
----------------------------------------------------------------------------
-- Enable WG
@@ -254,10 +281,14 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer(c_subband_sp * c_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp) * c_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer(c_subband_sp * c_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp) * c_wg_ampl_lsb), tb_clk);
-- Read current BSN
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 downto 0), tb_clk);
@@ -268,8 +299,10 @@ begin
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
v_bsn := c_bsn_start_wg;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
-- Wait for ADUH monitor to have filled with WG data
wait for c_subband_period * c_nof_taps;
@@ -279,11 +312,14 @@ begin
-- WG data : read ADUH monitor buffer
----------------------------------------------------------------------------
-- Wait for start of sync interval
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2,
c_subband_period, tb_clk);
- wait for c_subband_period; -- ensure that one block of samples has filled the ADUH monitor buffer after the sync
+ -- ensure that one block of samples has filled the ADUH monitor buffer after the sync
+ wait for c_subband_period;
-- Read via MM
for I in 0 to c_mon_buffer_nof_words - 1 loop
@@ -303,14 +339,18 @@ begin
-- Read ADUH monitor power sum
---------------------------------------------------------------------------
-- Wait for start of sync interval
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3,
c_subband_period, tb_clk);
-- Read ADUH monitor power sum
- mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk); -- read low part
+ -- read low part
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk);
sp_power_sum(31 downto 0) <= unsigned(rd_data);
- mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk); -- read high part
+ -- read high part
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk);
sp_power_sum(63 downto 32) <= unsigned(rd_data);
proc_common_wait_some_cycles(tb_clk, 1);
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
index 90b3f265619797cda4aaf7e0ba26920a0409748c..a128250bed6ff24d8caa02a06d63193b586ed8ab 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2b_beamformer_one_node is
generic (
g_design_name : string := "lofar2_unb2b_beamformer_one_node";
g_design_note : string := "Lofar2 beamformer one node design with all streams";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -72,7 +81,8 @@ entity lofar2_unb2b_beamformer_one_node is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers
QSFP_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -83,7 +93,8 @@ entity lofar2_unb2b_beamformer_one_node is
-- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
index ebaa797084ef9a4b6a073ae64fc2e71cae0a060d..c4a17a087b2675e65e7743806fe10f0766257dec 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2b_beamformer_one_node_256MHz is
generic (
g_design_name : string := "lofar2_unb2b_beamformer_one_node_256MHz";
g_design_note : string := "Lofar2 one node beamformer design with all streams on 256MHz ext clk";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -72,7 +81,8 @@ entity lofar2_unb2b_beamformer_one_node_256MHz is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers
QSFP_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -83,7 +93,8 @@ entity lofar2_unb2b_beamformer_one_node_256MHz is
-- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
index 0d815568ee1674d47062268d8106f9c41ab9358d..27bd79b813c14a752f0361bf737bf58a1dfb65f5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
@@ -46,12 +46,16 @@ entity lofar2_unb2b_beamformer is
g_design_name : string := "lofar2_unb2b_beamformer";
g_design_note : string := "UNUSED";
g_buf_nof_data : natural := 1024;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := false;
g_protect_addr_range : boolean := false;
g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
@@ -59,11 +63,16 @@ entity lofar2_unb2b_beamformer is
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -84,7 +93,8 @@ entity lofar2_unb2b_beamformer is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers
QSFP_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
QSFP_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
@@ -94,7 +104,8 @@ entity lofar2_unb2b_beamformer is
-- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0);
-- Connect to the BCK_RX pins in the top wrapper
- JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
+ -- Connect to BCK_REF_CLK pin in the top level wrapper
+ JESD204B_REFCLK : in std_logic;
-- jesd204b syncronization signals
JESD204B_SYSREF : in std_logic;
@@ -105,13 +116,15 @@ end lofar2_unb2b_beamformer;
architecture str of lofar2_unb2b_beamformer is
-- Revision parameters
constant c_revision_select : t_lofar2_unb2b_beamformer_config := func_sel_revision_rec(g_design_name);
- constant c_nof_streams : natural := c_revision_select.nof_streams_input; -- Streams actually passed through for processing
+ -- Streams actually passed through for processing
+ constant c_nof_streams : natural := c_revision_select.nof_streams_input;
constant c_dp_clk_freq : natural := c_revision_select.dp_clk_freq;
-- Firmware version x.y
constant c_fw_version : t_unb2b_board_fw_version := (1, 1);
constant c_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_100M;
- constant c_lofar2_sample_clk_freq : natural := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS
+ -- alternate 160MHz. TODO: Use to check PPS
+ constant c_lofar2_sample_clk_freq : natural := 200 * 10**6;
-- 10 GbE Interface
constant c_nof_streams_qsfp : natural := 4;
@@ -119,9 +132,11 @@ architecture str of lofar2_unb2b_beamformer is
constant c_nof_10GbE_offload_streams : natural := 1;
constant c_nof_blocks_per_packet : natural := 4;
constant c_nof_beamlets_per_block : natural := c_sdp_N_pol * c_sdp_S_sub_bf;
- constant c_10GbE_block_size : natural := c_nof_blocks_per_packet * c_nof_beamlets_per_block / 4; -- 4 beamlets fit in 1 64bit longword
+ -- 4 beamlets fit in 1 64bit longword
+ constant c_10GbE_block_size : natural := c_nof_blocks_per_packet * c_nof_beamlets_per_block / 4;
constant c_fifo_tx_fill : natural := c_10GbE_block_size;
- constant c_fifo_tx_size : natural := c_fifo_tx_fill + 11; -- Make fifo size large enough for adding header.
+ -- Make fifo size large enough for adding header.
+ constant c_fifo_tx_size : natural := c_fifo_tx_fill + 11;
-- Address widths of a single MM instance
constant c_addr_w_ram_ss_ss_wide : natural := ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
@@ -132,8 +147,10 @@ architecture str of lofar2_unb2b_beamformer is
constant c_addr_w_ram_st_bst : natural := ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol * (c_longword_sz / c_word_sz));
-- Read only sdp_info values
- constant c_f_adc : std_logic := '1'; -- '0' => 160M, '1' => 200M
- constant c_fsub_type : std_logic := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
+ -- '0' => 160M, '1' => 200M
+ constant c_f_adc : std_logic := '1';
+ -- '0' => critical sampled PFB, '1' => oversampled PFB
+ constant c_fsub_type : std_logic := '0';
signal gn_id : std_logic_vector(c_sdp_W_gn_id - 1 downto 0);
signal gn_index : natural := 0;
@@ -182,12 +199,16 @@ architecture str of lofar2_unb2b_beamformer is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -418,7 +439,8 @@ begin
mm_rst => mm_rst,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ -- Can be external 200MHz, or PLL generated
+ dp_clk => dp_clk,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
@@ -635,8 +657,10 @@ begin
u_sdp_info : entity lofar2_sdp_lib.sdp_info
port map(
-- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst => mm_rst,
+ -- memory-mapped bus clock
+ mm_clk => mm_clk,
dp_clk => dp_clk,
dp_rst => dp_rst,
@@ -659,11 +683,15 @@ begin
gn_id <= ID(c_sdp_W_gn_id - 1 downto 0);
gn_index <= TO_UINT(gn_id);
-- derive MAC, IP and UDP Port
- cep_eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
- cep_ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
+ -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
+ cep_eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w);
+ -- +1 to avoid IP = *.*.*.0
+ cep_ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1);
cep_udp_src_port <= c_sdp_cep_udp_src_port_15_8 & ID;
- stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
- stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
+ -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
+ stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w);
+ -- +1 to avoid IP = *.*.*.0
+ stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1);
sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
bst_udp_src_port <= c_sdp_bst_udp_src_port_15_8 & ID;
@@ -890,8 +918,10 @@ begin
generic map (
g_nof_input => c_sdp_N_beamsets,
g_sel_ctrl_invert => true,
- g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
+ -- no FIFO used but must match g_nof_input
+ g_fifo_size => array_init(0,c_sdp_N_beamsets),
+ -- no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0,c_sdp_N_beamsets)
)
port map (
clk => dp_clk,
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
index 27f912bd203d366a6d1cafe3ffe0fad8ae38d046..8e7f230db5c8854a94917f3d14eb806efa3935f9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
@@ -32,7 +32,8 @@ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2b_beamformer is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
index 1df2a17b4164dfe45e634bc1c67f6ca4b3a2b35b..cf3ba6838eabdf934d34ed909b2ab125eed84342 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
@@ -27,322 +27,638 @@ package qsys_lofar2_unb2b_beamformer_pkg is
-----------------------------------------------------------------------------
component qsys_lofar2_unb2b_beamformer is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buf_bsn_read_export : out std_logic; -- export
- ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buf_bsn_write_export : out std_logic; -- export
- ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buf_bsn_read_export : out std_logic; -- export
- reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buf_bsn_write_export : out std_logic; -- export
- reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- export
+ jesd204b_address_export : out std_logic_vector(11 downto 0);
+ -- export
+ jesd204b_clk_export : out std_logic;
+ -- export
+ jesd204b_read_export : out std_logic;
+ -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ jesd204b_reset_export : out std_logic;
+ -- export
+ jesd204b_write_export : out std_logic;
+ -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ ram_aduh_monitor_clk_export : out std_logic;
+ -- export
+ ram_aduh_monitor_read_export : out std_logic;
+ -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_aduh_monitor_reset_export : out std_logic;
+ -- export
+ ram_aduh_monitor_write_export : out std_logic;
+ -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0);
+ -- export
+ ram_bf_weights_clk_export : out std_logic;
+ -- export
+ ram_bf_weights_read_export : out std_logic;
+ -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_bf_weights_reset_export : out std_logic;
+ -- export
+ ram_bf_weights_write_export : out std_logic;
+ -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_diag_data_buf_bsn_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buf_bsn_read_export : out std_logic;
+ -- export
+ ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buf_bsn_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buf_bsn_write_export : out std_logic;
+ -- export
+ ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0);
+ -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ ram_equalizer_gains_clk_export : out std_logic;
+ -- export
+ ram_equalizer_gains_read_export : out std_logic;
+ -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_equalizer_gains_reset_export : out std_logic;
+ -- export
+ ram_equalizer_gains_write_export : out std_logic;
+ -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_fil_coefs_clk_export : out std_logic;
+ -- export
+ ram_fil_coefs_read_export : out std_logic;
+ -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_fil_coefs_reset_export : out std_logic;
+ -- export
+ ram_fil_coefs_write_export : out std_logic;
+ -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0);
+ -- export
+ ram_scrap_clk_export : out std_logic;
+ -- export
+ ram_scrap_read_export : out std_logic;
+ -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_scrap_reset_export : out std_logic;
+ -- export
+ ram_scrap_write_export : out std_logic;
+ -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_ss_ss_wide_clk_export : out std_logic;
+ -- export
+ ram_ss_ss_wide_read_export : out std_logic;
+ -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_ss_ss_wide_reset_export : out std_logic;
+ -- export
+ ram_ss_ss_wide_write_export : out std_logic;
+ -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0);
+ -- export
+ ram_st_bst_clk_export : out std_logic;
+ -- export
+ ram_st_bst_read_export : out std_logic;
+ -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_st_bst_reset_export : out std_logic;
+ -- export
+ ram_st_bst_write_export : out std_logic;
+ -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_st_sst_clk_export : out std_logic;
+ -- export
+ ram_st_sst_read_export : out std_logic;
+ -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_st_sst_reset_export : out std_logic;
+ -- export
+ ram_st_sst_write_export : out std_logic;
+ -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_wg_clk_export : out std_logic;
+ -- export
+ ram_wg_read_export : out std_logic;
+ -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_wg_reset_export : out std_logic;
+ -- export
+ ram_wg_write_export : out std_logic;
+ -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_aduh_monitor_clk_export : out std_logic;
+ -- export
+ reg_aduh_monitor_read_export : out std_logic;
+ -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_aduh_monitor_reset_export : out std_logic;
+ -- export
+ reg_aduh_monitor_write_export : out std_logic;
+ -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_bf_scale_clk_export : out std_logic;
+ -- export
+ reg_bf_scale_read_export : out std_logic;
+ -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bf_scale_reset_export : out std_logic;
+ -- export
+ reg_bf_scale_write_export : out std_logic;
+ -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0);
+ -- export
+ reg_bsn_monitor_input_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_input_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_bsn_scheduler_clk_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_read_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_scheduler_reset_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_write_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_bsn_source_clk_export : out std_logic;
+ -- export
+ reg_bsn_source_read_export : out std_logic;
+ -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_source_reset_export : out std_logic;
+ -- export
+ reg_bsn_source_write_export : out std_logic;
+ -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buf_bsn_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buf_bsn_read_export : out std_logic;
+ -- export
+ reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buf_bsn_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buf_bsn_write_export : out std_logic;
+ -- export
+ reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dp_selector_clk_export : out std_logic;
+ -- export
+ reg_dp_selector_read_export : out std_logic;
+ -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_selector_reset_export : out std_logic;
+ -- export
+ reg_dp_selector_write_export : out std_logic;
+ -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_dp_shiftram_clk_export : out std_logic;
+ -- export
+ reg_dp_shiftram_read_export : out std_logic;
+ -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_shiftram_reset_export : out std_logic;
+ -- export
+ reg_dp_shiftram_write_export : out std_logic;
+ -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_dp_xonoff_clk_export : out std_logic;
+ -- export
+ reg_dp_xonoff_read_export : out std_logic;
+ -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_xonoff_reset_export : out std_logic;
+ -- export
+ reg_dp_xonoff_write_export : out std_logic;
+ -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_hdr_dat_clk_export : out std_logic;
+ -- export
+ reg_hdr_dat_read_export : out std_logic;
+ -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_hdr_dat_reset_export : out std_logic;
+ -- export
+ reg_hdr_dat_write_export : out std_logic;
+ -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic;
+ -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic;
+ -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic;
+ -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic;
+ -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic;
+ -- export
+ reg_nw_10gbe_mac_read_export : out std_logic;
+ -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic;
+ -- export
+ reg_nw_10gbe_mac_write_export : out std_logic;
+ -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_sdp_info_clk_export : out std_logic;
+ -- export
+ reg_sdp_info_read_export : out std_logic;
+ -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_sdp_info_reset_export : out std_logic;
+ -- export
+ reg_sdp_info_write_export : out std_logic;
+ -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_si_clk_export : out std_logic;
+ -- export
+ reg_si_read_export : out std_logic;
+ -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_si_reset_export : out std_logic;
+ -- export
+ reg_si_write_export : out std_logic;
+ -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic;
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_wg_clk_export : out std_logic;
+ -- export
+ reg_wg_read_export : out std_logic;
+ -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wg_reset_export : out std_logic;
+ -- export
+ reg_wg_write_export : out std_logic;
+ -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0)
);
end component qsys_lofar2_unb2b_beamformer;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
index aef82a89ff36116894d3267561d23df702a525e7..38d0199a6d30417820873d8ad4ed6e205e04ef6e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
@@ -69,49 +69,67 @@ end tb_lofar2_unb2b_beamformer;
architecture tb of tb_lofar2_unb2b_beamformer is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
+ -- 644MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
constant c_pps_period : natural := 1000;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_cable_delay : time := 12 ns;
constant c_nof_block_per_sync : natural := 16;
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
- constant c_percentage : real := 0.05; -- percentage that actual value may differ from expected value
- constant c_lo_factor : real := 1.0 - c_percentage; -- lower boundary
- constant c_hi_factor : real := 1.0 + c_percentage; -- higher boundary
+ -- percentage that actual value may differ from expected value
+ constant c_percentage : real := 0.05;
+ -- lower boundary
+ constant c_lo_factor : real := 1.0 - c_percentage;
+ -- higher boundary
+ constant c_hi_factor : real := 1.0 + c_percentage;
-- WG
- constant c_full_scale_ampl : real := real(2**(14 - 1) - 1); -- = full scale of WG
- constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp_0 : natural := 2**(c_sdp_W_adc - 1) / 2; -- in number of lsb
- constant c_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
- constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
- constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- constant c_wg_ampl_lsb : real := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
+ -- = full scale of WG
+ constant c_full_scale_ampl : real := real(2**(14 - 1) - 1);
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := 2;
+ -- in number of lsb
+ constant c_ampl_sp_0 : natural := 2**(c_sdp_W_adc - 1) / 2;
+ -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+ constant c_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_sdp_N_fft);
+ -- in freq_unit
+ constant c_wg_freq_offset : real := 0.0 / 11.0;
+ -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ constant c_subband_sp_0 : real := 102.0;
+ -- amplitude in number of LSbit resolution steps
+ constant c_wg_ampl_lsb : real := c_diag_wg_ampl_unit / c_full_scale_ampl;
constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_sdp_N_fft * c_nof_block_per_sync);
-- WPFB
- constant c_wb_leakage_bin : natural := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor; -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
- constant c_exp_sp_beamlet_power_ratio : real := 1.0 / 8.0; -- depends on internal WPFB quantization and FIR coefficients
- constant c_exp_sp_beamlet_power_sum_ratio : real := c_exp_sp_beamlet_power_ratio; -- because all sinus power is expected in one subband
+ -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
+ constant c_wb_leakage_bin : natural := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor;
+ -- depends on internal WPFB quantization and FIR coefficients
+ constant c_exp_sp_beamlet_power_ratio : real := 1.0 / 8.0;
+ -- because all sinus power is expected in one subband
+ constant c_exp_sp_beamlet_power_sum_ratio : real := c_exp_sp_beamlet_power_ratio;
constant c_exp_beamlet_power_sp_0 : real := c_exp_wg_power_sp_0 * c_exp_sp_beamlet_power_ratio;
type t_real_arr is array (integer range <>) of real;
type t_slv_64_subbands_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_S_sub_bf);
-- ADUH
- constant c_mon_buffer_nof_samples : natural := 512; -- samples per stream
+ -- samples per stream
+ constant c_mon_buffer_nof_samples : natural := 512;
constant c_mon_buffer_nof_words : natural := c_mon_buffer_nof_samples;
-- MM
@@ -139,9 +157,11 @@ architecture tb of tb_lofar2_unb2b_beamformer is
signal current_bsn_wg : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
-- WPFB
- signal sp_subband_powers_arr2 : t_slv_64_subbands_arr(c_sdp_N_beamsets * c_sdp_N_pol - 1 downto 0); -- [sp][sub]
+ -- [sp][sub]
+ signal sp_subband_powers_arr2 : t_slv_64_subbands_arr(c_sdp_N_beamsets * c_sdp_N_pol - 1 downto 0);
- signal sp_beamlet_powers_arr2 : t_slv_64_subbands_arr(c_sdp_N_beamsets * c_sdp_N_pol - 1 downto 0); -- [sp][sub]
+ -- [sp][sub]
+ signal sp_beamlet_powers_arr2 : t_slv_64_subbands_arr(c_sdp_N_beamsets * c_sdp_N_pol - 1 downto 0);
signal sp_beamlet_power_0 : real;
signal sp_beamlet_power_sum : t_real_arr(c_sdp_N_beamsets * c_sdp_N_pol - 1 downto 0) := (others => 0.0);
signal sp_beamlet_power_sum_0 : real;
@@ -151,8 +171,10 @@ architecture tb of tb_lofar2_unb2b_beamformer is
-- 10GbE
constant c_exp_beamlet_index : natural := natural(c_subband_sp_0) * c_sdp_N_pol;
- constant c_exp_beamlet_re : std_logic_vector(7 downto 0) := x"81"; -- Derived from simulation
- constant c_exp_beamlet_im : std_logic_vector(7 downto 0) := x"7F"; -- Derived from simulation
+ -- Derived from simulation
+ constant c_exp_beamlet_re : std_logic_vector(7 downto 0) := x"81";
+ -- Derived from simulation
+ constant c_exp_beamlet_im : std_logic_vector(7 downto 0) := x"7F";
signal beamlet_arr2_re : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block - 1 downto 0);
signal beamlet_arr2_im : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block - 1 downto 0);
@@ -195,19 +217,29 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
- SA_CLK <= not SA_CLK after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ SA_CLK <= not SA_CLK after c_sa_clk_period / 2;
pps_rst <= '0' after c_ext_clk_period * 2;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -293,9 +325,12 @@ begin
port map (
-- Transceiver PLL reference clock
tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => tr_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => tr_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156,
-- MM interface
mm_rst => pps_rst,
@@ -314,14 +349,16 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
variable v_sp_power_sum_0 : real;
variable v_sp_beamlet_power : real;
variable v_sp_subband_power : real;
- variable v_W, v_T, v_U, v_S, v_B : natural; -- array indicies
+ -- array indicies
+ variable v_W, v_T, v_U, v_S, v_B : natural;
begin
-- Wait for DUT power up after reset
wait for 1 us;
@@ -338,9 +375,12 @@ begin
-- Enable BS
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk);
+ -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk);
----------------------------------------------------------------------------
-- Enable WG
@@ -350,10 +390,14 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk);
-- Read current BSN
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 downto 0), tb_clk);
@@ -364,12 +408,16 @@ begin
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
v_bsn := c_bsn_start_wg;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
-- Wait for enough WG data and start of sync interval
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3,
c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
@@ -452,7 +500,8 @@ begin
-- Read 10GbE Stream
---------------------------------------------------------------------------
proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.sop);
- for I in 0 to 8 loop -- Packet header is 9.25 words wide, which can be discarded
+ -- Packet header is 9.25 words wide, which can be discarded
+ for I in 0 to 8 loop
proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
proc_common_wait_some_cycles(ext_clk, 1);
end loop;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
index bae7a2ad5adc1e17b9214db699ee4da18638515d..9c74e8ed96e3711f0365028419c59241c4bf01f6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2b_filterbank_full is
generic (
g_design_name : string := "lofar2_unb2b_filterbank_full";
g_design_note : string := "Lofar2 filterbank with all streams";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -76,7 +85,8 @@ entity lofar2_unb2b_filterbank_full is
-- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
index e541eecf75e176cc2737f809a6499ac7cc2f8d40..74ef93443666290324d33b2e11ad16fb3a9e9fbe 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2b_filterbank_full_256MHz is
generic (
g_design_name : string := "lofar2_unb2b_filterbank_full_256MHz";
g_design_note : string := "Lofar2 filterbank with all streams on 256MHz ext clk";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -76,7 +85,8 @@ entity lofar2_unb2b_filterbank_full_256MHz is
-- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
index 9a0af000e4e08da7987274fa4ee76a468ce5f354..1851aa05a0214c92b6d7693d77122734d3345dae 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
@@ -46,13 +46,17 @@ entity lofar2_unb2b_filterbank is
g_design_name : string := "lofar2_unb2b_filterbank";
g_design_note : string := "UNUSED";
g_buf_nof_data : natural := 1024;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_sim_model_ddr : boolean := false;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := false;
g_protect_addr_range : boolean := false;
g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
@@ -60,11 +64,16 @@ entity lofar2_unb2b_filterbank is
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -90,7 +99,8 @@ entity lofar2_unb2b_filterbank is
-- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
-- Connect to the BCK_RX pins in the top wrapper
- JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
+ -- Connect to BCK_REF_CLK pin in the top level wrapper
+ JESD204B_REFCLK : in std_logic;
-- jesd204b syncronization signals
JESD204B_SYSREF : in std_logic;
@@ -101,19 +111,23 @@ end lofar2_unb2b_filterbank;
architecture str of lofar2_unb2b_filterbank is
-- Revision parameters
constant c_revision_select : t_lofar2_unb2b_filterbank_config := func_sel_revision_rec(g_design_name);
- constant c_nof_streams : natural := c_revision_select.nof_streams_input; -- Streams actually passed through for processing
+ -- Streams actually passed through for processing
+ constant c_nof_streams : natural := c_revision_select.nof_streams_input;
constant c_dp_clk_freq : natural := c_revision_select.dp_clk_freq;
-- Firmware version x.y
constant c_fw_version : t_unb2b_board_fw_version := (2, 0);
constant c_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_100M;
- constant c_lofar2_sample_clk_freq : natural := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS
+ -- alternate 160MHz. TODO: Use to check PPS
+ constant c_lofar2_sample_clk_freq : natural := 200 * 10**6;
constant c_udp_offload_nof_streams : natural := c_eth_nof_udp_ports;
-- Read only sdp_info values
- constant c_f_adc : std_logic := '1'; -- '0' => 160M, '1' => 200M
- constant c_fsub_type : std_logic := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
+ -- '0' => 160M, '1' => 200M
+ constant c_f_adc : std_logic := '1';
+ -- '0' => critical sampled PFB, '1' => oversampled PFB
+ constant c_fsub_type : std_logic := '0';
signal gn_id : std_logic_vector(c_sdp_W_gn_id - 1 downto 0);
signal gn_index : natural := 0;
@@ -162,12 +176,16 @@ architecture str of lofar2_unb2b_filterbank is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -328,7 +346,8 @@ begin
mm_rst => mm_rst,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ -- Can be external 200MHz, or PLL generated
+ dp_clk => dp_clk,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
@@ -543,15 +562,19 @@ begin
gn_id <= ID(c_sdp_W_gn_id - 1 downto 0);
gn_index <= TO_UINT(gn_id);
-- derive MAC, IP and UDP Port
- stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
- stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
+ -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
+ stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w);
+ -- +1 to avoid IP = *.*.*.0
+ stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1);
sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
u_sdp_info : entity lofar2_sdp_lib.sdp_info
port map(
-- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst => mm_rst,
+ -- memory-mapped bus clock
+ mm_clk => mm_clk,
dp_clk => dp_clk,
dp_rst => dp_rst,
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
index 736f555d99d7bab483adde375befeb779fe9e9e7..eb8d157878fcc9b5fce8e62db2a30bf3a5379cb1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
@@ -32,7 +32,8 @@ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2b_filterbank is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
index 21dc8f5640f021b9394624c55618ecaf3286de3a..46155e9a7fe8e7cffe553c9fe41ed65d06f14b5d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
@@ -27,290 +27,571 @@ package qsys_lofar2_unb2b_filterbank_pkg is
-----------------------------------------------------------------------------
component qsys_lofar2_unb2b_filterbank is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buf_bsn_read_export : out std_logic; -- export
- ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buf_bsn_write_export : out std_logic; -- export
- ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- export
+ jesd204b_address_export : out std_logic_vector(11 downto 0);
+ -- export
+ jesd204b_clk_export : out std_logic;
+ -- export
+ jesd204b_read_export : out std_logic;
+ -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ jesd204b_reset_export : out std_logic;
+ -- export
+ jesd204b_write_export : out std_logic;
+ -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ ram_aduh_monitor_clk_export : out std_logic;
+ -- export
+ ram_aduh_monitor_read_export : out std_logic;
+ -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_aduh_monitor_reset_export : out std_logic;
+ -- export
+ ram_aduh_monitor_write_export : out std_logic;
+ -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_diag_data_buf_bsn_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buf_bsn_read_export : out std_logic;
+ -- export
+ ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buf_bsn_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buf_bsn_write_export : out std_logic;
+ -- export
+ ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0);
+ -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ ram_equalizer_gains_clk_export : out std_logic;
+ -- export
+ ram_equalizer_gains_read_export : out std_logic;
+ -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_equalizer_gains_reset_export : out std_logic;
+ -- export
+ ram_equalizer_gains_write_export : out std_logic;
+ -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_fil_coefs_clk_export : out std_logic;
+ -- export
+ ram_fil_coefs_read_export : out std_logic;
+ -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_fil_coefs_reset_export : out std_logic;
+ -- export
+ ram_fil_coefs_write_export : out std_logic;
+ -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0);
+ -- export
+ ram_scrap_clk_export : out std_logic;
+ -- export
+ ram_scrap_read_export : out std_logic;
+ -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_scrap_reset_export : out std_logic;
+ -- export
+ ram_scrap_write_export : out std_logic;
+ -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_st_sst_clk_export : out std_logic;
+ -- export
+ ram_st_sst_read_export : out std_logic;
+ -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_st_sst_reset_export : out std_logic;
+ -- export
+ ram_st_sst_write_export : out std_logic;
+ -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_wg_clk_export : out std_logic;
+ -- export
+ ram_wg_read_export : out std_logic;
+ -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_wg_reset_export : out std_logic;
+ -- export
+ ram_wg_write_export : out std_logic;
+ -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0);
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_clk_export : out std_logic; -- export
- reg_stat_enable_read_export : out std_logic; -- export
- reg_stat_enable_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_reset_export : out std_logic; -- export
- reg_stat_enable_write_export : out std_logic; -- export
- reg_stat_enable_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_read_export : out std_logic; -- export
- reg_stat_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_write_export : out std_logic; -- export
- reg_stat_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_sdp_info_clk_export : out std_logic;
+ -- export
+ reg_sdp_info_read_export : out std_logic;
+ -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_sdp_info_reset_export : out std_logic;
+ -- export
+ reg_sdp_info_write_export : out std_logic;
+ -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stat_enable_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_stat_enable_clk_export : out std_logic;
+ -- export
+ reg_stat_enable_read_export : out std_logic;
+ -- export
+ reg_stat_enable_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stat_enable_reset_export : out std_logic;
+ -- export
+ reg_stat_enable_write_export : out std_logic;
+ -- export
+ reg_stat_enable_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stat_hdr_dat_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_stat_hdr_dat_clk_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_read_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stat_hdr_dat_reset_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_write_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_aduh_monitor_clk_export : out std_logic;
+ -- export
+ reg_aduh_monitor_read_export : out std_logic;
+ -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_aduh_monitor_reset_export : out std_logic;
+ -- export
+ reg_aduh_monitor_write_export : out std_logic;
+ -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0);
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buf_bsn_read_export : out std_logic; -- export
- reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buf_bsn_write_export : out std_logic; -- export
- reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0);
+ -- export
+ reg_bsn_monitor_input_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_input_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_bsn_scheduler_clk_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_read_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_scheduler_reset_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_write_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_bsn_source_clk_export : out std_logic;
+ -- export
+ reg_bsn_source_read_export : out std_logic;
+ -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_source_reset_export : out std_logic;
+ -- export
+ reg_bsn_source_write_export : out std_logic;
+ -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buf_bsn_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buf_bsn_read_export : out std_logic;
+ -- export
+ reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buf_bsn_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buf_bsn_write_export : out std_logic;
+ -- export
+ reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dp_selector_clk_export : out std_logic;
+ -- export
+ reg_dp_selector_read_export : out std_logic;
+ -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_selector_reset_export : out std_logic;
+ -- export
+ reg_dp_selector_write_export : out std_logic;
+ -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_dp_shiftram_clk_export : out std_logic;
+ -- export
+ reg_dp_shiftram_read_export : out std_logic;
+ -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_shiftram_reset_export : out std_logic;
+ -- export
+ reg_dp_shiftram_write_export : out std_logic;
+ -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_si_clk_export : out std_logic;
+ -- export
+ reg_si_read_export : out std_logic;
+ -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_si_reset_export : out std_logic;
+ -- export
+ reg_si_write_export : out std_logic;
+ -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic;
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_wg_clk_export : out std_logic;
+ -- export
+ reg_wg_read_export : out std_logic;
+ -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wg_reset_export : out std_logic;
+ -- export
+ reg_wg_write_export : out std_logic;
+ -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_jesd_ctrl_reset_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_clk_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_jesd_ctrl_write_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_jesd_ctrl_read_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X')
);
end component qsys_lofar2_unb2b_filterbank;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
index a0ade62951545450169b348d329fc8db6ee5de08..f831e804ef942970cbf9769b10de0524a1346521 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
@@ -70,49 +70,67 @@ end tb_lofar2_unb2b_filterbank;
architecture tb of tb_lofar2_unb2b_filterbank is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_cable_delay : time := 12 ns;
constant c_nof_block_per_sync : natural := 16;
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
- constant c_percentage : real := 0.05; -- percentage that actual value may differ from expected value
- constant c_lo_factor : real := 1.0 - c_percentage; -- lower boundary
- constant c_hi_factor : real := 1.0 + c_percentage; -- higher boundary
+ -- percentage that actual value may differ from expected value
+ constant c_percentage : real := 0.05;
+ -- lower boundary
+ constant c_lo_factor : real := 1.0 - c_percentage;
+ -- higher boundary
+ constant c_hi_factor : real := 1.0 + c_percentage;
-- WG
- constant c_full_scale_ampl : real := real(2**(18 - 1) - 1); -- = full scale of WG
- constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp_0 : natural := 2**(c_sdp_W_adc - 1) / 2; -- in number of lsb
- constant c_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
- constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
- constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- constant c_wg_ampl_lsb : real := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
+ -- = full scale of WG
+ constant c_full_scale_ampl : real := real(2**(18 - 1) - 1);
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := 2;
+ -- in number of lsb
+ constant c_ampl_sp_0 : natural := 2**(c_sdp_W_adc - 1) / 2;
+ -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+ constant c_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_sdp_N_fft);
+ -- in freq_unit
+ constant c_wg_freq_offset : real := 0.0 / 11.0;
+ -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ constant c_subband_sp_0 : real := 102.0;
+ -- amplitude in number of LSbit resolution steps
+ constant c_wg_ampl_lsb : real := c_diag_wg_ampl_unit / c_full_scale_ampl;
constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_sdp_N_fft * c_nof_block_per_sync);
-- WPFB
- constant c_nof_pfb : natural := 1; -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
- constant c_wb_leakage_bin : natural := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor; -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
- constant c_exp_sp_subband_power_ratio : real := 1.0 / 8.0; -- depends on internal WPFB quantization and FIR coefficients
- constant c_exp_sp_subband_power_sum_ratio : real := c_exp_sp_subband_power_ratio; -- because all sinus power is expected in one subband
+ -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
+ constant c_nof_pfb : natural := 1;
+ -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
+ constant c_wb_leakage_bin : natural := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor;
+ -- depends on internal WPFB quantization and FIR coefficients
+ constant c_exp_sp_subband_power_ratio : real := 1.0 / 8.0;
+ -- because all sinus power is expected in one subband
+ constant c_exp_sp_subband_power_sum_ratio : real := c_exp_sp_subband_power_ratio;
constant c_exp_subband_power_sp_0 : real := c_exp_wg_power_sp_0 * c_exp_sp_subband_power_ratio;
type t_real_arr is array (integer range <>) of real;
type t_slv_64_subbands_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_sub);
-- ADUH
- constant c_mon_buffer_nof_samples : natural := 512; -- samples per stream
+ -- samples per stream
+ constant c_mon_buffer_nof_samples : natural := 512;
constant c_mon_buffer_nof_words : natural := c_mon_buffer_nof_samples;
-- MM
@@ -138,7 +156,8 @@ architecture tb of tb_lofar2_unb2b_filterbank is
signal current_bsn_wg : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
-- WPFB
- signal sp_subband_powers_arr2 : t_slv_64_subbands_arr(c_nof_pfb * c_nof_complex - 1 downto 0); -- [sp][sub]
+ -- [sp][sub]
+ signal sp_subband_powers_arr2 : t_slv_64_subbands_arr(c_nof_pfb * c_nof_complex - 1 downto 0);
signal sp_subband_power_0 : real;
signal sp_subband_power_sum : t_real_arr(c_nof_pfb * c_nof_complex - 1 downto 0) := (others => 0.0);
signal sp_subband_power_sum_0 : real;
@@ -176,17 +195,26 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -249,13 +277,15 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
variable v_sp_power_sum_0 : real;
variable v_sp_subband_power : real;
- variable v_W, v_T, v_U, v_S, v_B : natural; -- array indicies
+ -- array indicies
+ variable v_W, v_T, v_U, v_S, v_B : natural;
begin
-- Wait for DUT power up after reset
wait for 1 us;
@@ -266,9 +296,12 @@ begin
-- Enable BS
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk);
+ -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk);
----------------------------------------------------------------------------
-- Enable WG
@@ -278,10 +311,14 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk);
-- Read current BSN
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 downto 0), tb_clk);
@@ -292,8 +329,10 @@ begin
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
v_bsn := c_bsn_start_wg;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
-- Wait for ADUH monitor to have filled with WG data
wait for c_sdp_T_sub * c_sdp_N_taps;
@@ -303,11 +342,14 @@ begin
-- WG data : read ADUH monitor buffer
----------------------------------------------------------------------------
-- Wait for start of sync interval
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2,
c_sdp_T_sub, tb_clk);
- wait for c_sdp_T_sub; -- ensure that one block of samples has filled the ADUH monitor buffer after the sync
+ -- ensure that one block of samples has filled the ADUH monitor buffer after the sync
+ wait for c_sdp_T_sub;
-- Read via MM
for I in 0 to c_mon_buffer_nof_words - 1 loop
@@ -327,14 +369,18 @@ begin
-- Read ADUH monitor power sum
---------------------------------------------------------------------------
-- Wait for start of sync interval
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3,
c_sdp_T_sub, tb_clk);
-- Read ADUH monitor power sum
- mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk); -- read low part
+ -- read low part
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk);
sp_power_sum(31 downto 0) <= rd_data;
- mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk); -- read high part
+ -- read high part
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk);
sp_power_sum(63 downto 32) <= rd_data;
proc_common_wait_some_cycles(tb_clk, 1);
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
index afbced0491d2897686cfa308ee72ff868e9ab676..d0f29abff63c15dc9dbccb79a114d7bf8133d6fe 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2b_ring_full is
generic (
g_design_name : string := "lofar2_unb2b_ring_full";
g_design_note : string := "Lofar2 Ring full design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -72,14 +81,16 @@ entity lofar2_unb2b_ring_full is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers
QSFP_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
QSFP_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
index 18ccf3dd9ee22e084b529e1a948256a2e6ecd29d..2f51e9426a218897dc9814c3a9a626ff5cc93e67 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
@@ -46,9 +46,11 @@ architecture tb of tb_lofar2_unb2b_ring_full is
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
+ -- 644MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
constant c_pps_period : natural := 1000;
-- Tb
@@ -84,17 +86,26 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- SA_CLK <= not SA_CLK after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ SA_CLK <= not SA_CLK after c_sa_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- DUT
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
index 86bb45908a0af897cc16e31e7c6369e2846ec416..01ff38437894414552eb01f3fcceb5c3480d29bc 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
@@ -41,20 +41,29 @@ entity lofar2_unb2b_ring_one is
generic (
g_design_name : string := "lofar2_unb2b_ring_one";
g_design_note : string := "Lofar2 Ring one design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -75,14 +84,16 @@ entity lofar2_unb2b_ring_one is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers
QSFP_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
QSFP_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
index eccc9a2de90ef4ffdfb240ba21b931328522b699..dfdbddd95f4c8c87bd6d4e81416b90e3f62bd5b2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
@@ -46,9 +46,11 @@ architecture tb of tb_lofar2_unb2b_ring_one is
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
+ -- 644MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
constant c_pps_period : natural := 1000;
-- Tb
@@ -84,17 +86,26 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- SA_CLK <= not SA_CLK after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ SA_CLK <= not SA_CLK after c_sa_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- DUT
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
index dbf744910f3b14dca09265aa302b51d6732d67f0..d2ca2c4cafb826b160433bb8560f0badd224994a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
@@ -47,23 +47,32 @@ entity lofar2_unb2b_ring is
generic (
g_design_name : string := "lofar2_unb2b_ring";
g_design_note : string := "UNUSED";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_sync_timeout : natural := c_sdp_sim.sync_timeout;
g_sim_unb_nr : natural := c_sdp_sim.unb_nr;
g_sim_node_nr : natural := c_sdp_sim.node_nr;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := false;
g_protect_addr_range : boolean := false
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -84,13 +93,15 @@ entity lofar2_unb2b_ring is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP1 for 10GbE output to CEP.
QSFP_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
QSFP_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
@@ -108,24 +119,32 @@ architecture str of lofar2_unb2b_ring is
-- Firmware version x.y
constant c_fw_version : t_unb2b_board_fw_version := (2, 0);
constant c_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_100M;
- constant c_lofar2_sample_clk_freq : natural := c_sdp_N_clk_per_sync; -- fixed 200 MHz for LOFAR2.0 stage 1
+ -- fixed 200 MHz for LOFAR2.0 stage 1
+ constant c_lofar2_sample_clk_freq : natural := c_sdp_N_clk_per_sync;
-- QSFP
constant c_nof_qsfp_bus : natural := 1;
- constant c_nof_streams_qsfp : natural := c_unb2b_board_tr_qsfp.bus_w * c_nof_qsfp_bus; -- 4
+ -- 4
+ constant c_nof_streams_qsfp : natural := c_unb2b_board_tr_qsfp.bus_w * c_nof_qsfp_bus;
-- RING
constant c_nof_ring_bus : natural := 2;
- constant c_ring_bus_w : natural := 4; -- Using 4 phisically, there are 12
- constant c_nof_streams_ring : natural := c_ring_bus_w * c_nof_ring_bus; -- c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus; -- 8
+ -- Using 4 phisically, there are 12
+ constant c_ring_bus_w : natural := 4;
+ -- c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus; -- 8
+ constant c_nof_streams_ring : natural := c_ring_bus_w * c_nof_ring_bus;
-- 10GbE
- constant c_nof_even_lanes : natural := ceil_div(c_nof_lanes, 2); -- nof lanes transmitting in positive direction. Using ceil_div as c_nof_lanes might be odd.
- constant c_nof_odd_lanes : natural := c_nof_lanes / 2; -- nof lanes transmitting in negative direction. Note for c_nof_lanes = 1 -> c_nof_odd_lanes = 1 / 2 => 0 which is desired.
- constant c_nof_mac : natural := 3 * c_nof_even_lanes; -- must match one of the MAC IP variations, e.g. 3, 12, 24, 48
+ -- nof lanes transmitting in positive direction. Using ceil_div as c_nof_lanes might be odd.
+ constant c_nof_even_lanes : natural := ceil_div(c_nof_lanes, 2);
+ -- nof lanes transmitting in negative direction. Note for c_nof_lanes = 1 -> c_nof_odd_lanes = 1 / 2 => 0 which is desired.
+ constant c_nof_odd_lanes : natural := c_nof_lanes / 2;
+ -- must match one of the MAC IP variations, e.g. 3, 12, 24, 48
+ constant c_nof_mac : natural := 3 * c_nof_even_lanes;
constant c_lane_data_w : natural := 64;
- constant c_lane_packet_length : natural := c_sdp_V_ring_pkt_len_max - c_ring_dp_hdr_field_size; -- = 48 longwords per packet, so the maximum data rate with a packetrate of 195312.5 and all 16 nodes combined = 16 * 48 / 1024 * 64 * 200M = 9.6 Gb/s
+ -- = 48 longwords per packet, so the maximum data rate with a packetrate of 195312.5 and all 16 nodes combined = 16 * 48 / 1024 * 64 * 200M = 9.6 Gb/s
+ constant c_lane_packet_length : natural := c_sdp_V_ring_pkt_len_max - c_ring_dp_hdr_field_size;
constant c_use_dp_layer : boolean := true;
constant c_nof_rx_monitors : natural := c_sdp_N_pn_max;
constant c_nof_tx_monitors : natural := c_sdp_N_pn_max;
@@ -134,14 +153,20 @@ architecture str of lofar2_unb2b_ring is
constant c_bsn_at_sync_check_channel : natural := 1;
constant c_validate_channel : boolean := true;
constant c_validate_channel_mode : string := "=";
- constant c_fifo_tx_fill : natural := c_lane_packet_length + sel_a_b(c_use_dp_layer, c_ring_dp_hdr_field_size, c_ring_eth_hdr_field_size); -- total packet length
+ -- total packet length
+ constant c_fifo_tx_fill : natural := c_lane_packet_length + sel_a_b(c_use_dp_layer, c_ring_dp_hdr_field_size, c_ring_eth_hdr_field_size);
constant c_fifo_tx_size : natural := 2 * c_lane_packet_length;
- constant c_lofar2_sync_timeout : natural := c_lofar2_sample_clk_freq + c_lofar2_sample_clk_freq / 10; -- 10% margin.
+ -- 10% margin.
+ constant c_lofar2_sync_timeout : natural := c_lofar2_sample_clk_freq + c_lofar2_sample_clk_freq / 10;
constant c_sync_timeout : natural := sel_a_b(g_sim, g_sim_sync_timeout, c_lofar2_sync_timeout );
- constant c_nof_if : natural := 3; -- 3 different interfaces, QSFP, RING_0 and RING_1
- constant c_qsfp_if_offset : natural := 0; -- QSFP signals are indexed at c_nof_if * I.
- constant c_ring_0_if_offset : natural := 1; -- RING_0 signals are indexed at c_nof_if * I + 1.
- constant c_ring_1_if_offset : natural := 2; -- RING_1 signals are indexed at c_nof_if * I + 2.
+ -- 3 different interfaces, QSFP, RING_0 and RING_1
+ constant c_nof_if : natural := 3;
+ -- QSFP signals are indexed at c_nof_if * I.
+ constant c_qsfp_if_offset : natural := 0;
+ -- RING_0 signals are indexed at c_nof_if * I + 1.
+ constant c_ring_0_if_offset : natural := 1;
+ -- RING_1 signals are indexed at c_nof_if * I + 2.
+ constant c_ring_1_if_offset : natural := 2;
constant c_addr_w_reg_ring_lane_info : natural := 1;
constant c_addr_w_reg_bsn_monitor_v2_ring_rx : natural := ceil_log2(c_nof_rx_monitors) + 3;
@@ -153,7 +178,8 @@ architecture str of lofar2_unb2b_ring is
adr_w => ceil_log2(c_nof_lanes),
dat_w => 1,
nof_dat => c_nof_lanes,
- init_sl => '0'); -- default use lane input = 0, 1 = local input.
+ -- default use lane input = 0, 1 = local input.
+ init_sl => '0');
signal gn_index : natural;
signal this_rn : std_logic_vector(c_byte_w - 1 downto 0);
@@ -203,12 +229,16 @@ architecture str of lofar2_unb2b_ring is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_copi : t_mem_copi := c_mem_copi_rst; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_copi : t_mem_copi := c_mem_copi_rst;
signal eth1g_tse_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal eth1g_reg_copi : t_mem_copi := c_mem_copi_rst; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_copi : t_mem_copi := c_mem_copi_rst;
signal eth1g_reg_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_copi : t_mem_copi := c_mem_copi_rst; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_copi : t_mem_copi := c_mem_copi_rst;
signal eth1g_ram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS read
@@ -370,7 +400,8 @@ begin
mm_rst => mm_rst,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ -- Can be external 200MHz, or PLL generated
+ dp_clk => dp_clk,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
@@ -637,7 +668,8 @@ begin
u_mmp_dp_xonoff_lane : entity dp_lib.mms_dp_xonoff
generic map (
g_nof_streams => c_nof_lanes,
- g_default_value => '1' -- default enabled, because standard behaviour is to only pass on packets from lane.
+ -- default enabled, because standard behaviour is to only pass on packets from lane.
+ g_default_value => '1'
)
port map (
mm_rst => mm_rst,
@@ -660,13 +692,15 @@ begin
-- MMP dp_xonoff local_sosi
-----------------------------------------------------------------------------
gen_copy_local: for I in 0 to c_nof_lanes - 1 generate
- dp_xonoff_local_snk_in_arr(I) <= local_sosi; -- copy local sosi to all lanes
+ -- copy local sosi to all lanes
+ dp_xonoff_local_snk_in_arr(I) <= local_sosi;
end generate;
u_mmp_dp_xonoff_local : entity dp_lib.mms_dp_xonoff
generic map (
g_nof_streams => c_nof_lanes,
- g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
+ -- default disabled, because standard behaviour is to only pass on packets from lane.
+ g_default_value => '0'
)
port map (
mm_rst => mm_rst,
@@ -741,7 +775,8 @@ begin
-- Use full c_byte_w range of ID for gn_index and ring_info.O_rn
gn_index <= TO_UINT(ID);
- this_rn <= TO_UVEC(gn_index - TO_UINT(ring_info.O_rn), c_byte_w) when rising_edge(dp_clk); -- Using register to ease timing closure.
+ -- Using register to ease timing closure.
+ this_rn <= TO_UVEC(gn_index - TO_UINT(ring_info.O_rn), c_byte_w) when rising_edge(dp_clk);
-----------------------------------------------------------------------------
-- Ring lane even indices.
@@ -749,7 +784,8 @@ begin
gen_even_lanes: for I in 0 to c_nof_even_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
generic map (
- g_lane_direction => 1, -- transport in positive direction.
+ -- transport in positive direction.
+ g_lane_direction => 1,
g_lane_data_w => c_lane_data_w,
g_lane_packet_length => c_lane_packet_length,
g_use_dp_layer => c_use_dp_layer,
@@ -768,7 +804,8 @@ begin
dp_clk => dp_clk,
dp_rst => dp_rst,
- from_lane_sosi => from_lane_sosi_arr(2 * I), -- even indices
+ -- even indices
+ from_lane_sosi => from_lane_sosi_arr(2 * I),
to_lane_sosi => to_lane_sosi_arr(2 * I),
lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I),
lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I),
@@ -800,7 +837,8 @@ begin
gen_odd_lanes : for I in 0 to c_nof_odd_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
generic map (
- g_lane_direction => 0, -- transport in negative direction.
+ -- transport in negative direction.
+ g_lane_direction => 0,
g_lane_data_w => c_lane_data_w,
g_lane_packet_length => c_lane_packet_length,
g_use_dp_layer => c_use_dp_layer,
@@ -819,7 +857,8 @@ begin
dp_clk => dp_clk,
dp_rst => dp_rst,
- from_lane_sosi => from_lane_sosi_arr(2 * I + 1), -- odd indices
+ -- odd indices
+ from_lane_sosi => from_lane_sosi_arr(2 * I + 1),
to_lane_sosi => to_lane_sosi_arr(2 * I + 1),
lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I),
lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I),
@@ -840,7 +879,8 @@ begin
this_rn => this_rn,
N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
+ -- reverse tx/rx select for odd indices.
+ rx_select => ring_info.use_cable_to_next_rn,
tx_select => ring_info.use_cable_to_previous_rn
);
end generate;
@@ -850,11 +890,15 @@ begin
-----------------------------------------------------------------------------
gen_combine: for I in 0 to c_nof_even_lanes - 1 generate
-- QSFP_RX
- lane_rx_cable_even_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_qsfp_if_offset) when ring_info.use_cable_to_previous_rn = '1' else c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> even lanes receive from cable
- lane_rx_cable_odd_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_qsfp_if_offset) when ring_info.use_cable_to_next_rn = '1' else c_dp_sosi_rst; -- use_cable_to_next_rn=1 -> odd lanes receive from cable
+ -- use_cable_to_previous_rn=1 -> even lanes receive from cable
+ lane_rx_cable_even_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_qsfp_if_offset) when ring_info.use_cable_to_previous_rn = '1' else c_dp_sosi_rst;
+ -- use_cable_to_next_rn=1 -> odd lanes receive from cable
+ lane_rx_cable_odd_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_qsfp_if_offset) when ring_info.use_cable_to_next_rn = '1' else c_dp_sosi_rst;
-- QSFP_TX
- tr_10gbe_snk_in_arr(c_nof_if * I + c_qsfp_if_offset) <= lane_tx_cable_even_sosi_arr(I) when ring_info.use_cable_to_next_rn = '1' else -- use_cable_to_next_rn=1 -> even lanes transmit to cable
- lane_tx_cable_odd_sosi_arr(I) when ring_info.use_cable_to_previous_rn = '1' else c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> odd lanes transmit to cable
+ -- use_cable_to_next_rn=1 -> even lanes transmit to cable
+ tr_10gbe_snk_in_arr(c_nof_if * I + c_qsfp_if_offset) <= lane_tx_cable_even_sosi_arr(I) when ring_info.use_cable_to_next_rn = '1' else
+ -- use_cable_to_previous_rn=1 -> odd lanes transmit to cable
+ lane_tx_cable_odd_sosi_arr(I) when ring_info.use_cable_to_previous_rn = '1' else c_dp_sosi_rst;
-- RING_0_RX even lanes receive from RING_0 (from the left)
lane_rx_board_even_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_ring_0_if_offset);
@@ -987,7 +1031,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
index 1ae1c752c22c1e09deeff3e8e390387ec3b170b3..d8cceaa5dc10958c06f5e1c2611844911db54fe5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
@@ -32,7 +32,8 @@ use lofar2_sdp_lib.sdp_pkg.all;
entity mmc_lofar2_unb2b_ring is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
index 44c943c0a76371ac71bff7354db5faa72e782bba..c21592dde021e3b6a4163abbb601f15ca9289356 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
@@ -28,217 +28,428 @@ package qsys_lofar2_unb2b_ring_pkg is
component qsys_lofar2_unb2b_ring is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export
- ram_diag_bg_clk_export : out std_logic; -- export
- ram_diag_bg_read_export : out std_logic; -- export
- ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_reset_export : out std_logic; -- export
- ram_diag_bg_write_export : out std_logic; -- export
- ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_clk_export : out std_logic; -- export
- reg_diag_bg_read_export : out std_logic; -- export
- reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_reset_export : out std_logic; -- export
- reg_diag_bg_write_export : out std_logic; -- export
- reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export
- reg_dp_block_validate_err_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_read_export : out std_logic; -- export
- reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_write_export : out std_logic; -- export
- reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_lane_clk_export : out std_logic; -- export
- reg_dp_xonoff_lane_read_export : out std_logic; -- export
- reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_lane_reset_export : out std_logic; -- export
- reg_dp_xonoff_lane_write_export : out std_logic; -- export
- reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_local_clk_export : out std_logic; -- export
- reg_dp_xonoff_local_read_export : out std_logic; -- export
- reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_local_reset_export : out std_logic; -- export
- reg_dp_xonoff_local_write_export : out std_logic; -- export
- reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_ring_lane_info_clk_export : out std_logic; -- export
- reg_ring_lane_info_read_export : out std_logic; -- export
- reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_reset_export : out std_logic; -- export
- reg_ring_lane_info_write_export : out std_logic; -- export
- reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ ram_diag_bg_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ ram_diag_bg_clk_export : out std_logic;
+ -- export
+ ram_diag_bg_read_export : out std_logic;
+ -- export
+ ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_bg_reset_export : out std_logic;
+ -- export
+ ram_diag_bg_write_export : out std_logic;
+ -- export
+ ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0);
+ -- export
+ ram_scrap_clk_export : out std_logic;
+ -- export
+ ram_scrap_read_export : out std_logic;
+ -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_scrap_reset_export : out std_logic;
+ -- export
+ ram_scrap_write_export : out std_logic;
+ -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_bg_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_bg_clk_export : out std_logic;
+ -- export
+ reg_diag_bg_read_export : out std_logic;
+ -- export
+ reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_bg_reset_export : out std_logic;
+ -- export
+ reg_diag_bg_write_export : out std_logic;
+ -- export
+ reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_read_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_write_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_dp_block_validate_err_clk_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_read_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_block_validate_err_reset_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_write_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_dp_xonoff_lane_clk_export : out std_logic;
+ -- export
+ reg_dp_xonoff_lane_read_export : out std_logic;
+ -- export
+ reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_xonoff_lane_reset_export : out std_logic;
+ -- export
+ reg_dp_xonoff_lane_write_export : out std_logic;
+ -- export
+ reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_dp_xonoff_local_clk_export : out std_logic;
+ -- export
+ reg_dp_xonoff_local_read_export : out std_logic;
+ -- export
+ reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_xonoff_local_reset_export : out std_logic;
+ -- export
+ reg_dp_xonoff_local_write_export : out std_logic;
+ -- export
+ reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_ring_info_clk_export : out std_logic;
+ -- export
+ reg_ring_info_read_export : out std_logic;
+ -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_ring_info_reset_export : out std_logic;
+ -- export
+ reg_ring_info_write_export : out std_logic;
+ -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_ring_lane_info_clk_export : out std_logic;
+ -- export
+ reg_ring_lane_info_read_export : out std_logic;
+ -- export
+ reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_ring_lane_info_reset_export : out std_logic;
+ -- export
+ reg_ring_lane_info_write_export : out std_logic;
+ -- export
+ reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_read_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_write_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic;
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0)
);
end component qsys_lofar2_unb2b_ring;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
index a41b295e624654a5b30cfca9e41c1f014839f0b1..74b0fa2583d779ad78b4217014478580b8d025ab 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
@@ -60,7 +60,8 @@ entity tb_lofar2_unb2b_ring is
g_access_scheme : integer range 1 to 3 := 1
);
port (
- tb_end : out std_logic := '0' -- For multi tb
+ -- For multi tb
+ tb_end : out std_logic := '0'
);
end tb_lofar2_unb2b_ring;
@@ -70,13 +71,16 @@ architecture tb of tb_lofar2_unb2b_ring is
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
+ -- 644MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
constant c_pps_period : natural := 1000;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_cable_delay : time := 12 ns;
constant c_revision_select : t_lofar2_unb2b_ring_config := func_sel_revision_rec(g_design_name);
@@ -85,7 +89,8 @@ architecture tb of tb_lofar2_unb2b_ring is
constant c_block_period : natural := 1024;
constant c_blocksize : natural := c_sdp_V_ring_pkt_len_max - c_ring_dp_hdr_field_size;
constant c_gapsize : natural := c_block_period - c_blocksize;
- constant c_sync_timeout : natural := c_block_period * g_nof_block_per_sync + 10; -- +10 for extra slack
+ -- +10 for extra slack
+ constant c_sync_timeout : natural := c_block_period * g_nof_block_per_sync + 10;
constant c_exp_bsn_at_sync : natural := g_nof_block_per_sync;
constant c_exp_nof_sop : natural := g_nof_block_per_sync;
constant c_exp_nof_valid : natural := g_nof_block_per_sync * c_blocksize;
@@ -137,21 +142,31 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- tb_clk <= not tb_clk or i_tb_end after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk or i_tb_end after c_tb_clk_period / 2;
- ext_clk <= not ext_clk or i_tb_end after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk or i_tb_end after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- SA_CLK <= not SA_CLK or i_tb_end after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk or i_tb_end after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk or i_tb_end after c_eth_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ SA_CLK <= not SA_CLK or i_tb_end after c_sa_clk_period / 2;
pps_rst <= '0' after c_ext_clk_period * 2;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -238,17 +253,23 @@ begin
-- Write ring configuration to all nodes.
for RN in 0 to g_nof_rn - 1 loop
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_INFO", 2, g_nof_rn, tb_clk); -- N_rn
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_INFO", 3, 0, tb_clk); -- O_rn
+ -- N_rn
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_INFO", 2, g_nof_rn, tb_clk);
+ -- O_rn
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_INFO", 3, 0, tb_clk);
end loop;
-- Start node specific settings
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_INFO", 0, 1, tb_clk); -- use_ring_to_previous_rn = 1
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_INFO", 1, 0, tb_clk); -- use_ring_to_next_rn = 0
+ -- use_ring_to_previous_rn = 1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_INFO", 0, 1, tb_clk);
+ -- use_ring_to_next_rn = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_INFO", 1, 0, tb_clk);
-- End node specific settings
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_RING_INFO", 0, 0, tb_clk); -- use_ring_to_previous_rn = 0
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_RING_INFO", 1, 1, tb_clk); -- use_ring_to_next_rn = 1
+ -- use_ring_to_previous_rn = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_RING_INFO", 0, 0, tb_clk);
+ -- use_ring_to_next_rn = 1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_RING_INFO", 1, 1, tb_clk);
----------------------------------------------------------------------------
-- Access scheme 1. A source RN creates the packets and sends them along the ring.
@@ -256,8 +277,10 @@ begin
if g_access_scheme = 1 then
for I in 0 to c_nof_lanes - 1 loop
-- Select local input (= 1) on start node on all lanes.
- mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_lane, I * 2, 0, tb_clk); -- Disable input from lane
- mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_local, I * 2, 1, tb_clk); -- Enable local input
+ -- Disable input from lane
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_lane, I * 2, 0, tb_clk);
+ -- Enable local input
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_local, I * 2, 1, tb_clk);
-- Set transport_nof_hops to N_rn on start node for a full transfer around the ring.
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_LANE_INFO", I * 2 + 1, g_nof_rn, tb_clk);
@@ -270,8 +293,10 @@ begin
for RN in 0 to g_nof_rn - 1 loop
for I in 0 to c_nof_lanes - 1 loop
-- Select both local and remote input on all nodes on all lanes.
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DP_XONOFF_LANE", I * 2, 1, tb_clk); -- Enable input from lane
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DP_XONOFF_LOCAL", I * 2, 1, tb_clk); -- Enable local input
+ -- Enable input from lane
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DP_XONOFF_LANE", I * 2, 1, tb_clk);
+ -- Enable local input
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DP_XONOFF_LOCAL", I * 2, 1, tb_clk);
-- Set transport_nof_hops to N_rn-1 on all nodes.
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_LANE_INFO", I * 2 + 1, g_nof_rn - 1, tb_clk);
@@ -282,37 +307,52 @@ begin
-- Enable BG on all nodes (for bs_sosi)
----------------------------------------------------------------------------
for RN in 0 to g_nof_rn - 1 loop
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 1, c_blocksize, tb_clk); -- samples per packet
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 2, g_nof_block_per_sync, tb_clk); -- blocks per sync
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 3, c_gapsize, tb_clk); -- gapsize
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 0, 3, tb_clk); -- enable at sync
+ -- samples per packet
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 1, c_blocksize, tb_clk);
+ -- blocks per sync
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 2, g_nof_block_per_sync, tb_clk);
+ -- gapsize
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 3, c_gapsize, tb_clk);
+ -- enable at sync
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 0, 3, tb_clk);
end loop;
----------------------------------------------------------------------------
-- Verify Access scheme 1 by reading rx / tx monitors on source RN
----------------------------------------------------------------------------
if g_access_scheme = 1 then
-- Wait for bsn monitor to have received a sync period.
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_monitor_v2_ring_rx, 4, -- read nof valid
- "SIGNED", rd_data, ">", 0, -- this is the wait until condition
- 1 us, tb_clk); -- read every 1 us
+ -- read nof valid
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_monitor_v2_ring_rx, 4,
+ -- this is the wait until condition
+ "SIGNED", rd_data, ">", 0,
+ -- read every 1 us
+ 1 us, tb_clk);
for I in 0 to c_nof_lanes - 1 loop
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 1, rd_data, tb_clk); -- bsn at sync
+ -- bsn at sync
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 1, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 3, rd_data, tb_clk); -- nof_sop
+ -- nof_sop
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 3, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 4, rd_data, tb_clk); -- nof_valid
+ -- nof_valid
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 4, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 5, rd_data, tb_clk); -- nof_err
+ -- nof_err
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 5, rd_data, tb_clk);
assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 1, rd_data, tb_clk); -- bsn at sync
+ -- bsn at sync
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 1, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 3, rd_data, tb_clk); -- nof_sop
+ -- nof_sop
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 3, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 4, rd_data, tb_clk); -- nof_valid
+ -- nof_valid
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 4, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 5, rd_data, tb_clk); -- nof_err
+ -- nof_err
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 5, rd_data, tb_clk);
assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
end loop;
@@ -321,42 +361,60 @@ begin
----------------------------------------------------------------------------
else
-- Wait for bsn monitor to have received a sync period.
- mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
- "SIGNED", rd_data, ">", 0, -- this is the wait until condition
- 1 us, tb_clk); -- read every 1 us
+ -- read nof valid
+ mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", 4,
+ -- this is the wait until condition
+ "SIGNED", rd_data, ">", 0,
+ -- read every 1 us
+ 1 us, tb_clk);
for RN in 0 to g_nof_rn - 1 loop
- for I in 0 to c_nof_lanes - 1 loop -- lane index
- for J in 0 to g_nof_rn - 1 loop -- bsn_monitor index
+ -- lane index
+ for I in 0 to c_nof_lanes - 1 loop
+ -- bsn_monitor index
+ for J in 0 to g_nof_rn - 1 loop
-- No packets transmitted from next RN (this_rn + 1 for even lanes, this_rn - 1 for odd lanes) as this RN should have removed it from the ring.
if (I mod 2 = 0 and (RN + 1) mod g_nof_rn = J) or (I mod 2 = 1 and (RN + g_nof_rn - 1) mod g_nof_rn = J) then
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
+ -- status bits
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk);
assert rd_data(2) = '1' report "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
else
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
+ -- status bits
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk);
assert rd_data(2) = '0' report "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 1, rd_data, tb_clk); -- bsn at sync
+ -- bsn at sync
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 1, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 3, rd_data, tb_clk); -- nof_sop
+ -- nof_sop
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 3, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 4, rd_data, tb_clk); -- nof_valid
+ -- nof_valid
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 4, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 5, rd_data, tb_clk); -- nof_err
+ -- nof_err
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 5, rd_data, tb_clk);
assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
end if;
- if RN = J then -- No packets received from itself as the previous RN should have removed it from the ring.
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
+ -- No packets received from itself as the previous RN should have removed it from the ring.
+ if RN = J then
+ -- status bits
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk);
assert rd_data(2) = '1' report "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
else
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
+ -- status bits
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk);
assert rd_data(2) = '0' report "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 1, rd_data, tb_clk); -- bsn at sync
+ -- bsn at sync
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 1, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 3, rd_data, tb_clk); -- nof_sop
+ -- nof_sop
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 3, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 4, rd_data, tb_clk); -- nof_valid
+ -- nof_valid
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 4, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 5, rd_data, tb_clk); -- nof_err
+ -- nof_err
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 5, rd_data, tb_clk);
assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
end if;
end loop;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
index d3b80ca5d9bb1acacc0877d95d9ae7ab801c8751..3d0da3f7d8c0a6db74881b7e06407267fc55ba4e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
@@ -40,7 +40,8 @@ architecture tb of tb_tb_lofar2_unb2b_ring is
constant c_nof_rn : natural := 3;
constant c_nof_tb : natural := 5;
signal tb_end_vec : std_logic_vector(c_nof_tb - 1 downto 0) := (others => '0');
- signal tb_end : std_logic; -- declare tb_end as STD_LOGIC to avoid 'No objects found' error on 'when -label tb_end' in *.do file
+ -- declare tb_end as STD_LOGIC to avoid 'No objects found' error on 'when -label tb_end' in *.do file
+ signal tb_end : std_logic;
begin
-- g_multi_tb : BOOLEAN := FALSE;
-- g_unb_nr : NATURAL := 4;
@@ -50,10 +51,14 @@ begin
-- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
-- using different g_unb_nr to avoid MM file clashing.
- u_one_1 : entity work.tb_lofar2_unb2b_ring generic map(true, 0, "lofar2_unb2b_ring_one", c_nof_rn, 3, 1) port map(tb_end_vec(0)); -- access scheme 1.
- u_one_2_3 : entity work.tb_lofar2_unb2b_ring generic map(true, 1, "lofar2_unb2b_ring_one", c_nof_rn, 3, 2) port map(tb_end_vec(1)); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
- u_full_1 : entity work.tb_lofar2_unb2b_ring generic map(true, 2, "lofar2_unb2b_ring_full", c_nof_rn, 3, 1) port map(tb_end_vec(2)); -- access scheme 1.
- u_full_2_3 : entity work.tb_lofar2_unb2b_ring generic map(true, 3, "lofar2_unb2b_ring_full", c_nof_rn, 32, 2) port map(tb_end_vec(3)); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
+ -- access scheme 1.
+ u_one_1 : entity work.tb_lofar2_unb2b_ring generic map(true, 0, "lofar2_unb2b_ring_one", c_nof_rn, 3, 1) port map(tb_end_vec(0));
+ -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
+ u_one_2_3 : entity work.tb_lofar2_unb2b_ring generic map(true, 1, "lofar2_unb2b_ring_one", c_nof_rn, 3, 2) port map(tb_end_vec(1));
+ -- access scheme 1.
+ u_full_1 : entity work.tb_lofar2_unb2b_ring generic map(true, 2, "lofar2_unb2b_ring_full", c_nof_rn, 3, 1) port map(tb_end_vec(2));
+ -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
+ u_full_2_3 : entity work.tb_lofar2_unb2b_ring generic map(true, 3, "lofar2_unb2b_ring_full", c_nof_rn, 32, 2) port map(tb_end_vec(3));
-- u_16_rn -> Using 16 ring nodes. Using the _one revision as it only uses 1 lane to limit MM readout time. Also using
-- g_nof_block_per_sync = 32 as all bsn monitors have to be read during one sync period which takes more time with 16 nodes.
u_16_rn : entity work.tb_lofar2_unb2b_ring generic map(true, 4, "lofar2_unb2b_ring_one", 16, 32, 2) port map(tb_end_vec(4));
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
index bd619d79329a78c77405e68e916edc70d06c6e90..52b5d35d9eb84109e2d7edaa15a02e8b28756886 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
@@ -38,20 +38,29 @@ entity disturb2_unb2b_sdp_station_full is
generic (
g_design_name : string := "disturb2_unb2b_sdp_station_full";
g_design_note : string := "Disturb2 SDP station full design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -72,7 +81,8 @@ entity disturb2_unb2b_sdp_station_full is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP0 for Ring.
QSFP_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -85,18 +95,22 @@ entity disturb2_unb2b_sdp_station_full is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (note only 6 are used in unb2b)
- BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0)
);
end disturb2_unb2b_sdp_station_full;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
index f8d63040562e1ce27dddf1de39a6e3e71ca931cb..23b9a51a221f05d2dee29c8fab3c01f54c883831 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
@@ -40,22 +40,31 @@ entity disturb2_unb2b_sdp_station_full_wg is
generic (
g_design_name : string := "disturb2_unb2b_sdp_station_full_wg";
g_design_note : string := "Disturb2 SDP station full design WG";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := "";
g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
g_wpfb_complex : t_wpfb := c_sdp_wpfb_complex_subbands
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -76,7 +85,8 @@ entity disturb2_unb2b_sdp_station_full_wg is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP0 for Ring.
QSFP_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -90,7 +100,8 @@ entity disturb2_unb2b_sdp_station_full_wg is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0)
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
index 4a1080e7605e740d0ba02b7b772795396a5a6d44..95286269c344563dcd9d9d3eab698d2a8b206db4 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
@@ -83,19 +83,23 @@ end tb_disturb2_unb2b_sdp_station_full_wg;
architecture tb of tb_disturb2_unb2b_sdp_station_full_wg is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
+ -- 644MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
constant c_pps_period : natural := 1000;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_cable_delay : time := 12 ns;
constant c_nof_block_per_sync : natural := 16;
@@ -104,35 +108,50 @@ architecture tb of tb_disturb2_unb2b_sdp_station_full_wg is
constant c_wpfb_complex_sim : t_wpfb := func_wpfb_map_real_input_wpfb_parameters_to_complex_input(c_wpfb_sim);
-- WG
- constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := 2;
-- . ampl
constant c_beamlet_scale : real := 1.0 / 2.0**9;
- constant c_wg_ampl_sp_0 : natural := natural(7.0 / c_beamlet_scale); -- choose < 8.0 to have no beamlet output overflow with unit weights and unit beamlet scale
- constant c_wg_ampl_sp_2 : natural := c_wg_ampl_sp_0 / 3; -- use different ampl for sp_0 and sp_2 to distinghuis them
+ -- choose < 8.0 to have no beamlet output overflow with unit weights and unit beamlet scale
+ constant c_wg_ampl_sp_0 : natural := natural(7.0 / c_beamlet_scale);
+ -- use different ampl for sp_0 and sp_2 to distinghuis them
+ constant c_wg_ampl_sp_2 : natural := c_wg_ampl_sp_0 / 3;
-- . phase
- constant c_subband_phase : real := 0.0; -- wanted subband phase in degrees = WG phase at sop
- constant c_wg_latency : integer := c_diag_wg_latency - 0; -- -0 to account for BSN scheduler start trigger latency
- constant c_subband_sp_0 : real := 102.0; -- use WG at sp-0 for subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- constant c_subband_sp_2 : real := 99.5; -- use WG at sp-2 for subband at index 99.5 = 99.5/1024 * 200MHz = 19.43359375 MHz
- constant c_subband_freq_sp_0 : real := real(c_subband_sp_0) / real(c_sdp_N_fft); -- normalized by fs = f_adc = 200 MHz = dp_clk rate
- constant c_subband_freq_sp_2 : real := real(c_subband_sp_2) / real(c_sdp_N_fft); -- normalized by fs = f_adc = 200 MHz = dp_clk rate
- constant c_wg_phase_offset_sp_0 : real := 360.0 * real(c_wg_latency) * c_subband_freq_sp_0; -- c_diag_wg_latency is in dp_clk cycles
- constant c_wg_phase_offset_sp_2 : real := 360.0 * real(c_wg_latency) * c_subband_freq_sp_2; -- c_diag_wg_latency is in dp_clk cycles
- constant c_wg_phase_sp_0 : real := c_subband_phase + c_wg_phase_offset_sp_0; -- WG phase in degrees
- constant c_wg_phase_sp_2 : real := c_subband_phase + c_wg_phase_offset_sp_2; -- WG phase in degrees
+ -- wanted subband phase in degrees = WG phase at sop
+ constant c_subband_phase : real := 0.0;
+ -- -0 to account for BSN scheduler start trigger latency
+ constant c_wg_latency : integer := c_diag_wg_latency - 0;
+ -- use WG at sp-0 for subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ constant c_subband_sp_0 : real := 102.0;
+ -- use WG at sp-2 for subband at index 99.5 = 99.5/1024 * 200MHz = 19.43359375 MHz
+ constant c_subband_sp_2 : real := 99.5;
+ -- normalized by fs = f_adc = 200 MHz = dp_clk rate
+ constant c_subband_freq_sp_0 : real := real(c_subband_sp_0) / real(c_sdp_N_fft);
+ -- normalized by fs = f_adc = 200 MHz = dp_clk rate
+ constant c_subband_freq_sp_2 : real := real(c_subband_sp_2) / real(c_sdp_N_fft);
+ -- c_diag_wg_latency is in dp_clk cycles
+ constant c_wg_phase_offset_sp_0 : real := 360.0 * real(c_wg_latency) * c_subband_freq_sp_0;
+ -- c_diag_wg_latency is in dp_clk cycles
+ constant c_wg_phase_offset_sp_2 : real := 360.0 * real(c_wg_latency) * c_subband_freq_sp_2;
+ -- WG phase in degrees
+ constant c_wg_phase_sp_0 : real := c_subband_phase + c_wg_phase_offset_sp_0;
+ -- WG phase in degrees
+ constant c_wg_phase_sp_2 : real := c_subband_phase + c_wg_phase_offset_sp_2;
-- WPFB, use default unit subband weights (= 1.0 + 0j)
constant c_exp_subband_ampl_sp_0 : real := real(c_wg_ampl_sp_0) * c_sdp_wpfb_subband_sp_ampl_ratio;
constant c_exp_subband_ampl_sp_2 : real := real(c_wg_ampl_sp_2) * c_sdp_wpfb_subband_sp_ampl_ratio;
- constant c_subband_phase_offset : real := -90.0; -- WG with zero phase sinus yields subband with -90 degrees phase (negative Im, zero Re)
+ -- WG with zero phase sinus yields subband with -90 degrees phase (negative Im, zero Re)
+ constant c_subband_phase_offset : real := -90.0;
constant c_exp_subband_phase : real := c_subband_phase + c_subband_phase_offset;
-- BF
-- . use one active WG per subband, so beamlet_sum of one subband
-- . use default unit BF weights (= 1.0 + 0j), so beamlet_sum = subband
-- . use beamlet output = beamlet_sum * c_beamlet_scale
- constant c_exp_beamlet_scale : natural := natural(c_beamlet_scale * real(c_sdp_unit_beamlet_scale)); -- c_sdp_unit_beamlet_scale = 2**15;
+ -- c_sdp_unit_beamlet_scale = 2**15;
+ constant c_exp_beamlet_scale : natural := natural(c_beamlet_scale * real(c_sdp_unit_beamlet_scale));
constant c_exp_beamlet_ampl_sp_0 : real := c_exp_subband_ampl_sp_0 * c_beamlet_scale;
constant c_exp_beamlet_ampl_sp_2 : real := c_exp_subband_ampl_sp_2 * c_beamlet_scale;
constant c_exp_beamlet_phase : real := c_exp_subband_phase;
@@ -224,18 +243,27 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- SA_CLK <= not SA_CLK after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ SA_CLK <= not SA_CLK after c_sa_clk_period / 2;
pps_rst <= '0' after c_ext_clk_period * 2;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -312,9 +340,12 @@ begin
port map (
-- Transceiver PLL reference clock
tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => tr_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => tr_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156,
-- MM interface
mm_rst => pps_rst,
@@ -332,7 +363,8 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
@@ -369,9 +401,12 @@ begin
-- Enable BS
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 1, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 1, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk);
----------------------------------------------------------------------------
-- Enable WG
@@ -383,16 +418,24 @@ begin
-- 3 : ampl[16:0]
-- WG at signal input 0
v_offset := 0 * c_mm_span_reg_diag_wg;
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase_sp_0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(c_subband_sp_0 * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase_sp_0 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(c_subband_sp_0 * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk);
-- WG at signal input 2
v_offset := 2 * c_mm_span_reg_diag_wg;
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase_sp_2 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(c_subband_sp_2 * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl_sp_2) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase_sp_2 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(c_subband_sp_2 * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl_sp_2) * c_sdp_wg_ampl_lsb), tb_clk);
-- Read current BSN
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 downto 0), tb_clk);
@@ -403,12 +446,16 @@ begin
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
v_bsn := c_bsn_start_wg;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
-- Wait for enough WG data and start of sync interval
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2,
c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
@@ -420,10 +467,12 @@ begin
for packet in 0 to 2 loop
-- Get beamlet_index from packet header
proc_common_wait_until_clk_and_high(ext_clk, tr_10GbE_src_out.sop);
- for I in 0 to 8 loop -- Packet header is 9.25 words wide, which can be discarded
+ -- Packet header is 9.25 words wide, which can be discarded
+ for I in 0 to 8 loop
if I = 7 then
rx_beamlet_scale <= tr_10GbE_src_out.data(55 downto 40);
- v_beamlet_index_offset := c_sdp_N_pol_bf * TO_UINT(tr_10GbE_src_out.data(39 downto 24)); -- Read beamlet index
+ -- Read beamlet index
+ v_beamlet_index_offset := c_sdp_N_pol_bf * TO_UINT(tr_10GbE_src_out.data(39 downto 24));
rx_beamlet_index_offset <= v_beamlet_index_offset;
rx_blocks_per_packet <= tr_10GbE_src_out.data(23 downto 16);
rx_beamlets_per_block <= tr_10GbE_src_out.data(15 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
index 061841c5e476d3f97ddef6398e4caa6978ab842a..dde334211b0f5f57c002d038ecca1025e196e39d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2b_sdp_station_adc is
generic (
g_design_name : string := "lofar2_unb2b_sdp_station_adc";
g_design_note : string := "Lofar2 SDP station adc design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -75,12 +84,15 @@ entity lofar2_unb2b_sdp_station_adc is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- back transceivers (note only 6 are used in unb2b)
- BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0)
);
end lofar2_unb2b_sdp_station_adc;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
index eefec65249bc24e73d6ebd6d769fe7c3963852f0..91a03b168ad387f392d3cce14cbd24ce01d055eb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
@@ -63,36 +63,49 @@ end tb_lofar2_unb2b_sdp_station_adc;
architecture tb of tb_lofar2_unb2b_sdp_station_adc is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_init_bsn : natural := 17; -- some recognizable value >= 0
+ -- some recognizable value >= 0
+ constant c_init_bsn : natural := 17;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
- constant c_nof_block_per_sync : natural := 7; -- use short interval to speed up simulation
+ -- use short interval to speed up simulation
+ constant c_nof_block_per_sync : natural := 7;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_pps_period : natural := c_nof_clk_per_sync;
- constant c_percentage : real := 0.05; -- percentage that actual value may differ from expected value, due to WG rounding
- constant c_lo_factor : real := 1.0 - c_percentage; -- lower boundary
- constant c_hi_factor : real := 1.0 + c_percentage; -- higher boundary
+ -- percentage that actual value may differ from expected value, due to WG rounding
+ constant c_percentage : real := 0.05;
+ -- lower boundary
+ constant c_lo_factor : real := 1.0 - c_percentage;
+ -- higher boundary
+ constant c_hi_factor : real := 1.0 + c_percentage;
-- WG
- constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2; -- = 0.5 * FS, so in number of lsb
- constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
- constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := c_init_bsn + 2;
+ -- = 0.5 * FS, so in number of lsb
+ constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2;
+ -- in freq_unit
+ constant c_wg_freq_offset : real := 0.0 / 11.0;
+ -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ constant c_subband_sp_0 : real := 102.0;
constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_nof_clk_per_sync);
-- ADUH
- constant c_mon_buffer_nof_samples : natural := 512; -- samples per stream
+ -- samples per stream
+ constant c_mon_buffer_nof_samples : natural := 512;
-- MM
constant c_mm_file_reg_ppsh : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
@@ -145,17 +158,26 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -218,13 +240,15 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
variable v_sp_power_sum_0 : real;
variable v_sp_subband_power : real;
- variable v_W, v_T, v_U, v_S, v_B : natural; -- array indicies
+ -- array indicies
+ variable v_W, v_T, v_U, v_S, v_B : natural;
begin
-- Wait for DUT power up after reset
wait for 1 us;
@@ -232,10 +256,14 @@ begin
----------------------------------------------------------------------------
-- Enable BS
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk); -- Init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk); -- Write high part activates the init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk);
+ -- Write high part activates the init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk);
-- Release PPS pulser, to get first PPS now and to start BSN source
wait for 1 us;
@@ -249,10 +277,14 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk);
-- Read current BSN
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 downto 0), tb_clk);
@@ -263,22 +295,28 @@ begin
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
v_bsn := c_bsn_start_wg;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
----------------------------------------------------------------------------
-- Wait for enough WG data and start of sync interval
----------------------------------------------------------------------------
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 2, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 2,
c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
-- Read ADUH monitor power sum
---------------------------------------------------------------------------
- mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk); -- read low part
+ -- read low part
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk);
sp_power_sum(31 downto 0) <= rd_data;
- mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk); -- read high part
+ -- read high part
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk);
sp_power_sum(63 downto 32) <= rd_data;
proc_common_wait_some_cycles(tb_clk, 1);
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
index 852d977aeeeecea267480821e3338a2d5fcf37ce..feaeba501aecb2b4954eb58033e02f8048b308bf 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2b_sdp_station_bf is
generic (
g_design_name : string := "lofar2_unb2b_sdp_station_bf";
g_design_note : string := "Lofar2 SDP station beamformer design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -72,7 +81,8 @@ entity lofar2_unb2b_sdp_station_bf is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers
QSFP_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -82,12 +92,15 @@ entity lofar2_unb2b_sdp_station_bf is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- back transceivers (note only 6 are used in unb2b)
- BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0)
);
end lofar2_unb2b_sdp_station_bf;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
index b941058df291306216f661588e8990cc4970ff50..d4b2d414450917e2d87d8bb891341f83a9ef6d85 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
@@ -86,103 +86,154 @@ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2b_sdp_station_bf is
generic (
- g_sp : natural := 0; -- WG signal path index in range(S_pn = 12)
- g_wg_ampl : real := 1.0; -- WG normalized amplitude
- g_subband : natural := 102; -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- g_beamlet : natural := 10; -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
- g_beamlet_scale : real := 1.0 / 2.0**10; -- g_beamlet output scale factor
- g_bf_gain : real := 1.0; -- g_beamlet BF weight normalized gain
- g_bf_phase : real := 30.0; -- g_beamlet BF weight phase rotation in degrees
- g_read_all_SST : boolean := false; -- when FALSE only read SST for g_subband, to save sim time
- g_read_all_BST : boolean := false -- when FALSE only read BST for g_beamlet, to save sim time
+ -- WG signal path index in range(S_pn = 12)
+ g_sp : natural := 0;
+ -- WG normalized amplitude
+ g_wg_ampl : real := 1.0;
+ -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_subband : natural := 102;
+ -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
+ g_beamlet : natural := 10;
+ -- g_beamlet output scale factor
+ g_beamlet_scale : real := 1.0 / 2.0**10;
+ -- g_beamlet BF weight normalized gain
+ g_bf_gain : real := 1.0;
+ -- g_beamlet BF weight phase rotation in degrees
+ g_bf_phase : real := 30.0;
+ -- when FALSE only read SST for g_subband, to save sim time
+ g_read_all_SST : boolean := false;
+ -- when FALSE only read BST for g_beamlet, to save sim time
+ g_read_all_BST : boolean := false
);
end tb_lofar2_unb2b_sdp_station_bf;
architecture tb of tb_lofar2_unb2b_sdp_station_bf is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
- constant c_gn_index : natural := c_unb_nr * 4 + c_node_nr; -- this node GN
- constant c_init_bsn : natural := 17; -- some recognizable value >= 0
+ -- this node GN
+ constant c_gn_index : natural := c_unb_nr * 4 + c_node_nr;
+ -- some recognizable value >= 0
+ constant c_init_bsn : natural := 17;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_gn_index, 8);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
constant c_mac_15_0 : std_logic_vector(15 downto 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr, 8);
- constant c_ip_15_0 : std_logic_vector(15 downto 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr + 1, 8); -- +1 to avoid IP = *.*.*.0
+ -- +1 to avoid IP = *.*.*.0
+ constant c_ip_15_0 : std_logic_vector(15 downto 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr + 1, 8);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
- constant c_mm_clk_period : time := 10 ns; -- 100 MHz internal mm_clk
+ -- 100 MHz internal mm_clk
+ constant c_mm_clk_period : time := 10 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
+ -- 644MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_nof_block_per_sync : natural := 16;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_pps_period : natural := c_nof_clk_per_sync;
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
- constant c_stat_data_sz : natural := c_wpfb_sim.stat_data_sz; -- = 2
+ -- = 2
+ constant c_stat_data_sz : natural := c_wpfb_sim.stat_data_sz;
- constant c_stat_percentage : real := 0.05; -- +-percentage margin that actual value may differ from expected value
- constant c_stat_lo_factor : real := 1.0 - c_stat_percentage; -- lower boundary
- constant c_stat_hi_factor : real := 1.0 + c_stat_percentage; -- higher boundary
+ -- +-percentage margin that actual value may differ from expected value
+ constant c_stat_percentage : real := 0.05;
+ -- lower boundary
+ constant c_stat_lo_factor : real := 1.0 - c_stat_percentage;
+ -- higher boundary
+ constant c_stat_hi_factor : real := 1.0 + c_stat_percentage;
- constant c_beamlet_output_delta : integer := 2; -- +-delta margin
+ -- +-delta margin
+ constant c_beamlet_output_delta : integer := 2;
-- header fields
- constant c_cep_eth_src_mac : std_logic_vector(47 downto 0) := c_sdp_cep_eth_src_mac_47_16 & c_mac_15_0; -- x"00228608"; -- 47:16, 15:8 = backplane, 7:0 = node
- constant c_cep_ip_src_addr : std_logic_vector(31 downto 0) := c_sdp_cep_ip_src_addr_31_16 & c_ip_15_0; -- C0A80001 = '192.168.0.1' = DOP36-eth0
- constant c_cep_udp_src_port : std_logic_vector(15 downto 0) := c_sdp_cep_udp_src_port_15_8 & c_id; -- D0 & c_id
+ -- x"00228608"; -- 47:16, 15:8 = backplane, 7:0 = node
+ constant c_cep_eth_src_mac : std_logic_vector(47 downto 0) := c_sdp_cep_eth_src_mac_47_16 & c_mac_15_0;
+ -- C0A80001 = '192.168.0.1' = DOP36-eth0
+ constant c_cep_ip_src_addr : std_logic_vector(31 downto 0) := c_sdp_cep_ip_src_addr_31_16 & c_ip_15_0;
+ -- D0 & c_id
+ constant c_cep_udp_src_port : std_logic_vector(15 downto 0) := c_sdp_cep_udp_src_port_15_8 & c_id;
- constant c_exp_ip_header_checksum : natural := 16#5BDE#; -- value obtained from rx_sdp_cep_header.ip.header_checksum in wave window
+ -- value obtained from rx_sdp_cep_header.ip.header_checksum in wave window
+ constant c_exp_ip_header_checksum : natural := 16#5BDE#;
- constant c_exp_beamlet_scale : natural := natural(g_beamlet_scale * real(c_sdp_unit_beamlet_scale)); -- c_sdp_unit_beamlet_scale = 2**15;
+ -- c_sdp_unit_beamlet_scale = 2**15;
+ constant c_exp_beamlet_scale : natural := natural(g_beamlet_scale * real(c_sdp_unit_beamlet_scale));
constant c_exp_sdp_info : t_sdp_info := (
- TO_UVEC(3, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
+ -- antenna_field_index
+ TO_UVEC(3, 6),
+ -- station_id
+ TO_UVEC(601, 10),
+ -- antenna_band_index
+ '0',
+ -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
+ x"7FFFFFFF",
+ -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ b"01",
+ -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '1',
+ -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0',
+ -- beam_repositioning_flag
+ '0',
+ -- block_period = 5120
+ x"1400"
);
-- WG
- constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := c_init_bsn + 2;
-- .ampl
- constant c_wg_ampl : natural := natural(g_wg_ampl * real(c_sdp_FS_adc)); -- in number of lsb
+ -- in number of lsb
+ constant c_wg_ampl : natural := natural(g_wg_ampl * real(c_sdp_FS_adc));
constant c_exp_sp_power : real := real(c_wg_ampl**2) / 2.0;
constant c_exp_sp_ast : real := c_exp_sp_power * real(c_nof_clk_per_sync);
-- . phase
- constant c_subband_phase : real := 0.0; -- wanted subband phase in degrees = WG phase at sop
- constant c_subband_freq : real := real(g_subband) / real(c_sdp_N_fft); -- normalized by fs = f_adc = 200 MHz = dp_clk rate
- constant c_wg_latency : integer := c_diag_wg_latency - 0; -- -0 to account for BSN scheduler start trigger latency
- constant c_wg_phase_offset : real := 360.0 * real(c_wg_latency) * c_subband_freq; -- c_diag_wg_latency is in dp_clk cycles
- constant c_wg_phase : real := c_subband_phase + c_wg_phase_offset; -- WG phase in degrees
+ -- wanted subband phase in degrees = WG phase at sop
+ constant c_subband_phase : real := 0.0;
+ -- normalized by fs = f_adc = 200 MHz = dp_clk rate
+ constant c_subband_freq : real := real(g_subband) / real(c_sdp_N_fft);
+ -- -0 to account for BSN scheduler start trigger latency
+ constant c_wg_latency : integer := c_diag_wg_latency - 0;
+ -- c_diag_wg_latency is in dp_clk cycles
+ constant c_wg_phase_offset : real := 360.0 * real(c_wg_latency) * c_subband_freq;
+ -- WG phase in degrees
+ constant c_wg_phase : real := c_subband_phase + c_wg_phase_offset;
-- WPFB
constant c_pol_index : natural := g_sp mod c_sdp_Q_fft;
- constant c_pfb_index : natural := g_sp / c_sdp_Q_fft; -- only read used WPFB unit out of range(c_sdp_P_pfb = 6)
- constant c_subband_phase_offset : real := -90.0; -- WG with zero phase sinues yields subband with -90 degrees phase (negative Im, zero Re)
- constant c_subband_weight_gain : real := 1.0; -- use default unit subband weights
- constant c_subband_weight_phase : real := 0.0; -- use default unit subband weights
+ -- only read used WPFB unit out of range(c_sdp_P_pfb = 6)
+ constant c_pfb_index : natural := g_sp / c_sdp_Q_fft;
+ -- WG with zero phase sinues yields subband with -90 degrees phase (negative Im, zero Re)
+ constant c_subband_phase_offset : real := -90.0;
+ -- use default unit subband weights
+ constant c_subband_weight_gain : real := 1.0;
+ -- use default unit subband weights
+ constant c_subband_weight_phase : real := 0.0;
constant c_exp_subband_ampl : real := real(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio * c_subband_weight_gain;
- constant c_exp_subband_power : real := c_exp_subband_ampl**2.0; -- complex, so no divide by 2
+ -- complex, so no divide by 2
+ constant c_exp_subband_power : real := c_exp_subband_ampl**2.0;
constant c_exp_subband_sst : real := c_exp_subband_power * real(c_nof_block_per_sync);
type t_real_arr is array (integer range <>) of real;
- type t_slv_64_subbands_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_sub - 1); -- 512
- type t_slv_64_beamlets_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_beamlets_sdp - 1); -- 2*488 = 976
+ -- 512
+ type t_slv_64_subbands_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_sub - 1);
+ -- 2*488 = 976
+ type t_slv_64_beamlets_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_beamlets_sdp - 1);
-- BF
-- . select
- constant c_exp_beamlet_index : natural := g_beamlet * c_sdp_N_pol_bf; -- in beamset 0
+ -- in beamset 0
+ constant c_exp_beamlet_index : natural := g_beamlet * c_sdp_N_pol_bf;
-- . Beamlet weights for selected g_sp
constant c_bf_weight_re : integer := integer(g_bf_gain * real(c_sdp_unit_bf_weight) * COS(g_bf_phase * MATH_2_PI / 360.0));
constant c_bf_weight_im : integer := integer(g_bf_gain * real(c_sdp_unit_bf_weight) * SIN(g_bf_phase * MATH_2_PI / 360.0));
@@ -192,8 +243,10 @@ architecture tb of tb_lofar2_unb2b_sdp_station_bf is
constant c_exp_beamlet_re : real := c_exp_beamlet_ampl * COS(c_exp_beamlet_phase * MATH_2_PI / 360.0);
constant c_exp_beamlet_im : real := c_exp_beamlet_ampl * SIN(c_exp_beamlet_phase * MATH_2_PI / 360.0);
-- . BST
- constant c_exp_beamlet_power : real := c_exp_beamlet_ampl**2.0; -- complex, so no divide by 2
- constant c_exp_beamlet_bst : real := c_exp_subband_sst * g_bf_gain**2.0; -- = c_exp_beamlet_power * REAL(c_nof_block_per_sync)
+ -- complex, so no divide by 2
+ constant c_exp_beamlet_power : real := c_exp_beamlet_ampl**2.0;
+ -- = c_exp_beamlet_power * REAL(c_nof_block_per_sync)
+ constant c_exp_beamlet_bst : real := c_exp_subband_sst * g_bf_gain**2.0;
-- . Beamlet output
constant c_exp_beamlet_output_ampl : real := c_exp_beamlet_ampl * g_beamlet_scale;
constant c_exp_beamlet_output_phase : real := c_exp_beamlet_phase;
@@ -235,7 +288,8 @@ architecture tb of tb_lofar2_unb2b_sdp_station_bf is
constant c_mm_file_ram_bf_weights : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_BF_WEIGHTS";
constant c_mm_file_reg_bf_scale : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BF_SCALE";
constant c_mm_file_reg_sdp_info : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_SDP_INFO";
- constant c_mm_file_reg_hdr_dat : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_HDR_DAT"; -- c_sdp_N_beamsets = 2 beamsets
+ -- c_sdp_N_beamsets = 2 beamsets
+ constant c_mm_file_reg_hdr_dat : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_HDR_DAT";
-- Tb
signal stimuli_done : std_logic := '0';
@@ -244,8 +298,10 @@ architecture tb of tb_lofar2_unb2b_sdp_station_bf is
signal tb_clk : std_logic := '0';
signal rd_data : std_logic_vector(c_32 - 1 downto 0);
- signal dest_rst : std_logic := '1'; -- use separate destination rst for Rx 10GbE in tb
- signal pps_rst : std_logic := '1'; -- use separate reset to release the PPS generator
+ -- use separate destination rst for Rx 10GbE in tb
+ signal dest_rst : std_logic := '1';
+ -- use separate reset to release the PPS generator
+ signal pps_rst : std_logic := '1';
signal gen_pps : std_logic := '0';
signal in_sync : std_logic := '0';
@@ -267,7 +323,8 @@ architecture tb of tb_lofar2_unb2b_sdp_station_bf is
-- FSUB
-- . Read sp_subband_ssts_arr2 = SST for one WPFB unit that processes g_sp
- signal sp_subband_ssts_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol - 1 downto 0); -- [pol][sub], for X,Y pair of A, B
+ -- [pol][sub], for X,Y pair of A, B
+ signal sp_subband_ssts_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol - 1 downto 0);
signal sp_subband_sst : real := 0.0;
signal stat_data : std_logic_vector(c_longword_w - 1 downto 0);
@@ -282,24 +339,32 @@ architecture tb of tb_lofar2_unb2b_sdp_station_bf is
-- BF
signal sp_subband_select : natural := 0;
- signal sp_subband_select_arr : t_natural_arr(0 to c_sdp_S_sub_bf * c_sdp_N_pol - 1) := (others => 0); -- Q_fft = N_pol = 2
+ -- Q_fft = N_pol = 2
+ signal sp_subband_select_arr : t_natural_arr(0 to c_sdp_S_sub_bf * c_sdp_N_pol - 1) := (others => 0);
signal sp_bf_weights_re_arr : t_integer_arr(0 to c_sdp_S_pn - 1) := (others => 0);
signal sp_bf_weights_im_arr : t_integer_arr(0 to c_sdp_S_pn - 1) := (others => 0);
signal sp_bf_weights_gain_arr : t_real_arr(0 to c_sdp_S_pn - 1) := (others => 0.0);
signal sp_bf_weights_phase_arr : t_real_arr(0 to c_sdp_S_pn - 1) := (others => 0.0);
- signal pol_beamlet_bsts_arr2 : t_slv_64_beamlets_arr(c_sdp_N_pol_bf - 1 downto 0); -- [pol_bf][blet]
- signal pol_beamlet_bst_X_arr : t_real_arr(0 to c_sdp_N_beamsets - 1) := (others => 0.0); -- [bset]
- signal pol_beamlet_bst_Y_arr : t_real_arr(0 to c_sdp_N_beamsets - 1) := (others => 0.0); -- [bset]
+ -- [pol_bf][blet]
+ signal pol_beamlet_bsts_arr2 : t_slv_64_beamlets_arr(c_sdp_N_pol_bf - 1 downto 0);
+ -- [bset]
+ signal pol_beamlet_bst_X_arr : t_real_arr(0 to c_sdp_N_beamsets - 1) := (others => 0.0);
+ -- [bset]
+ signal pol_beamlet_bst_Y_arr : t_real_arr(0 to c_sdp_N_beamsets - 1) := (others => 0.0);
-- 10GbE
- signal rx_beamlet_arr_re : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet - 1 downto 0); -- [3:0]
- signal rx_beamlet_arr_im : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet - 1 downto 0); -- [3:0]
+ -- [3:0]
+ signal rx_beamlet_arr_re : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet - 1 downto 0);
+ -- [3:0]
+ signal rx_beamlet_arr_im : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet - 1 downto 0);
signal rx_beamlet_cnt : natural;
signal rx_beamlet_valid : std_logic;
- signal rx_beamlet_list_re : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf - 1 downto 0); -- [488 * 2-1:0] = [975:0]
- signal rx_beamlet_list_im : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf - 1 downto 0); -- [488 * 2-1:0] = [975:0]
+ -- [488 * 2-1:0] = [975:0]
+ signal rx_beamlet_list_re : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf - 1 downto 0);
+ -- [488 * 2-1:0] = [975:0]
+ signal rx_beamlet_list_im : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf - 1 downto 0);
signal tr_10GbE_src_out : t_dp_sosi;
signal tr_10GbE_src_in : t_dp_siso;
@@ -312,7 +377,8 @@ architecture tb of tb_lofar2_unb2b_sdp_station_bf is
signal offload_rx_hdr_dat_miso : t_mem_miso;
signal test_offload_en : std_logic := '0';
- signal test_offload_data : std_logic_vector(c_longword_w - 1 downto 0); -- 64 bit
+ -- 64 bit
+ signal test_offload_data : std_logic_vector(c_longword_w - 1 downto 0);
signal test_offload_sosi : t_dp_sosi := c_dp_sosi_rst;
signal test_offload_sop_cnt : natural := 0;
signal test_offload_eop_cnt : natural := 0;
@@ -354,19 +420,29 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
- SA_CLK <= not SA_CLK after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ SA_CLK <= not SA_CLK after c_sa_clk_period / 2;
dest_rst <= '0' after c_ext_clk_period * 10;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -453,9 +529,12 @@ begin
port map (
-- Transceiver PLL reference clock
tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => tr_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => tr_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156,
-- MM interface
mm_rst => dest_rst,
@@ -502,7 +581,8 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
@@ -510,8 +590,10 @@ begin
variable v_pol_beamlet_bst : real := 0.0;
variable v_data_lo, v_data_hi : std_logic_vector(c_word_w - 1 downto 0);
variable v_stat_data : std_logic_vector(c_longword_w - 1 downto 0);
- variable v_len, v_span, v_offset, v_addr, v_sel : natural; -- address ranges, indices
- variable v_W, v_P, v_S, v_A, v_B, v_G : natural; -- array indicies
+ -- address ranges, indices
+ variable v_len, v_span, v_offset, v_addr, v_sel : natural;
+ -- array indicies
+ variable v_W, v_P, v_S, v_A, v_B, v_G : natural;
variable v_re, v_im, v_weight : integer;
variable v_re_exp, v_im_exp : real := 0.0;
begin
@@ -636,12 +718,16 @@ begin
-- Write tb defaults
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 39, TO_UINT(c_cep_eth_src_mac(47 downto 32)), tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 38, TO_SINT(c_cep_eth_src_mac(31 downto 0)), tb_clk); -- use signed to fit 32 b in INTEGER
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 26, TO_SINT(c_cep_ip_src_addr), tb_clk); -- use signed to fit 32 b in INTEGER
+ -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 38, TO_SINT(c_cep_eth_src_mac(31 downto 0)), tb_clk);
+ -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 26, TO_SINT(c_cep_ip_src_addr), tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 24, TO_UINT(c_cep_udp_src_port), tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 41, TO_UINT(c_sdp_cep_eth_dst_mac(47 downto 32)), tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 40, TO_SINT(c_sdp_cep_eth_dst_mac(31 downto 0)), tb_clk); -- use signed to fit 32 b in INTEGER
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 25, TO_SINT(c_sdp_cep_ip_dst_addr), tb_clk); -- use signed to fit 32 b in INTEGER
+ -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 40, TO_SINT(c_sdp_cep_eth_dst_mac(31 downto 0)), tb_clk);
+ -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 25, TO_SINT(c_sdp_cep_ip_dst_addr), tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 23, TO_UINT(c_sdp_cep_udp_dst_port), tb_clk);
proc_common_wait_cross_clock_domain_latency(c_mm_clk_period, c_ext_clk_period, c_common_cross_clock_domain_latency * 2);
@@ -673,10 +759,14 @@ begin
----------------------------------------------------------------------------
-- Enable BS
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk); -- Init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk); -- Write high part activates the init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk);
+ -- Write high part activates the init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk);
-- Release PPS pulser, to get first PPS now and to start BSN source
wait for 1 us;
@@ -692,10 +782,14 @@ begin
-- 3 : ampl[16:0]
-- . Put wanted signal on g_sp input
v_offset := g_sp * c_mm_span_reg_diag_wg;
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk);
-- Read current BSN
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 downto 0), tb_clk);
@@ -706,8 +800,10 @@ begin
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
v_bsn := c_bsn_start_wg;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
----------------------------------------------------------------------------
-- Read weighted subband selector
@@ -739,7 +835,8 @@ begin
-- . MM format: (uint16)RAM_SS_SS_WIDE[N_beamsets][A_pn]_[S_sub_bf][Q_fft], Q_fft = N_pol = 2
-- . write selection, only for g_beamlet to save sim time
- v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf); -- = 1024
+ -- = 1024
+ v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf);
for U in 0 to c_sdp_N_beamsets - 1 loop
-- Same selection for both beamsets
-- Select beamlet g_beamlet to subband g_subband
@@ -764,11 +861,13 @@ begin
mmf_mm_bus_rd(c_mm_file_ram_ss_ss_wide, v_addr, rd_data, tb_clk);
v_sel := (TO_UINT(rd_data) - v_P) / c_sdp_N_pol;
sp_subband_select_arr(B) <= v_sel;
- sp_subband_select <= v_sel; -- for time series view in Wave window
+ -- for time series view in Wave window
+ sp_subband_select <= v_sel;
end loop;
end loop;
proc_common_wait_some_cycles(tb_clk, 1);
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
----------------------------------------------------------------------------
-- Write beamlet weight for g_beamlet
@@ -776,7 +875,8 @@ begin
-- . MM format: (cint16)RAM_BF_WEIGHTS[N_beamsets][N_pol_bf][A_pn]_[N_pol][S_sub_bf]
-- . write BF weights, only for g_beamlet to save sim time
- v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf); -- = 1024
+ -- = 1024
+ v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf);
for U in 0 to c_sdp_N_beamsets - 1 loop
-- Same BF weights for both beamsets
for A in 0 to c_sdp_A_pn - 1 loop
@@ -815,13 +915,16 @@ begin
end loop;
end loop;
proc_common_wait_some_cycles(tb_clk, 1);
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
----------------------------------------------------------------------------
-- Wait for enough WG data and start of sync interval
----------------------------------------------------------------------------
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 3, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 3,
c_sdp_T_sub, tb_clk);
-- Stimuli done, now verify results at end of test
@@ -840,13 +943,19 @@ begin
-- . the subbands are output alternately so A0 B0 A1 B1 ... A511 B511 for input A, B
-- . the subband statistics multiple WPFB units appear in order in the ram_st_sst address map
-- . the subband statistics are stored first lo word 0 then hi word 1
- v_len := c_sdp_N_sub * c_sdp_N_pol * c_stat_data_sz; -- 2048 = 512 * 2 * 64/32
- v_span := true_log_pow2(v_len); -- = 2048
+ -- 2048 = 512 * 2 * 64/32
+ v_len := c_sdp_N_sub * c_sdp_N_pol * c_stat_data_sz;
+ -- = 2048
+ v_span := true_log_pow2(v_len);
for I in 0 to v_len - 1 loop
- v_W := I mod c_stat_data_sz; -- 0, 1 per statistics word, word index
- v_P := (I / c_stat_data_sz) mod c_sdp_N_pol; -- 0, 1 per SP pol, polarization index
- v_B := I / (c_sdp_N_pol * c_stat_data_sz); -- subband index, range(N_sub = 512) per dual pol
- v_addr := I + c_pfb_index * v_span; -- MM address
+ -- 0, 1 per statistics word, word index
+ v_W := I mod c_stat_data_sz;
+ -- 0, 1 per SP pol, polarization index
+ v_P := (I / c_stat_data_sz) mod c_sdp_N_pol;
+ -- subband index, range(N_sub = 512) per dual pol
+ v_B := I / (c_sdp_N_pol * c_stat_data_sz);
+ -- MM address
+ v_addr := I + c_pfb_index * v_span;
-- Only read SST for g_subband for dual pol SP, to save sim time
if g_read_all_SST = true or v_B = g_subband then
if v_W = 0 then
@@ -860,7 +969,8 @@ begin
v_stat_data := v_data_hi & v_data_lo;
sp_subband_ssts_arr2(v_P)(v_B) <= v_stat_data;
- stat_data <= v_stat_data; -- for time series view in Wave window
+ -- for time series view in Wave window
+ stat_data <= v_stat_data;
end if;
end if;
end loop;
@@ -872,7 +982,8 @@ begin
-- sinus, so most power will be in 1 subband.
sp_subband_sst <= TO_UREAL(sp_subband_ssts_arr2(c_pol_index)(g_subband));
proc_common_wait_some_cycles(tb_clk, 1);
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
---------------------------------------------------------------------------
-- Read beamlet statistics
@@ -882,15 +993,22 @@ begin
-- . the beamlets are output alternately so X0 Y0 X1 Y1 ... X487 Y487 for polarizations X, Y
-- . the beamlet statistics for multiple beamsets appear in order in the ram_st_bst address map
-- . the beamlet statistics are stored first lo word 0 then hi word 1
- v_len := c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_stat_data_sz; -- = 1952 = 488 * 2 * 64/32
- v_span := true_log_pow2(v_len); -- = 2048
+ -- = 1952 = 488 * 2 * 64/32
+ v_len := c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_stat_data_sz;
+ -- = 2048
+ v_span := true_log_pow2(v_len);
for U in 0 to c_sdp_N_beamsets - 1 loop
for I in 0 to v_len - 1 loop
- v_W := I mod c_stat_data_sz; -- 0, 1 per statistics word, word index
- v_P := (I / c_stat_data_sz) mod c_sdp_N_pol_bf; -- 0, 1 per BF pol, polarization index
- v_B := I / (c_sdp_N_pol_bf * c_stat_data_sz); -- beamlet index in beamset, range(S_sub_bf = 488) per dual pol
- v_G := v_B + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
- v_addr := I + U * v_span; -- MM address
+ -- 0, 1 per statistics word, word index
+ v_W := I mod c_stat_data_sz;
+ -- 0, 1 per BF pol, polarization index
+ v_P := (I / c_stat_data_sz) mod c_sdp_N_pol_bf;
+ -- beamlet index in beamset, range(S_sub_bf = 488) per dual pol
+ v_B := I / (c_sdp_N_pol_bf * c_stat_data_sz);
+ -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ v_G := v_B + U * c_sdp_S_sub_bf;
+ -- MM address
+ v_addr := I + U * v_span;
--Only read BST for g_beamlet and dual pol_bf 0 and 1 and for both beamsets, to save sim time
if g_read_all_BST = true or v_B = g_beamlet then
if v_W = 0 then
@@ -904,7 +1022,8 @@ begin
v_stat_data := v_data_hi & v_data_lo;
pol_beamlet_bsts_arr2(v_P)(v_G) <= v_stat_data;
- stat_data <= v_stat_data; -- for time series view in Wave window
+ -- for time series view in Wave window
+ stat_data <= v_stat_data;
end if;
end if;
end loop;
@@ -913,12 +1032,16 @@ begin
-- Beamlet power of g_beamlet X and Y, same for both beamsets
for U in 0 to c_sdp_N_beamsets - 1 loop
- v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
- pol_beamlet_bst_X_arr(U) <= TO_UREAL(pol_beamlet_bsts_arr2(0)(v_G)); -- X pol beamlet
- pol_beamlet_bst_Y_arr(U) <= TO_UREAL(pol_beamlet_bsts_arr2(1)(v_G)); -- Y pol beamlet
+ -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ v_G := g_beamlet + U * c_sdp_S_sub_bf;
+ -- X pol beamlet
+ pol_beamlet_bst_X_arr(U) <= TO_UREAL(pol_beamlet_bsts_arr2(0)(v_G));
+ -- Y pol beamlet
+ pol_beamlet_bst_Y_arr(U) <= TO_UREAL(pol_beamlet_bsts_arr2(1)(v_G));
end loop;
proc_common_wait_some_cycles(tb_clk, 1);
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
---------------------------------------------------------------------------
-- Log WG, subband and beamlet statistics
@@ -955,12 +1078,14 @@ begin
print_str(". c_exp_beamlet_bst = " & real_to_str(c_exp_beamlet_bst, 20, 1));
print_str("");
for U in 0 to c_sdp_N_beamsets - 1 loop
- v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ v_G := g_beamlet + U * c_sdp_S_sub_bf;
print_str(". pol_beamlet_bst_X beamlet(" & integer'image(v_G) & ") = " & real_to_str(pol_beamlet_bst_X_arr(U), 20, 1));
print_str(". pol_beamlet_bst_Y beamlet(" & integer'image(v_G) & ") = " & real_to_str(pol_beamlet_bst_Y_arr(U), 20, 1));
end loop;
for U in 0 to c_sdp_N_beamsets - 1 loop
- v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ v_G := g_beamlet + U * c_sdp_S_sub_bf;
print_str(". pol_beamlet_bst_X beamlet(" & integer'image(v_G) & ") / c_exp_beamlet_bst = " & real_to_str(pol_beamlet_bst_X_arr(U) / c_exp_beamlet_bst, 20, 6));
print_str(". pol_beamlet_bst_Y beamlet(" & integer'image(v_G) & ") / c_exp_beamlet_bst = " & real_to_str(pol_beamlet_bst_Y_arr(U) / c_exp_beamlet_bst, 20, 6));
end loop;
@@ -1009,7 +1134,8 @@ begin
-- End Simulation
---------------------------------------------------------------------------
tb_almost_end <= '1';
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
proc_common_stop_simulation(true, ext_clk, tb_almost_end, tb_end);
wait;
end process;
@@ -1024,17 +1150,20 @@ begin
if rising_edge(ext_clk) then
-- Count test_offload_sosi packets
if test_offload_sosi.sop = '1' then
- test_offload_sop_cnt <= test_offload_sop_cnt + 1; -- early count
+ -- early count
+ test_offload_sop_cnt <= test_offload_sop_cnt + 1;
end if;
if test_offload_sosi.eop = '1' then
- test_offload_eop_cnt <= test_offload_eop_cnt + 1; -- after count
+ -- after count
+ test_offload_eop_cnt <= test_offload_eop_cnt + 1;
end if;
end if;
end process;
-- Count sync intervals using in_sosi.sync, because there is no test_offload_sosi.sync
in_sync_cnt <= in_sync_cnt + 1 when rising_edge(ext_clk) and in_sync = '1';
- test_sync_cnt <= in_sync_cnt - 1; -- optionally adjust to fit test_offload_sosi
+ -- optionally adjust to fit test_offload_sosi
+ test_sync_cnt <= in_sync_cnt - 1;
-- Prepare exp_sdp_cep_header before test_offload_sosi.eop, so that
-- p_exp_sdp_cep_header can verify it at test_offload_sosi.eop.
@@ -1050,25 +1179,31 @@ begin
exp_sdp_cep_header.ip.version <= TO_UVEC( 4, c_network_ip_version_w);
exp_sdp_cep_header.ip.header_length <= TO_UVEC( 5, c_network_ip_header_length_w);
exp_sdp_cep_header.ip.services <= TO_UVEC( 0, c_network_ip_services_w);
- exp_sdp_cep_header.ip.total_length <= c_sdp_cep_ip_total_length; -- 7868, see ICD STAT-CEP
+ -- 7868, see ICD STAT-CEP
+ exp_sdp_cep_header.ip.total_length <= c_sdp_cep_ip_total_length;
exp_sdp_cep_header.ip.identification <= TO_UVEC( 0, c_network_ip_identification_w);
exp_sdp_cep_header.ip.flags <= TO_UVEC( 2, c_network_ip_flags_w);
exp_sdp_cep_header.ip.fragment_offset <= TO_UVEC( 0, c_network_ip_fragment_offset_w);
exp_sdp_cep_header.ip.time_to_live <= TO_UVEC( 127, c_network_ip_time_to_live_w);
exp_sdp_cep_header.ip.protocol <= TO_UVEC( 17, c_network_ip_protocol_w);
exp_sdp_cep_header.ip.header_checksum <= TO_UVEC( c_exp_ip_header_checksum, c_network_ip_header_checksum_w);
- exp_sdp_cep_header.ip.src_ip_addr <= c_cep_ip_src_addr; -- c_network_ip_addr_w
- exp_sdp_cep_header.ip.dst_ip_addr <= c_sdp_cep_ip_dst_addr; -- c_network_ip_addr_w
+ -- c_network_ip_addr_w
+ exp_sdp_cep_header.ip.src_ip_addr <= c_cep_ip_src_addr;
+ -- c_network_ip_addr_w
+ exp_sdp_cep_header.ip.dst_ip_addr <= c_sdp_cep_ip_dst_addr;
-- udp header
exp_sdp_cep_header.udp.src_port <= c_cep_udp_src_port;
exp_sdp_cep_header.udp.dst_port <= c_sdp_cep_udp_dst_port;
- exp_sdp_cep_header.udp.total_length <= c_sdp_cep_udp_total_length; -- 7848, see ICD STAT-CEP
+ -- 7848, see ICD STAT-CEP
+ exp_sdp_cep_header.udp.total_length <= c_sdp_cep_udp_total_length;
exp_sdp_cep_header.udp.checksum <= TO_UVEC( 0, c_network_udp_checksum_w);
-- app header
- exp_sdp_cep_header.app.sdp_marker <= TO_UVEC(c_sdp_marker_beamlets, 8); -- 98 = x"62" = 'b'
- exp_sdp_cep_header.app.sdp_version_id <= TO_UVEC(c_sdp_cep_version_id, 8); -- 5
+ -- 98 = x"62" = 'b'
+ exp_sdp_cep_header.app.sdp_marker <= TO_UVEC(c_sdp_marker_beamlets, 8);
+ -- 5
+ exp_sdp_cep_header.app.sdp_version_id <= TO_UVEC(c_sdp_cep_version_id, 8);
exp_sdp_cep_header.app.sdp_observation_id <= c_exp_sdp_info.observation_id;
exp_sdp_cep_header.app.sdp_station_info <= c_exp_sdp_info.antenna_field_index & c_exp_sdp_info.station_id;
@@ -1083,12 +1218,14 @@ begin
exp_sdp_cep_header.app.sdp_reserved <= TO_UVEC( 0, 40);
exp_sdp_cep_header.app.sdp_beamlet_scale <= TO_UVEC( c_exp_beamlet_scale, 16);
- exp_sdp_cep_header.app.sdp_beamlet_index <= TO_UVEC( 0, 16); -- depends on bset
+ -- depends on bset
+ exp_sdp_cep_header.app.sdp_beamlet_index <= TO_UVEC( 0, 16);
exp_sdp_cep_header.app.sdp_nof_blocks_per_packet <= TO_UVEC( c_sdp_cep_nof_blocks_per_packet, 8);
exp_sdp_cep_header.app.sdp_nof_beamlets_per_block <= TO_UVEC(c_sdp_cep_nof_beamlets_per_block, 16);
exp_sdp_cep_header.app.sdp_block_period <= c_exp_sdp_info.block_period;
- exp_sdp_cep_header.app.dp_bsn <= TO_UVEC(exp_dp_bsn, 64); -- depends on bset and time
+ -- depends on bset and time
+ exp_sdp_cep_header.app.dp_bsn <= TO_UVEC(exp_dp_bsn, 64);
end process;
rx_sdp_cep_header <= func_sdp_map_cep_header(rx_hdr_fields_raw);
@@ -1139,23 +1276,31 @@ begin
proc_common_wait_until_high(ext_clk, test_offload_sosi.valid);
rx_beamlet_valid <= '1';
-- Capture rx beamlets per longword in rx_beamlet_arr, for time series view in Wave window
- rx_beamlet_arr_re(0) <= test_offload_sosi.data(63 downto 56); -- X
+ -- X
+ rx_beamlet_arr_re(0) <= test_offload_sosi.data(63 downto 56);
rx_beamlet_arr_im(0) <= test_offload_sosi.data(55 downto 48);
- rx_beamlet_arr_re(1) <= test_offload_sosi.data(47 downto 40); -- Y
+ -- Y
+ rx_beamlet_arr_re(1) <= test_offload_sosi.data(47 downto 40);
rx_beamlet_arr_im(1) <= test_offload_sosi.data(39 downto 32);
- rx_beamlet_arr_re(2) <= test_offload_sosi.data(31 downto 24); -- X
+ -- X
+ rx_beamlet_arr_re(2) <= test_offload_sosi.data(31 downto 24);
rx_beamlet_arr_im(2) <= test_offload_sosi.data(23 downto 16);
- rx_beamlet_arr_re(3) <= test_offload_sosi.data(15 downto 8); -- Y
+ -- Y
+ rx_beamlet_arr_re(3) <= test_offload_sosi.data(15 downto 8);
rx_beamlet_arr_im(3) <= test_offload_sosi.data( 7 downto 0);
if I < c_sdp_cep_nof_beamlets_per_block / 2 then
-- Only capture the first beamlets block of each packet in rx_beamlet_list
- rx_beamlet_list_re(I * 4 + 0) <= test_offload_sosi.data(63 downto 56); -- X
+ -- X
+ rx_beamlet_list_re(I * 4 + 0) <= test_offload_sosi.data(63 downto 56);
rx_beamlet_list_im(I * 4 + 0) <= test_offload_sosi.data(55 downto 48);
- rx_beamlet_list_re(I * 4 + 1) <= test_offload_sosi.data(47 downto 40); -- Y
+ -- Y
+ rx_beamlet_list_re(I * 4 + 1) <= test_offload_sosi.data(47 downto 40);
rx_beamlet_list_im(I * 4 + 1) <= test_offload_sosi.data(39 downto 32);
- rx_beamlet_list_re(I * 4 + 2) <= test_offload_sosi.data(31 downto 24); -- X
+ -- X
+ rx_beamlet_list_re(I * 4 + 2) <= test_offload_sosi.data(31 downto 24);
rx_beamlet_list_im(I * 4 + 2) <= test_offload_sosi.data(23 downto 16);
- rx_beamlet_list_re(I * 4 + 3) <= test_offload_sosi.data(15 downto 8); -- Y
+ -- Y
+ rx_beamlet_list_re(I * 4 + 3) <= test_offload_sosi.data(15 downto 8);
rx_beamlet_list_im(I * 4 + 3) <= test_offload_sosi.data( 7 downto 0);
end if;
proc_common_wait_until_high(ext_clk, test_offload_sosi.valid);
@@ -1164,7 +1309,8 @@ begin
-- contains no WAIT statement.
wait until rising_edge(ext_clk);
rx_beamlet_valid <= '0';
- rx_beamlet_cnt <= (rx_beamlet_cnt + 4) mod c_sdp_cep_nof_beamlets_per_block; -- 4 blocks/packet
+ -- 4 blocks/packet
+ rx_beamlet_cnt <= (rx_beamlet_cnt + 4) mod c_sdp_cep_nof_beamlets_per_block;
end loop;
end process;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
index 2285e92f73ce6f98e3395c146054461765d58284..e33ee84fb8a07cd8035c4d9eb9fac62bc7fa012b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
@@ -58,19 +58,23 @@ end tb_lofar2_unb2b_sdp_station_bf_bst_offload;
architecture tb of tb_lofar2_unb2b_sdp_station_bf_bst_offload is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
- constant c_nof_block_per_sync : natural := 16; -- long enough to stream out udp data
+ -- long enough to stream out udp data
+ constant c_nof_block_per_sync : natural := 16;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_pps_period : natural := c_nof_clk_per_sync;
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
@@ -88,10 +92,14 @@ architecture tb of tb_lofar2_unb2b_sdp_station_bf_bst_offload is
signal eth_done : std_logic := '0';
-- . 1GbE output
- constant c_eth_check_nof_packets : natural := c_nof_sync * 1; -- 1 received packet per sync interval
- constant c_eth_header_size : natural := 19; -- words
- constant c_eth_crc_size : natural := 1; -- word
- constant c_eth_packet_size : natural := c_eth_header_size + c_eth_crc_size + (c_sdp_W_statistic / c_word_w) * c_sdp_S_sub_bf * c_sdp_N_pol; -- 20 + 2 * 488 * 2 = 1972
+ -- 1 received packet per sync interval
+ constant c_eth_check_nof_packets : natural := c_nof_sync * 1;
+ -- words
+ constant c_eth_header_size : natural := 19;
+ -- word
+ constant c_eth_crc_size : natural := 1;
+ -- 20 + 2 * 488 * 2 = 1972
+ constant c_eth_packet_size : natural := c_eth_header_size + c_eth_crc_size + (c_sdp_W_statistic / c_word_w) * c_sdp_S_sub_bf * c_sdp_N_pol;
constant c_eth_check_nof_valid : natural := c_eth_check_nof_packets * c_eth_packet_size;
-- eth statistics should be done after c_nof_sync + 1 intervals (+1 because first new_interval is skipped)
@@ -127,17 +135,26 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -200,7 +217,8 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
begin
@@ -211,9 +229,12 @@ begin
-- Enable BSN
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk); -- Enable BSN immediately
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BSN immediately
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk);
----------------------------------------------------------------------------
-- Offload enable
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
index 486993590125f4e5b065d84dbb19c848d0f80367..e9684ee7446547746fb68125f8b5c5e4e06320c0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2b_sdp_station_fsub is
generic (
g_design_name : string := "lofar2_unb2b_sdp_station_fsub";
g_design_note : string := "Lofar2 SDP station filterbank design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -75,12 +84,15 @@ entity lofar2_unb2b_sdp_station_fsub is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- back transceivers (note only 6 are used in unb2b)
- BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0)
);
end lofar2_unb2b_sdp_station_fsub;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
index ae4d83d08ea97fa788ff42172351ba2766e67b31..defb10de868297274bf663d08e88173090bdbf5f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
@@ -75,69 +75,95 @@ use unb2b_board_lib.unb2b_board_pkg.all;
entity tb_lofar2_unb2b_sdp_station_fsub is
generic (
- g_sp : natural := 3; -- signal path index in range(S_pn = 12)
- g_wg_ampl : real := 1.0; -- WG normalized amplitude
- g_subband : natural := 102; -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- g_subband_weight_gain : real := 1.0; -- subband weight normalized gain
- g_subband_weight_phase : real := 30.0; -- subband weight phase rotation in degrees
- g_read_all_SST : boolean := true -- when FALSE only read SST for g_subband, to save sim time
+ -- signal path index in range(S_pn = 12)
+ g_sp : natural := 3;
+ -- WG normalized amplitude
+ g_wg_ampl : real := 1.0;
+ -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_subband : natural := 102;
+ -- subband weight normalized gain
+ g_subband_weight_gain : real := 1.0;
+ -- subband weight phase rotation in degrees
+ g_subband_weight_phase : real := 30.0;
+ -- when FALSE only read SST for g_subband, to save sim time
+ g_read_all_SST : boolean := true
);
end tb_lofar2_unb2b_sdp_station_fsub;
architecture tb of tb_lofar2_unb2b_sdp_station_fsub is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
- constant c_init_bsn : natural := 17; -- some recognizable value >= 0
+ -- some recognizable value >= 0
+ constant c_init_bsn : natural := 17;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_nof_block_per_sync : natural := 16;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_pps_period : natural := c_nof_clk_per_sync;
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
- constant c_stat_data_sz : natural := c_wpfb_sim.stat_data_sz; -- = 2
+ -- = 2
+ constant c_stat_data_sz : natural := c_wpfb_sim.stat_data_sz;
- constant c_percentage : real := 0.05; -- percentage that actual value may differ from expected value
- constant c_lo_factor : real := 1.0 - c_percentage; -- lower boundary
- constant c_hi_factor : real := 1.0 + c_percentage; -- higher boundary
+ -- percentage that actual value may differ from expected value
+ constant c_percentage : real := 0.05;
+ -- lower boundary
+ constant c_lo_factor : real := 1.0 - c_percentage;
+ -- higher boundary
+ constant c_hi_factor : real := 1.0 + c_percentage;
-- WG
- constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := c_init_bsn + 2;
-- .ampl
- constant c_wg_ampl : natural := natural(g_wg_ampl * real(c_sdp_FS_adc)); -- in number of lsb
+ -- in number of lsb
+ constant c_wg_ampl : natural := natural(g_wg_ampl * real(c_sdp_FS_adc));
constant c_exp_sp_power : real := real(c_wg_ampl**2) / 2.0;
constant c_exp_sp_ast : real := c_exp_sp_power * real(c_nof_clk_per_sync);
-- . phase
- constant c_subband_phase : real := 0.0; -- wanted subband phase in degrees = WG phase at sop
- constant c_subband_freq : real := real(g_subband) / real(c_sdp_N_fft); -- normalized by fs = f_adc = 200 MHz is dp_clk
- constant c_wg_latency : integer := c_diag_wg_latency - 0; -- -0 to account for BSN scheduler start trigger latency
- constant c_wg_phase_offset : real := 360.0 * real(c_wg_latency) * c_subband_freq; -- c_diag_wg_latency is in dp_clk cycles
- constant c_wg_phase : real := c_subband_phase + c_wg_phase_offset; -- WG phase in degrees
+ -- wanted subband phase in degrees = WG phase at sop
+ constant c_subband_phase : real := 0.0;
+ -- normalized by fs = f_adc = 200 MHz is dp_clk
+ constant c_subband_freq : real := real(g_subband) / real(c_sdp_N_fft);
+ -- -0 to account for BSN scheduler start trigger latency
+ constant c_wg_latency : integer := c_diag_wg_latency - 0;
+ -- c_diag_wg_latency is in dp_clk cycles
+ constant c_wg_phase_offset : real := 360.0 * real(c_wg_latency) * c_subband_freq;
+ -- WG phase in degrees
+ constant c_wg_phase : real := c_subband_phase + c_wg_phase_offset;
-- FSUB
-- . WPFB
constant c_pol_index : natural := g_sp mod c_sdp_Q_fft;
- constant c_pfb_index : natural := g_sp / c_sdp_Q_fft; -- only read used WPFB unit out of range(c_sdp_P_pfb = 6)
+ -- only read used WPFB unit out of range(c_sdp_P_pfb = 6)
+ constant c_pfb_index : natural := g_sp / c_sdp_Q_fft;
constant c_exp_subband_ampl_raw : real := real(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio;
constant c_exp_subband_ampl_weighted : real := c_exp_subband_ampl_raw * g_subband_weight_gain;
- constant c_exp_subband_power_raw : real := c_exp_subband_ampl_raw**2.0; -- complex, so no divide by 2
- constant c_exp_subband_power_weighted : real := c_exp_subband_ampl_weighted**2.0; -- complex, so no divide by 2
+ -- complex, so no divide by 2
+ constant c_exp_subband_power_raw : real := c_exp_subband_ampl_raw**2.0;
+ -- complex, so no divide by 2
+ constant c_exp_subband_power_weighted : real := c_exp_subband_ampl_weighted**2.0;
constant c_exp_subband_sst_raw : real := c_exp_subband_power_raw * real(c_nof_block_per_sync);
constant c_exp_subband_sst_weighted : real := c_exp_subband_power_weighted * real(c_nof_block_per_sync);
-- . expected limit values, obtained with print_str() for g_subband = 102,
-- g_wg_ampl = 1.0, g_subband_weight_gain = 1.0, g_subband_weight_phase = 30.0
- constant c_exp_subband_sst_leakage_snr_dB : real := 70.0; -- < 74.913
- constant c_exp_subband_sst_crosstalk_snr_dB : real := 90.0; -- < 96.284
+ -- < 74.913
+ constant c_exp_subband_sst_leakage_snr_dB : real := 70.0;
+ -- < 96.284
+ constant c_exp_subband_sst_crosstalk_snr_dB : real := 90.0;
type t_real_arr is array (integer range <>) of real;
type t_slv_64_subbands_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_sub - 1);
@@ -173,13 +199,16 @@ architecture tb of tb_lofar2_unb2b_sdp_station_fsub is
-- FSUB
-- . WPFB
- signal sp_subband_ssts_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol - 1 downto 0); -- [pol][sub]
+ -- [pol][sub]
+ signal sp_subband_ssts_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol - 1 downto 0);
signal sp_subband_sst_sum_arr : t_real_arr(c_sdp_N_pol - 1 downto 0) := (others => 0.0);
signal sp_subband_sst : real := 0.0;
signal sp_subband_sst_leakage : real := 0.0;
- signal sp_subband_sst_leakage_snr_dB : real := 0.0; -- signal to noise (leakage) ratio
+ -- signal to noise (leakage) ratio
+ signal sp_subband_sst_leakage_snr_dB : real := 0.0;
signal sp_subband_sst_crosstalk : real := 0.0;
- signal sp_subband_sst_crosstalk_snr_dB : real := 0.0; -- signal to noise (crosstalk) ration
+ -- signal to noise (crosstalk) ration
+ signal sp_subband_sst_crosstalk_snr_dB : real := 0.0;
signal exp_subband_ampl : real := 0.0;
signal exp_subband_power : real := 0.0;
@@ -223,16 +252,24 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -301,14 +338,17 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
variable v_data_lo, v_data_hi : std_logic_vector(c_word_w - 1 downto 0);
variable v_stat_data : std_logic_vector(c_longword_w - 1 downto 0);
- variable v_len, v_span, v_offset, v_addr : natural; -- address ranges, indices
- variable v_W, v_P, v_U, v_S, v_B : natural; -- array indicies
+ -- address ranges, indices
+ variable v_len, v_span, v_offset, v_addr : natural;
+ -- array indicies
+ variable v_W, v_P, v_U, v_S, v_B : natural;
variable v_re, v_im, v_weight : integer;
variable v_power : real;
begin
@@ -318,10 +358,14 @@ begin
----------------------------------------------------------------------------
-- Enable BSN
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk); -- Init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk); -- Write high part activates the init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BSN at PPS
+ -- Init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk);
+ -- Write high part activates the init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BSN at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk);
-- Release PPS pulser, to get first PPS now and to start BSN source
wait for 1 us;
@@ -343,10 +387,14 @@ begin
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
v_offset := g_sp * c_mm_span_reg_diag_wg;
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk);
-- Read current BSN
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 downto 0), tb_clk);
@@ -356,8 +404,10 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
----------------------------------------------------------------------------
-- Write subband weight for selected g_sp and g_subband
@@ -373,7 +423,8 @@ begin
sp_subband_weight_gain <= SQRT(real(v_re)**2.0 + real(v_im)**2.0) / real(c_sdp_unit_sub_weight);
sp_subband_weight_phase <= atan2(Y => real(v_im), X => real(v_re)) * 360.0 / MATH_2_PI;
-- . write
- v_weight := pack_complex(re => c_subband_weight_re, im => c_subband_weight_im, w => c_sdp_W_sub_weight); -- c_sdp_W_sub_weight = 16 bit
+ -- c_sdp_W_sub_weight = 16 bit
+ v_weight := pack_complex(re => c_subband_weight_re, im => c_subband_weight_im, w => c_sdp_W_sub_weight);
mmf_mm_bus_wr(c_mm_file_ram_equalizer_gains, v_addr, v_weight, tb_clk);
-- . read back
mmf_mm_bus_rd(c_mm_file_ram_equalizer_gains, v_addr, rd_data, tb_clk);
@@ -387,8 +438,10 @@ begin
----------------------------------------------------------------------------
-- Wait for enough WG data and start of sync interval
----------------------------------------------------------------------------
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 3, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 3,
c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
@@ -404,13 +457,19 @@ begin
-- . the subbands are output alternately so A0 B0 A1 B1 ... A511 B511 for input A, B
-- . the subband statistics multiple WPFB units appear in order in the ram_st_sst address map
-- . the subband statistics are stored first lo word 0 then hi word 1
- v_len := c_sdp_N_sub * c_sdp_N_pol * c_stat_data_sz; -- 2048 = 512 * 2 * 64/32
- v_span := true_log_pow2(v_len); -- = 2048
+ -- 2048 = 512 * 2 * 64/32
+ v_len := c_sdp_N_sub * c_sdp_N_pol * c_stat_data_sz;
+ -- = 2048
+ v_span := true_log_pow2(v_len);
for I in 0 to v_len - 1 loop
- v_W := I mod c_stat_data_sz; -- 0, 1 per statistics word, word index
- v_P := (I / c_stat_data_sz) mod c_sdp_N_pol; -- 0, 1 per SP pol, polarization index
- v_B := I / (c_sdp_N_pol * c_stat_data_sz); -- subband index, range(N_sub = 512) per dual pol
- v_addr := I + c_pfb_index * v_span; -- MM address for WPFB unit of selected g_sp
+ -- 0, 1 per statistics word, word index
+ v_W := I mod c_stat_data_sz;
+ -- 0, 1 per SP pol, polarization index
+ v_P := (I / c_stat_data_sz) mod c_sdp_N_pol;
+ -- subband index, range(N_sub = 512) per dual pol
+ v_B := I / (c_sdp_N_pol * c_stat_data_sz);
+ -- MM address for WPFB unit of selected g_sp
+ v_addr := I + c_pfb_index * v_span;
-- Only read SST for g_subband for dual pol SP, to save sim time
if g_read_all_SST = true or v_B = g_subband then
if v_W = 0 then
@@ -424,7 +483,8 @@ begin
v_stat_data := v_data_hi & v_data_lo;
sp_subband_ssts_arr2(v_P)(v_B) <= v_stat_data;
- stat_data <= v_stat_data; -- for time series view in Wave window
+ -- for time series view in Wave window
+ stat_data <= v_stat_data;
-- sum of all subband powers per pol
sp_subband_sst_sum_arr(v_P) <= sp_subband_sst_sum_arr(v_P) + TO_UREAL(v_stat_data);
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
index 01701f878f46068c3a02ac7b9f690496b64f6208..b8f1a4aa85b67ce8216c80e7286e9ddefbfcfbf3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
@@ -59,17 +59,21 @@ architecture tb of tb_lofar2_unb2b_sdp_station_fsub_sst_offload is
constant c_sim : boolean := true;
constant c_unb_nr : natural := 2;
constant c_node_nr : natural := 1;
- constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr * 4 + c_node_nr, 8); -- c_unb2b_board_nof_node = 4, c_unb2b_board_aux.id_w = 8
+ -- c_unb2b_board_nof_node = 4, c_unb2b_board_aux.id_w = 8
+ constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr * 4 + c_node_nr, 8);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
- constant c_nof_block_per_sync : natural := 80; -- long enough to stream out udp data
+ -- long enough to stream out udp data
+ constant c_nof_block_per_sync : natural := 80;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_pps_period : natural := c_nof_clk_per_sync;
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
@@ -87,10 +91,14 @@ architecture tb of tb_lofar2_unb2b_sdp_station_fsub_sst_offload is
signal eth_done : std_logic := '0';
-- . 1GbE output
- constant c_eth_check_nof_packets : natural := c_nof_sync * c_sdp_S_pn; -- S_pn = 12 received packets per sync interval
- constant c_eth_header_size : natural := 19; -- words
- constant c_eth_crc_size : natural := 1; -- word
- constant c_eth_packet_size : natural := c_eth_header_size + c_eth_crc_size + c_sdp_N_sub * (c_sdp_W_statistic / c_word_w); -- 20 + 512 * 2 = 1044
+ -- S_pn = 12 received packets per sync interval
+ constant c_eth_check_nof_packets : natural := c_nof_sync * c_sdp_S_pn;
+ -- words
+ constant c_eth_header_size : natural := 19;
+ -- word
+ constant c_eth_crc_size : natural := 1;
+ -- 20 + 512 * 2 = 1044
+ constant c_eth_packet_size : natural := c_eth_header_size + c_eth_crc_size + c_sdp_N_sub * (c_sdp_W_statistic / c_word_w);
constant c_eth_check_nof_valid : natural := c_eth_check_nof_packets * c_eth_packet_size;
-- eth statistics should be done after c_nof_sync + 1 intervals (+1 because first new_interval is skipped)
@@ -126,17 +134,26 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -199,7 +216,8 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
begin
@@ -210,9 +228,12 @@ begin
-- Enable BSN
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk); -- Enable BSN immediately
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BSN immediately
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk);
----------------------------------------------------------------------------
-- Offload enable
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
index fd878bb3cf9de4a6271d3a4b340665f85b2b7383..f0d3229e427fb3323a97b7a01a271fc25a13d5b8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2b_sdp_station_full is
generic (
g_design_name : string := "lofar2_unb2b_sdp_station_full";
g_design_note : string := "Lofar2 SDP station full design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -72,7 +81,8 @@ entity lofar2_unb2b_sdp_station_full is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP0 for Ring.
QSFP_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -85,18 +95,22 @@ entity lofar2_unb2b_sdp_station_full is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (note only 6 are used in unb2b)
- BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0)
);
end lofar2_unb2b_sdp_station_full;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
index 5412994b0eead9bb2323560ce8d2bb771a82c8c3..bb5829a940842b134cb201ec0510fa68b01e9684 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2b_sdp_station_full_wg is
generic (
g_design_name : string := "lofar2_unb2b_sdp_station_full_wg";
g_design_note : string := "Lofar2 SDP station full design WG";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -72,7 +81,8 @@ entity lofar2_unb2b_sdp_station_full_wg is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP0 for Ring.
QSFP_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -86,7 +96,8 @@ entity lofar2_unb2b_sdp_station_full_wg is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0)
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
index 925e86ef84fc7f1e3f86c40c9a2c239e8e5e5992..8c1a2d84a1e8ac0e875d39db6e4bc96eafe6393a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2b_sdp_station_xsub_one is
generic (
g_design_name : string := "lofar2_unb2b_sdp_station_xsub_one";
g_design_note : string := "Lofar2 SDP station subband correlator design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -75,12 +84,15 @@ entity lofar2_unb2b_sdp_station_xsub_one is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- back transceivers (note only 6 are used in unb2b)
- BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0)
);
end lofar2_unb2b_sdp_station_xsub_one;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
index 95899d4d5894634e6b1ab3fda7976c57cc8819e0..7ad89b0b550e0b2e0087430e1787b428ea817ca9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -65,17 +65,20 @@ end tb_lofar2_unb2b_sdp_station_xsub_one;
architecture tb of tb_lofar2_unb2b_sdp_station_xsub_one is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_nof_block_per_sync : natural := 24;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
@@ -83,22 +86,33 @@ architecture tb of tb_lofar2_unb2b_sdp_station_xsub_one is
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
constant c_ctrl_interval_size : natural := c_nof_clk_per_sync;
- constant c_percentage : real := 0.05; -- percentage that actual value may differ from expected value
- constant c_lo_factor : real := 1.0 - c_percentage; -- lower boundary
- constant c_hi_factor : real := 1.0 + c_percentage; -- higher boundary
+ -- percentage that actual value may differ from expected value
+ constant c_percentage : real := 0.05;
+ -- lower boundary
+ constant c_lo_factor : real := 1.0 - c_percentage;
+ -- higher boundary
+ constant c_hi_factor : real := 1.0 + c_percentage;
-- WG
- constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2; -- = 0.5 * FS, so in number of lsb
- constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
- constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := 2;
+ -- = 0.5 * FS, so in number of lsb
+ constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2;
+ -- in freq_unit
+ constant c_wg_freq_offset : real := 0.0 / 11.0;
+ -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ constant c_subband_sp_0 : real := 102.0;
constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_nof_clk_per_sync);
-- WPFB
- constant c_nof_pfb : natural := 1; -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
- constant c_wb_leakage_bin : natural := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor; -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
- constant c_exp_sp_subband_power_ratio : real := 1.0 / 8.0; -- depends on internal WPFB quantization and FIR coefficients
- constant c_exp_sp_subband_power_sum_ratio : real := c_exp_sp_subband_power_ratio; -- because all sinus power is expected in one subband
+ -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
+ constant c_nof_pfb : natural := 1;
+ -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
+ constant c_wb_leakage_bin : natural := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor;
+ -- depends on internal WPFB quantization and FIR coefficients
+ constant c_exp_sp_subband_power_ratio : real := 1.0 / 8.0;
+ -- because all sinus power is expected in one subband
+ constant c_exp_sp_subband_power_sum_ratio : real := c_exp_sp_subband_power_ratio;
constant c_exp_subband_power_sp_0 : real := c_exp_wg_power_sp_0 * c_exp_sp_subband_power_ratio;
type t_real_arr is array (integer range <>) of real;
@@ -154,16 +168,24 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -227,12 +249,14 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
variable v_sp_subband_power : real;
- variable v_W, v_C, v_A, v_X, v_B, v_A_even, v_B_even : natural; -- array indicies
+ -- array indicies
+ variable v_W, v_C, v_A, v_X, v_B, v_A_even, v_B_even : natural;
begin
-- Wait for DUT power up after reset
wait for 1 us;
@@ -241,9 +265,12 @@ begin
-- Enable BSN
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BSN at PPS
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BSN at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk);
-- Release PPS pulser, to get first PPS now and to start BSN source
wait for 1 us;
@@ -252,8 +279,10 @@ begin
----------------------------------------------------------------------------
-- Crosslets Info
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 0, integer(c_subband_sp_0), tb_clk); -- offset
- mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 15, 0 , tb_clk); -- stepsize
+ -- offset
+ mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 0, integer(c_subband_sp_0), tb_clk);
+ -- stepsize
+ mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 15, 0 , tb_clk);
----------------------------------------------------------------------------
-- Enable WG
@@ -264,10 +293,14 @@ begin
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
for I in 0 to c_sdp_S_pn - 1 loop
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk);
end loop;
-- Read current BSN
@@ -278,18 +311,26 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
-- bsn_scheduler_xsub
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_bsn_start_wg, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- assume v_bsn < 2**31-1
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable
+ -- Interval size
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk);
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_bsn_start_wg, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk);
+ -- enable
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk);
-- Wait for enough WG data and start of sync interval
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2,
c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
index 955572365e77b02697bb9109ae11fccf0bd528a7..8dbcba278097d336048845fdaabbdf49a99d8cc6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
@@ -60,17 +60,21 @@ architecture tb of tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload is
constant c_sim : boolean := true;
constant c_unb_nr : natural := 2;
constant c_node_nr : natural := 1;
- constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr * 4 + c_node_nr, 8); -- c_unb2b_board_nof_node = 4, c_unb2b_board_aux.id_w = 8
+ -- c_unb2b_board_nof_node = 4, c_unb2b_board_aux.id_w = 8
+ constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr * 4 + c_node_nr, 8);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
- constant c_nof_block_per_sync : natural := 16; -- long enough to stream out udp data
+ -- long enough to stream out udp data
+ constant c_nof_block_per_sync : natural := 16;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_pps_period : natural := c_nof_clk_per_sync;
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
@@ -89,12 +93,17 @@ architecture tb of tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload is
signal eth_done : std_logic := '0';
-- . 1GbE output
- constant c_eth_check_nof_packets : natural := 1; -- received packets in 1 sync period
- constant c_eth_header_size : natural := 19; -- words
- constant c_eth_crc_size : natural := 1; -- word
- constant c_eth_packet_size : natural := c_eth_header_size + c_eth_crc_size + (c_sdp_W_statistic / c_word_w) * c_sdp_S_pn * c_sdp_S_pn * c_nof_complex; -- 20 + 2 * 12 * 12 * 2 = 596
+ -- received packets in 1 sync period
+ constant c_eth_check_nof_packets : natural := 1;
+ -- words
+ constant c_eth_header_size : natural := 19;
+ -- word
+ constant c_eth_crc_size : natural := 1;
+ -- 20 + 2 * 12 * 12 * 2 = 596
+ constant c_eth_packet_size : natural := c_eth_header_size + c_eth_crc_size + (c_sdp_W_statistic / c_word_w) * c_sdp_S_pn * c_sdp_S_pn * c_nof_complex;
constant c_eth_check_nof_valid : natural := c_eth_check_nof_packets * c_eth_packet_size;
- constant c_eth_runtime_timeout : time := 3 * c_nof_clk_per_sync * c_ext_clk_period; -- eth statistics should be done at the third sync interval
+ -- eth statistics should be done at the third sync interval
+ constant c_eth_runtime_timeout : time := 3 * c_nof_clk_per_sync * c_ext_clk_period;
-- DUT
signal ext_clk : std_logic := '0';
@@ -126,17 +135,26 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -199,7 +217,8 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
begin
@@ -210,9 +229,12 @@ begin
-- Enable BSN
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk); -- Enable BSN immediately
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BSN immediately
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk);
-- Release PPS pulser, to get first PPS now and to start BSN source
wait for 1 us;
@@ -221,10 +243,14 @@ begin
----------------------------------------------------------------------------
-- Enable xsub
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_nof_block_per_sync, tb_clk); -- first write bsn low then bsn high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- bsn high, assume v_bsn < 2**31-1
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable
+ -- Interval size
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk);
+ -- first write bsn low then bsn high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_nof_block_per_sync, tb_clk);
+ -- bsn high, assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk);
+ -- enable
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk);
----------------------------------------------------------------------------
-- Offload enable
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
index 1cd39a4cd95fd46ed27f655314b2054711fd1046..bb3c45e536baf916288cb18bcdad75c662393e8c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2b_sdp_station_xsub_ring is
generic (
g_design_name : string := "lofar2_unb2b_sdp_station_xsub_ring";
g_design_note : string := "Lofar2 SDP station xsub_ring design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -72,7 +81,8 @@ entity lofar2_unb2b_sdp_station_xsub_ring is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP0 for Ring.
QSFP_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -85,18 +95,22 @@ entity lofar2_unb2b_sdp_station_xsub_ring is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (note only 6 are used in unb2b)
- BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0)
);
end lofar2_unb2b_sdp_station_xsub_ring;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
index 9e7401c049e4ad2d0100efebeca9f6cac2999df2..2f19514089fd56e590abfa4ae0e9c5239d6d0b43 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -66,7 +66,8 @@ end tb_lofar2_unb2b_sdp_station_xsub_ring;
architecture tb of tb_lofar2_unb2b_sdp_station_xsub_ring is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_nof_rn : natural := 2;
constant c_P_sq : natural := (c_nof_rn / 2) + 1;
@@ -74,12 +75,15 @@ architecture tb of tb_lofar2_unb2b_sdp_station_xsub_ring is
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
+ -- 644MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_nof_block_per_sync : natural := 24;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
@@ -87,23 +91,34 @@ architecture tb of tb_lofar2_unb2b_sdp_station_xsub_ring is
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
constant c_ctrl_interval_size : natural := c_nof_clk_per_sync;
- constant c_percentage : real := 0.05; -- percentage that actual value may differ from expected value
- constant c_lo_factor : real := 1.0 - c_percentage; -- lower boundary
- constant c_hi_factor : real := 1.0 + c_percentage; -- higher boundary
+ -- percentage that actual value may differ from expected value
+ constant c_percentage : real := 0.05;
+ -- lower boundary
+ constant c_lo_factor : real := 1.0 - c_percentage;
+ -- higher boundary
+ constant c_hi_factor : real := 1.0 + c_percentage;
constant c_nof_lanes : natural := 1;
-- WG
- constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2; -- = 0.5 * FS, so in number of lsb
- constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
- constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := 2;
+ -- = 0.5 * FS, so in number of lsb
+ constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2;
+ -- in freq_unit
+ constant c_wg_freq_offset : real := 0.0 / 11.0;
+ -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ constant c_subband_sp_0 : real := 102.0;
constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_nof_clk_per_sync);
-- WPFB
- constant c_nof_pfb : natural := 1; -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
- constant c_wb_leakage_bin : natural := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor; -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
- constant c_exp_sp_subband_power_ratio : real := 1.0 / 8.0; -- depends on internal WPFB quantization and FIR coefficients
- constant c_exp_sp_subband_power_sum_ratio : real := c_exp_sp_subband_power_ratio; -- because all sinus power is expected in one subband
+ -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
+ constant c_nof_pfb : natural := 1;
+ -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
+ constant c_wb_leakage_bin : natural := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor;
+ -- depends on internal WPFB quantization and FIR coefficients
+ constant c_exp_sp_subband_power_ratio : real := 1.0 / 8.0;
+ -- because all sinus power is expected in one subband
+ constant c_exp_sp_subband_power_sum_ratio : real := c_exp_sp_subband_power_ratio;
constant c_exp_subband_power_sp_0 : real := c_exp_wg_power_sp_0 * c_exp_sp_subband_power_ratio;
type t_real_arr is array (integer range <>) of real;
@@ -167,18 +182,28 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- SA_CLK <= not SA_CLK after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ SA_CLK <= not SA_CLK after c_sa_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -267,12 +292,14 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
variable v_sp_subband_power : real;
- variable v_W, v_C, v_A, v_X, v_B, v_A_even, v_B_even, v_SQ_offset: natural; -- array indicies
+ -- array indicies
+ variable v_W, v_C, v_A, v_X, v_B, v_A_even, v_B_even, v_SQ_offset: natural;
begin
-- Wait for DUT power up after reset
wait for 1 us;
@@ -282,9 +309,12 @@ begin
----------------------------------------------------------------------------
for RN in 0 to c_nof_rn - 1 loop
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SOURCE_V2", 3, 0, tb_clk);
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SOURCE_V2", 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SOURCE_V2", 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SOURCE_V2", 0, 16#00000003#, tb_clk); -- Enable BSN at PPS
+ -- Init BSN = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SOURCE_V2", 2, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SOURCE_V2", 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BSN at PPS
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SOURCE_V2", 0, 16#00000003#, tb_clk);
end loop;
-- Release PPS pulser, to get first PPS now and to start BSN source
@@ -297,17 +327,23 @@ begin
----------------------------------------------------------------------------
-- Write ring configuration to all nodes.
for RN in 0 to c_nof_rn - 1 loop
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_INFO", 2, c_nof_rn, tb_clk); -- N_rn
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_INFO", 3, 0, tb_clk); -- O_rn
+ -- N_rn
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_INFO", 2, c_nof_rn, tb_clk);
+ -- O_rn
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_INFO", 3, 0, tb_clk);
end loop;
-- Start node specific settings
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, 0) & "REG_RING_INFO", 0, 1, tb_clk); -- use_ring_to_previous_rn = 1
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, 0) & "REG_RING_INFO", 1, 0, tb_clk); -- use_ring_to_next_rn = 0
+ -- use_ring_to_previous_rn = 1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, 0) & "REG_RING_INFO", 0, 1, tb_clk);
+ -- use_ring_to_next_rn = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, 0) & "REG_RING_INFO", 1, 0, tb_clk);
-- End node specific settings
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + ((c_nof_rn - 1) / c_quad), (c_nof_rn - 1) mod c_quad) & "REG_RING_INFO", 0, 0, tb_clk); -- use_ring_to_previous_rn = 0
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + ((c_nof_rn - 1) / c_quad), (c_nof_rn - 1) mod c_quad) & "REG_RING_INFO", 1, 1, tb_clk); -- use_ring_to_next_rn = 1
+ -- use_ring_to_previous_rn = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + ((c_nof_rn - 1) / c_quad), (c_nof_rn - 1) mod c_quad) & "REG_RING_INFO", 0, 0, tb_clk);
+ -- use_ring_to_next_rn = 1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + ((c_nof_rn - 1) / c_quad), (c_nof_rn - 1) mod c_quad) & "REG_RING_INFO", 1, 1, tb_clk);
-- Access scheme 3. Each RN creates packets and sends them along the ring.
for RN in 0 to c_nof_rn - 1 loop
@@ -328,8 +364,10 @@ begin
----------------------------------------------------------------------------
-- Crosslets Info
----------------------------------------------------------------------------
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_CROSSLETS_INFO", 0, integer(c_subband_sp_0), tb_clk); -- offset
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_CROSSLETS_INFO", 15, 0 , tb_clk); -- stepsize
+ -- offset
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_CROSSLETS_INFO", 0, integer(c_subband_sp_0), tb_clk);
+ -- stepsize
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_CROSSLETS_INFO", 15, 0 , tb_clk);
end loop;
----------------------------------------------------------------------------
-- Enable WG
@@ -341,10 +379,14 @@ begin
-- 3 : ampl[16:0]
for RN in 0 to c_nof_rn - 1 loop
for I in 0 to c_sdp_S_pn - 1 loop
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_WG", I * 4 + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_WG", I * 4 + 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_WG", I * 4 + 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_WG", I * 4 + 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_WG", I * 4 + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_WG", I * 4 + 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_WG", I * 4 + 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_WG", I * 4 + 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk);
end loop;
end loop;
@@ -358,19 +400,27 @@ begin
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
for RN in 0 to c_nof_rn - 1 loop
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SCHEDULER", 0, c_bsn_start_wg, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SCHEDULER", 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SCHEDULER", 0, c_bsn_start_wg, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SCHEDULER", 1, 0, tb_clk);
-- bsn_scheduler_xsub
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SYNC_SCHEDULER_XSUB", 1, c_ctrl_interval_size, tb_clk); -- Interval size
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SYNC_SCHEDULER_XSUB", 2, c_bsn_start_wg, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SYNC_SCHEDULER_XSUB", 3, 0, tb_clk); -- assume v_bsn < 2**31-1
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SYNC_SCHEDULER_XSUB", 0, 1, tb_clk); -- enable
+ -- Interval size
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SYNC_SCHEDULER_XSUB", 1, c_ctrl_interval_size, tb_clk);
+ -- first write low then high part
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SYNC_SCHEDULER_XSUB", 2, c_bsn_start_wg, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SYNC_SCHEDULER_XSUB", 3, 0, tb_clk);
+ -- enable
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SYNC_SCHEDULER_XSUB", 0, 1, tb_clk);
end loop;
-- Wait for enough WG data and start of sync interval
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2,
c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
@@ -381,7 +431,8 @@ begin
for I in 0 to c_nof_complex * c_sdp_X_sq * (c_longword_sz / c_word_sz) - 1 loop
v_W := I mod 2;
v_B := I / 2;
- v_SQ_offset := 2**ceil_log2(c_sdp_N_crosslets_max * c_nof_complex * c_sdp_X_sq * (c_longword_sz / c_word_sz)); -- Address offset for next P_sq.
+ -- Address offset for next P_sq.
+ v_SQ_offset := 2**ceil_log2(c_sdp_N_crosslets_max * c_nof_complex * c_sdp_X_sq * (c_longword_sz / c_word_sz));
if v_W = 0 then
-- low part
mmf_mm_bus_rd(c_mm_file_ram_st_xsq, v_SQ_offset + I, rd_data, tb_clk);
@@ -443,31 +494,44 @@ begin
-- Reporting BSN monitors of the bsn_align_v2
----------------------------------------------------------------------------
for RN in 0 to c_nof_rn - 1 loop
- for J in 0 to c_P_sq - 1 loop -- bsn_monitor index
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 0, rd_data, tb_clk); -- status bits
+ -- bsn_monitor index
+ for J in 0 to c_P_sq - 1 loop
+ -- status bits
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 0, rd_data, tb_clk);
report "sync_timeout = " & integer'image(TO_UINT(rd_data(2 downto 2))) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 1, rd_data, tb_clk); -- bsn at sync
+ -- bsn at sync
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 1, rd_data, tb_clk);
report "bsn_at_sync = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 3, rd_data, tb_clk); -- nof_sop
+ -- nof_sop
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 3, rd_data, tb_clk);
report "nof_sop = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 4, rd_data, tb_clk); -- nof_valid
+ -- nof_valid
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 4, rd_data, tb_clk);
report "nof_valid = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 5, rd_data, tb_clk); -- nof_err
+ -- nof_err
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 5, rd_data, tb_clk);
report "nof_err = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 6, rd_data, tb_clk); -- latency
+ -- latency
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 6, rd_data, tb_clk);
report "latency = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
end loop;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 0, rd_data, tb_clk); -- status bits
+ -- status bits
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 0, rd_data, tb_clk);
report "sync_timeout = " & integer'image(TO_UINT(rd_data(2 downto 2))) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 1, rd_data, tb_clk); -- bsn at sync
+ -- bsn at sync
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 1, rd_data, tb_clk);
report "bsn_at_sync = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 3, rd_data, tb_clk); -- nof_sop
+ -- nof_sop
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 3, rd_data, tb_clk);
report "nof_sop = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 4, rd_data, tb_clk); -- nof_valid
+ -- nof_valid
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 4, rd_data, tb_clk);
report "nof_valid = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 5, rd_data, tb_clk); -- nof_err
+ -- nof_err
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 5, rd_data, tb_clk);
report "nof_err = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 6, rd_data, tb_clk); -- latency
+ -- latency
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 6, rd_data, tb_clk);
report "latency = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
end loop;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index f4947909cf7154cc6ba578469c7455de0f72074e..1082fe2ba75d81abd32f62f07ed08659fd651d5d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -46,26 +46,36 @@ entity lofar2_unb2b_sdp_station is
generic (
g_design_name : string := "lofar2_unb2b_sdp_station";
g_design_note : string := "UNUSED";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := false;
g_protect_addr_range : boolean := false;
g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
g_wpfb_complex : t_wpfb := c_sdp_wpfb_complex_subbands;
- g_bsn_nof_clk_per_sync : natural := c_sdp_N_clk_per_sync; -- Default 200M, overide for short simulation
+ -- Default 200M, overide for short simulation
+ g_bsn_nof_clk_per_sync : natural := c_sdp_N_clk_per_sync;
g_scope_selected_subband : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -86,7 +96,8 @@ entity lofar2_unb2b_sdp_station is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP0 for Ring.
QSFP_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -99,19 +110,23 @@ entity lofar2_unb2b_sdp_station is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (Note: numbered from 0)
- JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0) := (others => '0'); -- c_sdp_S_pn = 12, c_unb2b_board_nof_tr_jesd204b = 6
+ -- c_sdp_S_pn = 12, c_unb2b_board_nof_tr_jesd204b = 6
+ JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0) := (others => '0');
-- Connect to the BCK_RX pins in the top wrapper
- JESD204B_REFCLK : in std_logic := '0'; -- Connect to BCK_REF_CLK pin in the top level wrapper
+ -- Connect to BCK_REF_CLK pin in the top level wrapper
+ JESD204B_REFCLK : in std_logic := '0';
-- jesd204b syncronization signals
JESD204B_SYSREF : in std_logic := '0';
- JESD204B_SYNC_N : out std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0) -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0)
);
end lofar2_unb2b_sdp_station;
@@ -173,12 +188,16 @@ architecture str of lofar2_unb2b_sdp_station is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_copi : t_mem_copi := c_mem_copi_rst; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_copi : t_mem_copi := c_mem_copi_rst;
signal eth1g_tse_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal eth1g_reg_copi : t_mem_copi := c_mem_copi_rst; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_copi : t_mem_copi := c_mem_copi_rst;
signal eth1g_reg_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_copi : t_mem_copi := c_mem_copi_rst; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_copi : t_mem_copi := c_mem_copi_rst;
signal eth1g_ram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS read
@@ -515,7 +534,8 @@ begin
mm_rst => mm_rst,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ -- Can be external 200MHz, or PLL generated
+ dp_clk => dp_clk,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
@@ -1034,7 +1054,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index 194e3ee4180e6c18c5a5c68184ba85ad7d511c58..6a8f471e3a6af5bd8254b7de80d9b4b2746d5600 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -32,7 +32,8 @@ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2b_sdp_station is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 5b73786a9702555b039c255550f2cb477f20c68f..91af44a30ef0504b3c033038e09edbc4a3f027ec 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -27,553 +27,1100 @@ package qsys_lofar2_unb2b_sdp_station_pkg is
-----------------------------------------------------------------------------
component qsys_lofar2_unb2b_sdp_station is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_cross_clk_export : out std_logic; -- export
- ram_equalizer_gains_cross_read_export : out std_logic; -- export
- ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_cross_reset_export : out std_logic; -- export
- ram_equalizer_gains_cross_write_export : out std_logic; -- export
- ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
- ram_st_histogram_clk_export : out std_logic; -- export
- ram_st_histogram_read_export : out std_logic; -- export
- ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_histogram_reset_export : out std_logic; -- export
- ram_st_histogram_write_export : out std_logic; -- export
- ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
- ram_st_xsq_clk_export : out std_logic; -- export
- ram_st_xsq_read_export : out std_logic; -- export
- ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_xsq_reset_export : out std_logic; -- export
- ram_st_xsq_write_export : out std_logic; -- export
- ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
- reg_bsn_align_v2_bf_read_export : out std_logic; -- export
- reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
- reg_bsn_align_v2_bf_write_export : out std_logic; -- export
- reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_crosslets_info_clk_export : out std_logic; -- export
- reg_crosslets_info_read_export : out std_logic; -- export
- reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_reset_export : out std_logic; -- export
- reg_crosslets_info_write_export : out std_logic; -- export
- reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nof_crosslets_clk_export : out std_logic; -- export
- reg_nof_crosslets_read_export : out std_logic; -- export
- reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nof_crosslets_reset_export : out std_logic; -- export
- reg_nof_crosslets_write_export : out std_logic; -- export
- reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_lane_info_bf_clk_export : out std_logic; -- export
- reg_ring_lane_info_bf_read_export : out std_logic; -- export
- reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_bf_reset_export : out std_logic; -- export
- reg_ring_lane_info_bf_write_export : out std_logic; -- export
- reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ring_lane_info_xst_clk_export : out std_logic; -- export
- reg_ring_lane_info_xst_read_export : out std_logic; -- export
- reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_xst_reset_export : out std_logic; -- export
- reg_ring_lane_info_xst_write_export : out std_logic; -- export
- reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_stat_enable_bst_clk_export : out std_logic; -- export
- reg_stat_enable_bst_read_export : out std_logic; -- export
- reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_bst_reset_export : out std_logic; -- export
- reg_stat_enable_bst_write_export : out std_logic; -- export
- reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_sst_clk_export : out std_logic; -- export
- reg_stat_enable_sst_read_export : out std_logic; -- export
- reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_sst_reset_export : out std_logic; -- export
- reg_stat_enable_sst_write_export : out std_logic; -- export
- reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_xst_clk_export : out std_logic; -- export
- reg_stat_enable_xst_read_export : out std_logic; -- export
- reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_xst_reset_export : out std_logic; -- export
- reg_stat_enable_xst_write_export : out std_logic; -- export
- reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- export
+ jesd204b_address_export : out std_logic_vector(11 downto 0);
+ -- export
+ jesd204b_clk_export : out std_logic;
+ -- export
+ jesd204b_read_export : out std_logic;
+ -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ jesd204b_reset_export : out std_logic;
+ -- export
+ jesd204b_write_export : out std_logic;
+ -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_jesd_ctrl_clk_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_read_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_jesd_ctrl_reset_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_write_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0);
+ -- export
+ ram_bf_weights_clk_export : out std_logic;
+ -- export
+ ram_bf_weights_read_export : out std_logic;
+ -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_bf_weights_reset_export : out std_logic;
+ -- export
+ ram_bf_weights_write_export : out std_logic;
+ -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0);
+ -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_equalizer_gains_clk_export : out std_logic;
+ -- export
+ ram_equalizer_gains_read_export : out std_logic;
+ -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_equalizer_gains_reset_export : out std_logic;
+ -- export
+ ram_equalizer_gains_write_export : out std_logic;
+ -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_equalizer_gains_cross_clk_export : out std_logic;
+ -- export
+ ram_equalizer_gains_cross_read_export : out std_logic;
+ -- export
+ ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_equalizer_gains_cross_reset_export : out std_logic;
+ -- export
+ ram_equalizer_gains_cross_write_export : out std_logic;
+ -- export
+ ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_fil_coefs_address_export : out std_logic_vector(14 downto 0);
+ -- export
+ ram_fil_coefs_clk_export : out std_logic;
+ -- export
+ ram_fil_coefs_read_export : out std_logic;
+ -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_fil_coefs_reset_export : out std_logic;
+ -- export
+ ram_fil_coefs_write_export : out std_logic;
+ -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0);
+ -- export
+ ram_scrap_clk_export : out std_logic;
+ -- export
+ ram_scrap_read_export : out std_logic;
+ -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_scrap_reset_export : out std_logic;
+ -- export
+ ram_scrap_write_export : out std_logic;
+ -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_ss_ss_wide_clk_export : out std_logic;
+ -- export
+ ram_ss_ss_wide_read_export : out std_logic;
+ -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_ss_ss_wide_reset_export : out std_logic;
+ -- export
+ ram_ss_ss_wide_write_export : out std_logic;
+ -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0);
+ -- export
+ ram_st_bst_clk_export : out std_logic;
+ -- export
+ ram_st_bst_read_export : out std_logic;
+ -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_st_bst_reset_export : out std_logic;
+ -- export
+ ram_st_bst_write_export : out std_logic;
+ -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ ram_st_histogram_clk_export : out std_logic;
+ -- export
+ ram_st_histogram_read_export : out std_logic;
+ -- export
+ ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_st_histogram_reset_export : out std_logic;
+ -- export
+ ram_st_histogram_write_export : out std_logic;
+ -- export
+ ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_st_sst_address_export : out std_logic_vector(14 downto 0);
+ -- export
+ ram_st_sst_clk_export : out std_logic;
+ -- export
+ ram_st_sst_read_export : out std_logic;
+ -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_st_sst_reset_export : out std_logic;
+ -- export
+ ram_st_sst_write_export : out std_logic;
+ -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_st_xsq_address_export : out std_logic_vector(15 downto 0);
+ -- export
+ ram_st_xsq_clk_export : out std_logic;
+ -- export
+ ram_st_xsq_read_export : out std_logic;
+ -- export
+ ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_st_xsq_reset_export : out std_logic;
+ -- export
+ ram_st_xsq_write_export : out std_logic;
+ -- export
+ ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_wg_clk_export : out std_logic;
+ -- export
+ ram_wg_read_export : out std_logic;
+ -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_wg_reset_export : out std_logic;
+ -- export
+ ram_wg_write_export : out std_logic;
+ -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_aduh_monitor_clk_export : out std_logic;
+ -- export
+ reg_aduh_monitor_read_export : out std_logic;
+ -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_aduh_monitor_reset_export : out std_logic;
+ -- export
+ reg_aduh_monitor_write_export : out std_logic;
+ -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_bf_scale_clk_export : out std_logic;
+ -- export
+ reg_bf_scale_read_export : out std_logic;
+ -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bf_scale_reset_export : out std_logic;
+ -- export
+ reg_bf_scale_write_export : out std_logic;
+ -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_bsn_align_v2_bf_clk_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_bf_read_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_align_v2_bf_reset_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_bf_write_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_bsn_align_v2_xsub_clk_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_xsub_read_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_align_v2_xsub_reset_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_xsub_write_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0);
+ -- export
+ reg_bsn_monitor_input_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_input_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_bst_offload_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_bst_offload_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_sst_offload_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_sst_offload_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_xst_offload_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_xst_offload_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_bsn_scheduler_clk_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_read_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_scheduler_reset_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_write_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_bsn_source_v2_clk_export : out std_logic;
+ -- export
+ reg_bsn_source_v2_read_export : out std_logic;
+ -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_source_v2_reset_export : out std_logic;
+ -- export
+ reg_bsn_source_v2_write_export : out std_logic;
+ -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic;
+ -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic;
+ -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic;
+ -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic;
+ -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_crosslets_info_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_crosslets_info_clk_export : out std_logic;
+ -- export
+ reg_crosslets_info_read_export : out std_logic;
+ -- export
+ reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_crosslets_info_reset_export : out std_logic;
+ -- export
+ reg_crosslets_info_write_export : out std_logic;
+ -- export
+ reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_dp_block_validate_err_bf_clk_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_bf_read_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_block_validate_err_bf_reset_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_bf_write_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_dp_block_validate_err_xst_clk_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_xst_read_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_block_validate_err_xst_reset_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_xst_write_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dp_selector_clk_export : out std_logic;
+ -- export
+ reg_dp_selector_read_export : out std_logic;
+ -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_selector_reset_export : out std_logic;
+ -- export
+ reg_dp_selector_write_export : out std_logic;
+ -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_dp_shiftram_clk_export : out std_logic;
+ -- export
+ reg_dp_shiftram_read_export : out std_logic;
+ -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_shiftram_reset_export : out std_logic;
+ -- export
+ reg_dp_shiftram_write_export : out std_logic;
+ -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_dp_xonoff_clk_export : out std_logic;
+ -- export
+ reg_dp_xonoff_read_export : out std_logic;
+ -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_xonoff_reset_export : out std_logic;
+ -- export
+ reg_dp_xonoff_write_export : out std_logic;
+ -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_hdr_dat_clk_export : out std_logic;
+ -- export
+ reg_hdr_dat_read_export : out std_logic;
+ -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_hdr_dat_reset_export : out std_logic;
+ -- export
+ reg_hdr_dat_write_export : out std_logic;
+ -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_nof_crosslets_clk_export : out std_logic;
+ -- export
+ reg_nof_crosslets_read_export : out std_logic;
+ -- export
+ reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_nof_crosslets_reset_export : out std_logic;
+ -- export
+ reg_nof_crosslets_write_export : out std_logic;
+ -- export
+ reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic;
+ -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic;
+ -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic;
+ -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic;
+ -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic;
+ -- export
+ reg_nw_10gbe_mac_read_export : out std_logic;
+ -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic;
+ -- export
+ reg_nw_10gbe_mac_write_export : out std_logic;
+ -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_ring_info_clk_export : out std_logic;
+ -- export
+ reg_ring_info_read_export : out std_logic;
+ -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_ring_info_reset_export : out std_logic;
+ -- export
+ reg_ring_info_write_export : out std_logic;
+ -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_ring_lane_info_bf_clk_export : out std_logic;
+ -- export
+ reg_ring_lane_info_bf_read_export : out std_logic;
+ -- export
+ reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_ring_lane_info_bf_reset_export : out std_logic;
+ -- export
+ reg_ring_lane_info_bf_write_export : out std_logic;
+ -- export
+ reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_ring_lane_info_xst_clk_export : out std_logic;
+ -- export
+ reg_ring_lane_info_xst_read_export : out std_logic;
+ -- export
+ reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_ring_lane_info_xst_reset_export : out std_logic;
+ -- export
+ reg_ring_lane_info_xst_write_export : out std_logic;
+ -- export
+ reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_sdp_info_clk_export : out std_logic;
+ -- export
+ reg_sdp_info_read_export : out std_logic;
+ -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_sdp_info_reset_export : out std_logic;
+ -- export
+ reg_sdp_info_write_export : out std_logic;
+ -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_si_clk_export : out std_logic;
+ -- export
+ reg_si_read_export : out std_logic;
+ -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_si_reset_export : out std_logic;
+ -- export
+ reg_si_write_export : out std_logic;
+ -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_stat_enable_bst_clk_export : out std_logic;
+ -- export
+ reg_stat_enable_bst_read_export : out std_logic;
+ -- export
+ reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stat_enable_bst_reset_export : out std_logic;
+ -- export
+ reg_stat_enable_bst_write_export : out std_logic;
+ -- export
+ reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_stat_enable_sst_clk_export : out std_logic;
+ -- export
+ reg_stat_enable_sst_read_export : out std_logic;
+ -- export
+ reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stat_enable_sst_reset_export : out std_logic;
+ -- export
+ reg_stat_enable_sst_write_export : out std_logic;
+ -- export
+ reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_stat_enable_xst_clk_export : out std_logic;
+ -- export
+ reg_stat_enable_xst_read_export : out std_logic;
+ -- export
+ reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stat_enable_xst_reset_export : out std_logic;
+ -- export
+ reg_stat_enable_xst_write_export : out std_logic;
+ -- export
+ reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_stat_hdr_dat_bst_clk_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_bst_read_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stat_hdr_dat_bst_reset_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_bst_write_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_stat_hdr_dat_sst_clk_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_sst_read_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stat_hdr_dat_sst_reset_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_sst_write_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_stat_hdr_dat_xst_clk_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_xst_read_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stat_hdr_dat_xst_reset_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_xst_write_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0);
+ -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_read_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_write_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic;
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_wg_clk_export : out std_logic;
+ -- export
+ reg_wg_read_export : out std_logic;
+ -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wg_reset_export : out std_logic;
+ -- export
+ reg_wg_write_export : out std_logic;
+ -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0)
);
end component qsys_lofar2_unb2b_sdp_station;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
index a057ddef1ed45cbf28976e972f10acd299a5b213..9f82d3876e8b72377f855ca81065592a7b344da0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
@@ -51,16 +51,19 @@ end tb_lofar2_unb2b_sdp_station;
architecture tb of tb_lofar2_unb2b_sdp_station is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_nof_block_per_sync : natural := 16;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
@@ -68,9 +71,12 @@ architecture tb of tb_lofar2_unb2b_sdp_station is
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
-- WG
- constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2; -- = 0.5 * FS, so in number of lsb
- constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := 2;
+ -- = 0.5 * FS, so in number of lsb
+ constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2;
+ -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ constant c_subband_sp_0 : real := 102.0;
-- . 1GbE output
constant c_eth_check_nof_packets : natural := 1;
@@ -121,17 +127,26 @@ architecture tb of tb_lofar2_unb2b_sdp_station is
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
begin
-- System setup
- ext_clk <= (not ext_clk) or tb_end after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= (not eth_clk) or tb_end after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= (not JESD204B_REFCLK) or tb_end after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= (not ext_clk) or tb_end after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= (not eth_clk) or tb_end after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= (not JESD204B_REFCLK) or tb_end after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
-- External PPS
proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
@@ -190,7 +205,8 @@ begin
---------------------------------------------------------------------------------------------------------------------
-- Stimuli
-- MM slave accesses via file IO
- tb_clk <= (not tb_clk) or tb_end after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= (not tb_clk) or tb_end after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
@@ -202,9 +218,12 @@ begin
-- Enable BS
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 1, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 1, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk);
-- Enable WG
-- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3)
@@ -212,10 +231,14 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer(c_subband_sp_0 * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer(c_subband_sp_0 * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk);
-- Read current BSN
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 downto 0), tb_clk);
@@ -226,8 +249,10 @@ begin
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
v_bsn := c_bsn_start_wg;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
-- Wait for ADUH monitor to have filled with WG data
wait for c_sdp_T_sub * c_sdp_N_taps;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
index 1556515bae9a2a48edf9c1abafa56ba96312953a..0f1081922733c42627020f4575086ef3ec8deede 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
@@ -37,22 +37,31 @@ entity lofar2_unb2c_ddrctrl is
g_design_name : string := "lofar2_unb2c_ddrctrl";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e2sg;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision id -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision id -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := false;
g_protect_addr_range: boolean := false
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -67,7 +76,8 @@ entity lofar2_unb2c_ddrctrl is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic := '0'; -- Reference clock for MB_I
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic := '0';
--MB_II_REF_CLK : IN STD_LOGIC := '0'; -- Reference clock for MB_II
-- SO-DIMM Memory Bank I
@@ -95,8 +105,10 @@ architecture str of lofar2_unb2c_ddrctrl is
-- wg_wideband_arr
constant c_wg_buf_directory : string := "data/";
- constant c_wg_buf_dat_w : natural := 18; -- default value of WG that fits 14 bits of ADC data
- constant c_wg_buf_addr_w : natural := 10; -- default value of WG for 1024 samples
+ -- default value of WG that fits 14 bits of ADC data
+ constant c_wg_buf_dat_w : natural := 18;
+ -- default value of WG for 1024 samples
+ constant c_wg_buf_addr_w : natural := 10;
constant c_bsn_nof_clk_per_sync : natural := sel_a_b(g_sim, 16 * c_bs_block_size, c_sdp_N_clk_per_sync);
-- ddrctrl
@@ -147,12 +159,16 @@ architecture str of lofar2_unb2c_ddrctrl is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -296,7 +312,8 @@ begin
dp_rst => st_rst,
dp_clk => st_clk,
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ -- only uses eop (= block sync), bsn[]
+ snk_in => bs_sosi,
trigger_out => trigger_wg
);
@@ -719,7 +736,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
index bc7d3e754784cf6a70dbd23d2c0ec3c2f91c8c01..1e4155a9d72345011a5f640564873690f47d4dd7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
@@ -32,7 +32,8 @@ use work.qsys_lofar2_unb2c_ddrctrl_pkg.all;
entity mmm_lofar2_unb2c_ddrctrl is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
index aa9cb7c67cda243aa068f6502e8a4471b38a6cee..0ba53c409a7e2e085c1941ec85ddb35d534a0251 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
@@ -29,182 +29,357 @@ package qsys_lofar2_unb2c_ddrctrl_pkg is
component qsys_lofar2_unb2c_ddrctrl is
port (
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bsn_buf_reset_export : out std_logic; -- export
- ram_bsn_buf_clk_export : out std_logic; -- export
- ram_bsn_buf_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bsn_buf_write_export : out std_logic; -- export
- ram_bsn_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bsn_buf_read_export : out std_logic; -- export
- ram_bsn_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_data_buf_reset_export : out std_logic; -- export
- ram_data_buf_clk_export : out std_logic; -- export
- ram_data_buf_address_export : out std_logic_vector(13 downto 0); -- export
- ram_data_buf_write_export : out std_logic; -- export
- ram_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_data_buf_read_export : out std_logic; -- export
- ram_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_wideband_arr_reset_export : out std_logic; -- export
- ram_wg_wideband_arr_clk_export : out std_logic; -- export
- ram_wg_wideband_arr_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_wideband_arr_write_export : out std_logic; -- export
- ram_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_wideband_arr_read_export : out std_logic; -- export
- ram_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stop_in_reset_export : out std_logic; -- export
- reg_stop_in_clk_export : out std_logic; -- export
- reg_stop_in_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stop_in_write_export : out std_logic; -- export
- reg_stop_in_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stop_in_read_export : out std_logic; -- export
- reg_stop_in_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_reset_export : out std_logic; -- export
- reg_io_ddr_clk_export : out std_logic; -- export
- reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
- reg_io_ddr_write_export : out std_logic; -- export
- reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_read_export : out std_logic; -- export
- reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_wideband_arr_reset_export : out std_logic; -- export
- reg_wg_wideband_arr_clk_export : out std_logic; -- export
- reg_wg_wideband_arr_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_wideband_arr_write_export : out std_logic; -- export
- reg_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_wideband_arr_read_export : out std_logic; -- export
- reg_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ddrctrl_ctrl_state_reset_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_clk_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ddrctrl_ctrl_state_write_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_ddrctrl_ctrl_state_read_export : out std_logic; -- export
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ ram_bsn_buf_reset_export : out std_logic;
+ -- export
+ ram_bsn_buf_clk_export : out std_logic;
+ -- export
+ ram_bsn_buf_address_export : out std_logic_vector(14 downto 0);
+ -- export
+ ram_bsn_buf_write_export : out std_logic;
+ -- export
+ ram_bsn_buf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_bsn_buf_read_export : out std_logic;
+ -- export
+ ram_bsn_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_data_buf_reset_export : out std_logic;
+ -- export
+ ram_data_buf_clk_export : out std_logic;
+ -- export
+ ram_data_buf_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_data_buf_write_export : out std_logic;
+ -- export
+ ram_data_buf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_data_buf_read_export : out std_logic;
+ -- export
+ ram_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_scrap_reset_export : out std_logic;
+ -- export
+ ram_scrap_clk_export : out std_logic;
+ -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0);
+ -- export
+ ram_scrap_write_export : out std_logic;
+ -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_scrap_read_export : out std_logic;
+ -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_wg_wideband_arr_reset_export : out std_logic;
+ -- export
+ ram_wg_wideband_arr_clk_export : out std_logic;
+ -- export
+ ram_wg_wideband_arr_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_wg_wideband_arr_write_export : out std_logic;
+ -- export
+ ram_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_wg_wideband_arr_read_export : out std_logic;
+ -- export
+ ram_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_scheduler_reset_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_clk_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_bsn_scheduler_write_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_scheduler_read_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_source_v2_reset_export : out std_logic;
+ -- export
+ reg_bsn_source_v2_clk_export : out std_logic;
+ -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_bsn_source_v2_write_export : out std_logic;
+ -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_source_v2_read_export : out std_logic;
+ -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stop_in_reset_export : out std_logic;
+ -- export
+ reg_stop_in_clk_export : out std_logic;
+ -- export
+ reg_stop_in_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_stop_in_write_export : out std_logic;
+ -- export
+ reg_stop_in_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stop_in_read_export : out std_logic;
+ -- export
+ reg_stop_in_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_io_ddr_reset_export : out std_logic;
+ -- export
+ reg_io_ddr_clk_export : out std_logic;
+ -- export
+ reg_io_ddr_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_io_ddr_write_export : out std_logic;
+ -- export
+ reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_io_ddr_read_export : out std_logic;
+ -- export
+ reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wg_wideband_arr_reset_export : out std_logic;
+ -- export
+ reg_wg_wideband_arr_clk_export : out std_logic;
+ -- export
+ reg_wg_wideband_arr_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_wg_wideband_arr_write_export : out std_logic;
+ -- export
+ reg_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wg_wideband_arr_read_export : out std_logic;
+ -- export
+ reg_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_ddrctrl_ctrl_state_reset_export : out std_logic;
+ -- export
+ reg_ddrctrl_ctrl_state_clk_export : out std_logic;
+ -- export
+ reg_ddrctrl_ctrl_state_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_ddrctrl_ctrl_state_write_export : out std_logic;
+ -- export
+ reg_ddrctrl_ctrl_state_writedata_export: out std_logic_vector(31 downto 0);
+ -- export
+ reg_ddrctrl_ctrl_state_read_export : out std_logic;
reg_ddrctrl_ctrl_state_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X')
);
end component qsys_lofar2_unb2c_ddrctrl;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
index 2e4ac9d8d868dd53538e960a49ef02807376189c..fe2b83bc73df1e17f49315725c30f3422656af5d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
@@ -60,8 +60,10 @@ use mm_lib.mm_file_unb_pkg.all;
entity tb_lofar2_unb2c_ddrctrl is
generic (
g_design_name : string := "lofar2_unb2c_ddrctrl";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Node 3
+ g_sim_node_nr : natural := 3
);
end tb_lofar2_unb2c_ddrctrl;
@@ -69,18 +71,24 @@ architecture tb of tb_lofar2_unb2c_ddrctrl is
constant c_sim : boolean := true;
constant c_rd_data_w : natural := 32;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb2c_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2c_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoardi
- constant c_st_clk_period : time := 5 ns; -- 200 MHz st clk
- constant c_tb_clk_period : time := 1 ns; -- 1000 MHz tb clk
- constant c_mm_clk_period : time := 10 ns; -- 100 MHz mm clk
+ -- 125 MHz XO on UniBoardi
+ constant c_eth_clk_period : time := 8 ns;
+ -- 200 MHz st clk
+ constant c_st_clk_period : time := 5 ns;
+ -- 1000 MHz tb clk
+ constant c_tb_clk_period : time := 1 ns;
+ -- 100 MHz mm clk
+ constant c_mm_clk_period : time := 10 ns;
constant c_pps_period : natural := 1000;
constant c_mm_file_reg_bsn_source_v2 : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
@@ -97,29 +105,39 @@ architecture tb of tb_lofar2_unb2c_ddrctrl is
-- c_check_vector
constant c_tech_ddr : t_c_tech_ddr := c_tech_ddr4_sim_16k;
- constant c_ctrl_data_w : natural := func_tech_ddr_ctlr_data_w(c_tech_ddr); -- 576
- constant c_adr_w : natural := func_tech_ddr_ctlr_address_w(c_tech_ddr); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
- constant c_max_adr : natural := 2**(c_adr_w) - 1; -- the maximal address that is possible within the address vector length
+ -- 576
+ constant c_ctrl_data_w : natural := func_tech_ddr_ctlr_data_w(c_tech_ddr);
+ -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
+ constant c_adr_w : natural := func_tech_ddr_ctlr_address_w(c_tech_ddr);
+ -- the maximal address that is possible within the address vector length
+ constant c_max_adr : natural := 2**(c_adr_w) - 1;
constant c_block_size : natural := 1024;
constant c_nof_streams : natural := 12;
constant c_data_w : natural := 14;
- constant c_bim : natural := (c_max_adr * c_ctrl_data_w) / (c_block_size * c_nof_streams * c_data_w); -- the amount of whole blocks that fit in memory.
+ -- the amount of whole blocks that fit in memory.
+ constant c_bim : natural := (c_max_adr * c_ctrl_data_w) / (c_block_size * c_nof_streams * c_data_w);
constant c_nof_st_in_mem : natural := c_bim * c_block_size;
- constant c_check_vector : std_logic_vector(c_ctrl_data_w * c_bim * c_block_size-1 downto 0) := (others => '0'); -- the sinewave of one stream for c_bim length
+ -- the sinewave of one stream for c_bim length
+ constant c_check_vector : std_logic_vector(c_ctrl_data_w * c_bim * c_block_size-1 downto 0) := (others => '0');
-- BSN
- constant c_init_bsn : natural := 17; -- some recognizable value >= 0
+ -- some recognizable value >= 0
+ constant c_init_bsn : natural := 17;
constant c_nof_block_per_sync : natural := 16;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_speed : natural := 4;
-- WG
- constant c_wg_phase : real := 0.0; -- WG phase in degrees
- constant c_wg_freq : real := 160.0; -- WG freq
- constant c_wg_ampl : natural := natural(1.0 * real(c_sdp_FS_adc)); -- in number of lsb
- constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ -- WG phase in degrees
+ constant c_wg_phase : real := 0.0;
+ -- WG freq
+ constant c_wg_freq : real := 160.0;
+ -- in number of lsb
+ constant c_wg_ampl : natural := natural(1.0 * real(c_sdp_FS_adc));
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := c_init_bsn + 2;
constant c_subband : real := 1.0 * (2**c_speed);
-- DUT
@@ -156,11 +174,15 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- st_clk <= not st_clk or tb_end after c_st_clk_period / 2; -- External clock (200 MHz)
- eth_clk(0) <= not eth_clk(0) or tb_end after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
+ -- External clock (200 MHz)
+ st_clk <= not st_clk or tb_end after c_st_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk(0) <= not eth_clk(0) or tb_end after c_eth_clk_period / 2;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -214,7 +236,8 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk or tb_end after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk or tb_end after c_tb_clk_period / 2;
p_mm_stimuli : process
@@ -224,10 +247,14 @@ begin
----------------------------------------------------------------------------
-- Enable BSN
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk); -- Init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk); -- Write high part activates the init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BSN at PPS
+ -- Init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk);
+ -- Write high part activates the init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BSN at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk);
--mmf_mm_bus_rd(c_mm_file_reg_dp_selector, 0, rd_data, tb_clk);
@@ -241,10 +268,14 @@ begin
-- 3 : ampl[16:0]
for I in 0 to c_nof_streams - 1 loop
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I * 4) + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I * 4) + 1, integer(c_wg_phase), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I * 4) + 2, integer(real(c_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I * 4) + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I * 4) + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I * 4) + 1, integer(c_wg_phase), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I * 4) + 2, integer(real(c_subband) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I * 4) + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk);
end loop;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
-- Read current BSN
@@ -255,8 +286,10 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & natural'image(v_bsn) & " > " & natural'image(c_bsn_start_wg) severity ERROR;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
-----------------------------------------------------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
index e8ebe5092ffb6baf376b6bf33af2e15c31ae5968..40d6c175aef5600f469299f93c9aee1f0ee47661 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2c_filterbank_full is
generic (
g_design_name : string := "lofar2_unb2c_filterbank_full";
g_design_note : string := "Lofar2 filterbank with all streams";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -68,15 +77,18 @@ entity lofar2_unb2c_filterbank_full is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGIN : in std_logic; -- STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : out std_logic; -- STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ -- STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : in std_logic;
+ -- STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : out std_logic;
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- back transceivers (note only 6 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b - 1 downto c_unb2c_board_nof_tr_jesd204b);
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
index 82942a08d3a10ab712f640a73207bcb9a7d7d6b1..19c4d53811f3fbe1ee0c762d271aea8ee901370e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2c_filterbank_full_256MHz is
generic (
g_design_name : string := "lofar2_unb2c_filterbank_full_256MHz";
g_design_note : string := "Lofar2 filterbank with all streams on 256MHz ext clk";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -68,15 +77,18 @@ entity lofar2_unb2c_filterbank_full_256MHz is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGIN : in std_logic; -- _VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : out std_logic; -- _VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ -- _VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : in std_logic;
+ -- _VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : out std_logic;
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- back transceivers (note only 6 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b - 1 downto c_unb2c_board_nof_tr_jesd204b);
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : in std_logic;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
index a8ae459ab259b858a1f6e7a89ff8c8a4f60bdde6..4a87c3422bbbabdfc1ee5bd7376fae6243fc4553 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
@@ -44,13 +44,17 @@ entity lofar2_unb2c_filterbank is
g_design_name : string := "lofar2_unb2c_filterbank";
g_design_note : string := "UNUSED";
g_buf_nof_data : natural := 1024;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_sim_model_ddr : boolean := false;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := false;
g_protect_addr_range : boolean := false;
g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
@@ -58,11 +62,16 @@ entity lofar2_unb2c_filterbank is
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -79,8 +88,10 @@ entity lofar2_unb2c_filterbank is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGIN : in std_logic; -- STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : out std_logic; -- STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ -- STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : in std_logic;
+ -- STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : out std_logic;
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
@@ -88,7 +99,8 @@ entity lofar2_unb2c_filterbank is
-- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
-- Connect to the BCK_RX pins in the top wrapper
- JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
+ -- Connect to BCK_REF_CLK pin in the top level wrapper
+ JESD204B_REFCLK : in std_logic;
-- jesd204b syncronization signals
JESD204B_SYSREF : in std_logic;
@@ -99,12 +111,14 @@ end lofar2_unb2c_filterbank;
architecture str of lofar2_unb2c_filterbank is
-- Revision parameters
constant c_revision_select : t_lofar2_unb2c_filterbank_config := func_sel_revision_rec(g_design_name);
- constant c_nof_streams : natural := c_revision_select.nof_streams_input; -- Streams actually passed through for processing
+ -- Streams actually passed through for processing
+ constant c_nof_streams : natural := c_revision_select.nof_streams_input;
-- Firmware version x.y
constant c_fw_version : t_unb2c_board_fw_version := (1, 1);
constant c_mm_clk_freq : natural := c_unb2c_board_mm_clk_freq_100M;
- constant c_lofar2_sample_clk_freq : natural := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS
+ -- alternate 160MHz. TODO: Use to check PPS
+ constant c_lofar2_sample_clk_freq : natural := 200 * 10**6;
-- System
signal cs_sim : std_logic;
@@ -151,12 +165,16 @@ architecture str of lofar2_unb2c_filterbank is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -285,7 +303,8 @@ begin
mm_rst => mm_rst,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ -- Can be external 200MHz, or PLL generated
+ dp_clk => dp_clk,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
index fa4e12bb7ebf8ffe23157e2fa7f24779c4c37f30..c0bf1cb249a084e49b8e6fc060d46317ddafef5c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
@@ -32,7 +32,8 @@ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2c_filterbank is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
index 3193b1a4e866e50ee1b08de077a7ac83b789782d..d6477d3e290c752523f5333b4a99733a15cb3f9c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
@@ -27,259 +27,512 @@ package qsys_lofar2_unb2c_filterbank_pkg is
-----------------------------------------------------------------------------
component qsys_lofar2_unb2c_filterbank is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buf_bsn_read_export : out std_logic; -- export
- ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buf_bsn_write_export : out std_logic; -- export
- ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buf_bsn_read_export : out std_logic; -- export
- reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buf_bsn_write_export : out std_logic; -- export
- reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- export
+ jesd204b_address_export : out std_logic_vector(11 downto 0);
+ -- export
+ jesd204b_clk_export : out std_logic;
+ -- export
+ jesd204b_read_export : out std_logic;
+ -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ jesd204b_reset_export : out std_logic;
+ -- export
+ jesd204b_write_export : out std_logic;
+ -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ ram_aduh_monitor_clk_export : out std_logic;
+ -- export
+ ram_aduh_monitor_read_export : out std_logic;
+ -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_aduh_monitor_reset_export : out std_logic;
+ -- export
+ ram_aduh_monitor_write_export : out std_logic;
+ -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_diag_data_buf_bsn_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buf_bsn_read_export : out std_logic;
+ -- export
+ ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buf_bsn_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buf_bsn_write_export : out std_logic;
+ -- export
+ ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0);
+ -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ ram_equalizer_gains_clk_export : out std_logic;
+ -- export
+ ram_equalizer_gains_read_export : out std_logic;
+ -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_equalizer_gains_reset_export : out std_logic;
+ -- export
+ ram_equalizer_gains_write_export : out std_logic;
+ -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_fil_coefs_clk_export : out std_logic;
+ -- export
+ ram_fil_coefs_read_export : out std_logic;
+ -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_fil_coefs_reset_export : out std_logic;
+ -- export
+ ram_fil_coefs_write_export : out std_logic;
+ -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0);
+ -- export
+ ram_scrap_clk_export : out std_logic;
+ -- export
+ ram_scrap_read_export : out std_logic;
+ -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_scrap_reset_export : out std_logic;
+ -- export
+ ram_scrap_write_export : out std_logic;
+ -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_st_sst_clk_export : out std_logic;
+ -- export
+ ram_st_sst_read_export : out std_logic;
+ -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_st_sst_reset_export : out std_logic;
+ -- export
+ ram_st_sst_write_export : out std_logic;
+ -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_wg_clk_export : out std_logic;
+ -- export
+ ram_wg_read_export : out std_logic;
+ -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_wg_reset_export : out std_logic;
+ -- export
+ ram_wg_write_export : out std_logic;
+ -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_aduh_monitor_clk_export : out std_logic;
+ -- export
+ reg_aduh_monitor_read_export : out std_logic;
+ -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_aduh_monitor_reset_export : out std_logic;
+ -- export
+ reg_aduh_monitor_write_export : out std_logic;
+ -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0);
+ -- export
+ reg_bsn_monitor_input_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_input_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_bsn_scheduler_clk_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_read_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_scheduler_reset_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_write_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_bsn_source_clk_export : out std_logic;
+ -- export
+ reg_bsn_source_read_export : out std_logic;
+ -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_source_reset_export : out std_logic;
+ -- export
+ reg_bsn_source_write_export : out std_logic;
+ -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buf_bsn_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buf_bsn_read_export : out std_logic;
+ -- export
+ reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buf_bsn_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buf_bsn_write_export : out std_logic;
+ -- export
+ reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dp_selector_clk_export : out std_logic;
+ -- export
+ reg_dp_selector_read_export : out std_logic;
+ -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_selector_reset_export : out std_logic;
+ -- export
+ reg_dp_selector_write_export : out std_logic;
+ -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_dp_shiftram_clk_export : out std_logic;
+ -- export
+ reg_dp_shiftram_read_export : out std_logic;
+ -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_shiftram_reset_export : out std_logic;
+ -- export
+ reg_dp_shiftram_write_export : out std_logic;
+ -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_si_clk_export : out std_logic;
+ -- export
+ reg_si_read_export : out std_logic;
+ -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_si_reset_export : out std_logic;
+ -- export
+ reg_si_write_export : out std_logic;
+ -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic;
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_wg_clk_export : out std_logic;
+ -- export
+ reg_wg_read_export : out std_logic;
+ -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wg_reset_export : out std_logic;
+ -- export
+ reg_wg_write_export : out std_logic;
+ -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0)
);
end component qsys_lofar2_unb2c_filterbank;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
index 260d1427fd7440fac1f3a4aec28bf8c4a34955b3..f3c6dff6dce2225690fffedfb9bf9ea0cd12cbda 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
@@ -70,49 +70,67 @@ end tb_lofar2_unb2c_filterbank;
architecture tb of tb_lofar2_unb2c_filterbank is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_cable_delay : time := 12 ns;
constant c_nof_block_per_sync : natural := 16;
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
- constant c_percentage : real := 0.05; -- percentage that actual value may differ from expected value
- constant c_lo_factor : real := 1.0 - c_percentage; -- lower boundary
- constant c_hi_factor : real := 1.0 + c_percentage; -- higher boundary
+ -- percentage that actual value may differ from expected value
+ constant c_percentage : real := 0.05;
+ -- lower boundary
+ constant c_lo_factor : real := 1.0 - c_percentage;
+ -- higher boundary
+ constant c_hi_factor : real := 1.0 + c_percentage;
-- WG
- constant c_full_scale_ampl : real := real(2**(18 - 1) - 1); -- = full scale of WG
- constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp_0 : natural := 2**(c_sdp_W_adc - 1) / 2; -- in number of lsb
- constant c_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
- constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
- constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- constant c_wg_ampl_lsb : real := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
+ -- = full scale of WG
+ constant c_full_scale_ampl : real := real(2**(18 - 1) - 1);
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := 2;
+ -- in number of lsb
+ constant c_ampl_sp_0 : natural := 2**(c_sdp_W_adc - 1) / 2;
+ -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+ constant c_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_sdp_N_fft);
+ -- in freq_unit
+ constant c_wg_freq_offset : real := 0.0 / 11.0;
+ -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ constant c_subband_sp_0 : real := 102.0;
+ -- amplitude in number of LSbit resolution steps
+ constant c_wg_ampl_lsb : real := c_diag_wg_ampl_unit / c_full_scale_ampl;
constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_sdp_N_fft * c_nof_block_per_sync);
-- WPFB
- constant c_nof_pfb : natural := 1; -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
- constant c_wb_leakage_bin : natural := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor; -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
- constant c_exp_sp_subband_power_ratio : real := 1.0 / 8.0; -- depends on internal WPFB quantization and FIR coefficients
- constant c_exp_sp_subband_power_sum_ratio : real := c_exp_sp_subband_power_ratio; -- because all sinus power is expected in one subband
+ -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
+ constant c_nof_pfb : natural := 1;
+ -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
+ constant c_wb_leakage_bin : natural := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor;
+ -- depends on internal WPFB quantization and FIR coefficients
+ constant c_exp_sp_subband_power_ratio : real := 1.0 / 8.0;
+ -- because all sinus power is expected in one subband
+ constant c_exp_sp_subband_power_sum_ratio : real := c_exp_sp_subband_power_ratio;
constant c_exp_subband_power_sp_0 : real := c_exp_wg_power_sp_0 * c_exp_sp_subband_power_ratio;
type t_real_arr is array (integer range <>) of real;
type t_slv_64_subbands_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_sub);
-- ADUH
- constant c_mon_buffer_nof_samples : natural := 512; -- samples per stream
+ -- samples per stream
+ constant c_mon_buffer_nof_samples : natural := 512;
constant c_mon_buffer_nof_words : natural := c_mon_buffer_nof_samples;
-- MM
@@ -138,7 +156,8 @@ architecture tb of tb_lofar2_unb2c_filterbank is
signal current_bsn_wg : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
-- WPFB
- signal sp_subband_powers_arr2 : t_slv_64_subbands_arr(c_nof_pfb * c_nof_complex - 1 downto 0); -- [sp][sub]
+ -- [sp][sub]
+ signal sp_subband_powers_arr2 : t_slv_64_subbands_arr(c_nof_pfb * c_nof_complex - 1 downto 0);
signal sp_subband_power_0 : real;
signal sp_subband_power_sum : t_real_arr(c_nof_pfb * c_nof_complex - 1 downto 0) := (others => 0.0);
signal sp_subband_power_sum_0 : real;
@@ -176,17 +195,26 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -249,13 +277,15 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
variable v_sp_power_sum_0 : real;
variable v_sp_subband_power : real;
- variable v_W, v_T, v_U, v_S, v_B : natural; -- array indicies
+ -- array indicies
+ variable v_W, v_T, v_U, v_S, v_B : natural;
begin
-- Wait for DUT power up after reset
wait for 1 us;
@@ -266,9 +296,12 @@ begin
-- Enable BS
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk);
+ -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk);
----------------------------------------------------------------------------
-- Enable WG
@@ -278,10 +311,14 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk);
-- Read current BSN
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 downto 0), tb_clk);
@@ -292,8 +329,10 @@ begin
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
v_bsn := c_bsn_start_wg;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
-- Wait for ADUH monitor to have filled with WG data
wait for c_sdp_T_sub * c_sdp_N_taps;
@@ -303,11 +342,14 @@ begin
-- WG data : read ADUH monitor buffer
----------------------------------------------------------------------------
-- Wait for start of sync interval
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2,
c_sdp_T_sub, tb_clk);
- wait for c_sdp_T_sub; -- ensure that one block of samples has filled the ADUH monitor buffer after the sync
+ -- ensure that one block of samples has filled the ADUH monitor buffer after the sync
+ wait for c_sdp_T_sub;
-- Read via MM
for I in 0 to c_mon_buffer_nof_words - 1 loop
@@ -327,14 +369,18 @@ begin
-- Read ADUH monitor power sum
---------------------------------------------------------------------------
-- Wait for start of sync interval
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3,
c_sdp_T_sub, tb_clk);
-- Read ADUH monitor power sum
- mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk); -- read low part
+ -- read low part
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk);
sp_power_sum(31 downto 0) <= rd_data;
- mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk); -- read high part
+ -- read high part
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk);
sp_power_sum(63 downto 32) <= rd_data;
proc_common_wait_some_cycles(tb_clk, 1);
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
index 896329e2ff83779b74d415115d61552c3a367eb4..b05d775b5ac3bcc2a6b340cf2e2abf4a31d0afab 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2c_ring_full is
generic (
g_design_name : string := "lofar2_unb2c_ring_full";
g_design_note : string := "Lofar2 Ring full design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -64,14 +73,16 @@ entity lofar2_unb2c_ring_full is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers
QSFP_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
QSFP_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
index 17830917aa4976d86f2bd11c8a9c70e26ce0206b..36ece61b47903cca5088365d2abe7a077f61e008 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
@@ -46,9 +46,11 @@ architecture tb of tb_lofar2_unb2c_ring_full is
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
+ -- 644MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
constant c_pps_period : natural := 1000;
-- Tb
@@ -84,12 +86,17 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- SA_CLK <= not SA_CLK after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ SA_CLK <= not SA_CLK after c_sa_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
index 991fdeb9228a16aadb54889827c1f81d926359e5..a86c5fafd0bb14d3610ff661034623357e5d9a97 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
@@ -41,20 +41,29 @@ entity lofar2_unb2c_ring_one is
generic (
g_design_name : string := "lofar2_unb2c_ring_one";
g_design_note : string := "Lofar2 Ring one design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -67,14 +76,16 @@ entity lofar2_unb2c_ring_one is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers
QSFP_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
QSFP_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
index 0aff49975ac74650b42b8206d7c239f9c9319ed2..bd297b04051b15bd70f789aa157fc40560c0845d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
@@ -46,9 +46,11 @@ architecture tb of tb_lofar2_unb2c_ring_one is
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
+ -- 644MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
constant c_pps_period : natural := 1000;
-- Tb
@@ -84,12 +86,17 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- SA_CLK <= not SA_CLK after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ SA_CLK <= not SA_CLK after c_sa_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
index 44d0371592780c69ebd37b2599f76fa3075634f9..9fab1d8d4113de115361867452ec8b76f0eeac62 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
@@ -47,23 +47,32 @@ entity lofar2_unb2c_ring is
generic (
g_design_name : string := "lofar2_unb2c_ring";
g_design_note : string := "UNUSED";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_sync_timeout : natural := c_sdp_sim.sync_timeout;
g_sim_unb_nr : natural := c_sdp_sim.unb_nr;
g_sim_node_nr : natural := c_sdp_sim.node_nr;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := false;
g_protect_addr_range : boolean := false
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -76,13 +85,15 @@ entity lofar2_unb2c_ring is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP1 for 10GbE output to CEP.
QSFP_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
QSFP_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
@@ -100,24 +111,32 @@ architecture str of lofar2_unb2c_ring is
-- Firmware version x.y
constant c_fw_version : t_unb2c_board_fw_version := (2, 0);
constant c_mm_clk_freq : natural := c_unb2c_board_mm_clk_freq_100M;
- constant c_lofar2_sample_clk_freq : natural := c_sdp_N_clk_per_sync; -- fixed 200 MHz for LOFAR2.0 stage 1
+ -- fixed 200 MHz for LOFAR2.0 stage 1
+ constant c_lofar2_sample_clk_freq : natural := c_sdp_N_clk_per_sync;
-- QSFP
constant c_nof_qsfp_bus : natural := 1;
- constant c_nof_streams_qsfp : natural := c_unb2c_board_tr_qsfp.bus_w * c_nof_qsfp_bus; -- 4
+ -- 4
+ constant c_nof_streams_qsfp : natural := c_unb2c_board_tr_qsfp.bus_w * c_nof_qsfp_bus;
-- RING
constant c_nof_ring_bus : natural := 2;
- constant c_ring_bus_w : natural := 4; -- Using 4 phisically, there are 12
- constant c_nof_streams_ring : natural := c_ring_bus_w * c_nof_ring_bus; -- c_unb2c_board_tr_ring.bus_w*c_nof_ring_bus; -- 8
+ -- Using 4 phisically, there are 12
+ constant c_ring_bus_w : natural := 4;
+ -- c_unb2c_board_tr_ring.bus_w*c_nof_ring_bus; -- 8
+ constant c_nof_streams_ring : natural := c_ring_bus_w * c_nof_ring_bus;
-- 10GbE
- constant c_nof_even_lanes : natural := ceil_div(c_nof_lanes, 2); -- nof lanes transmitting in positive direction. Using ceil_div as c_nof_lanes might be odd.
- constant c_nof_odd_lanes : natural := c_nof_lanes / 2; -- nof lanes transmitting in negative direction. Note for c_nof_lanes = 1 -> c_nof_odd_lanes = 1 / 2 => 0 which is desired.
- constant c_nof_mac : natural := 3 * c_nof_even_lanes; -- must match one of the MAC IP variations, e.g. 3, 12, 24, 48
+ -- nof lanes transmitting in positive direction. Using ceil_div as c_nof_lanes might be odd.
+ constant c_nof_even_lanes : natural := ceil_div(c_nof_lanes, 2);
+ -- nof lanes transmitting in negative direction. Note for c_nof_lanes = 1 -> c_nof_odd_lanes = 1 / 2 => 0 which is desired.
+ constant c_nof_odd_lanes : natural := c_nof_lanes / 2;
+ -- must match one of the MAC IP variations, e.g. 3, 12, 24, 48
+ constant c_nof_mac : natural := 3 * c_nof_even_lanes;
constant c_lane_data_w : natural := 64;
- constant c_lane_packet_length : natural := c_sdp_V_ring_pkt_len_max - c_ring_dp_hdr_field_size; -- = 48 longwords per packet, so the maximum data rate with a packetrate of 195312.5 and all 16 nodes combined = 16 * 48 / 1024 * 64 * 200M = 9.6 Gb/s
+ -- = 48 longwords per packet, so the maximum data rate with a packetrate of 195312.5 and all 16 nodes combined = 16 * 48 / 1024 * 64 * 200M = 9.6 Gb/s
+ constant c_lane_packet_length : natural := c_sdp_V_ring_pkt_len_max - c_ring_dp_hdr_field_size;
constant c_use_dp_layer : boolean := true;
constant c_nof_rx_monitors : natural := c_sdp_N_pn_max;
constant c_nof_tx_monitors : natural := c_sdp_N_pn_max;
@@ -126,14 +145,20 @@ architecture str of lofar2_unb2c_ring is
constant c_bsn_at_sync_check_channel : natural := 1;
constant c_validate_channel : boolean := true;
constant c_validate_channel_mode : string := "=";
- constant c_fifo_tx_fill : natural := c_lane_packet_length + sel_a_b(c_use_dp_layer, c_ring_dp_hdr_field_size, c_ring_eth_hdr_field_size); -- total packet length
+ -- total packet length
+ constant c_fifo_tx_fill : natural := c_lane_packet_length + sel_a_b(c_use_dp_layer, c_ring_dp_hdr_field_size, c_ring_eth_hdr_field_size);
constant c_fifo_tx_size : natural := 2 * c_lane_packet_length;
- constant c_lofar2_sync_timeout : natural := c_lofar2_sample_clk_freq + c_lofar2_sample_clk_freq / 10; -- 10% margin.
+ -- 10% margin.
+ constant c_lofar2_sync_timeout : natural := c_lofar2_sample_clk_freq + c_lofar2_sample_clk_freq / 10;
constant c_sync_timeout : natural := sel_a_b(g_sim, g_sim_sync_timeout, c_lofar2_sync_timeout );
- constant c_nof_if : natural := 3; -- 3 different interfaces, QSFP, RING_0 and RING_1
- constant c_qsfp_if_offset : natural := 0; -- QSFP signals are indexed at c_nof_if * I.
- constant c_ring_0_if_offset : natural := 1; -- RING_0 signals are indexed at c_nof_if * I + 1.
- constant c_ring_1_if_offset : natural := 2; -- RING_1 signals are indexed at c_nof_if * I + 2.
+ -- 3 different interfaces, QSFP, RING_0 and RING_1
+ constant c_nof_if : natural := 3;
+ -- QSFP signals are indexed at c_nof_if * I.
+ constant c_qsfp_if_offset : natural := 0;
+ -- RING_0 signals are indexed at c_nof_if * I + 1.
+ constant c_ring_0_if_offset : natural := 1;
+ -- RING_1 signals are indexed at c_nof_if * I + 2.
+ constant c_ring_1_if_offset : natural := 2;
constant c_addr_w_reg_ring_lane_info : natural := 1;
constant c_addr_w_reg_bsn_monitor_v2_ring_rx : natural := ceil_log2(c_nof_rx_monitors) + 3;
@@ -145,7 +170,8 @@ architecture str of lofar2_unb2c_ring is
adr_w => ceil_log2(c_nof_lanes),
dat_w => 1,
nof_dat => c_nof_lanes,
- init_sl => '0'); -- default use lane input = 0, 1 = local input.
+ -- default use lane input = 0, 1 = local input.
+ init_sl => '0');
signal gn_index : natural;
signal this_rn : std_logic_vector(c_byte_w - 1 downto 0);
@@ -187,12 +213,16 @@ architecture str of lofar2_unb2c_ring is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_copi : t_mem_copi := c_mem_copi_rst; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_copi : t_mem_copi := c_mem_copi_rst;
signal eth1g_tse_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal eth1g_reg_copi : t_mem_copi := c_mem_copi_rst; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_copi : t_mem_copi := c_mem_copi_rst;
signal eth1g_reg_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_copi : t_mem_copi := c_mem_copi_rst; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_copi : t_mem_copi := c_mem_copi_rst;
signal eth1g_ram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS read
@@ -354,7 +384,8 @@ begin
mm_rst => mm_rst,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ -- Can be external 200MHz, or PLL generated
+ dp_clk => dp_clk,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
@@ -603,7 +634,8 @@ begin
u_mmp_dp_xonoff_lane : entity dp_lib.mms_dp_xonoff
generic map (
g_nof_streams => c_nof_lanes,
- g_default_value => '1' -- default enabled, because standard behaviour is to only pass on packets from lane.
+ -- default enabled, because standard behaviour is to only pass on packets from lane.
+ g_default_value => '1'
)
port map (
mm_rst => mm_rst,
@@ -626,13 +658,15 @@ begin
-- MMP dp_xonoff local_sosi
-----------------------------------------------------------------------------
gen_copy_local: for I in 0 to c_nof_lanes - 1 generate
- dp_xonoff_local_snk_in_arr(I) <= local_sosi; -- copy local sosi to all lanes
+ -- copy local sosi to all lanes
+ dp_xonoff_local_snk_in_arr(I) <= local_sosi;
end generate;
u_mmp_dp_xonoff_local : entity dp_lib.mms_dp_xonoff
generic map (
g_nof_streams => c_nof_lanes,
- g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
+ -- default disabled, because standard behaviour is to only pass on packets from lane.
+ g_default_value => '0'
)
port map (
mm_rst => mm_rst,
@@ -707,7 +741,8 @@ begin
-- Use full c_byte_w range of ID for gn_index and ring_info.O_rn
gn_index <= TO_UINT(ID);
- this_rn <= TO_UVEC(gn_index - TO_UINT(ring_info.O_rn), c_byte_w) when rising_edge(dp_clk); -- Using register to ease timing closure.
+ -- Using register to ease timing closure.
+ this_rn <= TO_UVEC(gn_index - TO_UINT(ring_info.O_rn), c_byte_w) when rising_edge(dp_clk);
-----------------------------------------------------------------------------
-- Ring lane even indices.
@@ -715,7 +750,8 @@ begin
gen_even_lanes: for I in 0 to c_nof_even_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
generic map (
- g_lane_direction => 1, -- transport in positive direction.
+ -- transport in positive direction.
+ g_lane_direction => 1,
g_lane_data_w => c_lane_data_w,
g_lane_packet_length => c_lane_packet_length,
g_use_dp_layer => c_use_dp_layer,
@@ -734,7 +770,8 @@ begin
dp_clk => dp_clk,
dp_rst => dp_rst,
- from_lane_sosi => from_lane_sosi_arr(2 * I), -- even indices
+ -- even indices
+ from_lane_sosi => from_lane_sosi_arr(2 * I),
to_lane_sosi => to_lane_sosi_arr(2 * I),
lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I),
lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I),
@@ -766,7 +803,8 @@ begin
gen_odd_lanes : for I in 0 to c_nof_odd_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
generic map (
- g_lane_direction => 0, -- transport in negative direction.
+ -- transport in negative direction.
+ g_lane_direction => 0,
g_lane_data_w => c_lane_data_w,
g_lane_packet_length => c_lane_packet_length,
g_use_dp_layer => c_use_dp_layer,
@@ -785,7 +823,8 @@ begin
dp_clk => dp_clk,
dp_rst => dp_rst,
- from_lane_sosi => from_lane_sosi_arr(2 * I + 1), -- odd indices
+ -- odd indices
+ from_lane_sosi => from_lane_sosi_arr(2 * I + 1),
to_lane_sosi => to_lane_sosi_arr(2 * I + 1),
lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I),
lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I),
@@ -806,7 +845,8 @@ begin
this_rn => this_rn,
N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
+ -- reverse tx/rx select for odd indices.
+ rx_select => ring_info.use_cable_to_next_rn,
tx_select => ring_info.use_cable_to_previous_rn
);
end generate;
@@ -816,11 +856,15 @@ begin
-----------------------------------------------------------------------------
gen_combine: for I in 0 to c_nof_even_lanes - 1 generate
-- QSFP_RX
- lane_rx_cable_even_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_qsfp_if_offset) when ring_info.use_cable_to_previous_rn = '1' else c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> even lanes receive from cable
- lane_rx_cable_odd_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_qsfp_if_offset) when ring_info.use_cable_to_next_rn = '1' else c_dp_sosi_rst; -- use_cable_to_next_rn=1 -> odd lanes receive from cable
+ -- use_cable_to_previous_rn=1 -> even lanes receive from cable
+ lane_rx_cable_even_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_qsfp_if_offset) when ring_info.use_cable_to_previous_rn = '1' else c_dp_sosi_rst;
+ -- use_cable_to_next_rn=1 -> odd lanes receive from cable
+ lane_rx_cable_odd_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_qsfp_if_offset) when ring_info.use_cable_to_next_rn = '1' else c_dp_sosi_rst;
-- QSFP_TX
- tr_10gbe_snk_in_arr(c_nof_if * I + c_qsfp_if_offset) <= lane_tx_cable_even_sosi_arr(I) when ring_info.use_cable_to_next_rn = '1' else -- use_cable_to_next_rn=1 -> even lanes transmit to cable
- lane_tx_cable_odd_sosi_arr(I) when ring_info.use_cable_to_previous_rn = '1' else c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> odd lanes transmit to cable
+ -- use_cable_to_next_rn=1 -> even lanes transmit to cable
+ tr_10gbe_snk_in_arr(c_nof_if * I + c_qsfp_if_offset) <= lane_tx_cable_even_sosi_arr(I) when ring_info.use_cable_to_next_rn = '1' else
+ -- use_cable_to_previous_rn=1 -> odd lanes transmit to cable
+ lane_tx_cable_odd_sosi_arr(I) when ring_info.use_cable_to_previous_rn = '1' else c_dp_sosi_rst;
-- RING_0_RX even lanes receive from RING_0 (from the left)
lane_rx_board_even_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_ring_0_if_offset);
@@ -953,7 +997,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
index 42f7512e380976a981493559160d58b0950a99a8..4207fcdba96f5d0a121fbd60e0c9dfcba2f69a23 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
@@ -32,7 +32,8 @@ use lofar2_sdp_lib.sdp_pkg.all;
entity mmc_lofar2_unb2c_ring is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
index 8c35d482f28c694e83468ddaca51cb3918516597..05cc71262afea5b0f19171cd7ebfc4bb74fd987e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
@@ -28,203 +28,400 @@ package qsys_lofar2_unb2c_ring_pkg is
component qsys_lofar2_unb2c_ring is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export
- ram_diag_bg_clk_export : out std_logic; -- export
- ram_diag_bg_read_export : out std_logic; -- export
- ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_reset_export : out std_logic; -- export
- ram_diag_bg_write_export : out std_logic; -- export
- ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_clk_export : out std_logic; -- export
- reg_diag_bg_read_export : out std_logic; -- export
- reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_reset_export : out std_logic; -- export
- reg_diag_bg_write_export : out std_logic; -- export
- reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export
- reg_dp_block_validate_err_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_read_export : out std_logic; -- export
- reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_write_export : out std_logic; -- export
- reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_lane_clk_export : out std_logic; -- export
- reg_dp_xonoff_lane_read_export : out std_logic; -- export
- reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_lane_reset_export : out std_logic; -- export
- reg_dp_xonoff_lane_write_export : out std_logic; -- export
- reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_local_clk_export : out std_logic; -- export
- reg_dp_xonoff_local_read_export : out std_logic; -- export
- reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_local_reset_export : out std_logic; -- export
- reg_dp_xonoff_local_write_export : out std_logic; -- export
- reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_ring_lane_info_clk_export : out std_logic; -- export
- reg_ring_lane_info_read_export : out std_logic; -- export
- reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_reset_export : out std_logic; -- export
- reg_ring_lane_info_write_export : out std_logic; -- export
- reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ ram_diag_bg_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ ram_diag_bg_clk_export : out std_logic;
+ -- export
+ ram_diag_bg_read_export : out std_logic;
+ -- export
+ ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_bg_reset_export : out std_logic;
+ -- export
+ ram_diag_bg_write_export : out std_logic;
+ -- export
+ ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0);
+ -- export
+ ram_scrap_clk_export : out std_logic;
+ -- export
+ ram_scrap_read_export : out std_logic;
+ -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_scrap_reset_export : out std_logic;
+ -- export
+ ram_scrap_write_export : out std_logic;
+ -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_bg_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_bg_clk_export : out std_logic;
+ -- export
+ reg_diag_bg_read_export : out std_logic;
+ -- export
+ reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_bg_reset_export : out std_logic;
+ -- export
+ reg_diag_bg_write_export : out std_logic;
+ -- export
+ reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_read_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_write_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_dp_block_validate_err_clk_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_read_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_block_validate_err_reset_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_write_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_dp_xonoff_lane_clk_export : out std_logic;
+ -- export
+ reg_dp_xonoff_lane_read_export : out std_logic;
+ -- export
+ reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_xonoff_lane_reset_export : out std_logic;
+ -- export
+ reg_dp_xonoff_lane_write_export : out std_logic;
+ -- export
+ reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_dp_xonoff_local_clk_export : out std_logic;
+ -- export
+ reg_dp_xonoff_local_read_export : out std_logic;
+ -- export
+ reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_xonoff_local_reset_export : out std_logic;
+ -- export
+ reg_dp_xonoff_local_write_export : out std_logic;
+ -- export
+ reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_ring_info_clk_export : out std_logic;
+ -- export
+ reg_ring_info_read_export : out std_logic;
+ -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_ring_info_reset_export : out std_logic;
+ -- export
+ reg_ring_info_write_export : out std_logic;
+ -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_ring_lane_info_clk_export : out std_logic;
+ -- export
+ reg_ring_lane_info_read_export : out std_logic;
+ -- export
+ reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_ring_lane_info_reset_export : out std_logic;
+ -- export
+ reg_ring_lane_info_write_export : out std_logic;
+ -- export
+ reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_read_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_write_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0)
);
end component qsys_lofar2_unb2c_ring;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
index 60dc7bbea0781615a5844d2c59e1ec938e65793a..55b3d13d30b1caaffa63d25d75587866358c499a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
@@ -60,7 +60,8 @@ entity tb_lofar2_unb2c_ring is
g_access_scheme : integer range 1 to 3 := 1
);
port (
- tb_end : out std_logic := '0' -- For multi tb
+ -- For multi tb
+ tb_end : out std_logic := '0'
);
end tb_lofar2_unb2c_ring;
@@ -70,13 +71,16 @@ architecture tb of tb_lofar2_unb2c_ring is
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
+ -- 644MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
constant c_pps_period : natural := 1000;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_cable_delay : time := 12 ns;
constant c_revision_select : t_lofar2_unb2c_ring_config := func_sel_revision_rec(g_design_name);
@@ -85,7 +89,8 @@ architecture tb of tb_lofar2_unb2c_ring is
constant c_block_period : natural := 1024;
constant c_blocksize : natural := c_sdp_V_ring_pkt_len_max - c_ring_dp_hdr_field_size;
constant c_gapsize : natural := c_block_period - c_blocksize;
- constant c_sync_timeout : natural := c_block_period * g_nof_block_per_sync + 10; -- +10 for extra slack
+ -- +10 for extra slack
+ constant c_sync_timeout : natural := c_block_period * g_nof_block_per_sync + 10;
constant c_exp_bsn_at_sync : natural := g_nof_block_per_sync;
constant c_exp_nof_sop : natural := g_nof_block_per_sync;
constant c_exp_nof_valid : natural := g_nof_block_per_sync * c_blocksize;
@@ -137,21 +142,31 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
- ext_clk <= not ext_clk or i_tb_end after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk(0) <= not eth_clk(0) or i_tb_end after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- SA_CLK <= not SA_CLK or i_tb_end after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk or i_tb_end after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= not eth_clk(0) or i_tb_end after c_eth_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ SA_CLK <= not SA_CLK or i_tb_end after c_sa_clk_period / 2;
pps_rst <= '0' after c_ext_clk_period * 2;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -230,17 +245,23 @@ begin
-- Write ring configuration to all nodes.
for RN in 0 to g_nof_rn - 1 loop
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_INFO", 2, g_nof_rn, tb_clk); -- N_rn
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_INFO", 3, 0, tb_clk); -- O_rn
+ -- N_rn
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_INFO", 2, g_nof_rn, tb_clk);
+ -- O_rn
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_INFO", 3, 0, tb_clk);
end loop;
-- Start node specific settings
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_INFO", 0, 1, tb_clk); -- use_ring_to_previous_rn = 1
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_INFO", 1, 0, tb_clk); -- use_ring_to_next_rn = 0
+ -- use_ring_to_previous_rn = 1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_INFO", 0, 1, tb_clk);
+ -- use_ring_to_next_rn = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_INFO", 1, 0, tb_clk);
-- End node specific settings
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_RING_INFO", 0, 0, tb_clk); -- use_ring_to_previous_rn = 0
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_RING_INFO", 1, 1, tb_clk); -- use_ring_to_next_rn = 1
+ -- use_ring_to_previous_rn = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_RING_INFO", 0, 0, tb_clk);
+ -- use_ring_to_next_rn = 1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_RING_INFO", 1, 1, tb_clk);
----------------------------------------------------------------------------
-- Access scheme 1. A source RN creates the packets and sends them along the ring.
@@ -248,8 +269,10 @@ begin
if g_access_scheme = 1 then
for I in 0 to c_nof_lanes - 1 loop
-- Select local input (= 1) on start node on all lanes.
- mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_lane, I * 2, 0, tb_clk); -- Disable input from lane
- mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_local, I * 2, 1, tb_clk); -- Enable local input
+ -- Disable input from lane
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_lane, I * 2, 0, tb_clk);
+ -- Enable local input
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_local, I * 2, 1, tb_clk);
-- Set transport_nof_hops to N_rn on start node for a full transfer around the ring.
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_LANE_INFO", I * 2 + 1, g_nof_rn, tb_clk);
@@ -262,8 +285,10 @@ begin
for RN in 0 to g_nof_rn - 1 loop
for I in 0 to c_nof_lanes - 1 loop
-- Select both local and remote input on all nodes on all lanes.
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DP_XONOFF_LANE", I * 2, 1, tb_clk); -- Enable input from lane
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DP_XONOFF_LOCAL", I * 2, 1, tb_clk); -- Enable local input
+ -- Enable input from lane
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DP_XONOFF_LANE", I * 2, 1, tb_clk);
+ -- Enable local input
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DP_XONOFF_LOCAL", I * 2, 1, tb_clk);
-- Set transport_nof_hops to N_rn-1 on all nodes.
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_LANE_INFO", I * 2 + 1, g_nof_rn - 1, tb_clk);
@@ -274,37 +299,52 @@ begin
-- Enable BG on all nodes (for bs_sosi)
----------------------------------------------------------------------------
for RN in 0 to g_nof_rn - 1 loop
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 1, c_blocksize, tb_clk); -- samples per packet
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 2, g_nof_block_per_sync, tb_clk); -- blocks per sync
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 3, c_gapsize, tb_clk); -- gapsize
- mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 0, 3, tb_clk); -- enable at sync
+ -- samples per packet
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 1, c_blocksize, tb_clk);
+ -- blocks per sync
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 2, g_nof_block_per_sync, tb_clk);
+ -- gapsize
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 3, c_gapsize, tb_clk);
+ -- enable at sync
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_DIAG_BG", 0, 3, tb_clk);
end loop;
----------------------------------------------------------------------------
-- Verify Access scheme 1 by reading rx / tx monitors on source RN
----------------------------------------------------------------------------
if g_access_scheme = 1 then
-- Wait for bsn monitor to have received a sync period.
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_monitor_v2_ring_rx, 4, -- read nof valid
- "SIGNED", rd_data, ">", 0, -- this is the wait until condition
- 1 us, tb_clk); -- read every 1 us
+ -- read nof valid
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_monitor_v2_ring_rx, 4,
+ -- this is the wait until condition
+ "SIGNED", rd_data, ">", 0,
+ -- read every 1 us
+ 1 us, tb_clk);
for I in 0 to c_nof_lanes - 1 loop
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 1, rd_data, tb_clk); -- bsn at sync
+ -- bsn at sync
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 1, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 3, rd_data, tb_clk); -- nof_sop
+ -- nof_sop
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 3, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 4, rd_data, tb_clk); -- nof_valid
+ -- nof_valid
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 4, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 5, rd_data, tb_clk); -- nof_err
+ -- nof_err
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 5, rd_data, tb_clk);
assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_tx on source node in access scheme 1." severity ERROR;
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 1, rd_data, tb_clk); -- bsn at sync
+ -- bsn at sync
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 1, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 3, rd_data, tb_clk); -- nof_sop
+ -- nof_sop
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 3, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 4, rd_data, tb_clk); -- nof_valid
+ -- nof_valid
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 4, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
- mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 5, rd_data, tb_clk); -- nof_err
+ -- nof_err
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I * c_sdp_N_pn_max * 8 + 5, rd_data, tb_clk);
assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
end loop;
@@ -313,42 +353,60 @@ begin
----------------------------------------------------------------------------
else
-- Wait for bsn monitor to have received a sync period.
- mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
- "SIGNED", rd_data, ">", 0, -- this is the wait until condition
- 1 us, tb_clk); -- read every 1 us
+ -- read nof valid
+ mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", 4,
+ -- this is the wait until condition
+ "SIGNED", rd_data, ">", 0,
+ -- read every 1 us
+ 1 us, tb_clk);
for RN in 0 to g_nof_rn - 1 loop
- for I in 0 to c_nof_lanes - 1 loop -- lane index
- for J in 0 to g_nof_rn - 1 loop -- bsn_monitor index
+ -- lane index
+ for I in 0 to c_nof_lanes - 1 loop
+ -- bsn_monitor index
+ for J in 0 to g_nof_rn - 1 loop
-- No packets transmitted from next RN (this_rn + 1 for even lanes, this_rn - 1 for odd lanes) as this RN should have removed it from the ring.
if (I mod 2 = 0 and (RN + 1) mod g_nof_rn = J) or (I mod 2 = 1 and (RN + g_nof_rn - 1) mod g_nof_rn = J) then
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
+ -- status bits
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk);
assert rd_data(2) = '1' report "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
else
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
+ -- status bits
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk);
assert rd_data(2) = '0' report "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 1, rd_data, tb_clk); -- bsn at sync
+ -- bsn at sync
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 1, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 3, rd_data, tb_clk); -- nof_sop
+ -- nof_sop
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 3, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 4, rd_data, tb_clk); -- nof_valid
+ -- nof_valid
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 4, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 5, rd_data, tb_clk); -- nof_err
+ -- nof_err
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_TX", (I * c_sdp_N_pn_max + J) * 8 + 5, rd_data, tb_clk);
assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_tx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
end if;
- if RN = J then -- No packets received from itself as the previous RN should have removed it from the ring.
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
+ -- No packets received from itself as the previous RN should have removed it from the ring.
+ if RN = J then
+ -- status bits
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk);
assert rd_data(2) = '1' report "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
else
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk); -- status bits
+ -- status bits
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 0, rd_data, tb_clk);
assert rd_data(2) = '0' report "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 1, rd_data, tb_clk); -- bsn at sync
+ -- bsn at sync
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 1, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_bsn_at_sync report "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 3, rd_data, tb_clk); -- nof_sop
+ -- nof_sop
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 3, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_sop report "Wrong nof_sop value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 4, rd_data, tb_clk); -- nof_valid
+ -- nof_valid
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 4, rd_data, tb_clk);
assert TO_UINT(rd_data) = c_exp_nof_valid report "Wrong nof_valid value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
- mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 5, rd_data, tb_clk); -- nof_err
+ -- nof_err
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", (I * c_sdp_N_pn_max + J) * 8 + 5, rd_data, tb_clk);
assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_rx on RN_" & integer'image(RN) & " in access scheme 2/3." severity ERROR;
end if;
end loop;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
index 8d8576c59fc5a8963b9b38fd9587c055aaa59e37..f9b6939cf1e9d7e517f04589a608e5ea9b1e5a36 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
@@ -40,7 +40,8 @@ architecture tb of tb_tb_lofar2_unb2c_ring is
constant c_nof_rn : natural := 3;
constant c_nof_tb : natural := 5;
signal tb_end_vec : std_logic_vector(c_nof_tb - 1 downto 0) := (others => '0');
- signal tb_end : std_logic; -- declare tb_end as STD_LOGIC to avoid 'No objects found' error on 'when -label tb_end' in *.do file
+ -- declare tb_end as STD_LOGIC to avoid 'No objects found' error on 'when -label tb_end' in *.do file
+ signal tb_end : std_logic;
begin
-- g_multi_tb : BOOLEAN := FALSE;
-- g_unb_nr : NATURAL := 4;
@@ -50,10 +51,14 @@ begin
-- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
-- using different g_unb_nr to avoid MM file clashing.
- u_one_1 : entity work.tb_lofar2_unb2c_ring generic map(true, 0, "lofar2_unb2c_ring_one", c_nof_rn, 3, 1) port map(tb_end_vec(0)); -- access scheme 1.
- u_one_2_3 : entity work.tb_lofar2_unb2c_ring generic map(true, 1, "lofar2_unb2c_ring_one", c_nof_rn, 3, 2) port map(tb_end_vec(1)); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
- u_full_1 : entity work.tb_lofar2_unb2c_ring generic map(true, 2, "lofar2_unb2c_ring_full", c_nof_rn, 3, 1) port map(tb_end_vec(2)); -- access scheme 1.
- u_full_2_3 : entity work.tb_lofar2_unb2c_ring generic map(true, 3, "lofar2_unb2c_ring_full", c_nof_rn, 32, 2) port map(tb_end_vec(3)); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
+ -- access scheme 1.
+ u_one_1 : entity work.tb_lofar2_unb2c_ring generic map(true, 0, "lofar2_unb2c_ring_one", c_nof_rn, 3, 1) port map(tb_end_vec(0));
+ -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
+ u_one_2_3 : entity work.tb_lofar2_unb2c_ring generic map(true, 1, "lofar2_unb2c_ring_one", c_nof_rn, 3, 2) port map(tb_end_vec(1));
+ -- access scheme 1.
+ u_full_1 : entity work.tb_lofar2_unb2c_ring generic map(true, 2, "lofar2_unb2c_ring_full", c_nof_rn, 3, 1) port map(tb_end_vec(2));
+ -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
+ u_full_2_3 : entity work.tb_lofar2_unb2c_ring generic map(true, 3, "lofar2_unb2c_ring_full", c_nof_rn, 32, 2) port map(tb_end_vec(3));
-- u_16_rn -> Using 16 ring nodes. Using the _one revision as it only uses 1 lane to limit MM readout time. Also using
-- g_nof_block_per_sync = 32 as all bsn monitors have to be read during one sync period which takes more time with 16 nodes.
u_16_rn : entity work.tb_lofar2_unb2c_ring generic map(true, 4, "lofar2_unb2c_ring_one", 16, 32, 2) port map(tb_end_vec(4));
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
index 0a7c377d0a2ce6f6fff31adfcae2f1efb453f3f1..497e376ee30e560ef24d29b528af4becbe3db2df 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
@@ -38,20 +38,29 @@ entity disturb2_unb2c_sdp_station_full is
generic (
g_design_name : string := "disturb2_unb2c_sdp_station_full";
g_design_note : string := "Disturb2 SDP station full design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -64,7 +73,8 @@ entity disturb2_unb2c_sdp_station_full is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP0 for Ring.
QSFP_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -77,18 +87,22 @@ entity disturb2_unb2c_sdp_station_full is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (note only 12 are used in unb2c)
- BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0)
);
end disturb2_unb2c_sdp_station_full;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
index 0bd6efeaed403e1242fac2f0ef8779b4507fee20..ce95d2dc77af0eaec0c90b632370cd05e7406d65 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
@@ -38,20 +38,29 @@ entity disturb2_unb2c_sdp_station_full_wg is
generic (
g_design_name : string := "disturb2_unb2c_sdp_station_full_wg";
g_design_note : string := "Disturb2 SDP station full design WG";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -64,7 +73,8 @@ entity disturb2_unb2c_sdp_station_full_wg is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP0 for Ring.
QSFP_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -77,7 +87,8 @@ entity disturb2_unb2c_sdp_station_full_wg is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0)
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
index cde951b9a50baab6ffdcbb9846b03923bc9b252b..ae413bff2fe5c7d646a18a4b560864c82e126381 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2c_sdp_station_adc is
generic (
g_design_name : string := "lofar2_unb2c_sdp_station_adc";
g_design_note : string := "Lofar2 SDP station adc design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -67,12 +76,15 @@ entity lofar2_unb2c_sdp_station_adc is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- back transceivers (note only 12 are used in unb2c)
- BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0)
);
end lofar2_unb2c_sdp_station_adc;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
index e94d9e9a29ac5f69d5f323243a791b7d0f1fb4dd..8b4b7ca85a5134d0c1c044e04df73ab3e7ae3457 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
@@ -63,36 +63,49 @@ end tb_lofar2_unb2c_sdp_station_adc;
architecture tb of tb_lofar2_unb2c_sdp_station_adc is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
- constant c_init_bsn : natural := 17; -- some recognizable value >= 0
+ -- some recognizable value >= 0
+ constant c_init_bsn : natural := 17;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
- constant c_nof_block_per_sync : natural := 7; -- use short interval to speed up simulation
+ -- use short interval to speed up simulation
+ constant c_nof_block_per_sync : natural := 7;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_pps_period : natural := c_nof_clk_per_sync;
- constant c_percentage : real := 0.05; -- percentage that actual value may differ from expected value, due to WG rounding
- constant c_lo_factor : real := 1.0 - c_percentage; -- lower boundary
- constant c_hi_factor : real := 1.0 + c_percentage; -- higher boundary
+ -- percentage that actual value may differ from expected value, due to WG rounding
+ constant c_percentage : real := 0.05;
+ -- lower boundary
+ constant c_lo_factor : real := 1.0 - c_percentage;
+ -- higher boundary
+ constant c_hi_factor : real := 1.0 + c_percentage;
-- WG
- constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2; -- = 0.5 * FS, so in number of lsb
- constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
- constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := c_init_bsn + 2;
+ -- = 0.5 * FS, so in number of lsb
+ constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2;
+ -- in freq_unit
+ constant c_wg_freq_offset : real := 0.0 / 11.0;
+ -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ constant c_subband_sp_0 : real := 102.0;
constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_nof_clk_per_sync);
-- ADUH
- constant c_mon_buffer_nof_samples : natural := 512; -- samples per stream
+ -- samples per stream
+ constant c_mon_buffer_nof_samples : natural := 512;
-- MM
constant c_mm_file_reg_ppsh : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
@@ -140,12 +153,17 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -200,13 +218,15 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
variable v_sp_power_sum_0 : real;
variable v_sp_subband_power : real;
- variable v_W, v_T, v_U, v_S, v_B : natural; -- array indicies
+ -- array indicies
+ variable v_W, v_T, v_U, v_S, v_B : natural;
begin
-- Wait for DUT power up after reset
wait for 1 us;
@@ -214,10 +234,14 @@ begin
----------------------------------------------------------------------------
-- Enable BS
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk); -- Init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk); -- Write high part activates the init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk);
+ -- Write high part activates the init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk);
-- Release PPS pulser, to get first PPS now and to start BSN source
wait for 1 us;
@@ -231,10 +255,14 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk);
-- Read current BSN
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 downto 0), tb_clk);
@@ -245,22 +273,28 @@ begin
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
v_bsn := c_bsn_start_wg;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
----------------------------------------------------------------------------
-- Wait for enough WG data and start of sync interval
----------------------------------------------------------------------------
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 2, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 2,
c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
-- Read ADUH monitor power sum
---------------------------------------------------------------------------
- mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk); -- read low part
+ -- read low part
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk);
sp_power_sum(31 downto 0) <= rd_data;
- mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk); -- read high part
+ -- read high part
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk);
sp_power_sum(63 downto 32) <= rd_data;
proc_common_wait_some_cycles(tb_clk, 1);
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
index 02130ecf7708d27b33d450f0218a278e92a10272..c2d5cbd8e0f4683b2b4b037f0b5214a75c60f4cf 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
@@ -73,41 +73,56 @@ end tb_lofar2_unb2c_sdp_station_adc_jesd;
architecture tb of tb_lofar2_unb2c_sdp_station_adc_jesd is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
- constant c_init_bsn : natural := 17; -- some recognizable value >= 0
- constant c_si_dis : natural := 2; -- disable signal input 2 in range 0:c_sdp_S_pn_1
+ -- some recognizable value >= 0
+ constant c_init_bsn : natural := 17;
+ -- disable signal input 2 in range 0:c_sdp_S_pn_1
+ constant c_si_dis : natural := 2;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 10 ns; -- 100 ps; -- use fast tb_clk to speed up M&C
+ -- 100 ps; -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 10 ns;
constant c_nof_restarts : natural := 1;
- constant c_nof_block_per_sync : natural := 7; -- use short interval to speed up simulation
+ -- use short interval to speed up simulation
+ constant c_nof_block_per_sync : natural := 7;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_pps_period : time := c_nof_clk_per_sync * c_ext_clk_period;
- constant c_percentage : real := 0.05; -- percentage that actual value may differ from expected value, due to WG rounding
- constant c_lo_factor : real := 1.0 - c_percentage; -- lower boundary
- constant c_hi_factor : real := 1.0 + c_percentage; -- higher boundary
+ -- percentage that actual value may differ from expected value, due to WG rounding
+ constant c_percentage : real := 0.05;
+ -- lower boundary
+ constant c_lo_factor : real := 1.0 - c_percentage;
+ -- higher boundary
+ constant c_hi_factor : real := 1.0 + c_percentage;
-- Tx JESD
- constant c_nof_jesd204b_tx : natural := 3; -- <= c_sdp_S_pn = 12
+ -- <= c_sdp_S_pn = 12
+ constant c_nof_jesd204b_tx : natural := 3;
-- WG
- constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2; -- = 0.5 * FS, so in number of lsb
- constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
- constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := c_init_bsn + 2;
+ -- = 0.5 * FS, so in number of lsb
+ constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2;
+ -- in freq_unit
+ constant c_wg_freq_offset : real := 0.0 / 11.0;
+ -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ constant c_subband_sp_0 : real := 102.0;
constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_nof_clk_per_sync);
-- ADUH
- constant c_mon_buffer_nof_samples : natural := 512; -- samples per stream
+ -- samples per stream
+ constant c_mon_buffer_nof_samples : natural := 512;
-- MM
constant c_mm_file_reg_ppsh : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
@@ -274,12 +289,17 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -378,7 +398,8 @@ begin
csr_hd => OPEN,
csr_k => OPEN,
csr_l => OPEN,
- csr_lane_powerdown => open, -- out
+ -- out
+ csr_lane_powerdown => open,
csr_m => OPEN,
csr_n => OPEN,
csr_np => OPEN,
@@ -388,7 +409,8 @@ begin
csr_tx_testpattern_c => OPEN,
csr_tx_testpattern_d => OPEN,
csr_s => OPEN,
- dev_sync_n => dev_sync_n(i), -- out
+ -- out
+ dev_sync_n => dev_sync_n(i),
jesd204_tx_avs_chipselect => tx_avs_chipselect(i),
jesd204_tx_avs_address => tx_avs_address(i),
jesd204_tx_avs_read => tx_avs_read(i),
@@ -398,19 +420,29 @@ begin
jesd204_tx_avs_writedata => (others => '0'),
jesd204_tx_avs_clk => tx_avs_clk,
jesd204_tx_avs_rst_n => tx_avs_rst_n,
- jesd204_tx_dlb_data => open, -- debug/loopback testing
- jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
+ -- debug/loopback testing
+ jesd204_tx_dlb_data => open,
+ -- debug/loopback testing
+ jesd204_tx_dlb_kchar_data => open,
jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
jesd204_tx_frame_error => '0',
- jesd204_tx_int => OPEN, -- Connected to status IO in example design
- jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), -- in
- jesd204_tx_link_valid => jesd204b_tx_link_valid(i), -- in
- jesd204_tx_link_ready => jesd204b_tx_link_ready(i), -- out
- mdev_sync_n => dev_sync_n(i), -- in
- pll_locked => pll_locked, -- in
- sync_n => jesd204b_sync_adc_n(i), -- in
+ -- Connected to status IO in example design
+ jesd204_tx_int => OPEN,
+ -- in
+ jesd204_tx_link_data => jesd204b_tx_link_data_arr(i),
+ -- in
+ jesd204_tx_link_valid => jesd204b_tx_link_valid(i),
+ -- out
+ jesd204_tx_link_ready => jesd204b_tx_link_ready(i),
+ -- in
+ mdev_sync_n => dev_sync_n(i),
+ -- in
+ pll_locked => pll_locked,
+ -- in
+ sync_n => jesd204b_sync_adc_n(i),
tx_analogreset => tx_analogreset,
- tx_bonding_clocks => tx_bonding_clocks, -- : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ -- : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_bonding_clocks => tx_bonding_clocks,
tx_cal_busy => open,
tx_digitalreset => tx_digitalreset,
tx_serial_data => JESD204B_SERIAL_DATA(i downto i),
@@ -465,7 +497,8 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_offset : natural;
@@ -474,7 +507,8 @@ begin
variable v_bsn : natural;
variable v_sp_power_sum_0 : real;
variable v_sp_subband_power : real;
- variable v_W, v_T, v_U, v_S, v_B : natural; -- array indicies
+ -- array indicies
+ variable v_W, v_T, v_U, v_S, v_B : natural;
variable v_exp_input_delay : natural;
begin
dbg_restart <= 0;
@@ -494,15 +528,20 @@ begin
----------------------------------------------------------------------------
-- Enable BS
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk); -- Init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk); -- Write high part activates the init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk);
+ -- Write high part activates the init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk);
-- Release PPS pulser, to get first PPS now and to start BSN source
wait for 1 us;
pps_rst <= '0';
- dbg_bsn_source_en <= '1'; -- marker in wave window
+ -- marker in wave window
+ dbg_bsn_source_en <= '1';
---------------------------------------------------------------------------
-- Read JESD_CTRL register
@@ -523,10 +562,14 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk);
-- Read current BSN
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 downto 0), tb_clk);
@@ -537,14 +580,18 @@ begin
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
v_bsn := c_bsn_start_wg;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
----------------------------------------------------------------------------
-- Wait for enough WG data and start of sync interval
----------------------------------------------------------------------------
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 2, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 2,
c_sdp_T_sub, tb_clk);
----------------------------------------------------------------------------
@@ -575,9 +622,11 @@ begin
---------------------------------------------------------------------------
-- Read ADUH monitor power sum
---------------------------------------------------------------------------
- mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk); -- read low part
+ -- read low part
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk);
sp_power_sum(31 downto 0) <= rd_data;
- mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk); -- read high part
+ -- read high part
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk);
sp_power_sum(63 downto 32) <= rd_data;
proc_common_wait_some_cycles(tb_clk, 1);
@@ -592,10 +641,12 @@ begin
-- Try to reset via JESD_CTRL. This JESD_CTRL should be ignored.
-- Note: Awkward way to set MSbit without negative integer warning, using TO_SINT(v_word).
- dbg_jesd_ctrl_reset_ignore <= '1'; -- marker in wave window
+ -- marker in wave window
+ dbg_jesd_ctrl_reset_ignore <= '1';
-- apply JESD_CTRL reset
v_word := (others => '0');
- v_word(c_sdp_jesd_ctrl_reset_bi) := '1'; -- reset
+ -- reset
+ v_word(c_sdp_jesd_ctrl_reset_bi) := '1';
mmf_mm_bus_wr(c_mm_file_pio_jesd_ctrl, 0, TO_SINT(v_word), tb_clk);
proc_common_wait_cross_clock_domain_latency(tb_clk, ext_clk);
mmf_mm_bus_rd(c_mm_file_pio_jesd_ctrl, 0, rd_data, tb_clk);
@@ -606,7 +657,8 @@ begin
assert pio_jesd_ctrl_reset = '0' report "JESD_CTRL reset should be ignored when BSN source is on." severity ERROR;
-- remove JESD_CTRL reset
v_word := (others => '0');
- v_word(c_sdp_jesd_ctrl_reset_bi) := '0'; -- reset
+ -- reset
+ v_word(c_sdp_jesd_ctrl_reset_bi) := '0';
mmf_mm_bus_wr(c_mm_file_pio_jesd_ctrl, 0, TO_SINT(v_word), tb_clk);
proc_common_wait_cross_clock_domain_latency(tb_clk, ext_clk);
mmf_mm_bus_rd(c_mm_file_pio_jesd_ctrl, 0, rd_data, tb_clk);
@@ -629,13 +681,16 @@ begin
-- . Wait until BSN source has finished last block, use ext_clk as 200 MHz
-- equivalent for dp_clk, and wait for > 1 block of c_sdp_N_fft samples
proc_common_wait_some_cycles(ext_clk, c_sdp_N_fft * 2);
- dbg_bsn_source_en <= '0'; -- marker in wave window
+ -- marker in wave window
+ dbg_bsn_source_en <= '0';
-- 2) Reset via JESD_CTRL c_sdp_jesd_ctrl_reset_bi = 31 and read back
-- Note: Awkward way to set MSbit without negative integer warning, using TO_SINT(v_word).
- dbg_jesd_ctrl_reset <= '1'; -- marker in wave window
+ -- marker in wave window
+ dbg_jesd_ctrl_reset <= '1';
v_word := (others => '0');
- v_word(c_sdp_jesd_ctrl_reset_bi) := '1'; -- reset
+ -- reset
+ v_word(c_sdp_jesd_ctrl_reset_bi) := '1';
mmf_mm_bus_wr(c_mm_file_pio_jesd_ctrl, 0, TO_SINT(v_word), tb_clk);
proc_common_wait_cross_clock_domain_latency(tb_clk, ext_clk);
mmf_mm_bus_rd(c_mm_file_pio_jesd_ctrl, 0, rd_data, tb_clk);
@@ -667,15 +722,18 @@ begin
wait for c_pps_period;
-- . Re-enable via JESD_CTRL and read back
- v_word := (others => '0'); -- release reset
- v_word(c_si_dis) := '1'; -- disable one signal input
+ -- release reset
+ v_word := (others => '0');
+ -- disable one signal input
+ v_word(c_si_dis) := '1';
mmf_mm_bus_wr(c_mm_file_pio_jesd_ctrl, 0, TO_SINT(v_word), tb_clk);
proc_common_wait_cross_clock_domain_latency(tb_clk, ext_clk);
mmf_mm_bus_rd(c_mm_file_pio_jesd_ctrl, 0, rd_data, tb_clk);
pio_jesd_ctrl <= rd_data;
pio_jesd_ctrl_enable <= rd_data(c_sdp_jesd_ctrl_enable_w - 1 downto 0);
pio_jesd_ctrl_reset <= rd_data(c_sdp_jesd_ctrl_reset_bi);
- dbg_jesd_ctrl_reset <= '0'; -- marker in wave window
+ -- marker in wave window
+ dbg_jesd_ctrl_reset <= '0';
-- Read input delay after reset
mmf_mm_bus_rd(c_mm_file_reg_dp_shiftram, 0, rd_data, tb_clk);
@@ -696,7 +754,8 @@ begin
reg_jesd204b_csr_dev_syncn);
-- 3) Reinit the JESD204B link per signal input
- dbg_link_reinit <= '1'; -- marker in wave window
+ -- marker in wave window
+ dbg_link_reinit <= '1';
for I in 0 to c_sdp_S_pn - 1 loop
v_int := tech_jesd204b_field_rx_syncn_sysref_ctrl_link_reinit +
tech_jesd204b_field_rx_syncn_sysref_ctrl_sysref_alwayson;
@@ -718,7 +777,8 @@ begin
v_int := tech_jesd204b_field_rx_syncn_sysref_ctrl_sysref_alwayson;
mmf_mm_bus_wr(c_mm_file_jesd204b, v_offset + tech_jesd204b_field_rx_syncn_sysref_ctrl_adr, v_int, tb_clk);
end loop;
- dbg_link_reinit <= '0'; -- marker in wave window
+ -- marker in wave window
+ dbg_link_reinit <= '0';
-- Wait for a JESD204B_SYSREF pulse
wait for c_pps_period;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
index 9abb13ac1daf7f49579863db07164826d96ae873..6c423cebaacf50dd05a227dac9dbd1e05e5c2758 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2c_sdp_station_bf is
generic (
g_design_name : string := "lofar2_unb2c_sdp_station_bf";
g_design_note : string := "Lofar2 SDP station beamformer design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -64,7 +73,8 @@ entity lofar2_unb2c_sdp_station_bf is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers
QSFP_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -74,12 +84,15 @@ entity lofar2_unb2c_sdp_station_bf is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- back transceivers (note only 12 are used in unb2c)
- BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0)
);
end lofar2_unb2c_sdp_station_bf;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
index 74fa6e366d14530426c0c5a1256df0f55473062e..f68e7a7f76c689dbcf9ae4a9c90be218180cb7e2 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -154,122 +154,185 @@ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2c_sdp_station_bf is
generic (
- g_sp : natural := 3; -- WG signal path (SP) index in range(S_pn = 12)
- g_sp_ampl : real := 0.5; -- WG normalized amplitude
- g_sp_phase : real := -110.0; -- WG phase in degrees = subband phase
- g_sp_remnant_ampl : real := 0.1; -- WG normalized amplitude for remnant sp
- g_sp_remnant_phase : real := 15.0; -- WG phase in degrees for remnant sp
- g_subband : natural := 102; -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- g_beamlet : natural := c_sdp_S_sub_bf - 1; -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
- g_beamlet_scale : real := 1.0 / 2.0**9; -- g_beamlet output scale factor
- g_bf_x_gain : real := 0.7; -- g_beamlet X BF weight normalized gain for g_sp
- g_bf_y_gain : real := 0.6; -- g_beamlet Y BF weight normalized gain for g_sp
- g_bf_x_phase : real := 30.0; -- g_beamlet X BF weight phase rotation in degrees for g_sp
- g_bf_y_phase : real := 40.0; -- g_beamlet Y BF weight phase rotation in degrees for g_sp
- g_bf_remnant_x_gain : real := 0.05; -- g_beamlet X BF weight normalized gain for remnant sp
- g_bf_remnant_y_gain : real := 0.04; -- g_beamlet Y BF weight normalized gain for remnant sp
- g_bf_remnant_x_phase : real := 170.0; -- g_beamlet X BF weight phase rotation in degrees for remnant sp
- g_bf_remnant_y_phase : real := -135.0; -- g_beamlet Y BF weight phase rotation in degrees for remnant sp
- g_read_all_sub_sel : boolean := false; -- when FALSE only read subband selection for g_beamlet, to save sim time
- g_read_all_SST : boolean := false; -- when FALSE only read SST for g_subband, to save sim time
- g_read_all_BST : boolean := false -- when FALSE only read BST for g_beamlet, to save sim time
+ -- WG signal path (SP) index in range(S_pn = 12)
+ g_sp : natural := 3;
+ -- WG normalized amplitude
+ g_sp_ampl : real := 0.5;
+ -- WG phase in degrees = subband phase
+ g_sp_phase : real := -110.0;
+ -- WG normalized amplitude for remnant sp
+ g_sp_remnant_ampl : real := 0.1;
+ -- WG phase in degrees for remnant sp
+ g_sp_remnant_phase : real := 15.0;
+ -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_subband : natural := 102;
+ -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
+ g_beamlet : natural := c_sdp_S_sub_bf - 1;
+ -- g_beamlet output scale factor
+ g_beamlet_scale : real := 1.0 / 2.0**9;
+ -- g_beamlet X BF weight normalized gain for g_sp
+ g_bf_x_gain : real := 0.7;
+ -- g_beamlet Y BF weight normalized gain for g_sp
+ g_bf_y_gain : real := 0.6;
+ -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_x_phase : real := 30.0;
+ -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_bf_y_phase : real := 40.0;
+ -- g_beamlet X BF weight normalized gain for remnant sp
+ g_bf_remnant_x_gain : real := 0.05;
+ -- g_beamlet Y BF weight normalized gain for remnant sp
+ g_bf_remnant_y_gain : real := 0.04;
+ -- g_beamlet X BF weight phase rotation in degrees for remnant sp
+ g_bf_remnant_x_phase : real := 170.0;
+ -- g_beamlet Y BF weight phase rotation in degrees for remnant sp
+ g_bf_remnant_y_phase : real := -135.0;
+ -- when FALSE only read subband selection for g_beamlet, to save sim time
+ g_read_all_sub_sel : boolean := false;
+ -- when FALSE only read SST for g_subband, to save sim time
+ g_read_all_SST : boolean := false;
+ -- when FALSE only read BST for g_beamlet, to save sim time
+ g_read_all_BST : boolean := false
);
end tb_lofar2_unb2c_sdp_station_bf;
architecture tb of tb_lofar2_unb2c_sdp_station_bf is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
- constant c_gn_index : natural := c_unb_nr * 4 + c_node_nr; -- this node GN
- constant c_init_bsn : natural := 17; -- some recognizable value >= 0
- constant c_bsn_latency : natural := 5; -- used to time stimuli_done
+ -- this node GN
+ constant c_gn_index : natural := c_unb_nr * 4 + c_node_nr;
+ -- some recognizable value >= 0
+ constant c_init_bsn : natural := 17;
+ -- used to time stimuli_done
+ constant c_bsn_latency : natural := 5;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_gn_index, 8);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
constant c_mac_15_0 : std_logic_vector(15 downto 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr, 8);
- constant c_ip_15_0 : std_logic_vector(15 downto 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr + 1, 8); -- +1 to avoid IP = *.*.*.0
+ -- +1 to avoid IP = *.*.*.0
+ constant c_ip_15_0 : std_logic_vector(15 downto 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr + 1, 8);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
- constant c_mm_clk_period : time := 10 ns; -- 100 MHz internal mm_clk
+ -- 100 MHz internal mm_clk
+ constant c_mm_clk_period : time := 10 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
+ -- 644MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_nof_block_per_sync : natural := 16;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_pps_period : natural := c_nof_clk_per_sync;
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
- constant c_stat_data_sz : natural := c_wpfb_sim.stat_data_sz; -- = 2
+ -- = 2
+ constant c_stat_data_sz : natural := c_wpfb_sim.stat_data_sz;
- constant c_stat_percentage : real := 0.05; -- +-percentage margin that actual value may differ from expected value
- constant c_stat_lo_factor : real := 1.0 - c_stat_percentage; -- lower boundary
- constant c_stat_hi_factor : real := 1.0 + c_stat_percentage; -- higher boundary
+ -- +-percentage margin that actual value may differ from expected value
+ constant c_stat_percentage : real := 0.05;
+ -- lower boundary
+ constant c_stat_lo_factor : real := 1.0 - c_stat_percentage;
+ -- higher boundary
+ constant c_stat_hi_factor : real := 1.0 + c_stat_percentage;
- constant c_nof_beamlets_per_data : natural := c_sdp_cep_nof_beamlets_per_longword; -- = 2 dual pol beamlets per 64b data word
+ -- = 2 dual pol beamlets per 64b data word
+ constant c_nof_beamlets_per_data : natural := c_sdp_cep_nof_beamlets_per_longword;
- constant c_beamlet_output_delta : integer := 2; -- +-delta margin
+ -- +-delta margin
+ constant c_beamlet_output_delta : integer := 2;
-- header fields
constant c_cep_eth_src_mac : std_logic_vector(47 downto 0) := c_sdp_cep_eth_src_mac_47_16 & func_sdp_gn_index_to_mac_15_0(c_gn_index);
constant c_cep_ip_src_addr : std_logic_vector(31 downto 0) := c_sdp_cep_ip_src_addr_31_16 & func_sdp_gn_index_to_ip_15_0(c_gn_index);
constant c_cep_udp_src_port : std_logic_vector(15 downto 0) := c_sdp_cep_udp_src_port_15_8 & c_id;
- constant c_exp_ip_header_checksum : natural := 16#5BDE#; -- value obtained from rx_sdp_cep_header.ip.header_checksum in wave window
+ -- value obtained from rx_sdp_cep_header.ip.header_checksum in wave window
+ constant c_exp_ip_header_checksum : natural := 16#5BDE#;
- constant c_exp_beamlet_scale : natural := natural(g_beamlet_scale * real(c_sdp_unit_beamlet_scale)); -- c_sdp_unit_beamlet_scale = 2**15;
- constant c_exp_beamlet_index : natural := 0; -- depends on beamset bset * c_sdp_S_sub_bf
+ -- c_sdp_unit_beamlet_scale = 2**15;
+ constant c_exp_beamlet_scale : natural := natural(g_beamlet_scale * real(c_sdp_unit_beamlet_scale));
+ -- depends on beamset bset * c_sdp_S_sub_bf
+ constant c_exp_beamlet_index : natural := 0;
constant c_exp_sdp_info : t_sdp_info := (
- TO_UVEC(3, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
+ -- antenna_field_index
+ TO_UVEC(3, 6),
+ -- station_id
+ TO_UVEC(601, 10),
+ -- antenna_band_index
+ '0',
+ -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
+ x"7FFFFFFF",
+ -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ b"01",
+ -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '1',
+ -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0',
+ -- beam_repositioning_flag
+ '0',
+ -- block_period = 5120
+ x"1400"
);
-- WG
- constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := c_init_bsn + 2;
-- .ampl
- constant c_wg_ampl : natural := natural(g_sp_ampl * real(c_sdp_FS_adc)); -- in number of lsb
- constant c_wg_remnant_ampl : natural := natural(g_sp_remnant_ampl * real(c_sdp_FS_adc)); -- in number of lsb
+ -- in number of lsb
+ constant c_wg_ampl : natural := natural(g_sp_ampl * real(c_sdp_FS_adc));
+ -- in number of lsb
+ constant c_wg_remnant_ampl : natural := natural(g_sp_remnant_ampl * real(c_sdp_FS_adc));
constant c_exp_sp_power : real := real(c_wg_ampl**2) / 2.0;
constant c_exp_sp_ast : real := c_exp_sp_power * real(c_nof_clk_per_sync);
-- . phase
- constant c_subband_freq : real := real(g_subband) / real(c_sdp_N_fft); -- normalized by fs = f_adc = 200 MHz = dp_clk rate
- constant c_wg_latency : integer := c_diag_wg_latency - 0; -- -0 to account for BSN scheduler start trigger latency
- constant c_wg_phase_offset : real := 360.0 * real(c_wg_latency) * c_subband_freq; -- c_diag_wg_latency is in dp_clk cycles
- constant c_wg_phase : real := g_sp_phase + c_wg_phase_offset; -- WG phase in degrees
- constant c_wg_remnant_phase : real := g_sp_remnant_phase + c_wg_phase_offset; -- WG phase in degrees
+ -- normalized by fs = f_adc = 200 MHz = dp_clk rate
+ constant c_subband_freq : real := real(g_subband) / real(c_sdp_N_fft);
+ -- -0 to account for BSN scheduler start trigger latency
+ constant c_wg_latency : integer := c_diag_wg_latency - 0;
+ -- c_diag_wg_latency is in dp_clk cycles
+ constant c_wg_phase_offset : real := 360.0 * real(c_wg_latency) * c_subband_freq;
+ -- WG phase in degrees
+ constant c_wg_phase : real := g_sp_phase + c_wg_phase_offset;
+ -- WG phase in degrees
+ constant c_wg_remnant_phase : real := g_sp_remnant_phase + c_wg_phase_offset;
-- WPFB
constant c_pol_index : natural := g_sp mod c_sdp_Q_fft;
- constant c_pfb_index : natural := g_sp / c_sdp_Q_fft; -- only read used WPFB unit out of range(c_sdp_P_pfb = 6)
- constant c_subband_phase_offset : real := -90.0; -- WG with zero phase sinus yields subband with -90 degrees phase (negative Im, zero Re)
- constant c_subband_weight_gain : real := 1.0; -- use default unit subband weights
- constant c_subband_weight_phase : real := 0.0; -- use default unit subband weights
+ -- only read used WPFB unit out of range(c_sdp_P_pfb = 6)
+ constant c_pfb_index : natural := g_sp / c_sdp_Q_fft;
+ -- WG with zero phase sinus yields subband with -90 degrees phase (negative Im, zero Re)
+ constant c_subband_phase_offset : real := -90.0;
+ -- use default unit subband weights
+ constant c_subband_weight_gain : real := 1.0;
+ -- use default unit subband weights
+ constant c_subband_weight_phase : real := 0.0;
constant c_exp_subband_phase : real := g_sp_phase + c_subband_phase_offset + c_subband_weight_phase;
constant c_exp_subband_ampl : real := real(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio * c_subband_weight_gain;
- constant c_exp_subband_power : real := c_exp_subband_ampl**2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
+ -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
+ constant c_exp_subband_power : real := c_exp_subband_ampl**2.0;
constant c_exp_subband_sst : real := c_exp_subband_power * real(c_nof_block_per_sync);
constant c_exp_remnant_subband_phase : real := g_sp_remnant_phase + c_subband_phase_offset + c_subband_weight_phase;
constant c_exp_remnant_subband_ampl : real := real(c_wg_remnant_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio * c_subband_weight_gain;
- type t_slv_64_subbands_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_sub - 1); -- 512
- type t_slv_64_beamlets_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_beamlets_sdp - 1); -- 2*488 = 976
+ -- 512
+ type t_slv_64_subbands_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_sub - 1);
+ -- 2*488 = 976
+ type t_slv_64_beamlets_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_beamlets_sdp - 1);
-- BF X-pol and Y-pol
-- . select
- constant c_exp_beamlet_x_index : natural := g_beamlet * c_sdp_N_pol_bf; -- X index in beamset 0
- constant c_exp_beamlet_y_index : natural := g_beamlet * c_sdp_N_pol_bf + 1; -- Y index in beamset 0
+ -- X index in beamset 0
+ constant c_exp_beamlet_x_index : natural := g_beamlet * c_sdp_N_pol_bf;
+ -- Y index in beamset 0
+ constant c_exp_beamlet_y_index : natural := g_beamlet * c_sdp_N_pol_bf + 1;
-- . Beamlet weights for selected g_sp
constant c_bf_x_weight_re : integer := integer(COMPLEX_RE(g_bf_x_gain * real(c_sdp_unit_bf_weight), g_bf_x_phase));
constant c_bf_x_weight_im : integer := integer(COMPLEX_IM(g_bf_x_gain * real(c_sdp_unit_bf_weight), g_bf_x_phase));
@@ -301,9 +364,11 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
constant c_exp_beamlet_y_re : real := c_exp_beamlet_y_tuple(2);
constant c_exp_beamlet_y_im : real := c_exp_beamlet_y_tuple(3);
-- . BST
- constant c_exp_beamlet_x_power : real := c_exp_beamlet_x_ampl**2.0; -- complex signal ampl, so no divide by 2
+ -- complex signal ampl, so no divide by 2
+ constant c_exp_beamlet_x_power : real := c_exp_beamlet_x_ampl**2.0;
constant c_exp_beamlet_x_bst : real := c_exp_beamlet_x_power * real(c_nof_block_per_sync);
- constant c_exp_beamlet_y_power : real := c_exp_beamlet_y_ampl**2.0; -- complex signal ampl, so no divide by 2
+ -- complex signal ampl, so no divide by 2
+ constant c_exp_beamlet_y_power : real := c_exp_beamlet_y_ampl**2.0;
constant c_exp_beamlet_y_bst : real := c_exp_beamlet_y_power * real(c_nof_block_per_sync);
-- . Beamlet output
constant c_exp_beamlet_x_output_ampl : real := c_exp_beamlet_x_ampl * g_beamlet_scale;
@@ -347,13 +412,16 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
constant c_mm_file_reg_dp_selector : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_SELECTOR";
constant c_mm_file_ram_st_sst : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
constant c_mm_file_ram_st_bst : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_BST";
- constant c_mm_file_reg_stat_enable_bst : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_BST"; -- BST offload enable
- constant c_mm_file_reg_dp_xonoff : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF"; -- beamlet output enable
+ -- BST offload enable
+ constant c_mm_file_reg_stat_enable_bst : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_BST";
+ -- beamlet output enable
+ constant c_mm_file_reg_dp_xonoff : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF";
constant c_mm_file_ram_ss_ss_wide : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_SS_SS_WIDE";
constant c_mm_file_ram_bf_weights : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_BF_WEIGHTS";
constant c_mm_file_reg_bf_scale : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BF_SCALE";
constant c_mm_file_reg_sdp_info : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_SDP_INFO";
- constant c_mm_file_reg_hdr_dat : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_HDR_DAT"; -- c_sdp_N_beamsets = 2 beamsets
+ -- c_sdp_N_beamsets = 2 beamsets
+ constant c_mm_file_reg_hdr_dat : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_HDR_DAT";
-- Tb
signal stimuli_done : std_logic := '0';
@@ -362,8 +430,10 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
signal tb_clk : std_logic := '0';
signal rd_data : std_logic_vector(c_32 - 1 downto 0);
- signal dest_rst : std_logic := '1'; -- use separate destination rst for Rx 10GbE in tb
- signal pps_rst : std_logic := '1'; -- use separate reset to release the PPS generator
+ -- use separate destination rst for Rx 10GbE in tb
+ signal dest_rst : std_logic := '1';
+ -- use separate reset to release the PPS generator
+ signal pps_rst : std_logic := '1';
signal gen_pps : std_logic := '0';
signal in_sync : std_logic := '0';
@@ -385,7 +455,8 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
-- FSUB
-- . Read sp_ssts_arr2 = SST for one WPFB unit that processes g_sp
- signal sp_ssts_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol - 1 downto 0); -- [pol][sub], for X,Y pair of A, B
+ -- [pol][sub], for X,Y pair of A, B
+ signal sp_ssts_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol - 1 downto 0);
signal sp_sst : real := 0.0;
signal stat_data : std_logic_vector(c_longword_w - 1 downto 0);
@@ -401,7 +472,8 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
-- BF
-- . beamlet subband selection
signal sp_subband_select : natural := 0;
- signal sp_subband_select_arr : t_integer_arr(0 to c_sdp_S_sub_bf * c_sdp_N_pol - 1) := (others => -1); -- Q_fft = N_pol = 2
+ -- Q_fft = N_pol = 2
+ signal sp_subband_select_arr : t_integer_arr(0 to c_sdp_S_sub_bf * c_sdp_N_pol - 1) := (others => -1);
-- . beamlet X-pol
signal sp_bf_x_weights_re_arr : t_integer_arr(0 to c_sdp_S_pn - 1) := (others => 0);
@@ -415,9 +487,12 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
signal sp_bf_y_weights_phase_arr : t_real_arr(0 to c_sdp_S_pn - 1) := (others => 0.0);
-- . BST
- signal bsts_arr2 : t_slv_64_beamlets_arr(c_sdp_N_pol_bf - 1 downto 0); -- [pol_bf][blet]
- signal bst_x_arr : t_real_arr(0 to c_sdp_N_beamsets - 1) := (others => 0.0); -- [bset] for BF X pol
- signal bst_y_arr : t_real_arr(0 to c_sdp_N_beamsets - 1) := (others => 0.0); -- [bset] for BF Y pol
+ -- [pol_bf][blet]
+ signal bsts_arr2 : t_slv_64_beamlets_arr(c_sdp_N_pol_bf - 1 downto 0);
+ -- [bset] for BF X pol
+ signal bst_x_arr : t_real_arr(0 to c_sdp_N_beamsets - 1) := (others => 0.0);
+ -- [bset] for BF Y pol
+ signal bst_y_arr : t_real_arr(0 to c_sdp_N_beamsets - 1) := (others => 0.0);
-- CEP model
-- . 10GbE
@@ -441,18 +516,23 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
signal exp_payload_error : std_logic := '0';
-- Beamlets packets data
- signal rx_beamlet_data : std_logic_vector(c_longword_w - 1 downto 0); -- 64 bit
+ -- 64 bit
+ signal rx_beamlet_data : std_logic_vector(c_longword_w - 1 downto 0);
signal rx_beamlet_sosi : t_dp_sosi := c_dp_sosi_rst;
signal rx_beamlet_sop_cnt : natural := 0;
signal rx_beamlet_eop_cnt : natural := 0;
- signal rx_beamlet_arr_re : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet - 1 downto 0); -- [3:0]
- signal rx_beamlet_arr_im : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet - 1 downto 0); -- [3:0]
+ -- [3:0]
+ signal rx_beamlet_arr_re : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet - 1 downto 0);
+ -- [3:0]
+ signal rx_beamlet_arr_im : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet - 1 downto 0);
signal rx_beamlet_cnt : natural;
signal rx_beamlet_valid : std_logic;
- signal rx_beamlet_list_re : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf - 1 downto 0); -- [488 * 2-1:0] = [975:0]
- signal rx_beamlet_list_im : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf - 1 downto 0); -- [488 * 2-1:0] = [975:0]
+ -- [488 * 2-1:0] = [975:0]
+ signal rx_beamlet_list_re : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf - 1 downto 0);
+ -- [488 * 2-1:0] = [975:0]
+ signal rx_beamlet_list_im : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf - 1 downto 0);
signal rx_beamlet_x_output_re : integer;
signal rx_beamlet_x_output_im : integer;
@@ -485,14 +565,20 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
- SA_CLK <= not SA_CLK after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ SA_CLK <= not SA_CLK after c_sa_clk_period / 2;
dest_rst <= '0' after c_ext_clk_period * 10;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -574,9 +660,12 @@ begin
port map (
-- Transceiver PLL reference clock
tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => tr_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => tr_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156,
-- MM interface
mm_rst => dest_rst,
@@ -623,14 +712,17 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
variable v_data_lo, v_data_hi : std_logic_vector(c_word_w - 1 downto 0);
variable v_stat_data : std_logic_vector(c_longword_w - 1 downto 0);
- variable v_len, v_span, v_offset, v_addr, v_sel : natural; -- address ranges, indices
- variable v_W, v_P, v_PB, v_S, v_A, v_B, v_G : natural; -- array indicies
+ -- address ranges, indices
+ variable v_len, v_span, v_offset, v_addr, v_sel : natural;
+ -- array indicies
+ variable v_W, v_P, v_PB, v_S, v_A, v_B, v_G : natural;
variable v_re, v_im, v_weight : integer;
variable v_re_exp, v_im_exp : real := 0.0;
begin
@@ -756,12 +848,16 @@ begin
-- Write tb defaults
-- . Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on c_gn_index
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 39, TO_UINT(c_cep_eth_src_mac(47 downto 32)), tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 38, TO_SINT(c_cep_eth_src_mac(31 downto 0)), tb_clk); -- use signed to fit 32 b in INTEGER
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 26, TO_SINT(c_cep_ip_src_addr), tb_clk); -- use signed to fit 32 b in INTEGER
+ -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 38, TO_SINT(c_cep_eth_src_mac(31 downto 0)), tb_clk);
+ -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 26, TO_SINT(c_cep_ip_src_addr), tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 24, TO_UINT(c_cep_udp_src_port), tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 41, TO_UINT(c_sdp_cep_eth_dst_mac(47 downto 32)), tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 40, TO_SINT(c_sdp_cep_eth_dst_mac(31 downto 0)), tb_clk); -- use signed to fit 32 b in INTEGER
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 25, TO_SINT(c_sdp_cep_ip_dst_addr), tb_clk); -- use signed to fit 32 b in INTEGER
+ -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 40, TO_SINT(c_sdp_cep_eth_dst_mac(31 downto 0)), tb_clk);
+ -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 25, TO_SINT(c_sdp_cep_ip_dst_addr), tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 23, TO_UINT(c_sdp_cep_udp_dst_port), tb_clk);
proc_common_wait_cross_clock_domain_latency(c_mm_clk_period, c_ext_clk_period, c_common_cross_clock_domain_latency * 2);
@@ -802,10 +898,14 @@ begin
----------------------------------------------------------------------------
-- Enable BS
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk); -- Init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk); -- Write high part activates the init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk);
+ -- Write high part activates the init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk);
-- Release PPS pulser, to get first PPS now and to start BSN source
wait for 1 us;
@@ -824,16 +924,24 @@ begin
v_offset := S * c_mm_span_reg_diag_wg;
if S = g_sp then
-- Strong WG signal at g_sp
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk);
else
-- Weak WG signal on all other (remnant) SP
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_remnant_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_remnant_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_remnant_phase * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_remnant_ampl) * c_sdp_wg_ampl_lsb), tb_clk);
end if;
end loop;
@@ -846,8 +954,10 @@ begin
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
v_bsn := c_bsn_start_wg;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
----------------------------------------------------------------------------
-- Read weighted subband selector
@@ -879,7 +989,8 @@ begin
-- . MM format: (uint16)RAM_SS_SS_WIDE[N_beamsets][A_pn]_[S_sub_bf][Q_fft], Q_fft = N_pol = 2
-- . write selection, only for g_beamlet to save sim time
- v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf); -- = 1024
+ -- = 1024
+ v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf);
for U in 0 to c_sdp_N_beamsets - 1 loop
-- Same selection for both beamsets
-- Select beamlet g_beamlet to subband g_subband
@@ -905,13 +1016,15 @@ begin
mmf_mm_bus_rd(c_mm_file_ram_ss_ss_wide, v_addr, rd_data, tb_clk);
v_sel := (TO_UINT(rd_data) - v_P) / c_sdp_N_pol;
sp_subband_select_arr(B * c_sdp_N_pol + v_P) <= v_sel;
- sp_subband_select <= v_sel; -- for time series view in Wave window
+ -- for time series view in Wave window
+ sp_subband_select <= v_sel;
end if;
end loop;
end loop;
proc_common_wait_some_cycles(tb_clk, 1);
assert sp_subband_select_arr(g_beamlet * c_sdp_N_pol + v_P) = g_subband report "Wrong subband select at beamlet index." severity ERROR;
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
----------------------------------------------------------------------------
-- Write beamlet weight for g_beamlet in S_sub_bf
@@ -919,7 +1032,8 @@ begin
-- . MM format: (cint16)RAM_BF_WEIGHTS[N_beamsets][N_pol_bf][A_pn]_[N_pol][S_sub_bf]
-- . write BF weights, only for g_beamlet to save sim time
- v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf); -- = 1024
+ -- = 1024
+ v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf);
for U in 0 to c_sdp_N_beamsets - 1 loop
-- Same BF weights for both beamsets
for PB in 0 to c_sdp_N_pol_bf - 1 loop
@@ -945,22 +1059,32 @@ begin
end if;
-- Only need to set BF weight for g_beamlet, keep other beamlet BF weights at rst
-- default (= unit weight in sim).
- v_addr := g_beamlet; -- beamlet index
- v_addr := v_addr + P * c_sdp_S_sub_bf; -- antenna input polarization address offset
- v_addr := v_addr + A * v_span; -- antenna input address offset
- v_addr := v_addr + PB * c_sdp_A_pn * v_span; -- beamlet polarization address offset
- v_addr := v_addr + U * c_mm_span_ram_bf_weights; -- beamset address offset
+ -- beamlet index
+ v_addr := g_beamlet;
+ -- antenna input polarization address offset
+ v_addr := v_addr + P * c_sdp_S_sub_bf;
+ -- antenna input address offset
+ v_addr := v_addr + A * v_span;
+ -- beamlet polarization address offset
+ v_addr := v_addr + PB * c_sdp_A_pn * v_span;
+ -- beamset address offset
+ v_addr := v_addr + U * c_mm_span_ram_bf_weights;
mmf_mm_bus_wr(c_mm_file_ram_bf_weights, v_addr, v_weight, tb_clk);
-- Use v_weight = 0 for default beamlet subband selection at g_subband to force beamlet to 0,
-- or comment v_weight = 0 line to use same v_weight as for g_beamlet.
if g_beamlet /= g_subband then
v_weight := 0;
- v_addr := g_subband; -- beamlet index
- v_addr := v_addr + P * c_sdp_S_sub_bf; -- antenna input polarization address offset
- v_addr := v_addr + A * v_span; -- antenna input address offset
- v_addr := v_addr + PB * c_sdp_A_pn * v_span; -- beamlet polarization address offset
- v_addr := v_addr + U * c_mm_span_ram_bf_weights; -- beamset address offset
+ -- beamlet index
+ v_addr := g_subband;
+ -- antenna input polarization address offset
+ v_addr := v_addr + P * c_sdp_S_sub_bf;
+ -- antenna input address offset
+ v_addr := v_addr + A * v_span;
+ -- beamlet polarization address offset
+ v_addr := v_addr + PB * c_sdp_A_pn * v_span;
+ -- beamset address offset
+ v_addr := v_addr + U * c_mm_span_ram_bf_weights;
mmf_mm_bus_wr(c_mm_file_ram_bf_weights, v_addr, v_weight, tb_clk);
end if;
end loop;
@@ -973,11 +1097,16 @@ begin
for PB in 0 to c_sdp_N_pol_bf - 1 loop
for A in 0 to c_sdp_A_pn - 1 loop
for P in 0 to c_sdp_N_pol - 1 loop
- v_addr := g_beamlet; -- beamlet index
- v_addr := v_addr + P * c_sdp_S_sub_bf; -- antenna input polarization address offset
- v_addr := v_addr + A * v_span; -- antenna input address offset
- v_addr := v_addr + PB * c_sdp_A_pn * v_span; -- beamlet polarization address offset
- v_addr := v_addr + U * c_mm_span_ram_bf_weights; -- beamset address offset
+ -- beamlet index
+ v_addr := g_beamlet;
+ -- antenna input polarization address offset
+ v_addr := v_addr + P * c_sdp_S_sub_bf;
+ -- antenna input address offset
+ v_addr := v_addr + A * v_span;
+ -- beamlet polarization address offset
+ v_addr := v_addr + PB * c_sdp_A_pn * v_span;
+ -- beamset address offset
+ v_addr := v_addr + U * c_mm_span_ram_bf_weights;
mmf_mm_bus_rd(c_mm_file_ram_bf_weights, v_addr, rd_data, tb_clk);
v_re := unpack_complex_re(rd_data, c_sdp_W_bf_weight);
v_im := unpack_complex_im(rd_data, c_sdp_W_bf_weight);
@@ -1000,7 +1129,8 @@ begin
end loop;
end loop;
proc_common_wait_some_cycles(tb_clk, 1);
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
----------------------------------------------------------------------------
-- Wait for enough WG data and start of sync interval
@@ -1026,13 +1156,19 @@ begin
-- . the subbands are output alternately so A0 B0 A1 B1 ... A511 B511 for input A, B
-- . the subband statistics multiple WPFB units appear in order in the ram_st_sst address map
-- . the subband statistics are stored first lo word 0 then hi word 1
- v_len := c_sdp_N_sub * c_sdp_N_pol * c_stat_data_sz; -- 2048 = 512 * 2 * 64/32
- v_span := true_log_pow2(v_len); -- = 2048
+ -- 2048 = 512 * 2 * 64/32
+ v_len := c_sdp_N_sub * c_sdp_N_pol * c_stat_data_sz;
+ -- = 2048
+ v_span := true_log_pow2(v_len);
for I in 0 to v_len - 1 loop
- v_W := I mod c_stat_data_sz; -- 0, 1 per statistics word, word index
- v_P := (I / c_stat_data_sz) mod c_sdp_N_pol; -- 0, 1 per SP pol, polarization index
- v_B := I / (c_sdp_N_pol * c_stat_data_sz); -- subband index, range(N_sub = 512) per dual pol
- v_addr := I + c_pfb_index * v_span; -- MM address
+ -- 0, 1 per statistics word, word index
+ v_W := I mod c_stat_data_sz;
+ -- 0, 1 per SP pol, polarization index
+ v_P := (I / c_stat_data_sz) mod c_sdp_N_pol;
+ -- subband index, range(N_sub = 512) per dual pol
+ v_B := I / (c_sdp_N_pol * c_stat_data_sz);
+ -- MM address
+ v_addr := I + c_pfb_index * v_span;
-- Only read SST for g_subband for dual pol SP, to save sim time
if g_read_all_SST = true or v_B = g_subband then
if v_W = 0 then
@@ -1046,7 +1182,8 @@ begin
v_stat_data := v_data_hi & v_data_lo;
sp_ssts_arr2(v_P)(v_B) <= v_stat_data;
- stat_data <= v_stat_data; -- for time series view in Wave window
+ -- for time series view in Wave window
+ stat_data <= v_stat_data;
end if;
end if;
end loop;
@@ -1055,7 +1192,8 @@ begin
-- Subband power of g_subband in g_sp
sp_sst <= TO_UREAL(sp_ssts_arr2(c_pol_index)(g_subband));
proc_common_wait_some_cycles(tb_clk, 1);
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
---------------------------------------------------------------------------
-- Read beamlet statistics
@@ -1065,15 +1203,22 @@ begin
-- . the beamlets are output alternately so X0 Y0 X1 Y1 ... X487 Y487 for polarizations X, Y
-- . the beamlet statistics for multiple beamsets appear in order in the ram_st_bst address map
-- . the beamlet statistics are stored first lo word 0 then hi word 1
- v_len := c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_stat_data_sz; -- = 1952 = 488 * 2 * 64/32
- v_span := true_log_pow2(v_len); -- = 2048
+ -- = 1952 = 488 * 2 * 64/32
+ v_len := c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_stat_data_sz;
+ -- = 2048
+ v_span := true_log_pow2(v_len);
for U in 0 to c_sdp_N_beamsets - 1 loop
for I in 0 to v_len - 1 loop
- v_W := I mod c_stat_data_sz; -- 0, 1 per statistics word, word index
- v_PB := (I / c_stat_data_sz) mod c_sdp_N_pol_bf; -- 0, 1 per BF pol, polarization index
- v_B := I / (c_sdp_N_pol_bf * c_stat_data_sz); -- beamlet index in beamset, range(S_sub_bf = 488) per dual pol
- v_G := v_B + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
- v_addr := I + U * v_span; -- MM address
+ -- 0, 1 per statistics word, word index
+ v_W := I mod c_stat_data_sz;
+ -- 0, 1 per BF pol, polarization index
+ v_PB := (I / c_stat_data_sz) mod c_sdp_N_pol_bf;
+ -- beamlet index in beamset, range(S_sub_bf = 488) per dual pol
+ v_B := I / (c_sdp_N_pol_bf * c_stat_data_sz);
+ -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ v_G := v_B + U * c_sdp_S_sub_bf;
+ -- MM address
+ v_addr := I + U * v_span;
--Only read BST for g_beamlet and dual pol_bf 0 and 1 and for both beamsets, to save sim time
if g_read_all_BST = true or v_B = g_beamlet then
if v_W = 0 then
@@ -1087,7 +1232,8 @@ begin
v_stat_data := v_data_hi & v_data_lo;
bsts_arr2(v_PB)(v_G) <= v_stat_data;
- stat_data <= v_stat_data; -- for time series view in Wave window
+ -- for time series view in Wave window
+ stat_data <= v_stat_data;
end if;
end if;
end loop;
@@ -1096,12 +1242,16 @@ begin
-- Beamlet power of g_beamlet X and Y, same for both beamsets
for U in 0 to c_sdp_N_beamsets - 1 loop
- v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
- bst_x_arr(U) <= TO_UREAL(bsts_arr2(0)(v_G)); -- X pol beamlet
- bst_y_arr(U) <= TO_UREAL(bsts_arr2(1)(v_G)); -- Y pol beamlet
+ -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ v_G := g_beamlet + U * c_sdp_S_sub_bf;
+ -- X pol beamlet
+ bst_x_arr(U) <= TO_UREAL(bsts_arr2(0)(v_G));
+ -- Y pol beamlet
+ bst_y_arr(U) <= TO_UREAL(bsts_arr2(1)(v_G));
end loop;
proc_common_wait_some_cycles(tb_clk, 1);
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
---------------------------------------------------------------------------
-- Log WG, subband and beamlet statistics
@@ -1140,13 +1290,15 @@ begin
print_str(" . c_exp_beamlet_y_bst = " & real_to_str(c_exp_beamlet_y_bst, 20, 1));
print_str("");
for U in 0 to c_sdp_N_beamsets - 1 loop
- v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ v_G := g_beamlet + U * c_sdp_S_sub_bf;
print_str(" . bst_x_arr(" & integer'image(v_G) & ") = " & real_to_str(bst_x_arr(U), 20, 1));
print_str(" . bst_y_arr(" & integer'image(v_G) & ") = " & real_to_str(bst_y_arr(U), 20, 1));
end loop;
print_str("");
for U in 0 to c_sdp_N_beamsets - 1 loop
- v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ v_G := g_beamlet + U * c_sdp_S_sub_bf;
print_str(" . bst_x_arr(" & integer'image(v_G) & ") / c_exp_beamlet_x_bst = " & real_to_str(bst_x_arr(U) / c_exp_beamlet_x_bst, 20, 6));
print_str(" . bst_y_arr(" & integer'image(v_G) & ") / c_exp_beamlet_y_bst = " & real_to_str(bst_y_arr(U) / c_exp_beamlet_y_bst, 20, 6));
end loop;
@@ -1216,7 +1368,8 @@ begin
-- End Simulation
---------------------------------------------------------------------------
tb_almost_end <= '1';
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
proc_common_stop_simulation(true, ext_clk, tb_almost_end, tb_end);
wait;
end process;
@@ -1231,17 +1384,20 @@ begin
if rising_edge(ext_clk) then
-- Count rx_beamlet_sosi packets
if rx_beamlet_sosi.sop = '1' then
- rx_beamlet_sop_cnt <= rx_beamlet_sop_cnt + 1; -- early count
+ -- early count
+ rx_beamlet_sop_cnt <= rx_beamlet_sop_cnt + 1;
end if;
if rx_beamlet_sosi.eop = '1' then
- rx_beamlet_eop_cnt <= rx_beamlet_eop_cnt + 1; -- after count
+ -- after count
+ rx_beamlet_eop_cnt <= rx_beamlet_eop_cnt + 1;
end if;
end if;
end process;
-- Count sync intervals using in_sosi.sync, because there is no rx_beamlet_sosi.sync
in_sync_cnt <= in_sync_cnt + 1 when rising_edge(ext_clk) and in_sync = '1';
- test_sync_cnt <= in_sync_cnt - 1; -- optionally adjust to fit rx_beamlet_sosi
+ -- optionally adjust to fit rx_beamlet_sosi
+ test_sync_cnt <= in_sync_cnt - 1;
-- Prepare exp_sdp_cep_header before rx_beamlet_sosi.eop, so that
-- p_verify_cep_header can verify it at rx_beamlet_sosi.eop.
@@ -1325,23 +1481,31 @@ begin
proc_common_wait_until_high(ext_clk, rx_beamlet_sosi.valid);
rx_beamlet_valid <= '1';
-- Capture rx beamlets per longword in rx_beamlet_arr, for time series view in Wave window
- rx_beamlet_arr_re(0) <= rx_beamlet_sosi.data(63 downto 56); -- X
+ -- X
+ rx_beamlet_arr_re(0) <= rx_beamlet_sosi.data(63 downto 56);
rx_beamlet_arr_im(0) <= rx_beamlet_sosi.data(55 downto 48);
- rx_beamlet_arr_re(1) <= rx_beamlet_sosi.data(47 downto 40); -- Y
+ -- Y
+ rx_beamlet_arr_re(1) <= rx_beamlet_sosi.data(47 downto 40);
rx_beamlet_arr_im(1) <= rx_beamlet_sosi.data(39 downto 32);
- rx_beamlet_arr_re(2) <= rx_beamlet_sosi.data(31 downto 24); -- X
+ -- X
+ rx_beamlet_arr_re(2) <= rx_beamlet_sosi.data(31 downto 24);
rx_beamlet_arr_im(2) <= rx_beamlet_sosi.data(23 downto 16);
- rx_beamlet_arr_re(3) <= rx_beamlet_sosi.data(15 downto 8); -- Y
+ -- Y
+ rx_beamlet_arr_re(3) <= rx_beamlet_sosi.data(15 downto 8);
rx_beamlet_arr_im(3) <= rx_beamlet_sosi.data( 7 downto 0);
if I < c_sdp_cep_nof_beamlets_per_block / c_nof_beamlets_per_data then
-- Only capture the first beamlets block of each packet in rx_beamlet_list
- rx_beamlet_list_re(I * 4 + 0) <= rx_beamlet_sosi.data(63 downto 56); -- X
+ -- X
+ rx_beamlet_list_re(I * 4 + 0) <= rx_beamlet_sosi.data(63 downto 56);
rx_beamlet_list_im(I * 4 + 0) <= rx_beamlet_sosi.data(55 downto 48);
- rx_beamlet_list_re(I * 4 + 1) <= rx_beamlet_sosi.data(47 downto 40); -- Y
+ -- Y
+ rx_beamlet_list_re(I * 4 + 1) <= rx_beamlet_sosi.data(47 downto 40);
rx_beamlet_list_im(I * 4 + 1) <= rx_beamlet_sosi.data(39 downto 32);
- rx_beamlet_list_re(I * 4 + 2) <= rx_beamlet_sosi.data(31 downto 24); -- X
+ -- X
+ rx_beamlet_list_re(I * 4 + 2) <= rx_beamlet_sosi.data(31 downto 24);
rx_beamlet_list_im(I * 4 + 2) <= rx_beamlet_sosi.data(23 downto 16);
- rx_beamlet_list_re(I * 4 + 3) <= rx_beamlet_sosi.data(15 downto 8); -- Y
+ -- Y
+ rx_beamlet_list_re(I * 4 + 3) <= rx_beamlet_sosi.data(15 downto 8);
rx_beamlet_list_im(I * 4 + 3) <= rx_beamlet_sosi.data( 7 downto 0);
end if;
proc_common_wait_until_high(ext_clk, rx_beamlet_sosi.valid);
@@ -1350,7 +1514,8 @@ begin
-- contains no WAIT statement.
wait until rising_edge(ext_clk);
rx_beamlet_valid <= '0';
- rx_beamlet_cnt <= (rx_beamlet_cnt + c_nof_beamlets_per_data) mod c_sdp_cep_nof_beamlets_per_block; -- 4 blocks/packet
+ -- 4 blocks/packet
+ rx_beamlet_cnt <= (rx_beamlet_cnt + c_nof_beamlets_per_data) mod c_sdp_cep_nof_beamlets_per_block;
end loop;
end process;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
index 17d6d80420055ba503fdec77b55034b2de8d537c..a52c757a9bab0d4ff4363adbafe84f85d9516534 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
@@ -59,39 +59,54 @@ end tb_lofar2_unb2c_sdp_station_bf_bst_offload;
architecture tb of tb_lofar2_unb2c_sdp_station_bf_bst_offload is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_gn_nr : natural := c_unb_nr * 4 + c_node_nr;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_gn_nr, 8);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
- constant c_mm_clk_period : time := 10 ns; -- 100 MHz internal mm_clk
+ -- 100 MHz internal mm_clk
+ constant c_mm_clk_period : time := 10 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
- constant c_nof_block_per_sync : natural := 16; -- long enough to stream out udp data
+ -- long enough to stream out udp data
+ constant c_nof_block_per_sync : natural := 16;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_pps_period : natural := c_nof_clk_per_sync;
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
constant c_nof_sync : natural := 1;
-- header fields
- constant c_exp_beamlet_index : natural := 0; -- depends on beamset bset * c_sdp_S_sub_bf
+ -- depends on beamset bset * c_sdp_S_sub_bf
+ constant c_exp_beamlet_index : natural := 0;
constant c_exp_sdp_info : t_sdp_info := (
- TO_UVEC(3, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
+ -- antenna_field_index
+ TO_UVEC(3, 6),
+ -- station_id
+ TO_UVEC(601, 10),
+ -- antenna_band_index
+ '0',
+ -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
+ x"7FFFFFFF",
+ -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ b"01",
+ -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '1',
+ -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0',
+ -- beam_repositioning_flag
+ '0',
+ -- block_period = 5120
+ x"1400"
);
-- MM
@@ -108,16 +123,21 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_bst_offload is
signal eth_done : std_logic := '0';
-- . 1GbE output
- constant c_eth_check_nof_packets : natural := c_nof_sync * 1; -- 1 received packet per sync interval
- constant c_eth_header_size : natural := 19; -- words
- constant c_eth_crc_size : natural := 1; -- word
- constant c_eth_packet_size : natural := c_eth_header_size + c_eth_crc_size + (c_sdp_W_statistic / c_word_w) * c_sdp_S_sub_bf * c_sdp_N_pol; -- 20 + 2 * 488 * 2 = 1972
+ -- 1 received packet per sync interval
+ constant c_eth_check_nof_packets : natural := c_nof_sync * 1;
+ -- words
+ constant c_eth_header_size : natural := 19;
+ -- word
+ constant c_eth_crc_size : natural := 1;
+ -- 20 + 2 * 488 * 2 = 1972
+ constant c_eth_packet_size : natural := c_eth_header_size + c_eth_crc_size + (c_sdp_W_statistic / c_word_w) * c_sdp_S_sub_bf * c_sdp_N_pol;
constant c_eth_check_nof_valid : natural := c_eth_check_nof_packets * c_eth_packet_size;
-- eth statistics should be done after c_nof_sync + 1 intervals (+1 because first new_interval is skipped)
constant c_eth_runtime_timeout : time := (c_nof_sync + 2) * c_nof_clk_per_sync * c_ext_clk_period;
- constant c_exp_ip_header_checksum : natural := 16#C76C#; -- value obtained from rx_sdp_stat_header.ip.header_checksum in wave window
+ -- value obtained from rx_sdp_stat_header.ip.header_checksum in wave window
+ constant c_exp_ip_header_checksum : natural := 16#C76C#;
-- DUT
signal ext_clk : std_logic := '0';
@@ -155,12 +175,17 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -215,7 +240,8 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
begin
@@ -227,8 +253,10 @@ begin
-- Offload destination MAC/IP/UDP
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_stat_hdr_dat_bst, 41, TO_UINT(c_sdp_stat_eth_dst_mac(47 downto 32)), tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_stat_hdr_dat_bst, 40, TO_SINT(c_sdp_stat_eth_dst_mac(31 downto 0)), tb_clk); -- use signed to fit 32 b in INTEGER
- mmf_mm_bus_wr(c_mm_file_reg_stat_hdr_dat_bst, 25, TO_SINT(c_sdp_stat_ip_dst_addr), tb_clk); -- use signed to fit 32 b in INTEGER
+ -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_stat_hdr_dat_bst, 40, TO_SINT(c_sdp_stat_eth_dst_mac(31 downto 0)), tb_clk);
+ -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_stat_hdr_dat_bst, 25, TO_SINT(c_sdp_stat_ip_dst_addr), tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_stat_hdr_dat_bst, 23, TO_UINT(c_sdp_stat_udp_dst_port), tb_clk);
proc_common_wait_cross_clock_domain_latency(c_mm_clk_period, c_ext_clk_period);
@@ -246,14 +274,18 @@ begin
-- Enable BSN
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk); -- Enable BSN immediately
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BSN immediately
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk);
----------------------------------------------------------------------------
-- Offload enable
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_stat_enable_bst, 0, 1, tb_clk); -- only beamset 0
+ -- only beamset 0
+ mmf_mm_bus_wr(c_mm_file_reg_stat_enable_bst, 0, 1, tb_clk);
-- wait for udp offload is done
proc_common_wait_until_high(ext_clk, eth_done);
@@ -311,18 +343,25 @@ begin
rx_sdp_stat_header <= func_sdp_map_stat_header(rx_hdr_fields_raw);
- exp_sdp_stat_header <= func_sdp_compose_stat_header(c_exp_ip_header_checksum, -- calculated by IO eth
+ -- calculated by IO eth
+ exp_sdp_stat_header <= func_sdp_compose_stat_header(c_exp_ip_header_checksum,
c_exp_sdp_info,
"BST",
- '1', -- fixed '1' for BST and XST, weighted_subbands_flag
+ -- fixed '1' for BST and XST, weighted_subbands_flag
+ '1',
c_gn_nr,
c_nof_block_per_sync,
- 0, -- not used for BST, sst_signal_input
+ -- not used for BST, sst_signal_input
+ 0,
c_exp_beamlet_index,
- 0, -- not used for BST, subband_index
- 0, -- not used for BST, xst_signal_input_A
- 0, -- not used for BST, xst_signal_input_B
- 0); -- dp_bsn
+ -- not used for BST, subband_index
+ 0,
+ -- not used for BST, xst_signal_input_A
+ 0,
+ -- not used for BST, xst_signal_input_B
+ 0,
+ -- dp_bsn
+ 0);
p_verify_header : process(rx_offload_sosi)
variable v_bool : boolean;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
index b85519e4bd8305f112efcc0135334b271e4b60b7..1361a56b9da4348b0d1dfefae3fe2307d656c757 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -34,27 +34,46 @@ entity tb_tb_lofar2_unb2c_sdp_station_bf is
end tb_tb_lofar2_unb2c_sdp_station_bf;
architecture tb of tb_tb_lofar2_unb2c_sdp_station_bf is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
u_bf : entity work.tb_lofar2_unb2c_sdp_station_bf
generic map (
- g_sp => 3, -- WG signal path (SP) index in range(S_pn = 12)
- g_sp_ampl => 0.5, -- WG normalized amplitude
- g_sp_phase => -110.0, -- WG phase in degrees = subband phase
- g_sp_remnant_ampl => 0.1, -- WG normalized amplitude for remnant sp
- g_sp_remnant_phase => 15.0, -- WG phase in degrees for remnant sp
- g_subband => 102, -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- g_beamlet => c_sdp_S_sub_bf - 1, -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
- g_beamlet_scale => 1.0 / 2.0**9, -- g_beamlet output scale factor
- g_bf_x_gain => 0.7, -- g_beamlet X BF weight normalized gain for g_sp
- g_bf_y_gain => 0.6, -- g_beamlet Y BF weight normalized gain for g_sp
- g_bf_x_phase => 30.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
- g_bf_y_phase => 40.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
- g_bf_remnant_x_gain => 0.05, -- g_beamlet X BF weight normalized gain for remnant sp
- g_bf_remnant_y_gain => 0.04, -- g_beamlet Y BF weight normalized gain for remnant sp
- g_bf_remnant_x_phase => 170.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
- g_bf_remnant_y_phase => -135.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
- g_read_all_SST => false, -- when FALSE only read SST for g_subband, to save sim time
- g_read_all_BST => false -- when FALSE only read BST for g_beamlet, to save sim time
+ -- WG signal path (SP) index in range(S_pn = 12)
+ g_sp => 3,
+ -- WG normalized amplitude
+ g_sp_ampl => 0.5,
+ -- WG phase in degrees = subband phase
+ g_sp_phase => -110.0,
+ -- WG normalized amplitude for remnant sp
+ g_sp_remnant_ampl => 0.1,
+ -- WG phase in degrees for remnant sp
+ g_sp_remnant_phase => 15.0,
+ -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_subband => 102,
+ -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
+ g_beamlet => c_sdp_S_sub_bf - 1,
+ -- g_beamlet output scale factor
+ g_beamlet_scale => 1.0 / 2.0**9,
+ -- g_beamlet X BF weight normalized gain for g_sp
+ g_bf_x_gain => 0.7,
+ -- g_beamlet Y BF weight normalized gain for g_sp
+ g_bf_y_gain => 0.6,
+ -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_x_phase => 30.0,
+ -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_bf_y_phase => 40.0,
+ -- g_beamlet X BF weight normalized gain for remnant sp
+ g_bf_remnant_x_gain => 0.05,
+ -- g_beamlet Y BF weight normalized gain for remnant sp
+ g_bf_remnant_y_gain => 0.04,
+ -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_remnant_x_phase => 170.0,
+ -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_bf_remnant_y_phase => -135.0,
+ -- when FALSE only read SST for g_subband, to save sim time
+ g_read_all_SST => false,
+ -- when FALSE only read BST for g_beamlet, to save sim time
+ g_read_all_BST => false
);
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
index 2292509910d6d2468f946f75ee0c52bb5cbb5a07..f4fd55796734410acba39335a03ae14984c1bb13 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2c_sdp_station_bf is
generic (
g_design_name : string := "lofar2_unb2c_sdp_station_bf";
g_design_note : string := "Lofar2 SDP station beamformer design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -64,7 +73,8 @@ entity lofar2_unb2c_sdp_station_bf is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP0 for Ring.
QSFP_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -78,18 +88,22 @@ entity lofar2_unb2c_sdp_station_bf is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (note only 12 are used in unb2c)
- BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0)
);
end lofar2_unb2c_sdp_station_bf;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
index 351a0af16c45536bcdb590081907ba511f696b98..d2e9abc090e34cc387857068d13a319f038b92c4 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
@@ -146,135 +146,204 @@ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2c_sdp_station_bf_ring is
generic (
- g_first_gn : natural := 1; -- first global node (GN) in ring
- g_nof_rn : natural := 2; -- nof ring nodes (RN) in ring
- g_global_sp : natural := 15; -- WG global signal path (SP) index in range [c_first_sp : c_last_sp]
- g_sp_ampl : real := 0.5; -- WG normalized amplitude
- g_sp_phase : real := -110.0; -- WG phase in degrees = subband phase
- g_sp_remnant_ampl : real := 0.1; -- WG normalized amplitude for remnant sp
- g_sp_remnant_phase : real := 15.0; -- WG phase in degrees for remnant sp
- g_subband : natural := 102; -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- g_beamlet : natural := c_sdp_S_sub_bf - 1; -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
- g_beamlet_scale : real := 1.0 / 2.0**9; -- g_beamlet output scale factor
- g_bf_x_gain : real := 0.7; -- g_beamlet X BF weight normalized gain for g_global_sp
- g_bf_y_gain : real := 0.6; -- g_beamlet Y BF weight normalized gain for g_global_sp
- g_bf_x_phase : real := 30.0; -- g_beamlet X BF weight phase rotation in degrees for g_global_sp
- g_bf_y_phase : real := 40.0; -- g_beamlet Y BF weight phase rotation in degrees for g_global_sp
- g_bf_remnant_x_gain : real := 0.05; -- g_beamlet X BF weight normalized gain for remnant sp
- g_bf_remnant_y_gain : real := 0.04; -- g_beamlet Y BF weight normalized gain for remnant sp
- g_bf_remnant_x_phase : real := 170.0; -- g_beamlet X BF weight phase rotation in degrees for remnant sp
- g_bf_remnant_y_phase : real := -135.0; -- g_beamlet Y BF weight phase rotation in degrees for remnant sp
- g_read_all_sub_sel : boolean := false; -- when FALSE only read subband selection for g_beamlet, to save sim time
- g_read_all_SST : boolean := false; -- when FALSE only read SST for g_subband, to save sim time
- g_read_all_BST : boolean := false -- when FALSE only read BST for g_beamlet, to save sim time
+ -- first global node (GN) in ring
+ g_first_gn : natural := 1;
+ -- nof ring nodes (RN) in ring
+ g_nof_rn : natural := 2;
+ -- WG global signal path (SP) index in range [c_first_sp : c_last_sp]
+ g_global_sp : natural := 15;
+ -- WG normalized amplitude
+ g_sp_ampl : real := 0.5;
+ -- WG phase in degrees = subband phase
+ g_sp_phase : real := -110.0;
+ -- WG normalized amplitude for remnant sp
+ g_sp_remnant_ampl : real := 0.1;
+ -- WG phase in degrees for remnant sp
+ g_sp_remnant_phase : real := 15.0;
+ -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_subband : natural := 102;
+ -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
+ g_beamlet : natural := c_sdp_S_sub_bf - 1;
+ -- g_beamlet output scale factor
+ g_beamlet_scale : real := 1.0 / 2.0**9;
+ -- g_beamlet X BF weight normalized gain for g_global_sp
+ g_bf_x_gain : real := 0.7;
+ -- g_beamlet Y BF weight normalized gain for g_global_sp
+ g_bf_y_gain : real := 0.6;
+ -- g_beamlet X BF weight phase rotation in degrees for g_global_sp
+ g_bf_x_phase : real := 30.0;
+ -- g_beamlet Y BF weight phase rotation in degrees for g_global_sp
+ g_bf_y_phase : real := 40.0;
+ -- g_beamlet X BF weight normalized gain for remnant sp
+ g_bf_remnant_x_gain : real := 0.05;
+ -- g_beamlet Y BF weight normalized gain for remnant sp
+ g_bf_remnant_y_gain : real := 0.04;
+ -- g_beamlet X BF weight phase rotation in degrees for remnant sp
+ g_bf_remnant_x_phase : real := 170.0;
+ -- g_beamlet Y BF weight phase rotation in degrees for remnant sp
+ g_bf_remnant_y_phase : real := -135.0;
+ -- when FALSE only read subband selection for g_beamlet, to save sim time
+ g_read_all_sub_sel : boolean := false;
+ -- when FALSE only read SST for g_subband, to save sim time
+ g_read_all_SST : boolean := false;
+ -- when FALSE only read BST for g_beamlet, to save sim time
+ g_read_all_BST : boolean := false
);
end tb_lofar2_unb2c_sdp_station_bf_ring;
architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
constant c_sim : boolean := true;
- constant c_first_unb_nr : natural := g_first_gn / c_quad; -- c_quad = 4 FPGAs per UniBoard2
- constant c_first_node_nr : natural := g_first_gn mod c_quad; -- first node_nr in range(c_quad) = [0:3] on c_first_unb_nr
- constant c_last_rn : natural := g_nof_rn - 1; -- first RN has index 0 by definition.
- constant c_last_gn : natural := g_first_gn + c_last_rn; -- last global node (GN) in ring
+ -- c_quad = 4 FPGAs per UniBoard2
+ constant c_first_unb_nr : natural := g_first_gn / c_quad;
+ -- first node_nr in range(c_quad) = [0:3] on c_first_unb_nr
+ constant c_first_node_nr : natural := g_first_gn mod c_quad;
+ -- first RN has index 0 by definition.
+ constant c_last_rn : natural := g_nof_rn - 1;
+ -- last global node (GN) in ring
+ constant c_last_gn : natural := g_first_gn + c_last_rn;
constant c_last_unb_nr : natural := c_last_gn / c_quad;
constant c_last_node_nr : natural := c_last_gn mod c_quad;
- constant c_global_sp_gn : natural := g_global_sp / c_sdp_S_pn; -- global node (GN) of where g_global_sp is located
- constant c_local_sp : natural := g_global_sp mod c_sdp_S_pn; -- local SP index of g_global_sp on c_global_sp_gn
- constant c_global_sp_unb_nr : natural := c_global_sp_gn / c_quad; -- unb_nr of where g_global_sp is located
- constant c_global_sp_node_nr : natural := c_global_sp_gn mod c_quad; -- unb_nr of where g_global_sp is located
+ -- global node (GN) of where g_global_sp is located
+ constant c_global_sp_gn : natural := g_global_sp / c_sdp_S_pn;
+ -- local SP index of g_global_sp on c_global_sp_gn
+ constant c_local_sp : natural := g_global_sp mod c_sdp_S_pn;
+ -- unb_nr of where g_global_sp is located
+ constant c_global_sp_unb_nr : natural := c_global_sp_gn / c_quad;
+ -- unb_nr of where g_global_sp is located
+ constant c_global_sp_node_nr : natural := c_global_sp_gn mod c_quad;
constant c_first_sp : natural := g_first_gn * c_sdp_S_pn;
constant c_last_sp : natural := c_first_sp + g_nof_rn * c_sdp_S_pn - 1;
- constant c_init_bsn : natural := 17; -- some recognizable value >= 0
+ -- some recognizable value >= 0
+ constant c_init_bsn : natural := 17;
constant c_nof_lanes : natural := c_sdp_N_beamsets;
constant c_last_id : std_logic_vector(7 downto 0) := TO_UVEC(c_last_gn, 8);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
- constant c_mm_clk_period : time := 10 ns; -- 100 MHz internal mm_clk
+ -- 100 MHz internal mm_clk
+ constant c_mm_clk_period : time := 10 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
+ -- 644MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_nof_block_per_sync : natural := 16;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_pps_period : natural := c_nof_clk_per_sync;
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
- constant c_stat_data_sz : natural := c_wpfb_sim.stat_data_sz; -- = 2
+ -- = 2
+ constant c_stat_data_sz : natural := c_wpfb_sim.stat_data_sz;
- constant c_stat_percentage : real := 0.05; -- +-percentage margin that actual value may differ from expected value
- constant c_stat_lo_factor : real := 1.0 - c_stat_percentage; -- lower boundary
- constant c_stat_hi_factor : real := 1.0 + c_stat_percentage; -- higher boundary
+ -- +-percentage margin that actual value may differ from expected value
+ constant c_stat_percentage : real := 0.05;
+ -- lower boundary
+ constant c_stat_lo_factor : real := 1.0 - c_stat_percentage;
+ -- higher boundary
+ constant c_stat_hi_factor : real := 1.0 + c_stat_percentage;
- constant c_nof_beamlets_per_data : natural := 2; -- 2 dual pol beamlets (= XY, XY) per 64b data word
+ -- 2 dual pol beamlets (= XY, XY) per 64b data word
+ constant c_nof_beamlets_per_data : natural := 2;
- constant c_beamlet_output_delta : integer := 2; -- +-delta margin
+ -- +-delta margin
+ constant c_beamlet_output_delta : integer := 2;
-- header fields
-- . Use gn = 1 for c_cep_ip_src_addr to have fixed c_exp_ip_header_checksum
constant c_cep_eth_src_mac : std_logic_vector(47 downto 0) := c_sdp_cep_eth_src_mac_47_16 & func_sdp_gn_index_to_mac_15_0(c_last_gn);
constant c_cep_ip_src_addr : std_logic_vector(31 downto 0) := c_sdp_cep_ip_src_addr_31_16 & func_sdp_gn_index_to_ip_15_0(1);
- constant c_cep_udp_src_port : std_logic_vector(15 downto 0) := c_sdp_cep_udp_src_port_15_8 & c_last_id; -- D0 & c_last_id
+ -- D0 & c_last_id
+ constant c_cep_udp_src_port : std_logic_vector(15 downto 0) := c_sdp_cep_udp_src_port_15_8 & c_last_id;
-- . The ip_header_checksum depends on src IP, and therefore on the c_last_gn. The expected
-- value is obtained from rx_sdp_cep_header.ip.header_checksum in wave window for
-- c_last_gn = 1. Therefore in this tb use func_sdp_gn_index_to_ip_15_0(1) to have fixed
-- c_exp_ip_header_checksum, independent of actual c_last_gn.
constant c_exp_ip_header_checksum : natural := 16#5BDD#;
- constant c_exp_beamlet_scale : natural := natural(g_beamlet_scale * real(c_sdp_unit_beamlet_scale)); -- c_sdp_unit_beamlet_scale = 2**15;
- constant c_exp_beamlet_index : natural := 0; -- depends on beamset bset * c_sdp_S_sub_bf
+ -- c_sdp_unit_beamlet_scale = 2**15;
+ constant c_exp_beamlet_scale : natural := natural(g_beamlet_scale * real(c_sdp_unit_beamlet_scale));
+ -- depends on beamset bset * c_sdp_S_sub_bf
+ constant c_exp_beamlet_index : natural := 0;
constant c_exp_sdp_info : t_sdp_info := (
- TO_UVEC(3, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
+ -- antenna_field_index
+ TO_UVEC(3, 6),
+ -- station_id
+ TO_UVEC(601, 10),
+ -- antenna_band_index
+ '0',
+ -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
+ x"7FFFFFFF",
+ -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ b"01",
+ -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '1',
+ -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0',
+ -- beam_repositioning_flag
+ '0',
+ -- block_period = 5120
+ x"1400"
);
-- WG
- constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := c_init_bsn + 2;
-- .ampl
- constant c_wg_ampl : natural := natural(g_sp_ampl * real(c_sdp_FS_adc)); -- in number of lsb
- constant c_wg_remnant_ampl : natural := natural(g_sp_remnant_ampl * real(c_sdp_FS_adc)); -- in number of lsb
+ -- in number of lsb
+ constant c_wg_ampl : natural := natural(g_sp_ampl * real(c_sdp_FS_adc));
+ -- in number of lsb
+ constant c_wg_remnant_ampl : natural := natural(g_sp_remnant_ampl * real(c_sdp_FS_adc));
constant c_exp_sp_power : real := real(c_wg_ampl**2) / 2.0;
constant c_exp_sp_ast : real := c_exp_sp_power * real(c_nof_clk_per_sync);
-- . phase
- constant c_subband_freq : real := real(g_subband) / real(c_sdp_N_fft); -- normalized by fs = f_adc = 200 MHz = dp_clk rate
- constant c_wg_latency : integer := c_diag_wg_latency - 0; -- -0 to account for BSN scheduler start trigger latency
- constant c_wg_phase_offset : real := 360.0 * real(c_wg_latency) * c_subband_freq; -- c_diag_wg_latency is in dp_clk cycles
- constant c_wg_phase : real := g_sp_phase + c_wg_phase_offset; -- WG phase in degrees
- constant c_wg_remnant_phase : real := g_sp_remnant_phase + c_wg_phase_offset; -- WG phase in degrees
+ -- normalized by fs = f_adc = 200 MHz = dp_clk rate
+ constant c_subband_freq : real := real(g_subband) / real(c_sdp_N_fft);
+ -- -0 to account for BSN scheduler start trigger latency
+ constant c_wg_latency : integer := c_diag_wg_latency - 0;
+ -- c_diag_wg_latency is in dp_clk cycles
+ constant c_wg_phase_offset : real := 360.0 * real(c_wg_latency) * c_subband_freq;
+ -- WG phase in degrees
+ constant c_wg_phase : real := g_sp_phase + c_wg_phase_offset;
+ -- WG phase in degrees
+ constant c_wg_remnant_phase : real := g_sp_remnant_phase + c_wg_phase_offset;
-- WPFB
constant c_pol_index : natural := c_local_sp mod c_sdp_Q_fft;
- constant c_pfb_index : natural := c_local_sp / c_sdp_Q_fft; -- only read used WPFB unit out of range(c_sdp_P_pfb = 6)
- constant c_subband_phase_offset : real := -90.0; -- WG with zero phase sinus yields subband with -90 degrees phase (negative Im, zero Re)
- constant c_subband_weight_gain : real := 1.0; -- use default unit subband weights
- constant c_subband_weight_phase : real := 0.0; -- use default unit subband weights
+ -- only read used WPFB unit out of range(c_sdp_P_pfb = 6)
+ constant c_pfb_index : natural := c_local_sp / c_sdp_Q_fft;
+ -- WG with zero phase sinus yields subband with -90 degrees phase (negative Im, zero Re)
+ constant c_subband_phase_offset : real := -90.0;
+ -- use default unit subband weights
+ constant c_subband_weight_gain : real := 1.0;
+ -- use default unit subband weights
+ constant c_subband_weight_phase : real := 0.0;
constant c_exp_subband_phase : real := g_sp_phase + c_subband_phase_offset + c_subband_weight_phase;
constant c_exp_subband_ampl : real := real(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio * c_subband_weight_gain;
- constant c_exp_subband_power : real := c_exp_subband_ampl**2.0; -- complex signal ampl, so no divide by 2
+ -- complex signal ampl, so no divide by 2
+ constant c_exp_subband_power : real := c_exp_subband_ampl**2.0;
constant c_exp_subband_sst : real := c_exp_subband_power * real(c_nof_block_per_sync);
constant c_exp_remnant_subband_phase : real := g_sp_remnant_phase + c_subband_phase_offset + c_subband_weight_phase;
constant c_exp_remnant_subband_ampl : real := real(c_wg_remnant_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio * c_subband_weight_gain;
- type t_slv_64_subbands_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_sub - 1); -- 512
- type t_slv_64_beamlets_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_beamlets_sdp - 1); -- 2*488 = 976
+ -- 512
+ type t_slv_64_subbands_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_sub - 1);
+ -- 2*488 = 976
+ type t_slv_64_beamlets_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_beamlets_sdp - 1);
-- BF X-pol and Y-pol
-- . select
- constant c_exp_beamlet_x_index : natural := g_beamlet * c_sdp_N_pol_bf; -- X index in beamset 0
- constant c_exp_beamlet_y_index : natural := g_beamlet * c_sdp_N_pol_bf + 1; -- Y index in beamset 0
+ -- X index in beamset 0
+ constant c_exp_beamlet_x_index : natural := g_beamlet * c_sdp_N_pol_bf;
+ -- Y index in beamset 0
+ constant c_exp_beamlet_y_index : natural := g_beamlet * c_sdp_N_pol_bf + 1;
-- . Beamlet weights for selected g_global_sp
constant c_bf_x_weight_re : integer := integer(COMPLEX_RE(g_bf_x_gain * real(c_sdp_unit_bf_weight), g_bf_x_phase));
constant c_bf_x_weight_im : integer := integer(COMPLEX_IM(g_bf_x_gain * real(c_sdp_unit_bf_weight), g_bf_x_phase));
@@ -306,9 +375,11 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
constant c_exp_beamlet_y_re : real := c_exp_beamlet_y_tuple(2);
constant c_exp_beamlet_y_im : real := c_exp_beamlet_y_tuple(3);
-- . BST
- constant c_exp_beamlet_x_power : real := c_exp_beamlet_x_ampl**2.0; -- complex signal ampl, so no divide by 2
+ -- complex signal ampl, so no divide by 2
+ constant c_exp_beamlet_x_power : real := c_exp_beamlet_x_ampl**2.0;
constant c_exp_beamlet_x_bst : real := c_exp_beamlet_x_power * real(c_nof_block_per_sync);
- constant c_exp_beamlet_y_power : real := c_exp_beamlet_y_ampl**2.0; -- complex signal ampl, so no divide by 2
+ -- complex signal ampl, so no divide by 2
+ constant c_exp_beamlet_y_power : real := c_exp_beamlet_y_ampl**2.0;
constant c_exp_beamlet_y_bst : real := c_exp_beamlet_y_power * real(c_nof_block_per_sync);
-- . Beamlet output
constant c_exp_beamlet_x_output_ampl : real := c_exp_beamlet_x_ampl * g_beamlet_scale;
@@ -346,17 +417,28 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
-- Use c_mm_file_reg_* on c_last_gn for MM accesses to only last node in ring, e.g. for control beamlet output, read BSN, read back
-- Use mmf_unb_file_prefix() and range(g_nof_rn) for MM access loop to all nodes in ring, e.g. for control BSN source, BF weights
- constant c_mm_file_reg_bsn_scheduler_wg : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "REG_BSN_SCHEDULER"; -- read current BSN
- constant c_mm_file_ram_equalizer_gains : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "RAM_EQUALIZER_GAINS"; -- read default subband weight
- constant c_mm_file_reg_dp_selector : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "REG_DP_SELECTOR"; -- read sst_weighted_subbands_flag
- constant c_mm_file_ram_st_sst : string := mmf_unb_file_prefix(c_global_sp_unb_nr, c_global_sp_node_nr) & "RAM_ST_SST"; -- read SST from GN with g_global_sp
- constant c_mm_file_ram_st_bst : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "RAM_ST_BST"; -- read BST
- constant c_mm_file_reg_stat_enable_bst : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "REG_STAT_ENABLE_BST"; -- control BST offload
- constant c_mm_file_reg_dp_xonoff : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "REG_DP_XONOFF"; -- beamlet output
- constant c_mm_file_ram_ss_ss_wide : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "RAM_SS_SS_WIDE"; -- readback
- constant c_mm_file_ram_bf_weights : string := mmf_unb_file_prefix(c_global_sp_unb_nr, c_global_sp_node_nr) & "RAM_BF_WEIGHTS"; -- readback from GN with g_global_sp
- constant c_mm_file_reg_bf_scale : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "REG_BF_SCALE"; -- readback
- constant c_mm_file_reg_hdr_dat : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "REG_HDR_DAT"; -- control beamlet output
+ -- read current BSN
+ constant c_mm_file_reg_bsn_scheduler_wg : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "REG_BSN_SCHEDULER";
+ -- read default subband weight
+ constant c_mm_file_ram_equalizer_gains : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "RAM_EQUALIZER_GAINS";
+ -- read sst_weighted_subbands_flag
+ constant c_mm_file_reg_dp_selector : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "REG_DP_SELECTOR";
+ -- read SST from GN with g_global_sp
+ constant c_mm_file_ram_st_sst : string := mmf_unb_file_prefix(c_global_sp_unb_nr, c_global_sp_node_nr) & "RAM_ST_SST";
+ -- read BST
+ constant c_mm_file_ram_st_bst : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "RAM_ST_BST";
+ -- control BST offload
+ constant c_mm_file_reg_stat_enable_bst : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "REG_STAT_ENABLE_BST";
+ -- beamlet output
+ constant c_mm_file_reg_dp_xonoff : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "REG_DP_XONOFF";
+ -- readback
+ constant c_mm_file_ram_ss_ss_wide : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "RAM_SS_SS_WIDE";
+ -- readback from GN with g_global_sp
+ constant c_mm_file_ram_bf_weights : string := mmf_unb_file_prefix(c_global_sp_unb_nr, c_global_sp_node_nr) & "RAM_BF_WEIGHTS";
+ -- readback
+ constant c_mm_file_reg_bf_scale : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "REG_BF_SCALE";
+ -- control beamlet output
+ constant c_mm_file_reg_hdr_dat : string := mmf_unb_file_prefix(c_last_unb_nr, c_last_node_nr) & "REG_HDR_DAT";
-- Tb
signal stimuli_done : std_logic := '0';
@@ -365,8 +447,10 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
signal tb_clk : std_logic := '0';
signal rd_data : std_logic_vector(c_32 - 1 downto 0);
- signal dest_rst : std_logic := '1'; -- use separate destination rst for Rx 10GbE in tb
- signal pps_rst : std_logic := '1'; -- use separate reset to release the PPS generator
+ -- use separate destination rst for Rx 10GbE in tb
+ signal dest_rst : std_logic := '1';
+ -- use separate reset to release the PPS generator
+ signal pps_rst : std_logic := '1';
signal gen_pps : std_logic := '0';
signal in_sync : std_logic := '0';
@@ -388,7 +472,8 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
-- FSUB
-- . Read sp_ssts_arr2 = SST for one WPFB unit that processes g_global_sp
- signal sp_ssts_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol - 1 downto 0); -- [pol][sub], for X,Y pair of A, B
+ -- [pol][sub], for X,Y pair of A, B
+ signal sp_ssts_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol - 1 downto 0);
signal sp_sst : real := 0.0;
signal stat_data : std_logic_vector(c_longword_w - 1 downto 0);
@@ -404,7 +489,8 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
-- BF
-- . beamlet subband selection
signal sp_subband_select : natural := 0;
- signal sp_subband_select_arr : t_integer_arr(0 to c_sdp_S_sub_bf * c_sdp_N_pol - 1) := (others => -1); -- Q_fft = N_pol = 2
+ -- Q_fft = N_pol = 2
+ signal sp_subband_select_arr : t_integer_arr(0 to c_sdp_S_sub_bf * c_sdp_N_pol - 1) := (others => -1);
-- . beamlet X-pol
signal sp_bf_x_weights_re_arr : t_integer_arr(c_first_sp to c_last_sp) := (others => 0);
@@ -418,9 +504,12 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
signal sp_bf_y_weights_phase_arr : t_real_arr(c_first_sp to c_last_sp) := (others => 0.0);
-- . BST
- signal bsts_arr2 : t_slv_64_beamlets_arr(c_sdp_N_pol_bf - 1 downto 0); -- [pol_bf][blet]
- signal bst_x_arr : t_real_arr(0 to c_sdp_N_beamsets - 1) := (others => 0.0); -- [bset] for BF X pol
- signal bst_y_arr : t_real_arr(0 to c_sdp_N_beamsets - 1) := (others => 0.0); -- [bset] for BF Y pol
+ -- [pol_bf][blet]
+ signal bsts_arr2 : t_slv_64_beamlets_arr(c_sdp_N_pol_bf - 1 downto 0);
+ -- [bset] for BF X pol
+ signal bst_x_arr : t_real_arr(0 to c_sdp_N_beamsets - 1) := (others => 0.0);
+ -- [bset] for BF Y pol
+ signal bst_y_arr : t_real_arr(0 to c_sdp_N_beamsets - 1) := (others => 0.0);
-- CEP model
-- . 10GbE
@@ -444,18 +533,23 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
signal exp_payload_error : std_logic := '0';
-- Beamlets packets data
- signal rx_beamlet_data : std_logic_vector(c_longword_w - 1 downto 0); -- 64 bit
+ -- 64 bit
+ signal rx_beamlet_data : std_logic_vector(c_longword_w - 1 downto 0);
signal rx_beamlet_sosi : t_dp_sosi := c_dp_sosi_rst;
signal rx_beamlet_sop_cnt : natural := 0;
signal rx_beamlet_eop_cnt : natural := 0;
- signal rx_beamlet_arr_re : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet - 1 downto 0); -- [3:0]
- signal rx_beamlet_arr_im : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet - 1 downto 0); -- [3:0]
+ -- [3:0]
+ signal rx_beamlet_arr_re : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet - 1 downto 0);
+ -- [3:0]
+ signal rx_beamlet_arr_im : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet - 1 downto 0);
signal rx_beamlet_cnt : natural;
signal rx_beamlet_valid : std_logic;
- signal rx_beamlet_list_re : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf - 1 downto 0); -- [488 * 2-1:0] = [975:0]
- signal rx_beamlet_list_im : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf - 1 downto 0); -- [488 * 2-1:0] = [975:0]
+ -- [488 * 2-1:0] = [975:0]
+ signal rx_beamlet_list_re : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf - 1 downto 0);
+ -- [488 * 2-1:0] = [975:0]
+ signal rx_beamlet_list_im : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf - 1 downto 0);
-- DUT
signal ext_clk : std_logic := '0';
@@ -489,14 +583,20 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
- SA_CLK <= not SA_CLK after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ SA_CLK <= not SA_CLK after c_sa_clk_period / 2;
dest_rst <= '0' after c_ext_clk_period * 10;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -601,9 +701,12 @@ begin
port map (
-- Transceiver PLL reference clock
tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => tr_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => tr_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156,
-- MM interface
mm_rst => dest_rst,
@@ -613,7 +716,8 @@ begin
dp_rst => dest_rst,
dp_clk => ext_clk,
- serial_rx_arr(0) => i_QSFP_1_lpbk(c_last_rn)(0), -- Last RN must be used as end node.
+ -- Last RN must be used as end node.
+ serial_rx_arr(0) => i_QSFP_1_lpbk(c_last_rn)(0),
src_out_arr(0) => tr_10GbE_src_out,
src_in_arr(0) => tr_10GbE_src_in
@@ -650,15 +754,18 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_gn : natural;
variable v_bsn : natural;
variable v_data_lo, v_data_hi : std_logic_vector(c_word_w - 1 downto 0);
variable v_stat_data : std_logic_vector(c_longword_w - 1 downto 0);
- variable v_len, v_span, v_offset, v_addr, v_sel : natural; -- address ranges, indices
- variable v_W, v_P, v_PB, v_S, v_A, v_B, v_G : natural; -- array indicies
+ -- address ranges, indices
+ variable v_len, v_span, v_offset, v_addr, v_sel : natural;
+ -- array indicies
+ variable v_W, v_P, v_PB, v_S, v_A, v_B, v_G : natural;
variable v_re, v_im, v_weight : integer;
variable v_re_exp, v_im_exp : real := 0.0;
begin
@@ -833,12 +940,16 @@ begin
-- Write tb defaults
-- . Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on c_last_gn
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 39, TO_UINT(c_cep_eth_src_mac(47 downto 32)), tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 38, TO_SINT(c_cep_eth_src_mac(31 downto 0)), tb_clk); -- use signed to fit 32 b in INTEGER
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 26, TO_SINT(c_cep_ip_src_addr), tb_clk); -- use signed to fit 32 b in INTEGER
+ -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 38, TO_SINT(c_cep_eth_src_mac(31 downto 0)), tb_clk);
+ -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 26, TO_SINT(c_cep_ip_src_addr), tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 24, TO_UINT(c_cep_udp_src_port), tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 41, TO_UINT(c_sdp_cep_eth_dst_mac(47 downto 32)), tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 40, TO_SINT(c_sdp_cep_eth_dst_mac(31 downto 0)), tb_clk); -- use signed to fit 32 b in INTEGER
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 25, TO_SINT(c_sdp_cep_ip_dst_addr), tb_clk); -- use signed to fit 32 b in INTEGER
+ -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 40, TO_SINT(c_sdp_cep_eth_dst_mac(31 downto 0)), tb_clk);
+ -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 25, TO_SINT(c_sdp_cep_ip_dst_addr), tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 23, TO_UINT(c_sdp_cep_udp_dst_port), tb_clk);
proc_common_wait_cross_clock_domain_latency(c_mm_clk_period, c_ext_clk_period, c_common_cross_clock_domain_latency * 2);
@@ -881,10 +992,14 @@ begin
----------------------------------------------------------------------------
for RN in 0 to c_last_rn loop
v_gn := g_first_gn + RN;
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_BSN_SOURCE_V2", 2, c_init_bsn, tb_clk); -- Init BSN
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_BSN_SOURCE_V2", 3, 0, tb_clk); -- Write high part a
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_BSN_SOURCE_V2", 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_syn
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_BSN_SOURCE_V2", 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Init BSN
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_BSN_SOURCE_V2", 2, c_init_bsn, tb_clk);
+ -- Write high part a
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_BSN_SOURCE_V2", 3, 0, tb_clk);
+ -- nof_block_per_syn
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_BSN_SOURCE_V2", 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BS at PPS
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_BSN_SOURCE_V2", 0, 16#00000003#, tb_clk);
end loop;
-- Release PPS pulser, to get first PPS now and to start BSN source
@@ -897,24 +1012,32 @@ begin
-- Write ring configuration to all nodes.
for RN in 0 to c_last_rn loop
v_gn := g_first_gn + RN;
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 2, g_nof_rn, tb_clk); -- N_rn
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 3, g_first_gn, tb_clk); -- O_rn
+ -- N_rn
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 2, g_nof_rn, tb_clk);
+ -- O_rn
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 3, g_first_gn, tb_clk);
end loop;
for RN in 0 to c_last_rn loop
v_gn := g_first_gn + RN;
if v_gn = g_first_gn then
-- Start node specific settings
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 0, 1, tb_clk); -- use_cable_to_previous_rn = 1
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 1, 0, tb_clk); -- use_cable_to_next_rn = 0
+ -- use_cable_to_previous_rn = 1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 0, 1, tb_clk);
+ -- use_cable_to_next_rn = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 1, 0, tb_clk);
elsif v_gn = c_last_gn then
-- End node specific settings
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 0, 0, tb_clk); -- use_cable_to_previous_rn = 0
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 1, 1, tb_clk); -- use_cable_to_next_rn = 1
+ -- use_cable_to_previous_rn = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 0, 0, tb_clk);
+ -- use_cable_to_next_rn = 1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 1, 1, tb_clk);
else
-- Use same settings for all nodes in between
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 0, 0, tb_clk); -- use_cable_to_previous_rn = 0
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 1, 0, tb_clk); -- use_cable_to_next_rn = 0
+ -- use_cable_to_previous_rn = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 0, 0, tb_clk);
+ -- use_cable_to_next_rn = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_RING_INFO", 1, 0, tb_clk);
end if;
end loop;
@@ -948,16 +1071,24 @@ begin
for S in 0 to c_sdp_S_pn - 1 loop
if v_gn * c_sdp_S_pn + S = g_global_sp then
-- Strong WG signal at g_global_sp
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 1, integer(c_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 1, integer(c_wg_phase * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk);
else
-- Weak WG signal on all other (remnant) SP
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 1, integer(c_wg_remnant_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 3, integer(real(c_wg_remnant_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 1, integer(c_wg_remnant_phase * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 3, integer(real(c_wg_remnant_ampl) * c_sdp_wg_ampl_lsb), tb_clk);
end if;
end loop;
end loop;
@@ -973,8 +1104,10 @@ begin
for RN in 0 to c_last_rn loop
v_gn := g_first_gn + RN;
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_BSN_SCHEDULER", 0, c_bsn_start_wg, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_BSN_SCHEDULER", 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_BSN_SCHEDULER", 0, c_bsn_start_wg, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_BSN_SCHEDULER", 1, 0, tb_clk);
end loop;
----------------------------------------------------------------------------
@@ -1007,7 +1140,8 @@ begin
-- . MM format: (uint16)RAM_SS_SS_WIDE[N_beamsets][A_pn]_[S_sub_bf][Q_fft], Q_fft = N_pol = 2
-- . write selection, only for g_beamlet to save sim time
- v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf); -- = 1024
+ -- = 1024
+ v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf);
for U in 0 to c_sdp_N_beamsets - 1 loop
-- Same selection for both beamsets
-- Select beamlet g_beamlet to subband g_subband
@@ -1036,13 +1170,15 @@ begin
mmf_mm_bus_rd(c_mm_file_ram_ss_ss_wide, v_addr, rd_data, tb_clk);
v_sel := (TO_UINT(rd_data) - v_P) / c_sdp_N_pol;
sp_subband_select_arr(B * c_sdp_N_pol + v_P) <= v_sel;
- sp_subband_select <= v_sel; -- for time series view in Wave window
+ -- for time series view in Wave window
+ sp_subband_select <= v_sel;
end if;
end loop;
end loop;
proc_common_wait_some_cycles(tb_clk, 1);
assert sp_subband_select_arr(g_beamlet * c_sdp_N_pol + v_P) = g_subband report "Wrong subband select at beamlet index." severity ERROR;
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
----------------------------------------------------------------------------
-- Write beamlet weight for g_beamlet in S_sub_bf
@@ -1050,7 +1186,8 @@ begin
-- . MM format: (cint16)RAM_BF_WEIGHTS[N_beamsets][N_pol_bf][A_pn]_[N_pol][S_sub_bf]
-- . write BF weights, only for g_beamlet to save sim time
- v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf); -- = 1024
+ -- = 1024
+ v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf);
for RN in 0 to c_last_rn loop
v_gn := g_first_gn + RN;
for U in 0 to c_sdp_N_beamsets - 1 loop
@@ -1077,11 +1214,16 @@ begin
end if;
end if;
-- Only need to set BF weight for g_beamlet, keep other beamlet BF weights at zero rst default.
- v_addr := g_beamlet; -- beamlet index
- v_addr := v_addr + P * c_sdp_S_sub_bf; -- antenna input polarization address offset
- v_addr := v_addr + A * v_span; -- antenna input address offset
- v_addr := v_addr + PB * c_sdp_A_pn * v_span; -- beamlet polarization address offset
- v_addr := v_addr + U * c_mm_span_ram_bf_weights; -- beamset address offset
+ -- beamlet index
+ v_addr := g_beamlet;
+ -- antenna input polarization address offset
+ v_addr := v_addr + P * c_sdp_S_sub_bf;
+ -- antenna input address offset
+ v_addr := v_addr + A * v_span;
+ -- beamlet polarization address offset
+ v_addr := v_addr + PB * c_sdp_A_pn * v_span;
+ -- beamset address offset
+ v_addr := v_addr + U * c_mm_span_ram_bf_weights;
mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "RAM_BF_WEIGHTS", v_addr, v_weight, tb_clk);
end loop;
end loop;
@@ -1096,11 +1238,16 @@ begin
for PB in 0 to c_sdp_N_pol_bf - 1 loop
for A in 0 to c_sdp_A_pn - 1 loop
for P in 0 to c_sdp_N_pol - 1 loop
- v_addr := g_beamlet; -- beamlet index
- v_addr := v_addr + P * c_sdp_S_sub_bf; -- antenna input polarization address offset
- v_addr := v_addr + A * v_span; -- antenna input address offset
- v_addr := v_addr + PB * c_sdp_A_pn * v_span; -- beamlet polarization address offset
- v_addr := v_addr + U * c_mm_span_ram_bf_weights; -- beamset address offset
+ -- beamlet index
+ v_addr := g_beamlet;
+ -- antenna input polarization address offset
+ v_addr := v_addr + P * c_sdp_S_sub_bf;
+ -- antenna input address offset
+ v_addr := v_addr + A * v_span;
+ -- beamlet polarization address offset
+ v_addr := v_addr + PB * c_sdp_A_pn * v_span;
+ -- beamset address offset
+ v_addr := v_addr + U * c_mm_span_ram_bf_weights;
mmf_mm_bus_rd(c_mm_file_ram_bf_weights, v_addr, rd_data, tb_clk);
v_re := unpack_complex_re(rd_data, c_sdp_W_bf_weight);
v_im := unpack_complex_im(rd_data, c_sdp_W_bf_weight);
@@ -1124,13 +1271,16 @@ begin
end loop;
end loop;
proc_common_wait_some_cycles(tb_clk, 1);
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
----------------------------------------------------------------------------
-- Wait for enough WG data and start of sync interval
----------------------------------------------------------------------------
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 3, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 3,
c_sdp_T_sub, tb_clk);
-- Stimuli done, now verify results at end of test
@@ -1149,13 +1299,19 @@ begin
-- . the subbands are output alternately so A0 B0 A1 B1 ... A511 B511 for input A, B
-- . the subband statistics multiple WPFB units appear in order in the ram_st_sst address map
-- . the subband statistics are stored first lo word 0 then hi word 1
- v_len := c_sdp_N_sub * c_sdp_N_pol * c_stat_data_sz; -- 2048 = 512 * 2 * 64/32
- v_span := true_log_pow2(v_len); -- = 2048
+ -- 2048 = 512 * 2 * 64/32
+ v_len := c_sdp_N_sub * c_sdp_N_pol * c_stat_data_sz;
+ -- = 2048
+ v_span := true_log_pow2(v_len);
for I in 0 to v_len - 1 loop
- v_W := I mod c_stat_data_sz; -- 0, 1 per statistics word, word index
- v_P := (I / c_stat_data_sz) mod c_sdp_N_pol; -- 0, 1 per SP pol, polarization index
- v_B := I / (c_sdp_N_pol * c_stat_data_sz); -- subband index, range(N_sub = 512) per dual pol
- v_addr := I + c_pfb_index * v_span; -- MM address
+ -- 0, 1 per statistics word, word index
+ v_W := I mod c_stat_data_sz;
+ -- 0, 1 per SP pol, polarization index
+ v_P := (I / c_stat_data_sz) mod c_sdp_N_pol;
+ -- subband index, range(N_sub = 512) per dual pol
+ v_B := I / (c_sdp_N_pol * c_stat_data_sz);
+ -- MM address
+ v_addr := I + c_pfb_index * v_span;
-- Only read SST for g_subband for dual pol SP, to save sim time
if g_read_all_SST = true or v_B = g_subband then
if v_W = 0 then
@@ -1169,7 +1325,8 @@ begin
v_stat_data := v_data_hi & v_data_lo;
sp_ssts_arr2(v_P)(v_B) <= v_stat_data;
- stat_data <= v_stat_data; -- for time series view in Wave window
+ -- for time series view in Wave window
+ stat_data <= v_stat_data;
end if;
end if;
end loop;
@@ -1178,7 +1335,8 @@ begin
-- Subband power of g_subband in g_global_sp
sp_sst <= TO_UREAL(sp_ssts_arr2(c_pol_index)(g_subband));
proc_common_wait_some_cycles(tb_clk, 1);
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
---------------------------------------------------------------------------
-- Read beamlet statistics from last node
@@ -1188,15 +1346,22 @@ begin
-- . the beamlets are output alternately so X0 Y0 X1 Y1 ... X487 Y487 for polarizations X, Y
-- . the beamlet statistics for multiple beamsets appear in order in the ram_st_bst address map
-- . the beamlet statistics are stored first lo word 0 then hi word 1
- v_len := c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_stat_data_sz; -- = 1952 = 488 * 2 * 64/32
- v_span := true_log_pow2(v_len); -- = 2048
+ -- = 1952 = 488 * 2 * 64/32
+ v_len := c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_stat_data_sz;
+ -- = 2048
+ v_span := true_log_pow2(v_len);
for U in 0 to c_sdp_N_beamsets - 1 loop
for I in 0 to v_len - 1 loop
- v_W := I mod c_stat_data_sz; -- 0, 1 per statistics word, word index
- v_PB := (I / c_stat_data_sz) mod c_sdp_N_pol_bf; -- 0, 1 per BF pol, polarization index
- v_B := I / (c_sdp_N_pol_bf * c_stat_data_sz); -- beamlet index in beamset, range(S_sub_bf = 488) per dual pol
- v_G := v_B + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
- v_addr := I + U * v_span; -- MM address
+ -- 0, 1 per statistics word, word index
+ v_W := I mod c_stat_data_sz;
+ -- 0, 1 per BF pol, polarization index
+ v_PB := (I / c_stat_data_sz) mod c_sdp_N_pol_bf;
+ -- beamlet index in beamset, range(S_sub_bf = 488) per dual pol
+ v_B := I / (c_sdp_N_pol_bf * c_stat_data_sz);
+ -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ v_G := v_B + U * c_sdp_S_sub_bf;
+ -- MM address
+ v_addr := I + U * v_span;
--Only read BST for g_beamlet and dual pol_bf 0 and 1 and for both beamsets, to save sim time
if g_read_all_BST = true or v_B = g_beamlet then
if v_W = 0 then
@@ -1210,7 +1375,8 @@ begin
v_stat_data := v_data_hi & v_data_lo;
bsts_arr2(v_PB)(v_G) <= v_stat_data;
- stat_data <= v_stat_data; -- for time series view in Wave window
+ -- for time series view in Wave window
+ stat_data <= v_stat_data;
end if;
end if;
end loop;
@@ -1219,12 +1385,16 @@ begin
-- Beamlet power of g_beamlet X and Y, same for both beamsets
for U in 0 to c_sdp_N_beamsets - 1 loop
- v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
- bst_x_arr(U) <= TO_UREAL(bsts_arr2(0)(v_G)); -- X pol beamlet
- bst_y_arr(U) <= TO_UREAL(bsts_arr2(1)(v_G)); -- Y pol beamlet
+ -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ v_G := g_beamlet + U * c_sdp_S_sub_bf;
+ -- X pol beamlet
+ bst_x_arr(U) <= TO_UREAL(bsts_arr2(0)(v_G));
+ -- Y pol beamlet
+ bst_y_arr(U) <= TO_UREAL(bsts_arr2(1)(v_G));
end loop;
proc_common_wait_some_cycles(tb_clk, 1);
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
---------------------------------------------------------------------------
-- Log WG, subband and beamlet statistics
@@ -1263,12 +1433,14 @@ begin
print_str(". c_exp_beamlet_y_bst = " & real_to_str(c_exp_beamlet_y_bst, 20, 1));
print_str("");
for U in 0 to c_sdp_N_beamsets - 1 loop
- v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ v_G := g_beamlet + U * c_sdp_S_sub_bf;
print_str(". bst_x_arr(" & integer'image(v_G) & ") = " & real_to_str(bst_x_arr(U), 20, 1));
print_str(". bst_y_arr(" & integer'image(v_G) & ") = " & real_to_str(bst_y_arr(U), 20, 1));
end loop;
for U in 0 to c_sdp_N_beamsets - 1 loop
- v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ v_G := g_beamlet + U * c_sdp_S_sub_bf;
print_str(". bst_x_arr(" & integer'image(v_G) & ") / c_exp_beamlet_x_bst = " & real_to_str(bst_x_arr(U) / c_exp_beamlet_x_bst, 20, 6));
print_str(". bst_y_arr(" & integer'image(v_G) & ") / c_exp_beamlet_y_bst = " & real_to_str(bst_y_arr(U) / c_exp_beamlet_y_bst, 20, 6));
end loop;
@@ -1330,7 +1502,8 @@ begin
-- End Simulation
---------------------------------------------------------------------------
tb_almost_end <= '1';
- proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ -- delay for ease of view in Wave window
+ proc_common_wait_some_cycles(ext_clk, 100);
proc_common_stop_simulation(true, ext_clk, tb_almost_end, tb_end);
wait;
end process;
@@ -1345,17 +1518,20 @@ begin
if rising_edge(ext_clk) then
-- Count rx_beamlet_sosi packets
if rx_beamlet_sosi.sop = '1' then
- rx_beamlet_sop_cnt <= rx_beamlet_sop_cnt + 1; -- early count
+ -- early count
+ rx_beamlet_sop_cnt <= rx_beamlet_sop_cnt + 1;
end if;
if rx_beamlet_sosi.eop = '1' then
- rx_beamlet_eop_cnt <= rx_beamlet_eop_cnt + 1; -- after count
+ -- after count
+ rx_beamlet_eop_cnt <= rx_beamlet_eop_cnt + 1;
end if;
end if;
end process;
-- Count sync intervals using in_sosi.sync, because there is no rx_beamlet_sosi.sync
in_sync_cnt <= in_sync_cnt + 1 when rising_edge(ext_clk) and in_sync = '1';
- test_sync_cnt <= in_sync_cnt - 1; -- optionally adjust to fit rx_beamlet_sosi
+ -- optionally adjust to fit rx_beamlet_sosi
+ test_sync_cnt <= in_sync_cnt - 1;
-- Prepare exp_sdp_cep_header before rx_beamlet_sosi.eop, so that
-- p_verify_cep_header can verify it at rx_beamlet_sosi.eop.
@@ -1440,23 +1616,31 @@ begin
proc_common_wait_until_high(ext_clk, rx_beamlet_sosi.valid);
rx_beamlet_valid <= '1';
-- Capture rx beamlets per longword in rx_beamlet_arr, for time series view in Wave window
- rx_beamlet_arr_re(0) <= rx_beamlet_sosi.data(63 downto 56); -- X
+ -- X
+ rx_beamlet_arr_re(0) <= rx_beamlet_sosi.data(63 downto 56);
rx_beamlet_arr_im(0) <= rx_beamlet_sosi.data(55 downto 48);
- rx_beamlet_arr_re(1) <= rx_beamlet_sosi.data(47 downto 40); -- Y
+ -- Y
+ rx_beamlet_arr_re(1) <= rx_beamlet_sosi.data(47 downto 40);
rx_beamlet_arr_im(1) <= rx_beamlet_sosi.data(39 downto 32);
- rx_beamlet_arr_re(2) <= rx_beamlet_sosi.data(31 downto 24); -- X
+ -- X
+ rx_beamlet_arr_re(2) <= rx_beamlet_sosi.data(31 downto 24);
rx_beamlet_arr_im(2) <= rx_beamlet_sosi.data(23 downto 16);
- rx_beamlet_arr_re(3) <= rx_beamlet_sosi.data(15 downto 8); -- Y
+ -- Y
+ rx_beamlet_arr_re(3) <= rx_beamlet_sosi.data(15 downto 8);
rx_beamlet_arr_im(3) <= rx_beamlet_sosi.data( 7 downto 0);
if I < c_sdp_cep_nof_beamlets_per_block / c_nof_beamlets_per_data then
-- Only capture the first beamlets block of each packet in rx_beamlet_list
- rx_beamlet_list_re(I * 4 + 0) <= rx_beamlet_sosi.data(63 downto 56); -- X
+ -- X
+ rx_beamlet_list_re(I * 4 + 0) <= rx_beamlet_sosi.data(63 downto 56);
rx_beamlet_list_im(I * 4 + 0) <= rx_beamlet_sosi.data(55 downto 48);
- rx_beamlet_list_re(I * 4 + 1) <= rx_beamlet_sosi.data(47 downto 40); -- Y
+ -- Y
+ rx_beamlet_list_re(I * 4 + 1) <= rx_beamlet_sosi.data(47 downto 40);
rx_beamlet_list_im(I * 4 + 1) <= rx_beamlet_sosi.data(39 downto 32);
- rx_beamlet_list_re(I * 4 + 2) <= rx_beamlet_sosi.data(31 downto 24); -- X
+ -- X
+ rx_beamlet_list_re(I * 4 + 2) <= rx_beamlet_sosi.data(31 downto 24);
rx_beamlet_list_im(I * 4 + 2) <= rx_beamlet_sosi.data(23 downto 16);
- rx_beamlet_list_re(I * 4 + 3) <= rx_beamlet_sosi.data(15 downto 8); -- Y
+ -- Y
+ rx_beamlet_list_re(I * 4 + 3) <= rx_beamlet_sosi.data(15 downto 8);
rx_beamlet_list_im(I * 4 + 3) <= rx_beamlet_sosi.data( 7 downto 0);
end if;
proc_common_wait_until_high(ext_clk, rx_beamlet_sosi.valid);
@@ -1465,7 +1649,8 @@ begin
-- contains no WAIT statement.
wait until rising_edge(ext_clk);
rx_beamlet_valid <= '0';
- rx_beamlet_cnt <= (rx_beamlet_cnt + c_nof_beamlets_per_data) mod c_sdp_cep_nof_beamlets_per_block; -- 4 blocks/packet
+ -- 4 blocks/packet
+ rx_beamlet_cnt <= (rx_beamlet_cnt + c_nof_beamlets_per_data) mod c_sdp_cep_nof_beamlets_per_block;
end loop;
end process;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
index 10853a63baf3dd229888366c988e34cc04299429..1ca1646ed89dcc0840e516859c55c9c464e15420 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2c_sdp_station_fsub is
generic (
g_design_name : string := "lofar2_unb2c_sdp_station_fsub";
g_design_note : string := "Lofar2 SDP station filterbank design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -67,12 +76,15 @@ entity lofar2_unb2c_sdp_station_fsub is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- back transceivers (note only 12 are used in unb2c)
- BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0)
);
end lofar2_unb2c_sdp_station_fsub;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
index 7d739b0f82e19e68cee96ffde59911ff0b4aa33e..5aa0958723ac2bfb75e41ded68a3da4d2d241c41 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
@@ -79,25 +79,37 @@ use unb2c_board_lib.unb2c_board_pkg.all;
entity tb_lofar2_unb2c_sdp_station_fsub is
generic (
- g_sp : natural := 3; -- signal path index in range(S_pn = 12) of co-polarization
- g_co_wg_ampl : real := 0.5; -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
- g_cross_wg_ampl : real := 0.4; -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
- g_cross_wg_phase : real := 90.0; -- WG phase in degrees for cross-sp, relative to co-sp
- g_subband : natural := 102; -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- g_co_subband_weight_gain : real := 1.0; -- subband weight normalized gain, for co-polarization in g_sp
- g_co_subband_weight_phase : real := 30.0; -- subband weight phase rotation in degrees, for co-polarization in g_sp
+ -- signal path index in range(S_pn = 12) of co-polarization
+ g_sp : natural := 3;
+ -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ g_co_wg_ampl : real := 0.5;
+ -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ g_cross_wg_ampl : real := 0.4;
+ -- WG phase in degrees for cross-sp, relative to co-sp
+ g_cross_wg_phase : real := 90.0;
+ -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_subband : natural := 102;
+ -- subband weight normalized gain, for co-polarization in g_sp
+ g_co_subband_weight_gain : real := 1.0;
+ -- subband weight phase rotation in degrees, for co-polarization in g_sp
+ g_co_subband_weight_phase : real := 30.0;
g_use_cross_weight : boolean := true;
- g_sp_cross_subband_weight_gain : real := 0.5; -- subband weight normalized gain, for cross polarization of g_sp
- g_sp_cross_subband_weight_phase : real := -10.0; -- subband weight phase rotation in degrees, for cross polarization of g_sp
- g_read_all_SST : boolean := true -- when FALSE only read SST for g_subband, to save sim time
+ -- subband weight normalized gain, for cross polarization of g_sp
+ g_sp_cross_subband_weight_gain : real := 0.5;
+ -- subband weight phase rotation in degrees, for cross polarization of g_sp
+ g_sp_cross_subband_weight_phase : real := -10.0;
+ -- when FALSE only read SST for g_subband, to save sim time
+ g_read_all_SST : boolean := true
);
end tb_lofar2_unb2c_sdp_station_fsub;
architecture tb of tb_lofar2_unb2c_sdp_station_fsub is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
- constant c_init_bsn : natural := 17; -- some recognizable value >= 0
+ -- some recognizable value >= 0
+ constant c_init_bsn : natural := 17;
-- signal path index of cross-polarization
constant c_cross_sp : natural := sel_a_b(g_sp mod c_sdp_N_pol = 0, g_sp + 1, g_sp - 1);
@@ -106,58 +118,76 @@ architecture tb of tb_lofar2_unb2c_sdp_station_fsub is
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_nof_block_per_sync : natural := 16;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_pps_period : natural := c_nof_clk_per_sync;
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
- constant c_stat_data_sz : natural := c_wpfb_sim.stat_data_sz; -- = 2
+ -- = 2
+ constant c_stat_data_sz : natural := c_wpfb_sim.stat_data_sz;
- constant c_percentage : real := 0.05; -- percentage that actual value may differ from expected value
- constant c_lo_factor : real := 1.0 - c_percentage; -- lower boundary
- constant c_hi_factor : real := 1.0 + c_percentage; -- higher boundary
+ -- percentage that actual value may differ from expected value
+ constant c_percentage : real := 0.05;
+ -- lower boundary
+ constant c_lo_factor : real := 1.0 - c_percentage;
+ -- higher boundary
+ constant c_hi_factor : real := 1.0 + c_percentage;
-- WG
- constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := c_init_bsn + 2;
-- .ampl
- constant c_co_wg_ampl : natural := natural(g_co_wg_ampl * real(c_sdp_FS_adc)); -- in number of lsb
- constant c_cross_wg_ampl : natural := natural(g_cross_wg_ampl * real(c_sdp_FS_adc)); -- in number of lsb
+ -- in number of lsb
+ constant c_co_wg_ampl : natural := natural(g_co_wg_ampl * real(c_sdp_FS_adc));
+ -- in number of lsb
+ constant c_cross_wg_ampl : natural := natural(g_cross_wg_ampl * real(c_sdp_FS_adc));
constant c_exp_co_sp_power : real := real(c_co_wg_ampl**2) / 2.0;
constant c_exp_cross_sp_power : real := real(c_cross_wg_ampl**2) / 2.0;
constant c_exp_co_sp_ast : real := c_exp_co_sp_power * real(c_nof_clk_per_sync);
constant c_exp_cross_sp_ast : real := c_exp_cross_sp_power * real(c_nof_clk_per_sync);
-- . freq
- constant c_subband_freq : real := real(g_subband) / real(c_sdp_N_fft); -- normalized by fs = f_adc = 200 MHz is dp_clk
+ -- normalized by fs = f_adc = 200 MHz is dp_clk
+ constant c_subband_freq : real := real(g_subband) / real(c_sdp_N_fft);
-- . phase
- constant c_subband_phase : real := 0.0; -- wanted subband phase in degrees = WG phase at sop
- constant c_wg_latency : integer := c_diag_wg_latency - 0; -- -0 to account for BSN scheduler start trigger latency
- constant c_wg_phase_offset : real := 360.0 * real(c_wg_latency) * c_subband_freq; -- c_diag_wg_latency is in dp_clk cycles
- constant c_wg_phase : real := c_subband_phase + c_wg_phase_offset; -- WG phase in degrees
+ -- wanted subband phase in degrees = WG phase at sop
+ constant c_subband_phase : real := 0.0;
+ -- -0 to account for BSN scheduler start trigger latency
+ constant c_wg_latency : integer := c_diag_wg_latency - 0;
+ -- c_diag_wg_latency is in dp_clk cycles
+ constant c_wg_phase_offset : real := 360.0 * real(c_wg_latency) * c_subband_freq;
+ -- WG phase in degrees
+ constant c_wg_phase : real := c_subband_phase + c_wg_phase_offset;
constant c_co_wg_phase : real := c_wg_phase;
constant c_cross_wg_phase : real := c_wg_phase + g_cross_wg_phase;
- constant c_subband_phase_offset : real := -90.0; -- WG with zero phase sinus yields subband with -90 degrees phase (negative Im, zero Re)
+ -- WG with zero phase sinus yields subband with -90 degrees phase (negative Im, zero Re)
+ constant c_subband_phase_offset : real := -90.0;
constant c_co_subband_phase : real := c_subband_phase_offset + c_co_wg_phase;
constant c_cross_subband_phase : real := c_subband_phase_offset + c_cross_wg_phase;
-- FSUB
constant c_pol_index : natural := g_sp mod c_sdp_Q_fft;
- constant c_pfb_index : natural := g_sp / c_sdp_Q_fft; -- only read used WPFB unit out of range(c_sdp_P_pfb = 6)
+ -- only read used WPFB unit out of range(c_sdp_P_pfb = 6)
+ constant c_pfb_index : natural := g_sp / c_sdp_Q_fft;
constant c_exp_co_subband_ampl_raw : real := real(c_co_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio;
constant c_exp_cross_subband_ampl_raw : real := real(c_cross_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio;
constant c_exp_co_subband_ampl_weighted : real := c_exp_co_subband_ampl_raw * g_co_subband_weight_gain;
- constant c_exp_cross_subband_ampl_weighted : real := c_exp_cross_subband_ampl_raw * 1.0; -- unit gain, this is co gain for cross sp
+ -- unit gain, this is co gain for cross sp
+ constant c_exp_cross_subband_ampl_weighted : real := c_exp_cross_subband_ampl_raw * 1.0;
constant c_exp_jones_subband_tuple : t_real_arr(0 to 3) := func_sdp_subband_equalizer(
c_exp_co_subband_ampl_raw, c_co_subband_phase, g_co_subband_weight_gain, g_co_subband_weight_phase,
c_exp_cross_subband_ampl_raw, c_cross_subband_phase, g_sp_cross_subband_weight_gain, g_sp_cross_subband_weight_phase);
constant c_exp_sp_subband_ampl_weighted : real := sel_a_b(g_use_cross_weight, c_exp_jones_subband_tuple(0), c_exp_co_subband_ampl_weighted);
- constant c_exp_co_subband_power_raw : real := c_exp_co_subband_ampl_raw**2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
+ -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
+ constant c_exp_co_subband_power_raw : real := c_exp_co_subband_ampl_raw**2.0;
constant c_exp_cross_subband_power_raw : real := c_exp_cross_subband_ampl_raw**2.0;
constant c_exp_sp_subband_power_weighted : real := c_exp_sp_subband_ampl_weighted**2.0;
constant c_exp_cross_subband_power_weighted : real := c_exp_cross_subband_ampl_weighted**2.0;
@@ -168,8 +198,10 @@ architecture tb of tb_lofar2_unb2c_sdp_station_fsub is
-- . expected limit values, obtained with print_str() for g_subband = 102,
-- g_co_wg_ampl = 1.0, g_co_subband_weight_gain = 1.0, g_co_subband_weight_phase = 30.0
- constant c_exp_sp_subband_sst_leakage_snr_dB : real := 70.0; -- < 74.913
- constant c_exp_sp_subband_sst_crosstalk_snr_dB : real := 90.0; -- < 96.284
+ -- < 74.913
+ constant c_exp_sp_subband_sst_leakage_snr_dB : real := 70.0;
+ -- < 96.284
+ constant c_exp_sp_subband_sst_crosstalk_snr_dB : real := 90.0;
type t_real_arr is array (integer range <>) of real;
type t_slv_64_subbands_arr is array (integer range <>) of t_slv_64_arr(0 to c_sdp_N_sub - 1);
@@ -210,14 +242,17 @@ architecture tb of tb_lofar2_unb2c_sdp_station_fsub is
-- FSUB
-- . WPFB
- signal sp_subband_ssts_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol - 1 downto 0); -- [pol][sub]
+ -- [pol][sub]
+ signal sp_subband_ssts_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol - 1 downto 0);
signal sp_subband_sst_sum_arr : t_real_arr(c_sdp_N_pol - 1 downto 0) := (others => 0.0);
signal sp_subband_sst : real := 0.0;
signal sp_cross_subband_sst : real := 0.0;
signal sp_subband_sst_leakage : real := 0.0;
- signal sp_subband_sst_leakage_snr_dB : real := 0.0; -- signal to noise (leakage) ratio
+ -- signal to noise (leakage) ratio
+ signal sp_subband_sst_leakage_snr_dB : real := 0.0;
signal sp_subband_sst_crosstalk : real := 0.0;
- signal sp_subband_sst_crosstalk_snr_dB : real := 0.0; -- signal to noise (crosstalk) ration
+ -- signal to noise (crosstalk) ration
+ signal sp_subband_sst_crosstalk_snr_dB : real := 0.0;
signal exp_sp_subband_ampl : real := 0.0;
signal exp_sp_subband_power : real := 0.0;
@@ -264,11 +299,15 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -330,14 +369,17 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
variable v_data_lo, v_data_hi : std_logic_vector(c_word_w - 1 downto 0);
variable v_stat_data : std_logic_vector(c_longword_w - 1 downto 0);
- variable v_len, v_span, v_offset, v_addr : natural; -- address ranges, indices
- variable v_W, v_P, v_U, v_S, v_B : natural; -- array indicies
+ -- address ranges, indices
+ variable v_len, v_span, v_offset, v_addr : natural;
+ -- array indicies
+ variable v_W, v_P, v_U, v_S, v_B : natural;
variable v_re, v_im, v_weight : integer;
variable v_power : real;
begin
@@ -347,10 +389,14 @@ begin
----------------------------------------------------------------------------
-- Enable BSN
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk); -- Init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk); -- Write high part activates the init BSN
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BSN at PPS
+ -- Init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk);
+ -- Write high part activates the init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BSN at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk);
-- Release PPS pulser, to get first PPS now and to start BSN source
wait for 1 us;
@@ -373,18 +419,26 @@ begin
-- 3 : ampl[16:0]
-- g_sp is co-polarization
v_offset := g_sp * c_mm_span_reg_diag_wg;
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_co_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_co_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_co_wg_phase * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_co_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk);
if g_use_cross_weight then
-- c_cross_sp is cross-polarization for g_sp, use same WG settings for c_cross_sp as for g_sp
v_offset := c_cross_sp * c_mm_span_reg_diag_wg;
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_cross_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_cross_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_cross_wg_phase * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_cross_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk);
end if;
-- Read current BSN
@@ -395,8 +449,10 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
----------------------------------------------------------------------------
-- Write subband weight for selected g_sp and g_subband
@@ -418,7 +474,8 @@ begin
assert sp_co_subband_weight_re = c_sdp_unit_sub_weight report "Default sp_co_subband_weight_re /= c_sdp_unit_sub_weight" severity ERROR;
assert sp_co_subband_weight_im = 0 report "Default sp_co_subband_weight_im /= 0" severity ERROR;
-- . write
- v_weight := pack_complex(re => c_co_subband_weight_re, im => c_co_subband_weight_im, w => c_sdp_W_sub_weight); -- c_sdp_W_sub_weight = 16 bit
+ -- c_sdp_W_sub_weight = 16 bit
+ v_weight := pack_complex(re => c_co_subband_weight_re, im => c_co_subband_weight_im, w => c_sdp_W_sub_weight);
mmf_mm_bus_wr(c_mm_file_ram_equalizer_gains, v_addr, v_weight, tb_clk);
proc_common_wait_cross_clock_domain_latency(c_tb_clk_period, c_ext_clk_period, c_common_cross_clock_domain_latency * 2);
-- . read back
@@ -450,7 +507,8 @@ begin
assert sp_cross_subband_weight_re = 0 report "Default sp_cross_subband_weight_re /= 0" severity ERROR;
assert sp_cross_subband_weight_im = 0 report "Default sp_cross_subband_weight_im /= 0" severity ERROR;
-- . write
- v_weight := pack_complex(re => c_sp_cross_subband_weight_re, im => c_sp_cross_subband_weight_im, w => c_sdp_W_sub_weight); -- c_sdp_W_sub_weight = 16 bit
+ -- c_sdp_W_sub_weight = 16 bit
+ v_weight := pack_complex(re => c_sp_cross_subband_weight_re, im => c_sp_cross_subband_weight_im, w => c_sdp_W_sub_weight);
mmf_mm_bus_wr(c_mm_file_ram_equalizer_gains_cross, v_addr, v_weight, tb_clk);
proc_common_wait_cross_clock_domain_latency(c_tb_clk_period, c_ext_clk_period, c_common_cross_clock_domain_latency * 2);
-- . read back
@@ -469,8 +527,10 @@ begin
----------------------------------------------------------------------------
-- Wait for enough WG data and start of sync interval
----------------------------------------------------------------------------
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 3, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 3,
c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
@@ -486,13 +546,19 @@ begin
-- . the subbands are output alternately so A0 B0 A1 B1 ... A511 B511 for input A, B
-- . the subband statistics multiple WPFB units appear in order in the ram_st_sst address map
-- . the subband statistics are stored first lo word 0 then hi word 1
- v_len := c_sdp_N_sub * c_sdp_N_pol * c_stat_data_sz; -- 2048 = 512 * 2 * 64/32
- v_span := true_log_pow2(v_len); -- = 2048
+ -- 2048 = 512 * 2 * 64/32
+ v_len := c_sdp_N_sub * c_sdp_N_pol * c_stat_data_sz;
+ -- = 2048
+ v_span := true_log_pow2(v_len);
for I in 0 to v_len - 1 loop
- v_W := I mod c_stat_data_sz; -- 0, 1 per statistics word, word index
- v_P := (I / c_stat_data_sz) mod c_sdp_N_pol; -- 0, 1 per SP pol, polarization index
- v_B := I / (c_sdp_N_pol * c_stat_data_sz); -- subband index, range(N_sub = 512) per dual pol
- v_addr := I + c_pfb_index * v_span; -- MM address for WPFB unit of selected g_sp
+ -- 0, 1 per statistics word, word index
+ v_W := I mod c_stat_data_sz;
+ -- 0, 1 per SP pol, polarization index
+ v_P := (I / c_stat_data_sz) mod c_sdp_N_pol;
+ -- subband index, range(N_sub = 512) per dual pol
+ v_B := I / (c_sdp_N_pol * c_stat_data_sz);
+ -- MM address for WPFB unit of selected g_sp
+ v_addr := I + c_pfb_index * v_span;
-- Only read SST for g_subband for dual pol SP, to save sim time
if g_read_all_SST = true or v_B = g_subband then
if v_W = 0 then
@@ -506,7 +572,8 @@ begin
v_stat_data := v_data_hi & v_data_lo;
sp_subband_ssts_arr2(v_P)(v_B) <= v_stat_data;
- stat_data <= v_stat_data; -- for time series view in Wave window
+ -- for time series view in Wave window
+ stat_data <= v_stat_data;
-- sum of all subband powers per pol
sp_subband_sst_sum_arr(v_P) <= sp_subband_sst_sum_arr(v_P) + TO_UREAL(v_stat_data);
@@ -540,7 +607,8 @@ begin
-- The sp_subband_sst_crosstalk shows how much power from one WPFB input cross talks
-- into the other output, due to quantization cross talk in the complex FFT. The power
-- ration indicates the suppression, provided that the other input was zero.
- v_power := sp_subband_sst_sum_arr(not_int(c_pol_index)); -- not_int(0) = 1, not_int(/= 0) = 0
+ -- not_int(0) = 1, not_int(/= 0) = 0
+ v_power := sp_subband_sst_sum_arr(not_int(c_pol_index));
sp_subband_sst_crosstalk <= v_power;
if sp_subband_sst > c_eps and v_power > c_eps then
sp_subband_sst_crosstalk_snr_dB <= 10.0 * LOG10(sp_subband_sst / v_power);
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
index 15dc0b787d0e20a7d0dff92dbeaadb648a837fe0..fab05426ba27fb012cf2f183faf7e63fce1ec1c2 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
@@ -60,17 +60,21 @@ architecture tb of tb_lofar2_unb2c_sdp_station_fsub_sst_offload is
constant c_sim : boolean := true;
constant c_unb_nr : natural := 2;
constant c_node_nr : natural := 1;
- constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr * 4 + c_node_nr, 8); -- c_unb2b_board_nof_node = 4, c_unb2b_board_aux.id_w = 8
+ -- c_unb2b_board_nof_node = 4, c_unb2b_board_aux.id_w = 8
+ constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr * 4 + c_node_nr, 8);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
- constant c_nof_block_per_sync : natural := 80; -- long enough to stream out udp data
+ -- long enough to stream out udp data
+ constant c_nof_block_per_sync : natural := 80;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_pps_period : natural := c_nof_clk_per_sync;
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
@@ -89,10 +93,14 @@ architecture tb of tb_lofar2_unb2c_sdp_station_fsub_sst_offload is
signal eth_done : std_logic := '0';
-- . 1GbE output
- constant c_eth_check_nof_packets : natural := c_nof_sync * c_sdp_S_pn; -- S_pn = 12 received packets per sync interval
- constant c_eth_header_size : natural := 19; -- words
- constant c_eth_crc_size : natural := 1; -- word
- constant c_eth_packet_size : natural := c_eth_header_size + c_eth_crc_size + c_sdp_N_sub * (c_sdp_W_statistic / c_word_w); -- 20 + 512 * 2 = 1044
+ -- S_pn = 12 received packets per sync interval
+ constant c_eth_check_nof_packets : natural := c_nof_sync * c_sdp_S_pn;
+ -- words
+ constant c_eth_header_size : natural := 19;
+ -- word
+ constant c_eth_crc_size : natural := 1;
+ -- 20 + 512 * 2 = 1044
+ constant c_eth_packet_size : natural := c_eth_header_size + c_eth_crc_size + c_sdp_N_sub * (c_sdp_W_statistic / c_word_w);
constant c_eth_check_nof_valid : natural := c_eth_check_nof_packets * c_eth_packet_size;
-- eth statistics should be done after c_nof_sync + 1 intervals (+1 because first new_interval is skipped)
@@ -136,12 +144,17 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -196,7 +209,8 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
begin
@@ -207,9 +221,12 @@ begin
-- Enable BSN
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk); -- Enable BSN immediately
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BSN immediately
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk);
----------------------------------------------------------------------------
-- Read weighted subband selector
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
index 5ee8de349555ef55110c507da66066e4cebbe049..0e236a6ca00665a3fadee5524c46b9a73d79a3ea 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
@@ -34,7 +34,8 @@ entity tb_tb_lofar2_unb2c_sdp_station_fsub is
end tb_tb_lofar2_unb2c_sdp_station_fsub;
architecture tb of tb_tb_lofar2_unb2c_sdp_station_fsub is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Commented to save sim time in regression test
-- u_fsub_only_co : ENTITY work.tb_lofar2_unb2c_sdp_station_fsub
@@ -54,16 +55,26 @@ begin
u_fsub_use_cross : entity work.tb_lofar2_unb2c_sdp_station_fsub
generic map (
- g_sp => 3, -- signal path index in range(S_pn = 12) of co-polarization
- g_co_wg_ampl => 0.5, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
- g_cross_wg_ampl => 0.4, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
- g_cross_wg_phase => 90.0, -- WG phase in degrees for cross-sp, relative to co-sp
- g_subband => 102, -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- g_co_subband_weight_gain => 1.0, -- subband weight normalized gain, for co-polarization in g_sp
- g_co_subband_weight_phase => 30.0, -- subband weight phase rotation in degrees, for co-polarization in g_sp
+ -- signal path index in range(S_pn = 12) of co-polarization
+ g_sp => 3,
+ -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ g_co_wg_ampl => 0.5,
+ -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ g_cross_wg_ampl => 0.4,
+ -- WG phase in degrees for cross-sp, relative to co-sp
+ g_cross_wg_phase => 90.0,
+ -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_subband => 102,
+ -- subband weight normalized gain, for co-polarization in g_sp
+ g_co_subband_weight_gain => 1.0,
+ -- subband weight phase rotation in degrees, for co-polarization in g_sp
+ g_co_subband_weight_phase => 30.0,
g_use_cross_weight => true,
- g_sp_cross_subband_weight_gain => 0.5, -- subband weight normalized gain, for cross polarization of g_sp
- g_sp_cross_subband_weight_phase => -10.0, -- subband weight phase rotation in degrees, for cross polarization of g_sp
- g_read_all_SST => true -- when FALSE only read SST for g_subband, to save sim time
+ -- subband weight normalized gain, for cross polarization of g_sp
+ g_sp_cross_subband_weight_gain => 0.5,
+ -- subband weight phase rotation in degrees, for cross polarization of g_sp
+ g_sp_cross_subband_weight_phase => -10.0,
+ -- when FALSE only read SST for g_subband, to save sim time
+ g_read_all_SST => true
);
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
index f637461c321b7f1416fadff1251f8bba7facf813..11ff582e0c12b223d3ab225afd6bc7293430618a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2c_sdp_station_full is
generic (
g_design_name : string := "lofar2_unb2c_sdp_station_full";
g_design_note : string := "Lofar2 SDP station full design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -64,7 +73,8 @@ entity lofar2_unb2c_sdp_station_full is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP0 for Ring.
QSFP_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -77,18 +87,22 @@ entity lofar2_unb2c_sdp_station_full is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (note only 12 are used in unb2c)
- BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0)
);
end lofar2_unb2c_sdp_station_full;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
index 9e7d7250d9cc32cdaaad1ae0a4d120d643c38ca4..035af76e83d2328d6e069eef04b633aa42bd5587 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2c_sdp_station_full_wg is
generic (
g_design_name : string := "lofar2_unb2c_sdp_station_full_wg";
g_design_note : string := "Lofar2 SDP station full design WG";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -64,7 +73,8 @@ entity lofar2_unb2c_sdp_station_full_wg is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP0 for Ring.
QSFP_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -77,7 +87,8 @@ entity lofar2_unb2c_sdp_station_full_wg is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0)
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
index d210c368ad6efc98f279a3d97fe2809eb83f8294..9a194cc203ab4083bf1cfde2894bb2e97ec8adfa 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2c_sdp_station_xsub_one is
generic (
g_design_name : string := "lofar2_unb2c_sdp_station_xsub_one";
g_design_note : string := "Lofar2 SDP station subband correlator design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -67,12 +76,15 @@ entity lofar2_unb2c_sdp_station_xsub_one is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- back transceivers (note only 12 are used in unb2c)
- BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0)
);
end lofar2_unb2c_sdp_station_xsub_one;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
index ae39ff5891c1972fcf7a040bd245d465d9095cbc..f3a3d6bdf511f01c84c01c48dd6693a8fffd3030 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -66,17 +66,20 @@ end tb_lofar2_unb2c_sdp_station_xsub_one;
architecture tb of tb_lofar2_unb2c_sdp_station_xsub_one is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_nof_block_per_sync : natural := 20;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
@@ -84,20 +87,28 @@ architecture tb of tb_lofar2_unb2c_sdp_station_xsub_one is
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
constant c_ctrl_interval_size : natural := c_nof_clk_per_sync;
- constant c_max_ratio : real := 0.0001; -- ratio that actual value may differ from expected value
+ -- ratio that actual value may differ from expected value
+ constant c_max_ratio : real := 0.0001;
-- WG
- constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_sp_ampl : real := 0.25; -- WG normalized amplitude, 1.0 = FS (full scale), use <= 0.25 to avoid XST overflow
- constant c_wg_ampl : natural := natural(c_sp_ampl * real(c_sdp_FS_adc)); -- in number of lsb
- constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
- constant c_subband_sp : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := 2;
+ -- WG normalized amplitude, 1.0 = FS (full scale), use <= 0.25 to avoid XST overflow
+ constant c_sp_ampl : real := 0.25;
+ -- in number of lsb
+ constant c_wg_ampl : natural := natural(c_sp_ampl * real(c_sdp_FS_adc));
+ -- in freq_unit
+ constant c_wg_freq_offset : real := 0.0 / 11.0;
+ -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ constant c_subband_sp : real := 102.0;
-- WPFB
constant c_exp_subband_ampl : real := real(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio;
- constant c_exp_subband_power : real := c_exp_subband_ampl**2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
+ -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
+ constant c_exp_subband_power : real := c_exp_subband_ampl**2.0;
constant c_exp_subband_sst : real := c_exp_subband_power * real(c_nof_block_per_sync);
- constant c_exp_subband_xst : real := c_exp_subband_sst; -- all signal inputs use same WG, and auto correlation XST = SST
+ -- all signal inputs use same WG, and auto correlation XST = SST
+ constant c_exp_subband_xst : real := c_exp_subband_sst;
type t_real_arr is array (integer range <>) of real;
@@ -147,12 +158,17 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -208,12 +224,14 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
variable v_sp_subband_power : real;
- variable v_W, v_C, v_A, v_X, v_B, v_A_even, v_B_even : natural; -- array indicies
+ -- array indicies
+ variable v_W, v_C, v_A, v_X, v_B, v_A_even, v_B_even : natural;
begin
-- Wait for DUT power up after reset
wait for 1 us;
@@ -222,9 +240,12 @@ begin
-- Enable BSN
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BSN at PPS
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BSN at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk);
-- Release PPS pulser, to get first PPS now and to start BSN source
wait for 1 us;
@@ -233,8 +254,10 @@ begin
----------------------------------------------------------------------------
-- Crosslets Info
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 0, integer(c_subband_sp), tb_clk); -- offset
- mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 15, 0 , tb_clk); -- stepsize
+ -- offset
+ mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 0, integer(c_subband_sp), tb_clk);
+ -- stepsize
+ mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 15, 0 , tb_clk);
----------------------------------------------------------------------------
-- Enable WG
@@ -245,10 +268,14 @@ begin
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
for I in 0 to c_sdp_S_pn - 1 loop
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 1, integer(0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 2, integer((c_subband_sp + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 1, integer(0.0 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 2, integer((c_subband_sp + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk);
end loop;
-- Read current BSN
@@ -259,18 +286,26 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
-- bsn_scheduler_xsub
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_bsn_start_wg, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- assume v_bsn < 2**31-1
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable
+ -- Interval size
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk);
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_bsn_start_wg, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk);
+ -- enable
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk);
-- Wait for enough WG data and start of sync interval
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
+ -- read BSN low
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
+ -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3,
c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
index 657a3cebece3eccf10a661c3f3d048487d7d783a..48fba7961db9b81dd28cacd53cef9a747822ea33 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
@@ -77,40 +77,53 @@ end tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload;
architecture tb of tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload is
constant c_sim : boolean := true;
constant c_unb_nr : natural := sel_a_b(g_try_xst_restart, 0, 2);
- constant c_node_nr : natural := sel_a_b(g_try_xst_restart, 0, 1); -- use node > 0 to check nof_cycles_dly in sdp_statistics_offload.vhd
- constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr * 4 + c_node_nr, 8); -- c_unb2c_board_nof_node = 4, c_unb2c_board_aux.id_w = 8
+ -- use node > 0 to check nof_cycles_dly in sdp_statistics_offload.vhd
+ constant c_node_nr : natural := sel_a_b(g_try_xst_restart, 0, 1);
+ -- c_unb2c_board_nof_node = 4, c_unb2c_board_aux.id_w = 8
+ constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr * 4 + c_node_nr, 8);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
- constant c_nof_block_per_sync : natural := 16; -- long enough to stream out udp data
+ -- long enough to stream out udp data
+ constant c_nof_block_per_sync : natural := 16;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
constant c_pps_period : natural := c_nof_clk_per_sync;
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
constant c_ctrl_interval_size : natural := c_nof_clk_per_sync;
- constant c_nof_crosslets : natural := 3; -- not too large, so that offload still fits in c_nof_block_per_sync
+ -- not too large, so that offload still fits in c_nof_block_per_sync
+ constant c_nof_crosslets : natural := 3;
constant c_subband_select_arr : t_natural_arr(0 to c_sdp_N_crosslets_max - 1) := (10, 11, 12, 13, 14, 15, 16);
- constant c_subband_step : natural := 3; -- e.g. 0 or c_nof_crosslets
+ -- e.g. 0 or c_nof_crosslets
+ constant c_subband_step : natural := 3;
constant c_nof_sync : natural := 3;
- constant c_max_ratio : real := 0.001; -- ratio that actual value may differ from expected value
+ -- ratio that actual value may differ from expected value
+ constant c_max_ratio : real := 0.001;
-- WG
constant c_bsn_start_wg : natural := 2;
- constant c_sp_ampl : real := 0.25; -- WG normalized amplitude, 1.0 = FS (full scale), use <= 0.25 to avoid XST overflow
- constant c_wg_ampl : natural := natural(c_sp_ampl * real(c_sdp_FS_adc)); -- in number of lsb
+ -- WG normalized amplitude, 1.0 = FS (full scale), use <= 0.25 to avoid XST overflow
+ constant c_sp_ampl : real := 0.25;
+ -- in number of lsb
+ constant c_wg_ampl : natural := natural(c_sp_ampl * real(c_sdp_FS_adc));
constant c_wg_subband : natural := 12;
-- WPFB
- constant c_exp_subband_ampl : real := real(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio; -- = c_wg_ampl * 0.994817 * 8
- constant c_exp_subband_power : real := c_exp_subband_ampl**2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
+ -- = c_wg_ampl * 0.994817 * 8
+ constant c_exp_subband_ampl : real := real(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio;
+ -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
+ constant c_exp_subband_power : real := c_exp_subband_ampl**2.0;
constant c_exp_subband_sst : real := c_exp_subband_power * real(c_nof_block_per_sync);
- constant c_exp_subband_xst : real := c_exp_subband_sst; -- all signal inputs use same WG, and auto correlation XST = SST
+ -- all signal inputs use same WG, and auto correlation XST = SST
+ constant c_exp_subband_xst : real := c_exp_subband_sst;
-- MM
constant c_mm_file_reg_bsn_source_v2 : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
@@ -130,11 +143,15 @@ architecture tb of tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload is
-- . 1GbE output
constant c_eth_check_nof_packets : natural := c_nof_sync * c_nof_crosslets;
- constant c_eth_header_size : natural := 19; -- words
- constant c_eth_crc_size : natural := 1; -- word
- constant c_eth_packet_size : natural := c_eth_header_size + c_eth_crc_size + (c_sdp_W_statistic / c_word_w) * c_sdp_S_pn * c_sdp_S_pn * c_nof_complex; -- 20 + 2 * 12 * 12 * 2 = 596
+ -- words
+ constant c_eth_header_size : natural := 19;
+ -- word
+ constant c_eth_crc_size : natural := 1;
+ -- 20 + 2 * 12 * 12 * 2 = 596
+ constant c_eth_packet_size : natural := c_eth_header_size + c_eth_crc_size + (c_sdp_W_statistic / c_word_w) * c_sdp_S_pn * c_sdp_S_pn * c_nof_complex;
constant c_eth_check_nof_valid : natural := c_eth_check_nof_packets * c_eth_packet_size;
- constant c_eth_runtime_timeout : time := (c_nof_sync + 3) * c_nof_clk_per_sync * c_ext_clk_period; -- eth statistics should be done after c_nof_sync
+ -- eth statistics should be done after c_nof_sync
+ constant c_eth_runtime_timeout : time := (c_nof_sync + 3) * c_nof_clk_per_sync * c_ext_clk_period;
-- DUT
signal ext_clk : std_logic := '0';
@@ -187,12 +204,17 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2;
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= not JESD204B_REFCLK after c_bck_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -247,7 +269,8 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
@@ -259,9 +282,12 @@ begin
-- Enable BSN
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk); -- Enable BSN immediately
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BSN immediately
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk);
-- Release PPS pulser, to get first PPS now and to start BSN source
wait for 1 us;
@@ -276,10 +302,14 @@ begin
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
for I in 0 to c_sdp_S_pn - 1 loop
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 1, integer(0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 2, integer(real(c_wg_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 1, integer(0.0 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 2, integer(real(c_wg_subband) * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk);
end loop;
-- Read current BSN
@@ -290,8 +320,10 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
----------------------------------------------------------------------------
-- Setup and enable xsub
@@ -299,18 +331,24 @@ begin
-- Crosslets info
for I in 0 to c_sdp_N_crosslets_max - 1 loop
- mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, I, c_subband_select_arr(I), tb_clk); -- offsets
+ -- offsets
+ mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, I, c_subband_select_arr(I), tb_clk);
end loop;
- mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 15, c_subband_step, tb_clk); -- step size
+ -- step size
+ mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 15, c_subband_step, tb_clk);
-- Number of crosslets
mmf_mm_bus_wr(c_mm_file_reg_nof_crosslets, 0, c_nof_crosslets, tb_clk);
-- Integration interval and enable
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_nof_block_per_sync, tb_clk); -- first write bsn low then bsn high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- bsn high, assume v_bsn < 2**31-1
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable
+ -- Interval size
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk);
+ -- first write bsn low then bsn high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_nof_block_per_sync, tb_clk);
+ -- bsn high, assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk);
+ -- enable
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk);
----------------------------------------------------------------------------
-- XST offload enable
@@ -335,8 +373,10 @@ begin
-- XST processing enable
v_bsn := TO_UINT(current_bsn_wg) + 7;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, v_bsn, tb_clk); -- first write bsn low then bsn high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- bsn high, assume v_bsn < 2**31-1
+ -- first write bsn low then bsn high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, v_bsn, tb_clk);
+ -- bsn high, assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk);
proc_common_wait_some_cycles(ext_clk, c_nof_clk_per_sync * 4);
end if;
@@ -427,13 +467,15 @@ begin
end if;
if rx_offload_sosi.sop = '1' then
- rx_sdp_stat_index <= 0; -- restart per Rx packet
+ -- restart per Rx packet
+ rx_sdp_stat_index <= 0;
end if;
end if;
end process;
p_rx_sdp_verify_stat_data : process(eth_clk(0))
- variable v_subband_ix : natural; -- _ix = index
+ -- _ix = index
+ variable v_subband_ix : natural;
begin
if rising_edge(eth_clk(0)) then
v_subband_ix := TO_UINT(rx_sdp_stat_header.app.sdp_data_id_xst_subband_index);
@@ -462,6 +504,8 @@ begin
end process;
-- rx_sdp_stat_index counts the S_pn * S_pn = X_sq = 12 * 12 = 144 complex statistics
- rx_a_sp <= rx_sdp_stat_index / c_sdp_S_pn; -- signal input A
- rx_b_sp <= rx_sdp_stat_index mod c_sdp_S_pn; -- signal input B
+ -- signal input A
+ rx_a_sp <= rx_sdp_stat_index / c_sdp_S_pn;
+ -- signal input B
+ rx_b_sp <= rx_sdp_stat_index mod c_sdp_S_pn;
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
index 40b0196d31b2f7a8aed0ebb53653aa608a97bd41..367199793bf689a4a2698d086cc7f7cdca47108d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
@@ -38,20 +38,29 @@ entity lofar2_unb2c_sdp_station_xsub_ring is
generic (
g_design_name : string := "lofar2_unb2c_sdp_station_xsub_ring";
g_design_note : string := "Lofar2 SDP station xsub_ring design";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -64,7 +73,8 @@ entity lofar2_unb2c_sdp_station_xsub_ring is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP0 for Ring.
QSFP_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -77,18 +87,22 @@ entity lofar2_unb2c_sdp_station_xsub_ring is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (note only 12 are used in unb2c)
- BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
+ BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0);
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : in std_logic;
- JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0)
);
end lofar2_unb2c_sdp_station_xsub_ring;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index 0d4176a1f28ac31a330e9db3848355a5be3569f8..09e434fbd1b2aeba6b8c535f5ce57445ab5f568e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -46,25 +46,35 @@ entity lofar2_unb2c_sdp_station is
generic (
g_design_name : string := "lofar2_unb2c_sdp_station";
g_design_note : string := "UNUSED";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := false;
g_protect_addr_range : boolean := false;
g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
- g_bsn_nof_clk_per_sync : natural := c_sdp_N_clk_per_sync; -- Default 200M, overide for short simulation
+ -- Default 200M, overide for short simulation
+ g_bsn_nof_clk_per_sync : natural := c_sdp_N_clk_per_sync;
g_scope_selected_subband : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -77,7 +87,8 @@ entity lofar2_unb2c_sdp_station is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers QSFP0 for Ring.
QSFP_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -88,7 +99,8 @@ entity lofar2_unb2c_sdp_station is
QSFP_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
@@ -97,13 +109,16 @@ entity lofar2_unb2c_sdp_station is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- back transceivers (Note: numbered from 0)
- JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0) := (others => '0'); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
+ -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
+ JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0) := (others => '0');
-- Connect to the BCK_RX pins in the top wrapper
- JESD204B_REFCLK : in std_logic := '0'; -- Connect to BCK_REF_CLK pin in the top level wrapper
+ -- Connect to BCK_REF_CLK pin in the top level wrapper
+ JESD204B_REFCLK : in std_logic := '0';
-- jesd204b syncronization signals
JESD204B_SYSREF : in std_logic := '0';
- JESD204B_SYNC_N : out std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0) -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ JESD204B_SYNC_N : out std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0)
);
end lofar2_unb2c_sdp_station;
@@ -157,12 +172,16 @@ architecture str of lofar2_unb2c_sdp_station is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_copi : t_mem_copi := c_mem_copi_rst; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_copi : t_mem_copi := c_mem_copi_rst;
signal eth1g_tse_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal eth1g_reg_copi : t_mem_copi := c_mem_copi_rst; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_copi : t_mem_copi := c_mem_copi_rst;
signal eth1g_reg_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_copi : t_mem_copi := c_mem_copi_rst; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_copi : t_mem_copi := c_mem_copi_rst;
signal eth1g_ram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS read
@@ -499,7 +518,8 @@ begin
mm_rst => mm_rst,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ -- Can be external 200MHz, or PLL generated
+ dp_clk => dp_clk,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
@@ -999,7 +1019,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
index 663256c83f518a47f01c77824404e95a6ad0b0a7..4b0c1abd88e4f98ce6b53d27004c2f005efb3a16 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
@@ -32,7 +32,8 @@ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2c_sdp_station is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index 3fa9fa61c5117114f1c2adc01c8057ee2b2dd77c..3ab022eccb6b17955a509beec14fa6c24e831ade 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -27,539 +27,1072 @@ package qsys_lofar2_unb2c_sdp_station_pkg is
-----------------------------------------------------------------------------
component qsys_lofar2_unb2c_sdp_station is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_reset_export : out std_logic; -- export
- ram_st_histogram_clk_export : out std_logic; -- export
- ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
- ram_st_histogram_write_export : out std_logic; -- export
- ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_read_export : out std_logic; -- export
- ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
- ram_st_xsq_clk_export : out std_logic; -- export
- ram_st_xsq_read_export : out std_logic; -- export
- ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_xsq_reset_export : out std_logic; -- export
- ram_st_xsq_write_export : out std_logic; -- export
- ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
- reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
- reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_align_v2_bf_write_export : out std_logic; -- export
- reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_read_export : out std_logic; -- export
- reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_crosslets_info_clk_export : out std_logic; -- export
- reg_crosslets_info_read_export : out std_logic; -- export
- reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_reset_export : out std_logic; -- export
- reg_crosslets_info_write_export : out std_logic; -- export
- reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_reset_export : out std_logic; -- export
- reg_nof_crosslets_clk_export : out std_logic; -- export
- reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nof_crosslets_write_export : out std_logic; -- export
- reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_read_export : out std_logic; -- export
- reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_bf_reset_export : out std_logic; -- export
- reg_ring_lane_info_bf_clk_export : out std_logic; -- export
- reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_lane_info_bf_write_export : out std_logic; -- export
- reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_bf_read_export : out std_logic; -- export
- reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_xst_reset_export : out std_logic; -- export
- reg_ring_lane_info_xst_clk_export : out std_logic; -- export
- reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ring_lane_info_xst_write_export : out std_logic; -- export
- reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_xst_read_export : out std_logic; -- export
- reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_stat_enable_bst_clk_export : out std_logic; -- export
- reg_stat_enable_bst_read_export : out std_logic; -- export
- reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_bst_reset_export : out std_logic; -- export
- reg_stat_enable_bst_write_export : out std_logic; -- export
- reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_sst_clk_export : out std_logic; -- export
- reg_stat_enable_sst_read_export : out std_logic; -- export
- reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_sst_reset_export : out std_logic; -- export
- reg_stat_enable_sst_write_export : out std_logic; -- export
- reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_xst_clk_export : out std_logic; -- export
- reg_stat_enable_xst_read_export : out std_logic; -- export
- reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_xst_reset_export : out std_logic; -- export
- reg_stat_enable_xst_write_export : out std_logic; -- export
- reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_cross_reset_export : out std_logic; -- export
- ram_equalizer_gains_cross_clk_export : out std_logic; -- export
- ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_cross_write_export : out std_logic; -- export
- ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_cross_read_export : out std_logic; -- export
- ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ jesd204b_address_export : out std_logic_vector(11 downto 0);
+ -- export
+ jesd204b_clk_export : out std_logic;
+ -- export
+ jesd204b_read_export : out std_logic;
+ -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ jesd204b_reset_export : out std_logic;
+ -- export
+ jesd204b_write_export : out std_logic;
+ -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_jesd_ctrl_clk_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_read_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_jesd_ctrl_reset_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_write_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ ram_bf_weights_reset_export : out std_logic;
+ -- export
+ ram_bf_weights_clk_export : out std_logic;
+ -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0);
+ -- export
+ ram_bf_weights_write_export : out std_logic;
+ -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_bf_weights_read_export : out std_logic;
+ -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0);
+ -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_equalizer_gains_reset_export : out std_logic;
+ -- export
+ ram_equalizer_gains_clk_export : out std_logic;
+ -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_equalizer_gains_write_export : out std_logic;
+ -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_equalizer_gains_read_export : out std_logic;
+ -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_fil_coefs_address_export : out std_logic_vector(14 downto 0);
+ -- export
+ ram_fil_coefs_clk_export : out std_logic;
+ -- export
+ ram_fil_coefs_read_export : out std_logic;
+ -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_fil_coefs_reset_export : out std_logic;
+ -- export
+ ram_fil_coefs_write_export : out std_logic;
+ -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0);
+ -- export
+ ram_scrap_clk_export : out std_logic;
+ -- export
+ ram_scrap_read_export : out std_logic;
+ -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_scrap_reset_export : out std_logic;
+ -- export
+ ram_scrap_write_export : out std_logic;
+ -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_ss_ss_wide_clk_export : out std_logic;
+ -- export
+ ram_ss_ss_wide_read_export : out std_logic;
+ -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_ss_ss_wide_reset_export : out std_logic;
+ -- export
+ ram_ss_ss_wide_write_export : out std_logic;
+ -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0);
+ -- export
+ ram_st_bst_clk_export : out std_logic;
+ -- export
+ ram_st_bst_read_export : out std_logic;
+ -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_st_bst_reset_export : out std_logic;
+ -- export
+ ram_st_bst_write_export : out std_logic;
+ -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_st_histogram_reset_export : out std_logic;
+ -- export
+ ram_st_histogram_clk_export : out std_logic;
+ -- export
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ ram_st_histogram_write_export : out std_logic;
+ -- export
+ ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_st_histogram_read_export : out std_logic;
+ -- export
+ ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_st_sst_address_export : out std_logic_vector(14 downto 0);
+ -- export
+ ram_st_sst_clk_export : out std_logic;
+ -- export
+ ram_st_sst_read_export : out std_logic;
+ -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_st_sst_reset_export : out std_logic;
+ -- export
+ ram_st_sst_write_export : out std_logic;
+ -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_st_xsq_address_export : out std_logic_vector(15 downto 0);
+ -- export
+ ram_st_xsq_clk_export : out std_logic;
+ -- export
+ ram_st_xsq_read_export : out std_logic;
+ -- export
+ ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_st_xsq_reset_export : out std_logic;
+ -- export
+ ram_st_xsq_write_export : out std_logic;
+ -- export
+ ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_wg_clk_export : out std_logic;
+ -- export
+ ram_wg_read_export : out std_logic;
+ -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_wg_reset_export : out std_logic;
+ -- export
+ ram_wg_write_export : out std_logic;
+ -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_aduh_monitor_clk_export : out std_logic;
+ -- export
+ reg_aduh_monitor_read_export : out std_logic;
+ -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_aduh_monitor_reset_export : out std_logic;
+ -- export
+ reg_aduh_monitor_write_export : out std_logic;
+ -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_bf_scale_clk_export : out std_logic;
+ -- export
+ reg_bf_scale_read_export : out std_logic;
+ -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bf_scale_reset_export : out std_logic;
+ -- export
+ reg_bf_scale_write_export : out std_logic;
+ -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_align_v2_bf_reset_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_bf_clk_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_bsn_align_v2_bf_write_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_align_v2_bf_read_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_align_v2_xsub_reset_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_xsub_clk_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_bsn_align_v2_xsub_write_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_align_v2_xsub_read_export : out std_logic;
+ -- export
+ reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0);
+ -- export
+ reg_bsn_monitor_input_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_input_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_bsn_monitor_v2_bst_offload_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_bst_offload_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_bsn_monitor_v2_sst_offload_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_sst_offload_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_bsn_monitor_v2_xst_offload_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_xst_offload_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_bsn_scheduler_clk_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_read_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_scheduler_reset_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_write_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_bsn_source_v2_clk_export : out std_logic;
+ -- export
+ reg_bsn_source_v2_read_export : out std_logic;
+ -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_source_v2_reset_export : out std_logic;
+ -- export
+ reg_bsn_source_v2_write_export : out std_logic;
+ -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic;
+ -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic;
+ -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic;
+ -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic;
+ -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_crosslets_info_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_crosslets_info_clk_export : out std_logic;
+ -- export
+ reg_crosslets_info_read_export : out std_logic;
+ -- export
+ reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_crosslets_info_reset_export : out std_logic;
+ -- export
+ reg_crosslets_info_write_export : out std_logic;
+ -- export
+ reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic;
+ -- export
+ reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_block_validate_err_bf_reset_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_bf_clk_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_dp_block_validate_err_bf_write_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_block_validate_err_bf_read_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_block_validate_err_xst_reset_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_xst_clk_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_dp_block_validate_err_xst_write_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_block_validate_err_xst_read_export : out std_logic;
+ -- export
+ reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dp_selector_clk_export : out std_logic;
+ -- export
+ reg_dp_selector_read_export : out std_logic;
+ -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_selector_reset_export : out std_logic;
+ -- export
+ reg_dp_selector_write_export : out std_logic;
+ -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_dp_shiftram_clk_export : out std_logic;
+ -- export
+ reg_dp_shiftram_read_export : out std_logic;
+ -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_shiftram_reset_export : out std_logic;
+ -- export
+ reg_dp_shiftram_write_export : out std_logic;
+ -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_dp_xonoff_clk_export : out std_logic;
+ -- export
+ reg_dp_xonoff_read_export : out std_logic;
+ -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_xonoff_reset_export : out std_logic;
+ -- export
+ reg_dp_xonoff_write_export : out std_logic;
+ -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_hdr_dat_clk_export : out std_logic;
+ -- export
+ reg_hdr_dat_read_export : out std_logic;
+ -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_hdr_dat_reset_export : out std_logic;
+ -- export
+ reg_hdr_dat_write_export : out std_logic;
+ -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_nof_crosslets_reset_export : out std_logic;
+ -- export
+ reg_nof_crosslets_clk_export : out std_logic;
+ -- export
+ reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_nof_crosslets_write_export : out std_logic;
+ -- export
+ reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_nof_crosslets_read_export : out std_logic;
+ -- export
+ reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic;
+ -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic;
+ -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic;
+ -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic;
+ -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic;
+ -- export
+ reg_nw_10gbe_mac_read_export : out std_logic;
+ -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic;
+ -- export
+ reg_nw_10gbe_mac_write_export : out std_logic;
+ -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ring_info_reset_export : out std_logic;
+ -- export
+ reg_ring_info_clk_export : out std_logic;
+ -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_ring_info_write_export : out std_logic;
+ -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ring_info_read_export : out std_logic;
+ -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_ring_lane_info_bf_reset_export : out std_logic;
+ -- export
+ reg_ring_lane_info_bf_clk_export : out std_logic;
+ -- export
+ reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_ring_lane_info_bf_write_export : out std_logic;
+ -- export
+ reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ring_lane_info_bf_read_export : out std_logic;
+ -- export
+ reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_ring_lane_info_xst_reset_export : out std_logic;
+ -- export
+ reg_ring_lane_info_xst_clk_export : out std_logic;
+ -- export
+ reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_ring_lane_info_xst_write_export : out std_logic;
+ -- export
+ reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ring_lane_info_xst_read_export : out std_logic;
+ -- export
+ reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_sdp_info_clk_export : out std_logic;
+ -- export
+ reg_sdp_info_read_export : out std_logic;
+ -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_sdp_info_reset_export : out std_logic;
+ -- export
+ reg_sdp_info_write_export : out std_logic;
+ -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_si_clk_export : out std_logic;
+ -- export
+ reg_si_read_export : out std_logic;
+ -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_si_reset_export : out std_logic;
+ -- export
+ reg_si_write_export : out std_logic;
+ -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_stat_enable_bst_clk_export : out std_logic;
+ -- export
+ reg_stat_enable_bst_read_export : out std_logic;
+ -- export
+ reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stat_enable_bst_reset_export : out std_logic;
+ -- export
+ reg_stat_enable_bst_write_export : out std_logic;
+ -- export
+ reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_stat_enable_sst_clk_export : out std_logic;
+ -- export
+ reg_stat_enable_sst_read_export : out std_logic;
+ -- export
+ reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stat_enable_sst_reset_export : out std_logic;
+ -- export
+ reg_stat_enable_sst_write_export : out std_logic;
+ -- export
+ reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_stat_enable_xst_clk_export : out std_logic;
+ -- export
+ reg_stat_enable_xst_read_export : out std_logic;
+ -- export
+ reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stat_enable_xst_reset_export : out std_logic;
+ -- export
+ reg_stat_enable_xst_write_export : out std_logic;
+ -- export
+ reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_stat_hdr_dat_bst_clk_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_bst_read_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stat_hdr_dat_bst_reset_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_bst_write_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_stat_hdr_dat_sst_clk_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_sst_read_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stat_hdr_dat_sst_reset_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_sst_write_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_stat_hdr_dat_xst_clk_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_xst_read_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_stat_hdr_dat_xst_reset_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_xst_write_export : out std_logic;
+ -- export
+ reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic;
+ -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0);
+ -- export
+ reg_tr_10gbe_mac_write_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_mac_read_export : out std_logic;
+ -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_wg_clk_export : out std_logic;
+ -- export
+ reg_wg_read_export : out std_logic;
+ -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wg_reset_export : out std_logic;
+ -- export
+ reg_wg_write_export : out std_logic;
+ -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_equalizer_gains_cross_reset_export : out std_logic;
+ -- export
+ ram_equalizer_gains_cross_clk_export : out std_logic;
+ -- export
+ ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_equalizer_gains_cross_write_export : out std_logic;
+ -- export
+ ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_equalizer_gains_cross_read_export : out std_logic;
+ -- export
+ ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X')
);
end component qsys_lofar2_unb2c_sdp_station;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
index 8bdf7bca758f73305d94c939022399788dfe337d..d78d43972b51b01b0be15c8c88467920f1b3261e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
@@ -51,16 +51,19 @@ end tb_lofar2_unb2c_sdp_station;
architecture tb of tb_lofar2_unb2c_sdp_station is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_nof_block_per_sync : natural := 16;
constant c_nof_clk_per_sync : natural := c_nof_block_per_sync * c_sdp_N_fft;
@@ -68,9 +71,12 @@ architecture tb of tb_lofar2_unb2c_sdp_station is
constant c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
-- WG
- constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp_0 : natural := 2**(c_sdp_W_adc - 1) / 2; -- in number of lsb
- constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ constant c_bsn_start_wg : natural := 2;
+ -- in number of lsb
+ constant c_ampl_sp_0 : natural := 2**(c_sdp_W_adc - 1) / 2;
+ -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ constant c_subband_sp_0 : real := 102.0;
-- 1GbE output
constant c_eth_check_nof_packets : natural := 1;
@@ -116,17 +122,21 @@ architecture tb of tb_lofar2_unb2c_sdp_station is
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
begin
-- System setup
- ext_clk <= (not ext_clk) or tb_end after c_ext_clk_period / 2; -- External clock (200 MHz)
+ -- External clock (200 MHz)
+ ext_clk <= (not ext_clk) or tb_end after c_ext_clk_period / 2;
-- Ethernet ref clock (125 MHz)
eth_clk_slv(0) <= (not eth_clk_slv(0)) or tb_end after c_eth_clk_period / 2;
- eth_clk_slv(1) <= '0'; -- not used
+ -- not used
+ eth_clk_slv(1) <= '0';
-- JESD sample clock (200MHz)
JESD204B_REFCLK <= (not JESD204B_REFCLK) or tb_end after c_bck_ref_clk_period / 2;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
-- External PPS
proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
@@ -177,7 +187,8 @@ begin
---------------------------------------------------------------------------------------------------------------------
-- Stimuli
-- MM slave accesses via file IO
- tb_clk <= (not tb_clk) or tb_end after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= (not tb_clk) or tb_end after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
@@ -189,9 +200,12 @@ begin
-- Enable BS
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 1, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 1, tb_clk);
+ -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);
+ -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk);
-- Enable WG
-- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3)
@@ -199,10 +213,14 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer(c_subband_sp_0 * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+ -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk);
+ -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk);
+ -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer(c_subband_sp_0 * c_sdp_wg_subband_freq_unit), tb_clk);
+ -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk);
-- Read current BSN
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 downto 0), tb_clk);
@@ -213,8 +231,10 @@ begin
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
v_bsn := c_bsn_start_wg;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);
+ -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk);
-- Wait for ADUH monitor to have filled with WG data
wait for c_sdp_T_sub * c_sdp_N_taps;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
index c784b9032b3cddb878ec4eb192b2d5252c0787ed..ba29c584d32e79d445a029894e8363f99a431e9d 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
@@ -39,19 +39,32 @@ entity ddrctrl_controller is
generic (
g_tech_ddr : t_c_tech_ddr;
g_stop_percentage : natural := 50;
- g_nof_streams : natural; -- 12
- g_out_data_w : natural; -- 14
- g_wr_data_w : natural; -- 168
- g_rd_fifo_depth : natural; -- 256
- g_rd_data_w : natural; -- 256
- g_block_size : natural; -- 1024
- g_wr_fifo_uw_w : natural; -- 8
- g_rd_fifo_uw_w : natural; -- 8
- g_max_adr : natural; -- 16128
- g_burstsize : natural; -- 64
- g_last_burstsize : natural; -- 18
- g_adr_per_b : natural; -- 299
- g_bim : natural -- 54
+ -- 12
+ g_nof_streams : natural;
+ -- 14
+ g_out_data_w : natural;
+ -- 168
+ g_wr_data_w : natural;
+ -- 256
+ g_rd_fifo_depth : natural;
+ -- 256
+ g_rd_data_w : natural;
+ -- 1024
+ g_block_size : natural;
+ -- 8
+ g_wr_fifo_uw_w : natural;
+ -- 8
+ g_rd_fifo_uw_w : natural;
+ -- 16128
+ g_max_adr : natural;
+ -- 64
+ g_burstsize : natural;
+ -- 18
+ g_last_burstsize : natural;
+ -- 299
+ g_adr_per_b : natural;
+ -- 54
+ g_bim : natural
);
port (
clk : in std_logic;
@@ -82,17 +95,23 @@ entity ddrctrl_controller is
end ddrctrl_controller;
architecture rtl of ddrctrl_controller is
- constant c_bitshift_w : natural := ceil_log2(g_burstsize); -- bitshift to make sure there is only a burst start at a interval of c_burstsize.
- constant c_adr_w : natural := func_tech_ddr_ctlr_address_w( g_tech_ddr ); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
- constant c_pof_ma : natural := (((g_max_adr * (100 - g_stop_percentage)) / 100) / g_adr_per_b) * g_adr_per_b; -- percentage of max address.
+ -- bitshift to make sure there is only a burst start at a interval of c_burstsize.
+ constant c_bitshift_w : natural := ceil_log2(g_burstsize);
+ -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
+ constant c_adr_w : natural := func_tech_ddr_ctlr_address_w( g_tech_ddr );
+ -- percentage of max address.
+ constant c_pof_ma : natural := (((g_max_adr * (100 - g_stop_percentage)) / 100) / g_adr_per_b) * g_adr_per_b;
constant c_zeros : std_logic_vector(c_bitshift_w - 1 downto 0) := (others => '0');
-- constant for reading
- constant c_rd_data_w : natural := g_nof_streams * g_out_data_w; -- 168
- constant c_rest : natural := c_rd_data_w - (g_wr_data_w mod c_rd_data_w); -- 96
- constant c_io_ddr_data_w : natural := func_tech_ddr_ctlr_data_w(g_tech_ddr); -- 576
+ -- 168
+ constant c_rd_data_w : natural := g_nof_streams * g_out_data_w;
+ -- 96
+ constant c_rest : natural := c_rd_data_w - (g_wr_data_w mod c_rd_data_w);
+ -- 576
+ constant c_io_ddr_data_w : natural := func_tech_ddr_ctlr_data_w(g_tech_ddr);
-- type for statemachine
type t_state is (RESET, STOP_READING, WAIT_FOR_SOP, WRITING, SET_STOP, STOP_WRITING, LAST_WRITE_BURST, START_READING, READING);
@@ -197,7 +216,8 @@ begin
v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
else
v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0);
v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
end if;
else
@@ -255,7 +275,8 @@ begin
v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
else
v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0);
v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
end if;
else
@@ -292,7 +313,8 @@ begin
v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
else
v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0);
v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
end if;
else
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index bc766c0ba825314d27c2048578e80d0c06edbc92..f564256058f940c55fc1dcc01f35b815af2f4a56 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -46,11 +46,15 @@ use io_ddr_lib.all;
entity ddrctrl is
generic (
- g_tech_ddr : t_c_tech_ddr; -- type of memory
- g_sim_model : boolean := true; -- determens if this is a simulation
+ -- type of memory
+ g_tech_ddr : t_c_tech_ddr;
+ -- determens if this is a simulation
+ g_sim_model : boolean := true;
g_technology : natural := c_tech_select_default;
- g_nof_streams : natural := 12; -- number of input streams
- g_data_w : natural := 14; -- data with of input data vectors
+ -- number of input streams
+ g_nof_streams : natural := 12;
+ -- data with of input data vectors
+ g_data_w : natural := 14;
g_stop_percentage : natural := 50;
g_block_size : natural := 1024
);
@@ -61,7 +65,8 @@ entity ddrctrl is
ctlr_ref_rst : in std_logic;
mm_clk : in std_logic := '0';
mm_rst : in std_logic := '0';
- in_sosi_arr : in t_dp_sosi_arr; -- input data
+ -- input data
+ in_sosi_arr : in t_dp_sosi_arr;
stop_in : in std_logic := '0';
out_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
@@ -89,16 +94,22 @@ end ddrctrl;
architecture str of ddrctrl is
-- constant for readability
- constant c_io_ddr_data_w : natural := func_tech_ddr_ctlr_data_w(g_tech_ddr); -- 576
- constant c_wr_fifo_depth : natural := 256; -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
- constant c_rd_fifo_depth : natural := 256; -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ -- 576
+ constant c_io_ddr_data_w : natural := func_tech_ddr_ctlr_data_w(g_tech_ddr);
+ -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ constant c_wr_fifo_depth : natural := 256;
+ -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ constant c_rd_fifo_depth : natural := 256;
constant c_wr_fifo_uw_w : natural := ceil_log2(c_wr_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr) / c_io_ddr_data_w));
constant c_rd_fifo_uw_w : natural := ceil_log2(c_rd_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr) / c_io_ddr_data_w));
constant c_burstsize : natural := g_tech_ddr.maxburstsize;
- constant c_adr_w : natural := func_tech_ddr_ctlr_address_w(g_tech_ddr); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
- constant c_max_adr : natural := 2**(c_adr_w) - 1; -- the maximal address that is possible within the vector length of the address
- constant c_adr_per_b : natural := ((g_block_size * g_nof_streams * g_data_w) / c_io_ddr_data_w) + 1; -- rounding error removes the amount of extra addresses.
+ -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
+ constant c_adr_w : natural := func_tech_ddr_ctlr_address_w(g_tech_ddr);
+ -- the maximal address that is possible within the vector length of the address
+ constant c_max_adr : natural := 2**(c_adr_w) - 1;
+ -- rounding error removes the amount of extra addresses.
+ constant c_adr_per_b : natural := ((g_block_size * g_nof_streams * g_data_w) / c_io_ddr_data_w) + 1;
constant c_bim : natural := natural(floor(real(c_max_adr) / real(c_adr_per_b)));
signal s_adr_per_b : natural := c_adr_per_b;
@@ -109,7 +120,8 @@ architecture str of ddrctrl is
signal s_nof_adr : natural := c_nof_adr;
-- the amount of overflow after one block is written
- constant c_of_pb : natural := (g_block_size * g_nof_streams * g_data_w) - (((g_block_size * g_nof_streams * g_data_w) / c_io_ddr_data_w) * c_io_ddr_data_w); -- amount of overflow after one block is written to memory
+ -- amount of overflow after one block is written to memory
+ constant c_of_pb : natural := (g_block_size * g_nof_streams * g_data_w) - (((g_block_size * g_nof_streams * g_data_w) / c_io_ddr_data_w) * c_io_ddr_data_w);
constant c_aof_full_burst : natural := c_nof_adr / c_burstsize;
constant c_last_burstsize : natural := c_nof_adr - (c_aof_full_burst * c_burstsize);
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 69b4c10a71d9cde40702755a4709d38f7f538417..268d304aeb5d046e0ee7bdef7bafb59d01c16639 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -39,19 +39,32 @@ entity ddrctrl_controller is
generic (
g_tech_ddr : t_c_tech_ddr;
g_stop_percentage : natural := 50;
- g_nof_streams : natural; -- 12
- g_out_data_w : natural; -- 14
- g_wr_data_w : natural; -- 168
- g_rd_fifo_depth : natural; -- 256
- g_rd_data_w : natural; -- 256
- g_block_size : natural; -- 1024
- g_wr_fifo_uw_w : natural; -- 8
- g_rd_fifo_uw_w : natural; -- 8
- g_max_adr : natural; -- 16128
- g_burstsize : natural; -- 64
- g_last_burstsize : natural; -- 18
- g_adr_per_b : natural; -- 299
- g_bim : natural -- 54
+ -- 12
+ g_nof_streams : natural;
+ -- 14
+ g_out_data_w : natural;
+ -- 168
+ g_wr_data_w : natural;
+ -- 256
+ g_rd_fifo_depth : natural;
+ -- 256
+ g_rd_data_w : natural;
+ -- 1024
+ g_block_size : natural;
+ -- 8
+ g_wr_fifo_uw_w : natural;
+ -- 8
+ g_rd_fifo_uw_w : natural;
+ -- 16128
+ g_max_adr : natural;
+ -- 64
+ g_burstsize : natural;
+ -- 18
+ g_last_burstsize : natural;
+ -- 299
+ g_adr_per_b : natural;
+ -- 54
+ g_bim : natural
);
port (
clk : in std_logic;
@@ -86,17 +99,22 @@ entity ddrctrl_controller is
end ddrctrl_controller;
architecture rtl of ddrctrl_controller is
- constant c_bitshift_w : natural := ceil_log2(g_burstsize); -- bitshift to make sure there is only a burst start at a interval of c_burstsize.
- constant c_adr_w : natural := func_tech_ddr_ctlr_address_w( g_tech_ddr ); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
- constant c_pof_ma : natural := ((natural((real(g_max_adr) * (100.0 - real(g_stop_percentage))) / 100.0) / g_adr_per_b) * g_adr_per_b); -- percentage of max address.
+ -- bitshift to make sure there is only a burst start at a interval of c_burstsize.
+ constant c_bitshift_w : natural := ceil_log2(g_burstsize);
+ -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
+ constant c_adr_w : natural := func_tech_ddr_ctlr_address_w( g_tech_ddr );
+ -- percentage of max address.
+ constant c_pof_ma : natural := ((natural((real(g_max_adr) * (100.0 - real(g_stop_percentage))) / 100.0) / g_adr_per_b) * g_adr_per_b);
constant c_zeros : std_logic_vector(c_bitshift_w - 1 downto 0) := (others => '0');
constant c_stop_adr_zeros : std_logic_vector(c_adr_w - 1 downto 0) := (others => '0');
-- constant for reading
- constant c_rd_data_w : natural := g_nof_streams * g_out_data_w; -- 168
- constant c_io_ddr_data_w : natural := func_tech_ddr_ctlr_data_w(g_tech_ddr); -- 576
+ -- 168
+ constant c_rd_data_w : natural := g_nof_streams * g_out_data_w;
+ -- 576
+ constant c_io_ddr_data_w : natural := func_tech_ddr_ctlr_data_w(g_tech_ddr);
-- constant for debugging
constant c_always_one_ndx : natural := 0;
@@ -252,7 +270,8 @@ begin
v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
else
v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0);
v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
end if;
else
@@ -311,7 +330,8 @@ begin
v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
else
v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0);
v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
end if;
else
@@ -349,7 +369,8 @@ begin
v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
else
v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0);
v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
end if;
else
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
index a0f0eea2bd54923eddc34d38aa1508fc0997f093..371dd8a4386434b3b3c18a9fe90cb5d247a7204e 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
@@ -43,9 +43,12 @@ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_input is
generic (
- g_tech_ddr : t_c_tech_ddr; -- type of memory
- g_nof_streams : natural := 12; -- number of input streams
- g_data_w : natural := 14; -- data with of input data vectors
+ -- type of memory
+ g_tech_ddr : t_c_tech_ddr;
+ -- number of input streams
+ g_nof_streams : natural := 12;
+ -- data with of input data vectors
+ g_data_w : natural := 14;
g_max_adr : natural;
g_bim : natural;
g_of_pb : natural;
@@ -55,9 +58,11 @@ entity ddrctrl_input is
clk : in std_logic := '0';
rst : in std_logic;
rst_ddrctrl_input_ac : in std_logic;
- in_sosi_arr : in t_dp_sosi_arr; -- input data
+ -- input data
+ in_sosi_arr : in t_dp_sosi_arr;
in_stop : in std_logic;
- out_sosi : out t_dp_sosi; -- output data
+ -- output data
+ out_sosi : out t_dp_sosi;
out_adr : out natural;
out_bsn_adr : out natural;
out_data_stopped : out std_logic
@@ -66,7 +71,8 @@ end ddrctrl_input;
architecture str of ddrctrl_input is
-- constant for readability
- constant c_out_data_w : natural := g_nof_streams * g_data_w; -- the input data with for ddrctrl_repack
+ -- the input data with for ddrctrl_repack
+ constant c_out_data_w : natural := g_nof_streams * g_data_w;
-- signals for connecting the components
signal sosi_p_rp : t_dp_sosi := c_dp_sosi_init;
@@ -80,19 +86,25 @@ begin
-- makes one data vector out of all the data from the t_dp_sosi_arr
u_ddrctrl_input_pack : entity work.ddrctrl_input_pack
generic map(
- g_nof_streams => g_nof_streams, -- number of input streams
- g_data_w => g_data_w -- data with of input data vectors
+ -- number of input streams
+ g_nof_streams => g_nof_streams,
+ -- data with of input data vectors
+ g_data_w => g_data_w
)
port map(
- in_sosi_arr => in_sosi_arr, -- input data
- out_sosi => sosi_p_rp -- output data
+ -- input data
+ in_sosi_arr => in_sosi_arr,
+ -- output data
+ out_sosi => sosi_p_rp
);
-- resizes the input data vector so that the output data vector can be stored into the ddr memory
u_ddrctrl_input_repack : entity work.ddrctrl_input_repack
generic map(
- g_tech_ddr => g_tech_ddr, -- type of memory
- g_in_data_w => c_out_data_w, -- the input data with
+ -- type of memory
+ g_tech_ddr => g_tech_ddr,
+ -- the input data with
+ g_in_data_w => c_out_data_w,
g_bim => g_bim,
g_of_pb => g_of_pb,
g_block_size => g_block_size
@@ -100,24 +112,29 @@ begin
port map(
clk => clk,
rst => rst,
- in_sosi => sosi_p_rp, -- input data
+ -- input data
+ in_sosi => sosi_p_rp,
in_stop => in_stop,
- out_sosi => sosi_rp_ac, -- output data
+ -- output data
+ out_sosi => sosi_rp_ac,
out_data_stopped => data_stopped_rp_ac
);
-- creates address by counting input valids
u_ddrctrl_input_address_counter : entity work.ddrctrl_input_address_counter
generic map(
- g_tech_ddr => g_tech_ddr, -- type of memory
+ -- type of memory
+ g_tech_ddr => g_tech_ddr,
g_max_adr => g_max_adr
)
port map(
clk => clk,
rst => rst_ddrctrl_input_ac,
- in_sosi => sosi_rp_ac, -- input data
+ -- input data
+ in_sosi => sosi_rp_ac,
in_data_stopped => data_stopped_rp_ac,
- out_sosi => out_sosi, -- output data
+ -- output data
+ out_sosi => out_sosi,
out_adr => adr,
out_bsn_adr => out_bsn_adr,
out_data_stopped => out_data_stopped
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
index d5e7bd5d7ff86b33d07230934432be13e0621f10..614e6cc0f7375eebb03d35f3c303e8dd9dca5eb4 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
@@ -40,15 +40,18 @@ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_input_address_counter is
generic (
- g_tech_ddr : t_c_tech_ddr; -- type of memory
+ -- type of memory
+ g_tech_ddr : t_c_tech_ddr;
g_max_adr : natural
);
port (
clk : in std_logic;
rst : in std_logic;
- in_sosi : in t_dp_sosi; -- input data
+ -- input data
+ in_sosi : in t_dp_sosi;
in_data_stopped : in std_logic;
- out_sosi : out t_dp_sosi := c_dp_sosi_init; -- output data
+ -- output data
+ out_sosi : out t_dp_sosi := c_dp_sosi_init;
out_adr : out natural;
out_bsn_adr : out natural;
out_data_stopped : out std_logic
@@ -57,7 +60,8 @@ end ddrctrl_input_address_counter;
architecture rtl of ddrctrl_input_address_counter is
-- constants for readability
- constant c_data_w : natural := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the with of the input data and output data, 576
+ -- the with of the input data and output data, 576
+ constant c_data_w : natural := func_tech_ddr_ctlr_data_w( g_tech_ddr );
-- type for statemachine
type t_state is (RESET, COUNTING, MAX, IDLE);
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
index 4895077bd3f1da1a0570e9b981f67a2e1f635842..89525086d1a595ced840b21555ce30325078d745 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
@@ -33,12 +33,16 @@ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_input_pack is
generic (
- g_nof_streams : positive := 12; -- number of input streams
- g_data_w : natural := 14 -- data with of input data vectors
+ -- number of input streams
+ g_nof_streams : positive := 12;
+ -- data with of input data vectors
+ g_data_w : natural := 14
);
port (
- in_sosi_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- input data
- out_sosi : out t_dp_sosi := c_dp_sosi_init -- output data
+ -- input data
+ in_sosi_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ -- output data
+ out_sosi : out t_dp_sosi := c_dp_sosi_init
);
end ddrctrl_input_pack;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
index 2c232e370e4a19cdca0067674e2991ebbd649fbd..eb1195f7461b3e7264cb7cf5e41a9da8eff736bf 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
@@ -36,8 +36,10 @@ use tech_ddr_lib.tech_ddr_pkg.all;
entity ddrctrl_input_repack is
generic (
- g_tech_ddr : t_c_tech_ddr; -- type of memory
- g_in_data_w : natural := 168; -- the input data with
+ -- type of memory
+ g_tech_ddr : t_c_tech_ddr;
+ -- the input data with
+ g_in_data_w : natural := 168;
g_bim : natural;
g_of_pb : natural;
g_block_size : natural
@@ -45,9 +47,11 @@ entity ddrctrl_input_repack is
port (
clk : in std_logic;
rst : in std_logic;
- in_sosi : in t_dp_sosi; -- input data
+ -- input data
+ in_sosi : in t_dp_sosi;
in_stop : in std_logic := '0';
- out_sosi : out t_dp_sosi := c_dp_sosi_init; -- output data
+ -- output data
+ out_sosi : out t_dp_sosi := c_dp_sosi_init;
out_bsn_wr : out std_logic := '0';
out_data_stopped : out std_logic := '0'
);
@@ -55,24 +59,32 @@ end ddrctrl_input_repack;
architecture rtl of ddrctrl_input_repack is
-- constant for readability
- constant c_out_data_w : natural := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the output data with, 576
- constant k_c_v_w : natural := c_out_data_w * 2; -- the c_v data with, 2*576=1152
+ -- the output data with, 576
+ constant c_out_data_w : natural := func_tech_ddr_ctlr_data_w( g_tech_ddr );
+ -- the c_v data with, 2*576=1152
+ constant k_c_v_w : natural := c_out_data_w * 2;
-- type for statemachine
type t_state is (OVERFLOW_OUTPUT, FILL_VECTOR, FIRST_OUTPUT, RESET, STOP, BSN);
-- record for readability
type t_reg is record
- state : t_state; -- the state the process is currently in;
- c_v : std_logic_vector(k_c_v_w - 1 downto 0); -- the vector that stores the input data until the data is put into the output data vector
- c_v_count : natural; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
+ -- the state the process is currently in;
+ state : t_state;
+ -- the vector that stores the input data until the data is put into the output data vector
+ c_v : std_logic_vector(k_c_v_w - 1 downto 0);
+ -- the amount of times the c_v vector received data from the input since the last time it was filled completely
+ c_v_count : natural;
q_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
q_sop : std_logic;
s_input_cnt : natural;
out_of : natural;
- out_data_count : std_logic; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
- out_sosi : t_dp_sosi; -- this is the sosi stream that contains the data
- out_data_stopped : std_logic; -- this signal is '1' when there is no more data comming form ddrctrl_input_pack
+ -- the amount of times the output data vector has been filled since the last time c_v was filled completely
+ out_data_count : std_logic;
+ -- this is the sosi stream that contains the data
+ out_sosi : t_dp_sosi;
+ -- this signal is '1' when there is no more data comming form ddrctrl_input_pack
+ out_data_stopped : std_logic;
end record;
constant c_t_reg_init : t_reg := (RESET, (others => '0'), 0, (others => '0'), '0', 0, 0, '0', c_dp_sosi_init, '0');
@@ -91,35 +103,53 @@ begin
v := q_reg;
case q_reg.state is
- when FILL_VECTOR => -- if the input data doesn't exceeds the output data vector width
- v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
- v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
- v.out_sosi.valid := '0'; -- out_sosi.valid 0
+ -- if the input data doesn't exceeds the output data vector width
+ when FILL_VECTOR =>
+ -- fill c_v
+ v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0);
+ -- increase the counter of c_v with 1
+ v.c_v_count := q_reg.c_v_count + 1;
+ -- out_sosi.valid 0
+ v.out_sosi.valid := '0';
v.s_input_cnt := q_reg.s_input_cnt + 1;
v.out_sosi.sop := '0';
v.out_sosi.eop := '0';
v.out_data_stopped := '0';
- when FIRST_OUTPUT => -- if the input data exceeds output data vector width but not the c_v width
- v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
- v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
- v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(c_out_data_w - 1 downto 0); -- fill out_sosi.data with 1st part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- v.out_data_count := '1'; -- increase the counter of out_sosi.data with 1
+ -- if the input data exceeds output data vector width but not the c_v width
+ when FIRST_OUTPUT =>
+ -- fill c_v
+ v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0);
+ -- increase the counter of c_v with 1
+ v.c_v_count := q_reg.c_v_count + 1;
+ -- fill out_sosi.data with 1st part of c_v
+ v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(c_out_data_w - 1 downto 0);
+ -- out_sosi.valid 1
+ v.out_sosi.valid := '1';
+ -- increase the counter of out_sosi.data with 1
+ v.out_data_count := '1';
v.s_input_cnt := q_reg.s_input_cnt + 1;
v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := q_reg.q_bsn(c_dp_stream_bsn_w - 1 downto 0);
v.out_sosi.sop := q_reg.q_sop;
v.out_sosi.eop := '0';
v.out_data_stopped := '0';
- when OVERFLOW_OUTPUT => -- if the input data exceeds the output data vector width and the c_v width
- v.out_of := q_reg.out_of + (g_in_data_w * (q_reg.c_v_count + 1)) - (c_out_data_w * 2); -- check how much overflow there is and safe it in out_of
- v.c_v(k_c_v_w - 1 downto k_c_v_w - (g_in_data_w - v.out_of)) := in_sosi.data(g_in_data_w - v.out_of - 1 downto 0); -- fill the rest of c_v untill the end
- v.c_v(v.out_of - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto g_in_data_w - v.out_of); -- fill the start of c_v untill the out_of
- v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(k_c_v_w - 1 downto c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- v.c_v_count := 0; -- reset counter
- v.out_data_count := '0'; -- reset counter
+ -- if the input data exceeds the output data vector width and the c_v width
+ when OVERFLOW_OUTPUT =>
+ -- check how much overflow there is and safe it in out_of
+ v.out_of := q_reg.out_of + (g_in_data_w * (q_reg.c_v_count + 1)) - (c_out_data_w * 2);
+ -- fill the rest of c_v untill the end
+ v.c_v(k_c_v_w - 1 downto k_c_v_w - (g_in_data_w - v.out_of)) := in_sosi.data(g_in_data_w - v.out_of - 1 downto 0);
+ -- fill the start of c_v untill the out_of
+ v.c_v(v.out_of - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto g_in_data_w - v.out_of);
+ -- fill out_sosi.data with 2nd part of c_v
+ v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(k_c_v_w - 1 downto c_out_data_w);
+ -- out_sosi.valid 1
+ v.out_sosi.valid := '1';
+ -- reset counter
+ v.c_v_count := 0;
+ -- reset counter
+ v.out_data_count := '0';
v.s_input_cnt := q_reg.s_input_cnt + 1;
v.q_sop := '0';
v.out_sosi.sop := '0';
@@ -131,18 +161,26 @@ begin
v.c_v(k_c_v_w - 1 downto ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of)) := (others => '0');
v.out_of := 0;
if ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of < c_out_data_w * 1) then
- v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(c_out_data_w - 1 downto 0); -- fill out_sosi.data with 1st part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ -- fill out_sosi.data with 1st part of c_v
+ v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(c_out_data_w - 1 downto 0);
+ -- out_sosi.valid 1
+ v.out_sosi.valid := '1';
else
- v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(k_c_v_w - 1 downto c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ -- fill out_sosi.data with 2nd part of c_v
+ v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(k_c_v_w - 1 downto c_out_data_w);
+ -- out_sosi.valid 1
+ v.out_sosi.valid := '1';
end if;
-- BSN_INPUT
- v.q_bsn := in_sosi.bsn; -- a bsn number is saved when the bsn changes
- v.q_sop := '1'; -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
- v.c_v(g_in_data_w - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
- v.c_v_count := 1; -- increase the counter of c_v with 1
+ -- a bsn number is saved when the bsn changes
+ v.q_bsn := in_sosi.bsn;
+ -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
+ v.q_sop := '1';
+ -- fill c_v
+ v.c_v(g_in_data_w - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto 0);
+ -- increase the counter of c_v with 1
+ v.c_v_count := 1;
v.out_data_count := '0';
v.out_sosi.eop := '1';
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
index 69fee61b011b63c1a46bd14c0fb2995ff764d283..1c428a730b28b2a3faeadfce22f3b4a02871c9c6 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
@@ -41,28 +41,35 @@ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_output is
generic (
g_technology : natural;
- g_tech_ddr : t_c_tech_ddr; -- type of memory
- g_sim_model : boolean := true; -- determens if this is a simulation
+ -- type of memory
+ g_tech_ddr : t_c_tech_ddr;
+ -- determens if this is a simulation
+ g_sim_model : boolean := true;
g_in_data_w : natural := 576;
- g_nof_streams : natural := 12; -- number of input streams
- g_data_w : natural := 14; -- data with of input data vectors
+ -- number of input streams
+ g_nof_streams : natural := 12;
+ -- data with of input data vectors
+ g_data_w : natural := 14;
g_block_size : natural := 1024;
g_bim : natural := 54
);
port (
clk : in std_logic := '0';
rst : in std_logic;
- in_sosi : in t_dp_sosi := c_dp_sosi_init; -- input data
+ -- input data
+ in_sosi : in t_dp_sosi := c_dp_sosi_init;
in_bsn : in std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
out_siso : in t_dp_siso;
- out_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_init); -- output data
+ -- output data
+ out_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_init);
out_ready : out std_logic
);
end ddrctrl_output;
architecture str of ddrctrl_output is
-- constant for readability
- constant c_out_data_w : natural := g_nof_streams * g_data_w; -- the input data width for ddrctrl_repack 168
+ -- the input data width for ddrctrl_repack 168
+ constant c_out_data_w : natural := g_nof_streams * g_data_w;
-- fifo
constant c_fifo_size : natural := 2;
@@ -91,10 +98,12 @@ begin
port map(
clk => clk,
rst => rst,
- in_sosi => in_sosi, -- input data
+ -- input data
+ in_sosi => in_sosi,
in_bsn => in_bsn,
out_siso => out_siso,
- out_sosi => out_sosi, -- output data
+ -- output data
+ out_sosi => out_sosi,
out_ready => out_ready,
state_off => unpack_state_off
);
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 999afc3545127e74126d91f3c72c52bc67538ed6..36ddf65e935585eaa9992dd36197a563530946e2 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -36,19 +36,25 @@ use technology_lib.technology_select_pkg.all;
entity tb_ddrctrl is
generic (
- g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- type of memory
- g_nof_streams : positive := 12; -- number of input streams
- g_data_w : natural := 14; -- data with of input data vectors
+ -- type of memory
+ g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m;
+ -- number of input streams
+ g_nof_streams : positive := 12;
+ -- data with of input data vectors
+ g_data_w : natural := 14;
g_technology : natural := c_tech_select_default;
g_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
g_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
- g_stop_percentage : natural := 80; -- percentage there needs to be already written in the ddr memory when a stop gets triggered
- g_block_size : natural := 1024 -- amount of samples that goes into one bsn
+ -- percentage there needs to be already written in the ddr memory when a stop gets triggered
+ g_stop_percentage : natural := 80;
+ -- amount of samples that goes into one bsn
+ g_block_size : natural := 1024
);
end tb_ddrctrl;
architecture tb of tb_ddrctrl is
- constant c_sim_model : boolean := true; -- determens if this is a simulation
+ -- determens if this is a simulation
+ constant c_sim_model : boolean := true;
-- Select DDR3 or DDR4 dependent on the technology and sim model
constant c_mem_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_technology, g_tech_ddr3, g_tech_ddr4);
@@ -56,29 +62,41 @@ architecture tb of tb_ddrctrl is
constant c_tech_ddr : t_c_tech_ddr := func_tech_sel_ddr(c_sim_model, c_sim_ddr, c_mem_ddr);
-- constants for readability
- constant c_ctrl_data_w : natural := func_tech_ddr_ctlr_data_w(c_tech_ddr); -- 576
- constant c_in_data_w : natural := g_nof_streams * g_data_w; -- output data with, 168
+ -- 576
+ constant c_ctrl_data_w : natural := func_tech_ddr_ctlr_data_w(c_tech_ddr);
+ -- output data with, 168
+ constant c_in_data_w : natural := g_nof_streams * g_data_w;
-- constants for testbench
- constant c_clk_freq : natural := 200; -- clock frequency in MHz
- constant c_clk_period : time := (10**6 / c_clk_freq) * 1 ps; -- clock priod, 5 ns
- constant c_mm_clk_freq : natural := 100; -- mm clock frequency in MHz
- constant c_mm_clk_period : time := (10**6 / c_mm_clk_freq) * 1 ps; -- mm clock period, 10 ns
+ -- clock frequency in MHz
+ constant c_clk_freq : natural := 200;
+ -- clock priod, 5 ns
+ constant c_clk_period : time := (10**6 / c_clk_freq) * 1 ps;
+ -- mm clock frequency in MHz
+ constant c_mm_clk_freq : natural := 100;
+ -- mm clock period, 10 ns
+ constant c_mm_clk_period : time := (10**6 / c_mm_clk_freq) * 1 ps;
constant c_stop_value_for_j : natural := 14180;
-- constant for checking output data
- constant c_adr_w : natural := func_tech_ddr_ctlr_address_w(c_tech_ddr); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
- constant c_max_adr : natural := 2**(c_adr_w) - 1; -- the maximal address that is possible within the vector length of the address
+ -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
+ constant c_adr_w : natural := func_tech_ddr_ctlr_address_w(c_tech_ddr);
+ -- the maximal address that is possible within the vector length of the address
+ constant c_max_adr : natural := 2**(c_adr_w) - 1;
constant c_output_stop_adr : natural := (c_max_adr + 1) - ((((c_max_adr + 1) / 64) * g_stop_percentage / 100) * 64);
constant c_output_ds : natural := 144;
- constant c_bim : natural := (c_max_adr * c_ctrl_data_w) / (g_block_size * g_nof_streams * g_data_w); -- the amount of whole blocks that fit in memory.
- constant c_adr_per_b : natural := ((g_block_size * g_nof_streams * g_data_w) / c_ctrl_data_w) + 1; -- rounding error removes the amount of extra addresses.
+ -- the amount of whole blocks that fit in memory.
+ constant c_bim : natural := (c_max_adr * c_ctrl_data_w) / (g_block_size * g_nof_streams * g_data_w);
+ -- rounding error removes the amount of extra addresses.
+ constant c_adr_per_b : natural := ((g_block_size * g_nof_streams * g_data_w) / c_ctrl_data_w) + 1;
-- the amount of addresses used
- constant c_nof_adr : natural := (c_bim * g_block_size * g_nof_streams * g_data_w) / c_ctrl_data_w; -- rounding error removes the amount of extra addresses.
+ -- rounding error removes the amount of extra addresses.
+ constant c_nof_adr : natural := (c_bim * g_block_size * g_nof_streams * g_data_w) / c_ctrl_data_w;
-- the amount of overflow after one block is written
- constant c_of_pb : natural := (g_block_size * g_nof_streams * g_data_w) - (((g_block_size * g_nof_streams * g_data_w) / c_ctrl_data_w) * c_ctrl_data_w); -- amount of overflow after one block is written to memory
+ -- amount of overflow after one block is written to memory
+ constant c_of_pb : natural := (g_block_size * g_nof_streams * g_data_w) - (((g_block_size * g_nof_streams * g_data_w) / c_ctrl_data_w) * c_ctrl_data_w);
function c_of_after_nof_adr_init return natural is
variable temp : natural := 0;
@@ -99,7 +117,8 @@ architecture tb of tb_ddrctrl is
-- function for making total data vector
function c_total_vector_init return std_logic_vector is
variable temp : std_logic_vector(g_data_w * g_nof_streams * c_bim * g_block_size-1 downto 0);
- variable conv : std_logic_vector(32 - 1 downto 0) := (others => '0'); -- removes a warning
+ -- removes a warning
+ variable conv : std_logic_vector(32 - 1 downto 0) := (others => '0');
begin
for I in 0 to c_bim * g_block_size-1 loop
conv := TO_UVEC(I, 32);
@@ -111,7 +130,8 @@ architecture tb of tb_ddrctrl is
end function c_total_vector_init;
-- constant for running the test
- constant c_total_vector : std_logic_vector(g_data_w * g_nof_streams * c_bim * g_block_size-1 downto 0) := c_total_vector_init; -- vector which contains all input data vectors to make it easy to fill ctr_vector
+ -- vector which contains all input data vectors to make it easy to fill ctr_vector
+ constant c_total_vector : std_logic_vector(g_data_w * g_nof_streams * c_bim * g_block_size-1 downto 0) := c_total_vector_init;
signal c_total_vector_length : natural := c_total_vector'length;
@@ -124,17 +144,21 @@ architecture tb of tb_ddrctrl is
signal rst : std_logic := '0';
signal mm_clk : std_logic := '0';
signal mm_rst : std_logic := '0';
- signal in_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_init); -- input data signal for ddrctrl_pack.vhd
+ -- input data signal for ddrctrl_pack.vhd
+ signal in_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_init);
signal stop_in : std_logic := '0';
signal out_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_init);
signal out_siso : t_dp_siso;
-- testbench signal
- signal tb_end : std_logic := '0'; -- signal to turn the testbench off
+ -- signal to turn the testbench off
+ signal tb_end : std_logic := '0';
-- signals for running test
- signal in_data_cnt : natural := 0; -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd
- signal test_running : std_logic := '0'; -- signal to tell wheter the testing has started
+ -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd
+ signal in_data_cnt : natural := 0;
+ -- signal to tell wheter the testing has started
+ signal test_running : std_logic := '0';
signal bsn_cnt : natural := g_block_size-1;
-- signals for checking the output data
@@ -160,7 +184,8 @@ begin
out_siso.ready <= '1';
tb_end <= '0';
in_sosi_arr(0).valid <= '0';
- wait until rising_edge(clk); -- align to rising edge
+ -- align to rising edge
+ wait until rising_edge(clk);
wait for c_clk_period * 4;
rst <= '1';
mm_rst <= '1';
@@ -232,7 +257,8 @@ begin
assert false report "Test: OK" severity FAILURE;
end process;
- p_checking_output_data : process -- first do tickets L2SDP-708 and L2SDP-707 before finsishing this is worth time
+ -- first do tickets L2SDP-708 and L2SDP-707 before finsishing this is worth time
+ p_checking_output_data : process
begin
wait until rising_edge(clk);
if out_sosi_arr(0).valid = '1' then
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index 107e1a05883b173a0ea9f423426ca1eb60511687..4f90c8bcacc4120779e441a045e65c60d61869fc 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -39,7 +39,8 @@ entity node_sdp_adc_input_and_timing is
generic (
g_no_jesd : boolean := false;
g_buf_nof_data : natural := c_sdp_V_si_db;
- g_bsn_nof_clk_per_sync : natural := c_sdp_N_clk_per_sync; -- Default 200M, overide for short simulation
+ -- Default 200M, overide for short simulation
+ g_bsn_nof_clk_per_sync : natural := c_sdp_N_clk_per_sync;
g_sim : boolean := false
);
port (
@@ -103,28 +104,37 @@ entity node_sdp_adc_input_and_timing is
-- Streaming data output
out_sosi_arr : out t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0);
- dp_bsn_source_restart : out std_logic; -- for dp_sync_recover in WPFB
- dp_bsn_source_new_interval : out std_logic; -- for SST and BST statistics offload, XST uses new_interval based on xst_processing_enable
- dp_bsn_source_nof_clk_per_sync : out std_logic_vector(c_word_w - 1 downto 0) -- for RSN source in transient buffer
+ -- for dp_sync_recover in WPFB
+ dp_bsn_source_restart : out std_logic;
+ -- for SST and BST statistics offload, XST uses new_interval based on xst_processing_enable
+ dp_bsn_source_new_interval : out std_logic;
+ -- for RSN source in transient buffer
+ dp_bsn_source_nof_clk_per_sync : out std_logic_vector(c_word_w - 1 downto 0)
);
end node_sdp_adc_input_and_timing;
architecture str of node_sdp_adc_input_and_timing is
-- Waveform Generator
constant c_wg_buf_directory : string := "data/";
- constant c_wg_buf_dat_w : natural := 18; -- default value of WG that fits 14 bits of ADC data
- constant c_wg_buf_addr_w : natural := 10; -- default value of WG for 1024 samples;
+ -- default value of WG that fits 14 bits of ADC data
+ constant c_wg_buf_dat_w : natural := 18;
+ -- default value of WG for 1024 samples;
+ constant c_wg_buf_addr_w : natural := 10;
signal trigger_wg : std_logic;
-- Frame parameters
- constant c_bs_sync_timeout : natural := g_bsn_nof_clk_per_sync + g_bsn_nof_clk_per_sync / 10; -- +10% margin
- constant c_bs_bsn_w : natural := 64; -- > 51;
+ -- +10% margin
+ constant c_bs_sync_timeout : natural := g_bsn_nof_clk_per_sync + g_bsn_nof_clk_per_sync / 10;
+ -- > 51;
+ constant c_bs_bsn_w : natural := 64;
constant c_bs_aux_w : natural := 2;
- constant c_bs_block_size : natural := c_sdp_N_fft; -- =1024;
+ -- =1024;
+ constant c_bs_block_size : natural := c_sdp_N_fft;
constant c_dp_fifo_dc_size : natural := 64;
-- JESD signals
- signal rx_clk : std_logic; -- formerly jesd204b_frame_clk
+ -- formerly jesd204b_frame_clk
+ signal rx_clk : std_logic;
signal rx_rst : std_logic;
signal rx_sysref : std_logic;
@@ -188,7 +198,8 @@ begin
u_jesd204b: entity tech_jesd204b_lib.tech_jesd204b
generic map(
- g_sim => false, -- do not use g_sim, because JESD204B IP does support mm_clk in sim
+ -- do not use g_sim, because JESD204B IP does support mm_clk in sim
+ g_sim => false,
g_nof_streams => c_sdp_S_pn,
g_nof_sync_n => c_sdp_N_sync_jesd,
g_jesd_freq => c_sdp_jesd204b_freq
@@ -307,7 +318,8 @@ begin
dp_rst => rx_rst,
dp_clk => rx_clk,
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ -- only uses eop (= block sync), bsn[]
+ snk_in => bs_sosi,
trigger_out => trigger_wg
);
@@ -392,7 +404,8 @@ begin
---------------------------------------------------------------------------------------
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
generic map (
- g_nof_streams => 1, -- They're all the same
+ -- They're all the same
+ g_nof_streams => 1,
g_sync_timeout => c_bs_sync_timeout,
g_bsn_w => c_bs_bsn_w,
g_log_first_bsn => false
@@ -418,7 +431,8 @@ begin
g_cross_clock_domain => true,
g_nof_streams => c_sdp_S_pn,
g_symbol_w => c_sdp_W_adc,
- g_nof_symbols_per_data => 1, -- Wideband factor is 1
+ -- Wideband factor is 1
+ g_nof_symbols_per_data => 1,
g_nof_accumulations => g_bsn_nof_clk_per_sync
)
port map (
@@ -426,9 +440,11 @@ begin
mm_rst => mm_rst,
mm_clk => mm_clk,
- reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
+ -- read only access to the signal path data mean sum and power sum registers
+ reg_mosi => reg_aduh_monitor_mosi,
reg_miso => reg_aduh_monitor_miso,
- buf_mosi => c_mem_mosi_rst, -- Unused
+ -- Unused
+ buf_mosi => c_mem_mosi_rst,
buf_miso => OPEN,
-- Streaming clock domain
@@ -447,7 +463,8 @@ begin
g_nof_streams => c_sdp_S_pn,
g_data_w => c_sdp_W_adc,
g_buf_nof_data => g_buf_nof_data,
- g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ g_buf_use_sync => true
)
port map (
mm_rst => mm_rst,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
index a2ea28949b81de46b3caec0db64d887885664610..852a4ee4f38eb36f2108ae9193df7a44a0e60dc3 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
@@ -45,8 +45,10 @@ entity node_sdp_beamformer is
g_beamset_id : natural := 0;
g_scope_selected_beamlet : natural := 0;
-- Use no default raw width, to force instance to set it
- g_subband_raw_dat_w : natural; -- default: c_sdp_W_subband;
- g_subband_raw_fraction_w : natural -- default: 0
+ -- default: c_sdp_W_subband;
+ g_subband_raw_dat_w : natural;
+ -- default: 0
+ g_subband_raw_fraction_w : natural
);
port (
dp_clk : in std_logic;
@@ -100,7 +102,8 @@ entity node_sdp_beamformer is
bdo_ip_src_addr : in std_logic_vector(c_network_ip_addr_w - 1 downto 0);
bdo_udp_src_port : in std_logic_vector(c_network_udp_port_w - 1 downto 0);
- bdo_hdr_fields_out : out std_logic_vector(1023 downto 0); -- Needed by nw_10GbE for PING/ARP
+ -- Needed by nw_10GbE for PING/ARP
+ bdo_hdr_fields_out : out std_logic_vector(1023 downto 0);
-- beamlet statistics offload
stat_eth_src_mac : in std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
@@ -148,7 +151,8 @@ begin
---------------------------------------------------------------
u_reorder_col_wide : entity reorder_lib.reorder_col_wide
generic map (
- g_wb_factor => c_sdp_P_pfb, -- g_wb_factor is only used for number of parallel streams
+ -- g_wb_factor is only used for number of parallel streams
+ g_wb_factor => c_sdp_P_pfb,
g_dsp_data_w => g_subband_raw_dat_w,
g_nof_ch_in => c_sdp_N_sub * c_sdp_Q_fft,
g_nof_ch_sel => c_sdp_S_sub_bf * c_sdp_Q_fft,
@@ -334,15 +338,18 @@ begin
-- MM master multiplexer
---------------------------------------------------------------
-- Connect 2 mm_masters to the common_mem_mux output
- master_mosi_arr(0) <= ram_st_bst_mosi; -- MM access via QSYS MM bus
+ -- MM access via QSYS MM bus
+ master_mosi_arr(0) <= ram_st_bst_mosi;
ram_st_bst_miso <= master_miso_arr(0);
- master_mosi_arr(1) <= ram_st_offload_mosi; -- MM access by SST offload
+ -- MM access by SST offload
+ master_mosi_arr(1) <= ram_st_offload_mosi;
ram_st_offload_miso <= master_miso_arr(1);
u_mem_master_mux : entity mm_lib.mm_master_mux
generic map (
g_nof_masters => c_nof_masters,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ -- read latency of statistics RAM is 1
+ g_rd_latency_min => 1
)
port map (
mm_clk => mm_clk,
@@ -394,7 +401,8 @@ begin
gn_index => TO_UINT(gn_id),
ring_info => ring_info,
sdp_info => sdp_info,
- weighted_subbands_flag => '1' -- because BF uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
+ -- because BF uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
+ weighted_subbands_flag => '1'
);
---------------------------------------------------------------
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index fb263f5b4ccdd775cd50e95c9b7d44f38751bab2..3a5f2eb70516bc8dd0162294d5a893d3ac9fdd11 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -46,8 +46,10 @@ entity node_sdp_correlator is
g_sim_sdp : t_sdp_sim := c_sdp_sim;
g_P_sq : natural := c_sdp_P_sq;
-- Use no default raw width, to force instance to set it
- g_subband_raw_dat_w : natural; -- default: c_sdp_W_subband;
- g_subband_raw_fraction_w : natural -- default: 0
+ -- default: c_sdp_W_subband;
+ g_subband_raw_dat_w : natural;
+ -- default: 0
+ g_subband_raw_fraction_w : natural
);
port (
dp_clk : in std_logic;
@@ -95,7 +97,8 @@ end node_sdp_correlator;
architecture str of node_sdp_correlator is
constant c_nof_controllers : positive := 2;
constant c_block_size : natural := c_sdp_N_crosslets_max * c_sdp_S_pn;
- constant c_block_size_longwords : natural := ceil_div(c_block_size, 2); -- 32b -> 64b
+ -- 32b -> 64b
+ constant c_block_size_longwords : natural := ceil_div(c_block_size, 2);
constant c_data_w : natural := c_sdp_W_crosslet * c_nof_complex;
-- The size for 1 block is probably already enough as the number of blocks received
@@ -150,9 +153,11 @@ begin
g_complex => true,
g_representation => "SIGNED",
g_lsb_w => g_subband_raw_fraction_w,
- g_lsb_round => true, -- round subband fraction
+ -- round subband fraction
+ g_lsb_round => true,
g_lsb_round_clip => false,
- g_msb_clip => true, -- clip subband overflow
+ -- clip subband overflow
+ g_msb_clip => true,
g_msb_clip_symmetric => false,
g_pipeline_remove_lsb => 1,
g_pipeline_remove_msb => 1,
@@ -219,7 +224,8 @@ begin
g_in_nof_words => c_longword_w / c_data_w,
g_out_dat_w => c_longword_w,
g_out_nof_words => 1,
- g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
+ -- Needed for src_in.ready to snk_out.ready.
+ g_pipeline_ready => true
)
port map (
rst => dp_rst,
@@ -290,7 +296,8 @@ begin
g_in_nof_words => 1,
g_out_dat_w => c_data_w,
g_out_nof_words => c_longword_w / c_data_w,
- g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
+ -- Needed for src_in.ready to snk_out.ready.
+ g_pipeline_ready => true
)
port map (
rst => dp_rst,
@@ -309,7 +316,8 @@ begin
g_mode => 0,
g_nof_output => g_P_sq,
g_remove_channel_lo => false,
- g_sel_ctrl_invert => true -- TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ -- TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ g_sel_ctrl_invert => true
)
port map (
rst => dp_rst,
@@ -329,13 +337,16 @@ begin
-- for dp_bsn_align_v2
g_nof_streams => g_P_sq,
g_bsn_latency_max => 2,
- g_nof_aligners_max => 1, -- 1 for Access scheme 3.
+ -- 1 for Access scheme 3.
+ g_nof_aligners_max => 1,
g_block_size => c_block_size,
g_data_w => c_data_w,
g_use_mm_output => true,
- g_rd_latency => 1, -- Required for st_xst
+ -- Required for st_xst
+ g_rd_latency => 1,
-- for mms_dp_bsn_monitor_v2
- g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout_xsub, -- Using c_sdp_N_clk_sync_timeout_xsub as g_nof_clk_per_sync is used for BSN monitor timeout.
+ -- Using c_sdp_N_clk_sync_timeout_xsub as g_nof_clk_per_sync is used for BSN monitor timeout.
+ g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout_xsub,
g_nof_input_bsn_monitors => g_P_sq,
g_use_bsn_output_monitor => true
)
@@ -395,15 +406,18 @@ begin
-- MM controller multiplexer
---------------------------------------------------------------
-- Connect 2 mm_controllers to the common_mem_mux output
- controller_copi_arr(0) <= ram_st_xsq_copi; -- MM access via QSYS MM bus
+ -- MM access via QSYS MM bus
+ controller_copi_arr(0) <= ram_st_xsq_copi;
ram_st_xsq_cipo <= controller_cipo_arr(0);
- controller_copi_arr(1) <= ram_st_offload_copi; -- MM access by UDP offload
+ -- MM access by UDP offload
+ controller_copi_arr(1) <= ram_st_offload_copi;
ram_st_offload_cipo <= controller_cipo_arr(1);
u_mem_controller_mux : entity mm_lib.mm_master_mux
generic map (
g_nof_masters => c_nof_controllers,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ -- read latency of statistics RAM is 1
+ g_rd_latency_min => 1
)
port map (
mm_clk => mm_clk,
@@ -451,7 +465,8 @@ begin
g_statistics_type => "XST",
g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
g_P_sq => g_P_sq,
- g_crosslets_direction => 1, -- = lane direction
+ -- = lane direction
+ g_crosslets_direction => 1,
g_bsn_monitor_sync_timeout => c_sdp_N_clk_sync_timeout_xsub
)
port map (
@@ -486,9 +501,11 @@ begin
gn_index => TO_UINT(gn_id),
ring_info => ring_info,
sdp_info => sdp_info,
- weighted_subbands_flag => '1', -- because XSub uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
+ -- because XSub uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
+ weighted_subbands_flag => '1',
- nof_crosslets => nof_crosslets, -- from MM
+ -- from MM
+ nof_crosslets => nof_crosslets,
prev_crosslets_info_rec => prev_crosslets_info_rec
);
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index 691a5a916f2e60945d2288c84c4eaaf418767720..11ddd78d4a509499200ba8ded4f9b8f33eb76167 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -78,9 +78,12 @@ entity node_sdp_filterbank is
dp_bsn_source_restart : in std_logic;
dp_bsn_source_new_interval : in std_logic;
- in_sosi_arr : in t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0); -- c_sdp_W_adc bits
- fsub_quant_sosi_arr: out t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0); -- c_sdp_W_subband bits
- fsub_raw_sosi_arr : out t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0); -- c_sdp_W_subband + c_subband_raw_fraction_w bits
+ -- c_sdp_W_adc bits
+ in_sosi_arr : in t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0);
+ -- c_sdp_W_subband bits
+ fsub_quant_sosi_arr: out t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0);
+ -- c_sdp_W_subband + c_subband_raw_fraction_w bits
+ fsub_raw_sosi_arr : out t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0);
sst_udp_sosi : out t_dp_sosi;
sst_udp_siso : in t_dp_siso := c_dp_siso_rst;
@@ -129,7 +132,8 @@ architecture str of node_sdp_filterbank is
natural'image(c_sdp_W_sub_weight) & "b" &
natural'image(c_sdp_W_sub_weight_fraction) & "f_unit";
- constant c_nof_masters : positive := 2; -- for M&C MM access and for statistics offload MM access
+ -- for M&C MM access and for statistics offload MM access
+ constant c_nof_masters : positive := 2;
constant c_fft : t_fft := func_wpfb_map_wpfb_parameters_to_fft(g_wpfb);
constant c_subband_raw_dat_w : natural := func_fft_raw_dat_w(c_fft);
@@ -378,15 +382,18 @@ begin
);
-- Connect 2 mm_masters to the common_mem_mux output
- master_mosi_arr(0) <= ram_st_sst_mosi; -- MM access via QSYS MM bus
+ -- MM access via QSYS MM bus
+ master_mosi_arr(0) <= ram_st_sst_mosi;
ram_st_sst_miso <= master_miso_arr(0);
- master_mosi_arr(1) <= ram_st_offload_mosi; -- MM access by SST offload
+ -- MM access by SST offload
+ master_mosi_arr(1) <= ram_st_offload_mosi;
ram_st_offload_miso <= master_miso_arr(1);
u_mem_master_mux : entity mm_lib.mm_master_mux
generic map (
g_nof_masters => c_nof_masters,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ -- read latency of statistics RAM is 1
+ g_rd_latency_min => 1
)
port map (
mm_clk => mm_clk,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
index 3e9de6c4baba26d5f0883cd46a1de604b0f50b4f..76e668ab6c79750d9d7afa21fbd3170784d2e49e 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
@@ -114,14 +114,16 @@ architecture str of node_sdp_oversampled_filterbank is
constant c_subband_raw_fraction_w : natural := func_fft_raw_fraction_w(c_fft);
constant c_complex_subband_raw_dat_w : natural := func_fft_raw_dat_w(c_fft_complex);
constant c_complex_subband_raw_fraction_w : natural := func_fft_raw_fraction_w(c_fft_complex);
- constant c_dat_w_diff : integer := c_complex_subband_raw_dat_w - c_subband_raw_dat_w; -- = -1 which is used to shift 1 bit to the left.
+ -- = -1 which is used to shift 1 bit to the left.
+ constant c_dat_w_diff : integer := c_complex_subband_raw_dat_w - c_subband_raw_dat_w;
constant c_nof_masters : positive := 2;
constant c_si_pipeline : natural := 1;
constant c_complex_mult_pipeline : natural := 3;
constant c_complex_pfb_pipeline : natural := 2;
- constant c_pipeline_remove_lsb : natural := 1; -- to easy timing closure
+ -- to easy timing closure
+ constant c_pipeline_remove_lsb : natural := 1;
-- Use WG as local oscillator, buf contains 16b sin and 16b cos
-- . c_sdp_W_local_oscillator = 16b
@@ -139,7 +141,8 @@ architecture str of node_sdp_oversampled_filterbank is
(others => '0'),
(others => '0'),
(others => '0'));
- constant c_wg_phase_offset : natural := 6; -- Compensate for WG start latency. In nof samples.
+ -- Compensate for WG start latency. In nof samples.
+ constant c_wg_phase_offset : natural := 6;
constant c_fil_coefs_mem_addr_w : natural := ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
@@ -317,9 +320,11 @@ begin
dp_bsn_source_restart_delayed <= '0';
elsif si_sosi_arr(0).sop = '1' then
dp_bsn_source_restart_delayed <= dp_bsn_source_restart_pipe;
- if dp_bsn_source_restart_pipe = '1' and si_sosi_arr(0).bsn(0) = '0' then -- even bsn, start now.
+ -- even bsn, start now.
+ if dp_bsn_source_restart_pipe = '1' and si_sosi_arr(0).bsn(0) = '0' then
dp_bsn_source_restart_wg <= '1';
- else -- Odd bsn, start 1 block later.
+ -- Odd bsn, start 1 block later.
+ else
dp_bsn_source_restart_wg <= dp_bsn_source_restart_delayed;
end if;
end if;
@@ -353,9 +358,12 @@ begin
gen_complex_mult: for I in 0 to c_sdp_S_pn - 1 generate
u_common_complex_mult : entity common_mult_lib.common_complex_mult
generic map (
- g_in_a_w => c_sdp_W_local_oscillator, -- = 16
- g_in_b_w => c_sdp_W_adc, -- = 14
- g_out_p_w => c_sdp_W_local_oscillator + c_sdp_W_adc, -- = 16 + 14 = 30
+ -- = 16
+ g_in_a_w => c_sdp_W_local_oscillator,
+ -- = 14
+ g_in_b_w => c_sdp_W_adc,
+ -- = 16 + 14 = 30
+ g_out_p_w => c_sdp_W_local_oscillator + c_sdp_W_adc,
g_conjugate_b => false
)
port map (
@@ -714,15 +722,18 @@ begin
);
-- Connect 2 mm_masters to the common_mem_mux output
- master_mosi_arr(0) <= ram_st_sst_mosi; -- MM access via QSYS MM bus
+ -- MM access via QSYS MM bus
+ master_mosi_arr(0) <= ram_st_sst_mosi;
ram_st_sst_miso <= master_miso_arr(0);
- master_mosi_arr(1) <= ram_st_offload_mosi; -- MM access by SST offload
+ -- MM access by SST offload
+ master_mosi_arr(1) <= ram_st_offload_mosi;
ram_st_offload_miso <= master_miso_arr(1);
u_mem_master_mux : entity mm_lib.mm_master_mux
generic map (
g_nof_masters => c_nof_masters,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ -- read latency of statistics RAM is 1
+ g_rd_latency_min => 1
)
port map (
mm_clk => mm_clk,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
index 8281d80b1bd11b173bc637046d00f1ebb78177cc..49be2db07f55160f7f6afbea63aaf93b55d9d23d 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
@@ -41,8 +41,10 @@ entity sdp_beamformer_local is
generic (
g_bf_weights_file_name : string := "UNUSED";
-- Use no default raw width, to force instance to set it
- g_raw_dat_w : natural; -- default: c_sdp_W_subband;
- g_raw_fraction_w : natural -- default: 0
+ -- default: c_sdp_W_subband;
+ g_raw_dat_w : natural;
+ -- default: 0
+ g_raw_fraction_w : natural
);
port (
dp_clk : in std_logic;
@@ -61,7 +63,8 @@ end sdp_beamformer_local;
architecture str of sdp_beamformer_local is
constant c_complex_adder_latency : natural := ceil_log2(c_sdp_S_pn);
- constant c_bf_weights_latency : natural := 5; -- 3 for complex multiplier + 2 RAM latency
+ -- 3 for complex multiplier + 2 RAM latency
+ constant c_bf_weights_latency : natural := 5;
constant c_total_latency : natural := 3 + c_bf_weights_latency + c_complex_adder_latency;
-- Product width, do -1 to skip double sign bit in product
@@ -234,10 +237,12 @@ begin
g_lsb_w => c_sdp_W_bf_weight_fraction + g_raw_fraction_w,
g_lsb_round => true,
g_lsb_round_clip => false,
- g_msb_clip => false, -- wrap beamlet overflow
+ -- wrap beamlet overflow
+ g_msb_clip => false,
g_msb_clip_symmetric => false,
g_pipeline_remove_lsb => 1,
- g_pipeline_remove_msb => 0, -- no msb clipping, so no need for pipeline
+ -- no msb clipping, so no need for pipeline
+ g_pipeline_remove_msb => 0,
g_in_dat_w => c_complex_adder_sum_w,
g_out_dat_w => c_sdp_W_beamlet_sum
)
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
index 210c308c6596fb1d5d456602cce0a2b7807e870a..223ead69c17a775633f7a05b4abc8aafe3421675 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
@@ -76,8 +76,10 @@ entity sdp_beamformer_output is
end sdp_beamformer_output;
architecture str of sdp_beamformer_output is
- constant c_data_w : natural := c_nof_complex * c_sdp_W_beamlet; -- 16b
- constant c_beamlet_index : natural := g_beamset_id * c_sdp_S_sub_bf; -- call beamset 'id' and beamlet 'index'
+ -- 16b
+ constant c_data_w : natural := c_nof_complex * c_sdp_W_beamlet;
+ -- call beamset 'id' and beamlet 'index'
+ constant c_beamlet_index : natural := g_beamset_id * c_sdp_S_sub_bf;
-- Use c_fifo_fill = c_fifo_size - margin so that FIFO does not get read out too soon.
-- The dp_fifo_fill_eop takes care that the FIFO gets read out whenever there is an
@@ -85,8 +87,10 @@ architecture str of sdp_beamformer_output is
-- it possible to pass on blocks of variable length.
-- Make fifo size large enough for adding header, muxing c_sdp_N_beamsets beamsets and
-- delaying output to be able to realign snk_in.err field from snk_in.eop to src_out.sop.
- constant c_fifo_fill : natural := c_sdp_cep_payload_nof_longwords; -- 976
- constant c_fifo_size : natural := true_log_pow2(c_sdp_cep_payload_nof_longwords) * c_sdp_N_beamsets; -- 2048
+ -- 976
+ constant c_fifo_fill : natural := c_sdp_cep_payload_nof_longwords;
+ -- 2048
+ constant c_fifo_size : natural := true_log_pow2(c_sdp_cep_payload_nof_longwords) * c_sdp_N_beamsets;
signal snk_in_concat : t_dp_sosi;
signal dp_repack_data_src_out : t_dp_sosi;
@@ -108,7 +112,8 @@ architecture str of sdp_beamformer_output is
-- Default set all data path driven header fields to 0
signal dp_offload_tx_hdr_fields : std_logic_vector(1023 downto 0) := (others => '0');
- signal dp_offload_tx_header : t_sdp_cep_header; -- to view dp_offload_tx_hdr_fields in Wave window
+ -- to view dp_offload_tx_hdr_fields in Wave window
+ signal dp_offload_tx_header : t_sdp_cep_header;
begin
-------------------------------------------------------------------------------
-- Input rewiring: concatenate input complex fields to data field
@@ -197,7 +202,8 @@ begin
-- FIFO
-------------------------------------------------------------------------------
u_dp_fifo_fill_eop_sc : entity dp_lib.dp_fifo_fill_eop_sc
- generic map ( -- pass on dp_packet_merge_src_out.err via u_common_fifo_sc_err
+ -- pass on dp_packet_merge_src_out.err via u_common_fifo_sc_err
+ generic map (
g_data_w => c_longword_w,
g_empty_w => c_byte_w,
g_use_empty => true,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
index 11f74388b5f5cb189b8d17adfe68ea0044199480..16b2676693d72873a6b63c51f91fb60d3feedda6 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
@@ -65,9 +65,11 @@ end sdp_beamformer_remote;
architecture str of sdp_beamformer_remote is
constant c_data_w : natural := c_nof_complex * c_sdp_W_beamlet_sum;
constant c_block_size : natural := c_sdp_S_sub_bf * c_sdp_N_pol_bf;
- constant c_fifo_size : natural := 2**ceil_log2((c_block_size * 9) / 16); -- 9/16 = 36/64, 1 block of 64 bit words rounded to the next power of 2 = 1024.
+ -- 9/16 = 36/64, 1 block of 64 bit words rounded to the next power of 2 = 1024.
+ constant c_fifo_size : natural := 2**ceil_log2((c_block_size * 9) / 16);
- signal dispatch_sosi_arr : t_dp_sosi_arr(c_dual - 1 downto 0) := (others => c_dp_sosi_rst); -- 1 for local, 1 for remote.
+ -- 1 for local, 1 for remote.
+ signal dispatch_sosi_arr : t_dp_sosi_arr(c_dual - 1 downto 0) := (others => c_dp_sosi_rst);
signal dp_fifo_sosi : t_dp_sosi := c_dp_sosi_rst;
signal dp_fifo_siso : t_dp_siso := c_dp_siso_rdy;
signal beamlets_data_sosi_arr : t_dp_sosi_arr(c_dual - 1 downto 0) := (others => c_dp_sosi_rst);
@@ -109,9 +111,11 @@ begin
u_dp_repack_data_rx : entity dp_lib.dp_repack_data
generic map (
g_in_dat_w => c_longword_w,
- g_in_nof_words => 9, -- 9/16 = 36/64
+ -- 9/16 = 36/64
+ g_in_nof_words => 9,
g_out_dat_w => c_data_w,
- g_out_nof_words => 16, -- 9/16 = 36/64
+ -- 9/16 = 36/64
+ g_out_nof_words => 16,
g_pipeline_ready => true
)
port map (
@@ -130,14 +134,16 @@ begin
generic map(
-- for dp_bsn_align_v2
g_nof_streams => c_dual,
- g_bsn_latency_max => 2, -- max 2 blocks latency
+ -- max 2 blocks latency
+ g_bsn_latency_max => 2,
g_nof_aligners_max => c_sdp_N_pn_max,
g_block_size => c_block_size,
g_data_w => c_data_w,
g_use_mm_output => false,
g_rd_latency => 1,
-- for mms_dp_bsn_monitor_v2
- g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout, -- Using c_sdp_N_clk_sync_timeout as g_nof_clk_per_sync is used for BSN monitor timeout.
+ -- Using c_sdp_N_clk_sync_timeout as g_nof_clk_per_sync is used for BSN monitor timeout.
+ g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout,
g_nof_input_bsn_monitors => c_dual,
g_use_bsn_output_monitor => true
)
@@ -213,9 +219,11 @@ begin
u_dp_repack_data_local : entity dp_lib.dp_repack_data
generic map (
g_in_dat_w => c_data_w,
- g_in_nof_words => 16, -- 16/9 = 64/36
+ -- 16/9 = 64/36
+ g_in_nof_words => 16,
g_out_dat_w => c_longword_w,
- g_out_nof_words => 9, -- 16/9 = 64/36
+ -- 16/9 = 64/36
+ g_out_nof_words => 9,
g_pipeline_ready => true
)
port map (
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
index 567bc51fb6c9d9c075bebdd60f9523ac9d0f2bdd..4a3e099f20457c5b5b339f81e6b9cc2f65c40437 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
@@ -45,7 +45,8 @@ entity sdp_bf_weights is
generic (
g_gains_file_name : string := "UNUSED";
-- Use no default raw width, to force instance to set it
- g_raw_dat_w : natural -- default: c_sdp_W_subband;
+ -- default: c_sdp_W_subband;
+ g_raw_dat_w : natural
);
port (
dp_clk : in std_logic;
@@ -72,7 +73,8 @@ architecture str of sdp_bf_weights is
signal cnt : natural range 0 to c_sdp_Q_fft * c_sdp_S_sub_bf - 1;
signal gains_rd_address : std_logic_vector(c_gain_addr_w - 1 downto 0);
begin
- in_sosi <= in_sosi_arr(0); -- use ctrl from input [0]
+ -- use ctrl from input [0]
+ in_sosi <= in_sosi_arr(0);
---------------------------------------------------------------
-- Counter
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
index 9296c034921d37dd48dfd5199116263e881872a5..0141296e019f809f275d8fb05d8e6a2ba8d09fb7 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
@@ -87,7 +87,8 @@ architecture str of sdp_crosslets_subband_select is
constant c_row_select_pipeline : natural := 1;
constant c_out_sosi_pipeline : natural := 1;
- type t_crosslets_control_reg is record -- local registers
+ -- local registers
+ type t_crosslets_control_reg is record
offset_index : natural;
row_index : natural;
col_index : natural;
@@ -176,7 +177,8 @@ begin
p_set_unused_crosslets : process(cur_crosslets_info)
begin
-- MM readback the currently active crosslets info, instead of the initial MM written crosslets_info_reg
- crosslets_info_reg_in <= cur_crosslets_info; -- Always use crosslets info 6:0 + step(@ index 15)
+ -- Always use crosslets info 6:0 + step(@ index 15)
+ crosslets_info_reg_in <= cur_crosslets_info;
-- Set crosslets 14:7 to -1
for I in g_N_crosslets to c_sdp_mm_reg_crosslets_info.nof_dat - 2 loop
crosslets_info_reg_in((I + 1) * c_sdp_crosslets_index_w - 1 downto I * c_sdp_crosslets_index_w ) <= TO_SVEC(-1, c_sdp_crosslets_index_w);
@@ -207,11 +209,13 @@ begin
-- start/restart
if start_trigger = '1' then
- v.started := '1'; -- Once started r.started remains active. This is to prevent read/write actions before the initial start_trigger.
+ -- Once started r.started remains active. This is to prevent read/write actions before the initial start_trigger.
+ v.started := '1';
v.offset_index := 0;
v.row_index := 0;
v.col_index := 0;
- v.sync_detected := '0'; -- set sync_detected to 0 in the case that a sync has been detected before the initial start_trigger.
+ -- set sync_detected to 0 in the case that a sync has been detected before the initial start_trigger.
+ v.sync_detected := '0';
-- start_trigger is active on the sync so we can immediatly reset the offsets/step such that they are used in the next packet.
-- It is up to the user to schedule the start trigger on a BSN that coincides with a sync interval if that is desired.
@@ -227,9 +231,11 @@ begin
v.sync_detected := '1';
end if;
- if r.started = '1' then -- Once started r.started remains active.
+ -- Once started r.started remains active.
+ if r.started = '1' then
-- add step to offsets
- if dp_bsn_sync_scheduler_src_out_arr(0).eop = '1' and r.sync_detected = '1' then -- using r.sync_detected to change offsets 1 packet after the sync due to the buffered packet in reorder_col_wide_select
+ -- using r.sync_detected to change offsets 1 packet after the sync due to the buffered packet in reorder_col_wide_select
+ if dp_bsn_sync_scheduler_src_out_arr(0).eop = '1' and r.sync_detected = '1' then
v.sync_detected := '0';
for I in 0 to g_N_crosslets - 1 loop
v_offsets(I) := r.offsets(I) + r.step;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
index ba93d5bf2405af2d0ccdd5f517f258e1b9a146e6..423d66f7594feb95c505f2ce2cd9f659708c7699 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
@@ -42,8 +42,10 @@ use work.sdp_pkg.all;
entity sdp_info is
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
dp_clk : in std_logic;
dp_rst : in std_logic;
@@ -61,7 +63,8 @@ entity sdp_info is
end sdp_info;
architecture str of sdp_info is
- signal sdp_info_ro: t_sdp_info := c_sdp_info_rst; -- ro = read only
+ -- ro = read only
+ signal sdp_info_ro: t_sdp_info := c_sdp_info_rst;
signal block_period: std_logic_vector(15 downto 0);
begin
u_mm_fields: entity work.sdp_info_reg
@@ -87,15 +90,19 @@ begin
begin
if f_adc = '0' then
if fsub_type = '0' then
- block_period <= TO_UVEC(6400, block_period'length); -- 160M, critical sampled
+ -- 160M, critical sampled
+ block_period <= TO_UVEC(6400, block_period'length);
else
- block_period <= TO_UVEC(5400, block_period'length); -- 160M, oversampled
+ -- 160M, oversampled
+ block_period <= TO_UVEC(5400, block_period'length);
end if;
else
if fsub_type = '0' then
- block_period <= TO_UVEC(5120, block_period'length); -- 200M, critical sampled
+ -- 200M, critical sampled
+ block_period <= TO_UVEC(5120, block_period'length);
else
- block_period <= TO_UVEC(4320, block_period'length); -- 200M, oversampled
+ -- 200M, oversampled
+ block_period <= TO_UVEC(4320, block_period'length);
end if;
end if;
end process;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
index 3feac6001af561964fa7328c52b3505040ee1f55..03785568837814173b5c950d5dfbf91783d0b8bd 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
@@ -42,8 +42,10 @@ use work.sdp_pkg.all;
entity sdp_info_reg is
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
dp_clk : in std_logic;
dp_rst : in std_logic;
@@ -52,15 +54,18 @@ entity sdp_info_reg is
reg_miso : out t_mem_miso;
-- sdp info
- sdp_info_ro : in t_sdp_info; -- ro = read only
+ -- ro = read only
+ sdp_info_ro : in t_sdp_info;
sdp_info : out t_sdp_info
);
end sdp_info_reg;
architecture str of sdp_info_reg is
constant c_field_arr : t_common_field_arr(8 downto 0) :=
- ( (field_name_pad("antenna_field_index"), "RW", 6, field_default(0)), -- = station_info[15:10]
- (field_name_pad("station_id"), "RW", 10, field_default(0)), -- = station_info[9:0]
+ -- = station_info[15:10]
+ ( (field_name_pad("antenna_field_index"), "RW", 6, field_default(0)),
+ -- = station_info[9:0]
+ (field_name_pad("station_id"), "RW", 10, field_default(0)),
(field_name_pad("antenna_band_index"), "RW", 1, field_default(0)),
(field_name_pad("observation_id"), "RW", 32, field_default(0)),
(field_name_pad("nyquist_zone_index"), "RW", 2, field_default(0)),
@@ -90,7 +95,8 @@ begin
u_mm_fields: entity mm_lib.mm_fields
generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ -- use FALSE to save logic when always slv_in_val='1'
+ g_use_slv_in_val => false,
g_field_arr => c_field_arr
)
port map (
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index e9dc68716674a535bb5dd91fa0448a5ab3eb1180..41a5578b3bb464c5f18cac471330834a95f4ec83 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -47,8 +47,10 @@ package sdp_pkg is
-- LOFAR2-9258-SDP info per antenna band
-------------------------------------------------
type t_sdp_info is record
- antenna_field_index : std_logic_vector(5 downto 0); -- = station_info[15:10]
- station_id : std_logic_vector(9 downto 0); -- = station_info[9:0]
+ -- = station_info[15:10]
+ antenna_field_index : std_logic_vector(5 downto 0);
+ -- = station_info[9:0]
+ station_id : std_logic_vector(9 downto 0);
antenna_band_index : std_logic;
observation_id : std_logic_vector(31 downto 0);
nyquist_zone_index : std_logic_vector(1 downto 0);
@@ -66,26 +68,33 @@ package sdp_pkg is
-------------------------------------------------
-- SDP specific parameters as defined in [1]
constant c_sdp_f_adc_MHz : natural := 200;
- constant c_sdp_N_band : natural := 2; -- 2 antenna bands, LB and HB
- constant c_sdp_N_beamsets : natural := 2; -- = N_beamsets_sdp in doc
+ -- 2 antenna bands, LB and HB
+ constant c_sdp_N_band : natural := 2;
+ -- = N_beamsets_sdp in doc
+ constant c_sdp_N_beamsets : natural := 2;
constant c_sdp_N_cross_sets_sdp : natural := 1;
constant c_sdp_N_crosslets_max : natural := 7;
constant c_sdp_N_fft : natural := 1024;
- constant c_sdp_N_pn_max : natural := 16; -- max 16 PN per ring = per antenna band
+ -- max 16 PN per ring = per antenna band
+ constant c_sdp_N_pn_max : natural := 16;
constant c_sdp_N_pol : natural := 2;
constant c_sdp_N_pol_bf : natural := 2;
constant c_sdp_N_rings_sdp : natural := 1;
- constant c_sdp_N_ring_lanes_max : natural := 8; -- = N_lane in doc
+ -- = N_lane in doc
+ constant c_sdp_N_ring_lanes_max : natural := 8;
constant c_sdp_N_sub : natural := 512;
constant c_sdp_N_sync_rcu : natural := 1;
constant c_sdp_N_taps : natural := 16;
- constant c_sdp_P_sq : natural := 9; -- = N_pn / 2 + 1
+ -- = N_pn / 2 + 1
+ constant c_sdp_P_sq : natural := 9;
constant c_sdp_Q_fft : natural := 2;
constant c_sdp_S_pn : natural := 12;
constant c_sdp_S_rcu : natural := 3;
constant c_sdp_S_sub_bf : natural := 488;
- constant c_sdp_R_os : natural := 2; -- Oversampling factor of 2 for PFB.
- constant c_sdp_V_ring_pkt_len_max : natural := 48; -- for 16 nodes
+ -- Oversampling factor of 2 for PFB.
+ constant c_sdp_R_os : natural := 2;
+ -- for 16 nodes
+ constant c_sdp_V_ring_pkt_len_max : natural := 48;
constant c_sdp_V_sample_delay : natural := 4096;
constant c_sdp_V_si_db : natural := 1024;
constant c_sdp_V_si_db_large : natural := 131072;
@@ -97,49 +106,87 @@ package sdp_pkg is
constant c_sdp_W_crosslet : natural := 16;
constant c_sdp_W_beamlet_sum : natural := 18;
constant c_sdp_W_beamlet : natural := 8;
- constant c_sdp_W_gn_id : natural := 8; -- = UniBoard2 ID[7:0]
+ -- = UniBoard2 ID[7:0]
+ constant c_sdp_W_gn_id : natural := 8;
constant c_sdp_W_statistic : natural := 64;
- constant c_sdp_W_statistic_sz : natural := 2; -- = c_sdp_W_statistic / c_word_w
- constant c_sdp_W_sub_weight : natural := 16; -- = w in s(w, p), s = signed
- constant c_sdp_W_sub_weight_fraction : natural := 14; -- = p in s(w, p)
- constant c_sdp_W_sub_weight_magnitude : natural := c_sdp_W_sub_weight - c_sdp_W_sub_weight_fraction - 1; -- = 1
- constant c_sdp_W_beamlet_scale : natural := 16; -- = w in u(w, p), u = unsigned
- constant c_sdp_W_beamlet_scale_fraction : natural := 15; -- = p in u(w, p)
- constant c_sdp_W_beamlet_scale_magnitude : natural := c_sdp_W_beamlet_scale - c_sdp_W_beamlet_scale_fraction; -- = 1
- constant c_sdp_W_bf_weight : natural := 16; -- = w in s(w, p), s = signed
- constant c_sdp_W_bf_weight_fraction : natural := 14; -- = p in s(w, p)
- constant c_sdp_W_bf_weight_magnitude : natural := c_sdp_W_bf_weight - c_sdp_W_bf_weight_fraction - 1; -- = 1
- constant c_sdp_W_local_oscillator : natural := 16; -- = w in s(w, p), s = signed
- constant c_sdp_W_local_oscillator_fraction : natural := 15; -- = p in s(w, p)
- constant c_sdp_W_local_oscillator_magnitude : natural := c_sdp_W_local_oscillator - c_sdp_W_local_oscillator_fraction - 1; -- = 0
- constant c_sdp_N_ring_nof_mac10g : natural := 3; -- for sdp_station_xsub_ring design.
+ -- = c_sdp_W_statistic / c_word_w
+ constant c_sdp_W_statistic_sz : natural := 2;
+ -- = w in s(w, p), s = signed
+ constant c_sdp_W_sub_weight : natural := 16;
+ -- = p in s(w, p)
+ constant c_sdp_W_sub_weight_fraction : natural := 14;
+ -- = 1
+ constant c_sdp_W_sub_weight_magnitude : natural := c_sdp_W_sub_weight - c_sdp_W_sub_weight_fraction - 1;
+ -- = w in u(w, p), u = unsigned
+ constant c_sdp_W_beamlet_scale : natural := 16;
+ -- = p in u(w, p)
+ constant c_sdp_W_beamlet_scale_fraction : natural := 15;
+ -- = 1
+ constant c_sdp_W_beamlet_scale_magnitude : natural := c_sdp_W_beamlet_scale - c_sdp_W_beamlet_scale_fraction;
+ -- = w in s(w, p), s = signed
+ constant c_sdp_W_bf_weight : natural := 16;
+ -- = p in s(w, p)
+ constant c_sdp_W_bf_weight_fraction : natural := 14;
+ -- = 1
+ constant c_sdp_W_bf_weight_magnitude : natural := c_sdp_W_bf_weight - c_sdp_W_bf_weight_fraction - 1;
+ -- = w in s(w, p), s = signed
+ constant c_sdp_W_local_oscillator : natural := 16;
+ -- = p in s(w, p)
+ constant c_sdp_W_local_oscillator_fraction : natural := 15;
+ -- = 0
+ constant c_sdp_W_local_oscillator_magnitude : natural := c_sdp_W_local_oscillator - c_sdp_W_local_oscillator_fraction - 1;
+ -- for sdp_station_xsub_ring design.
+ constant c_sdp_N_ring_nof_mac10g : natural := 3;
-- Derived constants
- constant c_sdp_FS_adc : natural := 2**(c_sdp_W_adc - 1); -- full scale FS corresponds to amplitude 1.0, will just cause clipping of +FS to +FS-1
- constant c_sdp_wg_ampl_lsb : real := c_diag_wg_ampl_unit / real(c_sdp_FS_adc); -- WG amplitude in number of LSbit resolution steps
- constant c_sdp_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
- constant c_sdp_N_clk_per_second : natural := c_sdp_f_adc_MHz * 10**6; -- Default 200M clock cycles per second
- constant c_sdp_N_clk_per_sync : natural := c_sdp_f_adc_MHz * 10**6; -- Default 200M clock cycles per sync interval of 1 second
- constant c_sdp_N_clk_sync_timeout : natural := c_sdp_f_adc_MHz * 10**6 + c_sdp_f_adc_MHz * 10**5; -- 10% margin.
- constant c_sdp_N_clk_sync_timeout_xsub : natural := 2147483647; -- = 2**31 - 1 = largest value for NATURAL for 10.7 seconds. Do not use 2*31 to avoid Modelsim NATURAL overflow warning.
- constant c_sdp_N_sync_jesd : natural := c_sdp_S_pn * c_sdp_N_sync_rcu / c_sdp_S_rcu; -- = 4, nof JESD IP sync outputs per PN
- constant c_sdp_f_sub_Hz : real := real(c_sdp_f_adc_MHz * 10**6) / real(c_sdp_N_fft); -- = 195312.5
- constant c_sdp_N_int : natural := c_sdp_f_adc_MHz * 10**6; -- nof ADC sample periods per 1 s integration interval
- constant c_sdp_N_int_sub : real := c_sdp_f_sub_Hz; -- nof subband sample periods per 1 s integration interval
- constant c_sdp_N_int_sub_lo : natural := natural(FLOOR(c_sdp_N_int_sub)); -- = 195312
- constant c_sdp_N_int_sub_hi : natural := natural(CEIL(c_sdp_N_int_sub)); -- = 195313
- constant c_sdp_A_pn : natural := c_sdp_S_pn / c_sdp_N_pol; -- = 6 dual pol antenna per PN, is 6 signal input pairs
- constant c_sdp_P_pfb : natural := c_sdp_S_pn / c_sdp_Q_fft; -- = 6 PFB units, for 6 signal input pairs
- constant c_sdp_T_adc : time := (10**6 / c_sdp_f_adc_MHz) * 1 ps; -- = 5 ns @ 200MHz
- constant c_sdp_T_sub : time := c_sdp_N_fft * c_sdp_T_adc; -- = 5.12 us @ 200MHz
- constant c_sdp_X_sq : natural := c_sdp_S_pn * c_sdp_S_pn; -- = 144
- constant c_sdp_block_period : natural := c_sdp_N_fft * 1000 / c_sdp_f_adc_MHz; -- = 5120 [ns]
- constant c_sdp_N_beamlets_sdp : natural := c_sdp_N_beamsets * c_sdp_S_sub_bf; -- = 976
+ -- full scale FS corresponds to amplitude 1.0, will just cause clipping of +FS to +FS-1
+ constant c_sdp_FS_adc : natural := 2**(c_sdp_W_adc - 1);
+ -- WG amplitude in number of LSbit resolution steps
+ constant c_sdp_wg_ampl_lsb : real := c_diag_wg_ampl_unit / real(c_sdp_FS_adc);
+ -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+ constant c_sdp_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_sdp_N_fft);
+ -- Default 200M clock cycles per second
+ constant c_sdp_N_clk_per_second : natural := c_sdp_f_adc_MHz * 10**6;
+ -- Default 200M clock cycles per sync interval of 1 second
+ constant c_sdp_N_clk_per_sync : natural := c_sdp_f_adc_MHz * 10**6;
+ -- 10% margin.
+ constant c_sdp_N_clk_sync_timeout : natural := c_sdp_f_adc_MHz * 10**6 + c_sdp_f_adc_MHz * 10**5;
+ -- = 2**31 - 1 = largest value for NATURAL for 10.7 seconds. Do not use 2*31 to avoid Modelsim NATURAL overflow warning.
+ constant c_sdp_N_clk_sync_timeout_xsub : natural := 2147483647;
+ -- = 4, nof JESD IP sync outputs per PN
+ constant c_sdp_N_sync_jesd : natural := c_sdp_S_pn * c_sdp_N_sync_rcu / c_sdp_S_rcu;
+ -- = 195312.5
+ constant c_sdp_f_sub_Hz : real := real(c_sdp_f_adc_MHz * 10**6) / real(c_sdp_N_fft);
+ -- nof ADC sample periods per 1 s integration interval
+ constant c_sdp_N_int : natural := c_sdp_f_adc_MHz * 10**6;
+ -- nof subband sample periods per 1 s integration interval
+ constant c_sdp_N_int_sub : real := c_sdp_f_sub_Hz;
+ -- = 195312
+ constant c_sdp_N_int_sub_lo : natural := natural(FLOOR(c_sdp_N_int_sub));
+ -- = 195313
+ constant c_sdp_N_int_sub_hi : natural := natural(CEIL(c_sdp_N_int_sub));
+ -- = 6 dual pol antenna per PN, is 6 signal input pairs
+ constant c_sdp_A_pn : natural := c_sdp_S_pn / c_sdp_N_pol;
+ -- = 6 PFB units, for 6 signal input pairs
+ constant c_sdp_P_pfb : natural := c_sdp_S_pn / c_sdp_Q_fft;
+ -- = 5 ns @ 200MHz
+ constant c_sdp_T_adc : time := (10**6 / c_sdp_f_adc_MHz) * 1 ps;
+ -- = 5.12 us @ 200MHz
+ constant c_sdp_T_sub : time := c_sdp_N_fft * c_sdp_T_adc;
+ -- = 144
+ constant c_sdp_X_sq : natural := c_sdp_S_pn * c_sdp_S_pn;
+ -- = 5120 [ns]
+ constant c_sdp_block_period : natural := c_sdp_N_fft * 1000 / c_sdp_f_adc_MHz;
+ -- = 976
+ constant c_sdp_N_beamlets_sdp : natural := c_sdp_N_beamsets * c_sdp_S_sub_bf;
-- . unit weights
- constant c_sdp_unit_sub_weight : natural := 2**c_sdp_W_sub_weight_fraction; -- 2**13, so range +-4.0 for 16 bit signed weight
- constant c_sdp_unit_bf_weight : natural := 2**c_sdp_W_bf_weight_fraction; -- 2**14, so range +-2.0 for 16 bit signed weight
- constant c_sdp_unit_beamlet_scale : natural := 2**c_sdp_W_beamlet_scale_fraction; -- 2**15, so range +-1.0 for 16 bit signed weight
+ -- 2**13, so range +-4.0 for 16 bit signed weight
+ constant c_sdp_unit_sub_weight : natural := 2**c_sdp_W_sub_weight_fraction;
+ -- 2**14, so range +-2.0 for 16 bit signed weight
+ constant c_sdp_unit_bf_weight : natural := 2**c_sdp_W_bf_weight_fraction;
+ -- 2**15, so range +-1.0 for 16 bit signed weight
+ constant c_sdp_unit_beamlet_scale : natural := 2**c_sdp_W_beamlet_scale_fraction;
-----------------------------------------------------------------------------
-- PFB
@@ -215,7 +262,8 @@ package sdp_pkg is
constant c_sdp_W_fft_stage_dat : natural := 25;
constant c_sdp_W_fft_in_dat : natural := c_sdp_W_fft_stage_dat - c_sdp_W_fft_guard;
constant c_sdp_W_fft_out_gain : natural := 2;
- constant c_sdp_W_stat_data : natural := c_sdp_W_subband * 2 + ceil_log2(c_sdp_N_int_sub_hi); -- = 54
+ -- = 54
+ constant c_sdp_W_stat_data : natural := c_sdp_W_subband * 2 + ceil_log2(c_sdp_N_int_sub_hi);
constant c_sdp_wpfb_subbands : t_wpfb :=
(1, c_sdp_N_fft, 0, c_sdp_P_pfb,
@@ -223,19 +271,22 @@ package sdp_pkg is
true, false, true,
c_sdp_W_fft_in_dat, c_sdp_W_subband, c_sdp_W_fft_out_gain, c_sdp_W_fft_stage_dat, c_sdp_W_fft_guard, true,
c_sdp_W_stat_data, c_sdp_W_statistic_sz, c_sdp_N_int_sub_hi,
- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- = c_wpfb_lofar2_subbands_l2ts_18b
+ -- = c_wpfb_lofar2_subbands_l2ts_18b
+ c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
constant c_sdp_wpfb_complex_subbands : t_wpfb := func_wpfb_map_real_input_wpfb_parameters_to_complex_input(c_sdp_wpfb_subbands);
-- DC gain of WPFB FIR filter obtained from applications/lofar2/model/run_pfir_coef.m using application = 'lofar_subband'
-- Not used in RTL, only used in test benches to verify expected suband levels
- constant c_sdp_wpfb_fir_filter_dc_gain : real := c_fil_lofar1_fir_filter_dc_gain; -- = 0.994817, almost unit DC gain
+ -- = 0.994817, almost unit DC gain
+ constant c_sdp_wpfb_fir_filter_dc_gain : real := c_fil_lofar1_fir_filter_dc_gain;
constant c_sdp_wpfb_subband_sp_ampl_ratio : real := func_wpfb_subband_gain(c_sdp_wpfb_subbands, c_sdp_wpfb_fir_filter_dc_gain);
-----------------------------------------------------------------------------
-- Subband Equalizer
-----------------------------------------------------------------------------
- constant c_sdp_subband_equalizer_latency : natural := 11; -- 11 = 3 reverse + 1 sum + 5 weight + 2 requant
+ -- 11 = 3 reverse + 1 sum + 5 weight + 2 requant
+ constant c_sdp_subband_equalizer_latency : natural := 11;
-----------------------------------------------------------------------------
-- Statistics offload
@@ -251,24 +302,35 @@ package sdp_pkg is
-- Can use same offload time for all statistics, because 1GbE mux will combine them
-- see https://support.astron.nl/confluence/display/L2M/L3+SDP+Testing+Notebook%3A+Statistics+offload
--CONSTANT c_sdp_offload_time : NATURAL := 13000; -- from wave window 62855nS / 5nS = 12571 cycles.
- constant c_sdp_offload_time : natural := 600000; -- 600000 * 5 ns = 3 ms, so gn 31 starts after 93 ms
+ -- 600000 * 5 ns = 3 ms, so gn 31 starts after 93 ms
+ constant c_sdp_offload_time : natural := 600000;
-- packet lengths, see ICD SC-SDP
- constant c_sdp_nof_bytes_per_statistic : natural := 8; -- c_sdp_W_statistic_sz * c_word_sz = 2 * 4 = 8
+ -- c_sdp_W_statistic_sz * c_word_sz = 2 * 4 = 8
+ constant c_sdp_nof_bytes_per_statistic : natural := 8;
constant c_sdp_stat_app_header_len : natural := 32;
- constant c_sdp_stat_eth_dst_mac : std_logic_vector(47 downto 0) := x"001B217176B9"; -- 001B217176B9 = DOP36-enp2s0
- constant c_sdp_stat_eth_src_mac_47_16 : std_logic_vector(31 downto 0) := x"00228608"; -- 00:22:86:08:pp:qq = UNB_ETH_SRC_MAC_BASE in libraries/unb_osy/unbos_eth.h
- constant c_sdp_stat_ip_dst_addr : std_logic_vector(31 downto 0) := x"0A6300FE"; -- 0A6300FE = '10.99.0.254' = DOP36-enp2s0
- constant c_sdp_stat_ip_src_addr_31_16 : std_logic_vector(15 downto 0) := x"0A63"; -- 10.99.xx.yy = g_base_ip in ctrl_unb2#_board.vhd used in libraries/unb_osy/unbos_eth.c
- constant c_sdp_stat_udp_dst_port : std_logic_vector(15 downto 0) := TO_UVEC(5001, 16); -- 0x1389 = 5001
- constant c_sdp_sst_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D0"; -- TBC, 7:0 = gn_id (= ID[7:0] = backplane[5:0] & node[1:0])
- constant c_sdp_bst_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D1"; -- TBC
- constant c_sdp_xst_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D2"; -- TBC
+ -- 001B217176B9 = DOP36-enp2s0
+ constant c_sdp_stat_eth_dst_mac : std_logic_vector(47 downto 0) := x"001B217176B9";
+ -- 00:22:86:08:pp:qq = UNB_ETH_SRC_MAC_BASE in libraries/unb_osy/unbos_eth.h
+ constant c_sdp_stat_eth_src_mac_47_16 : std_logic_vector(31 downto 0) := x"00228608";
+ -- 0A6300FE = '10.99.0.254' = DOP36-enp2s0
+ constant c_sdp_stat_ip_dst_addr : std_logic_vector(31 downto 0) := x"0A6300FE";
+ -- 10.99.xx.yy = g_base_ip in ctrl_unb2#_board.vhd used in libraries/unb_osy/unbos_eth.c
+ constant c_sdp_stat_ip_src_addr_31_16 : std_logic_vector(15 downto 0) := x"0A63";
+ -- 0x1389 = 5001
+ constant c_sdp_stat_udp_dst_port : std_logic_vector(15 downto 0) := TO_UVEC(5001, 16);
+ -- TBC, 7:0 = gn_id (= ID[7:0] = backplane[5:0] & node[1:0])
+ constant c_sdp_sst_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D0";
+ -- TBC
+ constant c_sdp_bst_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D1";
+ -- TBC
+ constant c_sdp_xst_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D2";
constant c_sdp_stat_version_id : natural := 5;
- constant c_sdp_stat_nof_hdr_fields : natural := 1 + 3 + 12 + 4 + 4 + 8 + 7 + 1; -- 608b; 19 32b words
+ -- 608b; 19 32b words
+ constant c_sdp_stat_nof_hdr_fields : natural := 1 + 3 + 12 + 4 + 4 + 8 + 7 + 1;
-- hdr_field_sel bit selects where the hdr_field value is set:
-- . 0 = data path controlled, value is set in sdp_statistics_offload.vhd, so field_default() is not used.
@@ -285,22 +347,26 @@ package sdp_pkg is
-- hdr_fields_in_arr with all 0. Hence e.g. udp_checksum = 0 can be achieve via data path
-- and default hdr_fields_in_arr = 0 or via MM controlled and field_default(0).
-- eth ip udp app
- constant c_sdp_stat_hdr_field_sel : std_logic_vector(c_sdp_stat_nof_hdr_fields - 1 downto 0) := "1" & "101" & "111011111001" & "0100" & "0100" & "00000000" & "1000000" & "0"; -- current
+ -- current
+ constant c_sdp_stat_hdr_field_sel : std_logic_vector(c_sdp_stat_nof_hdr_fields - 1 downto 0) := "1" & "101" & "111011111001" & "0100" & "0100" & "00000000" & "1000000" & "0";
--CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "1"&"101"&"111011111001"&"0101"&"0100"&"00000000"&"0000100"&"0"; -- previous 26 nov 2021
--CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "0"&"100"&"000000010001"&"0100"&"0100"&"00000000"&"1000000"&"0"; -- initial
-- Default use destination MAC/IP/UDP = 0, so these have to be MM programmed before
-- statistics offload packets can be send.
constant c_sdp_stat_hdr_field_arr : t_common_field_arr(c_sdp_stat_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("word_align" ), "RW", 16, field_default(0) ), -- Tx TSE IP will strip these 2 padding bytes
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ), -- c_sdp_stat_eth_dst_mac
+ -- Tx TSE IP will strip these 2 padding bytes
+ ( field_name_pad("word_align" ), "RW", 16, field_default(0) ),
+ -- c_sdp_stat_eth_dst_mac
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ), -- differs for SST, BST, XST so set by data path
+ -- differs for SST, BST, XST so set by data path
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ),
( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
@@ -308,14 +374,18 @@ package sdp_pkg is
( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_sdp_stat_ip_dst_addr
+ -- c_sdp_stat_ip_dst_addr
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ),
( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_sdp_stat_udp_dst_port
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ), -- differs for SST, BST, XST so set by data path
+ -- c_sdp_stat_udp_dst_port
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
+ -- differs for SST, BST, XST so set by data path
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ),
( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("sdp_marker" ), "RW", 8, field_default(0) ), -- differs for SST, BST, XST so set by data path
+ -- differs for SST, BST, XST so set by data path
+ ( field_name_pad("sdp_marker" ), "RW", 8, field_default(0) ),
( field_name_pad("sdp_version_id" ), "RW", 8, field_default(c_sdp_stat_version_id) ),
( field_name_pad("sdp_observation_id" ), "RW", 32, field_default(0) ),
( field_name_pad("sdp_station_info" ), "RW", 16, field_default(0) ),
@@ -359,11 +429,16 @@ package sdp_pkg is
sdp_reserved : std_logic_vector( 7 downto 0);
sdp_integration_interval : std_logic_vector(23 downto 0);
sdp_data_id : std_logic_vector(31 downto 0);
- sdp_data_id_sst_signal_input_index : std_logic_vector( 7 downto 0); -- sdp_data_id sub field
- sdp_data_id_bst_beamlet_index : std_logic_vector(15 downto 0); -- sdp_data_id sub field
- sdp_data_id_xst_subband_index : std_logic_vector(24 downto 16); -- sdp_data_id sub field
- sdp_data_id_xst_signal_input_A_index : std_logic_vector(15 downto 8); -- sdp_data_id sub field
- sdp_data_id_xst_signal_input_B_index : std_logic_vector( 7 downto 0); -- sdp_data_id sub field
+ -- sdp_data_id sub field
+ sdp_data_id_sst_signal_input_index : std_logic_vector( 7 downto 0);
+ -- sdp_data_id sub field
+ sdp_data_id_bst_beamlet_index : std_logic_vector(15 downto 0);
+ -- sdp_data_id sub field
+ sdp_data_id_xst_subband_index : std_logic_vector(24 downto 16);
+ -- sdp_data_id sub field
+ sdp_data_id_xst_signal_input_A_index : std_logic_vector(15 downto 8);
+ -- sdp_data_id sub field
+ sdp_data_id_xst_signal_input_B_index : std_logic_vector( 7 downto 0);
sdp_nof_signal_inputs : std_logic_vector( 7 downto 0);
sdp_nof_bytes_per_statistic : std_logic_vector( 7 downto 0);
sdp_nof_statistics_per_packet : std_logic_vector(15 downto 0);
@@ -373,11 +448,16 @@ package sdp_pkg is
end record;
type t_sdp_stat_data_id is record
- sst_signal_input_index : natural range 0 to 2**8 - 1; -- < 192 = c_sdp_N_pn_max * c_sdp_S_pn
- bst_beamlet_index : natural range 0 to 2**16 - 1; -- < 976 = c_sdp_N_beamsets * c_sdp_S_sub_bf
- xst_subband_index : natural range 0 to 2**9 - 1; -- < 512 = c_sdp_N_sub
- xst_signal_input_A_index : natural range 0 to 2**8 - 1; -- < 192 = c_sdp_N_pn_max * c_sdp_S_pn
- xst_signal_input_B_index : natural range 0 to 2**8 - 1; -- < 192 = c_sdp_N_pn_max * c_sdp_S_pn
+ -- < 192 = c_sdp_N_pn_max * c_sdp_S_pn
+ sst_signal_input_index : natural range 0 to 2**8 - 1;
+ -- < 976 = c_sdp_N_beamsets * c_sdp_S_sub_bf
+ bst_beamlet_index : natural range 0 to 2**16 - 1;
+ -- < 512 = c_sdp_N_sub
+ xst_subband_index : natural range 0 to 2**9 - 1;
+ -- < 192 = c_sdp_N_pn_max * c_sdp_S_pn
+ xst_signal_input_A_index : natural range 0 to 2**8 - 1;
+ -- < 192 = c_sdp_N_pn_max * c_sdp_S_pn
+ xst_signal_input_B_index : natural range 0 to 2**8 - 1;
end record;
type t_sdp_stat_header is record
@@ -391,41 +471,60 @@ package sdp_pkg is
-- Beamlet output via 10GbE to CEP (= central processor, see ICD STAT-CEP)
-----------------------------------------------------------------------------
constant c_sdp_cep_version_id : natural := 5;
- constant c_sdp_marker_beamlets : natural := 98; -- = x"62" = 'b'
-
- constant c_sdp_cep_eth_dst_mac : std_logic_vector(47 downto 0) := x"00074306C700"; -- 00074306C700 = DOP36-eth0
- constant c_sdp_cep_eth_src_mac_47_16 : std_logic_vector(31 downto 0) := x"00228608"; -- 47:16, 15:8 = backplane, 7:0 = node
- constant c_sdp_cep_ip_dst_addr : std_logic_vector(31 downto 0) := x"C0A80001"; -- C0A80001 = '192.168.0.1' = DOP36-eth0
- constant c_sdp_cep_ip_src_addr_31_16 : std_logic_vector(15 downto 0) := x"C0A8"; -- 31:16, 15:8 = backplane, 7:0 = node + 1 = 192.168.xx.yy
- constant c_sdp_cep_ip_total_length : std_logic_vector(15 downto 0) := TO_UVEC(7868, 16); -- see ICD STAT-CEP
- constant c_sdp_cep_udp_total_length : std_logic_vector(15 downto 0) := TO_UVEC(7848, 16); -- see ICD STAT-CEP
- constant c_sdp_cep_udp_dst_port : std_logic_vector(15 downto 0) := TO_UVEC(5000, 16); -- 0x1388 = 5000
- constant c_sdp_cep_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D0"; -- 15:8, 7:0 = gn_id (= ID[7:0] = backplane[5:0] & node[1:0])
-
- constant c_sdp_cep_app_header_len : natural := 32; -- octets, see ICD STAT-CEP
- constant c_sdp_cep_header_len : natural := 14 + 20 + 8 + c_sdp_cep_app_header_len; -- = eth + ip + udp + app = 74 octets, see ICD STAT-CEP
-
- constant c_sdp_cep_nof_blocks_per_packet : natural := 4; -- number of time blocks of beamlets per output packet
- constant c_sdp_cep_nof_beamlets_per_block : natural := c_sdp_S_sub_bf; -- number of dual pol beamlets (c_sdp_N_pol_bf = 2)
- constant c_sdp_cep_nof_beamlets_per_longword : natural := 2; -- 2 dual pol, complex, 8bit beamlets fit in 1 64bit longword
- constant c_sdp_cep_payload_nof_longwords : natural := c_sdp_cep_nof_blocks_per_packet * c_sdp_cep_nof_beamlets_per_block / c_sdp_cep_nof_beamlets_per_longword; -- = 976
- constant c_sdp_cep_packet_nof_longwords : natural := ceil_div(c_sdp_cep_header_len, c_longword_sz) + c_sdp_cep_payload_nof_longwords; -- without tail CRC, the CRC is applied by 10GbE MAC
-
- constant c_sdp_cep_nof_hdr_fields : natural := 3 + 12 + 4 + 4 + 9 + 6 + 1; -- c_sdp_cep_header_len / c_longword_sz = 74 / 8 = 9.25 64b words = 592b
+ -- = x"62" = 'b'
+ constant c_sdp_marker_beamlets : natural := 98;
+
+ -- 00074306C700 = DOP36-eth0
+ constant c_sdp_cep_eth_dst_mac : std_logic_vector(47 downto 0) := x"00074306C700";
+ -- 47:16, 15:8 = backplane, 7:0 = node
+ constant c_sdp_cep_eth_src_mac_47_16 : std_logic_vector(31 downto 0) := x"00228608";
+ -- C0A80001 = '192.168.0.1' = DOP36-eth0
+ constant c_sdp_cep_ip_dst_addr : std_logic_vector(31 downto 0) := x"C0A80001";
+ -- 31:16, 15:8 = backplane, 7:0 = node + 1 = 192.168.xx.yy
+ constant c_sdp_cep_ip_src_addr_31_16 : std_logic_vector(15 downto 0) := x"C0A8";
+ -- see ICD STAT-CEP
+ constant c_sdp_cep_ip_total_length : std_logic_vector(15 downto 0) := TO_UVEC(7868, 16);
+ -- see ICD STAT-CEP
+ constant c_sdp_cep_udp_total_length : std_logic_vector(15 downto 0) := TO_UVEC(7848, 16);
+ -- 0x1388 = 5000
+ constant c_sdp_cep_udp_dst_port : std_logic_vector(15 downto 0) := TO_UVEC(5000, 16);
+ -- 15:8, 7:0 = gn_id (= ID[7:0] = backplane[5:0] & node[1:0])
+ constant c_sdp_cep_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D0";
+
+ -- octets, see ICD STAT-CEP
+ constant c_sdp_cep_app_header_len : natural := 32;
+ -- = eth + ip + udp + app = 74 octets, see ICD STAT-CEP
+ constant c_sdp_cep_header_len : natural := 14 + 20 + 8 + c_sdp_cep_app_header_len;
+
+ -- number of time blocks of beamlets per output packet
+ constant c_sdp_cep_nof_blocks_per_packet : natural := 4;
+ -- number of dual pol beamlets (c_sdp_N_pol_bf = 2)
+ constant c_sdp_cep_nof_beamlets_per_block : natural := c_sdp_S_sub_bf;
+ -- 2 dual pol, complex, 8bit beamlets fit in 1 64bit longword
+ constant c_sdp_cep_nof_beamlets_per_longword : natural := 2;
+ -- = 976
+ constant c_sdp_cep_payload_nof_longwords : natural := c_sdp_cep_nof_blocks_per_packet * c_sdp_cep_nof_beamlets_per_block / c_sdp_cep_nof_beamlets_per_longword;
+ -- without tail CRC, the CRC is applied by 10GbE MAC
+ constant c_sdp_cep_packet_nof_longwords : natural := ceil_div(c_sdp_cep_header_len, c_longword_sz) + c_sdp_cep_payload_nof_longwords;
+
+ -- c_sdp_cep_header_len / c_longword_sz = 74 / 8 = 9.25 64b words = 592b
+ constant c_sdp_cep_nof_hdr_fields : natural := 3 + 12 + 4 + 4 + 9 + 6 + 1;
-- hdr_field_sel bit selects where the hdr_field value is set:
-- . 0 = data path controlled, value is set in sdp_beamformer_output.vhd, so field_default() is not used.
-- . 1 = MM controlled, value is set via MM or by the field_default(), so any data path setting in
-- sdp_beamformer_output.vhd is not used.
-- Remarks: see remarks at c_sdp_stat_nof_hdr_fields.
-- eth ip udp app
- constant c_sdp_cep_hdr_field_sel : std_logic_vector(c_sdp_cep_nof_hdr_fields - 1 downto 0) := "111" & "111111111011" & "1110" & "1100" & "100000010" & "100110" & "0"; -- current
+ -- current
+ constant c_sdp_cep_hdr_field_sel : std_logic_vector(c_sdp_cep_nof_hdr_fields - 1 downto 0) := "111" & "111111111011" & "1110" & "1100" & "100000010" & "100110" & "0";
--CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111001"&"0111"&"1100"&"100000010"&"000110"&"0"; -- previous 27 sep 2022
--CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "100"&"000000010001"&"0100"&"0100"&"100000000"&"101000"&"0"; -- initial
-- Default use source MAC/IP/UDP = 0 and destination MAC/IP/UDP = 0, so these have to be MM programmed
-- before beamlet output packets can be send.
constant c_sdp_cep_hdr_field_arr : t_common_field_arr(c_sdp_cep_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ), -- c_sdp_cep_eth_dst_mac
+ -- c_sdp_cep_eth_dst_mac
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
@@ -440,10 +539,12 @@ package sdp_pkg is
( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_sdp_cep_ip_dst_addr
+ -- c_sdp_cep_ip_dst_addr
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ),
( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_sdp_cep_udp_dst_port
+ -- c_sdp_cep_udp_dst_port
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
( field_name_pad("udp_total_length" ), "RW", 16, field_default(c_sdp_cep_udp_total_length) ),
( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
@@ -524,11 +625,14 @@ package sdp_pkg is
adr_w => 1,
dat_w => c_word_w,
nof_dat => 1,
- init_sl => '0'); -- PIO_JESD_CTRL
+ -- PIO_JESD_CTRL
+ init_sl => '0');
-- AIT MM address widths
- constant c_sdp_jesd204b_addr_w : natural := ceil_log2(c_sdp_S_pn) + tech_jesd204b_port_span_w; -- = 4 + 8
- constant c_sdp_jesd_ctrl_addr_w : natural := c_sdp_mm_jesd_ctrl_reg.adr_w; -- = 1
+ -- = 4 + 8
+ constant c_sdp_jesd204b_addr_w : natural := ceil_log2(c_sdp_S_pn) + tech_jesd204b_port_span_w;
+ -- = 1
+ constant c_sdp_jesd_ctrl_addr_w : natural := c_sdp_mm_jesd_ctrl_reg.adr_w;
constant c_sdp_jesd_ctrl_reset_bi : natural := 31;
constant c_sdp_jesd_ctrl_enable_w : natural := 31;
constant c_sdp_reg_bsn_monitor_input_addr_w : natural := 8;
@@ -537,7 +641,8 @@ package sdp_pkg is
constant c_sdp_reg_dp_shiftram_addr_w : natural := ceil_log2(c_sdp_S_pn) + 1;
constant c_sdp_reg_bsn_source_v2_addr_w : natural := 3;
constant c_sdp_reg_bsn_scheduler_addr_w : natural := 1;
- constant c_sdp_ram_diag_data_buf_bsn_addr_w : natural := ceil_log2(c_sdp_S_pn) + ceil_log2(c_sdp_V_si_db_large); -- Dimension DB address range for largest DB, so that both the large and the default small DB fit.
+ -- Dimension DB address range for largest DB, so that both the large and the default small DB fit.
+ constant c_sdp_ram_diag_data_buf_bsn_addr_w : natural := ceil_log2(c_sdp_S_pn) + ceil_log2(c_sdp_V_si_db_large);
constant c_sdp_reg_diag_data_buf_bsn_addr_w : natural := ceil_log2(c_sdp_S_pn) + 1;
constant c_sdp_ram_st_histogram_addr_w : natural := ceil_log2(c_sdp_S_pn) + ceil_log2(c_sdp_V_si_histogram);
constant c_sdp_reg_aduh_monitor_addr_w : natural := ceil_log2(c_sdp_S_pn) + 2;
@@ -545,9 +650,11 @@ package sdp_pkg is
-- FSUB MM address widths
constant c_sdp_ram_fil_coefs_addr_w : natural := ceil_log2(c_sdp_R_os) + ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
constant c_sdp_ram_st_sst_addr_w : natural := ceil_log2(c_sdp_R_os * c_sdp_P_pfb) + ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * c_sdp_W_statistic_sz);
- constant c_sdp_reg_si_addr_w : natural := 1; -- enable/disable
+ -- enable/disable
+ constant c_sdp_reg_si_addr_w : natural := 1;
constant c_sdp_ram_equalizer_gains_addr_w : natural := ceil_log2(c_sdp_R_os * c_sdp_P_pfb) + ceil_log2(c_sdp_N_sub * c_sdp_Q_fft);
- constant c_sdp_reg_dp_selector_addr_w : natural := 1; -- Select input 0 or 1.
+ -- Select input 0 or 1.
+ constant c_sdp_reg_dp_selector_addr_w : natural := 1;
constant c_sdp_reg_bsn_monitor_v2_sst_offload_addr_w : natural := c_sdp_reg_bsn_monitor_v2_addr_w;
-- STAT UDP offload MM address widths
@@ -578,7 +685,8 @@ package sdp_pkg is
constant c_sdp_mm_reg_crosslets_info : t_c_mem := (latency => 1,
adr_w => 4,
dat_w => c_sdp_crosslets_index_w,
- nof_dat => 16, -- 15 offsets + 1 step
+ -- 15 offsets + 1 step
+ nof_dat => 16,
init_sl => '0');
constant c_sdp_crosslets_info_reg_w : natural := c_sdp_mm_reg_crosslets_info.nof_dat * c_sdp_mm_reg_crosslets_info.dat_w;
constant c_sdp_crosslets_info_nof_offsets : natural := c_sdp_mm_reg_crosslets_info.nof_dat - 1;
@@ -594,10 +702,12 @@ package sdp_pkg is
adr_w => 1,
dat_w => ceil_log2(c_sdp_N_crosslets_max + 1),
nof_dat => 1,
- init_sl => '0'); -- Default = 1
+ -- Default = 1
+ init_sl => '0');
constant c_sdp_nof_crosslets_reg_w : natural := c_sdp_mm_reg_nof_crosslets.nof_dat * c_sdp_mm_reg_nof_crosslets.dat_w;
- constant c_sdp_xst_nof_clk_per_sync_min : natural := c_sdp_N_clk_per_sync / 10; -- 0.1 second
+ -- 0.1 second
+ constant c_sdp_xst_nof_clk_per_sync_min : natural := c_sdp_N_clk_per_sync / 10;
-- XSUB MM address widths
constant c_sdp_reg_crosslets_info_addr_w : natural := c_sdp_mm_reg_crosslets_info.adr_w;
@@ -634,7 +744,8 @@ package sdp_pkg is
-------------------------------------------------
type t_sdp_sim is record
xst_nof_clk_per_sync_min : natural;
- offload_time : natural; -- select > 0 and gn_index > 0 to see effect of offload_time on statistics offload
+ -- select > 0 and gn_index > 0 to see effect of offload_time on statistics offload
+ offload_time : natural;
sync_timeout : natural;
unb_nr : natural;
node_nr : natural;
@@ -664,7 +775,8 @@ package sdp_pkg is
function func_sdp_get_stat_ip_total_length(g_statistics_type : string) return natural;
function func_sdp_get_stat_udp_src_port(g_statistics_type : string; gn_index : natural) return std_logic_vector;
function func_sdp_get_stat_nof_packets(g_statistics_type : string; S_pn, P_sq, N_crosslets : natural) return natural;
- function func_sdp_get_stat_nof_packets(g_statistics_type : string) return natural; -- use c_sdp_S_pn, c_sdp_P_sq, c_sdp_N_crosslets_max
+ -- use c_sdp_S_pn, c_sdp_P_sq, c_sdp_N_crosslets_max
+ function func_sdp_get_stat_nof_packets(g_statistics_type : string) return natural;
function func_sdp_map_stat_header(hdr_fields_raw : std_logic_vector) return t_sdp_stat_header;
function func_sdp_map_cep_header(hdr_fields_raw : std_logic_vector) return t_sdp_cep_header;
@@ -672,9 +784,12 @@ package sdp_pkg is
function func_sdp_map_stat_data_id(g_statistics_type : string; data_id_slv : std_logic_vector) return t_sdp_stat_data_id;
function func_sdp_map_stat_data_id(g_statistics_type : string; data_id_rec : t_sdp_stat_data_id) return std_logic_vector;
- function func_sdp_map_crosslets_info(info_slv : std_logic_vector) return t_sdp_crosslets_info; -- map all c_sdp_N_crosslets_max offsets
- function func_sdp_map_crosslets_info(info_rec : t_sdp_crosslets_info) return std_logic_vector; -- map all c_sdp_N_crosslets_max offsets
- function func_sdp_step_crosslets_info(info_rec : t_sdp_crosslets_info) return t_sdp_crosslets_info; -- step all c_sdp_N_crosslets_max offsets
+ -- map all c_sdp_N_crosslets_max offsets
+ function func_sdp_map_crosslets_info(info_slv : std_logic_vector) return t_sdp_crosslets_info;
+ -- map all c_sdp_N_crosslets_max offsets
+ function func_sdp_map_crosslets_info(info_rec : t_sdp_crosslets_info) return std_logic_vector;
+ -- step all c_sdp_N_crosslets_max offsets
+ function func_sdp_step_crosslets_info(info_rec : t_sdp_crosslets_info) return t_sdp_crosslets_info;
end package sdp_pkg;
@@ -695,7 +810,8 @@ package body sdp_pkg is
-- MOD it is possible to do:
--
-- pn_index = gn_index[3:0], because log2(16) = 4
- constant c_w : natural := ceil_log2(c_sdp_N_pn_max); -- = 4
+ -- = 4
+ constant c_w : natural := ceil_log2(c_sdp_N_pn_max);
variable v_index : std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(gn_index, c_word_w);
begin
@@ -713,58 +829,79 @@ package body sdp_pkg is
end func_sdp_modulo_N_sub;
function func_sdp_get_stat_marker(g_statistics_type : string) return natural is
- constant c_marker_sst : natural := 83; -- = 0x53 = 'S'
- constant c_marker_bst : natural := 66; -- = 0x42 = 'B'
- constant c_marker_xst : natural := 88; -- = 0x58 = 'X'
+ -- = 0x53 = 'S'
+ constant c_marker_sst : natural := 83;
+ -- = 0x42 = 'B'
+ constant c_marker_bst : natural := 66;
+ -- = 0x58 = 'X'
+ constant c_marker_xst : natural := 88;
begin
return sel_a_b(g_statistics_type = "BST", c_marker_bst,
sel_a_b(g_statistics_type = "XST", c_marker_xst,
- c_marker_sst)); -- SST, SST_OS
+ -- SST, SST_OS
+ c_marker_sst));
end func_sdp_get_stat_marker;
function func_sdp_get_stat_nof_signal_inputs(g_statistics_type : string) return natural is
begin
- return sel_a_b(g_statistics_type = "BST", 0, -- not applicable for BST, so use 0,
+ -- not applicable for BST, so use 0,
+ return sel_a_b(g_statistics_type = "BST", 0,
sel_a_b(g_statistics_type = "XST", c_sdp_S_pn,
- 1)); -- SST, SST_OS
+ -- SST, SST_OS
+ 1));
end func_sdp_get_stat_nof_signal_inputs;
function func_sdp_get_stat_from_mm_user_size(g_statistics_type : string) return natural is
-- see sdp_statistics_offload.vhd for description
begin
- return sel_a_b(g_statistics_type = "BST", c_sdp_W_statistic_sz, -- = 2, so preserve X, Y order
- sel_a_b(g_statistics_type = "XST", c_sdp_W_statistic_sz, -- = 2, so preserve Re, Im order
- c_sdp_W_statistic_sz)); -- = 2, SST, SST_OS
+ -- = 2, so preserve X, Y order
+ return sel_a_b(g_statistics_type = "BST", c_sdp_W_statistic_sz,
+ -- = 2, so preserve Re, Im order
+ sel_a_b(g_statistics_type = "XST", c_sdp_W_statistic_sz,
+ -- = 2, SST, SST_OS
+ c_sdp_W_statistic_sz));
end func_sdp_get_stat_from_mm_user_size;
function func_sdp_get_stat_from_mm_data_size(g_statistics_type : string) return natural is
begin
- return sel_a_b(g_statistics_type = "BST", c_sdp_N_pol_bf * c_sdp_W_statistic_sz, -- = 4
- sel_a_b(g_statistics_type = "XST", c_nof_complex * c_sdp_W_statistic_sz, -- = 4
- c_sdp_W_statistic_sz)); -- = 2, SST, SST_OS
+ -- = 4
+ return sel_a_b(g_statistics_type = "BST", c_sdp_N_pol_bf * c_sdp_W_statistic_sz,
+ -- = 4
+ sel_a_b(g_statistics_type = "XST", c_nof_complex * c_sdp_W_statistic_sz,
+ -- = 2, SST, SST_OS
+ c_sdp_W_statistic_sz));
end func_sdp_get_stat_from_mm_data_size;
function func_sdp_get_stat_from_mm_step_size(g_statistics_type : string) return natural is
constant c_data_size : natural := func_sdp_get_stat_from_mm_data_size(g_statistics_type);
begin
- return sel_a_b(g_statistics_type = "BST", c_data_size, -- = 4
- sel_a_b(g_statistics_type = "XST", c_data_size, -- = 4
- c_data_size * c_sdp_Q_fft)); -- = 4, SST, SST_OS
+ -- = 4
+ return sel_a_b(g_statistics_type = "BST", c_data_size,
+ -- = 4
+ sel_a_b(g_statistics_type = "XST", c_data_size,
+ -- = 4, SST, SST_OS
+ c_data_size * c_sdp_Q_fft));
end func_sdp_get_stat_from_mm_step_size;
function func_sdp_get_stat_from_mm_nof_data(g_statistics_type : string) return natural is
begin
- return sel_a_b(g_statistics_type = "BST", c_sdp_S_sub_bf, -- = 488
- sel_a_b(g_statistics_type = "XST", c_sdp_X_sq, -- = 144
- c_sdp_N_sub)); -- = 512, SST, SST_OS
+ -- = 488
+ return sel_a_b(g_statistics_type = "BST", c_sdp_S_sub_bf,
+ -- = 144
+ sel_a_b(g_statistics_type = "XST", c_sdp_X_sq,
+ -- = 512, SST, SST_OS
+ c_sdp_N_sub));
end func_sdp_get_stat_from_mm_nof_data;
-- nof_statistics_per_packet = mm_nof_data * mm_data_size / c_sdp_W_statistic_sz
function func_sdp_get_stat_nof_statistics_per_packet(g_statistics_type : string) return natural is
begin
- return sel_a_b(g_statistics_type = "BST", c_sdp_S_sub_bf * c_sdp_N_pol_bf, -- = 976
- sel_a_b(g_statistics_type = "XST", c_sdp_X_sq * c_nof_complex, -- = 288
- c_sdp_N_sub)); -- = 512, SST, SST_OS
+ -- = 976
+ return sel_a_b(g_statistics_type = "BST", c_sdp_S_sub_bf * c_sdp_N_pol_bf,
+ -- = 288
+ sel_a_b(g_statistics_type = "XST", c_sdp_X_sq * c_nof_complex,
+ -- = 512, SST, SST_OS
+ c_sdp_N_sub));
end func_sdp_get_stat_nof_statistics_per_packet;
function func_sdp_get_stat_app_total_length(g_statistics_type : string) return natural is
@@ -800,9 +937,12 @@ package body sdp_pkg is
function func_sdp_get_stat_udp_src_port(g_statistics_type : string; gn_index : natural) return std_logic_vector is
constant c_gn_index : std_logic_vector(7 downto 0) := TO_UVEC(gn_index, 8);
begin
- return sel_a_b(g_statistics_type = "BST", c_sdp_bst_udp_src_port_15_8 & c_gn_index, -- BST = 0xD1 & gn_index
- sel_a_b(g_statistics_type = "XST", c_sdp_xst_udp_src_port_15_8 & c_gn_index, -- XST = 0xD2 & gn_index
- c_sdp_sst_udp_src_port_15_8 & c_gn_index)); -- SST = 0xD0 & gn_index, SST_OS
+ -- BST = 0xD1 & gn_index
+ return sel_a_b(g_statistics_type = "BST", c_sdp_bst_udp_src_port_15_8 & c_gn_index,
+ -- XST = 0xD2 & gn_index
+ sel_a_b(g_statistics_type = "XST", c_sdp_xst_udp_src_port_15_8 & c_gn_index,
+ -- SST = 0xD0 & gn_index, SST_OS
+ c_sdp_sst_udp_src_port_15_8 & c_gn_index));
end func_sdp_get_stat_udp_src_port;
function func_sdp_get_stat_nof_packets(g_statistics_type : string; S_pn, P_sq, N_crosslets : natural) return natural is
@@ -810,7 +950,8 @@ package body sdp_pkg is
return sel_a_b(g_statistics_type = "BST", 1,
sel_a_b(g_statistics_type = "XST", P_sq * N_crosslets,
sel_a_b(g_statistics_type = "SST", S_pn,
- c_sdp_R_os * S_pn))); -- SST_OS
+ -- SST_OS
+ c_sdp_R_os * S_pn)));
end func_sdp_get_stat_nof_packets;
function func_sdp_get_stat_nof_packets(g_statistics_type : string) return natural is
@@ -942,7 +1083,8 @@ package body sdp_pkg is
v_rec.xst_subband_index := TO_UINT(data_id_slv(24 downto 16));
v_rec.xst_signal_input_A_index := TO_UINT(data_id_slv(15 downto 8));
v_rec.xst_signal_input_B_index := TO_UINT(data_id_slv(7 downto 0));
- else -- SST, SST_OS
+ -- SST, SST_OS
+ else
v_rec.sst_signal_input_index := TO_UINT(data_id_slv(7 downto 0));
end if;
return v_rec;
@@ -957,7 +1099,8 @@ package body sdp_pkg is
v_slv(24 downto 16) := TO_UVEC(data_id_rec.xst_subband_index, 9);
v_slv(15 downto 8) := TO_UVEC(data_id_rec.xst_signal_input_A_index, 8);
v_slv(7 downto 0) := TO_UVEC(data_id_rec.xst_signal_input_B_index, 8);
- else -- SST, SST_OS
+ -- SST, SST_OS
+ else
v_slv(7 downto 0) := TO_UVEC(data_id_rec.sst_signal_input_index, 8);
end if;
return v_slv;
@@ -966,7 +1109,8 @@ package body sdp_pkg is
function func_sdp_map_crosslets_info(info_slv : std_logic_vector) return t_sdp_crosslets_info is
variable v_info : t_sdp_crosslets_info;
begin
- for I in 0 to c_sdp_crosslets_info_nof_offsets - 1 loop -- map al offsets
+ -- map al offsets
+ for I in 0 to c_sdp_crosslets_info_nof_offsets - 1 loop
v_info.offset_arr(I) := TO_UINT(info_slv((I + 1) * c_sdp_crosslets_index_w - 1 downto I * c_sdp_crosslets_index_w));
end loop;
v_info.step := TO_UINT(info_slv(c_sdp_crosslets_info_reg_w - 1 downto c_sdp_crosslets_info_reg_w - c_sdp_crosslets_index_w));
@@ -976,7 +1120,8 @@ package body sdp_pkg is
function func_sdp_map_crosslets_info(info_rec : t_sdp_crosslets_info) return std_logic_vector is
variable v_info : std_logic_vector(c_sdp_crosslets_info_reg_w - 1 downto 0);
begin
- for I in 0 to c_sdp_crosslets_info_nof_offsets - 1 loop -- map all offsets
+ -- map all offsets
+ for I in 0 to c_sdp_crosslets_info_nof_offsets - 1 loop
v_info((I + 1) * c_sdp_crosslets_index_w - 1 downto I * c_sdp_crosslets_index_w) := TO_UVEC(info_rec.offset_arr(I), c_sdp_crosslets_index_w);
end loop;
v_info(c_sdp_crosslets_info_reg_w - 1 downto c_sdp_crosslets_info_reg_w - c_sdp_crosslets_index_w) := TO_UVEC(info_rec.step, c_sdp_crosslets_index_w);
@@ -986,7 +1131,8 @@ package body sdp_pkg is
function func_sdp_step_crosslets_info(info_rec : t_sdp_crosslets_info) return t_sdp_crosslets_info is
variable v_info : t_sdp_crosslets_info := info_rec;
begin
- for I in 0 to c_sdp_crosslets_info_nof_offsets - 1 loop -- step all offsets
+ -- step all offsets
+ for I in 0 to c_sdp_crosslets_info_nof_offsets - 1 loop
-- c_sdp_N_sub = 512 is power of 2, so MOD should be fine in synthesis (simpel skips MSbits, no need for division).
v_info.offset_arr(I) := (v_info.offset_arr(I) + v_info.step) mod c_sdp_N_sub;
end loop;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
index d6d46c4f058fdc98860dc875b0817a9e217fd04b..d1096c1455f03d3231c4c2ca02825a4f981318d8 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
@@ -40,10 +40,14 @@ use work.sdp_pkg.all;
entity sdp_scope is
generic (
g_sim : boolean := false;
- g_selection : natural := 0; -- Time index selection (subband/beamlet)
- g_nof_input : natural := 2; -- nof input streams
- g_n_deinterleave : natural := 2; -- deinterleave factor for each input stream
- g_dat_w : natural := 18 -- Data width
+ -- Time index selection (subband/beamlet)
+ g_selection : natural := 0;
+ -- nof input streams
+ g_nof_input : natural := 2;
+ -- deinterleave factor for each input stream
+ g_n_deinterleave : natural := 2;
+ -- Data width
+ g_dat_w : natural := 18
);
port (
clk : in std_logic;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index e4c467900159aeef3f5d866a652e9dd00cf63ddf..a3178ecf7270e41c59f978116a4535727ec65ea5 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -54,12 +54,15 @@ use ring_lib.ring_pkg.all;
entity sdp_station is
generic (
- g_sim : boolean := false; -- Overridden by TB
- g_sim_sdp : t_sdp_sim := c_sdp_sim; -- Used when g_sim = TRUE, otherwise use HW defaults
+ -- Overridden by TB
+ g_sim : boolean := false;
+ -- Used when g_sim = TRUE, otherwise use HW defaults
+ g_sim_sdp : t_sdp_sim := c_sdp_sim;
g_sim_sync_timeout : natural := 1024;
g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
g_wpfb_complex : t_wpfb := c_sdp_wpfb_complex_subbands;
- g_bsn_nof_clk_per_sync : natural := c_sdp_N_clk_per_sync; -- Default 200M, overide for short simulation
+ -- Default 200M, overide for short simulation
+ g_bsn_nof_clk_per_sync : natural := c_sdp_N_clk_per_sync;
g_scope_selected_subband : natural := 0;
g_no_jesd : boolean := false;
g_use_fsub : boolean := true;
@@ -79,17 +82,22 @@ entity sdp_station is
dp_clk : in std_logic;
-- ID
- gn_id : in std_logic_vector(c_sdp_W_gn_id - 1 downto 0); -- used for udp src port
- this_bck_id : in std_logic_vector(6 - 1 downto 0); -- used for src mac / ip
- this_chip_id : in std_logic_vector(2 - 1 downto 0); -- used for src mac / ip
+ -- used for udp src port
+ gn_id : in std_logic_vector(c_sdp_W_gn_id - 1 downto 0);
+ -- used for src mac / ip
+ this_bck_id : in std_logic_vector(6 - 1 downto 0);
+ -- used for src mac / ip
+ this_chip_id : in std_logic_vector(2 - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0);
-- Connect to the BCK_RX pins in the top wrapper
- JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
+ -- Connect to BCK_REF_CLK pin in the top level wrapper
+ JESD204B_REFCLK : in std_logic;
-- jesd204b syncronization signals
JESD204B_SYSREF : in std_logic;
@@ -392,15 +400,18 @@ architecture str of sdp_station is
constant c_subband_raw_fraction_w : natural := c_fft_raw_fraction_w;
-- Make Tx FIFOs at least c_fifo_tx_fill_margin larger than needed to fit the largest Tx packet
- constant c_fifo_tx_fill_margin : natural := 10; -- >= c_fifo_fill_margin = 6 that is used in dp_fifo_fill_eop
+ -- >= c_fifo_fill_margin = 6 that is used in dp_fifo_fill_eop
+ constant c_fifo_tx_fill_margin : natural := 10;
-- 10 GbE Interface for beamlet output
constant c_nof_10GbE_beamlet_output : natural := 1;
-- The nw_10GbE/tr_10GbE uses dp_fifo_fill_eop, so rely on releasing packets (beamlets, arp and ping) at eop instead
-- of at fill level. Make fifo size large enough to fit one packet and the c_fifo_tx_fill_margin.
- constant c_fifo_tx_size_beamlet_output : natural := true_log_pow2(c_sdp_cep_packet_nof_longwords + c_fifo_tx_fill_margin); -- = 976 + 6 --> 1024
- constant c_fifo_tx_fill_beamlet_output : natural := c_fifo_tx_size_beamlet_output - c_fifo_tx_fill_margin; -- = maximum fill level, so rely on eop
+ -- = 976 + 6 --> 1024
+ constant c_fifo_tx_size_beamlet_output : natural := true_log_pow2(c_sdp_cep_packet_nof_longwords + c_fifo_tx_fill_margin);
+ -- = maximum fill level, so rely on eop
+ constant c_fifo_tx_fill_beamlet_output : natural := c_fifo_tx_size_beamlet_output - c_fifo_tx_fill_margin;
-- Address widths of a single MM instance
constant c_addr_w_ram_ss_ss_wide : natural := ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
@@ -414,19 +425,25 @@ architecture str of sdp_station is
constant c_addr_w_reg_ring_lane_info_bf : natural := 1;
-- Read only sdp_info values
- constant c_f_adc : std_logic := '1'; -- '0' => 160M, '1' => 200M
- constant c_fsub_type : std_logic := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
-
- constant c_lane_payload_nof_longwords_xst : natural := c_sdp_N_crosslets_max * c_sdp_S_pn / 2; -- = crosslet subband select block size divided by 2 as it is repacked from 32b to 64b. = 42 longwords
- constant c_lane_payload_nof_longwords_bf : natural := (c_sdp_S_sub_bf * c_sdp_N_pol_bf * 9) / 16; -- = beamlet block size repacked from 36b to 64b (9/16 = 36/64). = 549 longwords
+ -- '0' => 160M, '1' => 200M
+ constant c_f_adc : std_logic := '1';
+ -- '0' => critical sampled PFB, '1' => oversampled PFB
+ constant c_fsub_type : std_logic := '0';
+
+ -- = crosslet subband select block size divided by 2 as it is repacked from 32b to 64b. = 42 longwords
+ constant c_lane_payload_nof_longwords_xst : natural := c_sdp_N_crosslets_max * c_sdp_S_pn / 2;
+ -- = beamlet block size repacked from 36b to 64b (9/16 = 36/64). = 549 longwords
+ constant c_lane_payload_nof_longwords_bf : natural := (c_sdp_S_sub_bf * c_sdp_N_pol_bf * 9) / 16;
constant c_lane_payload_nof_longwords_max : natural := largest(c_lane_payload_nof_longwords_xst, c_lane_payload_nof_longwords_bf);
- constant c_lane_packet_nof_longwords_max : natural := c_lane_payload_nof_longwords_max + c_ring_dp_hdr_field_size; -- = 549 + 3 = 552
+ -- = 549 + 3 = 552
+ constant c_lane_packet_nof_longwords_max : natural := c_lane_payload_nof_longwords_max + c_ring_dp_hdr_field_size;
-- Use large enough c_lane_total_nof_packets_w, so that lane total nof packets count will not overflow:
-- . For low band XST crosslets on ring : L_packet = (P_sq - 1) * f_sub = 8 * 195312.5 = 1.5625 M packets/s,
-- so 2**48 / (1.5625e6 * 3600 * 24 *365.25) = 5.7 years.
-- . Use same value for BF beamlets on ring.
- constant c_lane_total_nof_packets_w : natural := 48; -- <= c_longword_w = 64
+ -- <= c_longword_w = 64
+ constant c_lane_total_nof_packets_w : natural := 48;
constant c_err_bi : natural := 0;
constant c_nof_err_counts : natural := 8;
@@ -438,19 +455,27 @@ architecture str of sdp_station is
-- Use same Tx FIFO size for all lanes in the ring to ease the code, no need to optimize Tx FIFO RAM usage per lane.
-- The tr_10GbE uses dp_fifo_fill_eop, so rely on releasing packets (beamlets, crosslets) at eop instead
-- of at fill level. Make fifo size large enough to fit one packet and the c_fifo_tx_fill_margin.
- constant c_fifo_tx_size_ring : natural := true_log_pow2(c_lane_packet_nof_longwords_max + c_fifo_tx_fill_margin); -- = 552 + 6 --> 1024
- constant c_fifo_tx_fill_ring : natural := c_fifo_tx_size_ring - c_fifo_tx_fill_margin; -- = maximum fill level, so rely on eop
-
- constant c_nof_even_lanes : natural := 3; -- 0 = XST, 1 = BF_0, 2 = BF_1.
- constant c_lane_nof_if : natural := 3; -- 3 different 10GbE interfaces per pair of lanes: QSFP cable, RING_0 pcb and RING_1 pcb
- constant c_ring_qsfp_if_offset : natural := 0; -- QSFP cable signals are indexed at c_lane_nof_if * I.
- constant c_ring_0_if_offset : natural := 1; -- RING_0 pcb signals are indexed at c_lane_nof_if * I + 1.
- constant c_ring_1_if_offset : natural := 2; -- RING_1 pcb signals are indexed at c_lane_nof_if * I + 2.
+ -- = 552 + 6 --> 1024
+ constant c_fifo_tx_size_ring : natural := true_log_pow2(c_lane_packet_nof_longwords_max + c_fifo_tx_fill_margin);
+ -- = maximum fill level, so rely on eop
+ constant c_fifo_tx_fill_ring : natural := c_fifo_tx_size_ring - c_fifo_tx_fill_margin;
+
+ -- 0 = XST, 1 = BF_0, 2 = BF_1.
+ constant c_nof_even_lanes : natural := 3;
+ -- 3 different 10GbE interfaces per pair of lanes: QSFP cable, RING_0 pcb and RING_1 pcb
+ constant c_lane_nof_if : natural := 3;
+ -- QSFP cable signals are indexed at c_lane_nof_if * I.
+ constant c_ring_qsfp_if_offset : natural := 0;
+ -- RING_0 pcb signals are indexed at c_lane_nof_if * I + 1.
+ constant c_ring_0_if_offset : natural := 1;
+ -- RING_1 pcb signals are indexed at c_lane_nof_if * I + 2.
+ constant c_ring_1_if_offset : natural := 2;
constant c_ring_nof_mac : natural := c_nof_even_lanes * c_lane_nof_if;
-- Using c_ring_nof_mac out of 12 (this is NOT optimized away during synthesis), must
-- match one of the MAC IP variations, e.g. 1, 3, 4, 12, 24, 48
- constant c_ring_nof_mac_ip : natural := 12; -- >= c_ring_nof_mac
+ -- >= c_ring_nof_mac
+ constant c_ring_nof_mac_ip : natural := 12;
type t_dp_sosi_2arr_pfb is array (integer range <>) of t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0);
@@ -543,8 +568,10 @@ architecture str of sdp_station is
signal fsub_oversampled_raw_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0);
signal fsub_raw_sosi_2arr : t_dp_sosi_2arr_pfb(c_sdp_N_beamsets - 1 downto 0);
- signal xst_bs_sosi : t_dp_sosi; -- block sync reference for Xsub ring latency monitor
- signal bf_bs_sosi : t_dp_sosi; -- block sync reference for BF ring latency monitor
+ -- block sync reference for Xsub ring latency monitor
+ signal xst_bs_sosi : t_dp_sosi;
+ -- block sync reference for BF ring latency monitor
+ signal bf_bs_sosi : t_dp_sosi;
signal xst_from_ri_sosi : t_dp_sosi := c_dp_sosi_rst;
signal xst_to_ri_sosi : t_dp_sosi := c_dp_sosi_rst;
@@ -555,8 +582,10 @@ architecture str of sdp_station is
signal lane_rx_board_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0);
signal lane_tx_board_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0);
- signal dp_bsn_source_restart : std_logic; -- used to restart WPFB sync interval timing
- signal dp_bsn_source_new_interval : std_logic; -- used to mask out first sync interval for SST and BST offload
+ -- used to restart WPFB sync interval timing
+ signal dp_bsn_source_restart : std_logic;
+ -- used to mask out first sync interval for SST and BST offload
+ signal dp_bsn_source_new_interval : std_logic;
signal bf_udp_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets - 1 downto 0);
signal bf_udp_siso_arr : t_dp_siso_arr(c_sdp_N_beamsets - 1 downto 0);
@@ -602,15 +631,19 @@ begin
-- . derive beamlet output MAC, IP and UDP Port as in https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L1%20Interface%20Control%20Documents/STAT%20to%20CEP%20ICD
-- . these FW default beamlet output source MAC, IP and UDP port for 10GbE are NOT used in sdp_beamformer_output, because
-- instead they are MM programmable as set by c_sdp_cep_hdr_field_sel
- cep_eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
- cep_ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
+ -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
+ cep_eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w);
+ -- +1 to avoid IP = *.*.*.0
+ cep_ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1);
cep_udp_src_port <= c_sdp_cep_udp_src_port_15_8 & gn_id;
-- . derive statistics offload source MAC/IP/UDP as in: https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD
-- . these FW default statistics offload source MAC, IP and UDP port for 1GbE are used, as set by c_sdp_stat_hdr_field_sel.
-- . the source MAC, IP are the same as for the M&C, because M&C and statistics offload share the same 1GbE
- stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
- stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
+ -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
+ stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w);
+ -- +1 to avoid IP = *.*.*.0
+ stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1);
sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & gn_id;
bst_udp_src_port <= c_sdp_bst_udp_src_port_15_8 & gn_id;
xst_udp_src_port <= c_sdp_xst_udp_src_port_15_8 & gn_id;
@@ -618,8 +651,10 @@ begin
u_sdp_info : entity work.sdp_info
port map(
-- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst => mm_rst,
+ -- memory-mapped bus clock
+ mm_clk => mm_clk,
dp_clk => dp_clk,
dp_rst => dp_rst,
@@ -652,7 +687,8 @@ begin
ring_info => ring_info
);
- this_rn <= TO_UVEC(gn_index - TO_UINT(ring_info.O_rn), c_byte_w) when rising_edge(dp_clk); -- Using register to ease timing closure.
+ -- Using register to ease timing closure.
+ this_rn <= TO_UVEC(gn_index - TO_UINT(ring_info.O_rn), c_byte_w) when rising_edge(dp_clk);
-----------------------------------------------------------------------------
-- node_adc_input_and_timing (AIT)
@@ -714,7 +750,8 @@ begin
-- node_sdp_filterbank (FSUB)
-----------------------------------------------------------------------------
gen_use_fsub : if g_use_fsub generate
- gen_use_no_oversample : if not g_use_oversample generate -- Use normal filterbank
+ -- Use normal filterbank
+ gen_use_no_oversample : if not g_use_oversample generate
u_fsub : entity work.node_sdp_filterbank
generic map(
g_sim => g_sim,
@@ -774,7 +811,8 @@ begin
-----------------------------------------------------------------------------
-- node_sdp_oversampled_filterbank
-----------------------------------------------------------------------------
- gen_use_oversample : if g_use_oversample generate -- use oversampled filterbank instead of normal filterbank
+ -- use oversampled filterbank instead of normal filterbank
+ gen_use_oversample : if g_use_oversample generate
u_fsub : entity work.node_sdp_oversampled_filterbank
generic map(
g_sim => g_sim,
@@ -1141,8 +1179,10 @@ begin
generic map (
g_nof_input => c_sdp_N_beamsets,
g_sel_ctrl_invert => true,
- g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
+ -- no FIFO used but must match g_nof_input
+ g_fifo_size => array_init(0,c_sdp_N_beamsets),
+ -- no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0,c_sdp_N_beamsets)
)
port map (
clk => dp_clk,
@@ -1210,7 +1250,8 @@ begin
gen_xst_ring : if g_use_xsub generate
u_ring_lane_xst : entity ring_lib.ring_lane
generic map (
- g_lane_direction => 1, -- transport in positive direction.
+ -- transport in positive direction.
+ g_lane_direction => 1,
g_lane_data_w => c_longword_w,
g_lane_packet_length => c_lane_payload_nof_longwords_xst,
g_lane_total_nof_packets_w => c_lane_total_nof_packets_w,
@@ -1262,7 +1303,8 @@ begin
gen_beamset_ring : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
u_ring_lane_bf : entity ring_lib.ring_lane
generic map (
- g_lane_direction => 1, -- transport in positive direction.
+ -- transport in positive direction.
+ g_lane_direction => 1,
g_lane_data_w => c_longword_w,
g_lane_packet_length => c_lane_payload_nof_longwords_bf,
g_lane_total_nof_packets_w => c_lane_total_nof_packets_w,
@@ -1288,7 +1330,8 @@ begin
lane_rx_board_sosi => lane_rx_board_sosi_arr(1 + beamset_id),
lane_tx_cable_sosi => lane_tx_cable_sosi_arr(1 + beamset_id),
lane_tx_board_sosi => lane_tx_board_sosi_arr(1 + beamset_id),
- bs_sosi => bf_bs_sosi, -- used for bsn and sync
+ -- used for bsn and sync
+ bs_sosi => bf_bs_sosi,
reg_ring_lane_info_copi => reg_ring_lane_info_bf_copi_arr(beamset_id),
reg_ring_lane_info_cipo => reg_ring_lane_info_bf_cipo_arr(beamset_id),
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index 858a12ce9f8e979dbd3e1828ce5c5b972007d6fa..6e847787873c719ff5ad6de9e93aab959cee00bc 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -112,21 +112,27 @@ entity sdp_statistics_offload is
g_statistics_type : string := "SST";
g_offload_time : natural := c_sdp_offload_time;
g_beamset_id : natural := 0;
- g_P_sq : natural := c_sdp_P_sq; -- number of available correlator cells,
- g_crosslets_direction : natural := 1; -- > 0 for crosslet transport in positive direction (incrementing RN), else 0 for negative direction
- g_reverse_word_order : boolean := true; -- default word order is MSB after LSB, we need to stream LSB after MSB.
+ -- number of available correlator cells,
+ g_P_sq : natural := c_sdp_P_sq;
+ -- > 0 for crosslet transport in positive direction (incrementing RN), else 0 for negative direction
+ g_crosslets_direction : natural := 1;
+ -- default word order is MSB after LSB, we need to stream LSB after MSB.
+ g_reverse_word_order : boolean := true;
g_bsn_monitor_sync_timeout : natural := c_sdp_N_clk_sync_timeout
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
dp_clk : in std_logic;
dp_rst : in std_logic;
-- Memory access to statistics values
- master_mosi : out t_mem_mosi; -- := c_mem_mosi_rst;
+ -- := c_mem_mosi_rst;
+ master_mosi : out t_mem_mosi;
master_miso : in t_mem_miso;
-- Memory access to read/write settings
@@ -154,11 +160,13 @@ entity sdp_statistics_offload is
ip_src_addr : in std_logic_vector(c_network_ip_addr_w - 1 downto 0);
gn_index : in natural;
- ring_info : in t_ring_info := c_ring_info_rst; -- only needed for XST
+ -- only needed for XST
+ ring_info : in t_ring_info := c_ring_info_rst;
sdp_info : in t_sdp_info;
weighted_subbands_flag : in std_logic := '0';
- nof_crosslets : in std_logic_vector(c_sdp_nof_crosslets_reg_w - 1 downto 0) := (others => '0'); -- from MM
+ -- from MM
+ nof_crosslets : in std_logic_vector(c_sdp_nof_crosslets_reg_w - 1 downto 0) := (others => '0');
prev_crosslets_info_rec : in t_sdp_crosslets_info := c_sdp_crosslets_info_rst
);
end sdp_statistics_offload;
@@ -185,26 +193,42 @@ architecture str of sdp_statistics_offload is
-- Parameters that are fixed per node
type t_parameters is record
- gn_index : natural; -- index of this global node
- pn_index : natural; -- index of this node in antenna band
- rn_index : natural; -- index of this ring node
- local_si_offset : natural; -- index of first signal input on this node
- remote_rn : natural; -- index of remote ring node
- remote_gn : natural; -- index of remote global node
- remote_pn : natural; -- index of remote node in antenna band
- remote_si_offset : natural; -- index of first signal input on remote node
- base_dly : natural; -- same base offload delay for nof_cycles_dly per node
- nodes_dly : natural; -- incremental offload delay for nof_cycles_dly per node
- nof_cycles_dly : natural; -- trigger_offload delay for this node
- offset_rn : natural; -- = ring_info.O_rn, GN index of first ring node
- nof_rn : natural; -- = ring_info.N_rn, number of GN in the ring
- nof_used_P_sq : natural; -- number of used correlator cells <= g_P_sq (is number of available correlator cells)
+ -- index of this global node
+ gn_index : natural;
+ -- index of this node in antenna band
+ pn_index : natural;
+ -- index of this ring node
+ rn_index : natural;
+ -- index of first signal input on this node
+ local_si_offset : natural;
+ -- index of remote ring node
+ remote_rn : natural;
+ -- index of remote global node
+ remote_gn : natural;
+ -- index of remote node in antenna band
+ remote_pn : natural;
+ -- index of first signal input on remote node
+ remote_si_offset : natural;
+ -- same base offload delay for nof_cycles_dly per node
+ base_dly : natural;
+ -- incremental offload delay for nof_cycles_dly per node
+ nodes_dly : natural;
+ -- trigger_offload delay for this node
+ nof_cycles_dly : natural;
+ -- = ring_info.O_rn, GN index of first ring node
+ offset_rn : natural;
+ -- = ring_info.N_rn, number of GN in the ring
+ nof_rn : natural;
+ -- number of used correlator cells <= g_P_sq (is number of available correlator cells)
+ nof_used_P_sq : natural;
end record;
-- Input capture per sync interval
type t_input is record
- nof_crosslets : natural range 0 to c_sdp_N_crosslets_max; -- nof_crosslets from MM
- nof_packets : natural; -- nof XST offload packets per integration interval dependend on nof_crosslets
+ -- nof_crosslets from MM
+ nof_crosslets : natural range 0 to c_sdp_N_crosslets_max;
+ -- nof XST offload packets per integration interval dependend on nof_crosslets
+ nof_packets : natural;
bsn_at_sync : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
integration_interval : natural;
crosslets_info_rec : t_sdp_crosslets_info;
@@ -212,7 +236,8 @@ architecture str of sdp_statistics_offload is
payload_err : std_logic;
end record;
- constant c_input_rst : t_input := (0, 0, (others => '0'), 0, c_sdp_crosslets_info_rst, 0, '0'); -- to avoid initial 'X' in sim
+ -- to avoid initial 'X' in sim
+ constant c_input_rst : t_input := (0, 0, (others => '0'), 0, c_sdp_crosslets_info_rst, 0, '0');
-- Offload control
type t_reg is record
@@ -388,14 +413,17 @@ begin
p_reg_parameters : process(dp_clk)
begin
if rising_edge(dp_clk) then
- p.gn_index <= gn_index; -- gn_index[7:0] full GN range
- p.pn_index <= func_sdp_gn_index_to_pn_index(p.gn_index); -- pn_index = 0:15
+ -- gn_index[7:0] full GN range
+ p.gn_index <= gn_index;
+ -- pn_index = 0:15
+ p.pn_index <= func_sdp_gn_index_to_pn_index(p.gn_index);
p.offset_rn <= TO_UINT(ring_info.O_rn);
p.rn_index <= p.gn_index - p.offset_rn;
p.local_si_offset <= p.pn_index * c_sdp_S_pn;
p.base_dly <= TO_UINT(p_gn_id(7 downto 5)) * (g_offload_time / 8);
p.nodes_dly <= TO_UINT(p_gn_id(4 downto 0)) * g_offload_time;
- p.nof_cycles_dly <= p.base_dly + p.nodes_dly + 1; -- + 1 to ensure proper hdr_input.integration_interval also on node 0
+ -- + 1 to ensure proper hdr_input.integration_interval also on node 0
+ p.nof_cycles_dly <= p.base_dly + p.nodes_dly + 1;
p.nof_rn <= TO_UINT(ring_info.N_rn);
p.nof_used_P_sq <= smallest(p.nof_rn / 2 + 1, g_P_sq);
p.remote_rn <= func_ring_nof_hops_to_source_rn(r.instance_count, p.rn_index, p.nof_rn, g_crosslets_direction);
@@ -405,8 +433,10 @@ begin
end if;
end process;
- p_gn_id <= TO_UVEC(p.gn_index, 8); -- in slv format to ease slicing bit ranges
- pp_gn_id <= p_gn_id when rising_edge(dp_clk); -- pipeline again to ease timing closure
+ -- in slv format to ease slicing bit ranges
+ p_gn_id <= TO_UVEC(p.gn_index, 8);
+ -- pipeline again to ease timing closure
+ pp_gn_id <= p_gn_id when rising_edge(dp_clk);
-- Determine info from previous sync interval in which the statistics were
-- measured.
@@ -423,7 +453,8 @@ begin
if in_sosi.sync = '1' then
reg_input.nof_crosslets <= TO_UINT(nof_crosslets);
reg_input.bsn_at_sync <= in_sosi.bsn;
- reg_input.integration_interval <= reg_input.sop_cnt + 1; -- size = index + 1
+ -- size = index + 1
+ reg_input.integration_interval <= reg_input.sop_cnt + 1;
reg_input.crosslets_info_rec <= prev_crosslets_info_rec;
reg_input.sop_cnt <= 0;
reg_input.payload_err <= '0';
@@ -466,11 +497,13 @@ begin
gen_data_id_sst_os : if g_statistics_type = "SST_OS" generate
-- Signal input index is repeated, first 0:11 (r.packet_count 0:11) with fsub_type = 0.
-- Then for r.packet_count 12:23, signal input index is again 0:11 but with fsub_type = 1.
- fsub_type <= '0' when r.packet_count < c_sdp_S_pn else '1'; -- Set fsub_type = 0 for unshifted bands, '1' for shifted bands
+ -- Set fsub_type = 0 for unshifted bands, '1' for shifted bands
+ fsub_type <= '0' when r.packet_count < c_sdp_S_pn else '1';
data_id_rec.sst_signal_input_index <= r.packet_count + p.local_si_offset when r.packet_count < c_sdp_S_pn else r.packet_count - c_sdp_S_pn + p.local_si_offset;
end generate;
- gen_no_os : if g_statistics_type /= "SST_OS" generate -- Set fsub_type to sdp_info.fsub_type when g_statistics_type is not SST_OS.
+ -- Set fsub_type to sdp_info.fsub_type when g_statistics_type is not SST_OS.
+ gen_no_os : if g_statistics_type /= "SST_OS" generate
fsub_type <= sdp_info.fsub_type;
end generate;
@@ -511,11 +544,16 @@ begin
v.start_sync := '1';
v.start_address := 0;
v.packet_count := 0;
- v.interleave_count := 0; -- only used for SST
- v.interleave_address := 0; -- only used for SST
- v.crosslet_count := 0; -- only used for XST
- v.instance_count := 0; -- only used for XST
- v.instance_address := 0; -- only used for XST
+ -- only used for SST
+ v.interleave_count := 0;
+ -- only used for SST
+ v.interleave_address := 0;
+ -- only used for XST
+ v.crosslet_count := 0;
+ -- only used for XST
+ v.instance_count := 0;
+ -- only used for XST
+ v.instance_address := 0;
-- The dp_sop = '1' when the packet has been read from statistics memory
-- and is about to get out of the dp_fifo_fill_eop in
@@ -533,11 +571,13 @@ begin
if g_statistics_type = "SST" or g_statistics_type = "SST_OS" then
-- step step step step step step
-- start_address : 0, 2, 2048, 2050, 4096, 4098, 6144, 6146, 8192, 8194, 10240, 10242
- v.start_address := r.start_address + c_mm_data_size; -- default step to next packet in this step
+ -- default step to next packet in this step
+ v.start_address := r.start_address + c_mm_data_size;
v.interleave_count := r.interleave_count + 1;
if r.interleave_count = c_sdp_Q_fft - 1 then
-- jump to first packet for next step,
- v.start_address := r.interleave_address + c_sdp_N_sub * c_sdp_Q_fft * c_sdp_W_statistic_sz; -- = + 512 * 2 * 2 = + 2048
+ -- = + 512 * 2 * 2 = + 2048
+ v.start_address := r.interleave_address + c_sdp_N_sub * c_sdp_Q_fft * c_sdp_W_statistic_sz;
v.interleave_count := 0;
v.interleave_address := v.start_address;
end if;
@@ -545,7 +585,8 @@ begin
v.packet_count := r.packet_count + 1;
elsif g_statistics_type = "BST" then
- null; -- there is only one BST packet, so no more packets to offload here.
+ -- there is only one BST packet, so no more packets to offload here.
+ null;
elsif g_statistics_type = "XST" then
-- start_address:
@@ -561,19 +602,23 @@ begin
-- 6 24576, 25152, 25728, 26304, 26880, 27456, 28032
-- 7 28672, 29248, 29824, 30400, 30976, 31552, 32128
-- 8 32768, 33344, 33920, 34496, 35072, 35648, 36224
- v.start_address := r.start_address + c_sdp_X_sq * c_nof_complex * c_sdp_W_statistic_sz; -- continue with next packet in this instance
+ -- continue with next packet in this instance
+ v.start_address := r.start_address + c_sdp_X_sq * c_nof_complex * c_sdp_W_statistic_sz;
v.crosslet_count := r.crosslet_count + 1;
if r.crosslet_count = reg_input.nof_crosslets - 1 then
- v.start_address := r.instance_address + 2**c_sdp_ram_st_xsq_addr_w; -- jump to first packet in next instance
+ -- jump to first packet in next instance
+ v.start_address := r.instance_address + 2**c_sdp_ram_st_xsq_addr_w;
v.crosslet_count := 0;
v.instance_count := r.instance_count + 1;
- v.instance_address := v.start_address; -- use v.start_address to avoid multipier needed in (r.instance_count + 1) * 2**c_sdp_ram_st_xsq_addr_w
+ -- use v.start_address to avoid multipier needed in (r.instance_count + 1) * 2**c_sdp_ram_st_xsq_addr_w
+ v.instance_address := v.start_address;
end if;
v.start_pulse := '1';
v.packet_count := r.packet_count + 1;
else
- null; -- do nothing in case of unknown g_statistics_type
+ -- do nothing in case of unknown g_statistics_type
+ null;
end if;
end if;
end if;
@@ -617,7 +662,8 @@ begin
g_word_w => c_word_w,
g_reverse_word_order => g_reverse_word_order,
g_bsn_w => c_dp_stream_bsn_w,
- g_bsn_incr_enable => false -- all offload block have same bsn_at_sync
+ -- all offload block have same bsn_at_sync
+ g_bsn_incr_enable => false
)
port map(
dp_rst => dp_rst,
@@ -630,7 +676,8 @@ begin
start_address => r.start_address,
mm_mosi => master_mosi,
mm_miso => master_miso,
- out_sop => dp_sop, -- = dp_block_from_mm_src_out.sop
+ -- = dp_block_from_mm_src_out.sop
+ out_sop => dp_sop,
out_sosi => dp_block_from_mm_src_out,
out_siso => dp_block_from_mm_src_in
);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
index c42b95e49f6a87ace78f6d4f0a6d4566a5d9563d..8eac1ea7a38fa4661417871993a20a952f3c7e39 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
@@ -57,11 +57,14 @@ use work.sdp_pkg.all;
entity sdp_subband_equalizer is
generic (
- g_gains_file_name : string := "UNUSED"; -- for co-polarization
+ -- for co-polarization
+ g_gains_file_name : string := "UNUSED";
g_nof_streams : natural := c_sdp_P_pfb;
-- Use no default raw width, to force instance to set it
- g_raw_dat_w : natural; -- default: c_sdp_W_subband;
- g_raw_fraction_w : natural -- default: 0
+ -- default: c_sdp_W_subband;
+ g_raw_dat_w : natural;
+ -- default: 0
+ g_raw_fraction_w : natural
);
port (
dp_clk : in std_logic;
@@ -133,11 +136,14 @@ begin
gen_cross_pol : for I in 0 to g_nof_streams - 1 generate
u_cross_pol : entity dp_lib.dp_reverse_n_data
generic map (
- g_pipeline_demux_in => 1, -- serial to parallel section
+ -- serial to parallel section
+ g_pipeline_demux_in => 1,
g_pipeline_demux_out => 0,
- g_pipeline_mux_in => 0, -- parallel to serial section
+ -- parallel to serial section
+ g_pipeline_mux_in => 0,
g_pipeline_mux_out => 1,
- g_reverse_len => c_sdp_N_pol, -- = 2
+ -- = 2
+ g_reverse_len => c_sdp_N_pol,
g_data_w => g_raw_dat_w * c_nof_complex,
g_use_complex => true,
g_signed => true
@@ -157,7 +163,8 @@ begin
-- Total pipeline of sdp_subband_weights is: 5
u_sdp_subband_weigths : entity work.sdp_subband_weights
generic map (
- g_gains_file_name => g_gains_file_name, -- for co polarization
+ -- for co polarization
+ g_gains_file_name => g_gains_file_name,
g_nof_streams => g_nof_streams,
g_raw_dat_w => g_raw_dat_w
)
@@ -222,7 +229,8 @@ begin
g_lsb_w => c_sdp_W_sub_weight_fraction,
g_lsb_round => true,
g_lsb_round_clip => false,
- g_msb_clip => true, -- clip subband overflow
+ -- clip subband overflow
+ g_msb_clip => true,
g_msb_clip_symmetric => false,
g_pipeline_remove_lsb => c_pipeline_remove_lsb,
g_pipeline_remove_msb => c_pipeline_remove_msb,
@@ -247,7 +255,8 @@ begin
g_lsb_w => c_sdp_W_sub_weight_fraction + g_raw_fraction_w,
g_lsb_round => true,
g_lsb_round_clip => false,
- g_msb_clip => true, -- clip subband overflow
+ -- clip subband overflow
+ g_msb_clip => true,
g_msb_clip_symmetric => false,
g_pipeline_remove_lsb => c_pipeline_remove_lsb,
g_pipeline_remove_msb => c_pipeline_remove_msb,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
index 75cbf8a89d652a8f80617f94658647e4aefb2f6a..4b5dcf50717ec9aac403359ac9b9a5fbc91ef2a3 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
@@ -47,10 +47,12 @@ use work.sdp_pkg.all;
entity sdp_subband_weights is
generic (
- g_gains_file_name : string := "UNUSED"; -- for co-polarization
+ -- for co-polarization
+ g_gains_file_name : string := "UNUSED";
g_nof_streams : natural := c_sdp_P_pfb;
-- Use no default raw width, to force instance to set it
- g_raw_dat_w : natural -- default: c_sdp_W_subband
+ -- default: c_sdp_W_subband
+ g_raw_dat_w : natural
);
port (
dp_clk : in std_logic;
@@ -83,7 +85,8 @@ architecture str of sdp_subband_weights is
signal cnt : natural range 0 to c_sdp_Q_fft * c_sdp_N_sub - 1;
signal gains_rd_address : std_logic_vector(c_gain_addr_w - 1 downto 0);
begin
- in_sosi <= in_raw_sosi_arr(0); -- use ctrl from input [0]
+ -- use ctrl from input [0]
+ in_sosi <= in_raw_sosi_arr(0);
-----------------------------------------------------------------------------
-- Counter
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
index 39f4fb1d949f32e0ef866fd5d3505dfc7a93635a..1c5a9a3e569f9c30e93636510d381fd40cbdc69c 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
@@ -56,11 +56,14 @@ architecture tb of tb_sdp_crosslets_subband_select is
constant c_N_crosslets : natural := 2;
constant c_crosslet_offsets : t_natural_arr(0 to c_N_crosslets - 1) := (0, 15);
- constant c_crosslet_step : natural := 3; -- offset step size to increase per sync interval
+ -- offset step size to increase per sync interval
+ constant c_crosslet_step : natural := 3;
- constant c_nof_ch_in : natural := 1024; -- nof input words per block, identical for all input streams.
+ -- nof input words per block, identical for all input streams.
+ constant c_nof_ch_in : natural := 1024;
constant c_nof_ch_sel_row : natural := c_sdp_P_pfb;
- constant c_nof_ch_sel_col : natural := c_sdp_Q_fft; -- nof of sequential columns to select per row.
+ -- nof of sequential columns to select per row.
+ constant c_nof_ch_sel_col : natural := c_sdp_Q_fft;
constant c_nof_ch_sel : natural := c_N_crosslets * c_nof_ch_sel_col * c_nof_ch_sel_row;
constant c_ctrl_interval_size : natural := c_nof_block_per_sync * c_nof_ch_in;
@@ -103,25 +106,30 @@ begin
variable k : natural;
begin
proc_common_wait_until_low(mm_clk, rst);
- proc_common_wait_some_cycles(mm_clk, 50); -- Give dut some time to start
+ -- Give dut some time to start
+ proc_common_wait_some_cycles(mm_clk, 50);
-- Set BSN sync scheduler
proc_mem_mm_bus_wr(1, c_ctrl_interval_size, mm_clk, mm_trigger_miso, mm_trigger_mosi);
proc_mem_mm_bus_wr(2, c_scheduled_bsn, mm_clk, mm_trigger_miso, mm_trigger_mosi);
proc_mem_mm_bus_wr(3, 0, mm_clk, mm_trigger_miso, mm_trigger_mosi);
- proc_mem_mm_bus_wr(0, 1, mm_clk, mm_trigger_miso, mm_trigger_mosi); -- enable
+ -- enable
+ proc_mem_mm_bus_wr(0, 1, mm_clk, mm_trigger_miso, mm_trigger_mosi);
-- Set crosslet info
for I in 0 to c_N_crosslets - 1 loop
- proc_mem_mm_bus_wr(I, c_crosslet_offsets(I), mm_clk, mm_miso, mm_mosi); -- offsets
+ -- offsets
+ proc_mem_mm_bus_wr(I, c_crosslet_offsets(I), mm_clk, mm_miso, mm_mosi);
end loop;
- proc_mem_mm_bus_wr(15, c_crosslet_step, mm_clk, mm_miso, mm_mosi); -- step
+ -- step
+ proc_mem_mm_bus_wr(15, c_crosslet_step, mm_clk, mm_miso, mm_mosi);
proc_common_wait_cross_clock_domain_latency(c_clk_period, c_mm_clk_period);
-- Verify that MM reads the active crosslets_info
-- a) Readback crosslet info after rst release
for I in 0 to c_N_crosslets - 1 loop
- proc_mem_mm_bus_rd(I, mm_clk, mm_miso, mm_mosi); -- offsets
+ -- offsets
+ proc_mem_mm_bus_rd(I, mm_clk, mm_miso, mm_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
rd_crosslet_offsets(I) <= TO_UINT(mm_miso.rddata(c_word_w - 1 downto 0));
end loop;
@@ -141,7 +149,8 @@ begin
proc_common_wait_cross_clock_domain_latency(c_clk_period, c_mm_clk_period);
-- Readback crosslet info
for I in 0 to c_N_crosslets - 1 loop
- proc_mem_mm_bus_rd(I, mm_clk, mm_miso, mm_mosi); -- offsets
+ -- offsets
+ proc_mem_mm_bus_rd(I, mm_clk, mm_miso, mm_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
rd_crosslet_offsets(I) <= TO_UINT(mm_miso.rddata(c_word_w - 1 downto 0));
end loop;
@@ -174,11 +183,14 @@ begin
-- Run some sync intervals with DSP counter data for the real and imag fields
wait until rising_edge(clk);
for I in 0 to c_nof_sync - 1 loop
- proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K));
v_re := v_re + c_nof_ch_in;
v_im := v_im + c_nof_ch_in;
- for J in 0 to c_nof_block_per_sync - 2 loop -- provide sop and eop for block reference
- proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- no sync
+ -- provide sop and eop for block reference
+ for J in 0 to c_nof_block_per_sync - 2 loop
+ -- no sync
+ proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K));
v_re := v_re + c_nof_ch_in;
v_im := v_im + c_nof_ch_in;
end loop;
@@ -210,7 +222,8 @@ begin
variable v_col : natural := 0;
variable v_row : natural := 0;
variable v_offset : natural := 0;
- variable v_sync_ix : natural := 0; -- ix = index
+ -- ix = index
+ variable v_sync_ix : natural := 0;
variable v_k : natural := 0;
begin
for I in 0 to c_nof_sync * c_nof_block_per_sync - 1 loop
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
index ef323ac858df135b1b286ed9e8a2a1728705fed4..3df445f15ba06881cb70cd3c5b45a8657125d39a 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
@@ -45,8 +45,10 @@ entity tb_sdp_info is
end tb_sdp_info;
architecture tb of tb_sdp_info is
- constant c_dp_clk_period : time := 5 ns; -- 200 MHz
- constant c_mm_clk_period : time := 20 ns; -- 50 MHz
+ -- 200 MHz
+ constant c_dp_clk_period : time := 5 ns;
+ -- 50 MHz
+ constant c_mm_clk_period : time := 20 ns;
-- used mm_adresses on mm bus
constant c_mm_addr_block_period : natural := 0;
@@ -62,10 +64,12 @@ architecture tb of tb_sdp_info is
signal tb_end : std_logic := '0';
signal tb_mm_reg_end : std_logic := '0';
- signal dp_clk : std_logic := '1'; -- digital data path clock = 200 MHz (deser factor 4);
+ -- digital data path clock = 200 MHz (deser factor 4);
+ signal dp_clk : std_logic := '1';
signal dp_rst : std_logic;
- signal mm_clk : std_logic := '1'; -- MM control clock = 50 MHz
+ -- MM control clock = 50 MHz
+ signal mm_clk : std_logic := '1';
signal mm_rst : std_logic;
signal reg_mosi : t_mem_mosi := c_mem_mosi_rst;
@@ -95,10 +99,13 @@ begin
proc_common_wait_some_cycles(mm_clk, 100);
-- default all register hold value 0, try to write 1 in all registers
- proc_mem_mm_bus_wr(c_mm_addr_block_period ,11 ,mm_clk, reg_miso, reg_mosi); -- RO
+ -- RO
+ proc_mem_mm_bus_wr(c_mm_addr_block_period ,11 ,mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_wr(c_mm_addr_beam_repositioning_flag,1 ,mm_clk, reg_miso, reg_mosi);
- proc_mem_mm_bus_wr(c_mm_addr_fsub_type ,1 ,mm_clk, reg_miso, reg_mosi); -- RO
- proc_mem_mm_bus_wr(c_mm_addr_f_adc ,1 ,mm_clk, reg_miso, reg_mosi); -- RO
+ -- RO
+ proc_mem_mm_bus_wr(c_mm_addr_fsub_type ,1 ,mm_clk, reg_miso, reg_mosi);
+ -- RO
+ proc_mem_mm_bus_wr(c_mm_addr_f_adc ,1 ,mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_wr(c_mm_addr_nyquist_zone_index ,3 ,mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_wr(c_mm_addr_observation_id ,16 ,mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_wr(c_mm_addr_antenna_band_index ,1 ,mm_clk, reg_miso, reg_mosi);
@@ -201,7 +208,8 @@ begin
-- check if values in sdp_info match with expected values
p_sdp_info_stimuli : process
begin
- proc_common_wait_until_high(mm_clk, tb_mm_reg_end); -- wait for p_mm_reg_stimuli done
+ -- wait for p_mm_reg_stimuli done
+ proc_common_wait_until_high(mm_clk, tb_mm_reg_end);
assert TO_UINT(sdp_info.block_period) = 4320 report "wrong sdp_info.block_period value" severity ERROR;
assert sdp_info.beam_repositioning_flag = '1' report "wrong sdp_info.beam_repositioning_flag value" severity ERROR;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
index 47cc9348b285cc47fc7700505b731c141889f73c..0d1c216ef8cfa01d123f597b997e2ff22736f1f9 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
@@ -42,7 +42,8 @@ package tb_sdp_pkg is
-- Statistics offload
-----------------------------------------------------------------------------
function func_sdp_compose_stat_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
+ -- app header
+ sdp_info : t_sdp_info;
g_statistics_type : string;
weighted_subbands_flag : std_logic;
gn_index : natural;
@@ -61,7 +62,8 @@ package tb_sdp_pkg is
-----------------------------------------------------------------------------
function func_sdp_compose_cep_header(ip_src_addr : std_logic_vector;
ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
+ -- app header
+ sdp_info : t_sdp_info;
gn_index : natural;
payload_error : std_logic;
beamlet_scale : natural;
@@ -69,7 +71,8 @@ package tb_sdp_pkg is
dp_bsn : natural) return t_sdp_cep_header;
function func_sdp_compose_cep_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
+ -- app header
+ sdp_info : t_sdp_info;
gn_index : natural;
payload_error : std_logic;
beamlet_scale : natural;
@@ -90,7 +93,8 @@ package tb_sdp_pkg is
-- . cross_weight = (cross_esub_gain, cross_esub_phase)
function func_sdp_subband_equalizer(sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
- return t_real_arr; -- 0:3 = ampl, phase, re, im
+ -- 0:3 = ampl, phase, re, im
+ return t_real_arr;
-----------------------------------------------------------------------------
-- Beamformer (BF)
@@ -101,12 +105,14 @@ package tb_sdp_pkg is
function func_sdp_beamformer(sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
nof_rem : natural)
- return t_real_arr; -- 0:3 = ampl, phase, re, im
+ -- 0:3 = ampl, phase, re, im
+ return t_real_arr;
end package tb_sdp_pkg;
package body tb_sdp_pkg is
function func_sdp_gn_index_to_mac_15_0(gn_index : natural) return std_logic_vector is
- constant c_unb_nr : natural := gn_index / 4; -- 4 PN per Uniboard2
+ -- 4 PN per Uniboard2
+ constant c_unb_nr : natural := gn_index / 4;
constant c_node_nr : natural := gn_index mod 4;
constant c_mac_15_0 : std_logic_vector(15 downto 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr, 8);
begin
@@ -114,15 +120,18 @@ package body tb_sdp_pkg is
end func_sdp_gn_index_to_mac_15_0;
function func_sdp_gn_index_to_ip_15_0(gn_index : natural) return std_logic_vector is
- constant c_unb_nr : natural := gn_index / 4; -- 4 PN per Uniboard2
+ -- 4 PN per Uniboard2
+ constant c_unb_nr : natural := gn_index / 4;
constant c_node_nr : natural := gn_index mod 4;
- constant c_ip_15_0 : std_logic_vector(15 downto 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr + 1, 8); -- +1 to avoid IP = *.*.*.0
+ -- +1 to avoid IP = *.*.*.0
+ constant c_ip_15_0 : std_logic_vector(15 downto 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr + 1, 8);
begin
return c_ip_15_0;
end func_sdp_gn_index_to_ip_15_0;
function func_sdp_compose_stat_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
+ -- app header
+ sdp_info : t_sdp_info;
g_statistics_type : string;
weighted_subbands_flag : std_logic;
gn_index : natural;
@@ -162,8 +171,10 @@ package body tb_sdp_pkg is
v_hdr.ip.protocol := TO_UVEC( 17, c_network_ip_protocol_w);
-- the IP header check sum is calculated in IO eth, so still 0 here
v_hdr.ip.header_checksum := TO_UVEC(ip_header_checksum, c_network_ip_header_checksum_w);
- v_hdr.ip.src_ip_addr := c_sdp_stat_ip_src_addr_31_16 & c_ip_15_0; -- c_network_ip_addr_w
- v_hdr.ip.dst_ip_addr := c_sdp_stat_ip_dst_addr; -- c_network_ip_addr_w
+ -- c_network_ip_addr_w
+ v_hdr.ip.src_ip_addr := c_sdp_stat_ip_src_addr_31_16 & c_ip_15_0;
+ -- c_network_ip_addr_w
+ v_hdr.ip.dst_ip_addr := c_sdp_stat_ip_dst_addr;
-- udp header
v_hdr.udp.src_port := func_sdp_get_stat_udp_src_port(g_statistics_type, gn_index);
@@ -279,7 +290,8 @@ package body tb_sdp_pkg is
function func_sdp_compose_cep_header(ip_src_addr : std_logic_vector;
ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
+ -- app header
+ sdp_info : t_sdp_info;
gn_index : natural;
payload_error : std_logic;
beamlet_scale : natural;
@@ -305,8 +317,10 @@ package body tb_sdp_pkg is
v_hdr.ip.time_to_live := TO_UVEC( 127, c_network_ip_time_to_live_w);
v_hdr.ip.protocol := TO_UVEC( 17, c_network_ip_protocol_w);
v_hdr.ip.header_checksum := TO_UVEC( ip_header_checksum, c_network_ip_header_checksum_w);
- v_hdr.ip.src_ip_addr := ip_src_addr; -- c_network_ip_addr_w
- v_hdr.ip.dst_ip_addr := c_sdp_cep_ip_dst_addr; -- c_network_ip_addr_w
+ -- c_network_ip_addr_w
+ v_hdr.ip.src_ip_addr := ip_src_addr;
+ -- c_network_ip_addr_w
+ v_hdr.ip.dst_ip_addr := c_sdp_cep_ip_dst_addr;
-- udp header
v_hdr.udp.src_port := c_sdp_cep_udp_src_port_15_8 & TO_UVEC(gn_index, 8);
@@ -342,7 +356,8 @@ package body tb_sdp_pkg is
end func_sdp_compose_cep_header;
function func_sdp_compose_cep_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
+ -- app header
+ sdp_info : t_sdp_info;
gn_index : natural;
payload_error : std_logic;
beamlet_scale : natural;
@@ -421,7 +436,8 @@ package body tb_sdp_pkg is
function func_sdp_subband_equalizer(sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
- return t_real_arr is -- 0:3 = ampl, phase, re, im
+ -- 0:3 = ampl, phase, re, im
+ return t_real_arr is
variable v_sp_ampl, v_sp_phase, v_sp_re, v_sp_im : real;
variable v_cross_ampl, v_cross_phase, v_cross_re, v_cross_im : real;
variable v_sum_ampl, v_sum_phase, v_sum_re, v_sum_im : real;
@@ -435,8 +451,10 @@ package body tb_sdp_pkg is
v_cross_phase := cross_subband_phase + cross_esub_phase;
v_cross_re := COMPLEX_RE(v_cross_ampl, v_cross_phase);
v_cross_im := COMPLEX_IM(v_cross_ampl, v_cross_phase);
- v_sum_re := v_sp_re + v_cross_re; -- ESub sum re
- v_sum_im := v_sp_im + v_cross_im; -- ESub sum im
+ -- ESub sum re
+ v_sum_re := v_sp_re + v_cross_re;
+ -- ESub sum im
+ v_sum_im := v_sp_im + v_cross_im;
v_sum_ampl := COMPLEX_RADIUS(v_sum_re, v_sum_im);
v_sum_phase := COMPLEX_PHASE(v_sum_re, v_sum_im);
v_tuple := (0 => v_sum_ampl, 1 => v_sum_phase, 2 => v_sum_re, 3 => v_sum_im);
@@ -446,8 +464,10 @@ package body tb_sdp_pkg is
function func_sdp_beamformer(sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
nof_rem : natural)
- return t_real_arr is -- 0:3 = ampl, phase, re, im
- variable v_nof_rem : real := real(nof_rem); -- BF for one sp and nof_rem remnant signal inputs
+ -- 0:3 = ampl, phase, re, im
+ return t_real_arr is
+ -- BF for one sp and nof_rem remnant signal inputs
+ variable v_nof_rem : real := real(nof_rem);
variable v_sp_ampl, v_sp_phase, v_sp_re, v_sp_im : real;
variable v_rem_ampl, v_rem_phase, v_rem_re, v_rem_im : real;
variable v_sum_ampl, v_sum_phase, v_sum_re, v_sum_im : real;
@@ -461,8 +481,10 @@ package body tb_sdp_pkg is
v_rem_phase := rem_subband_phase + rem_bf_phase;
v_rem_re := COMPLEX_RE(v_rem_ampl, v_rem_phase);
v_rem_im := COMPLEX_IM(v_rem_ampl, v_rem_phase);
- v_sum_re := v_sp_re + v_nof_rem * v_rem_re; -- BF sum re
- v_sum_im := v_sp_im + v_nof_rem * v_rem_im; -- BF sum im
+ -- BF sum re
+ v_sum_re := v_sp_re + v_nof_rem * v_rem_re;
+ -- BF sum im
+ v_sum_im := v_sp_im + v_nof_rem * v_rem_im;
v_sum_ampl := COMPLEX_RADIUS(v_sum_re, v_sum_im);
v_sum_phase := COMPLEX_PHASE(v_sum_re, v_sum_im);
v_tuple := (0 => v_sum_ampl, 1 => v_sum_phase, 2 => v_sum_re, 3 => v_sum_im);
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
index 235b962b494b04abec47bb73ebe22f026af5bdfa..417de376e4ce01c3aac900cbaec67079f3ca70f7 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
@@ -53,26 +53,37 @@ use work.tb_sdp_pkg.all;
entity tb_sdp_statistics_offload is
generic (
-- All
- g_fast_mm_clk : boolean := true; -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
+ -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
+ g_fast_mm_clk : boolean := true;
-- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
g_statistics_type : string := "XST";
g_offload_time : natural := 50;
- g_reverse_word_order : boolean := true; -- when TRUE then stream LSB word after MSB word.
- g_gn_index : natural := 4; -- global node (GN) index, must be in range(O_rn, O_rn + N_rn), use > 0 to see effect of g_offload_time
- g_nof_sync : natural := 3; -- simulate some sync periods, choose >= 3
+ -- when TRUE then stream LSB word after MSB word.
+ g_reverse_word_order : boolean := true;
+ -- global node (GN) index, must be in range(O_rn, O_rn + N_rn), use > 0 to see effect of g_offload_time
+ g_gn_index : natural := 4;
+ -- simulate some sync periods, choose >= 3
+ g_nof_sync : natural := 3;
-- BST
- g_beamset_id : natural := 0; -- < c_sdp_N_beamsets
+ -- < c_sdp_N_beamsets
+ g_beamset_id : natural := 0;
-- XST
- g_O_rn : natural := 0; -- GN index of first ring node (RN)
- g_N_rn : natural := 8; -- <= c_sdp_N_rn_max = 16, number of nodes in ring
- g_P_sq : natural := 9; -- <= c_sdp_P_sq, nof available correlator cells
- g_nof_crosslets : natural := 4; -- <= c_sdp_N_crosslets_max
- g_crosslets_direction : natural := 1 -- > 0 for crosslet transport in positive direction (incrementing RN), else 0 for negative direction
+ -- GN index of first ring node (RN)
+ g_O_rn : natural := 0;
+ -- <= c_sdp_N_rn_max = 16, number of nodes in ring
+ g_N_rn : natural := 8;
+ -- <= c_sdp_P_sq, nof available correlator cells
+ g_P_sq : natural := 9;
+ -- <= c_sdp_N_crosslets_max
+ g_nof_crosslets : natural := 4;
+ -- > 0 for crosslet transport in positive direction (incrementing RN), else 0 for negative direction
+ g_crosslets_direction : natural := 1
);
end tb_sdp_statistics_offload;
architecture tb of tb_sdp_statistics_offload is
- constant c_dp_clk_period : time := 5 ns; -- 200 MHz
+ -- 200 MHz
+ constant c_dp_clk_period : time := 5 ns;
constant c_mm_clk_period : time := sel_a_b(g_fast_mm_clk, 1 , 10) * 1 ns;
constant c_mm_dp_clk_ratio : natural := sel_a_b(c_mm_clk_period > c_dp_clk_period, c_mm_clk_period / c_dp_clk_period, 1);
@@ -96,23 +107,37 @@ architecture tb of tb_sdp_statistics_offload is
constant c_nof_signal_inputs : natural := func_sdp_get_stat_nof_signal_inputs(g_statistics_type);
constant c_nof_packets_max : natural := func_sdp_get_stat_nof_packets(g_statistics_type, c_sdp_S_pn, g_P_sq, c_sdp_N_crosslets_max);
- constant c_exp_ip_header_checksum : natural := 0; -- 0 in this local tb, calculated by IO eth when used in design
-
- constant c_exp_sdp_info : t_sdp_info := (TO_UVEC(7, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"FFFFFFFF", -- observation_id
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
+ -- 0 in this local tb, calculated by IO eth when used in design
+ constant c_exp_ip_header_checksum : natural := 0;
+
+ -- antenna_field_index
+ constant c_exp_sdp_info : t_sdp_info := (TO_UVEC(7, 6),
+ -- station_id
+ TO_UVEC(601, 10),
+ -- antenna_band_index
+ '0',
+ -- observation_id
+ x"FFFFFFFF",
+ -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ b"01",
+ -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '1',
+ -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0',
+ -- beam_repositioning_flag
+ '0',
+ -- block_period = 5120
+ x"1400"
);
- constant c_exp_ring_info : t_ring_info := (TO_UVEC(g_O_rn, 8), -- GN index of first GN in ring
- TO_UVEC(g_N_rn, 8), -- number of GN in ring
- '0', -- use_cable_to_next_rn
- '0' -- use_cable_to_previous_rn
+ -- GN index of first GN in ring
+ constant c_exp_ring_info : t_ring_info := (TO_UVEC(g_O_rn, 8),
+ -- number of GN in ring
+ TO_UVEC(g_N_rn, 8),
+ -- use_cable_to_next_rn
+ '0',
+ -- use_cable_to_previous_rn
+ '0'
);
constant c_beamlet_index : natural := g_beamset_id * c_sdp_S_sub_bf;
@@ -123,7 +148,8 @@ architecture tb of tb_sdp_statistics_offload is
-- Crosslets settings
constant c_mm_nof_crosslets : std_logic_vector(c_sdp_nof_crosslets_reg_w - 1 downto 0) := TO_UVEC(g_nof_crosslets, c_sdp_nof_crosslets_reg_w);
- constant c_nof_used_P_sq : natural := smallest(g_N_rn / 2 + 1, g_P_sq); -- number of used correlator cells <= g_P_sq
+ -- number of used correlator cells <= g_P_sq
+ constant c_nof_used_P_sq : natural := smallest(g_N_rn / 2 + 1, g_P_sq);
constant c_rx_nof_packets : natural := func_sdp_get_stat_nof_packets(g_statistics_type, c_sdp_S_pn, c_nof_used_P_sq, g_nof_crosslets);
-- payload data
@@ -141,10 +167,12 @@ architecture tb of tb_sdp_statistics_offload is
constant c_mm_data_size : natural := func_sdp_get_stat_from_mm_data_size(g_statistics_type);
constant c_mm_step_size : natural := func_sdp_get_stat_from_mm_step_size(g_statistics_type);
constant c_mm_nof_data : natural := func_sdp_get_stat_from_mm_nof_data(g_statistics_type);
- constant c_mm_ram_size : natural := c_mm_nof_data * c_mm_data_size * c_nof_packets_max; -- = c_ram_size
+ -- = c_ram_size
+ constant c_mm_ram_size : natural := c_mm_nof_data * c_mm_data_size * c_nof_packets_max;
constant c_mm_nof_step : natural := c_mm_step_size / c_mm_data_size;
- constant c_mm_Xsq_span : natural := 2**ceil_log2(c_sdp_N_crosslets_max * c_packet_size); -- XST: 2**ceil_log2(7 * 576) = 4096
+ -- XST: 2**ceil_log2(7 * 576) = 4096
+ constant c_mm_Xsq_span : natural := 2**ceil_log2(c_sdp_N_crosslets_max * c_packet_size);
-- Define block timing.
constant c_bsn_init : natural := 0;
@@ -155,10 +183,12 @@ architecture tb of tb_sdp_statistics_offload is
signal tb_end : std_logic := '0';
- signal dp_clk : std_logic := '1'; -- Digital data path clock = 200 MHz (deser factor 4);
+ -- Digital data path clock = 200 MHz (deser factor 4);
+ signal dp_clk : std_logic := '1';
signal dp_rst : std_logic;
- signal mm_clk : std_logic := '1'; -- MM control clock = 50 MHz
+ -- MM control clock = 50 MHz
+ signal mm_clk : std_logic := '1';
signal mm_rst : std_logic;
signal master_mosi : t_mem_mosi := c_mem_mosi_rst;
@@ -177,12 +207,14 @@ architecture tb of tb_sdp_statistics_offload is
signal in_sosi : t_dp_sosi := c_dp_sosi_rst;
signal in_crosslets_info_rec : t_sdp_crosslets_info;
- signal sdp_offload_data : std_logic_vector(c_word_w - 1 downto 0); -- 32 bit
+ -- 32 bit
+ signal sdp_offload_data : std_logic_vector(c_word_w - 1 downto 0);
signal sdp_offload_sosi : t_dp_sosi;
signal sdp_offload_siso : t_dp_siso := c_dp_siso_rst;
signal rx_offload_en : std_logic := '0';
- signal rx_offload_data : std_logic_vector(c_word_w - 1 downto 0); -- 32 bit
+ -- 32 bit
+ signal rx_offload_data : std_logic_vector(c_word_w - 1 downto 0);
signal rx_offload_sosi : t_dp_sosi := c_dp_sosi_rst;
signal rx_offload_sop_cnt : natural := 0;
signal rx_offload_eop_cnt : natural := 0;
@@ -207,10 +239,14 @@ architecture tb of tb_sdp_statistics_offload is
signal rx_data : natural;
signal exp_data : natural;
- signal gn_index : natural := g_gn_index; -- this node GN
- signal rn_index : natural := g_gn_index - g_O_rn; -- this node RN
- signal source_rn : natural; -- source node RN
- signal source_gn : natural; -- source node GN
+ -- this node GN
+ signal gn_index : natural := g_gn_index;
+ -- this node RN
+ signal rn_index : natural := g_gn_index - g_O_rn;
+ -- source node RN
+ signal source_rn : natural;
+ -- source node GN
+ signal source_gn : natural;
signal weighted_subbands_flag : std_logic := '0';
@@ -333,8 +369,10 @@ begin
-- Write statistics offload destination MAC/IP/UDP
-- . obtain relative MM word addresses e.g. from lofar2_unb2c_sdp_station.mmap or from sdp.peripheral.yaml
proc_mem_mm_bus_wr(16#17#, TO_UINT(c_sdp_stat_udp_dst_port), mm_clk, hdr_dat_miso, hdr_dat_mosi);
- proc_mem_mm_bus_wr(16#19#, TO_SINT(c_sdp_stat_ip_dst_addr), mm_clk, hdr_dat_miso, hdr_dat_mosi); -- use signed to fit 32 b in INTEGER
- proc_mem_mm_bus_wr(16#28#, TO_SINT(c_sdp_stat_eth_dst_mac(31 downto 0)), mm_clk, hdr_dat_miso, hdr_dat_mosi); -- use signed to fit 32 b in INTEGER
+ -- use signed to fit 32 b in INTEGER
+ proc_mem_mm_bus_wr(16#19#, TO_SINT(c_sdp_stat_ip_dst_addr), mm_clk, hdr_dat_miso, hdr_dat_mosi);
+ -- use signed to fit 32 b in INTEGER
+ proc_mem_mm_bus_wr(16#28#, TO_SINT(c_sdp_stat_eth_dst_mac(31 downto 0)), mm_clk, hdr_dat_miso, hdr_dat_mosi);
proc_mem_mm_bus_wr(16#29#, TO_UINT(c_sdp_stat_eth_dst_mac(47 downto 32)), mm_clk, hdr_dat_miso, hdr_dat_mosi);
-- Enable common variable delay.
@@ -351,10 +389,12 @@ begin
if rising_edge(dp_clk) then
-- Count rx_offload_sosi packets
if rx_offload_sosi.sop = '1' then
- rx_offload_sop_cnt <= rx_offload_sop_cnt + 1; -- early count
+ -- early count
+ rx_offload_sop_cnt <= rx_offload_sop_cnt + 1;
end if;
if rx_offload_sosi.eop = '1' then
- rx_offload_eop_cnt <= rx_offload_eop_cnt + 1; -- after count
+ -- after count
+ rx_offload_eop_cnt <= rx_offload_eop_cnt + 1;
end if;
end if;
end process;
@@ -374,10 +414,13 @@ begin
-- verify it at rx_offload_sosi.eop.
-- For all statistics
- cur_dp_bsn <= c_bsn_init + 1 + rx_sync_cnt * c_nof_block_per_sync; -- in current sync interval
- exp_dp_bsn <= cur_dp_bsn when rising_edge(dp_clk) and rx_offload_sosi.sync = '1'; -- previous sync interval
+ -- in current sync interval
+ cur_dp_bsn <= c_bsn_init + 1 + rx_sync_cnt * c_nof_block_per_sync;
+ -- previous sync interval
+ exp_dp_bsn <= cur_dp_bsn when rising_edge(dp_clk) and rx_offload_sosi.sync = '1';
-- SST, SST_OS
- exp_sst_signal_input <= (rx_packet_cnt mod c_sdp_S_pn) + c_sdp_S_pn * gn_index; -- Using MOD c_sdp_S_pn for SST_OS.
+ -- Using MOD c_sdp_S_pn for SST_OS.
+ exp_sst_signal_input <= (rx_packet_cnt mod c_sdp_S_pn) + c_sdp_S_pn * gn_index;
gen_fsub_type : if g_statistics_type = "SST_OS" generate
exp_sdp_info.fsub_type <= '0' when rx_packet_cnt < c_sdp_S_pn else '1';
@@ -454,16 +497,26 @@ begin
end process;
p_verify_payload : process(dp_clk)
- variable W : natural; -- 32bit Words
- variable D : natural; -- Data values of c_mm_data_size
- variable S : natural; -- Statistic values of c_sdp_W_statistic_sz
- variable P : natural; -- Packet count
- variable I, J, K, L : natural; -- auxiliary index
- variable U : natural; -- real sUbband SST values
- variable B : natural; -- dual polarization Beamlet BST values
- variable X : natural; -- complex crosslet XST values
- variable v_rx_data : natural; -- received (rx) 32bit word
- variable v_exp_data : natural; -- expected (exp) 32bit word
+ -- 32bit Words
+ variable W : natural;
+ -- Data values of c_mm_data_size
+ variable D : natural;
+ -- Statistic values of c_sdp_W_statistic_sz
+ variable S : natural;
+ -- Packet count
+ variable P : natural;
+ -- auxiliary index
+ variable I, J, K, L : natural;
+ -- real sUbband SST values
+ variable U : natural;
+ -- dual polarization Beamlet BST values
+ variable B : natural;
+ -- complex crosslet XST values
+ variable X : natural;
+ -- received (rx) 32bit word
+ variable v_rx_data : natural;
+ -- expected (exp) 32bit word
+ variable v_exp_data : natural;
begin
if rising_edge(dp_clk) then
rx_val <= '0';
@@ -485,23 +538,34 @@ begin
-- g_reverse_word_order = TRUE: swaps odd and even W columns, because
-- c_mm_user_size = c_sdp_W_statistic_sz = 2
- W := rx_valid_cnt; -- range c_packet_size = 1024 32bit Words
- S := W / c_sdp_W_statistic_sz; -- range c_nof_statistics_per_packet = 512 Statistic values
- D := S; -- range c_mm_nof_data = 512 Data values, because
+ -- range c_packet_size = 1024 32bit Words
+ W := rx_valid_cnt;
+ -- range c_nof_statistics_per_packet = 512 Statistic values
+ S := W / c_sdp_W_statistic_sz;
+ -- range c_mm_nof_data = 512 Data values, because
+ D := S;
-- c_mm_data_size / c_sdp_W_statistic_sz = 1
- U := S; -- range c_sdp_N_sub = 512 SST values
- I := W mod c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
- P := rx_packet_cnt mod c_rx_nof_packets; -- range c_nof_packets_max = 12 = c_sdp_S_pn packets
- J := P mod c_mm_nof_step; -- range c_mm_nof_step = 2 = c_sdp_Q_fft
-
- v_exp_data := S * 4; -- due to c_mm_step_size = 4 = c_sdp_W_statistic_sz * c_sdp_Q_fft;
+ -- range c_sdp_N_sub = 512 SST values
+ U := S;
+ -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
+ I := W mod c_mm_user_size;
+ -- range c_nof_packets_max = 12 = c_sdp_S_pn packets
+ P := rx_packet_cnt mod c_rx_nof_packets;
+ -- range c_mm_nof_step = 2 = c_sdp_Q_fft
+ J := P mod c_mm_nof_step;
+
+ -- due to c_mm_step_size = 4 = c_sdp_W_statistic_sz * c_sdp_Q_fft;
+ v_exp_data := S * 4;
if I = sel_a_b(g_reverse_word_order, 0, 1) then
- v_exp_data := v_exp_data + 1; -- due to c_mm_user_size = 2
+ -- due to c_mm_user_size = 2
+ v_exp_data := v_exp_data + 1;
end if;
if J = 1 then
- v_exp_data := v_exp_data + 2; -- due to c_sdp_W_statistic_sz = 2 and c_mm_nof_step = 2 > 1
+ -- due to c_sdp_W_statistic_sz = 2 and c_mm_nof_step = 2 > 1
+ v_exp_data := v_exp_data + 2;
end if;
- v_exp_data := v_exp_data + (P / 2) * 2048; -- due to c_packet_size = 1024 and c_mm_nof_step = 2 > 1
+ -- due to c_packet_size = 1024 and c_mm_nof_step = 2 > 1
+ v_exp_data := v_exp_data + (P / 2) * 2048;
if g_statistics_type = "SST" then assert v_exp_data = v_rx_data report "Wrong SST payload data Rx" severity ERROR; end if;
if g_statistics_type = "SST_OS" then assert v_exp_data = v_rx_data report "Wrong SST_OS payload data Rx" severity ERROR; end if;
@@ -517,15 +581,22 @@ begin
-- g_reverse_word_order = TRUE: swaps odd and even W columns, because
-- c_mm_user_size = c_sdp_W_statistic_sz = 2
- W := rx_valid_cnt; -- range c_packet_size = 1952
- S := W / c_sdp_W_statistic_sz; -- range c_nof_statistics_per_packet = 976 Statistic values
- D := S / c_sdp_N_pol_bf; -- range c_mm_nof_data = 488 Data values, because
+ -- range c_packet_size = 1952
+ W := rx_valid_cnt;
+ -- range c_nof_statistics_per_packet = 976 Statistic values
+ S := W / c_sdp_W_statistic_sz;
+ -- range c_mm_nof_data = 488 Data values, because
+ D := S / c_sdp_N_pol_bf;
-- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_sdp_N_pol_bf
- B := D; -- range c_sdp_S_sub_bf = 488 dual polarization BST values
- I := W mod c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
- P := rx_packet_cnt mod c_rx_nof_packets; -- range c_nof_packets_max = 1 packet
-
- v_exp_data := S * c_mm_user_size; -- c_mm_user_size = 2
+ -- range c_sdp_S_sub_bf = 488 dual polarization BST values
+ B := D;
+ -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
+ I := W mod c_mm_user_size;
+ -- range c_nof_packets_max = 1 packet
+ P := rx_packet_cnt mod c_rx_nof_packets;
+
+ -- c_mm_user_size = 2
+ v_exp_data := S * c_mm_user_size;
if g_reverse_word_order = false then
v_exp_data := v_exp_data + I;
else
@@ -558,24 +629,35 @@ begin
-- g_reverse_word_order = TRUE: swaps odd and even W columns, because
-- c_mm_user_size = c_sdp_W_statistic_sz = 2
- W := rx_valid_cnt; -- range c_packet_size = 576
- S := W / c_sdp_W_statistic_sz; -- range c_nof_statistics_per_packet = 288 Statistic values
- D := S / c_nof_complex; -- range c_mm_nof_data = 144 Data values, because
+ -- range c_packet_size = 576
+ W := rx_valid_cnt;
+ -- range c_nof_statistics_per_packet = 288 Statistic values
+ S := W / c_sdp_W_statistic_sz;
+ -- range c_mm_nof_data = 144 Data values, because
+ D := S / c_nof_complex;
-- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_nof_complex
- X := D; -- range c_sdp_X_sq = 144 complex XST values
- I := W mod c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
- P := rx_packet_cnt mod c_rx_nof_packets; -- range c_nof_packets_max = c_nof_used_P_sq * g_nof_crosslets packets
- J := P mod g_nof_crosslets; -- range g_nof_crosslets
- K := P / g_nof_crosslets; -- range c_nof_used_P_sq
-
- v_exp_data := S * c_mm_user_size; -- c_mm_user_size = 2
+ -- range c_sdp_X_sq = 144 complex XST values
+ X := D;
+ -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
+ I := W mod c_mm_user_size;
+ -- range c_nof_packets_max = c_nof_used_P_sq * g_nof_crosslets packets
+ P := rx_packet_cnt mod c_rx_nof_packets;
+ -- range g_nof_crosslets
+ J := P mod g_nof_crosslets;
+ -- range c_nof_used_P_sq
+ K := P / g_nof_crosslets;
+
+ -- c_mm_user_size = 2
+ v_exp_data := S * c_mm_user_size;
if g_reverse_word_order = false then
v_exp_data := v_exp_data + I;
else
v_exp_data := v_exp_data - I + c_mm_user_size-1;
end if;
- v_exp_data := v_exp_data + J * c_packet_size; -- c_packet_size = 576
- v_exp_data := v_exp_data + K * c_mm_Xsq_span; -- c_mm_Xsq_span = 4096
+ -- c_packet_size = 576
+ v_exp_data := v_exp_data + J * c_packet_size;
+ -- c_mm_Xsq_span = 4096
+ v_exp_data := v_exp_data + K * c_mm_Xsq_span;
assert v_exp_data = v_rx_data report "Wrong XST payload data Rx" severity ERROR;
end if;
-- for debug in wave window
@@ -589,7 +671,8 @@ begin
p_dp_end : process
begin
proc_common_wait_until_high(mm_clk, init_ram_done);
- proc_common_wait_some_cycles(dp_clk, g_nof_sync * c_nof_clk_per_sync); -- will show some sync periods
+ -- will show some sync periods
+ proc_common_wait_some_cycles(dp_clk, g_nof_sync * c_nof_clk_per_sync);
tb_end <= '1';
wait;
end process;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
index c325ba9be21b0f986b274e1060af40f0e48548b3..870fc5bfeb3ae09ce7de51746b23b585239f427f 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
@@ -34,7 +34,8 @@ entity tb_tb_sdp_statistics_offload is
end tb_tb_sdp_statistics_offload;
architecture tb of tb_tb_sdp_statistics_offload is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- All
-- g_fast_mm_clk : BOOLEAN := TRUE; -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
@@ -67,8 +68,12 @@ begin
u_xst_P9_N3_no_reverse : entity work.tb_sdp_statistics_offload generic map( true, "XST", 50, false, 1, 3, 0, 0, 16, 9, 3, 1);
u_xst_P9_N3_neg_dir : entity work.tb_sdp_statistics_offload generic map( true, "XST", 50, true, 1, 3, 0, 0, 16, 9, 3, 0);
u_xst_P8_N7_RN1_15 : entity work.tb_sdp_statistics_offload generic map( true, "XST", 50, true, 1, 3, 0, 1, 15, 8, 7, 0);
- u_xst_P1_N7_RN0_7 : entity work.tb_sdp_statistics_offload generic map( true, "XST", 50, true, 3, 3, 0, 0, 8, 1, 7, 1); -- P_sq = 1 < N_rn/2+1 = 5
- u_xst_P9_N7_RN0_7 : entity work.tb_sdp_statistics_offload generic map( true, "XST", 50, true, 3, 3, 0, 0, 8, 9, 7, 1); -- P_sq = 9 > N_rn/2+1 = 5
- u_xst_P9_N4_RN0_7_slow_mm : entity work.tb_sdp_statistics_offload generic map(false, "XST", 50, true, 3, 3, 0, 0, 8, 9, 4, 1); -- P_sq = 9 > N_rn/2+1 = 5
- u_xst_P9_N7_RN0_7_slow_mm : entity work.tb_sdp_statistics_offload generic map(false, "XST", 50, true, 3, 3, 0, 0, 8, 9, 7, 1); -- P_sq = 9 > N_rn/2+1 = 5
+ -- P_sq = 1 < N_rn/2+1 = 5
+ u_xst_P1_N7_RN0_7 : entity work.tb_sdp_statistics_offload generic map( true, "XST", 50, true, 3, 3, 0, 0, 8, 1, 7, 1);
+ -- P_sq = 9 > N_rn/2+1 = 5
+ u_xst_P9_N7_RN0_7 : entity work.tb_sdp_statistics_offload generic map( true, "XST", 50, true, 3, 3, 0, 0, 8, 9, 7, 1);
+ -- P_sq = 9 > N_rn/2+1 = 5
+ u_xst_P9_N4_RN0_7_slow_mm : entity work.tb_sdp_statistics_offload generic map(false, "XST", 50, true, 3, 3, 0, 0, 8, 9, 4, 1);
+ -- P_sq = 9 > N_rn/2+1 = 5
+ u_xst_P9_N7_RN0_7_slow_mm : entity work.tb_sdp_statistics_offload generic map(false, "XST", 50, true, 3, 3, 0, 0, 8, 9, 7, 1);
end tb;
diff --git a/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd b/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd
index ebb8993efb0cc384c2288d53b4d707f9babaffba..f5c2f577a6cd8dbead4a88bc1af83a600ce499f2 100644
--- a/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd
+++ b/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd
@@ -63,7 +63,8 @@ package rdma_demo_pkg is
constant c_rdma_demo_dp_reg_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_rdma_demo_dp_hdr_field_arr, c_word_w));
constant c_rdma_demo_dp_reg_hdr_dat_addr_span : natural := 2**c_rdma_demo_dp_reg_hdr_dat_addr_w;
- constant c_rdma_demo_dp_app_hdr_len : natural := 12; -- octets
+ -- octets
+ constant c_rdma_demo_dp_app_hdr_len : natural := 12;
-- RoCEv2 header for RDMA write operation (excluding ETH, IP, UDP)
-- Base Transport Header (BTH) + RDMA Extended Transport Header (RETH) + Immediate Data
@@ -74,7 +75,8 @@ package rdma_demo_pkg is
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
+ -- depends on BG block size, so set by data path
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ),
( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
@@ -82,11 +84,14 @@ package rdma_demo_pkg is
( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_eth_tester_ip_dst_addr
+ -- c_eth_tester_ip_dst_addr
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ),
( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_eth_tester_udp_dst_port
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
+ -- c_eth_tester_udp_dst_port
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
+ -- depends on BG block size, so set by data path
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ),
( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
( field_name_pad("bth_opcode" ), "RW", 8, field_default(0) ),
@@ -112,8 +117,10 @@ package rdma_demo_pkg is
constant c_rdma_demo_roce_reg_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_rdma_demo_roce_hdr_field_arr, c_word_w));
constant c_rdma_demo_roce_reg_hdr_dat_addr_span : natural := 2**c_rdma_demo_roce_reg_hdr_dat_addr_w;
- constant c_rdma_demo_roce_hdr_len : natural := 32; -- octets
- constant c_rdma_demo_roce_icrc_len : natural := 4; -- octets
+ -- octets
+ constant c_rdma_demo_roce_hdr_len : natural := 32;
+ -- octets
+ constant c_rdma_demo_roce_icrc_len : natural := 4;
end rdma_demo_pkg;
package body rdma_demo_pkg is
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
index 6dd67461421825c623cf4ea6fe6d758361b640e0..e08a4443ce4b3c3148c71d886caa6ed6ae749ee5 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
@@ -28,7 +28,8 @@ use common_lib.common_pkg.all;
package ring_pkg is
function nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : natural) return integer;
- function nof_hops_to_source_rn(hops, this_rn, N_rn : std_logic_vector; lane_dir : natural) return std_logic_vector; -- return vector length is same as hops vector length
+ -- return vector length is same as hops vector length
+ function nof_hops_to_source_rn(hops, this_rn, N_rn : std_logic_vector; lane_dir : natural) return std_logic_vector;
end ring_pkg;
package body ring_pkg is
@@ -37,7 +38,8 @@ package body ring_pkg is
begin
if lane_dir > 0 then
v_source_rn := this_rn - hops;
- if v_source_rn < 0 then -- Cannot use MOD as N_rn is not a constant.
+ -- Cannot use MOD as N_rn is not a constant.
+ if v_source_rn < 0 then
v_source_rn := v_source_rn + N_rn;
end if;
@@ -49,7 +51,8 @@ package body ring_pkg is
end if;
if (v_source_rn < 0) or (v_source_rn > N_rn) then
- v_source_rn := -1; -- return -1 for invalid values. This can happen if nof hops > N_rn.
+ -- return -1 for invalid values. This can happen if nof hops > N_rn.
+ v_source_rn := -1;
end if;
return v_source_rn;
end;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
index 34b1424f815182181ca35334120e421656f29c93..cb3f097b2f6ff47fe24fd6dca458e1da58291a7f 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
@@ -67,19 +67,23 @@ end tb_lofar2_unb2b_ring_bsp;
architecture tb of tb_lofar2_unb2b_ring_bsp is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := "00000000";
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_bck_ref_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644MHz
+ -- 644MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
constant c_pps_period : natural := 1000;
- constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
+ -- use fast tb_clk to speed up M&C
+ constant c_tb_clk_period : time := 100 ps;
constant c_cable_delay : time := 12 ns;
constant c_nof_block_per_sync : natural := 16;
@@ -131,18 +135,27 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- SA_CLK <= not SA_CLK after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ SA_CLK <= not SA_CLK after c_sa_clk_period / 2;
pps_rst <= '0' after c_ext_clk_period * 2;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+ -- pull up
+ pmbus_scl <= 'H';
+ -- pull up
+ pmbus_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -223,9 +236,12 @@ begin
port map (
-- Transceiver PLL reference clock
tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => tr_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => tr_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156,
-- MM interface
mm_rst => pps_rst,
@@ -244,14 +260,16 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
variable v_sp_power_sum_0 : real;
variable v_sp_beamlet_power : real;
variable v_sp_subband_power : real;
- variable v_W, v_T, v_U, v_S, v_B : natural; -- array indicies
+ -- array indicies
+ variable v_W, v_T, v_U, v_S, v_B : natural;
begin
-- Wait for DUT power up after reset
wait for 1 us;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
index d13377d1b35d1ea75891924f3ed24f8a476641eb..fc62f794a0f0d44c52feca7780d5210ce54eb0c1 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
@@ -50,25 +50,37 @@ entity top is
g_design_name : string := "lofar2_unb2b_ring_bsp";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e1sg;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision_id, commit hash (first 9 chars) or number
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision_id, commit hash (first 9 chars) or number
+ g_revision_id : string := "";
g_factory_image : boolean := false;
g_protect_addr_range : boolean := false;
- g_nof_lanes : positive := 8; -- must be in range 1 - 8
- g_nof_rx_monitors : natural := 16; -- max = 16
- g_nof_tx_monitors : natural := 16 -- max = 16
+ -- must be in range 1 - 8
+ g_nof_lanes : positive := 8;
+ -- max = 16
+ g_nof_rx_monitors : natural := 16;
+ -- max = 16
+ g_nof_tx_monitors : natural := 16
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -89,14 +101,16 @@ entity top is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- front transceivers
QSFP_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
QSFP_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ -- Using qsfp bus width also for ring interfaces
+ RING_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
@@ -114,15 +128,19 @@ architecture str of top is
-- QSFP
constant c_nof_qsfp_bus : natural := 1;
- constant c_nof_streams_qsfp : natural := c_unb2b_board_tr_qsfp.bus_w * c_nof_qsfp_bus; -- 4
+ -- 4
+ constant c_nof_streams_qsfp : natural := c_unb2b_board_tr_qsfp.bus_w * c_nof_qsfp_bus;
-- RING
constant c_nof_ring_bus : natural := 2;
- constant c_ring_bus_w : natural := 4; -- Using 4 phisically, there are 12
- constant c_nof_streams_ring : natural := c_ring_bus_w * c_nof_ring_bus; -- c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus; -- 8
+ -- Using 4 phisically, there are 12
+ constant c_ring_bus_w : natural := 4;
+ -- c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus; -- 8
+ constant c_nof_streams_ring : natural := c_ring_bus_w * c_nof_ring_bus;
-- 10GbE
- constant c_max_nof_mac : natural := c_nof_streams_qsfp + c_nof_streams_ring; -- Use the 12 channel 10GbE IP
+ -- Use the 12 channel 10GbE IP
+ constant c_max_nof_mac : natural := c_nof_streams_qsfp + c_nof_streams_ring;
-- Firmware version x.y
constant c_fw_version : t_unb2b_board_fw_version := (1, 1);
@@ -194,12 +212,16 @@ architecture str of top is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -269,7 +291,8 @@ architecture str of top is
signal unb2b_board_front_io_serial_rx_arr : std_logic_vector(c_nof_streams_qsfp - 1 downto 0);
-- RING
- signal i_RING_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0); -- TODO make ring bus array with 4 elements
+ -- TODO make ring bus array with 4 elements
+ signal i_RING_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0);
signal i_RING_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0);
signal unb2b_board_ring_io_serial_tx_arr : std_logic_vector(c_nof_streams_ring - 1 downto 0) := (others => '0');
@@ -303,13 +326,20 @@ architecture str of top is
signal board_kernel_irq_irq : std_logic_vector(0 downto 0);
- signal board_kernel_register_mem_address : std_logic_vector(6 downto 0) := (others => '0'); -- address
- signal board_kernel_register_mem_clken : std_logic := '0'; -- clken
- signal board_kernel_register_mem_chipselect : std_logic := '0'; -- chipselect
- signal board_kernel_register_mem_write : std_logic := '0'; -- write
- signal board_kernel_register_mem_readdata : std_logic_vector(255 downto 0); -- readdata
- signal board_kernel_register_mem_writedata : std_logic_vector(255 downto 0) := (others => '0'); -- writedata
- signal board_kernel_register_mem_byteenable : std_logic_vector(31 downto 0) := (others => '0'); -- byteenable
+ -- address
+ signal board_kernel_register_mem_address : std_logic_vector(6 downto 0) := (others => '0');
+ -- clken
+ signal board_kernel_register_mem_clken : std_logic := '0';
+ -- chipselect
+ signal board_kernel_register_mem_chipselect : std_logic := '0';
+ -- write
+ signal board_kernel_register_mem_write : std_logic := '0';
+ -- readdata
+ signal board_kernel_register_mem_readdata : std_logic_vector(255 downto 0);
+ -- writedata
+ signal board_kernel_register_mem_writedata : std_logic_vector(255 downto 0) := (others => '0');
+ -- byteenable
+ signal board_kernel_register_mem_byteenable : std_logic_vector(31 downto 0) := (others => '0');
signal ta2_unb2b_10GbE_src_out_arr : t_dp_sosi_arr(c_max_nof_mac - 1 downto 0) := (others => c_dp_sosi_rst);
signal ta2_unb2b_10GbE_src_in_arr : t_dp_siso_arr(c_max_nof_mac - 1 downto 0) := (others => c_dp_siso_rst);
@@ -407,7 +437,8 @@ begin
--red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX -- ,
+ -- ,
+ QSFP_TX => i_QSFP_TX
--QSFP_LED => QSFP_LED
);
@@ -422,7 +453,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
@@ -517,7 +549,8 @@ begin
g_use_pll => true
)
port map (
- mm_clk => '0', -- mm_clk,
+ -- mm_clk,
+ mm_clk => '0',
mm_rst => mm_rst,
clk_ref_r => SA_CLK,
@@ -637,7 +670,8 @@ begin
-----------------------------------------------------------------------------
-- kernel clock crossing for tx_monitors
-----------------------------------------------------------------------------
- gen_tx_mon_sim_wires: if g_sim = true generate -- bypass OpenCL kernel in simulation
+ -- bypass OpenCL kernel in simulation
+ gen_tx_mon_sim_wires: if g_sim = true generate
kernel_tx_monitor_sosi_arr <= kernel_to_lane_sosi_arr;
kernel_to_lane_siso_arr <= kernel_tx_monitor_siso_arr;
end generate;
@@ -673,7 +707,8 @@ begin
dp_demux_tx_monitor_sosi_arr <= tx_monitor_sosi_arr;
for I in 0 to g_nof_lanes - 1 loop
- dp_demux_rx_monitor_sosi_arr(I).channel <= nof_hops_to_source_rn(rx_monitor_sosi_arr(I).channel, this_rn_id, sdp_info.N_rn, ((I + 1) mod 2)); -- Use (I+1) MOD 2 to get 1 if I is even and 0 if I is odd
+ -- Use (I+1) MOD 2 to get 1 if I is even and 0 if I is odd
+ dp_demux_rx_monitor_sosi_arr(I).channel <= nof_hops_to_source_rn(rx_monitor_sosi_arr(I).channel, this_rn_id, sdp_info.N_rn, ((I + 1) mod 2));
dp_demux_tx_monitor_sosi_arr(I).channel <= nof_hops_to_source_rn(tx_monitor_sosi_arr(I).channel, this_rn_id, sdp_info.N_rn, ((I + 1) mod 2));
end loop;
end process;
@@ -790,7 +825,8 @@ begin
generic map(
g_nof_streams => g_nof_lanes,
g_use_bg_buffer_ram => true,
- g_buf_dat_w => 32, -- BG is limited to 32 bits data
+ -- BG is limited to 32 bits data
+ g_buf_dat_w => 32,
g_buf_addr_w => 7,
g_file_name_prefix => "data/bf_in_data"
)
@@ -884,18 +920,23 @@ begin
g_mode => 0,
g_nof_input => 2,
g_append_channel_lo => false,
- g_sel_ctrl_invert => true, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ g_sel_ctrl_invert => true,
-- Input FIFO
g_use_fifo => false,
- g_fifo_size => array_init(1024, 2), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, 2) -- must match g_nof_input, even when g_use_fifo=FALSE
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_size => array_init(1024, 2),
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, 2)
)
port map (
rst => st_rst,
clk => st_clk,
-- ST sinks
- snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
- snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
+ -- [c_mux_nof_input-1:0]
+ snk_out_arr => mux_snk_out_2arr_2(I),
+ -- [c_mux_nof_input-1:0]
+ snk_in_arr => mux_snk_in_2arr_2(I),
-- ST source
src_in => to_lane_siso_arr(I),
src_out => to_lane_sosi_arr(I)
@@ -910,8 +951,10 @@ begin
u_sdp_info : entity lofar2_sdp_lib.sdp_info
port map(
-- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst => mm_rst,
+ -- memory-mapped bus clock
+ mm_clk => mm_clk,
dp_clk => st_clk,
dp_rst => st_rst,
@@ -1166,7 +1209,8 @@ begin
);
- i_kernel_rst <= not board_kernel_reset_reset_n; -- qsys output used to reset all OpenCL BSP components
+ -- qsys output used to reset all OpenCL BSP components
+ i_kernel_rst <= not board_kernel_reset_reset_n;
end generate;
gen_sim: if g_sim = true generate
@@ -1187,7 +1231,8 @@ begin
port map(mm_rst, mm_clk, reg_bg_ctrl_mosi, reg_bg_ctrl_miso );
end generate;
- i_reset_n <= not mm_rst; -- First reset OpenCL components in qsys (board)
+ -- First reset OpenCL components in qsys (board)
+ i_reset_n <= not mm_rst;
-- Kernel should start later than BSP. Delaying the reset from the qsys output to form the reset of the OpenCL kernel.
-- This way it is ensured the OpenCL kernel does not start reading/writing data before the components in the OpenCL BSP are ready.
u_common_areset : entity common_lib.common_areset
@@ -1386,7 +1431,8 @@ begin
reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 4 downto 0), -- temp fix
+ -- temp fix
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 4 downto 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -1398,7 +1444,8 @@ begin
pio_system_info_read_export => reg_unb_system_info_mosi.rd,
pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 2 downto 0), -- temp fix
+ -- temp fix
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 2 downto 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
index deca506ed84e4395f8ee499a9cfd70dd56c8925f..26c76aeaa5ce708f627c639f7c155829e9a5db8e 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
@@ -30,232 +30,452 @@ use IEEE.std_logic_1164.all;
package top_components_pkg is
component board is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- kernel_clk_clk : out std_logic; -- clk
- kernel_reset_reset_n : out std_logic; -- reset_n
- kernel_clk2x_clk : out std_logic; -- clk
- kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
- kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
- kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
- kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
- kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
- kernel_cra_address : out std_logic_vector(29 downto 0); -- address
- kernel_cra_write : out std_logic; -- write
- kernel_cra_read : out std_logic; -- read
- kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
- kernel_cra_debugaccess : out std_logic; -- debugaccess
- kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
- kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_rx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_tx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_tx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_tx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_ring_reset_export : out std_logic; -- export
- ram_diag_bg_ring_clk_export : out std_logic; -- export
- ram_diag_bg_ring_address_export : out std_logic_vector(9 downto 0); -- export
- ram_diag_bg_ring_write_export : out std_logic; -- export
- ram_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_ring_read_export : out std_logic; -- export
- ram_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_ring_reset_export : out std_logic; -- export
- reg_diag_bg_ring_clk_export : out std_logic; -- export
- reg_diag_bg_ring_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_ring_write_export : out std_logic; -- export
- reg_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_ring_read_export : out std_logic; -- export
- reg_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_bg_reset_export : out std_logic; -- export
- reg_dp_xonoff_bg_clk_export : out std_logic; -- export
- reg_dp_xonoff_bg_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_xonoff_bg_write_export : out std_logic; -- export
- reg_dp_xonoff_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_bg_read_export : out std_logic; -- export
- reg_dp_xonoff_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_from_lane_reset_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_clk_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_xonoff_from_lane_write_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_from_lane_read_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
- reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- clk
+ kernel_clk_clk : out std_logic;
+ -- reset_n
+ kernel_reset_reset_n : out std_logic;
+ -- clk
+ kernel_clk2x_clk : out std_logic;
+ -- waitrequest
+ kernel_cra_waitrequest : in std_logic := 'X';
+ -- readdata
+ kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X');
+ -- readdatavalid
+ kernel_cra_readdatavalid : in std_logic := 'X';
+ -- burstcount
+ kernel_cra_burstcount : out std_logic_vector(0 downto 0);
+ -- writedata
+ kernel_cra_writedata : out std_logic_vector(63 downto 0);
+ -- address
+ kernel_cra_address : out std_logic_vector(29 downto 0);
+ -- write
+ kernel_cra_write : out std_logic;
+ -- read
+ kernel_cra_read : out std_logic;
+ -- byteenable
+ kernel_cra_byteenable : out std_logic_vector(7 downto 0);
+ -- debugaccess
+ kernel_cra_debugaccess : out std_logic;
+ -- irq
+ kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- reset
+ kernel_interface_sw_reset_in_reset : in std_logic := 'X';
+ -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ reg_bsn_monitor_v2_rx_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_rx_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_tx_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_tx_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_tx_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ reg_bsn_monitor_v2_tx_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_tx_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_bg_ring_reset_export : out std_logic;
+ -- export
+ ram_diag_bg_ring_clk_export : out std_logic;
+ -- export
+ ram_diag_bg_ring_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ ram_diag_bg_ring_write_export : out std_logic;
+ -- export
+ ram_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_bg_ring_read_export : out std_logic;
+ -- export
+ ram_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_scrap_reset_export : out std_logic;
+ -- export
+ ram_scrap_clk_export : out std_logic;
+ -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0);
+ -- export
+ ram_scrap_write_export : out std_logic;
+ -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_scrap_read_export : out std_logic;
+ -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_bg_ring_reset_export : out std_logic;
+ -- export
+ reg_diag_bg_ring_clk_export : out std_logic;
+ -- export
+ reg_diag_bg_ring_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_bg_ring_write_export : out std_logic;
+ -- export
+ reg_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_bg_ring_read_export : out std_logic;
+ -- export
+ reg_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_xonoff_bg_reset_export : out std_logic;
+ -- export
+ reg_dp_xonoff_bg_clk_export : out std_logic;
+ -- export
+ reg_dp_xonoff_bg_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_dp_xonoff_bg_write_export : out std_logic;
+ -- export
+ reg_dp_xonoff_bg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_xonoff_bg_read_export : out std_logic;
+ -- export
+ reg_dp_xonoff_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_xonoff_from_lane_reset_export : out std_logic;
+ -- export
+ reg_dp_xonoff_from_lane_clk_export : out std_logic;
+ -- export
+ reg_dp_xonoff_from_lane_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_dp_xonoff_from_lane_write_export : out std_logic;
+ -- export
+ reg_dp_xonoff_from_lane_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_xonoff_from_lane_read_export : out std_logic;
+ -- export
+ reg_dp_xonoff_from_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_sdp_info_clk_export : out std_logic;
+ -- export
+ reg_sdp_info_read_export : out std_logic;
+ -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_sdp_info_reset_export : out std_logic;
+ -- export
+ reg_sdp_info_write_export : out std_logic;
+ -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ta2_unb2b_mm_io_reset_export : out std_logic;
+ -- export
+ reg_ta2_unb2b_mm_io_clk_export : out std_logic;
+ -- export
+ reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0);
+ -- export
+ reg_ta2_unb2b_mm_io_write_export : out std_logic;
+ -- export
+ reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ta2_unb2b_mm_io_read_export : out std_logic;
+ -- export
+ reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X';
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic;
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0)
);
end component board;
component freeze_wrapper is
port (
- board_kernel_clk_clk : in std_logic; -- input
- board_kernel_clk2x_clk : in std_logic; -- input
- board_kernel_reset_reset_n : in std_logic; -- input
- board_kernel_irq_irq : out std_logic_vector(0 downto 0); -- output [0:0]
- board_kernel_cra_waitrequest : out std_logic; -- output
- board_kernel_cra_readdata : out std_logic_vector(63 downto 0); -- output [63:0]
- board_kernel_cra_readdatavalid : out std_logic; -- output
- board_kernel_cra_burstcount : in std_logic_vector(0 downto 0); -- input [0:0]
- board_kernel_cra_writedata : in std_logic_vector(63 downto 0); -- input [63:0]
- board_kernel_cra_address : in std_logic_vector(29 downto 0); -- input [29:0]
- board_kernel_cra_write : in std_logic; -- input
- board_kernel_cra_read : in std_logic; -- input
- board_kernel_cra_byteenable : in std_logic_vector(7 downto 0); -- input [7:0]
- board_kernel_cra_debugaccess : in std_logic; -- input
-
- board_kernel_register_mem_address : out std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
- board_kernel_register_mem_clken : out std_logic; -- := 'X'; -- clken
- board_kernel_register_mem_chipselect : out std_logic; -- := 'X'; -- chipselect
- board_kernel_register_mem_write : out std_logic; -- := 'X'; -- write
- board_kernel_register_mem_readdata : in std_logic_vector(255 downto 0); -- readdata
- board_kernel_register_mem_writedata : out std_logic_vector(255 downto 0); -- := (others => 'X'); -- writedata
- board_kernel_register_mem_byteenable : out std_logic_vector(31 downto 0); -- := (others => 'X'); -- byteenable
+ -- input
+ board_kernel_clk_clk : in std_logic;
+ -- input
+ board_kernel_clk2x_clk : in std_logic;
+ -- input
+ board_kernel_reset_reset_n : in std_logic;
+ -- output [0:0]
+ board_kernel_irq_irq : out std_logic_vector(0 downto 0);
+ -- output
+ board_kernel_cra_waitrequest : out std_logic;
+ -- output [63:0]
+ board_kernel_cra_readdata : out std_logic_vector(63 downto 0);
+ -- output
+ board_kernel_cra_readdatavalid : out std_logic;
+ -- input [0:0]
+ board_kernel_cra_burstcount : in std_logic_vector(0 downto 0);
+ -- input [63:0]
+ board_kernel_cra_writedata : in std_logic_vector(63 downto 0);
+ -- input [29:0]
+ board_kernel_cra_address : in std_logic_vector(29 downto 0);
+ -- input
+ board_kernel_cra_write : in std_logic;
+ -- input
+ board_kernel_cra_read : in std_logic;
+ -- input [7:0]
+ board_kernel_cra_byteenable : in std_logic_vector(7 downto 0);
+ -- input
+ board_kernel_cra_debugaccess : in std_logic;
+
+ -- := (others => 'X'); -- address
+ board_kernel_register_mem_address : out std_logic_vector(6 downto 0);
+ -- := 'X'; -- clken
+ board_kernel_register_mem_clken : out std_logic;
+ -- := 'X'; -- chipselect
+ board_kernel_register_mem_chipselect : out std_logic;
+ -- := 'X'; -- write
+ board_kernel_register_mem_write : out std_logic;
+ -- readdata
+ board_kernel_register_mem_readdata : in std_logic_vector(255 downto 0);
+ -- := (others => 'X'); -- writedata
+ board_kernel_register_mem_writedata : out std_logic_vector(255 downto 0);
+ -- := (others => 'X'); -- byteenable
+ board_kernel_register_mem_byteenable : out std_logic_vector(31 downto 0);
board_kernel_stream_src_10GbE_ring_0_data : in std_logic_vector(103 downto 0);
board_kernel_stream_src_10GbE_ring_0_valid : in std_logic;
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
index 3af8c3fc2f25ce9d61ac987021c64ef9694a7b2a..456028fa41c24b04211ab05ffbda7a2e8d7a0baa 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
@@ -49,23 +49,32 @@ entity top is
g_design_name : string := "ta2_unb2b_bsp";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e1sg;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision_id, commit hash (first 9 chars) or number
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision_id, commit hash (first 9 chars) or number
+ g_revision_id : string := "";
g_factory_image : boolean := false;
g_protect_addr_range: boolean := false;
g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m_64
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -86,11 +95,14 @@ entity top is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic := '0'; -- Reference clock for MB_I
- MB_II_REF_CLK : in std_logic := '0'; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic := '0';
+ -- Reference clock for MB_II
+ MB_II_REF_CLK : in std_logic := '0';
-- front transceivers
QSFP_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
@@ -106,7 +118,8 @@ entity top is
-- back transceivers
BCK_RX : in std_logic_vector(0 downto 0);
- BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
+ -- Use as JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
-- jesd204b syncronization signals
JESD204B_SYSREF : in std_logic;
@@ -207,12 +220,16 @@ architecture str of top is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- Interface: 1GbE UDP streaming ports
@@ -292,28 +309,45 @@ architecture str of top is
signal board_kernel_irq_irq : std_logic_vector(0 downto 0);
- signal board_kernel_mem0_waitrequest : std_logic; -- readdata
- signal board_kernel_mem0_readdata : std_logic_vector(511 downto 0); -- readdata
- signal board_kernel_mem0_readdatavalid : std_logic; -- readdata
- signal board_kernel_mem0_burstcount : std_logic_vector(4 downto 0); -- := (others => 'X'); -- address
- signal board_kernel_mem0_writedata : std_logic_vector(511 downto 0); -- := (others => 'X'); -- address
- signal board_kernel_mem0_address : std_logic_vector(32 downto 0); -- := (others => 'X'); -- address
- signal board_kernel_mem0_write : std_logic; -- := 'X'; -- write
- signal board_kernel_mem0_read : std_logic; -- := 'X'; -- write
- signal board_kernel_mem0_byteenable : std_logic_vector(63 downto 0); -- := (others => 'X'); -- byteenable
- signal board_kernel_mem0_debugaccess : std_logic; -- := 'X'; -- write
+ -- readdata
+ signal board_kernel_mem0_waitrequest : std_logic;
+ -- readdata
+ signal board_kernel_mem0_readdata : std_logic_vector(511 downto 0);
+ -- readdata
+ signal board_kernel_mem0_readdatavalid : std_logic;
+ -- := (others => 'X'); -- address
+ signal board_kernel_mem0_burstcount : std_logic_vector(4 downto 0);
+ -- := (others => 'X'); -- address
+ signal board_kernel_mem0_writedata : std_logic_vector(511 downto 0);
+ -- := (others => 'X'); -- address
+ signal board_kernel_mem0_address : std_logic_vector(32 downto 0);
+ -- := 'X'; -- write
+ signal board_kernel_mem0_write : std_logic;
+ -- := 'X'; -- write
+ signal board_kernel_mem0_read : std_logic;
+ -- := (others => 'X'); -- byteenable
+ signal board_kernel_mem0_byteenable : std_logic_vector(63 downto 0);
+ -- := 'X'; -- write
+ signal board_kernel_mem0_debugaccess : std_logic;
-- SIGNAL amm_readdata : std_logic_vector(575 downto 0); -- readdata
-- SIGNAL amm_burstcount : std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
-- SIGNAL amm_writedata : std_logic_vector(575 downto 0); -- := (others => 'X'); -- address
-- SIGNAL amm_byteenable : std_logic_vector(71 downto 0); -- := (others => 'X'); -- byteenable
- signal board_kernel_register_mem_address : std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
- signal board_kernel_register_mem_clken : std_logic; -- := 'X'; -- clken
- signal board_kernel_register_mem_chipselect : std_logic; -- := 'X'; -- chipselect
- signal board_kernel_register_mem_write : std_logic; -- := 'X'; -- write
- signal board_kernel_register_mem_readdata : std_logic_vector(255 downto 0); -- readdata
- signal board_kernel_register_mem_writedata : std_logic_vector(255 downto 0); -- := (others => 'X'); -- writedata
- signal board_kernel_register_mem_byteenable : std_logic_vector(31 downto 0); -- := (others => 'X'); -- byteenable
+ -- := (others => 'X'); -- address
+ signal board_kernel_register_mem_address : std_logic_vector(6 downto 0);
+ -- := 'X'; -- clken
+ signal board_kernel_register_mem_clken : std_logic;
+ -- := 'X'; -- chipselect
+ signal board_kernel_register_mem_chipselect : std_logic;
+ -- := 'X'; -- write
+ signal board_kernel_register_mem_write : std_logic;
+ -- readdata
+ signal board_kernel_register_mem_readdata : std_logic_vector(255 downto 0);
+ -- := (others => 'X'); -- writedata
+ signal board_kernel_register_mem_writedata : std_logic_vector(255 downto 0);
+ -- := (others => 'X'); -- byteenable
+ signal board_kernel_register_mem_byteenable : std_logic_vector(31 downto 0);
signal ta2_unb2b_40GbE_src_out_arr : t_dp_sosi_arr(c_nof_40GbE_IP - 1 downto 0);
signal ta2_unb2b_40GbE_src_in_arr : t_dp_siso_arr(c_nof_40GbE_IP - 1 downto 0);
@@ -367,7 +401,8 @@ begin
--red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX -- ,
+ -- ,
+ QSFP_TX => i_QSFP_TX
--QSFP_LED => QSFP_LED
);
@@ -386,7 +421,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_nof_qsfp_bus + c_nof_ring_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
@@ -471,7 +507,8 @@ begin
g_nof_mac => c_nof_10GbE_IP
)
port map (
- mm_clk => '0', -- mm_clk,
+ -- mm_clk,
+ mm_clk => '0',
mm_rst => mm_rst,
clk_ref_r => SA_CLK,
@@ -905,7 +942,8 @@ begin
reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 4 downto 0), -- temp fix
+ -- temp fix
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 4 downto 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -917,7 +955,8 @@ begin
pio_system_info_read_export => reg_unb_system_info_mosi.rd,
pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 2 downto 0), -- temp fix
+ -- temp fix
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 2 downto 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
index fa7090c8ba2cab2ffc8a579323e373cdef3c2eb5..11adba71f42878ba8e96e4261e1de552e3c5dae7 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
@@ -30,230 +30,447 @@ use IEEE.std_logic_1164.all;
package top_components_pkg is
component board is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- kernel_register_mem_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address
- kernel_register_mem_clken : in std_logic := 'X'; -- clken
- kernel_register_mem_chipselect : in std_logic := 'X'; -- chipselect
- kernel_register_mem_write : in std_logic := 'X'; -- write
- kernel_register_mem_readdata : out std_logic_vector(255 downto 0); -- readdata
- kernel_register_mem_writedata : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
- kernel_register_mem_byteenable : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- kernel_clk_clk : out std_logic; -- clk
- kernel_reset_reset_n : out std_logic; -- reset_n
- kernel_clk2x_clk : out std_logic; -- clk
- kernel_mem0_waitrequest : out std_logic; -- waitrequest
- kernel_mem0_readdata : out std_logic_vector(511 downto 0); -- readdata
- kernel_mem0_readdatavalid : out std_logic; -- readdatavalid
- kernel_mem0_burstcount : in std_logic_vector(4 downto 0) := (others => 'X'); -- burstcount
- kernel_mem0_writedata : in std_logic_vector(511 downto 0) := (others => 'X'); -- writedata
- kernel_mem0_address : in std_logic_vector(32 downto 0) := (others => 'X'); -- address
- kernel_mem0_write : in std_logic := 'X'; -- write
- kernel_mem0_read : in std_logic := 'X'; -- read
- kernel_mem0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
- kernel_mem0_debugaccess : in std_logic := 'X'; -- debugaccess
- kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
- kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
- kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
- kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
- kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
- kernel_cra_address : out std_logic_vector(29 downto 0); -- address
- kernel_cra_write : out std_logic; -- write
- kernel_cra_read : out std_logic; -- read
- kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
- kernel_cra_debugaccess : out std_logic; -- debugaccess
- kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
- kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
- ddr4a_pll_ref_clk : in std_logic := 'X'; -- clk
- ddr4a_oct_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- ddr4a_mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- ddr4a_mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- ddr4a_mem_a : out std_logic_vector(16 downto 0); -- mem_a
- ddr4a_mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- ddr4a_mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- ddr4a_mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- ddr4a_mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- ddr4a_mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- ddr4a_mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- ddr4a_mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- ddr4a_mem_par : out std_logic_vector(0 downto 0); -- mem_par
- ddr4a_mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- ddr4a_mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
- ddr4a_mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
- ddr4a_mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
- ddr4a_mem_dbi_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dbi_n
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_jesd204b_address_export : out std_logic_vector(7 downto 0); -- export
- reg_ta2_unb2b_jesd204b_clk_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_read_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ta2_unb2b_jesd204b_reset_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_waitrequest_export : in std_logic := 'X'; -- export
- reg_ta2_unb2b_jesd204b_write_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
- reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- address
+ kernel_register_mem_address : in std_logic_vector(6 downto 0) := (others => 'X');
+ -- clken
+ kernel_register_mem_clken : in std_logic := 'X';
+ -- chipselect
+ kernel_register_mem_chipselect : in std_logic := 'X';
+ -- write
+ kernel_register_mem_write : in std_logic := 'X';
+ -- readdata
+ kernel_register_mem_readdata : out std_logic_vector(255 downto 0);
+ -- writedata
+ kernel_register_mem_writedata : in std_logic_vector(255 downto 0) := (others => 'X');
+ -- byteenable
+ kernel_register_mem_byteenable : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- clk
+ kernel_clk_clk : out std_logic;
+ -- reset_n
+ kernel_reset_reset_n : out std_logic;
+ -- clk
+ kernel_clk2x_clk : out std_logic;
+ -- waitrequest
+ kernel_mem0_waitrequest : out std_logic;
+ -- readdata
+ kernel_mem0_readdata : out std_logic_vector(511 downto 0);
+ -- readdatavalid
+ kernel_mem0_readdatavalid : out std_logic;
+ -- burstcount
+ kernel_mem0_burstcount : in std_logic_vector(4 downto 0) := (others => 'X');
+ -- writedata
+ kernel_mem0_writedata : in std_logic_vector(511 downto 0) := (others => 'X');
+ -- address
+ kernel_mem0_address : in std_logic_vector(32 downto 0) := (others => 'X');
+ -- write
+ kernel_mem0_write : in std_logic := 'X';
+ -- read
+ kernel_mem0_read : in std_logic := 'X';
+ -- byteenable
+ kernel_mem0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X');
+ -- debugaccess
+ kernel_mem0_debugaccess : in std_logic := 'X';
+ -- waitrequest
+ kernel_cra_waitrequest : in std_logic := 'X';
+ -- readdata
+ kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X');
+ -- readdatavalid
+ kernel_cra_readdatavalid : in std_logic := 'X';
+ -- burstcount
+ kernel_cra_burstcount : out std_logic_vector(0 downto 0);
+ -- writedata
+ kernel_cra_writedata : out std_logic_vector(63 downto 0);
+ -- address
+ kernel_cra_address : out std_logic_vector(29 downto 0);
+ -- write
+ kernel_cra_write : out std_logic;
+ -- read
+ kernel_cra_read : out std_logic;
+ -- byteenable
+ kernel_cra_byteenable : out std_logic_vector(7 downto 0);
+ -- debugaccess
+ kernel_cra_debugaccess : out std_logic;
+ -- irq
+ kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- reset
+ kernel_interface_sw_reset_in_reset : in std_logic := 'X';
+ -- clk
+ ddr4a_pll_ref_clk : in std_logic := 'X';
+ -- oct_rzqin
+ ddr4a_oct_oct_rzqin : in std_logic := 'X';
+ -- mem_ck
+ ddr4a_mem_ck : out std_logic_vector(1 downto 0);
+ -- mem_ck_n
+ ddr4a_mem_ck_n : out std_logic_vector(1 downto 0);
+ -- mem_a
+ ddr4a_mem_a : out std_logic_vector(16 downto 0);
+ -- mem_act_n
+ ddr4a_mem_act_n : out std_logic_vector(0 downto 0);
+ -- mem_ba
+ ddr4a_mem_ba : out std_logic_vector(1 downto 0);
+ -- mem_bg
+ ddr4a_mem_bg : out std_logic_vector(1 downto 0);
+ -- mem_cke
+ ddr4a_mem_cke : out std_logic_vector(1 downto 0);
+ -- mem_cs_n
+ ddr4a_mem_cs_n : out std_logic_vector(1 downto 0);
+ -- mem_odt
+ ddr4a_mem_odt : out std_logic_vector(1 downto 0);
+ -- mem_reset_n
+ ddr4a_mem_reset_n : out std_logic_vector(0 downto 0);
+ -- mem_par
+ ddr4a_mem_par : out std_logic_vector(0 downto 0);
+ -- mem_alert_n
+ ddr4a_mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- mem_dqs
+ ddr4a_mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X');
+ -- mem_dqs_n
+ ddr4a_mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X');
+ -- mem_dq
+ ddr4a_mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X');
+ -- mem_dbi_n
+ ddr4a_mem_dbi_n : inout std_logic_vector(7 downto 0) := (others => 'X');
+ -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ta2_unb2b_jesd204b_address_export : out std_logic_vector(7 downto 0);
+ -- export
+ reg_ta2_unb2b_jesd204b_clk_export : out std_logic;
+ -- export
+ reg_ta2_unb2b_jesd204b_read_export : out std_logic;
+ -- export
+ reg_ta2_unb2b_jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_ta2_unb2b_jesd204b_reset_export : out std_logic;
+ -- export
+ reg_ta2_unb2b_jesd204b_waitrequest_export : in std_logic := 'X';
+ -- export
+ reg_ta2_unb2b_jesd204b_write_export : out std_logic;
+ -- export
+ reg_ta2_unb2b_jesd204b_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ta2_unb2b_mm_io_reset_export : out std_logic;
+ -- export
+ reg_ta2_unb2b_mm_io_clk_export : out std_logic;
+ -- export
+ reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0);
+ -- export
+ reg_ta2_unb2b_mm_io_write_export : out std_logic;
+ -- export
+ reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_ta2_unb2b_mm_io_read_export : out std_logic;
+ -- export
+ reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X';
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic;
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0)
);
end component board;
component freeze_wrapper is
port (
- board_kernel_clk_clk : in std_logic; -- input
- board_kernel_clk2x_clk : in std_logic; -- input
- board_kernel_reset_reset_n : in std_logic; -- input
- board_kernel_irq_irq : out std_logic_vector(0 downto 0); -- output [0:0]
- board_kernel_cra_waitrequest : out std_logic; -- output
- board_kernel_cra_readdata : out std_logic_vector(63 downto 0); -- output [63:0]
- board_kernel_cra_readdatavalid : out std_logic; -- output
- board_kernel_cra_burstcount : in std_logic_vector(0 downto 0); -- input [0:0]
- board_kernel_cra_writedata : in std_logic_vector(63 downto 0); -- input [63:0]
- board_kernel_cra_address : in std_logic_vector(29 downto 0); -- input [29:0]
- board_kernel_cra_write : in std_logic; -- input
- board_kernel_cra_read : in std_logic; -- input
- board_kernel_cra_byteenable : in std_logic_vector(7 downto 0); -- input [7:0]
- board_kernel_cra_debugaccess : in std_logic; -- input
+ -- input
+ board_kernel_clk_clk : in std_logic;
+ -- input
+ board_kernel_clk2x_clk : in std_logic;
+ -- input
+ board_kernel_reset_reset_n : in std_logic;
+ -- output [0:0]
+ board_kernel_irq_irq : out std_logic_vector(0 downto 0);
+ -- output
+ board_kernel_cra_waitrequest : out std_logic;
+ -- output [63:0]
+ board_kernel_cra_readdata : out std_logic_vector(63 downto 0);
+ -- output
+ board_kernel_cra_readdatavalid : out std_logic;
+ -- input [0:0]
+ board_kernel_cra_burstcount : in std_logic_vector(0 downto 0);
+ -- input [63:0]
+ board_kernel_cra_writedata : in std_logic_vector(63 downto 0);
+ -- input [29:0]
+ board_kernel_cra_address : in std_logic_vector(29 downto 0);
+ -- input
+ board_kernel_cra_write : in std_logic;
+ -- input
+ board_kernel_cra_read : in std_logic;
+ -- input [7:0]
+ board_kernel_cra_byteenable : in std_logic_vector(7 downto 0);
+ -- input
+ board_kernel_cra_debugaccess : in std_logic;
- board_kernel_mem0_waitrequest : in std_logic; -- readdata
- board_kernel_mem0_readdata : in std_logic_vector(511 downto 0); -- readdata
- board_kernel_mem0_readdatavalid : in std_logic; -- readdata
- board_kernel_mem0_burstcount : out std_logic_vector(4 downto 0); -- := (others => 'X'); -- address
- board_kernel_mem0_writedata : out std_logic_vector(511 downto 0); -- := (others => 'X'); -- address
- board_kernel_mem0_address : out std_logic_vector(32 downto 0); -- := (others => 'X'); -- address
- board_kernel_mem0_write : out std_logic; -- := 'X'; -- write
- board_kernel_mem0_read : out std_logic; -- := 'X'; -- write
- board_kernel_mem0_byteenable : out std_logic_vector(63 downto 0); -- := (others => 'X'); -- byteenable
- board_kernel_mem0_debugaccess : out std_logic; -- := 'X'; -- write
+ -- readdata
+ board_kernel_mem0_waitrequest : in std_logic;
+ -- readdata
+ board_kernel_mem0_readdata : in std_logic_vector(511 downto 0);
+ -- readdata
+ board_kernel_mem0_readdatavalid : in std_logic;
+ -- := (others => 'X'); -- address
+ board_kernel_mem0_burstcount : out std_logic_vector(4 downto 0);
+ -- := (others => 'X'); -- address
+ board_kernel_mem0_writedata : out std_logic_vector(511 downto 0);
+ -- := (others => 'X'); -- address
+ board_kernel_mem0_address : out std_logic_vector(32 downto 0);
+ -- := 'X'; -- write
+ board_kernel_mem0_write : out std_logic;
+ -- := 'X'; -- write
+ board_kernel_mem0_read : out std_logic;
+ -- := (others => 'X'); -- byteenable
+ board_kernel_mem0_byteenable : out std_logic_vector(63 downto 0);
+ -- := 'X'; -- write
+ board_kernel_mem0_debugaccess : out std_logic;
- board_kernel_register_mem_address : out std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
- board_kernel_register_mem_clken : out std_logic; -- := 'X'; -- clken
- board_kernel_register_mem_chipselect : out std_logic; -- := 'X'; -- chipselect
- board_kernel_register_mem_write : out std_logic; -- := 'X'; -- write
- board_kernel_register_mem_readdata : in std_logic_vector(255 downto 0); -- readdata
- board_kernel_register_mem_writedata : out std_logic_vector(255 downto 0); -- := (others => 'X'); -- writedata
- board_kernel_register_mem_byteenable : out std_logic_vector(31 downto 0); -- := (others => 'X'); -- byteenable
+ -- := (others => 'X'); -- address
+ board_kernel_register_mem_address : out std_logic_vector(6 downto 0);
+ -- := 'X'; -- clken
+ board_kernel_register_mem_clken : out std_logic;
+ -- := 'X'; -- chipselect
+ board_kernel_register_mem_chipselect : out std_logic;
+ -- := 'X'; -- write
+ board_kernel_register_mem_write : out std_logic;
+ -- readdata
+ board_kernel_register_mem_readdata : in std_logic_vector(255 downto 0);
+ -- := (others => 'X'); -- writedata
+ board_kernel_register_mem_writedata : out std_logic_vector(255 downto 0);
+ -- := (others => 'X'); -- byteenable
+ board_kernel_register_mem_byteenable : out std_logic_vector(31 downto 0);
board_kernel_stream_src_40GbE_data : in std_logic_vector(263 downto 0);
board_kernel_stream_src_40GbE_valid : in std_logic;
diff --git a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
index 931a44d84138702620f0ed221b2c0a8252067b5c..50387c6fd8fa508426d13ba1231ed12fd219ee97 100644
--- a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
+++ b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
@@ -69,7 +69,8 @@ use technology_lib.technology_pkg.all;
entity ta2_channel_cross is
generic (
g_nof_streams : natural;
- g_nof_bytes : positive; -- nof bytes in payload field, Max = 32
+ -- nof bytes in payload field, Max = 32
+ g_nof_bytes : positive;
g_reverse_bytes : boolean := true;
g_fifo_size : natural := 8;
g_use_err : boolean := false;
@@ -89,7 +90,8 @@ entity ta2_channel_cross is
dp_snk_out_arr : out t_dp_siso_arr(g_nof_streams - 1 downto 0);
dp_snk_in_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
- kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
+ -- Kernel clock (runs the kernel_* I/O below)
+ kernel_clk : in std_logic;
kernel_reset : in std_logic;
kernel_src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0);
@@ -248,7 +250,8 @@ begin
dp_latency_adapter_rx_snk_in_arr(stream).sync <= kernel_snk_in_arr(stream).data(c_sync_offset) when g_use_sync else '0';
dp_latency_adapter_rx_snk_in_arr(stream).empty(c_empty_w - 1 downto 0) <= kernel_snk_in_arr(stream).data(c_empty_high - 1 downto c_empty_high - c_empty_w);
dp_latency_adapter_rx_snk_in_arr(stream).valid <= kernel_snk_in_arr(stream).valid;
- kernel_snk_out_arr(stream).ready <= dp_latency_adapter_rx_snk_out_arr(stream).ready; -- Flow control towards source
+ -- Flow control towards source
+ kernel_snk_out_arr(stream).ready <= dp_latency_adapter_rx_snk_out_arr(stream).ready;
kernel_snk_out_arr(stream).xon <= dp_latency_adapter_rx_snk_out_arr(stream).xon;
----------------------------------------------------------------------------
diff --git a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
index be705c1148968cb8f78a3d0045ceaec9f8fe07a8..17ffabf9d898c288cf79bdd4ee7454750c73ebf7 100644
--- a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
@@ -63,24 +63,30 @@ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
entity ta2_unb2b_10GbE is
generic (
- g_nof_mac : natural; -- Valid inputs are 1, 3, 4, 12, 24, 48
+ -- Valid inputs are 1, 3, 4, 12, 24, 48
+ g_nof_mac : natural;
g_use_err : boolean := false;
g_err_w : positive := 32;
g_use_pll : boolean := true
);
port (
- mm_clk : in std_logic; -- 100MHz clk for reconfig block and status interface
+ -- 100MHz clk for reconfig block and status interface
+ mm_clk : in std_logic;
mm_rst : in std_logic;
- clk_ref_r : in std_logic; -- 644.53125MHz 10G MAC reference clock
+ -- 644.53125MHz 10G MAC reference clock
+ clk_ref_r : in std_logic;
clk_156 : in std_logic := '0';
clk_312 : in std_logic := '0';
rst_156 : in std_logic := '0';
- tx_serial_r : out std_logic_vector(g_nof_mac - 1 downto 0); -- Serial TX lanes towards QSFP cage
- rx_serial_r : in std_logic_vector(g_nof_mac - 1 downto 0); -- Serial RX lanes from QSFP cage
+ -- Serial TX lanes towards QSFP cage
+ tx_serial_r : out std_logic_vector(g_nof_mac - 1 downto 0);
+ -- Serial RX lanes from QSFP cage
+ rx_serial_r : in std_logic_vector(g_nof_mac - 1 downto 0);
- kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
+ -- Kernel clock (runs the kernel_* I/O below)
+ kernel_clk : in std_logic;
kernel_reset : in std_logic;
src_out_arr : out t_dp_sosi_arr(g_nof_mac - 1 downto 0);
@@ -94,9 +100,11 @@ end ta2_unb2b_10GbE;
architecture str of ta2_unb2b_10GbE is
constant c_sim : boolean := false;
- constant c_tx_fifo_fill : natural := 1125; -- Largest frame is 9000 bytes = 1125
+ -- Largest frame is 9000 bytes = 1125
+ constant c_tx_fifo_fill : natural := 1125;
constant c_tx_fifo_size : natural := 2048;
- constant c_rx_fifo_size : natural := 256; -- should be large enough
+ -- should be large enough
+ constant c_rx_fifo_size : natural := 256;
signal tr_ref_clk_312 : std_logic;
signal tr_ref_clk_156 : std_logic;
@@ -206,8 +214,10 @@ begin
dp_latency_adapter_tx_snk_in_arr(mac).eop <= snk_in_arr(mac).data(65);
dp_latency_adapter_tx_snk_in_arr(mac).empty(2 downto 0) <= snk_in_arr(mac).data(71 downto 69);
dp_latency_adapter_tx_snk_in_arr(mac).valid <= snk_in_arr(mac).valid;
- snk_out_arr(mac).ready <= dp_latency_adapter_tx_snk_out_arr(mac).ready; -- Flow control towards source (kernel)
- snk_out_arr(mac).xon <= dp_xonoff_src_in_arr(mac).xon; -- use xonoff_src_in for status as xonoff_snk_out is always '1'
+ -- Flow control towards source (kernel)
+ snk_out_arr(mac).ready <= dp_latency_adapter_tx_snk_out_arr(mac).ready;
+ -- use xonoff_src_in for status as xonoff_snk_out is always '1'
+ snk_out_arr(mac).xon <= dp_xonoff_src_in_arr(mac).xon;
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
@@ -340,27 +350,34 @@ begin
generic map (
g_technology => c_tech_arria10_e1sg,
g_sim => c_sim,
- g_sim_level => 1, -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level => 1,
g_nof_channels => g_nof_mac,
g_direction => "TX_RX",
g_pre_header_padding => false
)
port map (
-- Transceiver PLL reference clock
- tr_ref_clk_644 => eth_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
- tr_ref_clk_312 => eth_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => eth_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => eth_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 => eth_ref_clk_644,
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => eth_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => eth_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => eth_ref_rst_156,
-- MM
mm_clk => '0',
mm_rst => '0',
-- ST
- tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr, -- 64 bit data @ 156 MHz
+ -- 64 bit data @ 156 MHz
+ tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr,
tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr,
- rx_src_out_arr => mac_10g_src_out_arr, -- 64 bit data @ 156 MHz
+ -- 64 bit data @ 156 MHz
+ rx_src_out_arr => mac_10g_src_out_arr,
rx_src_in_arr => mac_10g_src_in_arr,
-- PHY serial IO
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
index cd1da9699604da0e661e12c8a19e9b5af176e786..c5c7172dce6202d5007d38a9b83dfa85685297ab 100644
--- a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
@@ -61,7 +61,8 @@ entity ta2_unb2b_1GbE is
udp_rx_sosi : in t_dp_sosi;
udp_rx_siso : out t_dp_siso;
- kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
+ -- Kernel clock (runs the kernel_* I/O below)
+ kernel_clk : in std_logic;
kernel_reset : in std_logic;
src_out : out t_dp_sosi;
@@ -74,8 +75,10 @@ end ta2_unb2b_1GbE;
architecture str of ta2_unb2b_1GbE is
constant c_sim : boolean := false;
constant c_empty_w : natural := 2;
- constant c_tx_fifo_size : natural := 10; -- Can be small as flow control is enabled
- constant c_rx_fifo_size : natural := 10; -- Can be small as flow control is enabled
+ -- Can be small as flow control is enabled
+ constant c_tx_fifo_size : natural := 10;
+ -- Can be small as flow control is enabled
+ constant c_rx_fifo_size : natural := 10;
signal dp_latency_adapter_tx_src_out : t_dp_sosi;
signal dp_latency_adapter_tx_src_in : t_dp_siso;
@@ -110,7 +113,8 @@ begin
dp_latency_adapter_tx_snk_in.empty(1 downto 0) <= snk_in.data(39 downto 38);
dp_latency_adapter_tx_snk_in.valid <= snk_in.valid;
- snk_out.ready <= dp_latency_adapter_tx_snk_out.ready; -- Flow control towards source (kernel)
+ -- Flow control towards source (kernel)
+ snk_out.ready <= dp_latency_adapter_tx_snk_out.ready;
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
index 1083a6bc1589f0b8464b7266b90955fc2250ec08..81223be847a79d50c4cbe3ebad79ac676e08aeca 100644
--- a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
@@ -48,16 +48,23 @@ entity ta2_unb2b_1GbE_ip_wrapper is
udp_rx_siso_ready : out std_logic;
udp_rx_siso_xon : out std_logic;
- kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
+ -- Kernel clock (runs the kernel_* I/O below)
+ kernel_clk : in std_logic;
kernel_reset : in std_logic;
- kernel_src_data : out std_logic_vector(39 downto 0); -- RX Data to kernel
- kernel_src_valid : out std_logic; -- RX data valid signal to kernel
- kernel_src_ready : in std_logic; -- Flow control from kernel
-
- kernel_snk_data : in std_logic_vector(39 downto 0); -- TX Data from kernel
- kernel_snk_valid : in std_logic; -- TX data valid signal from kernel
- kernel_snk_ready : out std_logic -- Flow control towards kernel
+ -- RX Data to kernel
+ kernel_src_data : out std_logic_vector(39 downto 0);
+ -- RX data valid signal to kernel
+ kernel_src_valid : out std_logic;
+ -- Flow control from kernel
+ kernel_src_ready : in std_logic;
+
+ -- TX Data from kernel
+ kernel_snk_data : in std_logic_vector(39 downto 0);
+ -- TX data valid signal from kernel
+ kernel_snk_valid : in std_logic;
+ -- Flow control towards kernel
+ kernel_snk_ready : out std_logic
);
end ta2_unb2b_1GbE_ip_wrapper;
@@ -87,16 +94,23 @@ architecture str of ta2_unb2b_1GbE_ip_wrapper is
udp_rx_siso_ready : out std_logic;
udp_rx_siso_xon : out std_logic;
- kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
+ -- Kernel clock (runs the kernel_* I/O below)
+ kernel_clk : in std_logic;
kernel_reset : in std_logic;
- kernel_src_data : out std_logic_vector(39 downto 0); -- RX Data to kernel
- kernel_src_valid : out std_logic; -- RX data valid signal to kernel
- kernel_src_ready : in std_logic; -- Flow control from kernel
-
- kernel_snk_data : in std_logic_vector(39 downto 0); -- TX Data from kernel
- kernel_snk_valid : in std_logic; -- TX data valid signal from kernel
- kernel_snk_ready : out std_logic -- Flow control towards kernel
+ -- RX Data to kernel
+ kernel_src_data : out std_logic_vector(39 downto 0);
+ -- RX data valid signal to kernel
+ kernel_src_valid : out std_logic;
+ -- Flow control from kernel
+ kernel_src_ready : in std_logic;
+
+ -- TX Data from kernel
+ kernel_snk_data : in std_logic_vector(39 downto 0);
+ -- TX data valid signal from kernel
+ kernel_snk_valid : in std_logic;
+ -- Flow control towards kernel
+ kernel_snk_ready : out std_logic
);
end component ta2_unb2b_1GbE;
begin
diff --git a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
index 44b951b237f233c191c40d984a4b9a66e3091ff4..f0c17afc675b78b84acefa55a337f41b25483f2f 100644
--- a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
@@ -60,15 +60,20 @@ entity ta2_unb2b_40GbE is
g_nof_mac : natural := 1
);
port (
- mm_clk : in std_logic; -- 100MHz clk for reconfig block and status interface
+ -- 100MHz clk for reconfig block and status interface
+ mm_clk : in std_logic;
mm_rst : in std_logic;
- clk_ref_r : in std_logic; -- 644.53125MHz 40G MAC reference clock
+ -- 644.53125MHz 40G MAC reference clock
+ clk_ref_r : in std_logic;
- tx_serial_r : out std_logic_vector(4 * g_nof_mac - 1 downto 0); -- Serial TX lanes towards QSFP cage
- rx_serial_r : in std_logic_vector(4 * g_nof_mac - 1 downto 0); -- Serial RX lanes from QSFP cage
+ -- Serial TX lanes towards QSFP cage
+ tx_serial_r : out std_logic_vector(4 * g_nof_mac - 1 downto 0);
+ -- Serial RX lanes from QSFP cage
+ rx_serial_r : in std_logic_vector(4 * g_nof_mac - 1 downto 0);
- kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
+ -- Kernel clock (runs the kernel_* I/O below)
+ kernel_clk : in std_logic;
kernel_reset : in std_logic;
src_out_arr : out t_dp_sosi_arr(g_nof_mac - 1 downto 0);
@@ -80,10 +85,13 @@ entity ta2_unb2b_40GbE is
end ta2_unb2b_40GbE;
architecture str of ta2_unb2b_40GbE is
- constant c_max_packet_size : natural := 128; -- 128 * 256 bits words
- constant c_tx_fifo_fill : natural := 282; -- Largest frame is 9000 bytes = 1125
+ -- 128 * 256 bits words
+ constant c_max_packet_size : natural := 128;
+ -- Largest frame is 9000 bytes = 1125
+ constant c_tx_fifo_fill : natural := 282;
constant c_tx_fifo_size : natural := 512;
- constant c_rx_fifo_size : natural := 64; -- should be large enough
+ -- should be large enough
+ constant c_rx_fifo_size : natural := 64;
constant c_data_w : natural := 256;
----------------------------------------------------------------------------
@@ -134,8 +142,10 @@ architecture str of ta2_unb2b_40GbE is
signal rx_pcs_ready_arr : std_logic_vector(g_nof_mac - 1 downto 0);
- signal clk_txmac_arr : std_logic_vector(g_nof_mac - 1 downto 0); -- MAC + PCS clock - at least 312.5Mhz
- signal clk_rxmac_arr : std_logic_vector(g_nof_mac - 1 downto 0); -- MAC + PCS clock - at least 312.5Mhz
+ -- MAC + PCS clock - at least 312.5Mhz
+ signal clk_txmac_arr : std_logic_vector(g_nof_mac - 1 downto 0);
+ -- MAC + PCS clock - at least 312.5Mhz
+ signal clk_rxmac_arr : std_logic_vector(g_nof_mac - 1 downto 0);
signal l4_tx_sosi_arr : t_dp_sosi_arr(g_nof_mac - 1 downto 0);
signal l4_tx_siso_arr : t_dp_siso_arr(g_nof_mac - 1 downto 0);
@@ -153,11 +163,16 @@ architecture str of ta2_unb2b_40GbE is
----------------------------------------------------------------------------
component arria10_40g_atx_pll is
port (
- pll_cal_busy : out std_logic; -- pll_cal_busy
- pll_locked : out std_logic; -- pll_locked
- pll_powerdown : in std_logic := 'X'; -- pll_powerdown
- pll_refclk0 : in std_logic := 'X'; -- clk
- tx_serial_clk : out std_logic -- clk
+ -- pll_cal_busy
+ pll_cal_busy : out std_logic;
+ -- pll_locked
+ pll_locked : out std_logic;
+ -- pll_powerdown
+ pll_powerdown : in std_logic := 'X';
+ -- clk
+ pll_refclk0 : in std_logic := 'X';
+ -- clk
+ tx_serial_clk : out std_logic
);
end component arria10_40g_atx_pll;
@@ -166,103 +181,200 @@ architecture str of ta2_unb2b_40GbE is
----------------------------------------------------------------------------
component arria10_40g_mac is
port (
- l4_rx_error : out std_logic_vector(5 downto 0); -- l4_rx_error
- l4_rx_status : out std_logic_vector(2 downto 0); -- l4_rx_status
- l4_rx_valid : out std_logic; -- l4_rx_valid
- l4_rx_startofpacket : out std_logic; -- l4_rx_startofpacket
- l4_rx_endofpacket : out std_logic; -- l4_rx_endofpacket
- l4_rx_data : out std_logic_vector(255 downto 0); -- l4_rx_data
- l4_rx_empty : out std_logic_vector(4 downto 0); -- l4_rx_empty
- l4_rx_fcs_error : out std_logic; -- l4_rx_fcs_error
- l4_rx_fcs_valid : out std_logic; -- l4_rx_fcs_valid
- l4_tx_startofpacket : in std_logic := 'X'; -- l4_tx_startofpacket
- l4_tx_endofpacket : in std_logic := 'X'; -- l4_tx_endofpacket
- l4_tx_valid : in std_logic := 'X'; -- l4_tx_valid
- l4_tx_ready : out std_logic; -- l4_tx_ready
- l4_tx_empty : in std_logic_vector(4 downto 0) := (others => 'X'); -- l4_tx_empty
- l4_tx_data : in std_logic_vector(255 downto 0) := (others => 'X'); -- l4_tx_data
- l4_tx_error : in std_logic := 'X'; -- l4_tx_error
- clk_ref : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk_ref
- clk_rxmac : out std_logic_vector(0 downto 0); -- clk_rxmac
- clk_status : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk_status
- clk_txmac : out std_logic_vector(0 downto 0); -- clk_txmac
- reconfig_address : in std_logic_vector(11 downto 0) := (others => 'X'); -- reconfig_address
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_clk
- reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_read
- reconfig_readdata : out std_logic_vector(31 downto 0); -- reconfig_readdata
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_reset
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- reconfig_waitrequest
- reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_write
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- reconfig_writedata
- reset_async : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset_async
- reset_status : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset_status
- rx_pcs_ready : out std_logic_vector(0 downto 0); -- rx_pcs_ready
- rx_serial : in std_logic_vector(3 downto 0) := (others => 'X'); -- rx_serial
- rx_inc_octetsOK : out std_logic_vector(15 downto 0); -- rx_inc_octetsOK
- rx_inc_octetsOK_valid : out std_logic_vector(0 downto 0); -- rx_inc_octetsOK_valid
- rx_inc_runt : out std_logic_vector(0 downto 0); -- rx_inc_runt
- rx_inc_64 : out std_logic_vector(0 downto 0); -- rx_inc_64
- rx_inc_127 : out std_logic_vector(0 downto 0); -- rx_inc_127
- rx_inc_255 : out std_logic_vector(0 downto 0); -- rx_inc_255
- rx_inc_511 : out std_logic_vector(0 downto 0); -- rx_inc_511
- rx_inc_1023 : out std_logic_vector(0 downto 0); -- rx_inc_1023
- rx_inc_1518 : out std_logic_vector(0 downto 0); -- rx_inc_1518
- rx_inc_max : out std_logic_vector(0 downto 0); -- rx_inc_max
- rx_inc_over : out std_logic_vector(0 downto 0); -- rx_inc_over
- rx_inc_mcast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_mcast_data_err
- rx_inc_mcast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_mcast_data_ok
- rx_inc_bcast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_bcast_data_err
- rx_inc_bcast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_bcast_data_ok
- rx_inc_ucast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_ucast_data_err
- rx_inc_ucast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_ucast_data_ok
- rx_inc_mcast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_mcast_ctrl
- rx_inc_bcast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_bcast_ctrl
- rx_inc_ucast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_ucast_ctrl
- rx_inc_pause : out std_logic_vector(0 downto 0); -- rx_inc_pause
- rx_inc_fcs_err : out std_logic_vector(0 downto 0); -- rx_inc_fcs_err
- rx_inc_fragment : out std_logic_vector(0 downto 0); -- rx_inc_fragment
- rx_inc_jabber : out std_logic_vector(0 downto 0); -- rx_inc_jabber
- rx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0); -- rx_inc_sizeok_fcserr
- rx_inc_pause_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_pause_ctrl_err
- rx_inc_mcast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_mcast_ctrl_err
- rx_inc_bcast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_bcast_ctrl_err
- rx_inc_ucast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_ucast_ctrl_err
- status_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- status_write
- status_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- status_read
- status_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- status_addr
- status_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- status_writedata
- status_readdata : out std_logic_vector(31 downto 0); -- status_readdata
- status_readdata_valid : out std_logic_vector(0 downto 0); -- status_readdata_valid
- status_waitrequest : out std_logic_vector(0 downto 0); -- status_waitrequest
- status_read_timeout : out std_logic_vector(0 downto 0); -- status_read_timeout
- tx_lanes_stable : out std_logic_vector(0 downto 0); -- tx_lanes_stable
- tx_pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_pll_locked
- tx_serial : out std_logic_vector(3 downto 0); -- tx_serial
- tx_serial_clk : in std_logic_vector(3 downto 0) := (others => 'X'); -- tx_serial_clk
- tx_inc_octetsOK : out std_logic_vector(15 downto 0); -- tx_inc_octetsOK
- tx_inc_octetsOK_valid : out std_logic_vector(0 downto 0); -- tx_inc_octetsOK_valid
- tx_inc_64 : out std_logic_vector(0 downto 0); -- tx_inc_64
- tx_inc_127 : out std_logic_vector(0 downto 0); -- tx_inc_127
- tx_inc_255 : out std_logic_vector(0 downto 0); -- tx_inc_255
- tx_inc_511 : out std_logic_vector(0 downto 0); -- tx_inc_511
- tx_inc_1023 : out std_logic_vector(0 downto 0); -- tx_inc_1023
- tx_inc_1518 : out std_logic_vector(0 downto 0); -- tx_inc_1518
- tx_inc_max : out std_logic_vector(0 downto 0); -- tx_inc_max
- tx_inc_over : out std_logic_vector(0 downto 0); -- tx_inc_over
- tx_inc_mcast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_mcast_data_err
- tx_inc_mcast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_mcast_data_ok
- tx_inc_bcast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_bcast_data_err
- tx_inc_bcast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_bcast_data_ok
- tx_inc_ucast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_ucast_data_err
- tx_inc_ucast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_ucast_data_ok
- tx_inc_mcast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_mcast_ctrl
- tx_inc_bcast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_bcast_ctrl
- tx_inc_ucast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_ucast_ctrl
- tx_inc_pause : out std_logic_vector(0 downto 0); -- tx_inc_pause
- tx_inc_fcs_err : out std_logic_vector(0 downto 0); -- tx_inc_fcs_err
- tx_inc_fragment : out std_logic_vector(0 downto 0); -- tx_inc_fragment
- tx_inc_jabber : out std_logic_vector(0 downto 0); -- tx_inc_jabber
- tx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0) -- tx_inc_sizeok_fcserr
+ -- l4_rx_error
+ l4_rx_error : out std_logic_vector(5 downto 0);
+ -- l4_rx_status
+ l4_rx_status : out std_logic_vector(2 downto 0);
+ -- l4_rx_valid
+ l4_rx_valid : out std_logic;
+ -- l4_rx_startofpacket
+ l4_rx_startofpacket : out std_logic;
+ -- l4_rx_endofpacket
+ l4_rx_endofpacket : out std_logic;
+ -- l4_rx_data
+ l4_rx_data : out std_logic_vector(255 downto 0);
+ -- l4_rx_empty
+ l4_rx_empty : out std_logic_vector(4 downto 0);
+ -- l4_rx_fcs_error
+ l4_rx_fcs_error : out std_logic;
+ -- l4_rx_fcs_valid
+ l4_rx_fcs_valid : out std_logic;
+ -- l4_tx_startofpacket
+ l4_tx_startofpacket : in std_logic := 'X';
+ -- l4_tx_endofpacket
+ l4_tx_endofpacket : in std_logic := 'X';
+ -- l4_tx_valid
+ l4_tx_valid : in std_logic := 'X';
+ -- l4_tx_ready
+ l4_tx_ready : out std_logic;
+ -- l4_tx_empty
+ l4_tx_empty : in std_logic_vector(4 downto 0) := (others => 'X');
+ -- l4_tx_data
+ l4_tx_data : in std_logic_vector(255 downto 0) := (others => 'X');
+ -- l4_tx_error
+ l4_tx_error : in std_logic := 'X';
+ -- clk_ref
+ clk_ref : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- clk_rxmac
+ clk_rxmac : out std_logic_vector(0 downto 0);
+ -- clk_status
+ clk_status : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- clk_txmac
+ clk_txmac : out std_logic_vector(0 downto 0);
+ -- reconfig_address
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => 'X');
+ -- reconfig_clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- reconfig_read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- reconfig_readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- reconfig_reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- reconfig_waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- reconfig_writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- reset_async
+ reset_async : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- reset_status
+ reset_status : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_pcs_ready
+ rx_pcs_ready : out std_logic_vector(0 downto 0);
+ -- rx_serial
+ rx_serial : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- rx_inc_octetsOK
+ rx_inc_octetsOK : out std_logic_vector(15 downto 0);
+ -- rx_inc_octetsOK_valid
+ rx_inc_octetsOK_valid : out std_logic_vector(0 downto 0);
+ -- rx_inc_runt
+ rx_inc_runt : out std_logic_vector(0 downto 0);
+ -- rx_inc_64
+ rx_inc_64 : out std_logic_vector(0 downto 0);
+ -- rx_inc_127
+ rx_inc_127 : out std_logic_vector(0 downto 0);
+ -- rx_inc_255
+ rx_inc_255 : out std_logic_vector(0 downto 0);
+ -- rx_inc_511
+ rx_inc_511 : out std_logic_vector(0 downto 0);
+ -- rx_inc_1023
+ rx_inc_1023 : out std_logic_vector(0 downto 0);
+ -- rx_inc_1518
+ rx_inc_1518 : out std_logic_vector(0 downto 0);
+ -- rx_inc_max
+ rx_inc_max : out std_logic_vector(0 downto 0);
+ -- rx_inc_over
+ rx_inc_over : out std_logic_vector(0 downto 0);
+ -- rx_inc_mcast_data_err
+ rx_inc_mcast_data_err : out std_logic_vector(0 downto 0);
+ -- rx_inc_mcast_data_ok
+ rx_inc_mcast_data_ok : out std_logic_vector(0 downto 0);
+ -- rx_inc_bcast_data_err
+ rx_inc_bcast_data_err : out std_logic_vector(0 downto 0);
+ -- rx_inc_bcast_data_ok
+ rx_inc_bcast_data_ok : out std_logic_vector(0 downto 0);
+ -- rx_inc_ucast_data_err
+ rx_inc_ucast_data_err : out std_logic_vector(0 downto 0);
+ -- rx_inc_ucast_data_ok
+ rx_inc_ucast_data_ok : out std_logic_vector(0 downto 0);
+ -- rx_inc_mcast_ctrl
+ rx_inc_mcast_ctrl : out std_logic_vector(0 downto 0);
+ -- rx_inc_bcast_ctrl
+ rx_inc_bcast_ctrl : out std_logic_vector(0 downto 0);
+ -- rx_inc_ucast_ctrl
+ rx_inc_ucast_ctrl : out std_logic_vector(0 downto 0);
+ -- rx_inc_pause
+ rx_inc_pause : out std_logic_vector(0 downto 0);
+ -- rx_inc_fcs_err
+ rx_inc_fcs_err : out std_logic_vector(0 downto 0);
+ -- rx_inc_fragment
+ rx_inc_fragment : out std_logic_vector(0 downto 0);
+ -- rx_inc_jabber
+ rx_inc_jabber : out std_logic_vector(0 downto 0);
+ -- rx_inc_sizeok_fcserr
+ rx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0);
+ -- rx_inc_pause_ctrl_err
+ rx_inc_pause_ctrl_err : out std_logic_vector(0 downto 0);
+ -- rx_inc_mcast_ctrl_err
+ rx_inc_mcast_ctrl_err : out std_logic_vector(0 downto 0);
+ -- rx_inc_bcast_ctrl_err
+ rx_inc_bcast_ctrl_err : out std_logic_vector(0 downto 0);
+ -- rx_inc_ucast_ctrl_err
+ rx_inc_ucast_ctrl_err : out std_logic_vector(0 downto 0);
+ -- status_write
+ status_write : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- status_read
+ status_read : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- status_addr
+ status_addr : in std_logic_vector(15 downto 0) := (others => 'X');
+ -- status_writedata
+ status_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- status_readdata
+ status_readdata : out std_logic_vector(31 downto 0);
+ -- status_readdata_valid
+ status_readdata_valid : out std_logic_vector(0 downto 0);
+ -- status_waitrequest
+ status_waitrequest : out std_logic_vector(0 downto 0);
+ -- status_read_timeout
+ status_read_timeout : out std_logic_vector(0 downto 0);
+ -- tx_lanes_stable
+ tx_lanes_stable : out std_logic_vector(0 downto 0);
+ -- tx_pll_locked
+ tx_pll_locked : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- tx_serial
+ tx_serial : out std_logic_vector(3 downto 0);
+ -- tx_serial_clk
+ tx_serial_clk : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- tx_inc_octetsOK
+ tx_inc_octetsOK : out std_logic_vector(15 downto 0);
+ -- tx_inc_octetsOK_valid
+ tx_inc_octetsOK_valid : out std_logic_vector(0 downto 0);
+ -- tx_inc_64
+ tx_inc_64 : out std_logic_vector(0 downto 0);
+ -- tx_inc_127
+ tx_inc_127 : out std_logic_vector(0 downto 0);
+ -- tx_inc_255
+ tx_inc_255 : out std_logic_vector(0 downto 0);
+ -- tx_inc_511
+ tx_inc_511 : out std_logic_vector(0 downto 0);
+ -- tx_inc_1023
+ tx_inc_1023 : out std_logic_vector(0 downto 0);
+ -- tx_inc_1518
+ tx_inc_1518 : out std_logic_vector(0 downto 0);
+ -- tx_inc_max
+ tx_inc_max : out std_logic_vector(0 downto 0);
+ -- tx_inc_over
+ tx_inc_over : out std_logic_vector(0 downto 0);
+ -- tx_inc_mcast_data_err
+ tx_inc_mcast_data_err : out std_logic_vector(0 downto 0);
+ -- tx_inc_mcast_data_ok
+ tx_inc_mcast_data_ok : out std_logic_vector(0 downto 0);
+ -- tx_inc_bcast_data_err
+ tx_inc_bcast_data_err : out std_logic_vector(0 downto 0);
+ -- tx_inc_bcast_data_ok
+ tx_inc_bcast_data_ok : out std_logic_vector(0 downto 0);
+ -- tx_inc_ucast_data_err
+ tx_inc_ucast_data_err : out std_logic_vector(0 downto 0);
+ -- tx_inc_ucast_data_ok
+ tx_inc_ucast_data_ok : out std_logic_vector(0 downto 0);
+ -- tx_inc_mcast_ctrl
+ tx_inc_mcast_ctrl : out std_logic_vector(0 downto 0);
+ -- tx_inc_bcast_ctrl
+ tx_inc_bcast_ctrl : out std_logic_vector(0 downto 0);
+ -- tx_inc_ucast_ctrl
+ tx_inc_ucast_ctrl : out std_logic_vector(0 downto 0);
+ -- tx_inc_pause
+ tx_inc_pause : out std_logic_vector(0 downto 0);
+ -- tx_inc_fcs_err
+ tx_inc_fcs_err : out std_logic_vector(0 downto 0);
+ -- tx_inc_fragment
+ tx_inc_fragment : out std_logic_vector(0 downto 0);
+ -- tx_inc_jabber
+ tx_inc_jabber : out std_logic_vector(0 downto 0);
+ -- tx_inc_sizeok_fcserr
+ tx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0)
);
end component arria10_40g_mac;
begin
@@ -280,7 +392,8 @@ begin
dp_latency_adapter_tx_a_snk_in_arr(mac).eop <= snk_in_arr(mac).data(257);
dp_latency_adapter_tx_a_snk_in_arr(mac).empty(4 downto 0) <= snk_in_arr(mac).data(263 downto 259);
dp_latency_adapter_tx_a_snk_in_arr(mac).valid <= snk_in_arr(mac).valid;
- snk_out_arr(mac).ready <= dp_latency_adapter_tx_a_snk_out_arr(mac).ready; -- Flow control towards source (kernel)
+ -- Flow control towards source (kernel)
+ snk_out_arr(mac).ready <= dp_latency_adapter_tx_a_snk_out_arr(mac).ready;
snk_out_arr(mac).xon <= rx_pcs_ready_arr(mac);
----------------------------------------------------------------------------
@@ -314,7 +427,8 @@ begin
in_siso => dp_latency_adapter_tx_a_src_in_arr(mac),
out_sosi => dp_xonoff_src_out_arr(mac),
- out_siso => dp_xonoff_src_in_arr(mac) -- flush control via out_siso.xon
+ -- flush control via out_siso.xon
+ out_siso => dp_xonoff_src_in_arr(mac)
);
----------------------------------------------------------------------------
@@ -375,8 +489,10 @@ begin
u_arria10_40g_mac : arria10_40g_mac
port map (
reset_async(0) => mm_rst,
- clk_txmac(0) => clk_txmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
- clk_rxmac(0) => clk_rxmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
+ -- MAC + PCS clock - at least 312.5Mhz
+ clk_txmac(0) => clk_txmac_arr(mac),
+ -- MAC + PCS clock - at least 312.5Mhz
+ clk_rxmac(0) => clk_rxmac_arr(mac),
clk_ref(0) => clk_ref_r,
rx_pcs_ready(0) => rx_pcs_ready_arr(mac),
diff --git a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
index 4e29874e8d21f7e36ed70ea57ab2fdc582c7b927..c90995a4bb54a7252cc1236349306fbb39842234 100644
--- a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
+++ b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
@@ -41,36 +41,58 @@ use tech_ddr_lib.tech_ddr_component_pkg.all;
entity ta2_unb2b_ddr is
generic (
-- IO_DDR
- g_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
+ -- DDR4 has no master or slave, so no need to check number of MB
+ g_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_8g_1600m;
g_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_8g_1600m;
g_use_MB_I : boolean := true;
g_use_MB_II : boolean := true
);
port (
- kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
+ -- Kernel clock (runs the kernel_* I/O below)
+ kernel_clk : in std_logic;
kernel_reset : in std_logic;
- mem0_waitrequest : out std_logic; -- waitrequest
- mem0_readdata : out std_logic_vector(511 downto 0); -- readdata
- mem0_readdatavalid : out std_logic; -- readdatavalid
- mem0_burstcount : in std_logic_vector(4 downto 0) := (others => 'X'); -- burstcount
- mem0_writedata : in std_logic_vector(511 downto 0) := (others => 'X'); -- writedata
- mem0_address : in std_logic_vector(32 downto 0) := (others => 'X'); -- address
- mem0_write : in std_logic := 'X'; -- write
- mem0_read : in std_logic := 'X'; -- read
- mem0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
- mem0_debugaccess : in std_logic := 'X'; -- debugacce
-
- mem1_waitrequest : out std_logic; -- waitrequest
- mem1_readdata : out std_logic_vector(511 downto 0); -- readdata
- mem1_readdatavalid : out std_logic; -- readdatavalid
- mem1_burstcount : in std_logic_vector(4 downto 0) := (others => 'X'); -- burstcount
- mem1_writedata : in std_logic_vector(511 downto 0) := (others => 'X'); -- writedata
- mem1_address : in std_logic_vector(32 downto 0) := (others => 'X'); -- address
- mem1_write : in std_logic := 'X'; -- write
- mem1_read : in std_logic := 'X'; -- read
- mem1_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
- mem1_debugaccess : in std_logic := 'X'; -- debugacce
+ -- waitrequest
+ mem0_waitrequest : out std_logic;
+ -- readdata
+ mem0_readdata : out std_logic_vector(511 downto 0);
+ -- readdatavalid
+ mem0_readdatavalid : out std_logic;
+ -- burstcount
+ mem0_burstcount : in std_logic_vector(4 downto 0) := (others => 'X');
+ -- writedata
+ mem0_writedata : in std_logic_vector(511 downto 0) := (others => 'X');
+ -- address
+ mem0_address : in std_logic_vector(32 downto 0) := (others => 'X');
+ -- write
+ mem0_write : in std_logic := 'X';
+ -- read
+ mem0_read : in std_logic := 'X';
+ -- byteenable
+ mem0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X');
+ -- debugacce
+ mem0_debugaccess : in std_logic := 'X';
+
+ -- waitrequest
+ mem1_waitrequest : out std_logic;
+ -- readdata
+ mem1_readdata : out std_logic_vector(511 downto 0);
+ -- readdatavalid
+ mem1_readdatavalid : out std_logic;
+ -- burstcount
+ mem1_burstcount : in std_logic_vector(4 downto 0) := (others => 'X');
+ -- writedata
+ mem1_writedata : in std_logic_vector(511 downto 0) := (others => 'X');
+ -- address
+ mem1_address : in std_logic_vector(32 downto 0) := (others => 'X');
+ -- write
+ mem1_write : in std_logic := 'X';
+ -- read
+ mem1_read : in std_logic := 'X';
+ -- byteenable
+ mem1_byteenable : in std_logic_vector(63 downto 0) := (others => 'X');
+ -- debugacce
+ mem1_debugaccess : in std_logic := 'X';
mb_I_ref_clk : in std_logic := '0';
mb_I_ref_rst : in std_logic := '1';
@@ -93,12 +115,14 @@ end ta2_unb2b_ddr;
architecture str of ta2_unb2b_ddr is
constant c_gigabytes_MB_I : natural := func_tech_ddr_module_size(g_ddr_MB_I);
constant c_mb_I_ctlr_address_w : natural := func_tech_ddr_ctlr_address_w(g_ddr_MB_I);
- constant c_mb_I_ctlr_data_w : natural := 576; -- func_tech_ddr_ctlr_data_w(g_ddr_MB_I);
+ -- func_tech_ddr_ctlr_data_w(g_ddr_MB_I);
+ constant c_mb_I_ctlr_data_w : natural := 576;
constant c_mb_I_ctlr_byteenable_w : natural := 72;
constant c_gigabytes_MB_II : natural := func_tech_ddr_module_size(g_ddr_MB_II);
constant c_mb_II_ctlr_address_w : natural := func_tech_ddr_ctlr_address_w(g_ddr_MB_II);
- constant c_mb_II_ctlr_data_w : natural := 576; -- func_tech_ddr_ctlr_data_w(g_ddr_MB_II);
+ -- func_tech_ddr_ctlr_data_w(g_ddr_MB_II);
+ constant c_mb_II_ctlr_data_w : natural := 576;
constant c_mb_II_ctlr_byteenable_w : natural := 72;
constant c_data_w : natural := 512;
@@ -204,28 +228,50 @@ architecture str of ta2_unb2b_ddr is
SYNC_RESET : integer := 0
);
port (
- clk : in std_logic := 'X'; -- clk
- m0_waitrequest : in std_logic := 'X'; -- waitrequest
- m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- readdata
- m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
- m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0); -- burstcount
- m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- writedata
- m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0); -- address
- m0_write : out std_logic; -- write
- m0_read : out std_logic; -- read
- m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
- m0_debugaccess : out std_logic; -- debugaccess
- reset : in std_logic := 'X'; -- reset
- s0_waitrequest : out std_logic; -- waitrequest
- s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- readdata
- s0_readdatavalid : out std_logic; -- readdatavalid
- s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X'); -- burstcount
- s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- writedata
- s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X'); -- address
- s0_write : in std_logic := 'X'; -- write
- s0_read : in std_logic := 'X'; -- read
- s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
- s0_debugaccess : in std_logic := 'X' -- debugaccess
+ -- clk
+ clk : in std_logic := 'X';
+ -- waitrequest
+ m0_waitrequest : in std_logic := 'X';
+ -- readdata
+ m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X');
+ -- readdatavalid
+ m0_readdatavalid : in std_logic := 'X';
+ -- burstcount
+ m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0);
+ -- writedata
+ m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0);
+ -- address
+ m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0);
+ -- write
+ m0_write : out std_logic;
+ -- read
+ m0_read : out std_logic;
+ -- byteenable
+ m0_byteenable : out std_logic_vector(63 downto 0);
+ -- debugaccess
+ m0_debugaccess : out std_logic;
+ -- reset
+ reset : in std_logic := 'X';
+ -- waitrequest
+ s0_waitrequest : out std_logic;
+ -- readdata
+ s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0);
+ -- readdatavalid
+ s0_readdatavalid : out std_logic;
+ -- burstcount
+ s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X');
+ -- writedata
+ s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X');
+ -- address
+ s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X');
+ -- write
+ s0_write : in std_logic := 'X';
+ -- read
+ s0_read : in std_logic := 'X';
+ -- byteenable
+ s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X');
+ -- debugaccess
+ s0_debugaccess : in std_logic := 'X'
);
end component ta2_unb2b_ddr_pipe_stage;
@@ -242,30 +288,54 @@ architecture str of ta2_unb2b_ddr is
SLAVE_SYNC_DEPTH : integer := 2
);
port (
- m0_waitrequest : in std_logic := 'X'; -- waitrequest
- m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- readdata
- m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
- m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0); -- burstcount
- m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- writedata
- m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0); -- address
- m0_write : out std_logic; -- write
- m0_read : out std_logic; -- read
- m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
- m0_debugaccess : out std_logic; -- debugaccess
- m0_clk : in std_logic := 'X'; -- clk
- m0_reset : in std_logic := 'X'; -- reset
- s0_waitrequest : out std_logic; -- waitrequest
- s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- readdata
- s0_readdatavalid : out std_logic; -- readdatavalid
- s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X'); -- burstcount
- s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- writedata
- s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X'); -- address
- s0_write : in std_logic := 'X'; -- write
- s0_read : in std_logic := 'X'; -- read
- s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
- s0_debugaccess : in std_logic := 'X'; -- debugaccess
- s0_clk : in std_logic := 'X'; -- clk
- s0_reset : in std_logic := 'X' -- reset
+ -- waitrequest
+ m0_waitrequest : in std_logic := 'X';
+ -- readdata
+ m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X');
+ -- readdatavalid
+ m0_readdatavalid : in std_logic := 'X';
+ -- burstcount
+ m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0);
+ -- writedata
+ m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0);
+ -- address
+ m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0);
+ -- write
+ m0_write : out std_logic;
+ -- read
+ m0_read : out std_logic;
+ -- byteenable
+ m0_byteenable : out std_logic_vector(63 downto 0);
+ -- debugaccess
+ m0_debugaccess : out std_logic;
+ -- clk
+ m0_clk : in std_logic := 'X';
+ -- reset
+ m0_reset : in std_logic := 'X';
+ -- waitrequest
+ s0_waitrequest : out std_logic;
+ -- readdata
+ s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0);
+ -- readdatavalid
+ s0_readdatavalid : out std_logic;
+ -- burstcount
+ s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X');
+ -- writedata
+ s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X');
+ -- address
+ s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X');
+ -- write
+ s0_write : in std_logic := 'X';
+ -- read
+ s0_read : in std_logic := 'X';
+ -- byteenable
+ s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X');
+ -- debugaccess
+ s0_debugaccess : in std_logic := 'X';
+ -- clk
+ s0_clk : in std_logic := 'X';
+ -- reset
+ s0_reset : in std_logic := 'X'
);
end component ta2_unb2b_ddr_clock_cross;
begin
@@ -319,7 +389,8 @@ begin
SYNC_RESET => c_sync_reset
)
port map (
- clk => mb_I_emif_usr_clk, -- clk.clk
+ -- clk.clk
+ clk => mb_I_emif_usr_clk,
m0_waitrequest => mb_I_pipe_stage_m0_waitrequest,
m0_readdata => mb_I_pipe_stage_m0_readdata,
m0_readdatavalid => mb_I_pipe_stage_m0_readdatavalid,
@@ -330,17 +401,28 @@ begin
m0_read => mb_I_pipe_stage_m0_read,
m0_byteenable => mb_I_pipe_stage_m0_byteenable,
m0_debugaccess => mb_I_pipe_stage_m0_debugaccess,
- reset => mb_I_emif_usr_reset, -- reset.reset
- s0_waitrequest => mb_I_pipe_stage_s0_waitrequest, -- s0.waitrequest
- s0_readdata => mb_I_pipe_stage_s0_readdata, -- .readdata
- s0_readdatavalid => mb_I_pipe_stage_s0_readdatavalid, -- .readdatavalid
- s0_burstcount => mb_I_pipe_stage_s0_burstcount, -- .burstcount
- s0_writedata => mb_I_pipe_stage_s0_writedata, -- .writedata
- s0_address => mb_I_pipe_stage_s0_address, -- .address
- s0_write => mb_I_pipe_stage_s0_write, -- .write
- s0_read => mb_I_pipe_stage_s0_read, -- .read
- s0_byteenable => mb_I_pipe_stage_s0_byteenable, -- .byteenable
- s0_debugaccess => mb_I_pipe_stage_s0_debugaccess -- .debugaccess
+ -- reset.reset
+ reset => mb_I_emif_usr_reset,
+ -- s0.waitrequest
+ s0_waitrequest => mb_I_pipe_stage_s0_waitrequest,
+ -- .readdata
+ s0_readdata => mb_I_pipe_stage_s0_readdata,
+ -- .readdatavalid
+ s0_readdatavalid => mb_I_pipe_stage_s0_readdatavalid,
+ -- .burstcount
+ s0_burstcount => mb_I_pipe_stage_s0_burstcount,
+ -- .writedata
+ s0_writedata => mb_I_pipe_stage_s0_writedata,
+ -- .address
+ s0_address => mb_I_pipe_stage_s0_address,
+ -- .write
+ s0_write => mb_I_pipe_stage_s0_write,
+ -- .read
+ s0_read => mb_I_pipe_stage_s0_read,
+ -- .byteenable
+ s0_byteenable => mb_I_pipe_stage_s0_byteenable,
+ -- .debugaccess
+ s0_debugaccess => mb_I_pipe_stage_s0_debugaccess
);
mb_I_pipe_stage_m0_waitrequest <= not mb_I_amm_ready_0;
@@ -360,38 +442,70 @@ begin
gen_I_ip_arria10_e1sg_ddr4_8g_1600 : if g_ddr_MB_I.name = "DDR4" and c_gigabytes_MB_I = 8 and g_ddr_MB_I.mts = 1600 generate
u_ip_arria10_e1sg_ddr4_8g_1600 : ip_arria10_e1sg_ddr4_8g_1600
port map (
- amm_ready_0 => mb_I_amm_ready_0, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => mb_I_amm_read_0, -- .read
- amm_write_0 => mb_I_amm_write_0, -- .write
- amm_address_0 => mb_I_amm_address_0, -- .address
- amm_readdata_0 => mb_I_amm_readdata_0, -- .readdata
- amm_writedata_0 => mb_I_amm_writedata_0, -- .writedata
- amm_burstcount_0 => mb_I_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => mb_I_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => mb_I_amm_readdatavalid_0, -- .readdatavalid
- emif_usr_clk => mb_I_emif_usr_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => mb_I_emif_usr_reset_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => mb_I_ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => mb_I_ou.ck(g_ddr_MB_I.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => mb_I_ou.ck_n(g_ddr_MB_I.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => mb_I_ou.a(g_ddr_MB_I.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => mb_I_ou.act_n, -- .mem_act_n
- mem_ba => mb_I_ou.ba(g_ddr_MB_I.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => mb_I_ou.bg(g_ddr_MB_I.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => mb_I_ou.cke(g_ddr_MB_I.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => mb_I_ou.cs_n(g_ddr_MB_I.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => mb_I_ou.odt(g_ddr_MB_I.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => mb_I_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => mb_I_ou.par, -- .mem_par
- mem_alert_n => slv(mb_I_in.alert_n), -- .mem_alert_n
- mem_dqs => mb_I_io.dqs(g_ddr_MB_I.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => mb_I_io.dqs_n(g_ddr_MB_I.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => mb_I_io.dq(g_ddr_MB_I.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => mb_I_io.dbi_n(g_ddr_MB_I.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => mb_I_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => mb_I_ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => OPEN, -- status_conduit_end.local_cal_success
- local_cal_fail => open -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => mb_I_amm_ready_0,
+ -- .read
+ amm_read_0 => mb_I_amm_read_0,
+ -- .write
+ amm_write_0 => mb_I_amm_write_0,
+ -- .address
+ amm_address_0 => mb_I_amm_address_0,
+ -- .readdata
+ amm_readdata_0 => mb_I_amm_readdata_0,
+ -- .writedata
+ amm_writedata_0 => mb_I_amm_writedata_0,
+ -- .burstcount
+ amm_burstcount_0 => mb_I_amm_burstcount_0,
+ -- .byteenable
+ amm_byteenable_0 => mb_I_amm_byteenable_0,
+ -- .readdatavalid
+ amm_readdatavalid_0 => mb_I_amm_readdatavalid_0,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => mb_I_emif_usr_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => mb_I_emif_usr_reset_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => mb_I_ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => mb_I_ou.ck(g_ddr_MB_I.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => mb_I_ou.ck_n(g_ddr_MB_I.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => mb_I_ou.a(g_ddr_MB_I.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => mb_I_ou.act_n,
+ -- .mem_ba
+ mem_ba => mb_I_ou.ba(g_ddr_MB_I.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => mb_I_ou.bg(g_ddr_MB_I.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => mb_I_ou.cke(g_ddr_MB_I.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => mb_I_ou.cs_n(g_ddr_MB_I.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => mb_I_ou.odt(g_ddr_MB_I.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => mb_I_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => mb_I_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(mb_I_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => mb_I_io.dqs(g_ddr_MB_I.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => mb_I_io.dqs_n(g_ddr_MB_I.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => mb_I_io.dq(g_ddr_MB_I.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => mb_I_io.dbi_n(g_ddr_MB_I.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => mb_I_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => mb_I_ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => OPEN,
+ -- .local_cal_fail
+ local_cal_fail => open
);
end generate;
@@ -447,7 +561,8 @@ begin
SYNC_RESET => c_sync_reset
)
port map (
- clk => mb_II_emif_usr_clk, -- clk.clk
+ -- clk.clk
+ clk => mb_II_emif_usr_clk,
m0_waitrequest => mb_II_pipe_stage_m0_waitrequest,
m0_readdata => mb_II_pipe_stage_m0_readdata,
m0_readdatavalid => mb_II_pipe_stage_m0_readdatavalid,
@@ -458,17 +573,28 @@ begin
m0_read => mb_II_pipe_stage_m0_read,
m0_byteenable => mb_II_pipe_stage_m0_byteenable,
m0_debugaccess => mb_II_pipe_stage_m0_debugaccess,
- reset => mb_II_emif_usr_reset, -- reset.reset
- s0_waitrequest => mb_II_pipe_stage_s0_waitrequest, -- s0.waitrequest
- s0_readdata => mb_II_pipe_stage_s0_readdata, -- .readdata
- s0_readdatavalid => mb_II_pipe_stage_s0_readdatavalid, -- .readdatavalid
- s0_burstcount => mb_II_pipe_stage_s0_burstcount, -- .burstcount
- s0_writedata => mb_II_pipe_stage_s0_writedata, -- .writedata
- s0_address => mb_II_pipe_stage_s0_address, -- .address
- s0_write => mb_II_pipe_stage_s0_write, -- .write
- s0_read => mb_II_pipe_stage_s0_read, -- .read
- s0_byteenable => mb_II_pipe_stage_s0_byteenable, -- .byteenable
- s0_debugaccess => mb_II_pipe_stage_s0_debugaccess -- .debugaccess
+ -- reset.reset
+ reset => mb_II_emif_usr_reset,
+ -- s0.waitrequest
+ s0_waitrequest => mb_II_pipe_stage_s0_waitrequest,
+ -- .readdata
+ s0_readdata => mb_II_pipe_stage_s0_readdata,
+ -- .readdatavalid
+ s0_readdatavalid => mb_II_pipe_stage_s0_readdatavalid,
+ -- .burstcount
+ s0_burstcount => mb_II_pipe_stage_s0_burstcount,
+ -- .writedata
+ s0_writedata => mb_II_pipe_stage_s0_writedata,
+ -- .address
+ s0_address => mb_II_pipe_stage_s0_address,
+ -- .write
+ s0_write => mb_II_pipe_stage_s0_write,
+ -- .read
+ s0_read => mb_II_pipe_stage_s0_read,
+ -- .byteenable
+ s0_byteenable => mb_II_pipe_stage_s0_byteenable,
+ -- .debugaccess
+ s0_debugaccess => mb_II_pipe_stage_s0_debugaccess
);
mb_II_pipe_stage_m0_waitrequest <= not mb_II_amm_ready_0;
@@ -488,38 +614,70 @@ begin
gen_II_ip_arria10_e1sg_ddr4_8g_1600 : if g_ddr_MB_II.name = "DDR4" and c_gigabytes_MB_II = 8 and g_ddr_MB_II.mts = 1600 generate
u_ip_arria10_e1sg_ddr4_8g_1600 : ip_arria10_e1sg_ddr4_8g_1600
port map (
- amm_ready_0 => mb_II_amm_ready_0, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => mb_II_amm_read_0, -- .read
- amm_write_0 => mb_II_amm_write_0, -- .write
- amm_address_0 => mb_II_amm_address_0, -- .address
- amm_readdata_0 => mb_II_amm_readdata_0, -- .readdata
- amm_writedata_0 => mb_II_amm_writedata_0, -- .writedata
- amm_burstcount_0 => mb_II_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => mb_II_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => mb_II_amm_readdatavalid_0, -- .readdatavalid
- emif_usr_clk => mb_II_emif_usr_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => mb_II_emif_usr_reset_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => mb_II_ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => mb_II_ou.ck(g_ddr_MB_II.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => mb_II_ou.ck_n(g_ddr_MB_II.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => mb_II_ou.a(g_ddr_MB_II.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => mb_II_ou.act_n, -- .mem_act_n
- mem_ba => mb_II_ou.ba(g_ddr_MB_II.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => mb_II_ou.bg(g_ddr_MB_II.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => mb_II_ou.cke(g_ddr_MB_II.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => mb_II_ou.cs_n(g_ddr_MB_II.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => mb_II_ou.odt(g_ddr_MB_II.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => mb_II_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => mb_II_ou.par, -- .mem_par
- mem_alert_n => slv(mb_II_in.alert_n), -- .mem_alert_n
- mem_dqs => mb_II_io.dqs(g_ddr_MB_II.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => mb_II_io.dqs_n(g_ddr_MB_II.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => mb_II_io.dq(g_ddr_MB_II.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => mb_II_io.dbi_n(g_ddr_MB_II.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => mb_II_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => mb_II_ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => OPEN, -- status_conduit_end.local_cal_success
- local_cal_fail => open -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => mb_II_amm_ready_0,
+ -- .read
+ amm_read_0 => mb_II_amm_read_0,
+ -- .write
+ amm_write_0 => mb_II_amm_write_0,
+ -- .address
+ amm_address_0 => mb_II_amm_address_0,
+ -- .readdata
+ amm_readdata_0 => mb_II_amm_readdata_0,
+ -- .writedata
+ amm_writedata_0 => mb_II_amm_writedata_0,
+ -- .burstcount
+ amm_burstcount_0 => mb_II_amm_burstcount_0,
+ -- .byteenable
+ amm_byteenable_0 => mb_II_amm_byteenable_0,
+ -- .readdatavalid
+ amm_readdatavalid_0 => mb_II_amm_readdatavalid_0,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => mb_II_emif_usr_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => mb_II_emif_usr_reset_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => mb_II_ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => mb_II_ou.ck(g_ddr_MB_II.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => mb_II_ou.ck_n(g_ddr_MB_II.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => mb_II_ou.a(g_ddr_MB_II.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => mb_II_ou.act_n,
+ -- .mem_ba
+ mem_ba => mb_II_ou.ba(g_ddr_MB_II.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => mb_II_ou.bg(g_ddr_MB_II.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => mb_II_ou.cke(g_ddr_MB_II.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => mb_II_ou.cs_n(g_ddr_MB_II.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => mb_II_ou.odt(g_ddr_MB_II.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => mb_II_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => mb_II_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(mb_II_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => mb_II_io.dqs(g_ddr_MB_II.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => mb_II_io.dqs_n(g_ddr_MB_II.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => mb_II_io.dq(g_ddr_MB_II.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => mb_II_io.dbi_n(g_ddr_MB_II.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => mb_II_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => mb_II_ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => OPEN,
+ -- .local_cal_fail
+ local_cal_fail => open
);
end generate;
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
index c5d1073de0edb6f9d4e164f6c0f7834f51b5a02d..0e42fcb245e56848ffc23572959afc66c2eddf04 100644
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
@@ -51,10 +51,12 @@ use common_lib.common_interface_layers_pkg.all;
entity ta2_unb2b_jesd204b is
generic (
- g_nof_streams : natural := 12 -- can be 1-12
+ -- can be 1-12
+ g_nof_streams : natural := 12
);
port (
- mm_clk : in std_logic; -- 100MHz clk for reconfig block and status interface
+ -- 100MHz clk for reconfig block and status interface
+ mm_clk : in std_logic;
mm_rst : in std_logic;
-- MM Control
@@ -62,13 +64,17 @@ entity ta2_unb2b_jesd204b is
jesd204b_miso : out t_mem_miso;
-- JESD204B external signals
- jesd204b_refclk : in std_logic := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
- jesd204b_sysref : in std_logic := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : out std_logic_vector(g_nof_streams - 1 downto 0); -- output to control ADC initialization/syncronization phase
+ -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
+ jesd204b_refclk : in std_logic := '0';
+ -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
+ jesd204b_sysref : in std_logic := '0';
+ -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : out std_logic_vector(g_nof_streams - 1 downto 0);
serial_rx_arr : in std_logic_vector(g_nof_streams - 1 downto 0);
- kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
+ -- Kernel clock (runs the kernel_* I/O below)
+ kernel_clk : in std_logic;
kernel_reset : in std_logic;
src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0);
@@ -82,7 +88,8 @@ architecture str of ta2_unb2b_jesd204b is
constant c_nof_streams_jesd204b : natural := 12;
- constant c_rx_fifo_size : natural := 32; -- should be large enough
+ -- should be large enough
+ constant c_rx_fifo_size : natural := 32;
signal dp_fifo_dc_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal dp_fifo_dc_rx_snk_in_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
index 102c3f0ec1dcab780df235063bfcf51bbc7a36f8..526357da649f3b2dd73b938f3f782b360fcc0622 100644
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
@@ -28,7 +28,8 @@ use IEEE.std_logic_1164.all;
entity ta2_unb2b_jesd204b_ip_wrapper is
port (
- config_clk : in std_logic; -- 100MHz clk for reconfig block and status interface
+ -- 100MHz clk for reconfig block and status interface
+ config_clk : in std_logic;
config_reset : in std_logic;
-- MM Control
@@ -40,18 +41,25 @@ entity ta2_unb2b_jesd204b_ip_wrapper is
jesd204b_miso_waitrequest : out std_logic;
-- JESD204B external signals
- jesd204b_refclk : in std_logic := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
- jesd204b_sysref : in std_logic := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : out std_logic_vector(0 downto 0); -- output to control ADC initialization/syncronization phase
+ -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
+ jesd204b_refclk : in std_logic := '0';
+ -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
+ jesd204b_sysref : in std_logic := '0';
+ -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : out std_logic_vector(0 downto 0);
serial_rx_arr : in std_logic_vector(0 downto 0);
- kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
+ -- Kernel clock (runs the kernel_* I/O below)
+ kernel_clk : in std_logic;
kernel_reset : in std_logic;
- kernel_src_data : out std_logic_vector(15 downto 0); -- RX Data to kernel
- kernel_src_valid : out std_logic; -- RX data valid signal to kernel
- kernel_src_ready : in std_logic -- Flow control from kernel
+ -- RX Data to kernel
+ kernel_src_data : out std_logic_vector(15 downto 0);
+ -- RX data valid signal to kernel
+ kernel_src_valid : out std_logic;
+ -- Flow control from kernel
+ kernel_src_ready : in std_logic
);
end ta2_unb2b_jesd204b_ip_wrapper;
@@ -62,7 +70,8 @@ architecture str of ta2_unb2b_jesd204b_ip_wrapper is
----------------------------------------------------------------------------
component ta2_unb2b_jesd204b is
port (
- config_clk : in std_logic; -- 100MHz clk for reconfig block and status interface
+ -- 100MHz clk for reconfig block and status interface
+ config_clk : in std_logic;
config_reset : in std_logic;
-- MM Control
@@ -74,18 +83,25 @@ architecture str of ta2_unb2b_jesd204b_ip_wrapper is
jesd204b_miso_waitrequest : out std_logic;
-- JESD204B external signals
- jesd204b_refclk : in std_logic := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
- jesd204b_sysref : in std_logic := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : out std_logic_vector(0 downto 0); -- output to control ADC initialization/syncronization phase
+ -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
+ jesd204b_refclk : in std_logic := '0';
+ -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
+ jesd204b_sysref : in std_logic := '0';
+ -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : out std_logic_vector(0 downto 0);
serial_rx_arr : in std_logic_vector(0 downto 0);
- kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
+ -- Kernel clock (runs the kernel_* I/O below)
+ kernel_clk : in std_logic;
kernel_reset : in std_logic;
- kernel_src_data : out std_logic_vector(15 downto 0); -- RX Data to kernel
- kernel_src_valid : out std_logic; -- RX data valid signal to kernel
- kernel_src_ready : in std_logic -- Flow control from kernel
+ -- RX Data to kernel
+ kernel_src_data : out std_logic_vector(15 downto 0);
+ -- RX data valid signal to kernel
+ kernel_src_valid : out std_logic;
+ -- Flow control from kernel
+ kernel_src_ready : in std_logic
);
end component ta2_unb2b_jesd204b;
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
index f73837193b44a6a43ee128f28d0b03de0a8b2ff2..fb7c73ec9f7bd111580afb67468c2cbe31bf4766 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
@@ -76,7 +76,8 @@ entity ta2_unb2b_mm_io is
mm_clk : in std_logic;
mm_rst : in std_logic;
- kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
+ -- Kernel clock (runs the kernel_* I/O below)
+ kernel_clk : in std_logic;
kernel_reset : in std_logic;
-- MM registers
@@ -150,7 +151,8 @@ begin
generic map (
g_technology => c_tech_arria10_e1sg,
g_data_w => c_wr_data_w,
- g_use_ctrl => false, -- No sop & eop
+ -- No sop & eop
+ g_use_ctrl => false,
g_fifo_size => c_fifo_size,
g_fifo_rl => 0
)
@@ -173,7 +175,8 @@ begin
generic map (
g_technology => c_tech_arria10_e1sg,
g_data_w => c_rd_data_w,
- g_use_ctrl => false, -- No sop & eop
+ -- No sop & eop
+ g_use_ctrl => false,
g_fifo_size => c_fifo_size,
g_fifo_rl => 0
)
@@ -214,18 +217,22 @@ gen_no_opencl : if not g_use_opencl generate
begin
in_sosi.valid <= '0';
if out_sosi.valid = '1' then
- if out_sosi.data(64) = '1' then -- Write request
+ -- Write request
+ if out_sosi.data(64) = '1' then
if TO_UINT(out_sosi.data(63 downto 56)) = 0 then
reg_a <= out_sosi.data(31 downto 0);
elsif TO_UINT(out_sosi.data(63 downto 56)) = 1 then
- reg_b <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 1, 8) & out_sosi.data(23 downto 0); -- wrdata +1 to make distinguishable
+ -- wrdata +1 to make distinguishable
+ reg_b <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 1, 8) & out_sosi.data(23 downto 0);
elsif TO_UINT(out_sosi.data(63 downto 56)) = 2 then
reg_c <= out_sosi.data(31 downto 0);
elsif TO_UINT(out_sosi.data(63 downto 56)) = 3 then
- reg_d <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 2, 8) & out_sosi.data(23 downto 0); -- wrdata +2 to make distinguishable
+ -- wrdata +2 to make distinguishable
+ reg_d <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 2, 8) & out_sosi.data(23 downto 0);
end if;
out_siso.ready <= '1';
- else -- read request
+ -- read request
+ else
if not is_reading then
out_siso.ready <= '1';
in_sosi.valid <= '1';
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
index 262dbfdd93d69f7675bdc385c283003192bdcf92..ae110cc0d966409b8affde066a1eaf8633b08d19 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
@@ -98,19 +98,30 @@ begin
p_stim_mm : process
begin
wait until rst = '0';
- proc_common_wait_some_cycles(clk, 15); -- give dc fifos time to initialize
- proc_mem_mm_bus_wr(333, c_data_value, clk, mm_miso, mm_mosi); -- write value to unused address.
- proc_mem_mm_bus_wr(0, c_data_value, clk, mm_miso, mm_mosi); -- write value to address 0.
- proc_mem_mm_bus_wr(1, c_data_value+1, clk, mm_miso, mm_mosi); -- write value +1 to address 1.
- proc_mem_mm_bus_wr(2, c_data_value+2, clk, mm_miso, mm_mosi); -- write value +2 to address 2.
- proc_mem_mm_bus_wr(3, c_data_value+3, clk, mm_miso, mm_mosi); -- write value +3 to address 3.
+ -- give dc fifos time to initialize
+ proc_common_wait_some_cycles(clk, 15);
+ -- write value to unused address.
+ proc_mem_mm_bus_wr(333, c_data_value, clk, mm_miso, mm_mosi);
+ -- write value to address 0.
+ proc_mem_mm_bus_wr(0, c_data_value, clk, mm_miso, mm_mosi);
+ -- write value +1 to address 1.
+ proc_mem_mm_bus_wr(1, c_data_value+1, clk, mm_miso, mm_mosi);
+ -- write value +2 to address 2.
+ proc_mem_mm_bus_wr(2, c_data_value+2, clk, mm_miso, mm_mosi);
+ -- write value +3 to address 3.
+ proc_mem_mm_bus_wr(3, c_data_value+3, clk, mm_miso, mm_mosi);
proc_common_wait_some_cycles(clk, 5);
- proc_mem_mm_bus_rd(333, clk, mm_miso, mm_mosi); -- read address from undefined address.
- proc_mem_mm_bus_rd(3, clk, mm_miso, mm_mosi); -- read address 3.
- proc_mem_mm_bus_rd(2, clk, mm_miso, mm_mosi); -- read address 2.
- proc_mem_mm_bus_rd(1, clk, mm_miso, mm_mosi); -- read address 1.
- proc_mem_mm_bus_rd(0, clk, mm_miso, mm_mosi); -- read address 0.
+ -- read address from undefined address.
+ proc_mem_mm_bus_rd(333, clk, mm_miso, mm_mosi);
+ -- read address 3.
+ proc_mem_mm_bus_rd(3, clk, mm_miso, mm_mosi);
+ -- read address 2.
+ proc_mem_mm_bus_rd(2, clk, mm_miso, mm_mosi);
+ -- read address 1.
+ proc_mem_mm_bus_rd(1, clk, mm_miso, mm_mosi);
+ -- read address 0.
+ proc_mem_mm_bus_rd(0, clk, mm_miso, mm_mosi);
proc_common_wait_some_cycles(clk, 15);
@@ -125,7 +136,8 @@ begin
if in_sosi.valid = '1' then
proc_common_wait_some_cycles(clk, 1);
busy <= true;
- proc_common_wait_some_cycles(clk, 3); -- simulate request time
+ -- simulate request time
+ proc_common_wait_some_cycles(clk, 3);
busy <= false;
else
proc_common_wait_some_cycles(clk, 1);
@@ -138,7 +150,8 @@ begin
begin
in_sosi.valid <= '0';
if out_sosi.valid = '1' then
- if out_sosi.data(64) = '1' then -- Write request
+ -- Write request
+ if out_sosi.data(64) = '1' then
if TO_UINT(out_sosi.data(63 downto 56)) = 0 then
reg_a <= out_sosi.data(31 downto 0);
elsif TO_UINT(out_sosi.data(63 downto 56)) = 1 then
@@ -149,7 +162,8 @@ begin
reg_d <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 2, 8) & out_sosi.data(23 downto 0);
end if;
out_siso.ready <= '1';
- else -- read request
+ -- read request
+ else
if not busy then
out_siso.ready <= '1';
in_sosi.valid <= '1';
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
index e669d24a75b5631580f001a171f9755e4784b363..e5139db5c9ba2b551a11e05bbb0e097bd5c88434 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
@@ -61,7 +61,8 @@ entity node_unb1_bn_capture is
-- Auxiliary Interface
g_aux : t_c_unb1_board_aux := c_unb1_board_aux;
-- ADC Interface
- g_nof_dp_phs_clk : natural := 1; -- nof dp_phs_clk that can be used to detect the word phase
+ -- nof dp_phs_clk that can be used to detect the word phase
+ g_nof_dp_phs_clk : natural := 1;
g_ai : t_c_aduh_dd_ai := c_aduh_dd_ai
);
port (
@@ -70,31 +71,41 @@ entity node_unb1_bn_capture is
--
-- System
mm_rst : in std_logic;
- mm_clk : in std_logic; -- 50 MHz from xo_clk PLL in SOPC system
+ -- 50 MHz from xo_clk PLL in SOPC system
+ mm_clk : in std_logic;
dp_rst : in std_logic;
- dp_clk : in std_logic; -- 200 MHz from CLK system clock
- dp_phs_clk_vec : in std_logic_vector(g_nof_dp_phs_clk - 1 downto 0) := (others => '1'); -- divided and phase shifted dp_clk
- dp_pps : in std_logic; -- PPS in dp_clk domain
+ -- 200 MHz from CLK system clock
+ dp_clk : in std_logic;
+ -- divided and phase shifted dp_clk
+ dp_phs_clk_vec : in std_logic_vector(g_nof_dp_phs_clk - 1 downto 0) := (others => '1');
+ -- PPS in dp_clk domain
+ dp_pps : in std_logic;
- ext_clk : in std_logic; -- 200 MHz from CLK pin
+ -- 200 MHz from CLK pin
+ ext_clk : in std_logic;
-- MM bsn source
- reg_bsn_source_mosi : in t_mem_mosi; -- Start a BSN timestamp
+ -- Start a BSN timestamp
+ reg_bsn_source_mosi : in t_mem_mosi;
reg_bsn_source_miso : out t_mem_miso;
-- MM bsn scheduler for WG
- reg_bsn_scheduler_wg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- Schedule WG restart at a BSN, read current BSN
+ -- Schedule WG restart at a BSN, read current BSN
+ reg_bsn_scheduler_wg_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_bsn_scheduler_wg_miso : out t_mem_miso;
-- MM aduh quad
- reg_adc_quad_mosi : in t_mem_mosi := c_mem_mosi_rst; -- ADUH locked status and pattern verify for two half ADUs so 4 ADC inputs A, B, C and D
+ -- ADUH locked status and pattern verify for two half ADUs so 4 ADC inputs A, B, C and D
+ reg_adc_quad_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_adc_quad_miso : out t_mem_miso;
-- MM wideband waveform generator registers [0,1,2,3] for signal paths [A,B,C,D]
- reg_wg_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1) := (others => c_mem_mosi_rst); -- = [0:3] = Waveform Generator control ports [A,B,C,D]
+ -- = [0:3] = Waveform Generator control ports [A,B,C,D]
+ reg_wg_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1) := (others => c_mem_mosi_rst);
reg_wg_miso_arr : out t_mem_miso_arr(0 to g_ai.nof_sp - 1);
- ram_wg_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1) := (others => c_mem_mosi_rst); -- = [0:3] = Waveform Generator waveform buffer ports [A,B,C,D]
+ -- = [0:3] = Waveform Generator waveform buffer ports [A,B,C,D]
+ ram_wg_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1) := (others => c_mem_mosi_rst);
ram_wg_miso_arr : out t_mem_miso_arr(0 to g_ai.nof_sp - 1);
-- MM dp shiftram
@@ -102,9 +113,11 @@ entity node_unb1_bn_capture is
reg_dp_shiftram_miso : out t_mem_miso;
-- MM signal path monitors for [A, B, C, D]
- reg_mon_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1) := (others => c_mem_mosi_rst); -- = [0:3] = Read only access to the data mean sums and power sums [A,B,C,D]
+ -- = [0:3] = Read only access to the data mean sums and power sums [A,B,C,D]
+ reg_mon_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1) := (others => c_mem_mosi_rst);
reg_mon_miso_arr : out t_mem_miso_arr(0 to g_ai.nof_sp - 1);
- ram_mon_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1) := (others => c_mem_mosi_rst); -- = [0:3] = Read and overwrite access to the data monitor buffers [A,B,C,D]
+ -- = [0:3] = Read and overwrite access to the data monitor buffers [A,B,C,D]
+ ram_mon_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1) := (others => c_mem_mosi_rst);
ram_mon_miso_arr : out t_mem_miso_arr(0 to g_ai.nof_sp - 1);
-- MM registers [0,1] for I2C access with ADUs [AB,CD]
@@ -121,7 +134,8 @@ entity node_unb1_bn_capture is
reg_bsn_scheduler_sp_off_miso : out t_mem_miso;
-- ST
- sp_sosi_arr : out t_dp_sosi_arr(0 to g_ai.nof_sp - 1); -- = [0:3] = Signal Paths [A,B,C,D]
+ -- = [0:3] = Signal Paths [A,B,C,D]
+ sp_sosi_arr : out t_dp_sosi_arr(0 to g_ai.nof_sp - 1);
--
-- >>> Node FPGA pins
@@ -135,29 +149,42 @@ entity node_unb1_bn_capture is
ADC_BI_D : in std_logic_vector(g_ai.port_w - 1 downto 0);
ADC_BI_D_CLK : in std_logic := '0';
ADC_BI_D_CLK_RST : out std_logic;
- ADC_AB_SCL : inout std_logic; -- = ADC_SCL[0]
- ADC_AB_SDA : inout std_logic; -- = ADC_SDA[0]
- ADC_CD_SCL : inout std_logic; -- = ADC_SCL[3]
- ADC_CD_SDA : inout std_logic -- = ADC_SDA[3]
+ -- = ADC_SCL[0]
+ ADC_AB_SCL : inout std_logic;
+ -- = ADC_SDA[0]
+ ADC_AB_SDA : inout std_logic;
+ -- = ADC_SCL[3]
+ ADC_CD_SCL : inout std_logic;
+ -- = ADC_SDA[3]
+ ADC_CD_SDA : inout std_logic
);
end node_unb1_bn_capture;
architecture str of node_unb1_bn_capture is
-- Streaming ctrl path
constant c_dp_factor : natural := g_ai.rx_factor * g_ai.dd_factor;
- constant c_wideband_factor : natural := c_dp_factor; -- = 4 for dp_clk is 200 MHz frequency and sample frequency Fs is 800 MHz
- constant c_ai_block_size : natural := g_bn_capture.sp.nof_samples_per_block; -- = 1024 = nof 8b ADC samples per block
- constant c_sp_block_size : natural := c_ai_block_size / c_wideband_factor; -- = 256 = nof 32b samples words per block
-
- constant c_ai_data_w : natural := g_ai.port_w; -- = 8
- constant c_sp_data_w : natural := c_wideband_factor * c_ai_data_w; -- = 32
- constant c_sp_fifo_size : natural := 2 * c_sp_block_size; -- able to buffer at least one block of sp data
-
- constant c_use_result_ram : boolean := true; -- FALSE
+ -- = 4 for dp_clk is 200 MHz frequency and sample frequency Fs is 800 MHz
+ constant c_wideband_factor : natural := c_dp_factor;
+ -- = 1024 = nof 8b ADC samples per block
+ constant c_ai_block_size : natural := g_bn_capture.sp.nof_samples_per_block;
+ -- = 256 = nof 32b samples words per block
+ constant c_sp_block_size : natural := c_ai_block_size / c_wideband_factor;
+
+ -- = 8
+ constant c_ai_data_w : natural := g_ai.port_w;
+ -- = 32
+ constant c_sp_data_w : natural := c_wideband_factor * c_ai_data_w;
+ -- able to buffer at least one block of sp data
+ constant c_sp_fifo_size : natural := 2 * c_sp_block_size;
+
+ -- FALSE
+ constant c_use_result_ram : boolean := true;
-- Streaming output (4 signal paths with timestamp information, can be from ADU or from internal WG)
- signal i_sp_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1); -- = [0:3] = Signal Paths [A,B,C,D]
- signal sp_siso_arr : t_dp_siso_arr(0 to g_ai.nof_sp - 1); -- and e.g. A[31:0] = [A(t0), A(t1), A(t2), A(t3)], so 4 800M samples in time per one 32b word @ 200M
+ -- = [0:3] = Signal Paths [A,B,C,D]
+ signal i_sp_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1);
+ -- and e.g. A[31:0] = [A(t0), A(t1), A(t2), A(t3)], so 4 800M samples in time per one 32b word @ 200M
+ signal sp_siso_arr : t_dp_siso_arr(0 to g_ai.nof_sp - 1);
signal scheduled_sp_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1);
signal scheduled_sp_siso_arr : t_dp_siso_arr(0 to g_ai.nof_sp - 1);
@@ -257,7 +284,8 @@ begin
generic map (
g_sim => g_sim,
g_i2c_cmdr => c_i2c_cmdr_aduh_protocol_commander,
- g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm), -- use full address range in sim to avoid warnings
+ -- use full address range in sim to avoid warnings
+ g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm),
g_i2c_phy => func_i2c_calculate_phy(g_bn_capture.mm_clk_freq / 10**6),
g_protocol_ram_init_file => "data/adu_protocol_ram_init.hex",
g_use_result_ram => c_use_result_ram
@@ -288,7 +316,8 @@ begin
generic map (
g_sim => g_sim,
g_i2c_cmdr => c_i2c_cmdr_aduh_protocol_commander,
- g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm), -- use full address range in sim to avoid warnings
+ -- use full address range in sim to avoid warnings
+ g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm),
g_i2c_phy => func_i2c_calculate_phy(g_bn_capture.mm_clk_freq / 10**6),
g_protocol_ram_init_file => "data/adu_protocol_ram_init.hex",
g_use_result_ram => c_use_result_ram
@@ -368,7 +397,8 @@ begin
dp_rst => dp_rst,
dp_clk => dp_clk,
- snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
+ -- only uses eop (= block sync), bsn[]
+ snk_in => i_sp_sosi_arr(0),
trigger_out => dp_bsn_trigger_sp_on
);
@@ -389,7 +419,8 @@ begin
dp_rst => dp_rst,
dp_clk => dp_clk,
- snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
+ -- only uses eop (= block sync), bsn[]
+ snk_in => i_sp_sosi_arr(0),
trigger_out => dp_bsn_trigger_sp_off
);
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
index 39f0e51e1884df2cdb6217cc4ab4c3e7354038a8..b7c0fd3fe700845d1dd232e79feb5aaae68f605c 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
@@ -41,19 +41,27 @@ entity unb1_bn_capture is
g_sim : boolean := false;
g_design_name : string := "unb1_bn_capture";
-- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
- g_stamp_date : natural := 0; -- Date (YYYYMMDD)
- g_stamp_time : natural := 0; -- Time (HHMMSS)
- g_stamp_svn : natural := 0; -- SVN revision
+ -- Date (YYYYMMDD)
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS)
+ g_stamp_time : natural := 0;
+ -- SVN revision
+ g_stamp_svn : natural := 0;
-- Development note := "<---------max 32 chars--------->"
g_design_note : string := "ADUH 6 phs clocks; dp_shiftram"
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -72,29 +80,40 @@ entity unb1_bn_capture is
-- ADC Interface
ADC_BI_A : in std_logic_vector(c_aduh_dd_ai.port_w - 1 downto 0);
ADC_BI_B : in std_logic_vector(c_aduh_dd_ai.port_w - 1 downto 0);
- ADC_BI_A_CLK : in std_logic; -- use ADC_BI_A_CLK for port A and B, the ADC_BI_C_CLK is NC
- ADC_BI_A_CLK_RST : out std_logic; -- differential: via _P = ADC_SDL[1], _N = ADC_SCL[1] gets inferred
+ -- use ADC_BI_A_CLK for port A and B, the ADC_BI_C_CLK is NC
+ ADC_BI_A_CLK : in std_logic;
+ -- differential: via _P = ADC_SDL[1], _N = ADC_SCL[1] gets inferred
+ ADC_BI_A_CLK_RST : out std_logic;
ADC_BI_C : in std_logic_vector(c_aduh_dd_ai.port_w - 1 downto 0);
ADC_BI_D : in std_logic_vector(c_aduh_dd_ai.port_w - 1 downto 0);
- ADC_BI_D_CLK : in std_logic; -- use ADC_BI_D_CLK for port C and D, the ADC_BI_B_CLK is NC
- ADC_BI_D_CLK_RST : out std_logic; -- differential: via _P = ADC_SDL[2], _N = ADC_SCL[2] gets inferred
- ADC_AB_SCL : inout std_logic; -- = ADC_SCL[0]
- ADC_AB_SDA : inout std_logic; -- = ADC_SDA[0]
- ADC_CD_SCL : inout std_logic; -- = ADC_SCL[3]
- ADC_CD_SDA : inout std_logic -- = ADC_SDA[3]
+ -- use ADC_BI_D_CLK for port C and D, the ADC_BI_B_CLK is NC
+ ADC_BI_D_CLK : in std_logic;
+ -- differential: via _P = ADC_SDL[2], _N = ADC_SCL[2] gets inferred
+ ADC_BI_D_CLK_RST : out std_logic;
+ -- = ADC_SCL[0]
+ ADC_AB_SCL : inout std_logic;
+ -- = ADC_SDA[0]
+ ADC_AB_SDA : inout std_logic;
+ -- = ADC_SCL[3]
+ ADC_CD_SCL : inout std_logic;
+ -- = ADC_SDA[3]
+ ADC_CD_SDA : inout std_logic
);
end unb1_bn_capture;
architecture str of unb1_bn_capture is
- constant c_fw_version : t_unb1_board_fw_version := (1, 12); -- firmware version x.y
+ -- firmware version x.y
+ constant c_fw_version : t_unb1_board_fw_version := (1, 12);
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 0, 0, 0, 0, 1, 1);
constant c_dp_clk_use_pll : boolean := true;
- constant c_nof_dp_phs_clk : natural := 6; -- nof dp_phs_clk that can be used to detect the word phase, must be <= 6
+ -- nof dp_phs_clk that can be used to detect the word phase, must be <= 6
+ constant c_nof_dp_phs_clk : natural := 6;
constant c_bn_capture : t_c_bn_capture := c_bn_capture;
constant c_ai : t_c_aduh_dd_ai := c_aduh_dd_ai;
constant c_reg_dp_shiftram_adr_w : natural := 3;
- signal this_chip_id : std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0); -- [2:0], so range 0-3 for FN and range 4-7 BN
+ -- [2:0], so range 0-3 for FN and range 4-7 BN
+ signal this_chip_id : std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0);
-- System
signal cs_sim : std_logic;
@@ -132,36 +151,46 @@ architecture str of unb1_bn_capture is
signal rom_unb_system_info_miso : t_mem_miso;
-- UniBoard I2C sens
- signal reg_unb_sens_mosi : t_mem_mosi; -- mms_unb_sens registers
+ -- mms_unb_sens registers
+ signal reg_unb_sens_mosi : t_mem_mosi;
signal reg_unb_sens_miso : t_mem_miso;
-- eth1g
signal eth1g_tse_clk : std_logic;
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- MM bsn source
- signal reg_bsn_source_mosi : t_mem_mosi; -- Start a BSN timestamp
+ -- Start a BSN timestamp
+ signal reg_bsn_source_mosi : t_mem_mosi;
signal reg_bsn_source_miso : t_mem_miso;
-- MM bsn scheduler for WG
- signal reg_bsn_scheduler_wg_mosi : t_mem_mosi; -- Schedule WG restart at a BSN, read current BSN
+ -- Schedule WG restart at a BSN, read current BSN
+ signal reg_bsn_scheduler_wg_mosi : t_mem_mosi;
signal reg_bsn_scheduler_wg_miso : t_mem_miso;
-- MM aduh quad
- signal reg_adc_quad_mosi : t_mem_mosi; -- ADUH locked status and pattern verify for two half ADUs so 4 ADC inputs A, B, C and D
+ -- ADUH locked status and pattern verify for two half ADUs so 4 ADC inputs A, B, C and D
+ signal reg_adc_quad_mosi : t_mem_mosi;
signal reg_adc_quad_miso : t_mem_miso;
-- MM wideband waveform generator registers [0,1,2,3] for signal paths [A,B,C,D]
- signal reg_wg_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1); -- = [0:3] = Waveform Generator control ports [A,B,C,D]
+ -- = [0:3] = Waveform Generator control ports [A,B,C,D]
+ signal reg_wg_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1);
signal reg_wg_miso_arr : t_mem_miso_arr(0 to c_ai.nof_sp - 1);
- signal ram_wg_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1); -- = [0:3] = Waveform Generator waveform buffer ports [A,B,C,D]
+ -- = [0:3] = Waveform Generator waveform buffer ports [A,B,C,D]
+ signal ram_wg_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1);
signal ram_wg_miso_arr : t_mem_miso_arr(0 to c_ai.nof_sp - 1);
-- MM DP shiftram
@@ -169,9 +198,11 @@ architecture str of unb1_bn_capture is
signal reg_dp_shiftram_miso : t_mem_miso;
-- MM signal path monitors for [A, B, C, D]
- signal reg_mon_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1); -- = [0:3] = Read only access to the data mean sums and power sums [A,B,C,D]
+ -- = [0:3] = Read only access to the data mean sums and power sums [A,B,C,D]
+ signal reg_mon_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1);
signal reg_mon_miso_arr : t_mem_miso_arr(0 to c_ai.nof_sp - 1);
- signal ram_mon_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1); -- = [0:3] = Read only access to the data monitor buffers [A,B,C,D]
+ -- = [0:3] = Read only access to the data monitor buffers [A,B,C,D]
+ signal ram_mon_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1);
signal ram_mon_miso_arr : t_mem_miso_arr(0 to c_ai.nof_sp - 1);
-- MM registers [0,1] for I2C access with ADU AB and with ADU CD
@@ -194,11 +225,15 @@ begin
u_sopc : entity work.sopc_unb1_bn_capture
port map (
-- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ -- PLL reference = 25 MHz from ETH_clk pin
+ clk_0 => xo_clk,
reset_n => xo_rst_n,
- mm_clk => mm_clk, -- PLL clk[0] = 50 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => OPEN, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
+ -- PLL clk[0] = 50 MHz system clock that the NIOS2 and the MM bus run on
+ mm_clk => mm_clk,
+ -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ cal_clk => OPEN,
+ -- PLL clk[2] = 125 MHz calibration clock for the TSE
+ tse_clk => eth1g_tse_clk,
-- the_altpll_0
locked_from_the_altpll_0 => mm_locked,
@@ -247,7 +282,8 @@ begin
-- the_reg_bsn_scheduler_wg
coe_clk_export_from_the_reg_bsn_scheduler_wg => OPEN,
coe_reset_export_from_the_reg_bsn_scheduler_wg => OPEN,
- coe_address_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.address(0), -- reg_bsn_scheduler_adr_w = 1
+ -- reg_bsn_scheduler_adr_w = 1
+ coe_address_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.address(0),
coe_read_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.rd,
coe_readdata_export_to_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wr,
@@ -493,7 +529,8 @@ begin
-- the_pio_pps
coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1),
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
@@ -588,7 +625,8 @@ begin
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec, -- divided and phase shifted dp_clk
+ -- divided and phase shifted dp_clk
+ dp_phs_clk_vec => dp_phs_clk_vec,
this_chip_id => this_chip_id,
@@ -615,7 +653,8 @@ begin
reg_unb_sens_miso => reg_unb_sens_miso,
-- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
@@ -730,9 +769,11 @@ begin
ADC_BI_D => ADC_BI_D,
ADC_BI_D_CLK => ADC_BI_D_CLK,
ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
- ADC_AB_SCL => ADC_AB_SCL, -- I2C AB
+ -- I2C AB
+ ADC_AB_SCL => ADC_AB_SCL,
ADC_AB_SDA => ADC_AB_SDA,
- ADC_CD_SCL => ADC_CD_SCL, -- I2C CD
+ -- I2C CD
+ ADC_CD_SCL => ADC_CD_SCL,
ADC_CD_SDA => ADC_CD_SDA
);
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
index 79c2b1400580a02c5830e985980641183a1f83f2..dd1be014cdff8620ff45836d797fdfbd15982f24 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
@@ -43,7 +43,8 @@ entity unb1_bn_capture_input is
-- Use PHY Interface
g_use_phy : t_c_unb1_board_use_phy := (1, 0, 0, 0, 0, 0, 1, 1);
-- ADC Interface
- g_nof_dp_phs_clk : natural := 1; -- nof dp_phs_clk that can be used to detect the word phase
+ -- nof dp_phs_clk that can be used to detect the word phase
+ g_nof_dp_phs_clk : natural := 1;
g_ai : t_c_aduh_dd_ai := c_aduh_dd_ai
);
port (
@@ -61,29 +62,40 @@ entity unb1_bn_capture_input is
ADC_BI_D_CLK_RST : out std_logic;
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- dp_rst : in std_logic; -- reset synchronous with st_clk
- dp_clk : in std_logic; -- streaming clock domain clock
- dp_phs_clk_vec : in std_logic_vector(g_nof_dp_phs_clk - 1 downto 0); -- divided and phase shifted dp_clk
- dp_pps : in std_logic; -- external PPS in captured in dp_clk domain
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ dp_rst : in std_logic;
+ -- streaming clock domain clock
+ dp_clk : in std_logic;
+ -- divided and phase shifted dp_clk
+ dp_phs_clk_vec : in std_logic_vector(g_nof_dp_phs_clk - 1 downto 0);
+ -- external PPS in captured in dp_clk domain
+ dp_pps : in std_logic;
-- MM bsn source
- reg_bsn_source_mosi : in t_mem_mosi; -- Start a BSN timestamp
+ -- Start a BSN timestamp
+ reg_bsn_source_mosi : in t_mem_mosi;
reg_bsn_source_miso : out t_mem_miso;
-- MM bsn scheduler for WG
- reg_bsn_scheduler_wg_mosi : in t_mem_mosi; -- Schedule WG restart at a BSN, read current BSN
+ -- Schedule WG restart at a BSN, read current BSN
+ reg_bsn_scheduler_wg_mosi : in t_mem_mosi;
reg_bsn_scheduler_wg_miso : out t_mem_miso;
-- MM aduh quad
- reg_adc_quad_mosi : in t_mem_mosi; -- ADUH locked status and pattern verify for two half ADUs so 4 ADC inputs
+ -- ADUH locked status and pattern verify for two half ADUs so 4 ADC inputs
+ reg_adc_quad_mosi : in t_mem_mosi;
reg_adc_quad_miso : out t_mem_miso;
-- MM wideband waveform generator ports [A, B, C, D]
- reg_wg_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1); -- = [0:3] = WG control ports [A,B,C,D]
+ -- = [0:3] = WG control ports [A,B,C,D]
+ reg_wg_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1);
reg_wg_miso_arr : out t_mem_miso_arr(0 to g_ai.nof_sp - 1);
- ram_wg_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1); -- = [0:3] = WG buffer ports [A,B,C,D]
+ -- = [0:3] = WG buffer ports [A,B,C,D]
+ ram_wg_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1);
ram_wg_miso_arr : out t_mem_miso_arr(0 to g_ai.nof_sp - 1);
-- MM shiftram
@@ -91,24 +103,29 @@ entity unb1_bn_capture_input is
reg_dp_shiftram_miso : out t_mem_miso;
-- MM signal path monitor buffers for [A, B, C, D]
- reg_mon_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1); -- read only access to the data monitor mean sum and power sum
+ -- read only access to the data monitor mean sum and power sum
+ reg_mon_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1);
reg_mon_miso_arr : out t_mem_miso_arr(0 to g_ai.nof_sp - 1);
- ram_mon_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1); -- read and overwrite access to the data monitor buffers
+ -- read and overwrite access to the data monitor buffers
+ ram_mon_mosi_arr : in t_mem_mosi_arr(0 to g_ai.nof_sp - 1);
ram_mon_miso_arr : out t_mem_miso_arr(0 to g_ai.nof_sp - 1);
-- Streaming output (can be from ADU or from internal WG)
- sp_sosi_arr : out t_dp_sosi_arr(0 to g_ai.nof_sp - 1); -- = [0:3] = Signal Paths [A,B,C,D]
+ -- = [0:3] = Signal Paths [A,B,C,D]
+ sp_sosi_arr : out t_dp_sosi_arr(0 to g_ai.nof_sp - 1);
sp_siso_arr : in t_dp_siso_arr(0 to g_ai.nof_sp - 1)
);
end unb1_bn_capture_input;
architecture str of unb1_bn_capture_input is
constant c_dp_factor : natural := g_ai.rx_factor * g_ai.dd_factor;
- constant c_wideband_factor : natural := c_dp_factor; -- Wideband rate factor = 4 for dp_clk is 200 MHz frequency and sample frequency Fs is 800 MHz
+ -- Wideband rate factor = 4 for dp_clk is 200 MHz frequency and sample frequency Fs is 800 MHz
+ constant c_wideband_factor : natural := c_dp_factor;
constant c_bs_block_size : natural := g_bn_capture.sp.nof_samples_per_block / c_wideband_factor;
constant c_bs_nof_block_per_sync : natural := g_bn_capture.sp.nof_samples_per_sync / g_bn_capture.sp.nof_samples_per_block;
- constant c_bs_bsn_w : natural := c_dp_stream_bsn_w; -- = 48
+ -- = 48
+ constant c_bs_bsn_w : natural := c_dp_stream_bsn_w;
constant c_wg_buf_directory : string := "data/";
constant c_wg_buf_dat_w : natural := c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_dat_w;
@@ -118,15 +135,19 @@ architecture str of unb1_bn_capture_input is
signal bs_sosi : t_dp_sosi;
signal dp_bsn_trigger_wg : std_logic;
- signal aduh_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1); -- = [0:3] = ADC_BI ports [A,B,C,D]
+ -- = [0:3] = ADC_BI ports [A,B,C,D]
+ signal aduh_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1);
- signal wg_ovr : std_logic_vector(g_ai.nof_sp * c_wideband_factor - 1 downto 0); -- big endian, so first output sample in MSBit, MSData
+ -- big endian, so first output sample in MSBit, MSData
+ signal wg_ovr : std_logic_vector(g_ai.nof_sp * c_wideband_factor - 1 downto 0);
signal wg_dat : std_logic_vector(g_ai.nof_sp * c_wideband_factor * c_wg_buf_dat_w - 1 downto 0);
signal wg_val : std_logic_vector(g_ai.nof_sp * c_wideband_factor - 1 downto 0);
signal wg_sync : std_logic_vector(g_ai.nof_sp * c_wideband_factor - 1 downto 0);
- signal wg_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1); -- = [0:3] = WG ports [A,B,C,D]
+ -- = [0:3] = WG ports [A,B,C,D]
+ signal wg_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1);
- signal mux_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1); -- = [0:3] = Signal Paths [A,B,C,D]
+ -- = [0:3] = Signal Paths [A,B,C,D]
+ signal mux_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1);
signal nxt_mux_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1);
signal dp_shiftram_src_out_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1);
@@ -158,14 +179,18 @@ begin
-- . ADU_AB
ADC_BI_A => ADC_BI_A,
ADC_BI_B => ADC_BI_B,
- ADC_BI_A_CLK => ADC_BI_A_CLK, -- lvds clock from ADU_AB
- ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST, -- release synchronises ADU_AB DCLK divider
+ -- lvds clock from ADU_AB
+ ADC_BI_A_CLK => ADC_BI_A_CLK,
+ -- release synchronises ADU_AB DCLK divider
+ ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST,
-- . ADU_CD
ADC_BI_C => ADC_BI_C,
ADC_BI_D => ADC_BI_D,
- ADC_BI_D_CLK => ADC_BI_D_CLK, -- lvds clock from ADU_CD
- ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST, -- release synchronises ADU_CD DCLK divider
+ -- lvds clock from ADU_CD
+ ADC_BI_D_CLK => ADC_BI_D_CLK,
+ -- release synchronises ADU_CD DCLK divider
+ ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
-- MM clock domain
mm_rst => mm_rst,
@@ -230,7 +255,8 @@ begin
wg_sosi_arr(I).sync <= vector_or(wg_sync((I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ));
wg_sosi_arr(I).err <= TO_DP_ERROR(c_unb1_board_ok) when
vector_or(wg_ovr( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor )) = '0' else
- TO_DP_ERROR(2**c_unb1_board_error_adc_bi); -- pass ADC or WG overflow info on as an error signal
+ -- pass ADC or WG overflow info on as an error signal
+ TO_DP_ERROR(2**c_unb1_board_error_adc_bi);
end generate;
-----------------------------------------------------------------------------
@@ -274,9 +300,11 @@ begin
-----------------------------------------------------------------------------
u_dp_shiftram : entity dp_lib.dp_shiftram
generic map (
- g_nof_streams => g_ai.nof_sp, -- 4 signal paths
+ -- 4 signal paths
+ g_nof_streams => g_ai.nof_sp,
g_nof_words => 2048,
- g_data_w => c_wideband_factor * g_ai.port_w, -- 4 concatenated timesamples
+ -- 4 concatenated timesamples
+ g_data_w => c_wideband_factor * g_ai.port_w,
g_use_sync_in => true
)
port map (
@@ -339,7 +367,8 @@ begin
dp_rst => dp_rst,
dp_clk => dp_clk,
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ -- only uses eop (= block sync), bsn[]
+ snk_in => bs_sosi,
trigger_out => dp_bsn_trigger_wg
);
@@ -388,8 +417,10 @@ begin
generic map (
g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
g_symbol_w => g_ai.port_w,
- g_nof_symbols_per_data => c_wideband_factor, -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
- g_nof_accumulations => g_bn_capture.sp.nof_samples_per_sync, -- integration time in symbols, defines internal accumulator widths
+ -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data => c_wideband_factor,
+ -- integration time in symbols, defines internal accumulator widths
+ g_nof_accumulations => g_bn_capture.sp.nof_samples_per_sync,
g_buffer_nof_symbols => g_bn_capture.sp.monitor_buffer_nof_samples,
g_buffer_use_sync => g_bn_capture.sp.monitor_buffer_use_sync
)
@@ -398,9 +429,11 @@ begin
mm_rst => mm_rst,
mm_clk => mm_clk,
- reg_mosi => reg_mon_mosi_arr(I), -- read only access to the signal path data mean sum and power sum registers
+ -- read only access to the signal path data mean sum and power sum registers
+ reg_mosi => reg_mon_mosi_arr(I),
reg_miso => reg_mon_miso_arr(I),
- buf_mosi => ram_mon_mosi_arr(I), -- read and overwrite access to the signal path data buffers
+ -- read and overwrite access to the signal path data buffers
+ buf_mosi => ram_mon_mosi_arr(I),
buf_miso => ram_mon_miso_arr(I),
-- Streaming clock domain
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
index c6706e2421ec5038f0025dda055ce0ad451a2c4a..0b1dfdd43970e7bdbc4e56ef716df1a8592c4661 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
@@ -30,7 +30,8 @@ use dp_lib.dp_stream_pkg.all;
entity bn_capture_mux is
generic (
g_nof_input : natural := 4;
- g_in_fifo_size : natural := 512; -- 2 * 1024/4, at least 1 frame of block size 1024 8b samples, so 1024/4 32b samples words
+ -- 2 * 1024/4, at least 1 frame of block size 1024 8b samples, so 1024/4 32b samples words
+ g_in_fifo_size : natural := 512;
g_in_data_w : natural := 32;
g_mux_data_w : natural := 256
);
@@ -42,18 +43,21 @@ entity bn_capture_mux is
-- ST sinks (input signal paths)
in_siso_arr : out t_dp_siso_arr(0 to g_nof_input - 1);
- in_sosi_arr : in t_dp_sosi_arr(0 to g_nof_input - 1); -- = [0:3] = Signal Paths [A[31:0], B[31:0], C[31:0], D[31:0]]
+ -- = [0:3] = Signal Paths [A[31:0], B[31:0], C[31:0], D[31:0]]
+ in_sosi_arr : in t_dp_sosi_arr(0 to g_nof_input - 1);
-- and e.g. A[31:0] = [A(t0), A(t1), A(t2), A(t3)], so 4 8b samples in time per one 32b word
-- ST source (multiplexed output signal paths)
mux_wide_siso : in t_dp_siso := c_dp_siso_rdy;
- mux_wide_sosi : out t_dp_sosi -- = Signal Paths A[255:0], B[255:0], C[255:0], D[255:0] multiplexed in time
+ -- = Signal Paths A[255:0], B[255:0], C[255:0], D[255:0] multiplexed in time
+ mux_wide_sosi : out t_dp_sosi
-- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 8b samples in time per one 256b word
);
end bn_capture_mux;
architecture str of bn_capture_mux is
signal wide_siso_arr : t_dp_siso_arr(0 to g_nof_input - 1);
- signal wide_sosi_arr : t_dp_sosi_arr(0 to g_nof_input - 1); -- = [0:3] = Signal Paths [A,B,C,D]
+ -- = [0:3] = Signal Paths [A,B,C,D]
+ signal wide_sosi_arr : t_dp_sosi_arr(0 to g_nof_input - 1);
-- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 800M samples in time per one 256b word
begin
gen_fifo : for I in 0 to g_nof_input - 1 generate
@@ -95,8 +99,10 @@ begin
g_mode => 1,
g_nof_input => g_nof_input,
g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_input), -- dummy value must match g_nof_input
- g_fifo_fill => array_init( 0, g_nof_input) -- dummy value must match g_nof_input
+ -- dummy value must match g_nof_input
+ g_fifo_size => array_init(1024, g_nof_input),
+ -- dummy value must match g_nof_input
+ g_fifo_fill => array_init( 0, g_nof_input)
)
port map (
rst => mux_wide_rst,
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
index ced8c5739b7c1d50b097614e358faaf035293607..fffe6516e4e3057c301f72b26b260fc815cd219c 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
@@ -28,16 +28,23 @@ use unb1_board_lib.unb1_board_pkg.all;
package unb1_bn_capture_pkg is
-- Signal path input
type t_c_bn_capture_sp is record
- sample_freq : natural; -- = 800; -- The ADC sample rate is 800 Msps, so the LVDS rate is 800 Mbps per ADC BI data line,
- nof_samples_per_block : natural; -- = 1024; -- = nof 8b ADC samples per block, e.g. 1024 for PFB down sample factor of 1024
- nof_samples_per_sync : natural; -- = 800*10**6; -- = nof 8b ADC samples per sync interval
- monitor_buffer_nof_samples : natural; -- = 1024; -- = nof 8b ADC samples per monitor buffer
- monitor_buffer_use_sync : boolean; -- when TRUE start filling the buffer after the sync, else after the last word was read
+ -- = 800; -- The ADC sample rate is 800 Msps, so the LVDS rate is 800 Mbps per ADC BI data line,
+ sample_freq : natural;
+ -- = 1024; -- = nof 8b ADC samples per block, e.g. 1024 for PFB down sample factor of 1024
+ nof_samples_per_block : natural;
+ -- = 800*10**6; -- = nof 8b ADC samples per sync interval
+ nof_samples_per_sync : natural;
+ -- = 1024; -- = nof 8b ADC samples per monitor buffer
+ monitor_buffer_nof_samples : natural;
+ -- when TRUE start filling the buffer after the sync, else after the last word was read
+ monitor_buffer_use_sync : boolean;
end record;
- constant c_bn_capture_sp : t_c_bn_capture_sp := (800, 1024, 800000 * 1024, 1024, true); -- 800 MSps, block size 1024 samples, 800000 blocks per sync interval (= 1.024 s), monitor buffer 1024 samples using sync
+ -- 800 MSps, block size 1024 samples, 800000 blocks per sync interval (= 1.024 s), monitor buffer 1024 samples using sync
+ constant c_bn_capture_sp : t_c_bn_capture_sp := (800, 1024, 800000 * 1024, 1024, true);
- constant c_bn_capture_mm_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ constant c_bn_capture_mm_cross_clock_domain : boolean := true;
-- Aggregate BN capture constants record
type t_c_bn_capture is record
@@ -46,7 +53,8 @@ package unb1_bn_capture_pkg is
sp : t_c_bn_capture_sp;
end record;
- constant c_bn_capture : t_c_bn_capture := (c_unb1_board_mm_clk_freq_50M, -- must match PLL setting in sopc_bn_capture
+ -- must match PLL setting in sopc_bn_capture
+ constant c_bn_capture : t_c_bn_capture := (c_unb1_board_mm_clk_freq_50M,
c_unb1_board_ext_clk_freq_200M,
c_bn_capture_sp);
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
index 97a864cc1cca127daca023931905f7daa081c719..476ab7919dcc2e6d5ca94dcd0883094741ac9736 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
@@ -33,11 +33,15 @@ entity bn_capture_storage is
generic (
g_sim : boolean := false;
-- Multiplexed signal path interface
- g_nof_channel : natural := 2; -- nof channel is 4, i.e. port A, B, C and D, or 2 for only port A, B or port C, D
- g_start_channel : natural := 0; -- start storage when sop for this g_start_channel arrives
- g_mux_data_w : natural := 256; -- multiplexed data width is 256 so equal to the internal DDR3 data width
+ -- nof channel is 4, i.e. port A, B, C and D, or 2 for only port A, B or port C, D
+ g_nof_channel : natural := 2;
+ -- start storage when sop for this g_start_channel arrives
+ g_start_channel : natural := 0;
+ -- multiplexed data width is 256 so equal to the internal DDR3 data width
+ g_mux_data_w : natural := 256;
-- DDR3 Interface
- g_ddr : t_c_ddr3_phy := c_ddr3_phy_4g -- use c_ddr3_phy_4g or c_ddr3_phy_1g dependent on what was generated with the MegaWizard
+ -- use c_ddr3_phy_4g or c_ddr3_phy_1g dependent on what was generated with the MegaWizard
+ g_ddr : t_c_ddr3_phy := c_ddr3_phy_4g
);
port (
mm_rst : in std_logic;
@@ -52,11 +56,13 @@ entity bn_capture_storage is
phy_rst_2x : out std_logic;
phy_clk_2x : out std_logic;
- ext_clk : in std_logic; -- for DDR3 controller
+ -- for DDR3 controller
+ ext_clk : in std_logic;
-- ST sink (multiplexed input signal paths)
mux_wide_siso : out t_dp_siso := c_dp_siso_rdy;
- mux_wide_sosi : in t_dp_sosi; -- = Signal Paths A[255:0], B[255:0], C[255:0], D[255:0] multiplexed in time
+ -- = Signal Paths A[255:0], B[255:0], C[255:0], D[255:0] multiplexed in time
+ mux_wide_sosi : in t_dp_sosi;
-- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 8b samples in time per one 256b word
-- MM registers
ctrl_mosi : in t_mem_mosi := c_mem_mosi_rst;
@@ -191,7 +197,8 @@ begin
if dvr_en = '1' and dvr_wr_not_rd = '1' then
nxt_state <= s_stop;
end if;
- when others => -- s_stop
+ -- s_stop
+ when others =>
dvr_flush <= '1';
if mux_wide_sosi.sop = '1' and unsigned(mux_wide_sosi.channel(c_channel_w - 1 downto 0)) = g_start_channel then
nxt_state <= s_idle;
@@ -209,12 +216,14 @@ begin
snk_out => rd_siso,
snk_in => rd_sosi,
- usedw => rd_usedw, -- used words from rd FIFO
+ -- used words from rd FIFO
+ usedw => rd_usedw,
mm_rd => mm_rd,
mm_rddata => mm_rd_data,
mm_rdval => mm_rd_val,
- mm_usedw => mm_rd_usedw -- resized to 32 bits
+ -- resized to 32 bits
+ mm_usedw => mm_rd_usedw
);
-- DDR3 streaming read output to mm bus
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
index ded28ec91ca04a869ec6d7e2dbe80d9210eced4b..41db082f89696005bf68d121c78e5d0b9e6ffacd 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
@@ -31,14 +31,20 @@ entity bn_capture_storage_reg is
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
st_en_evt : out std_logic;
@@ -59,7 +65,8 @@ end bn_capture_storage_reg;
architecture rtl of bn_capture_storage_reg is
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(8),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 8,
init_sl => '0');
-- Registers in mm_clk domain
@@ -113,13 +120,16 @@ begin
mm_start_address <= sla_in.wrdata(31 downto 0);
when 6 =>
mm_end_address <= sla_in.wrdata(31 downto 0);
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read Block Sync
when 2 =>
@@ -130,7 +140,8 @@ begin
sla_out.rddata(0) <= mm_ctlr_rdy;
when 7 =>
sla_out.rddata(31 downto 0) <= mm_rd_usedw;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
index 6c96281275b7a849cd9deb61c52e1a746606a05e..f57238c02986ef6ac941b8be238a986b2b180476 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
@@ -81,43 +81,63 @@ architecture tb of tb_node_unb1_bn_capture is
constant c_id_bn0 : std_logic_vector(7 downto 0) := "00000100";
constant c_fw_version : t_unb1_board_fw_version := (1, 0);
- constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 48 * 1024, 4 * 1024, true); -- 800 MSps, block size 1024 samples, 48 blocks per sync interval, monitor buffer 4096 samples using sync
+ -- 800 MSps, block size 1024 samples, 48 blocks per sync interval, monitor buffer 4096 samples using sync
+ constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 48 * 1024, 4 * 1024, true);
constant c_bn_capture : t_c_bn_capture := (c_unb1_board_mm_clk_freq_50M,
c_unb1_board_ext_clk_freq_200M,
c_bn_capture_sp_sim);
- constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
- constant c_mm_clk_period : time := 20 ns; -- 50 MHz MM clock, altpll in SOPC will make this from the ETH 25 MHz XO clock
+ -- 25 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 40 ns;
+ -- 50 MHz MM clock, altpll in SOPC will make this from the ETH 25 MHz XO clock
+ constant c_mm_clk_period : time := 20 ns;
constant c_cable_delay : time := 12 ns;
-- ADU
- constant c_ai : t_c_aduh_dd_ai := (4, 2, 2, 8, 2, 2, false, false, c_aduh_delays); -- keep DCLK_RST = '0', others as in c_aduh_dd_ai
+ -- keep DCLK_RST = '0', others as in c_aduh_dd_ai
+ constant c_ai : t_c_aduh_dd_ai := (4, 2, 2, 8, 2, 2, false, false, c_aduh_delays);
--CONSTANT c_ai : t_c_aduh_dd_ai := (4, 2, 2, 8, 2, 2, TRUE, TRUE, c_aduh_delays); -- invert DCLK_RST, others as in c_aduh_dd_ai
--CONSTANT c_ai : t_c_aduh_dd_ai := c_aduh_dd_ai;
constant c_dp_factor : natural := c_ai.rx_factor * c_ai.dd_factor;
- constant c_wideband_factor : natural := c_dp_factor; -- = 4
+ -- = 4
+ constant c_wideband_factor : natural := c_dp_factor;
- constant c_sample_freq : natural := c_wideband_factor * c_unb1_board_ext_clk_freq_200M / 10**6; -- 800 MSps
- constant c_sample_period : time := (10**6 / c_sample_freq) * 1 ps; -- 1250 ns
- constant c_ext_clk_freq : natural := c_unb1_board_ext_clk_freq_200M; -- 200 MHz external reference clock for data path processing
- constant c_ext_clk_period : time := c_wideband_factor * c_sample_period; -- 200 MHz
+ -- 800 MSps
+ constant c_sample_freq : natural := c_wideband_factor * c_unb1_board_ext_clk_freq_200M / 10**6;
+ -- 1250 ns
+ constant c_sample_period : time := (10**6 / c_sample_freq) * 1 ps;
+ -- 200 MHz external reference clock for data path processing
+ constant c_ext_clk_freq : natural := c_unb1_board_ext_clk_freq_200M;
+ -- 200 MHz
+ constant c_ext_clk_period : time := c_wideband_factor * c_sample_period;
- constant c_ana_diff : natural := 16; -- analogue offset value between the port A, B, C, D, use 0 to have same data on all ports
+ -- analogue offset value between the port A, B, C, D, use 0 to have same data on all ports
+ constant c_ana_diff : natural := 16;
-- ADC
- signal ANA_DAT : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- Common ADC reference data source
- signal ANA_A : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port A
- signal ANA_B : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port B
- signal ANA_C : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port C
- signal ANA_D : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port D
+ -- Common ADC reference data source
+ signal ANA_DAT : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port A
+ signal ANA_A : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port B
+ signal ANA_B : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port C
+ signal ANA_C : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port D
+ signal ANA_D : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
signal ANA_OVR : std_logic := '0';
- signal SCLK : std_logic := '1'; -- central sample clock = 800 MHz
- signal DCLK_AB : std_logic; -- digital lvds clock = 400 MHz (DDR)
- signal DCLK_CD : std_logic; -- digital lvds clock = 400 MHz (DDR)
- signal DCLK_RST_AB : std_logic; -- synchronise digital lvds clock
- signal DCLK_RST_CD : std_logic; -- synchronise digital lvds clock
+ -- central sample clock = 800 MHz
+ signal SCLK : std_logic := '1';
+ -- digital lvds clock = 400 MHz (DDR)
+ signal DCLK_AB : std_logic;
+ -- digital lvds clock = 400 MHz (DDR)
+ signal DCLK_CD : std_logic;
+ -- synchronise digital lvds clock
+ signal DCLK_RST_AB : std_logic;
+ -- synchronise digital lvds clock
+ signal DCLK_RST_CD : std_logic;
signal DIG_A : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_B : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_C : std_logic_vector(c_ai.port_w - 1 downto 0);
@@ -165,18 +185,21 @@ architecture tb of tb_node_unb1_bn_capture is
signal pin_pps : std_logic_vector(c_word_w - 1 downto 0);
signal pin_pps_toggle : std_logic;
- signal pin_pps_capture_cnt : std_logic_vector(ceil_log2(c_ext_clk_freq) - 1 downto 0); -- counts the number of clock cycles between subsequent pps pulses
+ -- counts the number of clock cycles between subsequent pps pulses
+ signal pin_pps_capture_cnt : std_logic_vector(ceil_log2(c_ext_clk_freq) - 1 downto 0);
-- MM bsn source
signal current_bsn_wg : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
signal current_bsn_sp : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
signal nof_block_per_sync : std_logic_vector(c_word_w - 1 downto 0);
- signal reg_bsn_source_mosi : t_mem_mosi := c_mem_mosi_rst; -- Start a BSN timestamp
+ -- Start a BSN timestamp
+ signal reg_bsn_source_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_bsn_source_miso : t_mem_miso;
-- MM bsn schedule WG
- signal reg_bsn_scheduler_wg_mosi : t_mem_mosi := c_mem_mosi_rst; -- Schedule WG restart at a BSN, read current BSN
+ -- Schedule WG restart at a BSN, read current BSN
+ signal reg_bsn_scheduler_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_bsn_scheduler_wg_miso : t_mem_miso;
-- Wideband Waveform Generators [0,1,2,3] for signal paths [A,B,C,D]
@@ -196,7 +219,8 @@ architecture tb of tb_node_unb1_bn_capture is
-- Commander results [0,1] for ADU-[AB,CD]
signal cmdr_protocol_status : t_natural_arr(0 to c_ai.nof_adu - 1);
signal cmdr_result_data : t_natural_arr(0 to c_ai.nof_adu - 1);
- signal exp_result_data : t_natural_arr(0 to c_ai.nof_adu - 1) := (0, 60); -- expected temp 60 degrees in adu_half
+ -- expected temp 60 degrees in adu_half
+ signal exp_result_data : t_natural_arr(0 to c_ai.nof_adu - 1) := (0, 60);
signal cmdr_result_error_cnt : t_natural_arr(0 to c_ai.nof_adu - 1);
signal exp_result_error_cnt : t_natural_arr(0 to c_ai.nof_adu - 1) := (0, 0);
@@ -212,15 +236,20 @@ begin
tb_end <= '0', reg_input_stimuli_done and i2c_adu_stimuli_done after c_mm_clk_period * 100;
- eth_clk <= not eth_clk or tb_end after c_eth_clk_period / 2; -- 1GbE XO clock (25 MHz)
+ -- 1GbE XO clock (25 MHz)
+ eth_clk <= not eth_clk or tb_end after c_eth_clk_period / 2;
- mm_clk <= not mm_clk or tb_end after c_mm_clk_period / 2; -- MM clock (50 MHz)
+ -- MM clock (50 MHz)
+ mm_clk <= not mm_clk or tb_end after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_clk_period * 7;
- ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2; -- External clock (200 MHz)
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
VERSION <= c_version;
ID <= c_id_bn0;
@@ -260,8 +289,10 @@ begin
-- * address 2, 3
-- mm_bs_init_bsn : BSN[47:0]
proc_mem_mm_bus_wr(3, 16#00000000#, mm_clk, reg_bsn_source_mosi);
- proc_mem_mm_bus_wr(2, 16#00000000#, mm_clk, reg_bsn_source_mosi); -- Init BSN = 0
- proc_mem_mm_bus_wr(0, 16#00000001#, mm_clk, reg_bsn_source_mosi); -- Enable BS (start without using PPS)
+ -- Init BSN = 0
+ proc_mem_mm_bus_wr(2, 16#00000000#, mm_clk, reg_bsn_source_mosi);
+ -- Enable BS (start without using PPS)
+ proc_mem_mm_bus_wr(0, 16#00000001#, mm_clk, reg_bsn_source_mosi);
proc_common_wait_some_cycles(mm_clk, 10);
-- Wait for as long as we want ADU data to be processed
@@ -282,7 +313,8 @@ begin
-- . phase[15:0]
-- . freq[30:0]
-- . ampl[16:0]
- proc_mem_mm_bus_wr(0, 2 + 1024 * 2**16, mm_clk, reg_wg_mosi_arr(0)); -- mode repeat, nof_sample
+ -- mode repeat, nof_sample
+ proc_mem_mm_bus_wr(0, 2 + 1024 * 2**16, mm_clk, reg_wg_mosi_arr(0));
proc_mem_mm_bus_wr(0, 2 + 1024 * 2**16, mm_clk, reg_wg_mosi_arr(1));
proc_mem_mm_bus_wr(0, 2 + 1024 * 2**16, mm_clk, reg_wg_mosi_arr(2));
proc_mem_mm_bus_wr(0, 2 + 1024 * 2**16, mm_clk, reg_wg_mosi_arr(3));
@@ -300,8 +332,10 @@ begin
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
- proc_mem_mm_bus_wr(0, v_bsn, mm_clk, reg_bsn_scheduler_wg_mosi); -- first write low then high part
- proc_mem_mm_bus_wr(1, 0, mm_clk, reg_bsn_scheduler_wg_mosi); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ proc_mem_mm_bus_wr(0, v_bsn, mm_clk, reg_bsn_scheduler_wg_mosi);
+ -- assume v_bsn < 2**31-1
+ proc_mem_mm_bus_wr(1, 0, mm_clk, reg_bsn_scheduler_wg_mosi);
-- Continue forever with WG data
end if;
@@ -320,8 +354,10 @@ begin
constant c_result_error_cnt_wi : natural := 3 * c_i2c_cmdr_aduh_protocol_commander.nof_protocols + 1;
constant c_result_data_wi : natural := 3 * c_i2c_cmdr_aduh_protocol_commander.nof_protocols + 2;
- constant c_A : natural range 0 to c_ai.nof_adu - 1 := 1; -- only try ADUH index (1) = ADU-CD
- constant c_P : natural := 0; -- 0 = c_i2c_adu_max1617_protocol_list_read_temp --> expected temp 60 degrees in adu_half
+ -- only try ADUH index (1) = ADU-CD
+ constant c_A : natural range 0 to c_ai.nof_adu - 1 := 1;
+ -- 0 = c_i2c_adu_max1617_protocol_list_read_temp --> expected temp 60 degrees in adu_half
+ constant c_P : natural := 0;
begin
reg_commander_mosi_arr <= (others => c_mem_mosi_rst);
ram_protocol_mosi_arr <= (others => c_mem_mosi_rst);
@@ -399,15 +435,20 @@ begin
xo_clk => OPEN,
xo_rst_n => OPEN,
- mm_clk => mm_clk, -- 50 MHz
+ -- 50 MHz
+ mm_clk => mm_clk,
mm_locked => mm_locked,
mm_rst => mm_rst,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- 200 MHz from CLK system clock
- dp_pps => dp_pps, -- PPS in dp_clk domain
- dp_rst_in => dp_rst, -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
- dp_clk_in => dp_clk, -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk (due to dp_clk <= i_dp_clk assignment)
+ -- 200 MHz from CLK system clock
+ dp_clk => dp_clk,
+ -- PPS in dp_clk domain
+ dp_pps => dp_pps,
+ -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
+ dp_rst_in => dp_rst,
+ -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk (due to dp_clk <= i_dp_clk assignment)
+ dp_clk_in => dp_clk,
-- PIOs
pout_debug_wave => pout_debug_wave,
@@ -525,7 +566,8 @@ begin
ANA_B <= INCR_UVEC(ANA_DAT, 1 * c_ana_diff);
ANA_C <= INCR_UVEC(ANA_DAT, 2 * c_ana_diff);
ANA_D <= INCR_UVEC(ANA_DAT, 3 * c_ana_diff);
- ANA_OVR <= not ANA_OVR when rising_edge(SCLK); -- simple overflow model used for both ADC
+ -- simple overflow model used for both ADC
+ ANA_OVR <= not ANA_OVR when rising_edge(SCLK);
-- National ADC
u_adc_AB : entity aduh_lib.adu_half
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
index 1cf7b5d6fb00cd64f696b1d5682bb1bcfb73bf9b..5afdee5cf14b68e90f0ddb59a5d54807a98b5096 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
@@ -73,46 +73,67 @@ architecture tb of tb_bn_capture is
constant c_id_bn0 : std_logic_vector(7 downto 0) := "00000100";
constant c_fw_version : t_unb_fw_version := (1, 0);
- constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 1024 * 1024, 1024, true); -- 800 MSps, block size 1024 samples, nof blocks per sync interval, monitor buffer nof samples using sync
+ -- 800 MSps, block size 1024 samples, nof blocks per sync interval, monitor buffer nof samples using sync
+ constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 1024 * 1024, 1024, true);
constant c_bn_capture : t_c_bn_capture := (c_unb_mm_clk_freq_50M,
c_unb_ext_clk_freq_200M,
c_bn_capture_sp_sim);
- constant c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g; -- use c_ddr3_phy_4g or c_ddr3_phy_1g dependent on what was generated with the MegaWizard
+ -- use c_ddr3_phy_4g or c_ddr3_phy_1g dependent on what was generated with the MegaWizard
+ constant c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
- constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
+ -- 25 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 40 ns;
constant c_cable_delay : time := 12 ns;
- constant c_max1618_address : std_logic_vector := TO_UVEC(I2C_UNB_MAX1617_ADR, 7); -- MAX1618 address MID MID
+ -- MAX1618 address MID MID
+ constant c_max1618_address : std_logic_vector := TO_UVEC(I2C_UNB_MAX1617_ADR, 7);
constant c_max1618_temp : integer := 60;
-- ADU
- constant c_nof_dp_phs_clk : natural := 6; -- nof dp_phs_clk that can be used to detect the word phase
+ -- nof dp_phs_clk that can be used to detect the word phase
+ constant c_nof_dp_phs_clk : natural := 6;
constant c_ai : t_c_aduh_dd_ai := c_aduh_dd_ai;
constant c_dp_factor : natural := c_ai.rx_factor * c_ai.dd_factor;
- constant c_wideband_factor : natural := c_dp_factor; -- = 4
+ -- = 4
+ constant c_wideband_factor : natural := c_dp_factor;
- constant c_sample_freq : natural := c_wideband_factor * c_unb_ext_clk_freq_200M / 10**6; -- 800 MSps
- constant c_sample_period : time := (10**6 / c_sample_freq) * 1 ps; -- 1250 ns
- constant c_ext_clk_freq : natural := c_unb_ext_clk_freq_200M; -- 200 MHz external reference clock for data path processing
- constant c_ext_clk_period : time := c_wideband_factor * c_sample_period; -- 200 MHz
+ -- 800 MSps
+ constant c_sample_freq : natural := c_wideband_factor * c_unb_ext_clk_freq_200M / 10**6;
+ -- 1250 ns
+ constant c_sample_period : time := (10**6 / c_sample_freq) * 1 ps;
+ -- 200 MHz external reference clock for data path processing
+ constant c_ext_clk_freq : natural := c_unb_ext_clk_freq_200M;
+ -- 200 MHz
+ constant c_ext_clk_period : time := c_wideband_factor * c_sample_period;
- constant c_ana_diff : natural := 16; -- analogue offset value between the port A, B, C, D, use 0 to have same data on all ports
+ -- analogue offset value between the port A, B, C, D, use 0 to have same data on all ports
+ constant c_ana_diff : natural := 16;
-- ADC
- signal ANA_DAT : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- Common ADC reference data source
- signal ANA_A : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port A
- signal ANA_B : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port B
- signal ANA_C : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port C
- signal ANA_D : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port D
+ -- Common ADC reference data source
+ signal ANA_DAT : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port A
+ signal ANA_A : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port B
+ signal ANA_B : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port C
+ signal ANA_C : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port D
+ signal ANA_D : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
signal ANA_OVR : std_logic := '0';
- signal SCLK : std_logic := '1'; -- central sample clock = 800 MHz
- signal DCLK_AB : std_logic; -- digital lvds clock = 400 MHz (DDR)
- signal DCLK_CD : std_logic; -- digital lvds clock = 400 MHz (DDR)
- signal DCLK_RST_AB : std_logic; -- synchronise digital lvds clock
- signal DCLK_RST_CD : std_logic; -- synchronise digital lvds clock
+ -- central sample clock = 800 MHz
+ signal SCLK : std_logic := '1';
+ -- digital lvds clock = 400 MHz (DDR)
+ signal DCLK_AB : std_logic;
+ -- digital lvds clock = 400 MHz (DDR)
+ signal DCLK_CD : std_logic;
+ -- synchronise digital lvds clock
+ signal DCLK_RST_AB : std_logic;
+ -- synchronise digital lvds clock
+ signal DCLK_RST_CD : std_logic;
signal DIG_A : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_B : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_C : std_logic_vector(c_ai.port_w - 1 downto 0);
@@ -160,15 +181,21 @@ begin
-- System setup
----------------------------------------------------------------------------
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- 1GbE XO clock (25 MHz)
+ -- 1GbE XO clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
u_sens_temp : entity i2c_lib.dev_max1618
generic map (
@@ -265,7 +292,8 @@ begin
ANA_B <= INCR_UVEC(ANA_DAT, 1 * c_ana_diff);
ANA_C <= INCR_UVEC(ANA_DAT, 2 * c_ana_diff);
ANA_D <= INCR_UVEC(ANA_DAT, 3 * c_ana_diff);
- ANA_OVR <= not ANA_OVR when rising_edge(SCLK); -- simple overflow model used for both ADC
+ -- simple overflow model used for both ADC
+ ANA_OVR <= not ANA_OVR when rising_edge(SCLK);
-- Same sample clock for all ADC
SCLK <= not SCLK after c_sample_period / 2;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
index 3c4226b3cc4c4723d29f664c07f4f5ac68d708a4..22c20fe526d3cd0cd2076050c8c15ac8cbfdfcf8 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
@@ -69,7 +69,8 @@ end tb_unb1_bn_capture_input;
architecture tb of tb_unb1_bn_capture_input is
constant c_sim : boolean := true;
- constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 48 * 1024, 4 * 1024, true); -- 800 MSps, block size 1024 samples, 48 blocks per sync interval, monitor buffer 4096 samples using sync
+ -- 800 MSps, block size 1024 samples, 48 blocks per sync interval, monitor buffer 4096 samples using sync
+ constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 48 * 1024, 4 * 1024, true);
constant c_bn_capture : t_c_bn_capture := (c_unb1_board_mm_clk_freq_50M,
c_unb1_board_ext_clk_freq_200M,
c_bn_capture_sp_sim);
@@ -84,7 +85,8 @@ architecture tb of tb_unb1_bn_capture_input is
constant c_bsn_schedule_wg_on : natural := c_nof_block_per_sync * 4;
constant c_bsn_schedule_aduh_verify : natural := c_nof_block_per_sync * 7;
- constant c_bsn_schedule_aduh_monitor : natural := c_nof_block_per_sync + c_nof_block_per_monitor_buffer; -- read aduh monitor after buffer was filled again
+ -- read aduh monitor after buffer was filled again
+ constant c_bsn_schedule_aduh_monitor : natural := c_nof_block_per_sync + c_nof_block_per_monitor_buffer;
constant c_bsn_schedule_nof_events : natural := 8;
-- ADU
@@ -92,27 +94,43 @@ architecture tb of tb_unb1_bn_capture_input is
constant c_ai : t_c_aduh_dd_ai := c_aduh_dd_ai;
constant c_dp_factor : natural := c_ai.rx_factor * c_ai.dd_factor;
- constant c_wideband_factor : natural := c_dp_factor; -- = 4
-
- constant c_mm_clk_period : time := 20 ns; -- 50 MHz
- constant c_sample_period : time := 1250 ps; -- 800 MSps
- constant c_dp_clk_period : time := c_sample_period * c_wideband_factor; -- 200 MHz external reference clock for data path processing
- constant c_dp_phs_clk_step : time := c_dp_clk_period / 32; -- the PLL can output clocks with phase shifts of 360/32 = 11.25 degrees
+ -- = 4
+ constant c_wideband_factor : natural := c_dp_factor;
+
+ -- 50 MHz
+ constant c_mm_clk_period : time := 20 ns;
+ -- 800 MSps
+ constant c_sample_period : time := 1250 ps;
+ -- 200 MHz external reference clock for data path processing
+ constant c_dp_clk_period : time := c_sample_period * c_wideband_factor;
+ -- the PLL can output clocks with phase shifts of 360/32 = 11.25 degrees
+ constant c_dp_phs_clk_step : time := c_dp_clk_period / 32;
constant c_dp_phs_clk_div : natural := 32;
- constant c_ana_diff : natural := 16; -- analogue offset value between the port A, B, C, D, use 0 to have same data on all ports
+ -- analogue offset value between the port A, B, C, D, use 0 to have same data on all ports
+ constant c_ana_diff : natural := 16;
-- ADC
- signal ANA_DAT : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- Common ADC reference data source
- signal ANA_A : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port A
- signal ANA_B : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port B
- signal ANA_C : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port C
- signal ANA_D : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port D
- signal SCLK : std_logic := '1'; -- central sample clock = 800 MHz
- signal DCLK_AB : std_logic; -- digital lvds clock = 400 MHz (DDR)
- signal DCLK_CD : std_logic; -- digital lvds clock = 400 MHz (DDR)
- signal DCLK_RST_AB : std_logic; -- synchronise digital lvds clock
- signal DCLK_RST_CD : std_logic; -- synchronise digital lvds clock
+ -- Common ADC reference data source
+ signal ANA_DAT : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port A
+ signal ANA_A : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port B
+ signal ANA_B : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port C
+ signal ANA_C : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port D
+ signal ANA_D : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- central sample clock = 800 MHz
+ signal SCLK : std_logic := '1';
+ -- digital lvds clock = 400 MHz (DDR)
+ signal DCLK_AB : std_logic;
+ -- digital lvds clock = 400 MHz (DDR)
+ signal DCLK_CD : std_logic;
+ -- synchronise digital lvds clock
+ signal DCLK_RST_AB : std_logic;
+ -- synchronise digital lvds clock
+ signal DCLK_RST_CD : std_logic;
signal DIG_A : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_B : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_C : std_logic_vector(c_ai.port_w - 1 downto 0);
@@ -141,25 +159,32 @@ architecture tb of tb_unb1_bn_capture_input is
signal current_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
signal nof_block_per_sync : std_logic_vector(c_word_w - 1 downto 0);
- signal reg_bsn_source_mosi : t_mem_mosi := c_mem_mosi_rst; -- Start a BSN timestamp
+ -- Start a BSN timestamp
+ signal reg_bsn_source_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_bsn_source_miso : t_mem_miso;
-- MM bsn schedule WG
- signal reg_bsn_scheduler_wg_mosi : t_mem_mosi := c_mem_mosi_rst; -- Schedule WG restart at a BSN, read current BSN
+ -- Schedule WG restart at a BSN, read current BSN
+ signal reg_bsn_scheduler_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_bsn_scheduler_wg_miso : t_mem_miso;
-- MM aduh quad
signal aduh_ab_locked : std_logic_vector(c_word_w - 1 downto 0);
signal aduh_cd_locked : std_logic_vector(c_word_w - 1 downto 0);
- signal reg_adc_quad_mosi : t_mem_mosi := c_mem_mosi_rst; -- ADUH locked status and pattern verify for two half ADUs so 4 ADC inputs A, B, C and D
+ -- ADUH locked status and pattern verify for two half ADUs so 4 ADC inputs A, B, C and D
+ signal reg_adc_quad_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_adc_quad_miso : t_mem_miso;
-- Wideband waveform generators
- signal reg_wg_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1) := (others => c_mem_mosi_rst); -- = [0:3] = WG ports [A,B,C,D]
- signal reg_wg_miso_arr : t_mem_miso_arr(0 to c_ai.nof_sp - 1); -- = [0:3] = WG ports [A,B,C,D]
- signal ram_wg_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1) := (others => c_mem_mosi_rst); -- = [0:3] = WG ports [A,B,C,D]
- signal ram_wg_miso_arr : t_mem_miso_arr(0 to c_ai.nof_sp - 1); -- = [0:3] = WG ports [A,B,C,D]
+ -- = [0:3] = WG ports [A,B,C,D]
+ signal reg_wg_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1) := (others => c_mem_mosi_rst);
+ -- = [0:3] = WG ports [A,B,C,D]
+ signal reg_wg_miso_arr : t_mem_miso_arr(0 to c_ai.nof_sp - 1);
+ -- = [0:3] = WG ports [A,B,C,D]
+ signal ram_wg_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1) := (others => c_mem_mosi_rst);
+ -- = [0:3] = WG ports [A,B,C,D]
+ signal ram_wg_miso_arr : t_mem_miso_arr(0 to c_ai.nof_sp - 1);
signal ram_wg_mosi_sel : t_mem_mosi;
signal ram_wg_miso_sel : t_mem_miso;
signal ram_wg_sel : natural;
@@ -167,27 +192,35 @@ architecture tb of tb_unb1_bn_capture_input is
signal ram_wg_rdval : std_logic;
-- Data monitor buffers
- signal stat_mean_sum : t_slv_64_arr(0 to c_ai.nof_sp - 1); -- use fixed 64 bit sum width, expected value for sinus ~ 0
- signal stat_power_sum : t_slv_64_arr(0 to c_ai.nof_sp - 1); -- use fixed 64 bit sum width, expected value for sinus ~ (Amplitude**2)/2 * c_bn_capture.sp.nof_samples_per_sync = 117**2 * 48 * 1024 = 396386304
- signal exp_mean_sum : t_slv_64_arr(0 to c_ai.nof_sp - 1); -- exact expected mean sum for Fs/16 full scale sinus = 0
- signal exp_power_sum : t_slv_64_arr(0 to c_ai.nof_sp - 1); -- exact expected power sum for Fs/16 full scale sinus = [4*(49**2 + 90**2 + 117**2) + 2*(0**2 + 127**2)] * 48/16 * 1024 = 396343296
-
- signal reg_mon_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1) := (others => c_mem_mosi_rst); -- = [0:3] read only access to the data monitor mean sums and power sums [A,B,C,D]
+ -- use fixed 64 bit sum width, expected value for sinus ~ 0
+ signal stat_mean_sum : t_slv_64_arr(0 to c_ai.nof_sp - 1);
+ -- use fixed 64 bit sum width, expected value for sinus ~ (Amplitude**2)/2 * c_bn_capture.sp.nof_samples_per_sync = 117**2 * 48 * 1024 = 396386304
+ signal stat_power_sum : t_slv_64_arr(0 to c_ai.nof_sp - 1);
+ -- exact expected mean sum for Fs/16 full scale sinus = 0
+ signal exp_mean_sum : t_slv_64_arr(0 to c_ai.nof_sp - 1);
+ -- exact expected power sum for Fs/16 full scale sinus = [4*(49**2 + 90**2 + 117**2) + 2*(0**2 + 127**2)] * 48/16 * 1024 = 396343296
+ signal exp_power_sum : t_slv_64_arr(0 to c_ai.nof_sp - 1);
+
+ -- = [0:3] read only access to the data monitor mean sums and power sums [A,B,C,D]
+ signal reg_mon_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1) := (others => c_mem_mosi_rst);
signal reg_mon_miso_arr : t_mem_miso_arr(0 to c_ai.nof_sp - 1);
- signal ram_mon_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1) := (others => c_mem_mosi_rst); -- = [0:3] read only access to the data monitor buffers [A,B,C,D]
+ -- = [0:3] read only access to the data monitor buffers [A,B,C,D]
+ signal ram_mon_mosi_arr : t_mem_mosi_arr(0 to c_ai.nof_sp - 1) := (others => c_mem_mosi_rst);
signal ram_mon_miso_arr : t_mem_miso_arr(0 to c_ai.nof_sp - 1);
signal ram_mon_mosi_sel : t_mem_mosi;
signal ram_mon_miso_sel : t_mem_miso;
signal ram_mon_sel : natural;
signal ram_mon_rddata : std_logic_vector(c_ram_mon_dat_w - 1 downto 0);
signal ram_mon_rdval : std_logic;
- signal MCLK : std_logic := '1'; -- MCLK is 4 times mm_clk, similar as SCLK and dp_clk
+ -- MCLK is 4 times mm_clk, similar as SCLK and dp_clk
+ signal MCLK : std_logic := '1';
signal ram_mon_cnt : natural;
signal ram_mon_sample : std_logic_vector(c_ai.port_w - 1 downto 0);
signal ram_mon_sample_val : std_logic;
-- Signal paths
- signal sp_sosi_arr : t_dp_sosi_arr(0 to c_ai.nof_sp - 1); -- = [0:3] = Signal Paths [A,B,C,D]
+ -- = [0:3] = Signal Paths [A,B,C,D]
+ signal sp_sosi_arr : t_dp_sosi_arr(0 to c_ai.nof_sp - 1);
signal sp_siso_arr : t_dp_siso_arr(0 to c_ai.nof_sp - 1);
begin
gen_rdy : for I in 0 to c_ai.nof_sp - 1 generate
@@ -195,11 +228,15 @@ begin
end generate;
mm_rst <= '1', '0' after c_mm_clk_period * 10;
- dp_rst <= '1', '0' after c_dp_clk_period * 20; -- Release dp_rst after mm_rst
-
- mm_clk <= not mm_clk or tb_end after c_mm_clk_period / 2; -- MM clock (125 MHz)
- dp_clk <= not dp_clk or tb_end after c_dp_clk_period / 2; -- DP clock (200 MHz)
- dp_phs_clk <= not dp_phs_clk or tb_end after c_dp_clk_period * c_dp_phs_clk_div / 2; -- DP phase clock
+ -- Release dp_rst after mm_rst
+ dp_rst <= '1', '0' after c_dp_clk_period * 20;
+
+ -- MM clock (125 MHz)
+ mm_clk <= not mm_clk or tb_end after c_mm_clk_period / 2;
+ -- DP clock (200 MHz)
+ dp_clk <= not dp_clk or tb_end after c_dp_clk_period / 2;
+ -- DP phase clock
+ dp_phs_clk <= not dp_phs_clk or tb_end after c_dp_clk_period * c_dp_phs_clk_div / 2;
dp_phs_clk_vec <= transport (others => dp_phs_clk) after c_dp_phs_clk_step;
tb_end <= '0', verify_stat_done and ram_wg_stimuli_done and ram_mon_stimuli_done after c_mm_clk_period * 100;
@@ -238,8 +275,10 @@ begin
-- * address 2, 3
-- mm_bs_init_bsn : BSN[47:0]
proc_mem_mm_bus_wr(2, 16#00000007#, mm_clk, reg_bsn_source_mosi);
- proc_mem_mm_bus_wr(3, 16#00000000#, mm_clk, reg_bsn_source_mosi); -- Init BSN = 7
- proc_mem_mm_bus_wr(0, 16#00000001#, mm_clk, reg_bsn_source_mosi); -- Enable BS
+ -- Init BSN = 7
+ proc_mem_mm_bus_wr(3, 16#00000000#, mm_clk, reg_bsn_source_mosi);
+ -- Enable BS
+ proc_mem_mm_bus_wr(0, 16#00000001#, mm_clk, reg_bsn_source_mosi);
-- * address 1: Nof block per sync
proc_mem_mm_bus_rd(1, mm_clk, reg_bsn_source_mosi);
@@ -250,11 +289,16 @@ begin
proc_common_wait_some_cycles(mm_clk, 1000);
-- Prepare for data path restart at next PPS and init BSN = 0
- proc_mem_mm_bus_wr(2, 0, mm_clk, reg_bsn_source_mosi); -- Init BSN = 0
- proc_mem_mm_bus_wr(3, 0, mm_clk, reg_bsn_source_mosi); -- Init BSN = 0
- proc_mem_mm_bus_wr(0, 16#00000000#, mm_clk, reg_bsn_source_mosi); -- Disable the BS output to prepare for restart with new BSN at the next PPS
- proc_common_wait_some_cycles(mm_clk, 100); -- wait for at least one block
- proc_mem_mm_bus_wr(0, 16#00000003#, mm_clk, reg_bsn_source_mosi); -- Keep the BS enabled and restart the time stamp at the next PPS
+ -- Init BSN = 0
+ proc_mem_mm_bus_wr(2, 0, mm_clk, reg_bsn_source_mosi);
+ -- Init BSN = 0
+ proc_mem_mm_bus_wr(3, 0, mm_clk, reg_bsn_source_mosi);
+ -- Disable the BS output to prepare for restart with new BSN at the next PPS
+ proc_mem_mm_bus_wr(0, 16#00000000#, mm_clk, reg_bsn_source_mosi);
+ -- wait for at least one block
+ proc_common_wait_some_cycles(mm_clk, 100);
+ -- Keep the BS enabled and restart the time stamp at the next PPS
+ proc_mem_mm_bus_wr(0, 16#00000003#, mm_clk, reg_bsn_source_mosi);
----------------------------------------------------------------------------
-- ADUH activated so the data path now carries ADU data
@@ -264,19 +308,23 @@ begin
-- . phase[15:0]
-- . freq[30:0]
-- . ampl[16:0]
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(0)); -- mode off, nof_sample
+ -- mode off, nof_sample
+ proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(0));
proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(1));
proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(2));
proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(3));
- proc_mem_mm_bus_wr(1, integer( 0.0 * c_diag_wg_phase_unit), mm_clk, reg_wg_mosi_arr(0)); -- phase offset in degrees
+ -- phase offset in degrees
+ proc_mem_mm_bus_wr(1, integer( 0.0 * c_diag_wg_phase_unit), mm_clk, reg_wg_mosi_arr(0));
proc_mem_mm_bus_wr(1, integer( 90.0 * c_diag_wg_phase_unit), mm_clk, reg_wg_mosi_arr(1));
proc_mem_mm_bus_wr(1, integer(180.0 * c_diag_wg_phase_unit), mm_clk, reg_wg_mosi_arr(2));
proc_mem_mm_bus_wr(1, integer(270.0 * c_diag_wg_phase_unit), mm_clk, reg_wg_mosi_arr(3));
- proc_mem_mm_bus_wr(2, integer(0.0625 * c_diag_wg_freq_unit), mm_clk, reg_wg_mosi_arr(0)); -- freq = Fs/16 = 800 MSps/16 = 50 MHz sinus
+ -- freq = Fs/16 = 800 MSps/16 = 50 MHz sinus
+ proc_mem_mm_bus_wr(2, integer(0.0625 * c_diag_wg_freq_unit), mm_clk, reg_wg_mosi_arr(0));
proc_mem_mm_bus_wr(2, integer(0.0625 * c_diag_wg_freq_unit), mm_clk, reg_wg_mosi_arr(1));
proc_mem_mm_bus_wr(2, integer(0.0625 * c_diag_wg_freq_unit), mm_clk, reg_wg_mosi_arr(2));
proc_mem_mm_bus_wr(2, integer(0.0625 * c_diag_wg_freq_unit), mm_clk, reg_wg_mosi_arr(3));
- proc_mem_mm_bus_wr(3, integer(1.0 * c_diag_wg_ampl_unit), mm_clk, reg_wg_mosi_arr(0)); -- full scale sinus
+ -- full scale sinus
+ proc_mem_mm_bus_wr(3, integer(1.0 * c_diag_wg_ampl_unit), mm_clk, reg_wg_mosi_arr(0));
proc_mem_mm_bus_wr(3, integer(1.0 * c_diag_wg_ampl_unit), mm_clk, reg_wg_mosi_arr(1));
proc_mem_mm_bus_wr(3, integer(1.0 * c_diag_wg_ampl_unit), mm_clk, reg_wg_mosi_arr(2));
proc_mem_mm_bus_wr(3, integer(1.0 * c_diag_wg_ampl_unit), mm_clk, reg_wg_mosi_arr(3));
@@ -285,26 +333,31 @@ begin
proc_common_wait_some_cycles(mm_clk, 1000);
-- Issue a PPS pulse to restart the BS due to the pending mm_bs_restart_evt
- wait until rising_edge(dp_clk); -- to dp_clk domain
+ -- to dp_clk domain
+ wait until rising_edge(dp_clk);
dp_pps <= '1';
wait until rising_edge(dp_clk);
dp_pps <= '0';
- wait until rising_edge(mm_clk); -- back to mm_clk domain
+ -- back to mm_clk domain
+ wait until rising_edge(mm_clk);
----------------------------------------------------------------------------
-- Enable WG, so the data path will carry WG data
----------------------------------------------------------------------------
-- Enable calc mode
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 1, mm_clk, reg_wg_mosi_arr(0)); -- mode calc, nof_sample
+ -- mode calc, nof_sample
+ proc_mem_mm_bus_wr(0, 1024 * 2**16 + 1, mm_clk, reg_wg_mosi_arr(0));
proc_mem_mm_bus_wr(0, 1024 * 2**16 + 1, mm_clk, reg_wg_mosi_arr(1));
proc_mem_mm_bus_wr(0, 1024 * 2**16 + 1, mm_clk, reg_wg_mosi_arr(2));
proc_mem_mm_bus_wr(0, 1024 * 2**16 + 1, mm_clk, reg_wg_mosi_arr(3));
-- Write BSN scheduler to trigger start of WG at specific block
v_bsn := c_bsn_schedule_wg_on;
- proc_mem_mm_bus_wr(0, v_bsn, mm_clk, reg_bsn_scheduler_wg_mosi); -- first write low then high part
- proc_mem_mm_bus_wr(1, 0, mm_clk, reg_bsn_scheduler_wg_mosi); -- assume v_bsn < 2**31-1
+ -- first write low then high part
+ proc_mem_mm_bus_wr(0, v_bsn, mm_clk, reg_bsn_scheduler_wg_mosi);
+ -- assume v_bsn < 2**31-1
+ proc_mem_mm_bus_wr(1, 0, mm_clk, reg_bsn_scheduler_wg_mosi);
-- Read aduh locked status for AB, CD to set initial stable reference moment
proc_mem_mm_bus_rd(0, mm_clk, reg_adc_quad_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk); aduh_ab_locked <= reg_adc_quad_miso.rddata(31 downto 0);
@@ -355,7 +408,8 @@ begin
end loop;
-- Disable WG takes effect immediatly
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(0)); -- mode off, nof_sample
+ -- mode off, nof_sample
+ proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(0));
proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(1));
proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(2));
proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(3));
@@ -363,7 +417,8 @@ begin
-- Write scheduler BSN to trigger WG at specific block (no effect, because WG off already takes effect immediatly)
v_bsn := TO_UINT(current_bsn) + 2;
proc_mem_mm_bus_wr(0, v_bsn, mm_clk, reg_bsn_scheduler_wg_mosi);
- proc_mem_mm_bus_wr(1, 0, mm_clk, reg_bsn_scheduler_wg_mosi); -- assume v_bsn < 2**31-1
+ -- assume v_bsn < 2**31-1
+ proc_mem_mm_bus_wr(1, 0, mm_clk, reg_bsn_scheduler_wg_mosi);
-- Continue forever with WG data and keep reading the current BSN
while true loop
@@ -388,8 +443,10 @@ begin
proc_common_wait_some_cycles(mm_clk, 1);
end loop;
- exp_mean_sum <= (others => TO_UVEC( 0, 64)); -- exact expected mean sum for Fs/16 full scale sinus = 0
- exp_power_sum <= (others => TO_UVEC(396343296, 64)); -- exact expected power sum for Fs/16 full scale sinus = [4*(49**2 + 90**2 + 117**2) + 2*(0**2 + 127**2)] * 48/16 * 1024 = 396343296
+ -- exact expected mean sum for Fs/16 full scale sinus = 0
+ exp_mean_sum <= (others => TO_UVEC( 0, 64));
+ -- exact expected power sum for Fs/16 full scale sinus = [4*(49**2 + 90**2 + 117**2) + 2*(0**2 + 127**2)] * 48/16 * 1024 = 396343296
+ exp_power_sum <= (others => TO_UVEC(396343296, 64));
proc_common_wait_some_cycles(mm_clk, 1);
for I in 0 to c_ai.nof_sp - 1 loop
assert stat_mean_sum(I) = exp_mean_sum(I) report "Wrong mean sum value for sinus" severity ERROR;
@@ -421,11 +478,14 @@ begin
-- Read the RAM waveform buffer for all 4 wideband waveform generators
for I in 0 to c_ai.nof_sp - 1 loop
ram_wg_sel <= I;
- proc_common_wait_some_cycles(mm_clk, 100); -- wait some time between the RAM WG buffers to easy recognition in the Wave window
+ -- wait some time between the RAM WG buffers to easy recognition in the Wave window
+ proc_common_wait_some_cycles(mm_clk, 100);
for J in 0 to c_ram_wg_size-1 loop
- proc_mem_mm_bus_rd(J, mm_clk, ram_wg_mosi_sel); -- read request, result will be available after read latency, use ram_wg_rddata to view it in the Wave window
+ -- read request, result will be available after read latency, use ram_wg_rddata to view it in the Wave window
+ proc_mem_mm_bus_rd(J, mm_clk, ram_wg_mosi_sel);
end loop;
- proc_common_wait_some_cycles(mm_clk, 1); -- extra cycle to release read request
+ -- extra cycle to release read request
+ proc_common_wait_some_cycles(mm_clk, 1);
end loop;
ram_wg_stimuli_done <= '1';
@@ -463,10 +523,13 @@ begin
for I in 0 to c_ai.nof_sp - 1 loop
ram_mon_sel <= I;
for J in 0 to c_ram_mon_size-1 loop
- proc_mem_mm_bus_rd(J, mm_clk, ram_mon_mosi_sel); -- read request, result will be available after read latency, use ram_mon_rddata to view it in the Wave window
+ -- read request, result will be available after read latency, use ram_mon_rddata to view it in the Wave window
+ proc_mem_mm_bus_rd(J, mm_clk, ram_mon_mosi_sel);
end loop;
- proc_common_wait_some_cycles(mm_clk, 1); -- extra cycle to release read request
- proc_common_wait_some_cycles(mm_clk, 100); -- wait some time between the RAM Monitor buffers to easy recognition in the Wave window
+ -- extra cycle to release read request
+ proc_common_wait_some_cycles(mm_clk, 1);
+ -- wait some time between the RAM Monitor buffers to easy recognition in the Wave window
+ proc_common_wait_some_cycles(mm_clk, 100);
end loop;
end loop;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
index f1ac60af9ffc42bc825a84959c8143f0e40f447b..29545f006727e5ac8ab5d3bac399164e8089d262 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
@@ -31,25 +31,32 @@ use unb1_board_lib.unb1_board_pkg.all;
entity node_unb1_bn_terminal_bg is
generic(
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = simulate GX IP, 1 = use fast serial behavioural model
+ -- 0 = simulate GX IP, 1 = use fast serial behavioural model
+ g_sim_level : natural := 0;
-- Application interface
g_use_bg : boolean := true;
-- Terminals interface
g_usr_nof_streams : natural := 16;
- g_usr_data_w : natural := 32; -- im&re
- g_usr_block_len : natural := 96; -- nof complex samples per BG block
- g_usr_block_per : natural := 256; -- block period = block length + gap length
+ -- im&re
+ g_usr_data_w : natural := 32;
+ -- nof complex samples per BG block
+ g_usr_block_len : natural := 96;
+ -- block period = block length + gap length
+ g_usr_block_per : natural := 256;
-- .back
g_use_back : boolean := false;
g_back_nof_serial : natural := 4;
g_back_gx_mbps : natural := 5000;
-- .mesh
g_use_mesh : boolean := true;
- g_mesh_nof_serial : natural := 3; -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
+ -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
+ g_mesh_nof_serial : natural := 3;
g_mesh_gx_mbps : natural := 5000;
g_mesh_ena_reorder : boolean := true;
- g_mesh_use_rx : boolean := true; -- can be FALSE for BG, use TRUE to support for bidirectional TR diagnostics
- g_mesh_mon_select : natural := 0; -- 0 = no data monitor buffers via MM, else see unb_terminals_mesh.vhd
+ -- can be FALSE for BG, use TRUE to support for bidirectional TR diagnostics
+ g_mesh_use_rx : boolean := true;
+ -- 0 = no data monitor buffers via MM, else see unb_terminals_mesh.vhd
+ g_mesh_mon_select : natural := 0;
g_mesh_mon_nof_words : natural := 1024;
g_mesh_mon_use_sync : boolean := true;
-- Auxiliary Interface
@@ -57,17 +64,25 @@ entity node_unb1_bn_terminal_bg is
);
port(
-- System
- chip_id : in std_logic_vector(g_aux.chip_id_w - 1 downto 0); -- [2:0]
- bck_id : in std_logic_vector(c_unb1_board_nof_uniboard_w - 1 downto 0); -- [7:3]; only [1:0] required to index boards 3:0 in a subrack
+ -- [2:0]
+ chip_id : in std_logic_vector(g_aux.chip_id_w - 1 downto 0);
+ -- [7:3]; only [1:0] required to index boards 3:0 in a subrack
+ bck_id : in std_logic_vector(c_unb1_board_nof_uniboard_w - 1 downto 0);
mm_rst : in std_logic;
- mm_clk : in std_logic; -- 50 MHz from xo_clk PLL in SOPC system
+ -- 50 MHz from xo_clk PLL in SOPC system
+ mm_clk : in std_logic;
dp_rst : in std_logic;
- dp_clk : in std_logic; -- 200 MHz from CLK system clock
- dp_pps : in std_logic; -- external PPS pulse in dp_clk domain
- tr_mesh_clk : in std_logic := '0'; -- 156.25 MHz from SB_CLK transceiver clock
- tr_back_clk : in std_logic := '0'; -- 156.25 MHz from SA_CLK transceiver clock
- cal_clk : in std_logic; -- 40 MHz from xo_clk PLL in SOPC system
+ -- 200 MHz from CLK system clock
+ dp_clk : in std_logic;
+ -- external PPS pulse in dp_clk domain
+ dp_pps : in std_logic;
+ -- 156.25 MHz from SB_CLK transceiver clock
+ tr_mesh_clk : in std_logic := '0';
+ -- 156.25 MHz from SA_CLK transceiver clock
+ tr_back_clk : in std_logic := '0';
+ -- 40 MHz from xo_clk PLL in SOPC system
+ cal_clk : in std_logic;
-- Streaming data input when g_use_bg = FALSE
in_sosi_arr : in t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
@@ -94,24 +109,32 @@ entity node_unb1_bn_terminal_bg is
ram_mesh_diag_data_buf_miso : out t_mem_miso;
-- Mesh serial interface (tr_nonbonded)
- mesh_tx_serial_2arr : out t_unb1_board_mesh_sl_2arr; -- Tx
- mesh_rx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0')); -- Rx support for diagnostics
+ -- Tx
+ mesh_tx_serial_2arr : out t_unb1_board_mesh_sl_2arr;
+ -- Rx support for diagnostics
+ mesh_rx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0'));
-- Back serial interface (tr_nonbonded)
- back_tx_serial_2arr : out t_unb1_board_back_sl_2arr; -- Tx
- back_rx_serial_2arr : in t_unb1_board_back_sl_2arr := (others => (others => '0')) -- Rx
+ -- Tx
+ back_tx_serial_2arr : out t_unb1_board_back_sl_2arr;
+ -- Rx
+ back_rx_serial_2arr : in t_unb1_board_back_sl_2arr := (others => (others => '0'))
);
end node_unb1_bn_terminal_bg;
architecture str of node_unb1_bn_terminal_bg is
-- Terminals
- constant c_mesh_usr_nof_input : natural := g_usr_nof_streams / c_unb1_board_nof_fn; -- 16 / 4 = 4
+ -- 16 / 4 = 4
+ constant c_mesh_usr_nof_input : natural := g_usr_nof_streams / c_unb1_board_nof_fn;
- constant c_back_usr_nof_input : natural := g_usr_nof_streams / c_unb1_board_nof_uniboard; -- 16 / 4 = 4
+ -- 16 / 4 = 4
+ constant c_back_usr_nof_input : natural := g_usr_nof_streams / c_unb1_board_nof_uniboard;
- constant c_rx_timeout_w : natural := 0; -- ceil_log2(g_usr_block_per); -- uth_rx timeout_cnt
+ -- ceil_log2(g_usr_block_per); -- uth_rx timeout_cnt
+ constant c_rx_timeout_w : natural := 0;
- signal bg_siso_arr : t_dp_siso_arr(g_usr_nof_streams - 1 downto 0); -- for XON/OFF flow control
+ -- for XON/OFF flow control
+ signal bg_siso_arr : t_dp_siso_arr(g_usr_nof_streams - 1 downto 0);
signal bg_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
signal bg_siso_2arr : t_unb1_board_back_siso_2arr;
@@ -195,7 +218,8 @@ begin
g_sim => g_sim,
g_sim_level => g_sim_level,
-- System
- g_nof_bus => c_unb1_board_nof_uniboard, -- = 4 Uniboard in subrack, this UniBoard and 3 other UniBoards, so each UniBoard can be indexed by logical index 3:0
+ -- = 4 Uniboard in subrack, this UniBoard and 3 other UniBoards, so each UniBoard can be indexed by logical index 3:0
+ g_nof_bus => c_unb1_board_nof_uniboard,
-- User
g_usr_use_complex => true,
g_usr_data_w => g_usr_data_w,
@@ -208,7 +232,8 @@ begin
-- Tx
g_tx_input_use_fifo => true,
-- Rx
- g_rx_output_use_fifo => false, -- no need for Rx output FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ -- no need for Rx output FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_use_fifo => false,
g_rx_timeout_w => c_rx_timeout_w
)
port map (
@@ -230,8 +255,10 @@ begin
rx_usr_sosi_2arr => back_rx_usr_sosi_2arr,
-- Serial (tr_nonbonded)
- tx_serial_2arr => back_tx_serial_2arr, -- Tx
- rx_serial_2arr => back_rx_serial_2arr, -- Rx
+ -- Tx
+ tx_serial_2arr => back_tx_serial_2arr,
+ -- Rx
+ rx_serial_2arr => back_rx_serial_2arr,
-- MM Control
reg_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
@@ -258,7 +285,8 @@ begin
g_sim_level => g_sim_level,
-- System
g_node_type => e_bn,
- g_nof_bus => c_unb1_board_nof_fn, -- 4 to 4 nodes in mesh
+ -- 4 to 4 nodes in mesh
+ g_nof_bus => c_unb1_board_nof_fn,
-- User
g_usr_use_complex => true,
g_usr_data_w => g_usr_data_w,
@@ -270,11 +298,15 @@ begin
g_phy_rx_fifo_size => c_bram_m9k_fifo_depth,
g_phy_ena_reorder => g_mesh_ena_reorder,
-- Tx
- g_use_tx => true, -- user Tx must be TRUE for BG in BN,
- g_tx_input_use_fifo => true, -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ -- user Tx must be TRUE for BG in BN,
+ g_use_tx => true,
+ -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ g_tx_input_use_fifo => true,
-- Rx
- g_use_rx => g_mesh_use_rx, -- optionally do support diag Rx
- g_rx_output_use_fifo => false, -- no user Rx
+ -- optionally do support diag Rx
+ g_use_rx => g_mesh_use_rx,
+ -- no user Rx
+ g_rx_output_use_fifo => false,
-- Monitoring
g_mon_select => g_mesh_mon_select,
g_mon_nof_words => g_mesh_mon_nof_words,
@@ -293,11 +325,14 @@ begin
-- User interface (4 nodes)(4 input streams)
tx_usr_siso_2arr => mesh_tx_usr_siso_2arr,
- tx_usr_sosi_2arr => mesh_tx_usr_sosi_2arr, -- Tx (user Rx from FN to BN is unused)
+ -- Tx (user Rx from FN to BN is unused)
+ tx_usr_sosi_2arr => mesh_tx_usr_sosi_2arr,
-- Serial mesh interface (tr_nonbonded)
- tx_serial_2arr => mesh_tx_serial_2arr, -- Tx
- rx_serial_2arr => mesh_rx_serial_2arr, -- Rx
+ -- Tx
+ tx_serial_2arr => mesh_tx_serial_2arr,
+ -- Rx
+ rx_serial_2arr => mesh_rx_serial_2arr,
-- MM Control
reg_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
index a5254c63ff944c2e7aa6b0f5e8f60ce9605a1a86..f33248571fcb4fd182d9513c684db2244ca29f56 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
@@ -32,20 +32,30 @@ entity unb1_bn_terminal_bg is
generic (
-- General
g_sim : boolean := false;
- g_rev_multi_unb : boolean := false; -- Set to TRUE by Quartus revision bn_terminal_bg_rev_multi
- g_design_name : string := "unb1_bn_terminal_bg"; -- Set to "bn_terminal_bg_rev_multi_unb" by revision bn_terminal_bg_rev_multi
+ -- Set to TRUE by Quartus revision bn_terminal_bg_rev_multi
+ g_rev_multi_unb : boolean := false;
+ -- Set to "bn_terminal_bg_rev_multi_unb" by revision bn_terminal_bg_rev_multi
+ g_design_name : string := "unb1_bn_terminal_bg";
g_design_note : string := "UNUSED";
- g_stamp_date : natural := 0; -- Date (YYYYMMDD)
- g_stamp_time : natural := 0; -- Time (HHMMSS)
- g_stamp_svn : natural := 0 -- SVN revision
+ -- Date (YYYYMMDD)
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS)
+ g_stamp_time : natural := 0;
+ -- SVN revision
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -62,8 +72,10 @@ entity unb1_bn_terminal_bg is
ETH_SGOUT : out std_logic;
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- TR clock BN-BI (backplane)
- SB_CLK : in std_logic := '0'; -- TR clock FN-BN (mesh)
+ -- TR clock BN-BI (backplane)
+ SA_CLK : in std_logic := '0';
+ -- TR clock FN-BN (mesh)
+ SB_CLK : in std_logic := '0';
-- Serial I/O
FN_BN_0_TX : out std_logic_vector(c_unb1_board_tr_mesh.bus_w - 1 downto 0);
@@ -85,7 +97,8 @@ entity unb1_bn_terminal_bg is
end unb1_bn_terminal_bg;
architecture str of unb1_bn_terminal_bg is
- constant c_fw_version : t_unb1_board_fw_version := (1, 0); -- firmware version x.y
+ -- firmware version x.y
+ constant c_fw_version : t_unb1_board_fw_version := (1, 0);
-- Use PHY Interface
-- TYPE t_c_unb_use_phy IS RECORD
-- eth1g : NATURAL;
@@ -106,17 +119,23 @@ architecture str of unb1_bn_terminal_bg is
constant c_usr_nof_streams : natural := 16;
constant c_usr_block_len : natural := 96;
- constant c_ram_diag_bg_addr_w : natural := ceil_log2(c_usr_nof_streams * pow2(ceil_log2(c_usr_block_len))); -- Total addressable nof words required: 16 streams * (128 words / block_gen).
+ -- Total addressable nof words required: 16 streams * (128 words / block_gen).
+ constant c_ram_diag_bg_addr_w : natural := ceil_log2(c_usr_nof_streams * pow2(ceil_log2(c_usr_block_len)));
-- Mesh settings
constant c_use_mesh : boolean := c_use_phy.tr_mesh = 1;
- constant c_mesh_nof_serial : natural := 3; -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
- constant c_mesh_use_rx : boolean := true; -- can be FALSE for BG functionality, use TRUE to support for bidirectional TR diagnostics
+ -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
+ constant c_mesh_nof_serial : natural := 3;
+ -- can be FALSE for BG functionality, use TRUE to support for bidirectional TR diagnostics
+ constant c_mesh_use_rx : boolean := true;
constant c_mesh_gx_mbps : natural := 5000;
- constant c_mesh_mon_select : natural := 5; -- > 0 = enable SOSI data buffers monitor via MM
- constant c_mesh_mon_nof_words : natural := c_unb1_board_peripherals_mm_reg_default.ram_diag_db_buf_size; -- = 1024
- constant c_mesh_mon_use_sync : boolean := true; -- when TRUE use dp_pps to trigger the data buffer capture, else new data capture after read access of last data word
+ -- > 0 = enable SOSI data buffers monitor via MM
+ constant c_mesh_mon_select : natural := 5;
+ -- = 1024
+ constant c_mesh_mon_nof_words : natural := c_unb1_board_peripherals_mm_reg_default.ram_diag_db_buf_size;
+ -- when TRUE use dp_pps to trigger the data buffer capture, else new data capture after read access of last data word
+ constant c_mesh_mon_use_sync : boolean := true;
-- System
signal cs_sim : std_logic;
@@ -131,8 +150,10 @@ architecture str of unb1_bn_terminal_bg is
signal dp_clk : std_logic;
signal dp_pps : std_logic;
- signal this_chip_id : std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0); -- ID[2:0], so range 0-3 for FN and range 4-7 BN
- signal this_bck_id : std_logic_vector(c_unb1_board_nof_uniboard_w - 1 downto 0); -- ID[7:3]
+ -- ID[2:0], so range 0-3 for FN and range 4-7 BN
+ signal this_chip_id : std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0);
+ -- ID[7:3]
+ signal this_bck_id : std_logic_vector(c_unb1_board_nof_uniboard_w - 1 downto 0);
-- PIOs
signal pout_debug_wave : std_logic_vector(c_word_w - 1 downto 0);
@@ -152,27 +173,36 @@ architecture str of unb1_bn_terminal_bg is
signal reg_wdi_miso : t_mem_miso;
-- UniBoard I2C sens
- signal reg_unb_sens_mosi : t_mem_mosi; -- mms_unb_sens registers
+ -- mms_unb_sens registers
+ signal reg_unb_sens_mosi : t_mem_mosi;
signal reg_unb_sens_miso : t_mem_miso;
-- eth1g
signal eth1g_tse_clk : std_logic;
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_ram_miso : t_mem_miso;
-- tr_mesh
- signal mesh_tx_serial_2arr : t_unb1_board_mesh_sl_2arr; -- Tx
- signal mesh_rx_serial_2arr : t_unb1_board_mesh_sl_2arr; -- Rx support for diagnostics
+ -- Tx
+ signal mesh_tx_serial_2arr : t_unb1_board_mesh_sl_2arr;
+ -- Rx support for diagnostics
+ signal mesh_rx_serial_2arr : t_unb1_board_mesh_sl_2arr;
-- tr_back
- signal back_tx_serial_2arr : t_unb1_board_back_sl_2arr; -- Tx
- signal back_rx_serial_2arr : t_unb1_board_back_sl_2arr; -- Rx
+ -- Tx
+ signal back_tx_serial_2arr : t_unb1_board_back_sl_2arr;
+ -- Rx
+ signal back_rx_serial_2arr : t_unb1_board_back_sl_2arr;
-- MM block generator register for BN-FN streams[0:15] = [0,4,8,12, 1,5,9,13, 2,6,10,14, 3,7,11,15]
signal reg_diag_bg_mosi : t_mem_mosi := c_mem_mosi_rst;
@@ -207,11 +237,15 @@ begin
u_sopc : entity work.sopc_unb1_bn_terminal_bg
port map (
-- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ -- PLL reference = 25 MHz from ETH_clk pin
+ clk_0 => xo_clk,
reset_n => xo_rst_n,
- mm_clk => mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+ -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ mm_clk => mm_clk,
+ -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ cal_clk => cal_clk,
+ -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+ tse_clk => eth1g_tse_clk,
-- the_altpll_0
areset_to_the_altpll_0 => '0',
@@ -402,7 +436,8 @@ begin
reg_unb_sens_miso => reg_unb_sens_miso,
-- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
index 65c1746710ca576d7336ad7f67c21868b6746d2e..e488d37669bdba6a718689506ac6e619106bc3cb 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
@@ -43,9 +43,12 @@ use diagnostics_lib.tb_diagnostics_trnb_pkg.all;
entity tb_node_unb1_bn_terminal_bg is
generic (
-- Tb
- g_sim_level : natural := 1; -- 0 = simulate GX IP, 1 = use fast serial behavioural model
- g_nof_sync : natural := 2; -- use > c_bst_skip_nof_sync = 1 to also verify the BST once (more sync yield the same BST)
- g_chip_id : natural := 4; -- BN chip ID 4, 5, 6, 7 used in case of multiple tb instances, default BN0 with chip ID 4
+ -- 0 = simulate GX IP, 1 = use fast serial behavioural model
+ g_sim_level : natural := 1;
+ -- use > c_bst_skip_nof_sync = 1 to also verify the BST once (more sync yield the same BST)
+ g_nof_sync : natural := 2;
+ -- BN chip ID 4, 5, 6, 7 used in case of multiple tb instances, default BN0 with chip ID 4
+ g_chip_id : natural := 4;
g_bck_id : natural := 0;
-- Application
g_bf : t_c_bf := c_bf;
@@ -54,18 +57,24 @@ entity tb_node_unb1_bn_terminal_bg is
g_bg_data_file_name : string := "data/bf_in_data";
-- Diagnostics - TRNB
g_diagnostics_en : boolean := false;
- g_diagnostics_init_interval : real := 6.0; -- unit us
- g_diagnostics_on_interval : real := 1.0; -- unit us
- g_diagnostics_off_interval : real := 10.3; -- unit us
+ -- unit us
+ g_diagnostics_init_interval : real := 6.0;
+ -- unit us
+ g_diagnostics_on_interval : real := 1.0;
+ -- unit us
+ g_diagnostics_off_interval : real := 10.3;
-- Terminals interface
-- . back
g_use_back : boolean := false;
-- . mesh
- g_mesh_nof_serial : natural := 3; -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
- g_mesh_use_rx : boolean := false; -- can be FALSE for BG functionality, use TRUE to support for bidirectional TR diagnostics
+ -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
+ g_mesh_nof_serial : natural := 3;
+ -- can be FALSE for BG functionality, use TRUE to support for bidirectional TR diagnostics
+ g_mesh_use_rx : boolean := false;
g_mesh_gx_mbps : natural := 5000;
- g_mesh_mon_select : natural := 0; -- 0 = no Tx terminals monitor via MM, else see unb_terminals_mesh.vhd
+ -- 0 = no Tx terminals monitor via MM, else see unb_terminals_mesh.vhd
+ g_mesh_mon_select : natural := 0;
g_mesh_mon_nof_words : natural := 1024;
g_mesh_mon_use_sync : boolean := true;
g_mesh_ena_reorder : boolean := false
@@ -78,11 +87,14 @@ entity tb_node_unb1_bn_terminal_bg is
dp_pps : in std_logic;
-- Mesh serial interface (tr_nonbonded)
- mesh_tx_serial_2arr : out t_unb1_board_mesh_sl_2arr; -- Tx
- mesh_rx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0')); -- Rx support for diagnostics
+ -- Tx
+ mesh_tx_serial_2arr : out t_unb1_board_mesh_sl_2arr;
+ -- Rx support for diagnostics
+ mesh_rx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0'));
-- Back serial interface (tr_nonbonded)
- back_tx_serial_2arr : out t_unb1_board_back_sl_2arr; -- Tx
+ -- Tx
+ back_tx_serial_2arr : out t_unb1_board_back_sl_2arr;
back_rx_serial_2arr : in t_unb1_board_back_sl_2arr := (others => (others => '0'))
);
end tb_node_unb1_bn_terminal_bg;
@@ -93,10 +105,14 @@ architecture tb of tb_node_unb1_bn_terminal_bg is
constant c_bg_data_file_dat : string := g_bg_data_file_name & ".dat";
constant c_bg_try_re_enable : boolean := false;
- constant c_mm_clk_ps : natural := 1000; -- default is e.g. 8 ns, but use faster mm_clk to speed up simulation by using less c_nof_accum_per_sync
- constant c_dp_clk_ps : natural := 5000; -- 200 MHz
- constant c_cal_clk_ps : natural := 25000; -- 40 MHz
- constant c_tr_clk_ps : natural := 6400; -- 156.25 MHz
+ -- default is e.g. 8 ns, but use faster mm_clk to speed up simulation by using less c_nof_accum_per_sync
+ constant c_mm_clk_ps : natural := 1000;
+ -- 200 MHz
+ constant c_dp_clk_ps : natural := 5000;
+ -- 40 MHz
+ constant c_cal_clk_ps : natural := 25000;
+ -- 156.25 MHz
+ constant c_tr_clk_ps : natural := 6400;
constant c_mm_clk_1us : real := 1000000.0 / real(c_mm_clk_ps);
constant c_mm_clk_period : time := c_mm_clk_ps * 1 ps;
constant c_dp_clk_period : time := c_dp_clk_ps * 1 ps;
@@ -107,16 +123,21 @@ architecture tb of tb_node_unb1_bn_terminal_bg is
constant c_nof_samples_in_packet : natural := g_bf.nof_signal_paths * g_bf.nof_subbands / g_bf.nof_input_streams;
constant c_block_size : natural := g_bf.nof_weights;
constant c_gap : natural := c_block_size - c_nof_samples_in_packet;
- constant c_nof_accum_per_sync : natural := 20 * c_mm_clk_ps / c_dp_clk_ps + 1; -- integration time, account for mm_clk speed versus the dp_clk speed
+ -- integration time, account for mm_clk speed versus the dp_clk speed
+ constant c_nof_accum_per_sync : natural := 20 * c_mm_clk_ps / c_dp_clk_ps + 1;
constant c_dp_run_nof_cycles : natural := (g_nof_sync * c_nof_accum_per_sync + 1) * c_block_size;
- constant c_bsn_init_hi : natural := 0; -- 16#BA98#;
- constant c_bsn_init_lo : natural := 32; -- 16#76543210#;
+ -- 16#BA98#;
+ constant c_bsn_init_hi : natural := 0;
+ -- 16#76543210#;
+ constant c_bsn_init_lo : natural := 32;
constant c_bg_buf_adr_w : natural := ceil_log2(c_nof_samples_in_packet);
-- TRNB diagnostics
- constant c_nof_gx : natural := g_mesh_nof_serial * c_unb1_board_nof_node; -- = 12 = 3 * 4
+ -- = 12 = 3 * 4
+ constant c_nof_gx : natural := g_mesh_nof_serial * c_unb1_board_nof_node;
constant c_nof_gx_mask : natural := 2**c_nof_gx - 1;
- constant c_gx_link_delay : real := 3.0; -- unit us
+ -- unit us
+ constant c_gx_link_delay : real := 3.0;
signal i_tb_end : std_logic;
signal mm_clk : std_logic := '0';
@@ -181,23 +202,33 @@ begin
proc_common_wait_until_high(mm_clk, init_waveforms_done);
-- Set and enable the waveform generators. All generators are controlled by the same registers
- proc_mem_mm_bus_wr(1, c_nof_samples_in_packet, mm_clk, reg_diag_bg_mosi); -- Set the number of samples per block
- proc_mem_mm_bus_wr(2, c_nof_accum_per_sync, mm_clk, reg_diag_bg_mosi); -- Set the number of blocks per sync
- proc_mem_mm_bus_wr(3, c_gap, mm_clk, reg_diag_bg_mosi); -- Set the gapsize
- proc_mem_mm_bus_wr(4, 0, mm_clk, reg_diag_bg_mosi); -- Set the start address of the memory
- proc_mem_mm_bus_wr(5, c_nof_samples_in_packet - 1, mm_clk, reg_diag_bg_mosi); -- Set the end address of the memory
- proc_mem_mm_bus_wr(6, c_bsn_init_lo, mm_clk, reg_diag_bg_mosi); -- Set the BSNInit low value
- proc_mem_mm_bus_wr(7, c_bsn_init_hi, mm_clk, reg_diag_bg_mosi); -- Set the BSNInit high value
- proc_mem_mm_bus_wr(0, 3, mm_clk, reg_diag_bg_mosi); -- Enable the WG to start at PPS
+ -- Set the number of samples per block
+ proc_mem_mm_bus_wr(1, c_nof_samples_in_packet, mm_clk, reg_diag_bg_mosi);
+ -- Set the number of blocks per sync
+ proc_mem_mm_bus_wr(2, c_nof_accum_per_sync, mm_clk, reg_diag_bg_mosi);
+ -- Set the gapsize
+ proc_mem_mm_bus_wr(3, c_gap, mm_clk, reg_diag_bg_mosi);
+ -- Set the start address of the memory
+ proc_mem_mm_bus_wr(4, 0, mm_clk, reg_diag_bg_mosi);
+ -- Set the end address of the memory
+ proc_mem_mm_bus_wr(5, c_nof_samples_in_packet - 1, mm_clk, reg_diag_bg_mosi);
+ -- Set the BSNInit low value
+ proc_mem_mm_bus_wr(6, c_bsn_init_lo, mm_clk, reg_diag_bg_mosi);
+ -- Set the BSNInit high value
+ proc_mem_mm_bus_wr(7, c_bsn_init_hi, mm_clk, reg_diag_bg_mosi);
+ -- Enable the WG to start at PPS
+ proc_mem_mm_bus_wr(0, 3, mm_clk, reg_diag_bg_mosi);
proc_common_wait_until_high(dp_clk, dp_pps);
-- Optionally try disable and re-enable BG to verify that this occurs at block boundaries
if c_bg_try_re_enable = true then
proc_common_wait_some_cycles(mm_clk, 1000);
- proc_mem_mm_bus_wr(0, 0, mm_clk, reg_diag_bg_mosi); -- Disable the BG
+ -- Disable the BG
+ proc_mem_mm_bus_wr(0, 0, mm_clk, reg_diag_bg_mosi);
proc_common_wait_some_cycles(mm_clk, 500);
- proc_mem_mm_bus_wr(0, 1, mm_clk, reg_diag_bg_mosi); -- Re-enable the BG to start immediately
+ -- Re-enable the BG to start immediately
+ proc_mem_mm_bus_wr(0, 1, mm_clk, reg_diag_bg_mosi);
end if;
-- Run time
@@ -216,7 +247,8 @@ begin
generic map(
g_nof_streams => g_bf.nof_input_streams,
g_buf_dat_w => c_nof_complex * g_bf.in_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => g_bg_data_file_index_arr,
g_file_name_prefix => g_bg_data_file_name
)
@@ -299,8 +331,10 @@ begin
)
port map (
-- System
- chip_id => TO_UVEC(g_chip_id, c_unb1_board_nof_chip_w), -- BN chip ID 4, 5, 6, 7
- bck_id => TO_UVEC(g_bck_id, c_unb1_board_nof_uniboard_w), -- Backplane ID 0,1,2,3
+ -- BN chip ID 4, 5, 6, 7
+ chip_id => TO_UVEC(g_chip_id, c_unb1_board_nof_chip_w),
+ -- Backplane ID 0,1,2,3
+ bck_id => TO_UVEC(g_bck_id, c_unb1_board_nof_uniboard_w),
mm_rst => mm_rst,
mm_clk => mm_clk,
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
index b521c00a23e2e0e0dbfa5383d9f9316d6aa5322c..46475e8d3575cfb0cb634fd21ee7b87e379cd287 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
@@ -41,15 +41,18 @@ use unb_common_lib.unb_common_pkg.all;
entity tb_tb_node_bn_terminal_bg is
generic (
- g_diagnostics_en : boolean := true; -- when TRUE then alternately insert diagnostics data over the transceivers, else only BG data
+ -- when TRUE then alternately insert diagnostics data over the transceivers, else only BG data
+ g_diagnostics_en : boolean := true;
g_nof_sync : natural := 15
);
end tb_tb_node_bn_terminal_bg;
architecture tb of tb_tb_node_bn_terminal_bg is
- constant c_dp_pps_period : natural := 1024; -- sufficiently long for all nodes to have initialized their TR PHY
+ -- sufficiently long for all nodes to have initialized their TR PHY
+ constant c_dp_pps_period : natural := 1024;
- constant c_mesh_nof_serial : natural := 3; -- need at least 3 to support the 4 input streams from the BG, use 4 to have transparant dp_distibute
+ -- need at least 3 to support the 4 input streams from the BG, use 4 to have transparant dp_distibute
+ constant c_mesh_nof_serial : natural := 3;
constant c_mesh_use_rx : boolean := true or g_diagnostics_en;
constant c_mesh_ena_reorder : boolean := false;
@@ -65,7 +68,8 @@ begin
u_tb_node_bn_terminal_bg : entity work.tb_node_bn_terminal_bg
generic map (
-- Tb
- g_sim_level => 1, -- 0 = simulate GX IP, 1 = use fast serial behavioural model
+ -- 0 = simulate GX IP, 1 = use fast serial behavioural model
+ g_sim_level => 1,
g_nof_sync => g_nof_sync,
g_chip_id => 4,
-- Application
@@ -110,5 +114,6 @@ begin
-- Test bench end
------------------------------------------------------------------------------
- assert not(NOW > 0 ps and tb_end = '1') report "Note: TB END" severity FAILURE; -- need to use FAILURE to stop the simulation, apparently resetting the tr_nonbonded is not enough
+ -- need to use FAILURE to stop the simulation, apparently resetting the tr_nonbonded is not enough
+ assert not(NOW > 0 ps and tb_end = '1') report "Note: TB END" severity FAILURE;
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
index 45beb6d4fd0ed4fb8bb98b369acc4cd213d51c4c..59d07aef2ffccf4251e26b021da13231076cc097 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
@@ -36,7 +36,8 @@ use eth_lib.eth_pkg.all;
entity mmm_unb1_ddr3 is
generic (
- g_sim : boolean := true; -- FALSE: use SOPC; TRUE: use mm_file I/O
+ -- FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim : boolean := true;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
@@ -123,7 +124,8 @@ architecture str of mmm_unb1_ddr3 is
constant c_mm_reg_diag_rx_seq_addr_w : natural := 3;
-- Simulation
- constant c_mm_clk_period : time := 8 ns; -- 500 ps;
+ -- 500 ps;
+ constant c_mm_clk_period : time := 8 ns;
constant c_tse_clk_period : time := 8 ns;
constant c_cal_clk_period : time := 25 ns;
@@ -216,7 +218,8 @@ begin
wait until rising_edge(i_mm_clk);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_dut_control_rx_en, i_mm_clk, eth1g_reg_miso, eth1g_reg_proc_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_dut_control_rx_en, i_mm_clk, eth1g_reg_miso, eth1g_reg_proc_mosi);
mm_bus_switch <= '0';
wait;
@@ -244,11 +247,15 @@ begin
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_ddr3
port map (
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ -- PLL reference = 25 MHz from ETH_clk pin
+ clk_0 => xo_clk,
reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => i_cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+ -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ mm_clk => i_mm_clk,
+ -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ cal_clk => i_cal_clk,
+ -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+ tse_clk => i_tse_clk,
-- the_altpll_0
areset_to_the_altpll_0 => '0',
@@ -291,7 +298,8 @@ begin
-- the_pio_pps
coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1),
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
index 4467803f06ffb303fe56e6f532d212f62415c01b..3fe911b049439ee07edd5730657abee614979406 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
@@ -35,7 +35,8 @@ entity node_unb1_ddr3 is
g_sim : boolean := false;
g_technology : natural := c_tech_select_default;
g_tech_ddr : t_c_tech_ddr;
- g_st_dat_w : natural := 64 -- Any power of two 8..256
+ -- Any power of two 8..256
+ g_st_dat_w : natural := 64
);
port (
-- System
@@ -92,8 +93,10 @@ architecture str of node_unb1_ddr3 is
constant c_rd_data_w : natural := g_st_dat_w;
constant c_data_w : natural := g_st_dat_w;
- constant c_wr_fifo_depth : natural := 1024; -- >=16 , defined at DDR side of the FIFO.
- constant c_rd_fifo_depth : natural := 1024; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
+ -- >=16 , defined at DDR side of the FIFO.
+ constant c_wr_fifo_depth : natural := 1024;
+ -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
+ constant c_rd_fifo_depth : natural := 1024;
constant c_use_bg : boolean := false;
constant c_use_tx_seq : boolean := true;
@@ -105,9 +108,12 @@ architecture str of node_unb1_ddr3 is
signal en_sync : std_logic;
- signal out_siso_arr : t_dp_siso_arr(c_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy); -- Default xon='1'
- signal out_sosi_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0); -- Output SOSI that contains the waveform data
- signal in_siso_arr : t_dp_siso_arr(c_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy); -- Default xon='1'
+ -- Default xon='1'
+ signal out_siso_arr : t_dp_siso_arr(c_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
+ -- Output SOSI that contains the waveform data
+ signal out_sosi_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0);
+ -- Default xon='1'
+ signal in_siso_arr : t_dp_siso_arr(c_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
signal in_sosi_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0);
begin
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
index 80af69d3f773ad7d65ac0ba8e4e2be97b3efcab4..cd70d2afa036e2fc753ab5cf5a402583681f8bf4 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
@@ -37,18 +37,27 @@ entity unb1_ddr3 is
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 4;
-- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
- g_stamp_date : natural := 0; -- Date (YYYYMMDD)
- g_stamp_time : natural := 0; -- Time (HHMMSS)
- g_stamp_svn : natural := 0; -- SVN revision
- g_st_dat_w : natural := 64 -- Any power of two 8..256
+ -- Date (YYYYMMDD)
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS)
+ g_stamp_time : natural := 0;
+ -- SVN revision
+ g_stamp_svn : natural := 0;
+ -- Any power of two 8..256
+ g_st_dat_w : natural := 64
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -75,7 +84,8 @@ architecture str of unb1_ddr3 is
-- Constant definitions for ctrl_unb_common
constant c_design_name : string := "unb1_ddr3";
constant c_design_note : string := "DDR3 reference design";
- constant c_fw_version : t_unb1_board_fw_version := (0, 3); -- firmware version x.y
+ -- firmware version x.y
+ constant c_fw_version : t_unb1_board_fw_version := (0, 3);
-- Use PHY Interface
-- TYPE t_c_unb_use_phy IS RECORD
-- eth1g : NATURAL;
@@ -109,7 +119,8 @@ architecture str of unb1_ddr3 is
signal ddr_ref_rst : std_logic;
- signal this_chip_id : std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0); -- [2:0], so range 0-3 for FN and range 4-7 BN
+ -- [2:0], so range 0-3 for FN and range 4-7 BN
+ signal this_chip_id : std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0);
signal app_led_red : std_logic := '0';
signal app_led_green : std_logic := '1';
@@ -135,12 +146,16 @@ architecture str of unb1_ddr3 is
-- eth1g
signal eth1g_tse_clk : std_logic;
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_ram_miso : t_mem_miso;
-- SIGNAL eth1g_led : t_tech_tse_led;
diff --git a/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
index 55751e463fe336cd8e7c907f3eb39d0f8ab65e8f..0001e33b61e89d84ea947996f10274b48940ba9a 100644
--- a/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
@@ -55,8 +55,10 @@ end tb_unb1_ddr3;
architecture tb of tb_unb1_ddr3 is
-- UniBoard
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Front node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Front node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
@@ -64,10 +66,12 @@ architecture tb of tb_unb1_ddr3 is
constant c_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
- constant c_st_dat_w : natural := 64; -- Any power of two 8..256
+ -- Any power of two 8..256
+ constant c_st_dat_w : natural := 64;
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
+ -- 25 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 40 ns;
constant c_ext_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -99,14 +103,20 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_ext_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
index f2880d95fff355bf58535b3d9a1d9652632edff7..934d47305029104deec3557a3bfa7f425b510b2e 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
@@ -30,8 +30,10 @@ entity tb_unb1_ddr3_reorder_dual_rank is
generic (
g_design_name : string := "unb1_ddr3_reorder_dual_rank";
g_design_note : string := "Reference Reorder";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7; -- Back node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Back node 3
+ g_sim_node_nr : natural := 7;
g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master
);
end tb_unb1_ddr3_reorder_dual_rank;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
index 5622c88c07a81536c2dbca7c7e0000626c3627c6..21ad6dbedf285c9e9df670030915c8bdadbc7ac1 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
@@ -28,26 +28,36 @@ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_ddr3_reorder_dual_rank is
generic (
- g_design_name : string := "unb1_ddr3_reorder_dual_rank"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_ddr3_reorder_dual_rank";
g_design_note : string := "Reference Reorder";
g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 4;
-- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
- g_stamp_date : natural := 0; -- Date (YYYYMMDD)
- g_stamp_time : natural := 0; -- Time (HHMMSS)
- g_stamp_svn : natural := 0; -- SVN revision
- g_use_MB_I : natural := 1; -- 1: use MB_I 0: do not use
+ -- Date (YYYYMMDD)
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS)
+ g_stamp_time : natural := 0;
+ -- SVN revision
+ g_stamp_svn : natural := 0;
+ -- 1: use MB_I 0: do not use
+ g_use_MB_I : natural := 1;
g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
g_aux : t_c_unb1_board_aux := c_unb1_board_aux
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
index 01306cde2b28d4f27ece81f4888cd13afadf67e7..47ab4f4ce94229063c0b061955e0a9fdfcc36691 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
@@ -30,8 +30,10 @@ entity tb_unb1_ddr3_reorder_single_rank is
generic (
g_design_name : string := "unb1_ddr3_reorder_single_rank";
g_design_note : string := "Reference Reorder";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7; -- Back node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Back node 3
+ g_sim_node_nr : natural := 7;
g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master
);
end tb_unb1_ddr3_reorder_single_rank;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
index 5bd73002e062806ac18d0eb832e82573ea720246..1d0f7ba7213a5ed5b14310e69f77ed3cbd031363 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
@@ -28,26 +28,36 @@ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_ddr3_reorder_single_rank is
generic (
- g_design_name : string := "unb1_ddr3_reorder_single_rank"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_ddr3_reorder_single_rank";
g_design_note : string := "Reference Reorder";
g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 4;
-- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
- g_stamp_date : natural := 0; -- Date (YYYYMMDD)
- g_stamp_time : natural := 0; -- Time (HHMMSS)
- g_stamp_svn : natural := 0; -- SVN revision
- g_use_MB_I : natural := 1; -- 1: use MB_I 0: do not use
+ -- Date (YYYYMMDD)
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS)
+ g_stamp_time : natural := 0;
+ -- SVN revision
+ g_stamp_svn : natural := 0;
+ -- 1: use MB_I 0: do not use
+ g_use_MB_I : natural := 1;
g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master;
g_aux : t_c_unb1_board_aux := c_unb1_board_aux
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
index 34532416bb3622692dba4d69c0881e639d640e6c..e41dcffddb8d90869071eb274152fe1dda3fa57b 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
@@ -41,7 +41,8 @@ use eth_lib.eth_pkg.all;
entity mmm_unb1_ddr3_reorder is
generic (
- g_sim : boolean := true; -- FALSE: use SOPC; TRUE: use mm_file I/O
+ -- FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim : boolean := true;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_nof_streams : natural := 4;
@@ -229,7 +230,8 @@ begin
wait until rising_edge(i_mm_clk);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_dut_control_rx_en, i_mm_clk, eth1g_reg_miso, eth1g_reg_proc_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_dut_control_rx_en, i_mm_clk, eth1g_reg_miso, eth1g_reg_proc_mosi);
mm_bus_switch <= '0';
wait;
@@ -303,7 +305,8 @@ begin
-- the_pio_pps
coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1),
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
index 2af884041ac29abf351f5c7214a288db05772a54..2f4913157228d14eb38d5de2fc4183dfb7e83077 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
@@ -109,7 +109,8 @@ architecture str of node_unb1_ddr3_reorder is
constant c_total_data_w : natural := g_nof_streams * g_in_dat_w;
constant c_complex_data_w : natural := c_total_data_w * c_nof_complex;
constant c_data_w : natural := sel_a_b(c_use_complex, c_complex_data_w, c_total_data_w);
- constant c_fifo_depth : natural := 256; -- >=16 , defined at DDR side of the FIFO.
+ -- >=16 , defined at DDR side of the FIFO.
+ constant c_fifo_depth : natural := 256;
constant c_use_db : boolean := false;
constant c_use_rx_seq : boolean := true;
constant c_use_steps : boolean := true;
@@ -140,7 +141,8 @@ architecture str of node_unb1_ddr3_reorder is
begin
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
generic map (
- g_nof_streams => c_nof_bsn_streams, -- Check one input and one output stream
+ -- Check one input and one output stream
+ g_nof_streams => c_nof_bsn_streams,
g_cross_clock_domain => true,
g_bsn_w => c_dp_stream_bsn_w,
g_cnt_sop_w => c_word_w,
@@ -233,7 +235,8 @@ begin
ctlr_ref_rst => ddr_ref_rst,
-- DDR controller clock domain
- ctlr_clk_out => ddr_out_clk_i, -- output clock of the ddr controller is used as DP clk.
+ -- output clock of the ddr controller is used as DP clk.
+ ctlr_clk_out => ddr_out_clk_i,
ctlr_rst_out => ddr_out_rst_i,
ctlr_clk_in => ddr_out_clk_i,
@@ -324,10 +327,12 @@ begin
-- General
g_nof_streams => g_nof_streams,
-- DB settings
- g_data_type => e_data, -- define the sosi field that gets stored: e_data=data, e_complex=im&re, e_real=re, e_imag=im,
+ -- define the sosi field that gets stored: e_data=data, e_complex=im&re, e_real=re, e_imag=im,
+ g_data_type => e_data,
g_data_w => c_data_w,
g_buf_nof_data => c_buf_nof_data,
- g_buf_use_sync => c_buf_use_sync, -- when TRUE start filling the buffer at the in_sync, else after the last word was read,
+ -- when TRUE start filling the buffer at the in_sync, else after the last word was read,
+ g_buf_use_sync => c_buf_use_sync,
-- Rx_seq
g_use_steps => c_use_steps,
g_seq_dat_w => c_data_w
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
index a0f4448402a1c0f8d47f6c28dde9d61eeb5aca0d..5821e2d4cddd3c24b64ff5b4a4a521b7f84d4d8b 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
@@ -41,20 +41,29 @@ entity unb1_ddr3_reorder is
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 4;
-- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
- g_stamp_date : natural := 0; -- Date (YYYYMMDD)
- g_stamp_time : natural := 0; -- Time (HHMMSS)
- g_stamp_svn : natural := 0; -- SVN revision
- g_use_MB_I : natural := 1; -- 1: use MB_I 0: do not use
+ -- Date (YYYYMMDD)
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS)
+ g_stamp_time : natural := 0;
+ -- SVN revision
+ g_stamp_svn : natural := 0;
+ -- 1: use MB_I 0: do not use
+ g_use_MB_I : natural := 1;
g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master;
g_aux : t_c_unb1_board_aux := c_unb1_board_aux
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -117,7 +126,8 @@ architecture str of unb1_ddr3_reorder is
signal dp_pps : std_logic;
signal ddr_ref_rst : std_logic;
- signal this_chip_id : std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0); -- [2:0], so range 0-3 for FN and range 4-7 BN
+ -- [2:0], so range 0-3 for FN and range 4-7 BN
+ signal this_chip_id : std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0);
signal app_led_red : std_logic := '0';
signal app_led_green : std_logic := '1';
@@ -222,8 +232,10 @@ begin
mm_locked => mm_locked,
mm_rst => mm_rst,
- dp_rst => OPEN, -- dp_rst,
- dp_clk => OPEN, -- dp_clk, -- dp_clk is now generated in the DDR controller
+ -- dp_rst,
+ dp_rst => OPEN,
+ -- dp_clk, -- dp_clk is now generated in the DDR controller
+ dp_clk => OPEN,
dp_pps => OPEN,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
@@ -402,12 +414,14 @@ begin
dp_rst => dp_rst,
dp_clk => dp_clk,
- ddr_ref_clk => CLK, -- Provide external 200 MHZ clk to DDR controller
+ -- Provide external 200 MHZ clk to DDR controller
+ ddr_ref_clk => CLK,
ddr_ref_rst => ddr_ref_rst,
-- Clock outputs
ddr_out_clk => dp_clk,
- ddr_out_rst => dp_rst, -- dp_clk is generated by DDR controller
+ -- dp_clk is generated by DDR controller
+ ddr_out_rst => dp_rst,
-- IO DDR register map
reg_io_ddr_mosi => reg_io_ddr_mosi,
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
index 013700e86659870ff590f0e9f647e4980b63fb64..d952d4dd239ffdc098ce49548bf121ab4591ec56 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
@@ -46,8 +46,10 @@ entity tb_unb1_ddr3_reorder is
generic (
g_design_name : string := "unb1_ddr3_reorder";
g_design_note : string := "Reference Reorder";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7; -- Back node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Back node 3
+ g_sim_node_nr : natural := 7;
g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master
);
end tb_unb1_ddr3_reorder;
@@ -55,15 +57,18 @@ end tb_unb1_ddr3_reorder;
architecture tb of tb_unb1_ddr3_reorder is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 7; -- Back node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Back node 3
+ constant c_node_nr : natural := 7;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(g_sim_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(g_sim_node_nr, c_unb1_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb1_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
+ -- 25 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 40 ns;
constant c_clk_period : time := 5 ns;
constant c_sa_clk_period : time := 6.4 ns;
constant c_pps_period : natural := 1000;
@@ -95,28 +100,41 @@ architecture tb of tb_unb1_ddr3_reorder is
signal phy_ou : t_tech_ddr3_phy_ou;
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
index 6687a715a0fd68ff9c0a2484c21174f5fc74d032..88bac85368402b3d37c125daf14dd5a210989129 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
@@ -33,7 +33,8 @@ use ddr3_lib.ddr3_pkg.all;
entity mmm_unb_ddr3_transpose is
generic (
- g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
+ -- FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_frame_size_in : natural := 256;
@@ -240,7 +241,8 @@ begin
-- the_pio_pps
coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1),
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
index 1f1463d40ddf153677f593cf22140353f94e8eb3..ddee617c76a34215b5b8398e3be831cbc831862a 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
@@ -34,24 +34,34 @@ use ddr3_lib.ddr3_pkg.all;
entity unb1_ddr3_transpose is
generic (
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_design_name : string := "unb1_ddr3_transpose";
g_design_note : string := "Test Design";
--g_technology : NATURAL := c_tech_stratixiv;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0; -- SVN revision -- set by QSF
- g_use_MB_I : natural := 1 -- 1: use MB_I 0: do not use
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0;
+ -- 1: use MB_I 0: do not use
+ g_use_MB_I : natural := 1
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -81,12 +91,18 @@ architecture str of unb1_ddr3_transpose is
constant c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(g_sim, 0, 1), 0, 0, 0, 1, 0, 0, 1);
-- Compose the Constants for the DUT
- constant c_wr_chunksize : positive := sel_a_b(g_sim, 64, 64); -- 256);
- constant c_wr_nof_chunks : positive := sel_a_b(g_sim, 1, 1); -- 1);
- constant c_rd_chunksize : positive := sel_a_b(g_sim, 16, 16); -- 16);
- constant c_rd_nof_chunks : positive := sel_a_b(g_sim, 4, 4); -- 16);
- constant c_gapsize : natural := sel_a_b(g_sim, 0, 0); -- 0);
- constant c_nof_blocks : positive := sel_a_b(g_sim, 4, 4); -- 16);
+ -- 256);
+ constant c_wr_chunksize : positive := sel_a_b(g_sim, 64, 64);
+ -- 1);
+ constant c_wr_nof_chunks : positive := sel_a_b(g_sim, 1, 1);
+ -- 16);
+ constant c_rd_chunksize : positive := sel_a_b(g_sim, 16, 16);
+ -- 16);
+ constant c_rd_nof_chunks : positive := sel_a_b(g_sim, 4, 4);
+ -- 0);
+ constant c_gapsize : natural := sel_a_b(g_sim, 0, 0);
+ -- 16);
+ constant c_nof_blocks : positive := sel_a_b(g_sim, 4, 4);
constant c_ddr3_seq_conf : t_ddr3_seq := (c_wr_chunksize,
c_wr_nof_chunks,
@@ -98,7 +114,8 @@ architecture str of unb1_ddr3_transpose is
constant c_blocksize : positive := c_wr_nof_chunks * c_wr_chunksize;
constant c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
- constant c_mts : natural := 800; -- 1066; --800
+ -- 1066; --800
+ constant c_mts : natural := 800;
constant c_phy : natural := 1;
constant c_data_w : natural := 8;
constant c_nof_streams : positive := 4;
@@ -114,7 +131,8 @@ architecture str of unb1_ddr3_transpose is
-- Configuration of the block generator:
constant c_bg_buf_dat_w : positive := c_nof_complex * c_data_w;
constant c_bg_buf_adr_w : positive := ceil_log2(c_bg_block_len);
- constant c_bg_data_file_prefix : string := "UNUSED"; -- "../../../src/hex/tb_bg_dat";
+ -- "../../../src/hex/tb_bg_dat";
+ constant c_bg_data_file_prefix : string := "UNUSED";
constant c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, 128, 1);
-- Configuration of the databuffers:
@@ -161,12 +179,16 @@ architecture str of unb1_ddr3_transpose is
-- eth1g
signal eth1g_tse_clk : std_logic;
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
--SIGNAL eth1g_led : t_tse_led;
@@ -238,8 +260,10 @@ begin
mm_locked => mm_locked,
mm_rst => mm_rst,
- dp_rst => OPEN, -- dp_rst,
- dp_clk => OPEN, -- dp_clk,
+ -- dp_rst,
+ dp_rst => OPEN,
+ -- dp_clk,
+ dp_clk => OPEN,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
@@ -264,7 +288,8 @@ begin
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
@@ -406,7 +431,8 @@ begin
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
generic map (
- g_nof_streams => 2, -- Check one input and one output stream
+ -- Check one input and one output stream
+ g_nof_streams => 2,
g_cross_clock_domain => true,
g_bsn_w => c_dp_stream_bsn_w,
g_cnt_sop_w => c_word_w,
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
index 3d8ecf213a834d8c9206e1a9f6204949b944cf1e..b0e57864865c7cfae50ae3ba9c162f5c61bcf74d 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
@@ -39,15 +39,18 @@ end tb_unb1_ddr3_transpose;
architecture tb of tb_unb1_ddr3_transpose is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 7; -- Back node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Back node 3
+ constant c_node_nr : natural := 7;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w ) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb1_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
+ -- 25 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 40 ns;
constant c_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -79,28 +82,41 @@ architecture tb of tb_unb1_ddr3_transpose is
signal phy_ou : t_tech_ddr3_phy_ou;
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
index 02d12daee571723b79912c82f1427aafe8dfcaa0..b32ee12809ab22648a626601ce5d50eac9e6f2e2 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
@@ -38,7 +38,8 @@ use tech_tse_lib.tb_tech_tse_pkg.all;
entity mmm_unb1_fn_terminal_db is
generic (
- g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
+ -- FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
@@ -195,7 +196,8 @@ begin
proc_tech_tse_setup(c_tech_stratixiv, false, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, i_mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, i_mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi);
sim_eth_mm_bus_switch <= '0';
wait;
@@ -227,11 +229,15 @@ begin
u_sopc : entity work.sopc_unb1_fn_terminal_db
port map (
-- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ -- PLL reference = 25 MHz from ETH_clk pin
+ clk_0 => xo_clk,
reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+ -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ mm_clk => i_mm_clk,
+ -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ cal_clk => cal_clk,
+ -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+ tse_clk => i_tse_clk,
-- the_altpll_0
areset_to_the_altpll_0 => '0',
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
index f7ddc510062859aa916d7f5743157ee601e5a717..2853d3e1e5546ff8e3fa804a3887db71d49f47e0 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
@@ -134,39 +134,51 @@ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity node_unb1_fn_terminal_db is
generic(
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = simulate GX IP, 1 = use fast serial behavioural model
- g_use_bsn_align : boolean := true; -- default TRUE, support FALSE for packet flow debugging purposes (faster synthesis)
+ -- 0 = simulate GX IP, 1 = use fast serial behavioural model
+ g_sim_level : natural := 0;
+ -- default TRUE, support FALSE for packet flow debugging purposes (faster synthesis)
+ g_use_bsn_align : boolean := true;
g_use_data_buf : boolean := true;
-- Application Interface
g_usr_nof_streams : natural := 16;
g_usr_data_w : natural := 32;
g_usr_block_len : natural := 96;
- g_usr_block_per : natural := 256; -- block period = block length + gap length
+ -- block period = block length + gap length
+ g_usr_block_per : natural := 256;
-- Terminals Interface
g_multi_unb : boolean := false;
g_use_mesh : boolean := true;
- g_mesh_nof_serial : natural := 3; -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
+ -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
+ g_mesh_nof_serial : natural := 3;
g_mesh_gx_mbps : natural := 5000;
g_mesh_ena_reorder : boolean := true;
- g_mesh_use_tx : boolean := true; -- can be FALSE for BF, use TRUE to support for bidirectional TR diagnostics
- g_mesh_mon_select : natural := 0; -- 0 = no data monitor buffers via MM, else see unb_terminals_mesh.vhd
+ -- can be FALSE for BF, use TRUE to support for bidirectional TR diagnostics
+ g_mesh_use_tx : boolean := true;
+ -- 0 = no data monitor buffers via MM, else see unb_terminals_mesh.vhd
+ g_mesh_mon_select : natural := 0;
g_mesh_mon_nof_words : natural := 1024;
g_mesh_mon_use_sync : boolean := true;
- g_mesh_sync_timeout : natural := 220 * 10**6; -- >= number dp_clk per sync (choose = can be too tight due to asynchronous mesh link, so then choose somewhat larger)
+ -- >= number dp_clk per sync (choose = can be too tight due to asynchronous mesh link, so then choose somewhat larger)
+ g_mesh_sync_timeout : natural := 220 * 10**6;
-- Auxiliary Interface
g_aux : t_c_unb1_board_aux := c_unb1_board_aux
);
port(
-- System
- chip_id : in std_logic_vector(g_aux.chip_id_w - 1 downto 0); -- [2:0]
+ -- [2:0]
+ chip_id : in std_logic_vector(g_aux.chip_id_w - 1 downto 0);
mm_rst : in std_logic;
- mm_clk : in std_logic; -- 50 MHz from xo_clk PLL in SOPC system
+ -- 50 MHz from xo_clk PLL in SOPC system
+ mm_clk : in std_logic;
dp_rst : in std_logic;
- dp_clk : in std_logic; -- 200 MHz from CLK system clock
+ -- 200 MHz from CLK system clock
+ dp_clk : in std_logic;
dp_pps : in std_logic := '0';
- tr_mesh_clk : in std_logic; -- 156.25 MHz from SB_CLK transceiver clock
- cal_clk : in std_logic; -- 40 MHz from xo_clk PLL in SOPC system
+ -- 156.25 MHz from SB_CLK transceiver clock
+ tr_mesh_clk : in std_logic;
+ -- 40 MHz from xo_clk PLL in SOPC system
+ cal_clk : in std_logic;
-- MM interface
-- . diag_data_buffer
@@ -191,8 +203,10 @@ entity node_unb1_fn_terminal_db is
dp_out_siso_arr : in t_dp_siso_arr(g_usr_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
-- Mesh serial interface (tr_nonbonded)
- tx_serial_2arr : out t_unb1_board_mesh_sl_2arr; -- Tx
- rx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0')) -- Rx support for diagnostics
+ -- Tx
+ tx_serial_2arr : out t_unb1_board_mesh_sl_2arr;
+ -- Rx support for diagnostics
+ rx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0'))
);
end node_unb1_fn_terminal_db;
@@ -200,33 +214,43 @@ architecture str of node_unb1_fn_terminal_db is
-----------------------------------------------------------------------------
-- BSN align
-----------------------------------------------------------------------------
- constant c_bsn_request_pipeline : natural := 2; -- need to use 2 to ease timing closure at 200 MHz
+ -- need to use 2 to ease timing closure at 200 MHz
+ constant c_bsn_request_pipeline : natural := 2;
constant c_bsn_latency : natural := 3;
- constant c_burst_usr_nof_block : natural := g_mesh_nof_serial; -- 3 phy lane blocks t012 per user stream
+ -- 3 phy lane blocks t012 per user stream
+ constant c_burst_usr_nof_block : natural := g_mesh_nof_serial;
constant c_burst_bsn_latency : natural := c_bsn_latency + c_burst_usr_nof_block;
-----------------------------------------------------------------------------
-- Terminals
-----------------------------------------------------------------------------
- constant c_usr_nof_streams_per_bus : natural := g_usr_nof_streams / c_unb1_board_nof_bn; -- 16 / 4 = 4
+ -- 16 / 4 = 4
+ constant c_usr_nof_streams_per_bus : natural := g_usr_nof_streams / c_unb1_board_nof_bn;
-- . tr_nonbonded rx fifo
- constant c_burst_phy_nof_block : natural := c_usr_nof_streams_per_bus; -- burst of 4 usr blocks per t0 per phy lane
- constant c_phy_block_len : natural := g_usr_block_len; -- no data packing so phy frame is about as long as the user frame (expect for few overhead words)
- constant c_phy_rx_fifo_len : natural := c_phy_block_len * 1; -- assume only need to store less than one block in practise
- constant c_phy_rx_fifo_size : natural := ceil_value(c_phy_rx_fifo_len, c_bram_m9k_fifo_depth); -- use tr_nonbonded Rx dual clock FIFO to buffer for dp_distribute
+ -- burst of 4 usr blocks per t0 per phy lane
+ constant c_burst_phy_nof_block : natural := c_usr_nof_streams_per_bus;
+ -- no data packing so phy frame is about as long as the user frame (expect for few overhead words)
+ constant c_phy_block_len : natural := g_usr_block_len;
+ -- assume only need to store less than one block in practise
+ constant c_phy_rx_fifo_len : natural := c_phy_block_len * 1;
+ -- use tr_nonbonded Rx dual clock FIFO to buffer for dp_distribute
+ constant c_phy_rx_fifo_size : natural := ceil_value(c_phy_rx_fifo_len, c_bram_m9k_fifo_depth);
-- . uth_rx timeout_cnt
- constant c_rx_timeout_w : natural := 0; -- ceil_log2(g_usr_block_per);
+ -- ceil_log2(g_usr_block_per);
+ constant c_rx_timeout_w : natural := 0;
-- . uth_terminal_rx output fifo
constant c_rx_output_fifo_len : natural := (c_burst_bsn_latency + 2) * g_usr_block_len;
constant c_rx_output_fifo_size : natural := ceil_value(c_rx_output_fifo_len, c_bram_m9k_fifo_depth);
- constant c_rx_output_fifo_fill : natural := g_usr_block_len; -- keep a full block in the FIFO to ensure that dp_bsn_align gets input without data not valid gaps when the lane rate is slower (as with tr_nonbonded)
+ -- keep a full block in the FIFO to ensure that dp_bsn_align gets input without data not valid gaps when the lane rate is slower (as with tr_nonbonded)
+ constant c_rx_output_fifo_fill : natural := g_usr_block_len;
-- . BSN aligner timeouts
- constant c_sop_timeout : natural := (c_burst_bsn_latency + 1) * g_usr_block_per; -- wait for sop for some block periods
+ -- wait for sop for some block periods
+ constant c_sop_timeout : natural := (c_burst_bsn_latency + 1) * g_usr_block_per;
constant c_xoff_timeout : natural := c_burst_bsn_latency * 2 * g_usr_block_per;
signal rx_usr_siso_2arr : t_unb1_board_mesh_siso_2arr;
@@ -254,7 +278,8 @@ begin
g_sim_level => g_sim_level,
-- System
g_node_type => e_fn,
- g_nof_bus => c_unb1_board_nof_bn, -- 4 to 4 nodes in mesh
+ -- 4 to 4 nodes in mesh
+ g_nof_bus => c_unb1_board_nof_bn,
-- User
g_usr_use_complex => true,
g_usr_data_w => g_usr_data_w,
@@ -266,11 +291,15 @@ begin
g_phy_rx_fifo_size => c_phy_rx_fifo_size,
g_phy_ena_reorder => g_mesh_ena_reorder,
-- Tx
- g_use_tx => g_mesh_use_tx, -- optionally do support diag Tx
- g_tx_input_use_fifo => false, -- no user Tx
+ -- optionally do support diag Tx
+ g_use_tx => g_mesh_use_tx,
+ -- no user Tx
+ g_tx_input_use_fifo => false,
-- Rx
- g_use_rx => true, -- user Rx must be TRUE for DB in FN,
- g_rx_output_use_fifo => true, -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ -- user Rx must be TRUE for DB in FN,
+ g_use_rx => true,
+ -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_use_fifo => true,
g_rx_output_fifo_size => c_rx_output_fifo_size,
g_rx_output_fifo_fill => c_rx_output_fifo_fill,
g_rx_timeout_w => c_rx_timeout_w,
@@ -292,12 +321,15 @@ begin
-- User interface (4 nodes)(4 input streams)
rx_usr_siso_2arr => rx_usr_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- Rx (user Tx from FN to BN is unused)
+ -- Rx (user Tx from FN to BN is unused)
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr,
-- Mesh interface level (4 nodes)(4 lanes)
-- . Serial (tr_nonbonded)
- tx_serial_2arr => tx_serial_2arr, -- Tx
- rx_serial_2arr => rx_serial_2arr, -- Rx
+ -- Tx
+ tx_serial_2arr => tx_serial_2arr,
+ -- Rx
+ rx_serial_2arr => rx_serial_2arr,
-- MM Control
-- . tr_nonbonded
@@ -363,13 +395,16 @@ begin
src_in_arr => dp_out_siso_arr,
src_out_arr => db_in_sosi_arr,
-- MM
- in_en_evt => '0', -- pulse '1' indicates that the in_en_arr user input enables have been updated
- in_en_arr => (others => '1') -- default all user inputs are enabled
+ -- pulse '1' indicates that the in_en_arr user input enables have been updated
+ in_en_evt => '0',
+ -- default all user inputs are enabled
+ in_en_arr => (others => '1')
);
u_bsn_monitor_align : entity dp_lib.mms_dp_bsn_monitor
generic map (
- g_nof_streams => 1, -- All streams are synchronous. Only monitor stream(0).
+ -- All streams are synchronous. Only monitor stream(0).
+ g_nof_streams => 1,
g_cross_clock_domain => true,
g_sync_timeout => g_mesh_sync_timeout,
g_bsn_w => c_dp_stream_bsn_w,
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
index c3b0cd899761a0826b370b36ba22671b8825cdff..b47d3131fab08a9a6840e977c7d3a8821ce631f7 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
@@ -36,23 +36,34 @@ use tech_tse_lib.tb_tech_tse_pkg.all;
entity unb1_fn_terminal_db is
generic (
-- General
- g_rev_multi_unb : boolean := false; -- Set to TRUE by Quartus revision fn_terminal_db_rev_multi.
- g_design_name : string := "unb1_fn_terminal_db"; -- Set to "fn_terminal_db_rev_multi_unb" by revision fn_terminal_db_rev_multi
+ -- Set to TRUE by Quartus revision fn_terminal_db_rev_multi.
+ g_rev_multi_unb : boolean := false;
+ -- Set to "fn_terminal_db_rev_multi_unb" by revision fn_terminal_db_rev_multi
+ g_design_name : string := "unb1_fn_terminal_db";
g_design_note : string := "UNUSED";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -70,7 +81,8 @@ entity unb1_fn_terminal_db is
-- Transceiver clocks
--SA_CLK : IN STD_LOGIC := '0'; -- TR clock BN-BI (backplane)
- SB_CLK : in std_logic := '0'; -- TR clock FN-BN (mesh)
+ -- TR clock FN-BN (mesh)
+ SB_CLK : in std_logic := '0';
-- Serial I/O
FN_BN_0_TX : out std_logic_vector(c_unb1_board_tr_mesh.bus_w - 1 downto 0);
@@ -86,12 +98,16 @@ end unb1_fn_terminal_db;
architecture str of unb1_fn_terminal_db is
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 1, 0, 0, 0, 0, 1);
- constant c_fw_version : t_unb1_board_fw_version := (1, 0); -- firmware version x.y
+ -- firmware version x.y
+ constant c_fw_version : t_unb1_board_fw_version := (1, 0);
constant c_use_mesh : boolean := c_use_phy.tr_mesh = 1;
- constant c_mesh_mon_select : natural := 1; -- > 0 = enable SOSI data buffers monitor via MM
- constant c_mesh_mon_nof_words : natural := c_unb1_board_peripherals_mm_reg_default.ram_diag_db_buf_size; -- = 1024
- constant c_mesh_mon_use_sync : boolean := true; -- when TRUE use dp_pps to trigger the data buffer capture, else new data capture after read access of last data word
+ -- > 0 = enable SOSI data buffers monitor via MM
+ constant c_mesh_mon_select : natural := 1;
+ -- = 1024
+ constant c_mesh_mon_nof_words : natural := c_unb1_board_peripherals_mm_reg_default.ram_diag_db_buf_size;
+ -- when TRUE use dp_pps to trigger the data buffer capture, else new data capture after read access of last data word
+ constant c_mesh_mon_use_sync : boolean := true;
constant c_reg_diag_db_adr_w : natural := 5;
@@ -109,7 +125,8 @@ architecture str of unb1_fn_terminal_db is
signal dp_clk : std_logic;
signal dp_pps : std_logic;
- signal this_chip_id : std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0); -- [2:0], so range 0-3 for FN and range 4-7 BN
+ -- [2:0], so range 0-3 for FN and range 4-7 BN
+ signal this_chip_id : std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0);
-- PIOs
signal pout_debug_wave : std_logic_vector(c_word_w - 1 downto 0);
@@ -129,23 +146,30 @@ architecture str of unb1_fn_terminal_db is
signal rom_unb_system_info_miso : t_mem_miso;
-- UniBoard I2C sens
- signal reg_unb_sens_mosi : t_mem_mosi; -- mms_unb_sens registers
+ -- mms_unb_sens registers
+ signal reg_unb_sens_mosi : t_mem_mosi;
signal reg_unb_sens_miso : t_mem_miso;
-- eth1g
signal eth1g_tse_clk : std_logic;
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_ram_miso : t_mem_miso;
-- tr_mesh
- signal tx_serial_2arr : t_unb1_board_mesh_sl_2arr; -- Tx
- signal rx_serial_2arr : t_unb1_board_mesh_sl_2arr; -- Rx support for diagnostics
+ -- Tx
+ signal tx_serial_2arr : t_unb1_board_mesh_sl_2arr;
+ -- Rx support for diagnostics
+ signal rx_serial_2arr : t_unb1_board_mesh_sl_2arr;
-- MM tr_nonbonded with diagnostics
signal reg_tr_nonbonded_mosi : t_mem_mosi := c_mem_mosi_rst;
@@ -221,7 +245,8 @@ begin
reg_unb_sens_miso => reg_unb_sens_miso,
-- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
index 25bd96f7d89711519fc854a42162f667075a8031..3f1b239ba4caf88d960405319cb12bdc1444cf65 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
@@ -87,19 +87,23 @@ use mm_lib.mm_file_unb_pkg.all;
entity tb_mmf_node_fn_terminal_db is
generic (
- g_sim_level : natural := 1; -- 0 = use accurate GX IP model, 1 = use fast GX behavioural model in tr_nonbonded
- g_unb_sys : t_c_mmf_unb_sys := (4, 1, 4) -- (nof_unb, nof_fn per UniBoard, nof_bn per UniBoard);
+ -- 0 = use accurate GX IP model, 1 = use fast GX behavioural model in tr_nonbonded
+ g_sim_level : natural := 1;
+ -- (nof_unb, nof_fn per UniBoard, nof_bn per UniBoard);
+ g_unb_sys : t_c_mmf_unb_sys := (4, 1, 4)
);
end tb_mmf_node_fn_terminal_db;
architecture tb of tb_mmf_node_fn_terminal_db is
constant c_sim : boolean := true;
- constant c_use_back : boolean := sel_a_b(g_unb_sys.nof_unb = 4, true, false); -- To interconnect multiple boards via the backplane when g_unb_sys.nof_unb=4 else when g_unb_sys.nof_unb=1
+ -- To interconnect multiple boards via the backplane when g_unb_sys.nof_unb=4 else when g_unb_sys.nof_unb=1
+ constant c_use_back : boolean := sel_a_b(g_unb_sys.nof_unb = 4, true, false);
-- this loops back each back node's BN_BI_TX to BN_BI_RX.
constant c_ena_mesh_reorder : boolean := true;
constant c_mesh_use_bidir : boolean := false;
- constant c_mesh_nof_serial : natural := 3; -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
+ -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
+ constant c_mesh_nof_serial : natural := 3;
----------------------------------------------------------------------------
-- Clocks and resets
@@ -271,8 +275,10 @@ begin
tr_back_clk => tr_CLK,
cal_clk => cal_rec_clk,
- chip_id => TO_UVEC(BN + 4, c_unb_nof_chip_w), -- BN chip ID 4,5,6,7
- bck_id => TO_UVEC(UNB, c_unb_nof_uniboard_w), -- Backplane ID 0,1,2,3
+ -- BN chip ID 4,5,6,7
+ chip_id => TO_UVEC(BN + 4, c_unb_nof_chip_w),
+ -- Backplane ID 0,1,2,3
+ bck_id => TO_UVEC(UNB, c_unb_nof_uniboard_w),
-- MM interface
-- . block generator
@@ -356,7 +362,8 @@ begin
tr_mesh_clk => tr_clk,
cal_clk => cal_rec_clk,
- chip_id => TO_UVEC(FN, c_unb_nof_chip_w), -- FN chip ID 0,1,2,3
+ -- FN chip ID 0,1,2,3
+ chip_id => TO_UVEC(FN, c_unb_nof_chip_w),
-- MM interface
-- . tr_nonbonded
@@ -378,8 +385,10 @@ begin
-- Mesh interface level
-- . Serial (tr_nonbonded)
- tx_serial_2arr => fn_out_mesh_serial_4arr(UNB)(FN), -- Tx support for diagnostics
- rx_serial_2arr => fn_in_mesh_serial_4arr(UNB)(FN) -- Rx
+ -- Tx support for diagnostics
+ tx_serial_2arr => fn_out_mesh_serial_4arr(UNB)(FN),
+ -- Rx
+ rx_serial_2arr => fn_in_mesh_serial_4arr(UNB)(FN)
);
end generate;
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
index 78bdc17f233b68281ae52a27903f3657d6d7e08d..c725d0fe87e55a1233214c73501ac84705124983 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
@@ -104,8 +104,10 @@ entity mmm_unb1_heater is
end mmm_unb1_heater;
architecture str of mmm_unb1_heater is
- constant c_mm_clk_period : time := 8 ns; -- 125 MHz
- constant c_epcs_clk_period : time := 50 ns; -- 20 MHz
+ -- 125 MHz
+ constant c_mm_clk_period : time := 8 ns;
+ -- 20 MHz
+ constant c_epcs_clk_period : time := 50 ns;
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr < 4, "FN", "BN");
constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type = "BN", g_sim_node_nr - 4, g_sim_node_nr);
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
index 6ab5775f35323f6cb09dd41e5a6b51e08d93a79a..a7dc666e240dadb3f0b0499461844c5911c8b8f8 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
@@ -29,119 +29,232 @@ package qsys_unb1_heater_pkg is
component qsys_unb1_heater is
port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- mm_clk : out std_logic; -- clk
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- tse_clk : out std_logic; -- clk
- epcs_clk : out std_logic; -- clk
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- c3_from_the_altpll_0 : out std_logic; -- export
- coe_read_export_from_the_reg_remu : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(3 downto 0); -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_reset_export : out std_logic -- export
+ -- export
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- clk
+ mm_clk : out std_logic;
+ -- export
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0);
+ -- export
+ coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0);
+ -- export
+ coe_reset_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0);
+ -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0);
+ -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_remu : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_read_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0);
+ -- export
+ coe_read_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0);
+ -- export
+ coe_clk_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0);
+ -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0);
+ -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0);
+ -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_write_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0);
+ -- export
+ coe_write_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_write_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X';
+ -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_read_export_from_the_rom_system_info : out std_logic;
+ -- export
+ phasedone_from_the_altpll_0 : out std_logic;
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- export
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic;
+ -- clk
+ clk_0 : in std_logic := 'X';
+ -- export
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0);
+ -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0);
+ -- clk
+ tse_clk : out std_logic;
+ -- clk
+ epcs_clk : out std_logic;
+ -- export
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0);
+ -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_read_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_write_export_from_the_reg_remu : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0);
+ -- export
+ out_port_from_the_pio_wdi : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_remu : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0);
+ -- export
+ coe_write_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_write_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_read_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0);
+ -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0);
+ -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X';
+ -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0);
+ -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0);
+ -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0);
+ -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0);
+ -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0);
+ -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0);
+ -- export
+ areset_to_the_altpll_0 : in std_logic := 'X';
+ -- export
+ locked_from_the_altpll_0 : out std_logic;
+ -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ c3_from_the_altpll_0 : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_remu : out std_logic;
+ -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_heater_read_export : out std_logic;
+ -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_heater_write_export : out std_logic;
+ -- export
+ reg_heater_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_heater_clk_export : out std_logic;
+ -- export
+ reg_heater_reset_export : out std_logic
);
end component qsys_unb1_heater;
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
index 8187b73626611866ff1ac6d01ecd72c65c2b4ffa..d92c13dbf6a4278f107ac46c80b86d6333cef0b4 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
@@ -34,20 +34,29 @@ entity unb1_heater is
g_design_name : string := "unb1_heater";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_stratixiv;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -112,12 +121,16 @@ architecture str of unb1_heater is
-- eth1g
signal eth1g_tse_clk : std_logic;
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -223,7 +236,8 @@ begin
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
diff --git a/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
index 42cf774fa0baec99a5258e50fc374fe297a965b7..17de223065c9465cdeed49f73cf95533f0d35819 100644
--- a/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
@@ -52,23 +52,28 @@ use common_lib.tb_common_pkg.all;
entity tb_unb1_heater is
generic (
g_design_name : string := "unb1_heater";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Back node 3
+ g_sim_node_nr : natural := 7
);
end tb_unb1_heater;
architecture tb of tb_unb1_heater is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 7; -- Back node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Back node 3
+ constant c_node_nr : natural := 7;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb1_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
+ -- 25 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 40 ns;
constant c_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -93,28 +98,41 @@ architecture tb of tb_unb1_heater is
signal sens_sda : std_logic;
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
index 158c2a2617ea08a4d6399a911ab2548a4f1643b3..d6f6d9da2e991aa8f6a66f059a4221f18d6342d3 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
@@ -34,6 +34,7 @@ begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
generic map (
g_design_name => "unb1_minimal_mm_arbiter",
- g_sim_node_nr => 7 -- BN3
+ -- BN3
+ g_sim_node_nr => 7
);
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
index 94b8a71585d0c48b2e788098e0449a91a2a51c3c..f350f2d7b95025543ae96101c5d23e6a0c1f7756 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
@@ -26,22 +26,32 @@ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_mm_arbiter is
generic (
- g_design_name : string := "unb1_minimal_mm_arbiter"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_minimal_mm_arbiter";
g_design_note : string := "None";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
index 86785da2a3dbbdaa2ff1b05e30d779402650090d..5ab272b994e53d145cc3f20c65d9cf52fbed6db6 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
@@ -34,6 +34,7 @@ begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
generic map (
g_design_name => "unb1_minimal_qsys",
- g_sim_node_nr => 7 -- BN3
+ -- BN3
+ g_sim_node_nr => 7
);
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
index 984cbc8b4cea62a341335896d2d437aa93d8cfde..d57919a5a13763795667d893b27ea3718fe038a1 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
@@ -58,8 +58,10 @@ end tb_unb1_minimal_qsys_stimuli;
architecture tb of tb_unb1_minimal_qsys_stimuli is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 7; -- Back node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Back node 3
+ constant c_node_nr : natural := 7;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
@@ -67,8 +69,10 @@ architecture tb of tb_unb1_minimal_qsys_stimuli is
constant c_cable_delay : time := 12 ns;
constant c_tb_clk_period : time := 10 ns;
- constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
- constant c_ext_clk_period : time := 5 ns; -- 200 MHz
+ -- 25 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 40 ns;
+ -- 200 MHz
+ constant c_ext_clk_period : time := 5 ns;
constant c_ext_pps_period : natural := 1000;
constant c_cross_clock_domain_delay : natural := 50;
@@ -114,33 +118,46 @@ architecture tb of tb_unb1_minimal_qsys_stimuli is
signal sens_sda : std_logic;
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
constant c_temp_high : integer := 85;
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
constant c_extpected_cnt : natural := (1000 ms) / c_ext_clk_period;
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2; -- External clock (200 MHz)
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
ext_rst <= '1', '0' after c_ext_clk_period * 10;
- eth_clk <= not eth_clk or tb_end after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk or tb_end after c_eth_clk_period / 2;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
@@ -224,7 +241,8 @@ begin
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= not tb_clk or tb_end after c_tb_clk_period / 2; -- Testbench MM clock
+ -- Testbench MM clock
+ tb_clk <= not tb_clk or tb_end after c_tb_clk_period / 2;
p_mm_stimuli : process
variable v_bsn : natural;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
index 0f6289c4b140bd78a6f0543e7a32a0b2e5d2a06e..7e3892d05f94c25aac61012e0e8b7618749067fe 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
@@ -26,22 +26,32 @@ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_qsys is
generic (
- g_design_name : string := "unb1_minimal_qsys"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_minimal_qsys";
g_design_note : string := "using qsys";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : integer := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : integer := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
index 225991915478557e0526f302a2ea6e41550bec83..bc7493a79788612e4afef097cf28783ecd8b80cf 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
@@ -41,7 +41,8 @@ use work.qsys_wo_pll_unb1_minimal_pkg.all;
entity mmm_unb1_minimal_qsys_wo_pll is
generic (
- g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
+ -- FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_mm_clk_freq : natural := c_unb1_board_mm_clk_freq_50M
@@ -158,7 +159,8 @@ begin
wait until rising_edge(mm_clk);
proc_tech_tse_setup(c_tech_stratixiv, false, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi);
sim_eth_mm_bus_switch <= '0';
wait;
end process;
@@ -225,7 +227,8 @@ begin
-- the_pio_pps
coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1),
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
index 142125fe43a2877ae7f01bfc3caab67d082ade0a..008e330d39defd99d9743a22e8e322ef9ff2ae28 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
@@ -30,105 +30,204 @@ package qsys_wo_pll_unb1_minimal_pkg is
component qsys_wo_pll_unb1_minimal is
port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_remu : out std_logic -- export
+ -- export
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0);
+ -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_reset_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0);
+ -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_remu : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_read_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0);
+ -- export
+ coe_read_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0);
+ -- export
+ coe_clk_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0);
+ -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_write_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0);
+ -- export
+ coe_write_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_write_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X';
+ -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_read_export_from_the_rom_system_info : out std_logic;
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- export
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic;
+ -- clk
+ clk_0 : in std_logic := 'X';
+ -- export
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0);
+ -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0);
+ -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_read_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_write_export_from_the_reg_remu : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0);
+ -- export
+ out_port_from_the_pio_wdi : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_remu : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic;
+ -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_write_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_write_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_read_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0);
+ -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0);
+ -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X';
+ -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0);
+ -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0);
+ -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0);
+ -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0);
+ -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0);
+ -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ coe_read_export_from_the_reg_remu : out std_logic
);
end component qsys_wo_pll_unb1_minimal;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
index 0359b319110d7ccfaa3794a5b6938ae577521101..9b7b5ad6901d87afafcb2d0706e45c14c4cf5e04 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
@@ -52,23 +52,28 @@ use common_lib.tb_common_pkg.all;
entity tb_unb1_minimal_qsys_wo_pll is
generic (
g_design_name : string := "unb1_minimal_qsys_wo_pll";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Back node 3
+ g_sim_node_nr : natural := 7
);
end tb_unb1_minimal_qsys_wo_pll;
architecture tb of tb_unb1_minimal_qsys_wo_pll is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 7; -- Back node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Back node 3
+ constant c_node_nr : natural := 7;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb1_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
+ -- 25 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 40 ns;
constant c_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -93,28 +98,41 @@ architecture tb of tb_unb1_minimal_qsys_wo_pll is
signal sens_sda : std_logic;
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
index 408c4bc506017ca1d924566a62823f2e48154beb..8efcc6557e277b768c3110c92fe48f2b725b97a4 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
@@ -29,22 +29,32 @@ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_qsys_wo_pll is
generic (
- g_design_name : string := "unb1_minimal_qsys_wo_pll"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_minimal_qsys_wo_pll";
g_design_note : string := "using qsys w/o altpll_0";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -86,7 +96,8 @@ architecture str of unb1_minimal_qsys_wo_pll is
signal eth1g_tse_clk : std_logic;
signal eth1g_mm_rst : std_logic;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
-- PIOs
signal pout_wdi : std_logic;
@@ -110,11 +121,14 @@ architecture str of unb1_minimal_qsys_wo_pll is
signal reg_unb_sens_miso : t_mem_miso;
-- eth1g
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -226,7 +240,8 @@ begin
-- eth1g
eth1g_tse_clk_out => eth1g_tse_clk,
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
index 73b74d631423c98f5bfca6e7ad9ff68548eadaf6..650aca1661ae704f9741de9376f055ad00c68169 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
@@ -34,6 +34,7 @@ begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
generic map (
g_design_name => "unb1_minimal_sopc",
- g_sim_node_nr => 7 -- BN3
+ -- BN3
+ g_sim_node_nr => 7
);
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
index 31d891bafd689e7910b4bd57833a04e0d9393a30..fb650a737d463959eecd74bf04e4c6d88a8e99d9 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
@@ -26,22 +26,32 @@ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_sopc is
generic (
- g_design_name : string := "unb1_minimal_sopc"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_minimal_sopc";
g_design_note : string := "using sopc";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : integer := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : integer := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
index d0dbf2fd6e39c1f69358d620fdbd979b401fc58f..d92755cd7dad056749c8db5d9188a57ee7fd4bae 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
@@ -32,7 +32,8 @@ use work.qsys_unb1_minimal_pkg.all;
entity mmm_unb1_minimal is
generic (
- g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
+ -- FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_use_qsys : boolean := false;
@@ -102,8 +103,10 @@ entity mmm_unb1_minimal is
end mmm_unb1_minimal;
architecture str of mmm_unb1_minimal is
- constant c_mm_clk_period : time := 8 ns; -- 125 MHz
- constant c_epcs_clk_period : time := 50 ns; -- 20 MHz
+ -- 125 MHz
+ constant c_mm_clk_period : time := 8 ns;
+ -- 20 MHz
+ constant c_epcs_clk_period : time := 50 ns;
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr < 4, "FN", "BN");
constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type = "BN", g_sim_node_nr - 4, g_sim_node_nr);
@@ -235,7 +238,8 @@ begin
-- the_pio_pps
coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1),
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
@@ -374,7 +378,8 @@ begin
-- the_pio_pps
coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1),
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
@@ -469,7 +474,8 @@ begin
-----------------------------------------------------------------------------
-- MM arbiter experiment
-----------------------------------------------------------------------------
- gen_mm_arbiter : if g_use_qsys = false and g_use_sopc = false generate -- Still a QSYS actually....bus a minimal one.
+ -- Still a QSYS actually....bus a minimal one.
+ gen_mm_arbiter : if g_use_qsys = false and g_use_sopc = false generate
-----------------------------------------------------------------------------
-- MM master: a minimal QSYS (for now)
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
index 63e5d9c4da7458d9ab0c6208a30252181f8406be..b93a46fbfa7eecc88b4897bb7bb34a0b3605ba22 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
@@ -30,160 +30,309 @@ package qsys_unb1_minimal_pkg is
component qsys_unb1_minimal is
port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- mm_clk : out std_logic; -- clk
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- tse_clk : out std_logic; -- clk
- epcs_clk : out std_logic; -- clk
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- c3_from_the_altpll_0 : out std_logic; -- export
- coe_read_export_from_the_reg_remu : out std_logic -- export
+ -- export
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- clk
+ mm_clk : out std_logic;
+ -- export
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0);
+ -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_reset_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0);
+ -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_remu : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_read_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0);
+ -- export
+ coe_read_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0);
+ -- export
+ coe_clk_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0);
+ -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_write_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0);
+ -- export
+ coe_write_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_write_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X';
+ -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_read_export_from_the_rom_system_info : out std_logic;
+ -- export
+ phasedone_from_the_altpll_0 : out std_logic;
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- export
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic;
+ -- clk
+ clk_0 : in std_logic := 'X';
+ -- export
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0);
+ -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0);
+ -- clk
+ tse_clk : out std_logic;
+ -- clk
+ epcs_clk : out std_logic;
+ -- export
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0);
+ -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_read_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_write_export_from_the_reg_remu : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0);
+ -- export
+ out_port_from_the_pio_wdi : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_remu : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic;
+ -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_write_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_write_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_read_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0);
+ -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0);
+ -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X';
+ -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0);
+ -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0);
+ -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0);
+ -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0);
+ -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0);
+ -- export
+ areset_to_the_altpll_0 : in std_logic := 'X';
+ -- export
+ locked_from_the_altpll_0 : out std_logic;
+ -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ c3_from_the_altpll_0 : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_remu : out std_logic
);
end component qsys_unb1_minimal;
component qsys_unb1_minimal_mm_arbiter is
port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- mm_clk : out std_logic; -- clk
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- tse_clk : out std_logic; -- clk
- epcs_clk : out std_logic; -- clk
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- c3_from_the_altpll_0 : out std_logic; -- export
- to_mm_arbiter_reset_export : out std_logic; -- export
- to_mm_arbiter_clk_export : out std_logic; -- export
- to_mm_arbiter_address_export : out std_logic_vector(10 downto 0); -- export
- to_mm_arbiter_write_export : out std_logic; -- export
- to_mm_arbiter_writedata_export : out std_logic_vector(31 downto 0); -- export
- to_mm_arbiter_read_export : out std_logic; -- export
- to_mm_arbiter_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ -- export
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic;
+ -- clk
+ mm_clk : out std_logic;
+ -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0);
+ -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0);
+ -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X';
+ -- export
+ phasedone_from_the_altpll_0 : out std_logic;
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- export
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic;
+ -- clk
+ clk_0 : in std_logic := 'X';
+ -- clk
+ tse_clk : out std_logic;
+ -- clk
+ epcs_clk : out std_logic;
+ -- export
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ out_port_from_the_pio_wdi : out std_logic;
+ -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X';
+ -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0);
+ -- export
+ areset_to_the_altpll_0 : in std_logic := 'X';
+ -- export
+ locked_from_the_altpll_0 : out std_logic;
+ -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ c3_from_the_altpll_0 : out std_logic;
+ -- export
+ to_mm_arbiter_reset_export : out std_logic;
+ -- export
+ to_mm_arbiter_clk_export : out std_logic;
+ -- export
+ to_mm_arbiter_address_export : out std_logic_vector(10 downto 0);
+ -- export
+ to_mm_arbiter_write_export : out std_logic;
+ -- export
+ to_mm_arbiter_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ to_mm_arbiter_read_export : out std_logic;
+ -- export
+ to_mm_arbiter_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X')
);
end component qsys_unb1_minimal_mm_arbiter;
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
index fbb7e941a498c245f4b613ce475fb52afcdcbf16..404a1a877462600d856a9f1ed4d976ab4623aac9 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
@@ -31,20 +31,29 @@ entity unb1_minimal is
generic (
g_design_name : string := "unb1_minimal";
g_design_note : string := "UNUSED";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : integer := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : integer := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -112,12 +121,16 @@ architecture str of unb1_minimal is
-- eth1g
signal eth1g_tse_clk : std_logic;
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -220,7 +233,8 @@ begin
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
diff --git a/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
index 4ffbccca21578df961a7fefa384f08dd05e2bbd5..0b433db48399510e2284821c1a76c4effb563326 100644
--- a/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
@@ -52,23 +52,28 @@ use common_lib.tb_common_pkg.all;
entity tb_unb1_minimal is
generic (
g_design_name : string := "unb1_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Back node 3
+ g_sim_node_nr : natural := 7
);
end tb_unb1_minimal;
architecture tb of tb_unb1_minimal is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 7; -- Back node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Back node 3
+ constant c_node_nr : natural := 7;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb1_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
+ -- 25 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 40 ns;
constant c_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -93,28 +98,41 @@ architecture tb of tb_unb1_minimal is
signal sens_sda : std_logic;
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
index 438450102620f3443679561df9df3d0682264f75..a6de05a946be4921944ddb4504ca7fad01c588a1 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -311,7 +311,8 @@ begin
wait until rising_edge(mm_clk);
proc_tech_tse_setup(c_tech_stratixiv, false, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi);
sim_eth_mm_bus_switch <= '0';
wait;
end process;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
index f70200f9e086dfadf9bf9f00fef0540ef1e0761b..f3362dd20586103240f8e08f526806d51f67c035 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
@@ -47,31 +47,44 @@ entity node_unb1_terminal_bg_mesh_db is
-- MESH TERMINAL
-- System
- g_node_type : t_e_unb1_board_node := e_any; -- or e_fn, or e_bn
- g_nof_bus : natural := 4; -- one bus to each of the 4 nodes on the other side of the mesh
+ -- or e_fn, or e_bn
+ g_node_type : t_e_unb1_board_node := e_any;
+ -- one bus to each of the 4 nodes on the other side of the mesh
+ g_nof_bus : natural := 4;
-- User
- g_usr_use_complex : boolean := false; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
- g_usr_data_w : natural := 16; -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit
+ -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ g_usr_use_complex : boolean := false;
+ -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit
+ g_usr_data_w : natural := 16;
g_usr_frame_len : natural := 20;
- g_usr_nof_streams : natural := 3; -- number of user streams per bus
+ -- number of user streams per bus
+ g_usr_nof_streams : natural := 3;
-- Phy
- g_phy_nof_serial : natural := 3; -- up to 4 serial lanes per bus
+ -- up to 4 serial lanes per bus
+ g_phy_nof_serial : natural := 3;
g_phy_gx_mbps : natural := 5000;
- g_phy_rx_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY
+ -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY
+ g_phy_rx_fifo_size : natural := c_bram_m9k_fifo_depth;
g_phy_ena_reorder : boolean := true;
-- Tx
g_use_tx : boolean := true;
- g_tx_input_use_fifo : boolean := true; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
- g_tx_input_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ g_tx_input_use_fifo : boolean := true;
+ -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ g_tx_input_fifo_size : natural := c_bram_m9k_fifo_depth;
g_tx_input_fifo_fill : natural := 0;
-- Rx
g_use_rx : boolean := true;
- g_rx_output_use_fifo : boolean := true; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_output_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_use_fifo : boolean := true;
+ -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ g_rx_output_fifo_size : natural := c_bram_m9k_fifo_depth;
g_rx_output_fifo_fill : natural := 0;
- g_rx_timeout_w : natural := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ g_rx_timeout_w : natural := 0;
-- Monitoring
- g_mon_select : natural := 0; -- 0 = no SOSI data buffers monitor via MM
+ -- 0 = no SOSI data buffers monitor via MM
+ g_mon_select : natural := 0;
-- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
-- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
-- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
@@ -81,27 +94,35 @@ entity node_unb1_terminal_bg_mesh_db is
g_mon_nof_words : natural := 1024;
g_mon_use_sync : boolean := true;
-- UTH
- g_uth_len_max : natural := 255; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
- g_uth_typ_ofs : natural := 256; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ g_uth_len_max : natural := 255;
+ -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ g_uth_typ_ofs : natural := 256;
-- Auxiliary Interface
g_aux : t_c_unb1_board_aux := c_unb1_board_aux;
-- BSN ALIGNER
- g_use_bsn_align : boolean := true; -- default TRUE, support FALSE for packet flow debugging purposes (faster synthesis)
+ -- default TRUE, support FALSE for packet flow debugging purposes (faster synthesis)
+ g_use_bsn_align : boolean := true;
-- DATA BUFFER
g_use_data_buf : boolean := true
);
port(
-- System
- chip_id : in std_logic_vector(g_aux.chip_id_w - 1 downto 0); -- [2:0]
+ -- [2:0]
+ chip_id : in std_logic_vector(g_aux.chip_id_w - 1 downto 0);
mm_rst : in std_logic;
- mm_clk : in std_logic; -- 50 MHz from xo_clk PLL in SOPC system
+ -- 50 MHz from xo_clk PLL in SOPC system
+ mm_clk : in std_logic;
dp_rst : in std_logic;
- dp_clk : in std_logic; -- 200 MHz from CLK system clock
+ -- 200 MHz from CLK system clock
+ dp_clk : in std_logic;
dp_pps : in std_logic := '0';
- tr_mesh_clk : in std_logic; -- 156.25 MHz from SB_CLK transceiver clock
- cal_clk : in std_logic; -- 40 MHz from xo_clk PLL in SOPC system
+ -- 156.25 MHz from SB_CLK transceiver clock
+ tr_mesh_clk : in std_logic;
+ -- 40 MHz from xo_clk PLL in SOPC system
+ cal_clk : in std_logic;
-- MM interface
-- . block generator
@@ -128,13 +149,17 @@ entity node_unb1_terminal_bg_mesh_db is
-- Datapath User interface (4 nodes)(4 input streams)
tx_usr_siso_2arr : out t_unb1_board_mesh_siso_2arr;
- tx_usr_sosi_2arr : in t_unb1_board_mesh_sosi_2arr := (others => (others => c_dp_sosi_rst)); -- Tx
+ -- Tx
+ tx_usr_sosi_2arr : in t_unb1_board_mesh_sosi_2arr := (others => (others => c_dp_sosi_rst));
rx_usr_siso_2arr : in t_unb1_board_mesh_siso_2arr := (others => (others => c_dp_siso_rdy));
- rx_usr_sosi_2arr : out t_unb1_board_mesh_sosi_2arr; -- Rx
+ -- Rx
+ rx_usr_sosi_2arr : out t_unb1_board_mesh_sosi_2arr;
-- Mesh serial interface (tr_nonbonded)
- tx_serial_2arr : out t_unb1_board_mesh_sl_2arr; -- Tx
- rx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0')) -- Rx support for diagnostics
+ -- Tx
+ tx_serial_2arr : out t_unb1_board_mesh_sl_2arr;
+ -- Rx support for diagnostics
+ rx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0'))
);
end node_unb1_terminal_bg_mesh_db;
@@ -143,7 +168,8 @@ architecture str of node_unb1_terminal_bg_mesh_db is
-- Block Generator
-----------------------------------------------------------------------------
constant c_use_usr_input : boolean := not(g_use_bg);
- constant c_bg_nof_streams : natural := g_nof_bus * g_usr_nof_streams; -- 4 x 3 = 12
+ -- 4 x 3 = 12
+ constant c_bg_nof_streams : natural := g_nof_bus * g_usr_nof_streams;
constant c_in_dat_w : natural := g_usr_data_w;
constant c_bg_addr_w : natural := 7;
constant c_file_name_prefix : string := "hex/bg_in_data";
@@ -152,11 +178,14 @@ architecture str of node_unb1_terminal_bg_mesh_db is
-- BSN Aligner
-----------------------------------------------------------------------------
constant c_bsn_align_nof_streams : natural := c_bg_nof_streams;
- constant c_block_size : natural := 128; -- FIXME: current fn_beamformer output block size.
+ -- FIXME: current fn_beamformer output block size.
+ constant c_block_size : natural := 128;
constant c_block_period : natural := 192;
constant c_bsn_align_latency : natural := 3;
- constant c_bsn_align_xoff_timeout : natural := c_bsn_align_latency * 2 * c_block_period; -- flush factor 2 longer than needed
- constant c_bsn_align_sop_timeout : natural := (c_bsn_align_latency + 1) * c_block_period; -- wait somewhat more than c_bsn_align_latency periods
+ -- flush factor 2 longer than needed
+ constant c_bsn_align_xoff_timeout : natural := c_bsn_align_latency * 2 * c_block_period;
+ -- wait somewhat more than c_bsn_align_latency periods
+ constant c_bsn_align_sop_timeout : natural := (c_bsn_align_latency + 1) * c_block_period;
-----------------------------------------------------------------------------
-- BSN Monitor
@@ -303,9 +332,11 @@ begin
-- User interface (4 nodes)(4 input streams)
tx_usr_siso_2arr => bg_out_siso_2arr,
- tx_usr_sosi_2arr => bg_out_sosi_2arr, -- <== Data to the Mesh
+ -- <== Data to the Mesh
+ tx_usr_sosi_2arr => bg_out_sosi_2arr,
rx_usr_siso_2arr => rx_usr_i_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_i_sosi_2arr, -- ==> Data from the Mesh
+ -- ==> Data from the Mesh
+ rx_usr_sosi_2arr => rx_usr_i_sosi_2arr,
-- Serial (tr_nonbonded)
tx_serial_2arr => tx_serial_2arr,
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
index ec6f3afdfdca813569388e2c23ac27861bc3f7d1..498d1925fb1f016ea93dbe1214486264f02f4ff1 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
@@ -38,21 +38,30 @@ entity unb1_terminal_bg_mesh_db is
-- General
g_design_name : string := "unb1_terminal_bg_mesh_db";
g_design_note : string := "UNUSED";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_level : natural := 0;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -69,7 +78,8 @@ entity unb1_terminal_bg_mesh_db is
ETH_SGOUT : out std_logic;
-- Transceiver clocks
- SB_CLK : in std_logic := '0'; -- TR clock FN-BN (mesh)
+ -- TR clock FN-BN (mesh)
+ SB_CLK : in std_logic := '0';
-- Serial I/O
FN_BN_0_TX : out std_logic_vector(c_unb1_board_tr_mesh.bus_w - 1 downto 0);
@@ -85,40 +95,61 @@ end unb1_terminal_bg_mesh_db;
architecture str of unb1_terminal_bg_mesh_db is
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 1, 0, 0, 0, 0, 1);
- constant c_fw_version : t_unb1_board_fw_version := (1, 0); -- firmware version x.y
+ -- firmware version x.y
+ constant c_fw_version : t_unb1_board_fw_version := (1, 0);
constant c_use_bg : boolean := true;
- constant c_node_type : t_e_unb1_board_node := e_any; -- or e_fn, or e_bn
- constant c_nof_bus : natural := 4; -- one bus to each of the 4 nodes on the other side of the mesh
- constant c_usr_use_complex : boolean := false; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
- constant c_usr_data_w : natural := 16; -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit
- constant c_usr_frame_len : natural := 128; -- 20;
- constant c_usr_nof_streams : natural := 3; -- number of user streams per bus
- constant c_phy_nof_serial : natural := 3; -- up to 4 serial lanes per bus
- constant c_phy_gx_mbps : natural := 6250; -- 5000;
- constant c_phy_rx_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY
+ -- or e_fn, or e_bn
+ constant c_node_type : t_e_unb1_board_node := e_any;
+ -- one bus to each of the 4 nodes on the other side of the mesh
+ constant c_nof_bus : natural := 4;
+ -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ constant c_usr_use_complex : boolean := false;
+ -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit
+ constant c_usr_data_w : natural := 16;
+ -- 20;
+ constant c_usr_frame_len : natural := 128;
+ -- number of user streams per bus
+ constant c_usr_nof_streams : natural := 3;
+ -- up to 4 serial lanes per bus
+ constant c_phy_nof_serial : natural := 3;
+ -- 5000;
+ constant c_phy_gx_mbps : natural := 6250;
+ -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY
+ constant c_phy_rx_fifo_size : natural := c_bram_m9k_fifo_depth;
constant c_phy_ena_reorder : boolean := true;
constant c_use_tx : boolean := true;
- constant c_tx_input_use_fifo : boolean := true; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
- constant c_tx_input_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ constant c_tx_input_use_fifo : boolean := true;
+ -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ constant c_tx_input_fifo_size : natural := c_bram_m9k_fifo_depth;
constant c_tx_input_fifo_fill : natural := 0;
constant c_use_rx : boolean := true;
- constant c_rx_output_use_fifo : boolean := true; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- constant c_rx_output_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ constant c_rx_output_use_fifo : boolean := true;
+ -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ constant c_rx_output_fifo_size : natural := c_bram_m9k_fifo_depth;
constant c_rx_output_fifo_fill : natural := 128;
- constant c_rx_timeout_w : natural := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ constant c_rx_timeout_w : natural := 0;
constant c_mon_select : natural := 0;
constant c_mon_nof_words : natural := 1024;
constant c_mon_use_sync : boolean := true;
- constant c_uth_len_max : natural := 255; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
- constant c_uth_typ_ofs : natural := 256; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ constant c_uth_len_max : natural := 255;
+ -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ constant c_uth_typ_ofs : natural := 256;
constant c_aux : t_c_unb1_board_aux := c_unb1_board_aux;
- constant c_use_bsn_align : boolean := true; -- default TRUE, support FALSE for packet flow debugging purposes (faster synthesis)
+ -- default TRUE, support FALSE for packet flow debugging purposes (faster synthesis)
+ constant c_use_bsn_align : boolean := true;
constant c_use_data_buf : boolean := true;
- constant c_mesh_mon_select : natural := 1; -- > 0 = enable SOSI data buffers monitor via MM
- constant c_mesh_mon_nof_words : natural := c_unb1_board_peripherals_mm_reg_default.ram_diag_db_buf_size; -- = 1024
- constant c_mesh_mon_use_sync : boolean := true; -- when TRUE use dp_pps to trigger the data buffer capture, else new data capture after read access of last data word
+ -- > 0 = enable SOSI data buffers monitor via MM
+ constant c_mesh_mon_select : natural := 1;
+ -- = 1024
+ constant c_mesh_mon_nof_words : natural := c_unb1_board_peripherals_mm_reg_default.ram_diag_db_buf_size;
+ -- when TRUE use dp_pps to trigger the data buffer capture, else new data capture after read access of last data word
+ constant c_mesh_mon_use_sync : boolean := true;
constant c_reg_diag_db_adr_w : natural := 5;
@@ -137,7 +168,8 @@ architecture str of unb1_terminal_bg_mesh_db is
signal dp_clk : std_logic;
signal dp_pps : std_logic;
- signal this_chip_id : std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0); -- [2:0], so range 0-3 for FN and range 4-7 BN
+ -- [2:0], so range 0-3 for FN and range 4-7 BN
+ signal this_chip_id : std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0);
-- PIOs
signal pout_debug_wave : std_logic_vector(c_word_w - 1 downto 0);
@@ -158,28 +190,37 @@ architecture str of unb1_terminal_bg_mesh_db is
signal rom_unb_system_info_miso : t_mem_miso;
-- UniBoard I2C sens
- signal reg_unb_sens_mosi : t_mem_mosi; -- mms_unb_sens registers
+ -- mms_unb_sens registers
+ signal reg_unb_sens_mosi : t_mem_mosi;
signal reg_unb_sens_miso : t_mem_miso;
-- eth1g
signal eth1g_mm_rst : std_logic;
signal eth1g_tse_clk : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_ram_miso : t_mem_miso;
signal tx_usr_siso_2arr : t_unb1_board_mesh_siso_2arr := (others => (others => c_dp_siso_rdy));
- signal tx_usr_sosi_2arr : t_unb1_board_mesh_sosi_2arr := (others => (others => c_dp_sosi_rst)); -- Tx
+ -- Tx
+ signal tx_usr_sosi_2arr : t_unb1_board_mesh_sosi_2arr := (others => (others => c_dp_sosi_rst));
signal rx_usr_siso_2arr : t_unb1_board_mesh_siso_2arr := (others => (others => c_dp_siso_rdy));
- signal rx_usr_sosi_2arr : t_unb1_board_mesh_sosi_2arr := (others => (others => c_dp_sosi_rst)); -- Rx
+ -- Rx
+ signal rx_usr_sosi_2arr : t_unb1_board_mesh_sosi_2arr := (others => (others => c_dp_sosi_rst));
-- tr_mesh
- signal tx_serial_2arr : t_unb1_board_mesh_sl_2arr; -- Tx
- signal rx_serial_2arr : t_unb1_board_mesh_sl_2arr; -- Rx support for diagnostics
+ -- Tx
+ signal tx_serial_2arr : t_unb1_board_mesh_sl_2arr;
+ -- Rx support for diagnostics
+ signal rx_serial_2arr : t_unb1_board_mesh_sl_2arr;
-- MM tr_nonbonded with diagnostics
signal reg_tr_nonbonded_mosi : t_mem_mosi := c_mem_mosi_rst;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
index 4069b5616d5cc8fc41c9b8f6975c3b1cf71290bd..5fd5fe77f2256dc030078db513231d8193007c89 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
@@ -52,9 +52,12 @@ architecture tb of tb_unb1_terminal_bg_mesh_db is
constant c_cable_delay : time := 12 ns;
- constant c_ext_clk_period : time := 5 ns; -- 200 MHz
- constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
- constant c_tr_clk_period : time := 6400 ps; -- 156.25 MHz XO on UniBoard
+ -- 200 MHz
+ constant c_ext_clk_period : time := 5 ns;
+ -- 25 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 40 ns;
+ -- 156.25 MHz XO on UniBoard
+ constant c_tr_clk_period : time := 6400 ps;
type t_mesh_arr is array (c_nof_nodes - 1 downto 0) of std_logic_vector(c_unb1_board_tr_mesh.bus_w - 1 downto 0);
@@ -96,17 +99,25 @@ architecture tb of tb_unb1_terminal_bg_mesh_db is
signal fn_out_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
begin
-- Run 1 ms
- ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- 1GbE XO clock (25 MHz)
- tr_clk <= not tr_clk after c_tr_clk_period / 2; -- Transceiver clock (156.25 MHz)
-
- ext_pps <= '0'; -- not used
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ ext_clk <= not ext_clk after c_ext_clk_period / 2;
+ -- 1GbE XO clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- Transceiver clock (156.25 MHz)
+ tr_clk <= not tr_clk after c_tr_clk_period / 2;
+
+ -- not used
+ ext_pps <= '0';
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
VERSION <= c_version;
@@ -132,7 +143,8 @@ begin
-- Others
VERSION => VERSION,
- ID => TO_UVEC(BN + 4, c_unb1_board_aux.id_w), -- BN chip ID 4,5,6,7
+ -- BN chip ID 4,5,6,7
+ ID => TO_UVEC(BN + 4, c_unb1_board_aux.id_w),
TESTIO => TESTIO,
-- I2C Interface to Sensors
@@ -140,12 +152,14 @@ begin
sens_sd => sens_sda,
-- 1GbE Control Interface
- ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
+ -- ETH reference clock also used for system reference clock
+ ETH_clk => eth_clk,
ETH_SGIN => eth_rxp(BN + c_nof_fn),
ETH_SGOUT => eth_txp(BN + c_nof_fn),
-- Transceiver clocks
- SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
+ -- TR clock FN-BN(mesh)
+ SB_CLK => tr_clk,
-- Mesh serial I/O
FN_BN_0_TX => FN_BN_0_TX_arr(BN + c_nof_fn),
@@ -198,7 +212,8 @@ begin
-- Others
VERSION => VERSION,
- ID => TO_UVEC(FN, c_unb1_board_aux.id_w), -- FN chip ID 0,1,2,3,
+ -- FN chip ID 0,1,2,3,
+ ID => TO_UVEC(FN, c_unb1_board_aux.id_w),
TESTIO => TESTIO,
-- I2C Interface to Sensors
@@ -206,12 +221,14 @@ begin
sens_sd => sens_sda,
-- 1GbE Control Interface
- ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
+ -- ETH reference clock also used for system reference clock
+ ETH_clk => eth_clk,
ETH_SGIN => eth_rxp(FN),
ETH_SGOUT => eth_txp(FN),
-- Transceiver clocks
- SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
+ -- TR clock FN-BN(mesh)
+ SB_CLK => tr_clk,
-- Mesh serial I/O
FN_BN_0_TX => FN_BN_0_TX_arr(FN),
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
index e81056c6c6ca96cf753ae4d3907cf9546c9b5151..5fec81ebfe966c87f598bc122bebc1726b2ebebe 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
@@ -35,6 +35,7 @@ begin
generic map (
g_design_name => "unb1_test_10GbE",
--g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
+ -- FN0
+ g_sim_node_nr => 0
);
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
index b0979cb122226b362df92eefb5f996545d98235f..cfcef5fa126432f8ad02214ce630434286057dcd 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
@@ -28,22 +28,33 @@ use technology_lib.technology_select_pkg.all;
entity unb1_test_10GbE is
generic (
- g_design_name : string := "unb1_test_10GbE"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_test_10GbE";
g_design_note : string := "Test Design with 10GbE";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
- g_sim_node_nr : natural := 0; -- FN0
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- FN0
+ g_sim_node_nr : natural := 0;
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -60,7 +71,8 @@ entity unb1_test_10GbE is
ETH_SGOUT : out std_logic;
-- Transceiver clocks
- SA_CLK : in std_logic; -- SerDes Clock BN-BI / SI_FN
+ -- SerDes Clock BN-BI / SI_FN
+ SA_CLK : in std_logic;
-- Serial I/O
SI_FN_0_TX : out std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
@@ -72,11 +84,13 @@ entity unb1_test_10GbE is
SI_FN_3_TX : out std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
SI_FN_3_RX : in std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
- SI_FN_0_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0); -- (0 = LASI; 1=MDC; 2=MDIO)
+ -- (0 = LASI; 1=MDC; 2=MDIO)
+ SI_FN_0_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_1_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_2_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_3_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
- SI_FN_RSTN : out std_logic := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ SI_FN_RSTN : out std_logic := '1';
BN_BI_0_TX : out std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
BN_BI_0_RX : in std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
index d5bd19a9c3283e8b1302638e11c1c0abae86ce6b..2ffbd21da245feb456d5cf7ef029718105d47772 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
@@ -35,6 +35,7 @@ begin
generic map (
g_design_name => "unb1_test_10GbE_tx_only",
--g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
+ -- FN0
+ g_sim_node_nr => 0
);
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
index 3043972db629a52b6dfa4e96c2b9864da10aad4b..8ef03b589aad5391801c260407ae7d8a222fada5 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
@@ -28,22 +28,33 @@ use technology_lib.technology_select_pkg.all;
entity unb1_test_10GbE_tx_only is
generic (
- g_design_name : string := "unb1_test_10GbE_tx_only"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_test_10GbE_tx_only";
g_design_note : string := "Test Design with 10GbE Tx only";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
- g_sim_node_nr : natural := 0; -- FN0
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- FN0
+ g_sim_node_nr : natural := 0;
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -60,7 +71,8 @@ entity unb1_test_10GbE_tx_only is
ETH_SGOUT : out std_logic;
-- Transceiver clocks
- SA_CLK : in std_logic; -- SerDes Clock BN-BI / SI_FN
+ -- SerDes Clock BN-BI / SI_FN
+ SA_CLK : in std_logic;
-- Serial I/O
SI_FN_0_TX : out std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
@@ -72,11 +84,13 @@ entity unb1_test_10GbE_tx_only is
SI_FN_3_TX : out std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
SI_FN_3_RX : in std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
- SI_FN_0_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0); -- (0 = LASI; 1=MDC; 2=MDIO)
+ -- (0 = LASI; 1=MDC; 2=MDIO)
+ SI_FN_0_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_1_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_2_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_3_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
- SI_FN_RSTN : out std_logic := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ SI_FN_RSTN : out std_logic := '1'
);
end unb1_test_10GbE_tx_only;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
index c56b4f415af6b3b865a88031151e7d205b25a345..17ffb2530b9a89eb1ee5df8e9a254fbec4b1ee1f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
@@ -35,6 +35,7 @@ begin
generic map (
g_design_name => "unb1_test_1GbE",
--g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
+ -- FN0
+ g_sim_node_nr => 0
);
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
index 4ce67372f9f115a50cea341e785b020925f39eac..11e95befc36014b6fd183d7bd5f5f20db98c7766 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
@@ -28,22 +28,33 @@ use technology_lib.technology_select_pkg.all;
entity unb1_test_1GbE is
generic (
- g_design_name : string := "unb1_test_1GbE"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_test_1GbE";
g_design_note : string := "Test Design with 1GbE";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
- g_sim_node_nr : natural := 0; -- FN0
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- FN0
+ g_sim_node_nr : natural := 0;
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
index c5dc616e081843f7d741d75432356777dfec2b9b..b0c880d08f10e186123314de0d0267d3833e13bd 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
@@ -35,6 +35,7 @@ begin
generic map (
g_design_name => "unb1_test_all",
--g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
+ -- FN0
+ g_sim_node_nr => 0
);
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
index d17bc71fa1fbc013fdfabeb004a906d400dbeb87..add0db976dbe4ee4ab23041fcc5993a9fe211e90 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
@@ -29,22 +29,33 @@ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_all is
generic (
- g_design_name : string := "unb1_test_all"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_test_all";
g_design_note : string := "Test Design with all";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
- g_sim_node_nr : natural := 0; -- FN0
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- FN0
+ g_sim_node_nr : natural := 0;
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -61,7 +72,8 @@ entity unb1_test_all is
ETH_SGOUT : out std_logic;
-- Transceiver clocks
- SA_CLK : in std_logic; -- SerDes Clock BN-BI / SI_FN
+ -- SerDes Clock BN-BI / SI_FN
+ SA_CLK : in std_logic;
-- Serial I/O
SI_FN_0_TX : out std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
@@ -73,11 +85,13 @@ entity unb1_test_all is
SI_FN_3_TX : out std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
SI_FN_3_RX : in std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
- SI_FN_0_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0); -- (0 = LASI; 1=MDC; 2=MDIO)
+ -- (0 = LASI; 1=MDC; 2=MDIO)
+ SI_FN_0_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_1_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_2_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_3_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
- SI_FN_RSTN : out std_logic := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ SI_FN_RSTN : out std_logic := '1';
BN_BI_0_TX : out std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
BN_BI_0_RX : in std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
index 969c0768bd86ee7176b7cc6d416635f8877f0eeb..e3a43a05e5efa1d1192a5654c4c6d009f7c22f1b 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
@@ -35,6 +35,7 @@ begin
generic map (
g_design_name => "unb1_test_ddr",
--g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
+ -- FN0
+ g_sim_node_nr => 0
);
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
index df41e0d91aa2d46276cfdedd4fe24ed6c6f178dd..cd3f770aabebefede80b1ccd13986d632a9f6c7e 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
@@ -29,22 +29,33 @@ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr is
generic (
- g_design_name : string := "unb1_test_ddr"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_test_ddr";
g_design_note : string := "Test Design with ddr";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
- g_sim_node_nr : natural := 0; -- FN0
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- FN0
+ g_sim_node_nr : natural := 0;
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
index 3dac8535f14e5439141cc3f0b2c24c215e38af24..49f4965ba0a37626c56ee0d6869ffa1e9078297e 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
@@ -35,6 +35,7 @@ begin
generic map (
g_design_name => "unb1_test_ddr_16g_MB_I",
--g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
+ -- FN0
+ g_sim_node_nr => 0
);
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
index 6f4ce8542b20eef5ee2826a2341f7f82603ee915..e21ce2c5289438a55f2c48bb86d62e230c9b2abe 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
@@ -29,22 +29,33 @@ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_16g_MB_I is
generic (
- g_design_name : string := "unb1_test_ddr_16g_MB_I"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_test_ddr_16g_MB_I";
g_design_note : string := "Test with 16GB MB_I DDR3";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
- g_sim_node_nr : natural := 0; -- FN0
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- FN0
+ g_sim_node_nr : natural := 0;
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
index 51e1bc635bf8462d08ea93c8bbf96c7da5a43486..d32a86716fda6eb7f31d7d37c89c5cde371960e3 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
@@ -35,6 +35,7 @@ begin
generic map (
g_design_name => "unb1_test_ddr_16g_MB_II",
--g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
+ -- FN0
+ g_sim_node_nr => 0
);
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
index af5925eda507c7a76e0257690a9d885df47dcd9a..cd9033edc4d5152b83f15e2b5e20b0ead4a80c71 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
@@ -29,22 +29,33 @@ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_16g_MB_II is
generic (
- g_design_name : string := "unb1_test_ddr_16g_MB_II"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_test_ddr_16g_MB_II";
g_design_note : string := "Test with 16GB MB_II DDR3";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
- g_sim_node_nr : natural := 0; -- FN0
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- FN0
+ g_sim_node_nr : natural := 0;
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
index 29cb419b28d29b88ebc26bac8a44f34c3f0c40d6..5af4ef01f6ae667b531741b8a61bf64cb29bfa36 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
@@ -35,6 +35,7 @@ begin
generic map (
g_design_name => "unb1_test_ddr_16g_MB_I_II",
--g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
+ -- FN0
+ g_sim_node_nr => 0
);
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
index 8b8d0ee03e1c1620edc7073b57d164521b6a46de..d168425ec3df6e1f5a6aba0b9cd283596d70cea1 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
@@ -29,22 +29,33 @@ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_16g_MB_I_II is
generic (
- g_design_name : string := "unb1_test_ddr_16g_MB_I_II"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_test_ddr_16g_MB_I_II";
g_design_note : string := "Test with 16GB MB I and II DDR3";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
- g_sim_node_nr : natural := 0; -- FN0
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- FN0
+ g_sim_node_nr : natural := 0;
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
index 12ef1917691d1dd94bf1796d79807d0c7e2395c7..0d87557a7d0f0661132b65da9318ad6c84d24cd6 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
@@ -35,6 +35,7 @@ begin
generic map (
g_design_name => "unb1_test_ddr_MB_I",
--g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
+ -- FN0
+ g_sim_node_nr => 0
);
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
index dda6de35318a4df53541a3050cad7b0e003989ec..6221f96c0b6b091f7109a7ebd081ea4c940b0ce7 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
@@ -35,6 +35,7 @@ begin
generic map (
g_design_name => "unb1_test_ddr_MB_II",
--g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
+ -- FN0
+ g_sim_node_nr => 0
);
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
index c1f597d928df224812b1fc30abae65f8fe69fae1..9e102317a3b8d072a7a22d9cbf37645dcda307a0 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
@@ -35,6 +35,7 @@ begin
generic map (
g_design_name => "unb1_test_ddr_MB_I_II",
--g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 1 -- FN0
+ -- FN0
+ g_sim_node_nr => 1
);
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
index f5524185b2b14002e0a574f0c58d1e38e60e3e3c..62bd43776857d4836fd9dd668ee7e970d568c3af 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
@@ -29,22 +29,33 @@ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_MB_I_II is
generic (
- g_design_name : string := "unb1_test_ddr_MB_I_II"; -- use revision name = entity name = design name
+ -- use revision name = entity name = design name
+ g_design_name : string := "unb1_test_ddr_MB_I_II";
g_design_note : string := "Test Design with 2-ch ddr";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
- g_sim_node_nr : natural := 0; -- FN0
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- FN0
+ g_sim_node_nr : natural := 0;
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 7e468fa82dd68c100cdca0d5f9bdb6d5d6a42c56..673160021d661f0639f02ec9acba2917fcfc6a91 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -42,7 +42,8 @@ use work.unb1_test_pkg.all;
entity mmm_unb1_test is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_nof_streams_1GbE : natural;
@@ -202,7 +203,8 @@ architecture str of mmm_unb1_test is
constant c_ram_diag_databuffer_ddr_addr_w : natural := ceil_log2(2 * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
- constant c_reg_dp_offload_tx_adr_w : natural := 1; -- Dev note: add to c_unb1_board_peripherals_mm_reg_default
+ -- Dev note: add to c_unb1_board_peripherals_mm_reg_default
+ constant c_reg_dp_offload_tx_adr_w : natural := 1;
constant c_reg_dp_offload_tx_1GbE_multi_adr_w : natural := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
constant c_reg_dp_offload_tx_10GbE_multi_adr_w : natural := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_dp_offload_tx_adr_w));
@@ -350,10 +352,12 @@ begin
u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
- u_mm_file_reg_tr_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE") -- , c_mm_clk_period, FALSE, 0)
+ -- , c_mm_clk_period, FALSE, 0)
+ u_mm_file_reg_tr_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE")
port map(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso);
- u_mm_file_reg_tr_xaui : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI") -- , c_mm_clk_period, FALSE, 0)
+ -- , c_mm_clk_period, FALSE, 0)
+ u_mm_file_reg_tr_xaui : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI")
port map(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso);
----------------------------------------------------------------------------
@@ -370,7 +374,8 @@ begin
proc_tech_tse_setup(c_tech_stratixiv, false, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi);
sim_eth_mm_bus_switch <= '0';
wait;
@@ -490,7 +495,8 @@ begin
-- the_pio_pps
coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
index 3c257fae3c3952152f5c7f2c4966ff5fd449cf8c..2d60956b573ab19abc03a82ddd5cf5e40ed593cd 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
@@ -28,331 +28,656 @@ package qsys_unb1_test_pkg is
-----------------------------------------------------------------------------
component qsys_unb1_test is
port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
- coe_waitrequest_export_to_the_reg_tr_10GbE : in std_logic := 'X'; -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_tr_xaui : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_tr_xaui : out std_logic_vector(10 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_waitrequest_export_to_the_reg_tr_xaui : in std_logic := 'X'; -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_reset_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
- coe_address_export_from_the_reg_tr_10GbE : out std_logic_vector(14 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_tr_xaui : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_tr_10GbE : out std_logic_vector(31 downto 0); -- export
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_clk_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_clk_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- coe_readdata_export_to_the_reg_tr_10GbE : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reset_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_remu : out std_logic; -- export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(11 downto 0); -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_10gbe_read_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_10gbe_write_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_offload_tx_10gbe_clk_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_offload_tx_1gbe_write_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_1gbe_read_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_1gbe_write_export : out std_logic; -- export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_1gbe_read_export : out std_logic; -- export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0); -- export
- ram_diag_bg_1gbe_write_export : out std_logic; -- export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_1gbe_read_export : out std_logic; -- export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ -- export
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0);
+ -- export
+ coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0);
+ -- export
+ coe_waitrequest_export_to_the_reg_tr_10GbE : in std_logic := 'X';
+ -- export
+ coe_reset_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0);
+ -- export
+ coe_write_export_from_the_reg_tr_xaui : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_tr_xaui : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0);
+ -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0);
+ -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_remu : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ coe_address_export_from_the_reg_tr_xaui : out std_logic_vector(10 downto 0);
+ -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0);
+ -- export
+ coe_read_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0);
+ -- export
+ coe_waitrequest_export_to_the_reg_tr_xaui : in std_logic := 'X';
+ -- export
+ coe_clk_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_write_export_from_the_reg_tr_10GbE : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_tr_xaui : out std_logic;
+ -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0);
+ -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0);
+ -- export
+ coe_address_export_from_the_reg_tr_10GbE : out std_logic_vector(14 downto 0);
+ -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0);
+ -- export
+ coe_write_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0);
+ -- export
+ coe_write_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_write_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X';
+ -- export
+ coe_read_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic;
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- export
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- clk
+ clk_0 : in std_logic := 'X';
+ -- export
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_tr_xaui : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0);
+ -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0);
+ -- export
+ coe_writedata_export_from_the_reg_tr_10GbE : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_read_export_from_the_reg_tr_10GbE : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_tr_10GbE : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0);
+ -- export
+ coe_read_export_from_the_reg_tr_xaui : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_read_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_write_export_from_the_reg_remu : out std_logic;
+ -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0);
+ -- export
+ out_port_from_the_pio_wdi : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_remu : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0);
+ -- export
+ coe_write_export_from_the_reg_epcs : out std_logic;
+ -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_write_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_tr_xaui : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_read_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0);
+ -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0);
+ -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic;
+ -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0);
+ -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X';
+ -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0);
+ -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0);
+ -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0);
+ -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0);
+ -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic;
+ -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0);
+ -- export
+ coe_readdata_export_to_the_reg_tr_10GbE : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_tr_10GbE : out std_logic;
+ -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ coe_read_export_from_the_reg_remu : out std_logic;
+ -- export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_1gbe_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_1gbe_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic;
+ -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_bg_10gbe_read_export : out std_logic;
+ -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_bg_10gbe_write_export : out std_logic;
+ -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(11 downto 0);
+ -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic;
+ -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_bg_10gbe_read_export : out std_logic;
+ -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_bg_10gbe_write_export : out std_logic;
+ -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic;
+ -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_read_export : out std_logic;
+ -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_write_export : out std_logic;
+ -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0);
+ -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_clk_export : out std_logic;
+ -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_reset_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_read_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_write_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0);
+ -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_clk_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_reset_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_offload_tx_10gbe_read_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_offload_tx_10gbe_write_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_10gbe_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_dp_offload_tx_10gbe_clk_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_10gbe_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_1gbe_reset_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_1gbe_clk_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dp_offload_tx_1gbe_write_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_offload_tx_1gbe_read_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic;
+ -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_reset_export : out std_logic;
+ -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_clk_export : out std_logic;
+ -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_write_export : out std_logic;
+ -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_read_export : out std_logic;
+ -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_bg_1gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_bg_1gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_bg_1gbe_write_export : out std_logic;
+ -- export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_bg_1gbe_read_export : out std_logic;
+ -- export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_bg_1gbe_reset_export : out std_logic;
+ -- export
+ ram_diag_bg_1gbe_clk_export : out std_logic;
+ -- export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ ram_diag_bg_1gbe_write_export : out std_logic;
+ -- export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_bg_1gbe_read_export : out std_logic;
+ -- export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(13 downto 0);
+ -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0);
+ -- export
+ reg_io_ddr_mb_i_write_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_io_ddr_mb_i_read_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0);
+ -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0);
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0);
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X')
);
end component qsys_unb1_test;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
index 2d696a1218f996dd3a87688ac3367ed18405558d..92bae9e70c82a51ed8c4e22e1ce58c3ba56c4970 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
@@ -59,9 +59,11 @@ entity udp_stream is
ID : in std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0);
-- blockgen mm
- reg_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- BG control register (one for all streams)
+ -- BG control register (one for all streams)
+ reg_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_diag_bg_miso : out t_mem_miso;
- ram_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream)
+ -- BG buffer RAM (one per stream)
+ ram_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_diag_bg_miso : out t_mem_miso;
reg_diag_tx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_diag_tx_seq_miso : out t_mem_miso;
@@ -100,8 +102,10 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
+ -- enable (disabled by default)
+ constant c_bg_ctrl : t_diag_block_gen := ('0',
+ -- enable_sync
+ '0',
TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
@@ -312,9 +316,11 @@ begin
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
generic map (
g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
+ -- g_data_w, --FIXME
+ g_data_w => 32,
g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
+ -- sync by reading last address of data buffer
+ g_buf_use_sync => false,
g_use_rx_seq => true
)
port map (
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index 428faa733ef9d0cd312c91c357cf64025323e96e..11ce7735840663070d9cb6591f4b0e3983977ae0 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -39,23 +39,33 @@ use work.unb1_test_pkg.all;
entity unb1_test is
generic (
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_design_name : string := "unb1_test"; -- set by QSF
+ -- set by QSF
+ g_design_name : string := "unb1_test";
g_design_note : string := "Test Design";
g_technology : natural := c_tech_stratixiv;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -72,7 +82,8 @@ entity unb1_test is
ETH_SGOUT : out std_logic;
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- SerDes Clock BN-BI / SI_FN
+ -- SerDes Clock BN-BI / SI_FN
+ SA_CLK : in std_logic := '0';
-- Serial I/O
SI_FN_0_TX : out std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
@@ -84,11 +95,13 @@ entity unb1_test is
SI_FN_3_TX : out std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
SI_FN_3_RX : in std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0) := (others => '0');
- SI_FN_0_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0); -- (0 = LASI; 1=MDC; 2=MDIO)
+ -- (0 = LASI; 1=MDC; 2=MDIO)
+ SI_FN_0_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_1_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_2_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_3_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
- SI_FN_RSTN : out std_logic := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ SI_FN_RSTN : out std_logic := '1';
BN_BI_0_TX : out std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
BN_BI_0_RX : in std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0) := (others => '0');
@@ -120,7 +133,8 @@ architecture str of unb1_test is
constant c_revision_select : t_unb1_test_config := func_unb1_test_sel_revision_rec(g_design_name);
-- ddr
- constant c_nof_MB : natural := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
+ -- Fixed control infrastructure for 2 modules per FPGA
+ constant c_nof_MB : natural := c_unb1_board_nof_ddr3;
constant c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(c_revision_select.use_streaming_1GbE, 1, 0),
c_revision_select.use_front, 0,
@@ -134,18 +148,23 @@ architecture str of unb1_test is
constant c_nof_streams_1GbE : natural := c_revision_select.use_nof_streams_1GbE;
constant c_nof_streams_ddr : natural := c_revision_select.use_nof_streams_ddr;
constant c_nof_streams : natural := c_nof_streams_1GbE + c_nof_streams_10GbE + c_nof_streams_ddr;
- constant c_data_w_32 : natural := c_eth_data_w; -- 1GbE
- constant c_data_w_64 : natural := c_xgmii_data_w; -- 10GbE
+ -- 1GbE
+ constant c_data_w_32 : natural := c_eth_data_w;
+ -- 10GbE
+ constant c_data_w_64 : natural := c_xgmii_data_w;
-- Block generator constants
constant c_bg_block_size : natural := 900;
constant c_bg_gapsize_1GbE : natural := 1000;
constant c_bg_gapsize_10GbE : natural := 100;
- constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
+ -- 200000*(900+100) = 200000000 cycles = 1 second
+ constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000);
constant c_use_jumbo_frames : boolean := false;
- constant c_def_1GbE_block_size : natural := 20; -- 0 first so we have time to set RX demux reg in dest. node
- constant c_def_10GbE_block_size : natural := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
+ -- 0 first so we have time to set RX demux reg in dest. node
+ constant c_def_1GbE_block_size : natural := 20;
+ -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
+ constant c_def_10GbE_block_size : natural := 700;
constant c_max_frame_len : natural := sel_a_b(c_use_jumbo_frames, 9018, 1518);
constant c_nof_header_bytes : natural := field_slv_len(c_hdr_field_arr) / c_byte_w;
@@ -158,8 +177,10 @@ architecture str of unb1_test is
constant c_max_nof_blocks_per_packet_10GbE : natural := c_max_udp_payload_nof_words_10GbE / c_min_nof_words_per_block;
-- DDR3 constants
- constant c_wr_fifo_depth : natural := 1024; -- >=16 , defined at DDR side of the FIFO.
- constant c_rd_fifo_depth : natural := 1024; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
+ -- >=16 , defined at DDR side of the FIFO.
+ constant c_wr_fifo_depth : natural := 1024;
+ -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
+ constant c_rd_fifo_depth : natural := 1024;
constant c_use_db : boolean := false;
constant c_buf_nof_data : natural := 1024;
@@ -207,12 +228,15 @@ architecture str of unb1_test is
-- eth1g
signal eth1g_tse_clk : std_logic;
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
signal eth1g_reg_interrupt : std_logic;
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -488,8 +512,10 @@ begin
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_nof_streams_1GbE => c_nof_streams_1GbE,
- g_nof_streams_10GbE => 3, -- c_nof_streams_10GbE,
- g_nof_streams_ddr => 1, -- c_nof_streams_ddr,
+ -- c_nof_streams_10GbE,
+ g_nof_streams_10GbE => 3,
+ -- c_nof_streams_ddr,
+ g_nof_streams_ddr => 1,
g_bg_block_size => c_bg_block_size
)
port map(
@@ -781,7 +807,8 @@ begin
tr_ref_clk_156 => SA_CLK,
tr_ref_rst_156 => sa_rst,
- cal_rec_clk => cal_rec_clk, -- mm_clk, --cal_clk, mm_clk required by XAUI phy
+ -- mm_clk, --cal_clk, mm_clk required by XAUI phy
+ cal_rec_clk => cal_rec_clk,
-- MM interface
mm_rst => mm_rst,
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
index a1c4f5a3856ce1a8df548e1190e7af7fcedeb604..f32cad644af5ba2eddacc1fc9ad482d3ce097575 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
@@ -41,7 +41,8 @@ package unb1_test_pkg is
end record;
-- dp_offload_tx
- constant c_nof_hdr_fields : natural := 4 + 12 + 4 + 9; -- Total header bits = 512
+ -- Total header bits = 512
+ constant c_nof_hdr_fields : natural := 4 + 12 + 4 + 9;
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
diff --git a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
index fd3eea1c8906c14b0f5954900da4ffd3b0059732..0cc45fdb4cb04401644687e0a0a78f9c85372255 100644
--- a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
@@ -57,8 +57,10 @@ use work.unb1_test_pkg.all;
entity tb_unb1_test is
generic (
g_design_name : string := "unb1_test";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Back node 3
+ g_sim_node_nr : natural := 7
);
end tb_unb1_test;
@@ -70,7 +72,8 @@ architecture tb of tb_unb1_test is
constant c_fw_version : t_unb1_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
+ -- 25 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 40 ns;
constant c_clk_period : time := 5 ns;
constant c_sa_clk_period : time := 6.4 ns;
constant c_pps_period : natural := 1000;
@@ -117,29 +120,43 @@ architecture tb of tb_unb1_test is
signal phy_MB_II_ou : t_tech_ddr3_phy_ou;
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
- sa_clk <= not sa_clk after c_sa_clk_period / 2; -- sa clock (156.25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- sa clock (156.25 MHz)
+ sa_clk <= not sa_clk after c_sa_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
index 289839f6e9daa2b3af18e6de67b6f92ae6593bd0..4abfcad31783d09ed01dab7147adb3633947a8d9 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
@@ -41,18 +41,27 @@ use tech_tse_lib.tb_tech_tse_pkg.all;
entity unb1_tr_10GbE is
generic (
g_design_name : string := "unb1_tr_10GbE";
- g_sim : boolean := false; -- Overridden by TB
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Overridden by TB
+ g_sim : boolean := false;
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -69,7 +78,8 @@ entity unb1_tr_10GbE is
ETH_SGOUT : out std_logic;
-- Transceiver clocks
- SA_CLK : in std_logic; -- SerDes Clock BN-BI / SI_FN
+ -- SerDes Clock BN-BI / SI_FN
+ SA_CLK : in std_logic;
-- Serial I/O: 10GbE receivers
SI_FN_0_TX : out std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
@@ -85,21 +95,25 @@ entity unb1_tr_10GbE is
SI_FN_1_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_2_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_3_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
- SI_FN_RSTN : out std_logic := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ SI_FN_RSTN : out std_logic := '1'
-- So we need to assign a '1' to it.
);
end unb1_tr_10GbE;
architecture str of unb1_tr_10GbE is
constant c_use_phy : t_c_unb1_board_use_phy := (1, 1, 0, 0, 0, 0, 0, 1);
- constant c_nof_10GbE_streams : natural := 3; -- The number of 10G input streams
+ -- The number of 10G input streams
+ constant c_nof_10GbE_streams : natural := 3;
-- Block generator
constant c_bg_block_size : natural := 176;
constant c_bg_gapsize : natural := 256 - 176;
constant c_bg_blocks_per_sync : natural := 100;
- constant c_bg_ctrl : t_diag_block_gen := (sel_a_b(g_sim, '1', '0'), -- enable: On by default in simulation; MM enable required on hardware.
- '0', -- enable_sync
+ -- enable: On by default in simulation; MM enable required on hardware.
+ constant c_bg_ctrl : t_diag_block_gen := (sel_a_b(g_sim, '1', '0'),
+ -- enable_sync
+ '0',
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
@@ -124,7 +138,8 @@ architecture str of unb1_tr_10GbE is
signal eth1g_tse_clk : std_logic;
signal eth1g_mm_rst : std_logic;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
-- PIOs
signal pout_wdi : std_logic;
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
index 3c298d5e150f24bc44068be7a26b712e08eaa951..f4fb75a3f60e70d73c8eb14e26e23e7b54d0f2c3 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
@@ -37,15 +37,18 @@ end tb_unb1_tr_10GbE;
architecture tb of tb_unb1_tr_10GbE is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 7; -- Back node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Back node 3
+ constant c_node_nr : natural := 7;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb1_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
+ -- 25 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 40 ns;
constant c_sa_clk_period : time := 6.4 ns;
constant c_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -80,15 +83,21 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
sa_clk <= not sa_clk after c_sa_clk_period / 2;
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
index a26175ea386e55baf9e1192f275b4efe3d48cabb..324d265993824ed1784e719d49d1606243f36a38 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
@@ -45,18 +45,24 @@ entity ctrl_unb1_board is
----------------------------------------------------------------------------
g_technology : natural := c_tech_stratixiv;
g_sim : boolean := false;
- g_sim_level : natural := 0; -- when g_sim = TRUE, then 0 = use IP; 1 = use fast serdes model
- g_sim_flash_model : boolean := false; -- only maximum one instance should have the flash model (see mms_epcs.vhd description)
- g_base_ip : std_logic_vector(16 - 1 downto 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy
+ -- when g_sim = TRUE, then 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
+ -- only maximum one instance should have the flash model (see mms_epcs.vhd description)
+ g_sim_flash_model : boolean := false;
+ -- Base IP address used by unb_osy: 10.99.xx.yy
+ g_base_ip : std_logic_vector(16 - 1 downto 0) := X"0A63";
g_design_name : string := "UNUSED ";
- g_fw_version : t_unb1_board_fw_version := (0, 0); -- firmware version x.y
+ -- firmware version x.y
+ g_fw_version : t_unb1_board_fw_version := (0, 0);
g_stamp_date : natural := 0;
g_stamp_time : natural := 0;
g_stamp_svn : integer := 0;
g_design_note : string := "UNUSED";
- g_mm_clk_freq : natural := c_unb1_board_mm_clk_freq_125M; -- default use same MM clock as for TSE clock
+ -- default use same MM clock as for TSE clock
+ g_mm_clk_freq : natural := c_unb1_board_mm_clk_freq_125M;
g_xo_clk_use_pll : boolean := false;
- g_dp_clk_use_xo_pll : boolean := false; -- Use the 200MHz XO PLL output (no external CLK)
+ -- Use the 200MHz XO PLL output (no external CLK)
+ g_dp_clk_use_xo_pll : boolean := false;
----------------------------------------------------------------------------
-- External CLK
@@ -97,9 +103,12 @@ entity ctrl_unb1_board is
-- STRING := "4688" = 3750+ 938 = 337.5
-- STRING := "4844" = 3750+1094 = 348.75
-- STRING := "5000" = 3750+1250 = 360
- g_dp_clk_phase : string := "0"; -- phase offset for PLL c0, typically any phase is fine, do not use 225 +-30 degrees because there the PPS edge occurs
- g_dp_phs_clk_vec_w : natural := 0; -- >= 0 and <= 6, nof extra PLL output clocks dp_phs_clk_vec[5:0] = [c6, c5, c4, c3, c2, c1]
- g_dp_phs_clk_divide_by : natural := 32; -- divided by factor for dp_phs_clk_vec[5:0]
+ -- phase offset for PLL c0, typically any phase is fine, do not use 225 +-30 degrees because there the PPS edge occurs
+ g_dp_clk_phase : string := "0";
+ -- >= 0 and <= 6, nof extra PLL output clocks dp_phs_clk_vec[5:0] = [c6, c5, c4, c3, c2, c1]
+ g_dp_phs_clk_vec_w : natural := 0;
+ -- divided by factor for dp_phs_clk_vec[5:0]
+ g_dp_phs_clk_divide_by : natural := 32;
----------------------------------------------------------------------------
-- PPS delay
@@ -133,8 +142,10 @@ entity ctrl_unb1_board is
-- Auxiliary Interface
----------------------------------------------------------------------------
g_fpga_temp_high : natural := 85;
- g_app_led_red : boolean := false; -- when TRUE use external LED control via app_led_red
- g_app_led_green : boolean := false; -- when TRUE use external LED control via app_led_green
+ -- when TRUE use external LED control via app_led_red
+ g_app_led_red : boolean := false;
+ -- when TRUE use external LED control via app_led_green
+ g_app_led_green : boolean := false;
g_aux : t_c_unb1_board_aux := c_unb1_board_aux;
g_epcs_protect_addr_range : boolean := false
@@ -145,38 +156,51 @@ entity ctrl_unb1_board is
--
-- System
cs_sim : out std_logic;
- xo_clk : out std_logic; -- 25 MHz ETH_clk
+ -- 25 MHz ETH_clk
+ xo_clk : out std_logic;
xo_rst : out std_logic;
xo_rst_n : out std_logic;
- mm_clk : in std_logic := '0'; -- from QSYS
+ -- from QSYS
+ mm_clk : in std_logic := '0';
mm_clk_out : out std_logic;
- mm_locked : in std_logic := '0'; -- from QSYS
+ -- from QSYS
+ mm_locked : in std_logic := '0';
mm_locked_out : out std_logic;
mm_rst : out std_logic;
- epcs_clk : in std_logic := '0'; -- from QSYS
+ -- from QSYS
+ epcs_clk : in std_logic := '0';
epcs_clk_out : out std_logic;
dp_rst : out std_logic;
- dp_clk : out std_logic; -- 200 MHz from CLK system clock
- dp_phs_clk_vec : out std_logic_vector(g_dp_phs_clk_vec_w - 1 downto 0); -- divided and phase shifted from 200 MHz CLK system clock when a PLL is used
- dp_pps : out std_logic; -- PPS in dp_clk domain
- dp_rst_in : in std_logic; -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
- dp_clk_in : in std_logic; -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
+ -- 200 MHz from CLK system clock
+ dp_clk : out std_logic;
+ -- divided and phase shifted from 200 MHz CLK system clock when a PLL is used
+ dp_phs_clk_vec : out std_logic_vector(g_dp_phs_clk_vec_w - 1 downto 0);
+ -- PPS in dp_clk domain
+ dp_pps : out std_logic;
+ -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
+ dp_rst_in : in std_logic;
+ -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
+ dp_clk_in : in std_logic;
cal_rec_clk : out std_logic;
- this_chip_id : out std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0); -- [2:0], so range 0-3 for FN and range 4-7 for BN
- this_bck_id : out std_logic_vector(c_unb1_board_nof_uniboard_w - 1 downto 0); -- [1:0] used out of ID[7:3] to index boards 3..0 in subrack
+ -- [2:0], so range 0-3 for FN and range 4-7 for BN
+ this_chip_id : out std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0);
+ -- [1:0] used out of ID[7:3] to index boards 3..0 in subrack
+ this_bck_id : out std_logic_vector(c_unb1_board_nof_uniboard_w - 1 downto 0);
app_led_red : in std_logic := '0';
app_led_green : in std_logic := '1';
-- PIOs
- pout_debug_wave : in std_logic_vector(c_word_w - 1 downto 0) := (others => '0'); -- can be removed !!, has no more function
- pout_wdi : in std_logic; -- Toggled by unb_osy; can be overriden by reg_wdi.
+ -- can be removed !!, has no more function
+ pout_debug_wave : in std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
+ -- Toggled by unb_osy; can be overriden by reg_wdi.
+ pout_wdi : in std_logic;
-- Manual WDI override
reg_wdi_mosi : in t_mem_mosi := c_mem_mosi_rst;
@@ -225,12 +249,16 @@ entity ctrl_unb1_board is
eth1g_tse_clk_out : out std_logic;
eth1g_tse_clk : in std_logic;
eth1g_mm_rst : in std_logic;
- eth1g_tse_mosi : in t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ eth1g_tse_mosi : in t_mem_mosi;
eth1g_tse_miso : out t_mem_miso;
- eth1g_reg_mosi : in t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ eth1g_reg_mosi : in t_mem_mosi;
eth1g_reg_miso : out t_mem_miso;
- eth1g_reg_interrupt : out std_logic; -- Interrupt
- eth1g_ram_mosi : in t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ eth1g_reg_interrupt : out std_logic;
+ -- ETH rx frame and tx frame memory
+ eth1g_ram_mosi : in t_mem_mosi;
eth1g_ram_miso : out t_mem_miso;
-- eth1g UDP streaming ports
@@ -243,11 +271,16 @@ entity ctrl_unb1_board is
-- >>> Ctrl FPGA pins
--
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(g_aux.version_w - 1 downto 0);
@@ -266,9 +299,11 @@ entity ctrl_unb1_board is
end ctrl_unb1_board;
architecture str of ctrl_unb1_board is
- constant c_use_flash : boolean := g_sim = false or g_sim_flash_model = true; -- enable on HW, disable to save simulation time when not used in tb
+ -- enable on HW, disable to save simulation time when not used in tb
+ constant c_use_flash : boolean := g_sim = false or g_sim_flash_model = true;
- constant c_rom_version : natural := 1; -- Only increment when something changes to the register map of rom_system_info.
+ -- Only increment when something changes to the register map of rom_system_info.
+ constant c_rom_version : natural := 1;
-- g_sel=0 for clk200_pll.vhd : used when ADUH is not used so g_dp_phs_clk_vec_w = g_nof_dp_phs_clk = 0
-- g_sel=1 for clk200_pll_p6.vhd : used when ADUH is used so g_dp_phs_clk_vec_w = g_nof_dp_phs_clk > 0
@@ -276,12 +311,18 @@ architecture str of ctrl_unb1_board is
-- Define c_dp_clk*_phase dependend on g_dp_phs_clk_vec_w in equal steps from 0 to 90 degrees of 200 MHz dp_clk.
-- g_dp_clk_vec_w = g_nof_dp_phs_clk = 0 1 2 3 4 5 6
- constant c_dp_clk1_phase : string := sel_n(g_dp_phs_clk_vec_w, "0", "0", "0", "0", "0", "0", "0"); -- degrees phase shifted PLL c1 output clock = dp_phs_clk_vec(0)
- constant c_dp_clk2_phase : string := sel_n(g_dp_phs_clk_vec_w, "0", "0", "625", "313", "313", "156", "156"); -- degrees phase shifted PLL c2 output clock = dp_phs_clk_vec(1)
- constant c_dp_clk3_phase : string := sel_n(g_dp_phs_clk_vec_w, "0", "0", "0", "781", "625", "313", "313"); -- degrees phase shifted PLL c3 output clock = dp_phs_clk_vec(2)
- constant c_dp_clk4_phase : string := sel_n(g_dp_phs_clk_vec_w, "0", "0", "0", "0", "938", "469", "469"); -- degrees phase shifted PLL c4 output clock = dp_phs_clk_vec(3)
- constant c_dp_clk5_phase : string := sel_n(g_dp_phs_clk_vec_w, "0", "0", "0", "0", "0", "625", "625"); -- degrees phase shifted PLL c5 output clock = dp_phs_clk_vec(4)
- constant c_dp_clk6_phase : string := sel_n(g_dp_phs_clk_vec_w, "0", "0", "0", "0", "0", "0", "938"); -- degrees phase shifted PLL c6 output clock = dp_phs_clk_vec(5)
+ -- degrees phase shifted PLL c1 output clock = dp_phs_clk_vec(0)
+ constant c_dp_clk1_phase : string := sel_n(g_dp_phs_clk_vec_w, "0", "0", "0", "0", "0", "0", "0");
+ -- degrees phase shifted PLL c2 output clock = dp_phs_clk_vec(1)
+ constant c_dp_clk2_phase : string := sel_n(g_dp_phs_clk_vec_w, "0", "0", "625", "313", "313", "156", "156");
+ -- degrees phase shifted PLL c3 output clock = dp_phs_clk_vec(2)
+ constant c_dp_clk3_phase : string := sel_n(g_dp_phs_clk_vec_w, "0", "0", "0", "781", "625", "313", "313");
+ -- degrees phase shifted PLL c4 output clock = dp_phs_clk_vec(3)
+ constant c_dp_clk4_phase : string := sel_n(g_dp_phs_clk_vec_w, "0", "0", "0", "0", "938", "469", "469");
+ -- degrees phase shifted PLL c5 output clock = dp_phs_clk_vec(4)
+ constant c_dp_clk5_phase : string := sel_n(g_dp_phs_clk_vec_w, "0", "0", "0", "0", "0", "625", "625");
+ -- degrees phase shifted PLL c6 output clock = dp_phs_clk_vec(5)
+ constant c_dp_clk6_phase : string := sel_n(g_dp_phs_clk_vec_w, "0", "0", "0", "0", "0", "0", "938");
-- Simulation
signal sim_mm_clk : std_logic := '1';
@@ -353,14 +394,19 @@ begin
INTA <= 'Z';
INTB <= 'Z';
- TESTIO <= (others => 'Z'); -- Leave unused INOUT tri-state
+ -- Leave unused INOUT tri-state
+ TESTIO <= (others => 'Z');
-- Clock and reset
- i_xo_clk <= ETH_CLK; -- use the 25 MHz from the ETH_CLK pin as xo_clk
- ext_clk <= CLK; -- use the external 200 MHz CLK as ext_clk
- ext_pps <= PPS; -- use more special name for PPS pin signal to ease searching for it in editor
+ -- use the 25 MHz from the ETH_CLK pin as xo_clk
+ i_xo_clk <= ETH_CLK;
+ -- use the external 200 MHz CLK as ext_clk
+ ext_clk <= CLK;
+ -- use more special name for PPS pin signal to ease searching for it in editor
+ ext_pps <= PPS;
- dp_dis <= i_mm_rst; -- could use software control for this instead
+ -- could use software control for this instead
+ dp_dis <= i_mm_rst;
gen_pll: if g_dp_clk_use_pll = true generate
u_unb1_board_clk200_pll : entity work.unb1_board_clk200_pll
@@ -369,12 +415,18 @@ begin
g_sel => c_dp_clk_pll_sel,
g_clk200_phase_shift => g_dp_clk_phase,
g_clk_vec_w => g_dp_phs_clk_vec_w,
- g_clk1_phase_shift => c_dp_clk1_phase, -- dp_phs_clk_vec(0)
- g_clk2_phase_shift => c_dp_clk2_phase, -- dp_phs_clk_vec(1)
- g_clk3_phase_shift => c_dp_clk3_phase, -- dp_phs_clk_vec(2)
- g_clk4_phase_shift => c_dp_clk4_phase, -- dp_phs_clk_vec(3)
- g_clk5_phase_shift => c_dp_clk5_phase, -- dp_phs_clk_vec(4)
- g_clk6_phase_shift => c_dp_clk6_phase, -- dp_phs_clk_vec(5)
+ -- dp_phs_clk_vec(0)
+ g_clk1_phase_shift => c_dp_clk1_phase,
+ -- dp_phs_clk_vec(1)
+ g_clk2_phase_shift => c_dp_clk2_phase,
+ -- dp_phs_clk_vec(2)
+ g_clk3_phase_shift => c_dp_clk3_phase,
+ -- dp_phs_clk_vec(3)
+ g_clk4_phase_shift => c_dp_clk4_phase,
+ -- dp_phs_clk_vec(4)
+ g_clk5_phase_shift => c_dp_clk5_phase,
+ -- dp_phs_clk_vec(5)
+ g_clk6_phase_shift => c_dp_clk6_phase,
g_clk1_divide_by => g_dp_phs_clk_divide_by,
g_clk2_divide_by => g_dp_phs_clk_divide_by,
g_clk3_divide_by => g_dp_phs_clk_divide_by,
@@ -385,9 +437,11 @@ begin
port map (
arst => dp_dis,
clk200 => ext_clk,
- st_clk200 => dp_clk, -- = c0
+ -- = c0
+ st_clk200 => dp_clk,
st_rst200 => dp_rst,
- st_clk_vec => dp_phs_clk_vec -- PLL c6-c1
+ -- PLL c6-c1
+ st_clk_vec => dp_phs_clk_vec
);
end generate;
@@ -435,7 +489,8 @@ begin
u_unb1_board_node_ctrl : entity work.unb1_board_node_ctrl
generic map (
- g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us => g_mm_clk_freq / (10**6)
)
port map (
xo_clk => i_xo_clk,
@@ -448,10 +503,12 @@ begin
st_clk => node_ctrl_dp_clk_in,
st_rst => node_ctrl_dp_rst_out,
wdi_in => pout_wdi,
- wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ wdi_out => mm_wdi,
pulse_us => OPEN,
pulse_ms => mm_pulse_ms,
- pulse_s => mm_pulse_s -- could be used to toggle a LED
+ -- could be used to toggle a LED
+ pulse_s => mm_pulse_s
);
-- System info
@@ -552,7 +609,8 @@ begin
-- Every design instantiates an mms_remu instance + MM status & control ports.
-- So there is full control over the memory mapped registers to set start address of the flash
-- and reconfigure from that address.
- gen_mms_remu : if c_use_flash = true generate -- enable on HW, disable to save simulation time when not used in tb
+ -- enable on HW, disable to save simulation time when not used in tb
+ gen_mms_remu : if c_use_flash = true generate
u_mms_remu : entity remu_lib.mms_remu
port map (
mm_rst => i_mm_rst,
@@ -572,7 +630,8 @@ begin
-----------------------------------------------------------------------------
-- EPCS
-----------------------------------------------------------------------------
- gen_mms_epcs : if c_use_flash = true generate -- enable on HW, disable to save simulation time when not used in tb
+ -- enable on HW, disable to save simulation time when not used in tb
+ gen_mms_epcs : if c_use_flash = true generate
u_mms_epcs : entity epcs_lib.mms_epcs
generic map (
g_sim_flash_model => g_sim_flash_model,
@@ -621,7 +680,8 @@ begin
mm_clk => mm_clk,
st_rst => dp_rst_in,
st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+ -- with unknown but constant phase to st_clk
+ pps_ext => ext_pps,
-- Memory-mapped clock domain
reg_mosi => reg_ppsh_mosi,
@@ -661,7 +721,8 @@ begin
-- I2C control for UniBoard sensors
------------------------------------------------------------------------------
- mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_ms; -- speed up in simulation
+ -- speed up in simulation
+ mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_ms;
u_mms_unb1_board_sens : entity work.mms_unb1_board_sens
generic map (
@@ -715,16 +776,20 @@ begin
u_mac : entity eth_lib.eth
generic map (
g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ -- Last two bytes set by board/FPGA ID.
+ g_init_ip_address => g_base_ip & X"0000",
g_cross_clock_domain => g_udp_offload,
g_sim => g_sim,
g_sim_level => g_sim_level
)
port map (
-- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => mm_clk, -- use mm_clk direct
- eth_clk => eth1g_tse_clk, -- use the dedicated 125 MHz tse_clock, independent of the mm_clk
+ -- use reset from QSYS
+ mm_rst => eth1g_mm_rst,
+ -- use mm_clk direct
+ mm_clk => mm_clk,
+ -- use the dedicated 125 MHz tse_clock, independent of the mm_clk
+ eth_clk => eth1g_tse_clk,
st_rst => eth1g_st_rst,
st_clk => eth1g_st_clk,
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
index b6754497a9df7b060f29f3a9e7857ec10a2b674a..8013093fd736b07a05cd81b7ca24a1388675d0eb 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
@@ -31,18 +31,23 @@ use common_lib.common_mem_pkg.all;
entity mms_unb1_board_sens is
generic (
g_sim : boolean := false;
- g_clk_freq : natural := 100 * 10**6; -- clk frequency in Hz
+ -- clk frequency in Hz
+ g_clk_freq : natural := 100 * 10**6;
g_temp_high : natural := 85
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
mm_start : in std_logic;
-- Memory-mapped clock domain
- reg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
- reg_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ reg_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ -- actual ranges defined by c_mm_reg
+ reg_miso : out t_mem_miso;
-- i2c bus
scl : inout std_logic := '0';
@@ -54,8 +59,10 @@ entity mms_unb1_board_sens is
end mms_unb1_board_sens;
architecture str of mms_unb1_board_sens is
- constant c_sens_nof_result : natural := 4; -- Should match nof read bytes via I2C in the unb1_board_sens_ctrl SEQUENCE list
- constant c_temp_high_w : natural := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+ -- Should match nof read bytes via I2C in the unb1_board_sens_ctrl SEQUENCE list
+ constant c_sens_nof_result : natural := 4;
+ -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+ constant c_temp_high_w : natural := 7;
signal sens_err : std_logic;
signal sens_data : t_slv_8_arr(0 to c_sens_nof_result - 1);
@@ -77,7 +84,8 @@ begin
sla_out => reg_miso,
-- MM registers
- sens_err => sens_err, -- using same protocol list for both BN3 and all nodes implies that sens_err is only valid for BN3.
+ -- using same protocol list for both BN3 and all nodes implies that sens_err is only valid for BN3.
+ sens_err => sens_err,
sens_data => sens_data,
-- Max temp threshold
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
index 35016608694c658dc4ba2234c6ee3f4855414ee9..775b7fc78d324be432535261ff2d27bec19ec88a 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
@@ -31,12 +31,14 @@ entity mms_unb1_board_system_info is
g_sim : boolean := false;
g_design_name : string;
g_use_phy : t_c_unb1_board_use_phy;
- g_fw_version : t_unb1_board_fw_version := c_unb1_board_fw_version; -- firmware version x.y
+ -- firmware version x.y
+ g_fw_version : t_unb1_board_fw_version := c_unb1_board_fw_version;
g_stamp_date : natural := 0;
g_stamp_time : natural := 0;
g_stamp_svn : integer := 0;
g_design_note : string := "";
- g_aux : t_c_unb1_board_aux := c_unb1_board_aux; -- aux contains the hardware version
+ -- aux contains the hardware version
+ g_aux : t_c_unb1_board_aux := c_unb1_board_aux;
g_rom_version : natural := 1;
g_technology : natural := c_tech_stratixiv
);
@@ -73,12 +75,14 @@ architecture str of mms_unb1_board_system_info is
-- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
- constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
+ -- 2^10 = 1024 addresses * 32 bits = 4 kiB
+ constant c_rom_addr_w : natural := 10;
constant c_mm_rom : t_c_mem := (latency => 1,
adr_w => c_rom_addr_w,
dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ -- = 2**adr_w
+ nof_dat => 2**c_rom_addr_w,
init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
index f7ddc510062859aa916d7f5743157ee601e5a717..2853d3e1e5546ff8e3fa804a3887db71d49f47e0 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
@@ -134,39 +134,51 @@ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity node_unb1_fn_terminal_db is
generic(
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = simulate GX IP, 1 = use fast serial behavioural model
- g_use_bsn_align : boolean := true; -- default TRUE, support FALSE for packet flow debugging purposes (faster synthesis)
+ -- 0 = simulate GX IP, 1 = use fast serial behavioural model
+ g_sim_level : natural := 0;
+ -- default TRUE, support FALSE for packet flow debugging purposes (faster synthesis)
+ g_use_bsn_align : boolean := true;
g_use_data_buf : boolean := true;
-- Application Interface
g_usr_nof_streams : natural := 16;
g_usr_data_w : natural := 32;
g_usr_block_len : natural := 96;
- g_usr_block_per : natural := 256; -- block period = block length + gap length
+ -- block period = block length + gap length
+ g_usr_block_per : natural := 256;
-- Terminals Interface
g_multi_unb : boolean := false;
g_use_mesh : boolean := true;
- g_mesh_nof_serial : natural := 3; -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
+ -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
+ g_mesh_nof_serial : natural := 3;
g_mesh_gx_mbps : natural := 5000;
g_mesh_ena_reorder : boolean := true;
- g_mesh_use_tx : boolean := true; -- can be FALSE for BF, use TRUE to support for bidirectional TR diagnostics
- g_mesh_mon_select : natural := 0; -- 0 = no data monitor buffers via MM, else see unb_terminals_mesh.vhd
+ -- can be FALSE for BF, use TRUE to support for bidirectional TR diagnostics
+ g_mesh_use_tx : boolean := true;
+ -- 0 = no data monitor buffers via MM, else see unb_terminals_mesh.vhd
+ g_mesh_mon_select : natural := 0;
g_mesh_mon_nof_words : natural := 1024;
g_mesh_mon_use_sync : boolean := true;
- g_mesh_sync_timeout : natural := 220 * 10**6; -- >= number dp_clk per sync (choose = can be too tight due to asynchronous mesh link, so then choose somewhat larger)
+ -- >= number dp_clk per sync (choose = can be too tight due to asynchronous mesh link, so then choose somewhat larger)
+ g_mesh_sync_timeout : natural := 220 * 10**6;
-- Auxiliary Interface
g_aux : t_c_unb1_board_aux := c_unb1_board_aux
);
port(
-- System
- chip_id : in std_logic_vector(g_aux.chip_id_w - 1 downto 0); -- [2:0]
+ -- [2:0]
+ chip_id : in std_logic_vector(g_aux.chip_id_w - 1 downto 0);
mm_rst : in std_logic;
- mm_clk : in std_logic; -- 50 MHz from xo_clk PLL in SOPC system
+ -- 50 MHz from xo_clk PLL in SOPC system
+ mm_clk : in std_logic;
dp_rst : in std_logic;
- dp_clk : in std_logic; -- 200 MHz from CLK system clock
+ -- 200 MHz from CLK system clock
+ dp_clk : in std_logic;
dp_pps : in std_logic := '0';
- tr_mesh_clk : in std_logic; -- 156.25 MHz from SB_CLK transceiver clock
- cal_clk : in std_logic; -- 40 MHz from xo_clk PLL in SOPC system
+ -- 156.25 MHz from SB_CLK transceiver clock
+ tr_mesh_clk : in std_logic;
+ -- 40 MHz from xo_clk PLL in SOPC system
+ cal_clk : in std_logic;
-- MM interface
-- . diag_data_buffer
@@ -191,8 +203,10 @@ entity node_unb1_fn_terminal_db is
dp_out_siso_arr : in t_dp_siso_arr(g_usr_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
-- Mesh serial interface (tr_nonbonded)
- tx_serial_2arr : out t_unb1_board_mesh_sl_2arr; -- Tx
- rx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0')) -- Rx support for diagnostics
+ -- Tx
+ tx_serial_2arr : out t_unb1_board_mesh_sl_2arr;
+ -- Rx support for diagnostics
+ rx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0'))
);
end node_unb1_fn_terminal_db;
@@ -200,33 +214,43 @@ architecture str of node_unb1_fn_terminal_db is
-----------------------------------------------------------------------------
-- BSN align
-----------------------------------------------------------------------------
- constant c_bsn_request_pipeline : natural := 2; -- need to use 2 to ease timing closure at 200 MHz
+ -- need to use 2 to ease timing closure at 200 MHz
+ constant c_bsn_request_pipeline : natural := 2;
constant c_bsn_latency : natural := 3;
- constant c_burst_usr_nof_block : natural := g_mesh_nof_serial; -- 3 phy lane blocks t012 per user stream
+ -- 3 phy lane blocks t012 per user stream
+ constant c_burst_usr_nof_block : natural := g_mesh_nof_serial;
constant c_burst_bsn_latency : natural := c_bsn_latency + c_burst_usr_nof_block;
-----------------------------------------------------------------------------
-- Terminals
-----------------------------------------------------------------------------
- constant c_usr_nof_streams_per_bus : natural := g_usr_nof_streams / c_unb1_board_nof_bn; -- 16 / 4 = 4
+ -- 16 / 4 = 4
+ constant c_usr_nof_streams_per_bus : natural := g_usr_nof_streams / c_unb1_board_nof_bn;
-- . tr_nonbonded rx fifo
- constant c_burst_phy_nof_block : natural := c_usr_nof_streams_per_bus; -- burst of 4 usr blocks per t0 per phy lane
- constant c_phy_block_len : natural := g_usr_block_len; -- no data packing so phy frame is about as long as the user frame (expect for few overhead words)
- constant c_phy_rx_fifo_len : natural := c_phy_block_len * 1; -- assume only need to store less than one block in practise
- constant c_phy_rx_fifo_size : natural := ceil_value(c_phy_rx_fifo_len, c_bram_m9k_fifo_depth); -- use tr_nonbonded Rx dual clock FIFO to buffer for dp_distribute
+ -- burst of 4 usr blocks per t0 per phy lane
+ constant c_burst_phy_nof_block : natural := c_usr_nof_streams_per_bus;
+ -- no data packing so phy frame is about as long as the user frame (expect for few overhead words)
+ constant c_phy_block_len : natural := g_usr_block_len;
+ -- assume only need to store less than one block in practise
+ constant c_phy_rx_fifo_len : natural := c_phy_block_len * 1;
+ -- use tr_nonbonded Rx dual clock FIFO to buffer for dp_distribute
+ constant c_phy_rx_fifo_size : natural := ceil_value(c_phy_rx_fifo_len, c_bram_m9k_fifo_depth);
-- . uth_rx timeout_cnt
- constant c_rx_timeout_w : natural := 0; -- ceil_log2(g_usr_block_per);
+ -- ceil_log2(g_usr_block_per);
+ constant c_rx_timeout_w : natural := 0;
-- . uth_terminal_rx output fifo
constant c_rx_output_fifo_len : natural := (c_burst_bsn_latency + 2) * g_usr_block_len;
constant c_rx_output_fifo_size : natural := ceil_value(c_rx_output_fifo_len, c_bram_m9k_fifo_depth);
- constant c_rx_output_fifo_fill : natural := g_usr_block_len; -- keep a full block in the FIFO to ensure that dp_bsn_align gets input without data not valid gaps when the lane rate is slower (as with tr_nonbonded)
+ -- keep a full block in the FIFO to ensure that dp_bsn_align gets input without data not valid gaps when the lane rate is slower (as with tr_nonbonded)
+ constant c_rx_output_fifo_fill : natural := g_usr_block_len;
-- . BSN aligner timeouts
- constant c_sop_timeout : natural := (c_burst_bsn_latency + 1) * g_usr_block_per; -- wait for sop for some block periods
+ -- wait for sop for some block periods
+ constant c_sop_timeout : natural := (c_burst_bsn_latency + 1) * g_usr_block_per;
constant c_xoff_timeout : natural := c_burst_bsn_latency * 2 * g_usr_block_per;
signal rx_usr_siso_2arr : t_unb1_board_mesh_siso_2arr;
@@ -254,7 +278,8 @@ begin
g_sim_level => g_sim_level,
-- System
g_node_type => e_fn,
- g_nof_bus => c_unb1_board_nof_bn, -- 4 to 4 nodes in mesh
+ -- 4 to 4 nodes in mesh
+ g_nof_bus => c_unb1_board_nof_bn,
-- User
g_usr_use_complex => true,
g_usr_data_w => g_usr_data_w,
@@ -266,11 +291,15 @@ begin
g_phy_rx_fifo_size => c_phy_rx_fifo_size,
g_phy_ena_reorder => g_mesh_ena_reorder,
-- Tx
- g_use_tx => g_mesh_use_tx, -- optionally do support diag Tx
- g_tx_input_use_fifo => false, -- no user Tx
+ -- optionally do support diag Tx
+ g_use_tx => g_mesh_use_tx,
+ -- no user Tx
+ g_tx_input_use_fifo => false,
-- Rx
- g_use_rx => true, -- user Rx must be TRUE for DB in FN,
- g_rx_output_use_fifo => true, -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ -- user Rx must be TRUE for DB in FN,
+ g_use_rx => true,
+ -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_use_fifo => true,
g_rx_output_fifo_size => c_rx_output_fifo_size,
g_rx_output_fifo_fill => c_rx_output_fifo_fill,
g_rx_timeout_w => c_rx_timeout_w,
@@ -292,12 +321,15 @@ begin
-- User interface (4 nodes)(4 input streams)
rx_usr_siso_2arr => rx_usr_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- Rx (user Tx from FN to BN is unused)
+ -- Rx (user Tx from FN to BN is unused)
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr,
-- Mesh interface level (4 nodes)(4 lanes)
-- . Serial (tr_nonbonded)
- tx_serial_2arr => tx_serial_2arr, -- Tx
- rx_serial_2arr => rx_serial_2arr, -- Rx
+ -- Tx
+ tx_serial_2arr => tx_serial_2arr,
+ -- Rx
+ rx_serial_2arr => rx_serial_2arr,
-- MM Control
-- . tr_nonbonded
@@ -363,13 +395,16 @@ begin
src_in_arr => dp_out_siso_arr,
src_out_arr => db_in_sosi_arr,
-- MM
- in_en_evt => '0', -- pulse '1' indicates that the in_en_arr user input enables have been updated
- in_en_arr => (others => '1') -- default all user inputs are enabled
+ -- pulse '1' indicates that the in_en_arr user input enables have been updated
+ in_en_evt => '0',
+ -- default all user inputs are enabled
+ in_en_arr => (others => '1')
);
u_bsn_monitor_align : entity dp_lib.mms_dp_bsn_monitor
generic map (
- g_nof_streams => 1, -- All streams are synchronous. Only monitor stream(0).
+ -- All streams are synchronous. Only monitor stream(0).
+ g_nof_streams => 1,
g_cross_clock_domain => true,
g_sync_timeout => g_mesh_sync_timeout,
g_bsn_w => c_dp_stream_bsn_w,
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
index 8f32540b83c6c94ebffbfd2b5b331a084ff6851e..2b5078e2bd74047f181dcf329d812fef973ee2b0 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
@@ -97,67 +97,91 @@ begin
case TO_UINT(bck_id) is
when 0 =>
-- UniBoard 0 connects to UniBoards 3,2,1 via phy busses 0,2,1
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
+ -- to unb 1
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1);
tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
+ -- from unb 1
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1);
rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
+ -- to unb 2
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2);
tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
+ -- from unb 2
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2);
rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
+ -- to unb 3
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3);
tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
+ -- from unb 3
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0);
rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
when 1 =>
-- UniBoard 1 connects to UniBoards 3,2,0 via phy busses 0,1,2
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
+ -- to unb 0
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0);
tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
+ -- from unb 0
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2);
rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(2); -- to unb 2
+ -- to unb 2
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(2);
tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1); -- from unb 2
+ -- from unb 2
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1);
rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(2);
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
+ -- to unb 3
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3);
tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
+ -- from unb 3
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0);
rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
when 2 =>
-- UniBoard 2 connects to UniBoards 3,1,0 via phy busses 1,0,2
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
+ -- to unb 0
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0);
tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
+ -- from unb 0
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2);
rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(1); -- to unb 1
+ -- to unb 1
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(1);
tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(0); -- from unb 1
+ -- from unb 1
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(0);
rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(1);
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(3); -- to unb 3
+ -- to unb 3
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(3);
tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(1); -- from unb 3
+ -- from unb 3
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(1);
rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(3);
when 3 =>
-- UniBoard 3 connects to UniBoards 2,1,0 via phy busses 2,1,0
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(0); -- to unb 0
+ -- to unb 0
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(0);
tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(0); -- from unb 0
+ -- from unb 0
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(0);
rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(0);
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
+ -- to unb 1
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1);
tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
+ -- from unb 1
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1);
rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
+ -- to unb 2
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2);
tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
+ -- from unb 2
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2);
rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
when others => null;
end case;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
index 1ee7f136478cfb001d46ccc8237c79f1ebe933a4..9423e06c3184aebbf4cf51a69cfa766a49c71776 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
@@ -37,25 +37,34 @@ use uth_lib.uth_pkg.all;
entity unb1_board_back_uth_terminals_bidir is
generic (
-- User
- g_usr_nof_streams : natural := 4; -- number of user streams per bus
- g_usr_use_complex : boolean := false; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ -- number of user streams per bus
+ g_usr_nof_streams : natural := 4;
+ -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ g_usr_use_complex : boolean := false;
g_usr_data_w : natural := 32;
g_usr_frame_len : natural := 20;
-- DP/UTH packet
- g_packet_data_w : natural := 32; -- packet data width for DP packet and for UTH packet, must be >= g_usr_data_w
+ -- packet data width for DP packet and for UTH packet, must be >= g_usr_data_w
+ g_packet_data_w : natural := 32;
-- Phy
- g_phy_nof_serial : natural := 4; -- up to 4 serial lanes per bus
+ -- up to 4 serial lanes per bus
+ g_phy_nof_serial : natural := 4;
-- Tx
g_use_tx : boolean := true;
- g_tx_input_use_fifo : boolean := true; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
- g_tx_input_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ g_tx_input_use_fifo : boolean := true;
+ -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ g_tx_input_fifo_size : natural := c_bram_m9k_fifo_depth;
g_tx_input_fifo_fill : natural := 0;
-- Rx
g_use_rx : boolean := true;
- g_rx_output_use_fifo : boolean := true; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_output_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_use_fifo : boolean := true;
+ -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ g_rx_output_fifo_size : natural := c_bram_m9k_fifo_depth;
g_rx_output_fifo_fill : natural := 0;
- g_rx_timeout_w : natural := 0 -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ g_rx_timeout_w : natural := 0
);
port (
dp_rst : in std_logic;
@@ -78,8 +87,10 @@ entity unb1_board_back_uth_terminals_bidir is
end unb1_board_back_uth_terminals_bidir;
architecture str of unb1_board_back_uth_terminals_bidir is
- constant c_tx_mux_mode : natural := 1; -- can use 0 for non-blocking tx mux in dp_distribute or use 1 to preserve input order for tx
- constant c_rx_mux_mode : natural := 0; -- must use 0 for non-blocking rx mux in dp_distribute (can not use 1 to preserve input order for rx, because some rx frames may go lost)
+ -- can use 0 for non-blocking tx mux in dp_distribute or use 1 to preserve input order for tx
+ constant c_tx_mux_mode : natural := 1;
+ -- must use 0 for non-blocking rx mux in dp_distribute (can not use 1 to preserve input order for rx, because some rx frames may go lost)
+ constant c_rx_mux_mode : natural := 0;
begin
gen_bus : for I in 0 to c_unb1_board_tr_back.nof_bus - 1 generate
u_uth_terminal_bidir : entity uth_lib.uth_terminal_bidir
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
index 54d62c3a5def1be5cf5d2b3b32e667346ce45695..fa989aae5968a5ffe4d573a5941d1fb74cf10fd3 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
@@ -94,44 +94,66 @@ entity unb1_board_clk200_pll is
generic (
g_technology : natural := c_tech_stratixiv;
g_sel : natural := 0;
- g_operation_mode : string := "NORMAL"; -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
+ -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
+ g_operation_mode : string := "NORMAL";
-- g_sel=0 for clk200_pll.vhd
- g_clk200_phase_shift : string := "0"; -- default use 0 degrees, see clk200_pll.vhd for other phase values
- g_clk200p_phase_shift : string := "0"; -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ g_clk200_phase_shift : string := "0";
+ -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ g_clk200p_phase_shift : string := "0";
-- g_sel=1 for clk200_pll_p6.vhd
- g_clk0_phase_shift : string := "0"; -- = 000 = st_clk_vec[0] = st_clk200
- g_clk_vec_w : natural := 6; -- clk200_pll_p6.vhd and supports up to 6 extra output clocks, e.g. with phase 0 to 90 in steps of 11.25 degrees, and with same or lower frequency
- g_clk1_phase_shift : string := "0"; -- = 000 = st_clk_vec[1] = st_clk200p
- g_clk2_phase_shift : string := "156"; -- = 011.25 = st_clk_vec[2]
- g_clk3_phase_shift : string := "313"; -- = 022.5 = st_clk_vec[3]
- g_clk4_phase_shift : string := "469"; -- = 033.75 = st_clk_vec[4]
- g_clk5_phase_shift : string := "625"; -- = 045 = st_clk_vec[5]
+ -- = 000 = st_clk_vec[0] = st_clk200
+ g_clk0_phase_shift : string := "0";
+ -- clk200_pll_p6.vhd and supports up to 6 extra output clocks, e.g. with phase 0 to 90 in steps of 11.25 degrees, and with same or lower frequency
+ g_clk_vec_w : natural := 6;
+ -- = 000 = st_clk_vec[1] = st_clk200p
+ g_clk1_phase_shift : string := "0";
+ -- = 011.25 = st_clk_vec[2]
+ g_clk2_phase_shift : string := "156";
+ -- = 022.5 = st_clk_vec[3]
+ g_clk3_phase_shift : string := "313";
+ -- = 033.75 = st_clk_vec[4]
+ g_clk4_phase_shift : string := "469";
+ -- = 045 = st_clk_vec[5]
+ g_clk5_phase_shift : string := "625";
-- "781"; -- = 056.25
- g_clk6_phase_shift : string := "938"; -- = 067.5 = st_clk_vec[6]
+ -- = 067.5 = st_clk_vec[6]
+ g_clk6_phase_shift : string := "938";
-- "1094"; -- = 078.75
- g_clk1_divide_by : natural := 32; -- = clk 200/32 MHz
- g_clk2_divide_by : natural := 32; -- = clk 200/32 MHz
- g_clk3_divide_by : natural := 32; -- = clk 200/32 MHz
- g_clk4_divide_by : natural := 32; -- = clk 200/32 MHz
- g_clk5_divide_by : natural := 32; -- = clk 200/32 MHz
- g_clk6_divide_by : natural := 32 -- = clk 200/32 MHz
+ -- = clk 200/32 MHz
+ g_clk1_divide_by : natural := 32;
+ -- = clk 200/32 MHz
+ g_clk2_divide_by : natural := 32;
+ -- = clk 200/32 MHz
+ g_clk3_divide_by : natural := 32;
+ -- = clk 200/32 MHz
+ g_clk4_divide_by : natural := 32;
+ -- = clk 200/32 MHz
+ g_clk5_divide_by : natural := 32;
+ -- = clk 200/32 MHz
+ g_clk6_divide_by : natural := 32
);
port (
-- It depends on g_sel which outputs are actually available
-- . common
arst : in std_logic := '0';
- clk200 : in std_logic := '0'; -- connect to UniBoard CLK pin
- st_clk200 : out std_logic; -- PLL c0 = g_clk200_phase_shift degrees phase offset to input clk200
+ -- connect to UniBoard CLK pin
+ clk200 : in std_logic := '0';
+ -- PLL c0 = g_clk200_phase_shift degrees phase offset to input clk200
+ st_clk200 : out std_logic;
st_rst200 : out std_logic;
-- . g_sel=0
- st_clk200p : out std_logic; -- PLL c1 = g_clk200p_phase_shift degrees phase offset to input clk200 (see clk200_pll.vhd from MegaWizard)
+ -- PLL c1 = g_clk200p_phase_shift degrees phase offset to input clk200 (see clk200_pll.vhd from MegaWizard)
+ st_clk200p : out std_logic;
st_rst200p : out std_logic;
- st_clk400 : out std_logic; -- PLL c2 = 0 degrees phase offset to input clk200
+ -- PLL c2 = 0 degrees phase offset to input clk200
+ st_clk400 : out std_logic;
st_rst400 : out std_logic;
-- . g_sel=1
- st_clk_vec : out std_logic_vector(g_clk_vec_w - 1 downto 0) -- PLL c6-c1
+ -- PLL c6-c1
+ st_clk_vec : out std_logic_vector(g_clk_vec_w - 1 downto 0)
);
end unb1_board_clk200_pll;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
index f5684a4c5c866e8f11968beb953ac30f187a589c..f3e029d11412508ef3f2ec1c605f14f179f1f30e 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
@@ -39,13 +39,19 @@ entity unb1_board_clk25_pll is
);
port (
arst : in std_logic := '0';
- clk25 : in std_logic := '0'; -- connect to UniBoard ETH_clk pin (25 MHz)
+ -- connect to UniBoard ETH_clk pin (25 MHz)
+ clk25 : in std_logic := '0';
- c0_clk20 : out std_logic; -- PLL c0
- c1_clk40 : out std_logic; -- PLL c1
- c2_clk50 : out std_logic; -- PLL c2
- c3_clk125 : out std_logic; -- PLL c3
- c4_clk200 : out std_logic; -- PLL c4 FIXME only StratixIV
+ -- PLL c0
+ c0_clk20 : out std_logic;
+ -- PLL c1
+ c1_clk40 : out std_logic;
+ -- PLL c2
+ c2_clk50 : out std_logic;
+ -- PLL c3
+ c3_clk125 : out std_logic;
+ -- PLL c4 FIXME only StratixIV
+ c4_clk200 : out std_logic;
pll_locked : out std_logic
);
end unb1_board_clk25_pll;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
index 4498f945ae69c11320ddfe1a96de83c9ed05cb35..84bcdea672e1e80f03de3a863a9c9686d0907451 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
@@ -33,20 +33,27 @@ use common_lib.common_pkg.all;
entity unb1_board_clk_rst is
port (
-- Reference clock and reset to SOPC system PLL
- xo_clk : in std_logic; -- reference XO clock (e.g. 25 MHz also use by PLL in SOPC)
- xo_rst_n : out std_logic; -- NOT xo_rst (e.g. to reset the SOPC with NIOS2 uP)
+ -- reference XO clock (e.g. 25 MHz also use by PLL in SOPC)
+ xo_clk : in std_logic;
+ -- NOT xo_rst (e.g. to reset the SOPC with NIOS2 uP)
+ xo_rst_n : out std_logic;
-- System clock and locked from SOPC system PLL
- sys_clk : in std_logic; -- system clock derived from the reference XO clock (e.g. 125 MHz by a PLL from SOPC with NIOS2 uP)
- sys_locked : in std_logic; -- system clock PLL locked
- sys_rst : out std_logic -- system reset released some cycles after the system clock PLL has in locked
+ -- system clock derived from the reference XO clock (e.g. 125 MHz by a PLL from SOPC with NIOS2 uP)
+ sys_clk : in std_logic;
+ -- system clock PLL locked
+ sys_locked : in std_logic;
+ -- system reset released some cycles after the system clock PLL has in locked
+ sys_rst : out std_logic
);
end unb1_board_clk_rst;
architecture str of unb1_board_clk_rst is
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
-- XO clock domain
- signal xo_rst : std_logic; -- initial reset released after some XO clock cycles
+ -- initial reset released after some XO clock cycles
+ signal xo_rst : std_logic;
-- SYS clock domain
signal sys_locked_n : std_logic;
@@ -56,11 +63,13 @@ begin
u_common_areset_xo : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => xo_clk,
out_rst => xo_rst
);
@@ -70,11 +79,13 @@ begin
u_common_areset_sys : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ -- release reset after some clock cycles when the PLL has locked
+ in_rst => sys_locked_n,
clk => sys_clk,
out_rst => sys_rst
);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
index f16b3b3714b61fd33155b0e9e20b47225c1a6799..251964080426206cf31a79b75b71136ecc60a625 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
@@ -25,7 +25,8 @@ use work.unb1_board_pkg.all;
entity unb1_board_mesh_io is
generic (
- g_bus_w : natural := 3 -- use 4 to include the CMU transceives at port (3) else use 3 to only use the HW transceivers on port (2:0)
+ -- use 4 to include the CMU transceives at port (3) else use 3 to only use the HW transceivers on port (2:0)
+ g_bus_w : natural := 3
);
port (
tx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0'));
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
index 28c28e6f37d7c579f208370edd249925e777aef4..e644f4a88a7ea131dee3ea3d069cd79a65f02415 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
@@ -141,24 +141,30 @@ use work.unb1_board_pkg.all;
entity unb1_board_mesh_reorder_bidir is
generic (
- g_node_type : t_e_unb1_board_node := e_any; -- or e_fn, or e_bn
+ -- or e_fn, or e_bn
+ g_node_type : t_e_unb1_board_node := e_any;
g_reorder : boolean := true
);
port (
- chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0); -- [2:0]
+ -- [2:0]
+ chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
-- Transmit clock domain --> output data to node across the mesh
tx_clk : in std_logic;
- tx_usr_sosi_2arr : in t_unb1_board_mesh_sosi_2arr; -- user side
+ -- user side
+ tx_usr_sosi_2arr : in t_unb1_board_mesh_sosi_2arr;
tx_usr_siso_2arr : out t_unb1_board_mesh_siso_2arr;
- tx_phy_sosi_2arr : out t_unb1_board_mesh_sosi_2arr; -- phy side
+ -- phy side
+ tx_phy_sosi_2arr : out t_unb1_board_mesh_sosi_2arr;
tx_phy_siso_2arr : in t_unb1_board_mesh_siso_2arr := c_unb1_board_mesh_siso_2arr_rst;
-- Receive clock domain --> input data from node across the mesh
rx_clk : in std_logic;
- rx_phy_sosi_2arr : in t_unb1_board_mesh_sosi_2arr; -- phy side
+ -- phy side
+ rx_phy_sosi_2arr : in t_unb1_board_mesh_sosi_2arr;
rx_phy_siso_2arr : out t_unb1_board_mesh_siso_2arr;
- rx_usr_sosi_2arr : out t_unb1_board_mesh_sosi_2arr; -- user side
+ -- user side
+ rx_usr_sosi_2arr : out t_unb1_board_mesh_sosi_2arr;
rx_usr_siso_2arr : in t_unb1_board_mesh_siso_2arr := c_unb1_board_mesh_siso_2arr_rst
);
end unb1_board_mesh_reorder_bidir;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
index 71b2ca81148443b5ee2188af3661006c96fc78a6..a8a1e50eedf35c5c1fb162e87f0e5e59f1d268b8 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
@@ -43,9 +43,11 @@ entity unb1_board_mesh_reorder_rx is
g_reorder : boolean := true
);
port (
- chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0); -- [2:0]
+ -- [2:0]
+ chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
clk : in std_logic;
- rx_phy_sosi_2arr : in t_unb1_board_mesh_sosi_2arr; -- _2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
+ -- _2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
+ rx_phy_sosi_2arr : in t_unb1_board_mesh_sosi_2arr;
tx_phy_siso_2arr : in t_unb1_board_mesh_siso_2arr := c_unb1_board_mesh_siso_2arr_rst;
rx_usr_sosi_2arr : out t_unb1_board_mesh_sosi_2arr;
tx_usr_siso_2arr : out t_unb1_board_mesh_siso_2arr
@@ -66,7 +68,8 @@ begin
if g_reorder = true then
-- make the reordering to compensate for the reordering of the UniBoard mesh
case TO_UINT(chip_id_i) is
- when 0 => -- this is FN0, connect phy bus 0,1,2,3 to usr bus 0,3,2,1
+ -- this is FN0, connect phy bus 0,1,2,3 to usr bus 0,3,2,1
+ when 0 =>
-- sosi
rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(1);
rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2);
@@ -75,15 +78,18 @@ begin
tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(1);
tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(3);
- when 1 => -- this is FN1, connect phy bus 0,1,2,3 to usr bus 0,1,3,2
+ -- this is FN1, connect phy bus 0,1,2,3 to usr bus 0,1,3,2
+ when 1 =>
-- sosi
rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(2);
rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(3);
-- siso
tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(2);
tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(3);
- when 2 => -- this is FN2, connect phy bus 0,1,2,3 to usr bus 0,1,2,3
- when 3 => -- this is FN3, connect phy bus 0,1,2,3 to usr bus 1,0,2,3
+ -- this is FN2, connect phy bus 0,1,2,3 to usr bus 0,1,2,3
+ when 2 =>
+ -- this is FN3, connect phy bus 0,1,2,3 to usr bus 1,0,2,3
+ when 3 =>
-- sosi
rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(0);
rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(1);
@@ -91,7 +97,8 @@ begin
tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(0);
tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(1);
when 4 |
- 5 => -- this is BN0
+ -- this is BN0
+ 5 =>
-- or BN1, connect phy bus 0,1,2,3 to usr bus 3,2,1,0
-- sosi
rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0);
@@ -103,7 +110,8 @@ begin
tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(1);
tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(2);
tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(3);
- when 6 => -- this is BN2, connect phy bus 0,1,2,3 to usr bus 3,2,0,1
+ -- this is BN2, connect phy bus 0,1,2,3 to usr bus 3,2,0,1
+ when 6 =>
-- sosi
rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0);
rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1);
@@ -114,7 +122,8 @@ begin
tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(1);
tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(3);
- when 7 => -- this is BN3, connect phy bus 0,1,2,3 to usr bus 3,0,2,1
+ -- this is BN3, connect phy bus 0,1,2,3 to usr bus 3,0,2,1
+ when 7 =>
-- sosi
rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0);
rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(1);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
index 7fe1309d411ffe2e996a2656772676fc7634a219..9a2c7f9e63e95c645946bdf140bba03002335c16 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
@@ -43,9 +43,11 @@ entity unb1_board_mesh_reorder_tx is
g_reorder : boolean := true
);
port (
- chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0); -- [2:0]
+ -- [2:0]
+ chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
clk : in std_logic;
- tx_usr_sosi_2arr : in t_unb1_board_mesh_sosi_2arr; -- _2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
+ -- _2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
+ tx_usr_sosi_2arr : in t_unb1_board_mesh_sosi_2arr;
rx_usr_siso_2arr : in t_unb1_board_mesh_siso_2arr := c_unb1_board_mesh_siso_2arr_rst;
tx_phy_sosi_2arr : out t_unb1_board_mesh_sosi_2arr;
rx_phy_siso_2arr : out t_unb1_board_mesh_siso_2arr
@@ -84,7 +86,8 @@ begin
if g_reorder = true then
-- make the reordering to compensate for the reordering of the UniBoard mesh
case TO_UINT(chip_id_i) is
- when 0 => -- this is FN0, connect usr bus 0,1,2,3 to phy bus 0,3,2,1
+ -- this is FN0, connect usr bus 0,1,2,3 to phy bus 0,3,2,1
+ when 0 =>
-- sosi
tx_phy_sosi_2arr(3) <= tx_usr_sosi_2arr(1);
tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2);
@@ -93,15 +96,18 @@ begin
rx_phy_siso_2arr(3) <= rx_usr_siso_2arr(1);
rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(3);
- when 1 => -- this is FN1, connect usr bus 0,1,2,3 to phy bus 0,1,3,2
+ -- this is FN1, connect usr bus 0,1,2,3 to phy bus 0,1,3,2
+ when 1 =>
-- sosi
tx_phy_sosi_2arr(3) <= tx_usr_sosi_2arr(2);
tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(3);
-- siso
rx_phy_siso_2arr(3) <= rx_usr_siso_2arr(2);
rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(3);
- when 2 => -- this is FN2, connect usr bus 0,1,2,3 to phy bus 0,1,2,3
- when 3 => -- this is FN3, connect usr bus 0,1,2,3 to phy bus 1,0,2,3
+ -- this is FN2, connect usr bus 0,1,2,3 to phy bus 0,1,2,3
+ when 2 =>
+ -- this is FN3, connect usr bus 0,1,2,3 to phy bus 1,0,2,3
+ when 3 =>
-- sosi
tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(0);
tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(1);
@@ -109,7 +115,8 @@ begin
rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(0);
rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(1);
when 4 |
- 5 => -- this is BN0
+ -- this is BN0
+ 5 =>
-- or BN1, connect usr bus 0,1,2,3 to phy bus 3,2,1,0
-- sosi
tx_phy_sosi_2arr(3) <= tx_usr_sosi_2arr(0);
@@ -121,7 +128,8 @@ begin
rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(1);
rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(2);
rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
- when 6 => -- this is BN2, connect usr bus 0,1,2,3 to phy bus 2,3,1,0
+ -- this is BN2, connect usr bus 0,1,2,3 to phy bus 2,3,1,0
+ when 6 =>
-- sosi
tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0);
tx_phy_sosi_2arr(3) <= tx_usr_sosi_2arr(1);
@@ -132,7 +140,8 @@ begin
rx_phy_siso_2arr(3) <= rx_usr_siso_2arr(1);
rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(2);
rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
- when 7 => -- this is BN3, connect usr bus 0,1,2,3 to phy bus 1,3,2,0
+ -- this is BN3, connect usr bus 0,1,2,3 to phy bus 1,3,2,0
+ when 7 =>
-- sosi
tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(0);
tx_phy_sosi_2arr(3) <= tx_usr_sosi_2arr(1);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
index a4259a7adea7c7e99a672f4afb6a6cf2127f1b6b..738da17e23372feaea11ad6002e7cf98ab697c2e 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
@@ -37,28 +37,39 @@ use uth_lib.uth_pkg.all;
entity unb1_board_mesh_uth_terminals_bidir is
generic (
-- User
- g_usr_nof_streams : natural := 4; -- number of user streams per bus
- g_usr_use_complex : boolean := false; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ -- number of user streams per bus
+ g_usr_nof_streams : natural := 4;
+ -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ g_usr_use_complex : boolean := false;
g_usr_data_w : natural := 32;
g_usr_frame_len : natural := 20;
-- DP/UTH packet
- g_packet_data_w : natural := 32; -- packet data width for DP packet and for UTH packet, must be >= g_usr_data_w
+ -- packet data width for DP packet and for UTH packet, must be >= g_usr_data_w
+ g_packet_data_w : natural := 32;
-- Phy
- g_phy_nof_serial : natural := 4; -- up to 4 serial lanes per bus
+ -- up to 4 serial lanes per bus
+ g_phy_nof_serial : natural := 4;
-- Tx
g_use_tx : boolean := true;
- g_tx_input_use_fifo : boolean := true; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
- g_tx_input_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ g_tx_input_use_fifo : boolean := true;
+ -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ g_tx_input_fifo_size : natural := c_bram_m9k_fifo_depth;
g_tx_input_fifo_fill : natural := 0;
-- Rx
g_use_rx : boolean := true;
- g_rx_output_use_fifo : boolean := true; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_output_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_use_fifo : boolean := true;
+ -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ g_rx_output_fifo_size : natural := c_bram_m9k_fifo_depth;
g_rx_output_fifo_fill : natural := 0;
- g_rx_timeout_w : natural := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ g_rx_timeout_w : natural := 0;
-- UTH
- g_uth_len_max : natural := 255; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
- g_uth_typ_ofs : natural := 256 -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ g_uth_len_max : natural := 255;
+ -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ g_uth_typ_ofs : natural := 256
);
port (
dp_rst : in std_logic;
@@ -85,8 +96,10 @@ entity unb1_board_mesh_uth_terminals_bidir is
end unb1_board_mesh_uth_terminals_bidir;
architecture str of unb1_board_mesh_uth_terminals_bidir is
- constant c_tx_mux_mode : natural := 0; -- can use 0 for non-blocking tx mux in dp_distribute or use 1 to preserve input order for tx
- constant c_rx_mux_mode : natural := 0; -- must use 0 for non-blocking rx mux in dp_distribute (can not use 1 to preserve input order for rx, because some rx frames may go lost)
+ -- can use 0 for non-blocking tx mux in dp_distribute or use 1 to preserve input order for tx
+ constant c_tx_mux_mode : natural := 0;
+ -- must use 0 for non-blocking rx mux in dp_distribute (can not use 1 to preserve input order for rx, because some rx frames may go lost)
+ constant c_rx_mux_mode : natural := 0;
begin
gen_uth_terminal_bidir : for I in 0 to c_unb1_board_tr_mesh.nof_bus - 1 generate
u_uth_terminal_bidir : entity uth_lib.uth_terminal_bidir
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
index d5644e7de883ffe3e3e1cd1b9fe0caa76f9fd6ee..75b40b12ef4aaa55e4bb7cce77ccecb86296e85e 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
@@ -32,31 +32,50 @@ use common_lib.common_pkg.all;
entity unb1_board_node_ctrl is
generic (
- g_pulse_us : natural := 125; -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- g_pulse_ms : natural := 1000; -- nof pulse_us pulses to get ms period (fixed, use less to speed up simulation)
- g_pulse_s : natural := 1000; -- nof pulse_ms pulses to get s period (fixed, use less to speed up simulation)
- g_wdi_extend_w : natural := 14 -- extend wdi by about 2**(14-1)= 8 s
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us : natural := 125;
+ -- nof pulse_us pulses to get ms period (fixed, use less to speed up simulation)
+ g_pulse_ms : natural := 1000;
+ -- nof pulse_ms pulses to get s period (fixed, use less to speed up simulation)
+ g_pulse_s : natural := 1000;
+ -- extend wdi by about 2**(14-1)= 8 s
+ g_wdi_extend_w : natural := 14
);
port (
- xo_clk : in std_logic; -- from pin, also used as reference for the PLL in the SOPC design
- xo_rst_n : out std_logic; -- to SOPC design
- sys_clk : in std_logic; -- system clock from PLL in SOPC design (= mm_clk)
- sys_locked : in std_logic; -- system clock PLL locked from SOPC design
- sys_rst : out std_logic; -- system reset released after system clock PLL has locked (= mm_rst)
- cal_clk : in std_logic := '0'; -- calibration or configuration interface clock
- cal_rst : out std_logic; -- calibration or configuration interface reset, released after sys_rst is released
- st_clk : in std_logic := '0'; -- streaming interface clock
- st_rst : out std_logic; -- streaming interface reset, released after sys_rst is released
- wdi_in : in std_logic; -- from SW running on the NIOS2 in the SOPC design
- wdi_out : out std_logic; -- to FPGA pin
- pulse_us : out std_logic; -- pulses every us
- pulse_ms : out std_logic; -- pulses every ms
- pulse_s : out std_logic -- pulses every s
+ -- from pin, also used as reference for the PLL in the SOPC design
+ xo_clk : in std_logic;
+ -- to SOPC design
+ xo_rst_n : out std_logic;
+ -- system clock from PLL in SOPC design (= mm_clk)
+ sys_clk : in std_logic;
+ -- system clock PLL locked from SOPC design
+ sys_locked : in std_logic;
+ -- system reset released after system clock PLL has locked (= mm_rst)
+ sys_rst : out std_logic;
+ -- calibration or configuration interface clock
+ cal_clk : in std_logic := '0';
+ -- calibration or configuration interface reset, released after sys_rst is released
+ cal_rst : out std_logic;
+ -- streaming interface clock
+ st_clk : in std_logic := '0';
+ -- streaming interface reset, released after sys_rst is released
+ st_rst : out std_logic;
+ -- from SW running on the NIOS2 in the SOPC design
+ wdi_in : in std_logic;
+ -- to FPGA pin
+ wdi_out : out std_logic;
+ -- pulses every us
+ pulse_us : out std_logic;
+ -- pulses every ms
+ pulse_ms : out std_logic;
+ -- pulses every s
+ pulse_s : out std_logic
);
end unb1_board_node_ctrl;
architecture str of unb1_board_node_ctrl is
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
signal i_sys_rst : std_logic;
signal i_pulse_ms : std_logic;
@@ -71,7 +90,8 @@ begin
xo_rst_n => xo_rst_n,
sys_clk => sys_clk,
sys_locked => sys_locked,
- sys_rst => i_sys_rst -- release reset some clock cycles after sys_locked went high
+ -- release reset some clock cycles after sys_locked went high
+ sys_rst => i_sys_rst
);
u_common_areset_cal : entity common_lib.common_areset
@@ -80,7 +100,8 @@ begin
g_delay_len => c_reset_len
)
port map (
- in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
+ -- release reset some clock cycles after i_sys_rst went low
+ in_rst => i_sys_rst,
clk => cal_clk,
out_rst => cal_rst
);
@@ -91,7 +112,8 @@ begin
g_delay_len => c_reset_len
)
port map (
- in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
+ -- release reset some clock cycles after i_sys_rst went low
+ in_rst => i_sys_rst,
clk => st_clk,
out_rst => st_rst
);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
index d524e5a62326d474ef631bf8ea9bd9333f760fe2..99fb7d6f717f5baf2d76c35f53f94035fd61679e 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
@@ -45,115 +45,162 @@ package unb1_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
-- *_dat_w : The default MM data width is c_word_w=32, otherwise it is specified in the record
type t_c_unb1_board_peripherals_mm_reg is record
- cross_clock_domain : boolean; -- = TRUE -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ -- = TRUE -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ cross_clock_domain : boolean;
-- 1GbE
- reg_tse_adr_w : natural; -- = 10 -- = c_tse_byte_addr_w from tse_pkg.vhd
- reg_eth_adr_w : natural; -- = 4 -- = c_eth_reg_addr_w from eth_pkg.vhd
- ram_eth_adr_w : natural; -- = 10 -- = c_eth_ram_addr_w from eth_pkg.vhd
+ -- = 10 -- = c_tse_byte_addr_w from tse_pkg.vhd
+ reg_tse_adr_w : natural;
+ -- = 4 -- = c_eth_reg_addr_w from eth_pkg.vhd
+ reg_eth_adr_w : natural;
+ -- = 10 -- = c_eth_ram_addr_w from eth_pkg.vhd
+ ram_eth_adr_w : natural;
-- pi_system_info (first word of reg_unb_system_info_adr_w is backwards compatible with the original single word PIO system info)
- reg_unb_system_info_adr_w : natural; -- = 5 -- fixed, from c_mm_reg in unb_system_info_reg
- rom_unb_system_info_adr_w : natural; -- = 10 -- fixed, from c_mm_rom in mms_unb_system_info
+ -- = 5 -- fixed, from c_mm_reg in unb_system_info_reg
+ reg_unb_system_info_adr_w : natural;
+ -- = 10 -- fixed, from c_mm_rom in mms_unb_system_info
+ rom_unb_system_info_adr_w : natural;
-- pi_reg_common
- reg_common_adr_w : natural; -- = 1 -- fixed, from c_mem_reg in mms_common_reg
+ -- = 1 -- fixed, from c_mem_reg in mms_common_reg
+ reg_common_adr_w : natural;
-- pi_ppsh
- reg_ppsh_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in ppsh_reg
+ -- = 1 -- fixed, from c_mm_reg in ppsh_reg
+ reg_ppsh_adr_w : natural;
-- pi_unb_sens
- reg_unb_sens_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in unb_sens_reg
+ -- = 3 -- fixed, from c_mm_reg in unb_sens_reg
+ reg_unb_sens_adr_w : natural;
-- pi_dpmm
- reg_dpmm_data_adr_w : natural; -- = 1 -- fixed, see dp_fifo_to_mm.vhd
- reg_dpmm_ctrl_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_fifo_to_mm_reg.vhd
+ -- = 1 -- fixed, see dp_fifo_to_mm.vhd
+ reg_dpmm_data_adr_w : natural;
+ -- = 1 -- fixed, from c_mm_reg in dp_fifo_to_mm_reg.vhd
+ reg_dpmm_ctrl_adr_w : natural;
-- pi_mmdp
- reg_mmdp_data_adr_w : natural; -- = 1 -- fixed, see dp_fifo_from_mm.vhd
- reg_mmdp_ctrl_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_fifo_from_mm_reg.vhd
+ -- = 1 -- fixed, see dp_fifo_from_mm.vhd
+ reg_mmdp_data_adr_w : natural;
+ -- = 1 -- fixed, from c_mm_reg in dp_fifo_from_mm_reg.vhd
+ reg_mmdp_ctrl_adr_w : natural;
-- pi_dp_ram_from_mm
- reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
+ -- = 1 -- fixed, see dp_ram_from_mm.vhd
+ reg_dp_ram_from_mm_adr_w : natural;
-- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
-- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
- reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
+ -- = 3 -- fixed, from c_mm_reg in epcs_reg
+ reg_epcs_adr_w : natural;
-- pi_remu
- reg_remu_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in remu_reg
+ -- = 3 -- fixed, from c_mm_reg in remu_reg
+ reg_remu_adr_w : natural;
-- pi_ddr
-- pi_ddr_capture (uses DP-MM read FIFO for data access)
- reg_ddr_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in ddr_reg
+ -- = 3 -- fixed, from c_mm_reg in ddr_reg
+ reg_ddr_adr_w : natural;
-- pi_io_ddr
- reg_io_ddr_adr_w : natural; -- = 16 -- fixed, from c_mm_reg in io_ddr (3) and in io_ddr_reg (8) that get multiplexed in on addresses 0..2, 8..15
+ -- = 16 -- fixed, from c_mm_reg in io_ddr (3) and in io_ddr_reg (8) that get multiplexed in on addresses 0..2, 8..15
+ reg_io_ddr_adr_w : natural;
-- pi_tr_nonbonded
- reg_tr_nonbonded_adr_w : natural; -- = 4 -- fixed, from c_mm_reg in tr_nonbonded_reg
+ -- = 4 -- fixed, from c_mm_reg in tr_nonbonded_reg
+ reg_tr_nonbonded_adr_w : natural;
-- pi_diagnostics
- reg_diagnostics_adr_w : natural; -- = 6 -- fixed, from c_mm_reg in diagnostics_reg
+ -- = 6 -- fixed, from c_mm_reg in diagnostics_reg
+ reg_diagnostics_adr_w : natural;
-- pi_dp_throttle
- reg_dp_throttle_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in dp_throttle_reg
+ -- = 2 -- fixed, from c_mm_reg in dp_throttle_reg
+ reg_dp_throttle_adr_w : natural;
-- pi_bsn_source
- reg_bsn_source_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in dp_bsn_source_reg.vhd
+ -- = 2 -- fixed, from c_mm_reg in dp_bsn_source_reg.vhd
+ reg_bsn_source_adr_w : natural;
-- pi_bsn_schedurer
- reg_bsn_scheduler_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_bsn_scheduler_reg.vhd
+ -- = 1 -- fixed, from c_mm_reg in dp_bsn_scheduler_reg.vhd
+ reg_bsn_scheduler_adr_w : natural;
-- pi_bsn_monitor
- reg_bsn_monitor_adr_w : natural; -- = 4 -- fixed, from c_mm_reg in dp_bsn_monitor_reg.vhd
+ -- = 4 -- fixed, from c_mm_reg in dp_bsn_monitor_reg.vhd
+ reg_bsn_monitor_adr_w : natural;
-- pi_aduh_quad (defaults for ADU)
- reg_adc_quad_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in aduh_quad_reg.vhd
+ -- = 3 -- fixed, from c_mm_reg in aduh_quad_reg.vhd
+ reg_adc_quad_adr_w : natural;
-- pi_aduh_i2c_commander (defaults for ADU)
- reg_i2c_commander_adr_w : natural; -- = 6 -- = c_i2c_cmdr_aduh_i2c_mm.control_adr_w, from i2c_commander_aduh_pkg, used to pass on commander_adr_w
- ram_i2c_protocol_adr_w : natural; -- = 13 -- = c_i2c_cmdr_aduh_i2c_mm.protocol_adr_w, from i2c_commander_aduh_pkg
- ram_i2c_result_adr_w : natural; -- = 12 -- = c_i2c_cmdr_aduh_i2c_mm.result_adr_w, from i2c_commander_aduh_pkg
+ -- = 6 -- = c_i2c_cmdr_aduh_i2c_mm.control_adr_w, from i2c_commander_aduh_pkg, used to pass on commander_adr_w
+ reg_i2c_commander_adr_w : natural;
+ -- = 13 -- = c_i2c_cmdr_aduh_i2c_mm.protocol_adr_w, from i2c_commander_aduh_pkg
+ ram_i2c_protocol_adr_w : natural;
+ -- = 12 -- = c_i2c_cmdr_aduh_i2c_mm.result_adr_w, from i2c_commander_aduh_pkg
+ ram_i2c_result_adr_w : natural;
-- pi_aduh_monitor (defaults for ADU or WG used in bn_capture)
- reg_aduh_mon_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in aduh_monitor_reg.vhd
- ram_aduh_mon_dat_w : natural; -- = 32 -- = c_sp_data_w, see node_bn_capture.vhd
- ram_aduh_mon_adr_w : natural; -- = 8 -- = ceil_log2(c_bn_capture.sp.monitor_buffer_nof_samples/c_wideband_factor), see node_bn_capture.vhd
+ -- = 2 -- fixed, from c_mm_reg in aduh_monitor_reg.vhd
+ reg_aduh_mon_adr_w : natural;
+ -- = 32 -- = c_sp_data_w, see node_bn_capture.vhd
+ ram_aduh_mon_dat_w : natural;
+ -- = 8 -- = ceil_log2(c_bn_capture.sp.monitor_buffer_nof_samples/c_wideband_factor), see node_bn_capture.vhd
+ ram_aduh_mon_adr_w : natural;
-- pi_diag_wg_wideband.py (defaults for WG used in bn_capture)
- reg_diag_wg_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in diag_wg_wideband_reg
- ram_diag_wg_dat_w : natural; -- = 8 -- defined here, see bn_capture_input.vhd
- ram_diag_wg_adr_w : natural; -- = 10 -- defined here, see bn_capture_input.vhd
+ -- = 2 -- fixed, from c_mm_reg in diag_wg_wideband_reg
+ reg_diag_wg_adr_w : natural;
+ -- = 8 -- defined here, see bn_capture_input.vhd
+ ram_diag_wg_dat_w : natural;
+ -- = 10 -- defined here, see bn_capture_input.vhd
+ ram_diag_wg_adr_w : natural;
-- pi_diag_data_buffer.py (defaults for unb1_board_terminals_mesh used in fn_terminal_bf)
- ram_diag_db_nof_buf : natural; -- = 16
- ram_diag_db_buf_size : natural; -- = 1024
- ram_diag_db_adr_w : natural; -- = 14 -- = ram_diag_db_nof_buf*ceil_log2(ram_diag_db_buf_size)
- reg_diag_db_adr_w : natural; -- = 5 -- 32 words for 16 streams max
+ -- = 16
+ ram_diag_db_nof_buf : natural;
+ -- = 1024
+ ram_diag_db_buf_size : natural;
+ -- = 14 -- = ram_diag_db_nof_buf*ceil_log2(ram_diag_db_buf_size)
+ ram_diag_db_adr_w : natural;
+ -- = 5 -- 32 words for 16 streams max
+ reg_diag_db_adr_w : natural;
-- pi_diag_block_gen (defaults when used with the BF for Apertif)
- reg_diag_bg_adr_w : natural; -- = 3
- ram_diag_bg_adr_w : natural; -- = 11 -- = ceil_log2(c_bf.nof_subbands*c_bf.nof_signal_paths/c_bf.nof_input_streams = 24*64/16 = 96) + ceil_log2(c_bf.nof_input_streams = 16)
+ -- = 3
+ reg_diag_bg_adr_w : natural;
+ -- = 11 -- = ceil_log2(c_bf.nof_subbands*c_bf.nof_signal_paths/c_bf.nof_input_streams = 24*64/16 = 96) + ceil_log2(c_bf.nof_input_streams = 16)
+ ram_diag_bg_adr_w : natural;
-- pi_diag_tx_seq.py
- reg_diag_tx_seq_w : natural; -- = 2
+ -- = 2
+ reg_diag_tx_seq_w : natural;
-- pi_diag_tx_seq.py
- reg_diag_rx_seq_w : natural; -- = 3
+ -- = 3
+ reg_diag_rx_seq_w : natural;
-- pi_bf_bf (defaults for the BF for Apertif)
- reg_bf_offsets_adr_w : natural; -- = 5 -- = ceil_log2(c_bf.nof_offsets = 6) + ceil_log2(c_bf.nof_bf_units = 4)
- ram_bf_weights_adr_w : natural; -- = 16 -- = ceil_log2(c_bf.nof_bf_units*c_bf.nof_signal_paths*c_bf.nof_weights = 4 * 64 * 256 = 65536)
- ram_st_sst_bf_adr_w : natural; -- = 11 -- = ceil_log2(c_bf.nof_bf_units*c_bf.stat_data_sz*c_bf.nof_weights = 4 * 2 * 256 = 2048)
+ -- = 5 -- = ceil_log2(c_bf.nof_offsets = 6) + ceil_log2(c_bf.nof_bf_units = 4)
+ reg_bf_offsets_adr_w : natural;
+ -- = 16 -- = ceil_log2(c_bf.nof_bf_units*c_bf.nof_signal_paths*c_bf.nof_weights = 4 * 64 * 256 = 65536)
+ ram_bf_weights_adr_w : natural;
+ -- = 11 -- = ceil_log2(c_bf.nof_bf_units*c_bf.stat_data_sz*c_bf.nof_weights = 4 * 2 * 256 = 2048)
+ ram_st_sst_bf_adr_w : natural;
-- pi_mdio
- reg_mdio_adr_w : natural; -- = 3
+ -- = 3
+ reg_mdio_adr_w : natural;
-- dp_offload
- reg_dp_offload_tx_adr_w : natural; -- = 1
+ -- = 1
+ reg_dp_offload_tx_adr_w : natural;
end record;
constant c_unb1_board_peripherals_mm_reg_default : t_c_unb1_board_peripherals_mm_reg := (true, 10, 4, 10, 5, 10, 1, 1, 3, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
index 180b535b22becf962ec54fbf906e62071c0757a8..9743fee75cac675a5669ce2ff701c8397146597d 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
@@ -28,26 +28,42 @@ use dp_lib.dp_stream_pkg.all;
package unb1_board_pkg is
-- UniBoard
- constant c_unb1_board_nof_node : natural := 4; -- nof FN or nof BN on UniBoard
- constant c_unb1_board_nof_node_w : natural := 2; -- = ceil_log2(c_unb1_board_nof_node)
- constant c_unb1_board_nof_fn : natural := c_unb1_board_nof_node; -- nof Front Node FPGAs on UniBoard
- constant c_unb1_board_nof_bn : natural := c_unb1_board_nof_node; -- nof Back Node FPGAs on UniBoard
- constant c_unb1_board_nof_chip : natural := c_unb1_board_nof_fn + c_unb1_board_nof_bn; -- = 8
- constant c_unb1_board_nof_chip_w : natural := 3; -- = ceil_log2(c_unb1_board_nof_chip)
- constant c_unb1_board_nof_ddr3 : natural := 2; -- each node has 2 DDR3 modules
+ -- nof FN or nof BN on UniBoard
+ constant c_unb1_board_nof_node : natural := 4;
+ -- = ceil_log2(c_unb1_board_nof_node)
+ constant c_unb1_board_nof_node_w : natural := 2;
+ -- nof Front Node FPGAs on UniBoard
+ constant c_unb1_board_nof_fn : natural := c_unb1_board_nof_node;
+ -- nof Back Node FPGAs on UniBoard
+ constant c_unb1_board_nof_bn : natural := c_unb1_board_nof_node;
+ -- = 8
+ constant c_unb1_board_nof_chip : natural := c_unb1_board_nof_fn + c_unb1_board_nof_bn;
+ -- = ceil_log2(c_unb1_board_nof_chip)
+ constant c_unb1_board_nof_chip_w : natural := 3;
+ -- each node has 2 DDR3 modules
+ constant c_unb1_board_nof_ddr3 : natural := 2;
-- Subrack
- constant c_unb1_board_nof_uniboard : natural := 4; -- nof UniBoard in a subrack
- constant c_unb1_board_nof_uniboard_w : natural := 5; -- Only 2 required for 4 boards; full width is 5.
+ -- nof UniBoard in a subrack
+ constant c_unb1_board_nof_uniboard : natural := 4;
+ -- Only 2 required for 4 boards; full width is 5.
+ constant c_unb1_board_nof_uniboard_w : natural := 5;
-- Clock frequencies
- constant c_unb1_board_ext_clk_freq_200M : natural := 200 * 10**6; -- external clock, SMA clock
- constant c_unb1_board_eth_clk_freq : natural := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL in SOPC
- constant c_unb1_board_tse_clk_freq : natural := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL in SOPC
- constant c_unb1_board_cal_clk_freq : natural := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL in SOPC
- constant c_unb1_board_mm_clk_freq_50M : natural := 50 * 10**6; -- SOPC memory mapped bus clock derived from ETH_clk by PLL in SOPC
- constant c_unb1_board_mm_clk_freq_100M : natural := 100 * 10**6; -- SOPC memory mapped bus clock derived from ETH_clk by PLL in SOPC
- constant c_unb1_board_mm_clk_freq_125M : natural := 125 * 10**6; -- SOPC memory mapped bus clock derived from ETH_clk by PLL in SOPC
+ -- external clock, SMA clock
+ constant c_unb1_board_ext_clk_freq_200M : natural := 200 * 10**6;
+ -- fixed 25 MHz ETH XO clock used as reference clock for the PLL in SOPC
+ constant c_unb1_board_eth_clk_freq : natural := 25 * 10**6;
+ -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL in SOPC
+ constant c_unb1_board_tse_clk_freq : natural := 125 * 10**6;
+ -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL in SOPC
+ constant c_unb1_board_cal_clk_freq : natural := 40 * 10**6;
+ -- SOPC memory mapped bus clock derived from ETH_clk by PLL in SOPC
+ constant c_unb1_board_mm_clk_freq_50M : natural := 50 * 10**6;
+ -- SOPC memory mapped bus clock derived from ETH_clk by PLL in SOPC
+ constant c_unb1_board_mm_clk_freq_100M : natural := 100 * 10**6;
+ -- SOPC memory mapped bus clock derived from ETH_clk by PLL in SOPC
+ constant c_unb1_board_mm_clk_freq_125M : natural := 125 * 10**6;
-- PHY interface device numbers
constant c_unb1_board_phy_id_eth1g : natural := 1;
@@ -59,72 +75,105 @@ package unb1_board_pkg is
constant c_unb1_board_phy_id_adc : natural := 7;
-- PHY interface error numbers
- constant c_unb1_board_ok : natural := 0; -- value
- constant c_unb1_board_error : integer := 1; -- value
- constant c_unb1_board_error_eth1g_bi : natural := 1; -- = c_unb1_board_phy_id_eth1g; -- bit number index
- constant c_unb1_board_error_eth10g_bi : natural := 2; -- = c_unb1_board_phy_id_eth10g;
- constant c_unb1_board_error_tr_mesh_bi : natural := 3; -- = c_unb1_board_phy_id_tr_mesh;
- constant c_unb1_board_error_tr_back_bi : natural := 4; -- = c_unb1_board_phy_id_tr_back;
- constant c_unb1_board_error_ddr3_I_bi : natural := 5; -- = c_unb1_board_phy_id_ddr3_I;
- constant c_unb1_board_error_ddr3_II_bi : natural := 6; -- = c_unb1_board_phy_id_ddr3_II;
- constant c_unb1_board_error_adc_bi : natural := 7; -- = c_unb1_board_phy_id_adc;
+ -- value
+ constant c_unb1_board_ok : natural := 0;
+ -- value
+ constant c_unb1_board_error : integer := 1;
+ -- = c_unb1_board_phy_id_eth1g; -- bit number index
+ constant c_unb1_board_error_eth1g_bi : natural := 1;
+ -- = c_unb1_board_phy_id_eth10g;
+ constant c_unb1_board_error_eth10g_bi : natural := 2;
+ -- = c_unb1_board_phy_id_tr_mesh;
+ constant c_unb1_board_error_tr_mesh_bi : natural := 3;
+ -- = c_unb1_board_phy_id_tr_back;
+ constant c_unb1_board_error_tr_back_bi : natural := 4;
+ -- = c_unb1_board_phy_id_ddr3_I;
+ constant c_unb1_board_error_ddr3_I_bi : natural := 5;
+ -- = c_unb1_board_phy_id_ddr3_II;
+ constant c_unb1_board_error_ddr3_II_bi : natural := 6;
+ -- = c_unb1_board_phy_id_adc;
+ constant c_unb1_board_error_adc_bi : natural := 7;
constant c_unb1_board_error_w : natural := 8;
-- I2C
- constant c_unb1_board_reg_sens_adr_w : natural := 3; -- must match ceil_log2(c_mm_nof_dat) in unb1_board_sens_reg.vhd
+ -- must match ceil_log2(c_mm_nof_dat) in unb1_board_sens_reg.vhd
+ constant c_unb1_board_reg_sens_adr_w : natural := 3;
-- 10G
- constant c_unb1_board_nof_mdio : natural := 3; -- Number of MD interfaces
+ -- Number of MD interfaces
+ constant c_unb1_board_nof_mdio : natural := 3;
-- CONSTANT RECORD DECLARATIONS ---------------------------------------------
-- PHY interface instantiation control
type t_c_unb1_board_use_phy is record
- eth1g : natural; -- used to set g_udp_offload for streaming DP offload (or onload), the 1GbE for MM control on hardware is always enabled in ctrl_unb1_board
+ -- used to set g_udp_offload for streaming DP offload (or onload), the 1GbE for MM control on hardware is always enabled in ctrl_unb1_board
+ eth1g : natural;
tr_front : natural;
tr_mesh : natural;
tr_back : natural;
ddr3_I : natural;
ddr3_II : natural;
adc : natural;
- wdi : natural; -- enable WDI when 1, else disable by leaving unconnected so 'Z'
+ -- enable WDI when 1, else disable by leaving unconnected so 'Z'
+ wdi : natural;
end record;
-- Transceivers
type t_c_unb1_board_tr is record
- nof_bus : natural; -- = 4; -- FN-BN, BN-BI
- bus_w : natural; -- = 4; -- FN-BN, BN-BI
- cntrl_w : natural; -- = 3; -- SI-FN
- cntrl_lasi_id : natural; -- = 0; -- SI-FN
- cntrl_mdc_id : natural; -- = 1; -- SI-FN
- cntrl_mdio_id : natural; -- = 2; -- SI-FN
+ -- = 4; -- FN-BN, BN-BI
+ nof_bus : natural;
+ -- = 4; -- FN-BN, BN-BI
+ bus_w : natural;
+ -- = 3; -- SI-FN
+ cntrl_w : natural;
+ -- = 0; -- SI-FN
+ cntrl_lasi_id : natural;
+ -- = 1; -- SI-FN
+ cntrl_mdc_id : natural;
+ -- = 2; -- SI-FN
+ cntrl_mdio_id : natural;
end record;
- constant c_unb1_board_tr : t_c_unb1_board_tr := ( 4, 4, 3, 0, 1, 2); -- UniBoard hardware has 4 bundles of 4 transceivers or 16 individual transceivers (including CMU transceivers)
- constant c_unb1_board_tr_mesh : t_c_unb1_board_tr := ( 4, 3, 3, 0, 1, 2); -- the FN-BN mesh uses 4 bundles of 3 transceivers or 12 individual transceivers (not using the CMU transceivers)
- constant c_unb1_board_tr_back : t_c_unb1_board_tr := ( 3, 4, 3, 0, 1, 2); -- the BN-BI back uses 3 bundles of 4 transceivers or 12 individual transceivers (not using the CMU transceivers)
- constant c_unb1_board_tr_xaui : t_c_unb1_board_tr := ( 3, 4, 3, 0, 1, 2); -- FN-XAUI use 3 bundles of 4 transceivers (the CMU transceivers are not HW connected) and XAUI PHY control for 10GbE
+ -- UniBoard hardware has 4 bundles of 4 transceivers or 16 individual transceivers (including CMU transceivers)
+ constant c_unb1_board_tr : t_c_unb1_board_tr := ( 4, 4, 3, 0, 1, 2);
+ -- the FN-BN mesh uses 4 bundles of 3 transceivers or 12 individual transceivers (not using the CMU transceivers)
+ constant c_unb1_board_tr_mesh : t_c_unb1_board_tr := ( 4, 3, 3, 0, 1, 2);
+ -- the BN-BI back uses 3 bundles of 4 transceivers or 12 individual transceivers (not using the CMU transceivers)
+ constant c_unb1_board_tr_back : t_c_unb1_board_tr := ( 3, 4, 3, 0, 1, 2);
+ -- FN-XAUI use 3 bundles of 4 transceivers (the CMU transceivers are not HW connected) and XAUI PHY control for 10GbE
+ constant c_unb1_board_tr_xaui : t_c_unb1_board_tr := ( 3, 4, 3, 0, 1, 2);
-- Transceivers network array types for the UniBoard mesh HW and for a backplane HW
- constant c_unb1_board_tr_mesh_hw_nof_bus : natural := c_unb1_board_nof_node; -- fixed 4 FN and 4 BN on one UniBoard
- constant c_unb1_board_tr_mesh_hw_bus_w : natural := 4; -- effectively 4-1 = 3, because the CMU tranceivers are connected on the mesh, but typically not used
- constant c_unb1_board_tr_back_hw_nof_bus : natural := c_unb1_board_nof_uniboard; -- assume 4 UniBoard in a subrack (could be more), so connect to 4 - 1= 3 other UniBoards in subrack. Also allow complete range 3..0 to be used for logical indexing (including the hosting board itself).
- constant c_unb1_board_tr_back_hw_bus_w : natural := 4; -- the CMU tranceivers are not connected on the backplane
+ -- fixed 4 FN and 4 BN on one UniBoard
+ constant c_unb1_board_tr_mesh_hw_nof_bus : natural := c_unb1_board_nof_node;
+ -- effectively 4-1 = 3, because the CMU tranceivers are connected on the mesh, but typically not used
+ constant c_unb1_board_tr_mesh_hw_bus_w : natural := 4;
+ -- assume 4 UniBoard in a subrack (could be more), so connect to 4 - 1= 3 other UniBoards in subrack. Also allow complete range 3..0 to be used for logical indexing (including the hosting board itself).
+ constant c_unb1_board_tr_back_hw_nof_bus : natural := c_unb1_board_nof_uniboard;
+ -- the CMU tranceivers are not connected on the backplane
+ constant c_unb1_board_tr_back_hw_bus_w : natural := 4;
constant c_unb1_board_tr_xaui_hw_bus_w : natural := 4;
-- TR mesh node IO for 1 to 4 nodes
- type t_unb1_board_mesh_sosi_2arr is array (c_unb1_board_tr_mesh_hw_nof_bus - 1 downto 0) of t_dp_sosi_arr( c_unb1_board_tr_mesh_hw_bus_w - 1 downto 0); -- indexing (node id 3,2,1,0)(transceiver lane 3,2,1,0)
- type t_unb1_board_mesh_siso_2arr is array (c_unb1_board_tr_mesh_hw_nof_bus - 1 downto 0) of t_dp_siso_arr( c_unb1_board_tr_mesh_hw_bus_w - 1 downto 0); -- indexing (node id 3,2,1,0)(transceiver lane 3,2,1,0)
- type t_unb1_board_mesh_sl_2arr is array (c_unb1_board_tr_mesh_hw_nof_bus - 1 downto 0) of std_logic_vector(c_unb1_board_tr_mesh_hw_bus_w - 1 downto 0); -- indexing (node id 3,2,1,0)(transceiver lane 3,2,1,0)
+ -- indexing (node id 3,2,1,0)(transceiver lane 3,2,1,0)
+ type t_unb1_board_mesh_sosi_2arr is array (c_unb1_board_tr_mesh_hw_nof_bus - 1 downto 0) of t_dp_sosi_arr( c_unb1_board_tr_mesh_hw_bus_w - 1 downto 0);
+ -- indexing (node id 3,2,1,0)(transceiver lane 3,2,1,0)
+ type t_unb1_board_mesh_siso_2arr is array (c_unb1_board_tr_mesh_hw_nof_bus - 1 downto 0) of t_dp_siso_arr( c_unb1_board_tr_mesh_hw_bus_w - 1 downto 0);
+ -- indexing (node id 3,2,1,0)(transceiver lane 3,2,1,0)
+ type t_unb1_board_mesh_sl_2arr is array (c_unb1_board_tr_mesh_hw_nof_bus - 1 downto 0) of std_logic_vector(c_unb1_board_tr_mesh_hw_bus_w - 1 downto 0);
constant c_unb1_board_mesh_sosi_2arr_rst : t_unb1_board_mesh_sosi_2arr := (others => (others => c_dp_sosi_rst));
constant c_unb1_board_mesh_siso_2arr_rst : t_unb1_board_mesh_siso_2arr := (others => (others => c_dp_siso_rst));
constant c_unb1_board_mesh_sl_2arr_rst : t_unb1_board_mesh_sl_2arr := (others => (others => '0'));
-- TR backplane node IO for 1 BN to 3 BN each on the 3 other UniBoards
- type t_unb1_board_back_sosi_2arr is array (c_unb1_board_tr_back_hw_nof_bus - 1 downto 0) of t_dp_sosi_arr( c_unb1_board_tr_back_hw_bus_w - 1 downto 0); -- indexing (other uniboard 2,1,0)(transceiver lane 3,2,1,0) or indexing (uniboard 3,2,1,0)(transceiver lane 3,2,1,0)
- type t_unb1_board_back_siso_2arr is array (c_unb1_board_tr_back_hw_nof_bus - 1 downto 0) of t_dp_siso_arr( c_unb1_board_tr_back_hw_bus_w - 1 downto 0); -- indexing (other uniboard 2,1,0)(transceiver lane 3,2,1,0) or indexing (uniboard 3,2,1,0)(transceiver lane 3,2,1,0)
- type t_unb1_board_back_sl_2arr is array (c_unb1_board_tr_back_hw_nof_bus - 1 downto 0) of std_logic_vector(c_unb1_board_tr_back_hw_bus_w - 1 downto 0); -- indexing (other uniboard 2,1,0)(transceiver lane 3,2,1,0)
+ -- indexing (other uniboard 2,1,0)(transceiver lane 3,2,1,0) or indexing (uniboard 3,2,1,0)(transceiver lane 3,2,1,0)
+ type t_unb1_board_back_sosi_2arr is array (c_unb1_board_tr_back_hw_nof_bus - 1 downto 0) of t_dp_sosi_arr( c_unb1_board_tr_back_hw_bus_w - 1 downto 0);
+ -- indexing (other uniboard 2,1,0)(transceiver lane 3,2,1,0) or indexing (uniboard 3,2,1,0)(transceiver lane 3,2,1,0)
+ type t_unb1_board_back_siso_2arr is array (c_unb1_board_tr_back_hw_nof_bus - 1 downto 0) of t_dp_siso_arr( c_unb1_board_tr_back_hw_bus_w - 1 downto 0);
+ -- indexing (other uniboard 2,1,0)(transceiver lane 3,2,1,0)
+ type t_unb1_board_back_sl_2arr is array (c_unb1_board_tr_back_hw_nof_bus - 1 downto 0) of std_logic_vector(c_unb1_board_tr_back_hw_bus_w - 1 downto 0);
type t_unb1_board_xaui_sl_2arr is array (integer range <>) of std_logic_vector(c_unb1_board_tr_xaui_hw_bus_w - 1 downto 0);
@@ -134,14 +183,22 @@ package unb1_board_pkg is
-- DDR3 (definitions similar as in ug_altmemphy.pdf)
type t_c_unb1_board_ddr is record
- a_w : natural; -- = 16;
- ba_w : natural; -- = 3;
- dq_w : natural; -- = 64;
- nof_dq_per_dqs : natural; -- = 8;
- dqs_w : natural; -- = 8; -- = dq_w / nof_dq_per_dqs;
- dm_w : natural; -- = 8;
- cs_w : natural; -- = 2;
- clk_w : natural; -- = 2;
+ -- = 16;
+ a_w : natural;
+ -- = 3;
+ ba_w : natural;
+ -- = 64;
+ dq_w : natural;
+ -- = 8;
+ nof_dq_per_dqs : natural;
+ -- = 8; -- = dq_w / nof_dq_per_dqs;
+ dqs_w : natural;
+ -- = 8;
+ dm_w : natural;
+ -- = 2;
+ cs_w : natural;
+ -- = 2;
+ clk_w : natural;
end record;
constant c_unb1_board_ddr : t_c_unb1_board_ddr := (16, 3, 64, 8, 8, 8, 2, 2);
@@ -152,12 +209,18 @@ package unb1_board_pkg is
-- Test IO Interface
type t_c_unb1_board_testio is record
- tst_w : natural; -- = nof tst = 4; [tst_w-1 +tst_lo : tst_lo] = [7:4],
- led_w : natural; -- = nof led = 2; [led_w-1 +led_lo : led_lo] = [3:2],
- jmp_w : natural; -- = nof jmp = 2; [jmp_w-1 +jmp_lo : jmp_lo] = [1:0],
- tst_lo : natural; -- = 4;
- led_lo : natural; -- = 2;
- jmp_lo : natural; -- = 0;
+ -- = nof tst = 4; [tst_w-1 +tst_lo : tst_lo] = [7:4],
+ tst_w : natural;
+ -- = nof led = 2; [led_w-1 +led_lo : led_lo] = [3:2],
+ led_w : natural;
+ -- = nof jmp = 2; [jmp_w-1 +jmp_lo : jmp_lo] = [1:0],
+ jmp_w : natural;
+ -- = 4;
+ tst_lo : natural;
+ -- = 2;
+ led_lo : natural;
+ -- = 0;
+ jmp_lo : natural;
end record;
constant c_unb1_board_testio : t_c_unb1_board_testio := (4, 2, 2, 4, 2, 0);
@@ -165,10 +228,14 @@ package unb1_board_pkg is
constant c_unb1_board_testio_led_red : natural := c_unb1_board_testio.led_lo + 1;
type t_c_unb1_board_aux is record
- version_w : natural; -- = 2;
- id_w : natural; -- = 8; -- 5+3 bits wide = total node ID for up to 32 UniBoards in a system and 8 nodes per board
- chip_id_w : natural; -- = 3; -- board node ID for the 8 FPGA nodes on a UniBoard
- testio_w : natural; -- = 8;
+ -- = 2;
+ version_w : natural;
+ -- = 8; -- 5+3 bits wide = total node ID for up to 32 UniBoards in a system and 8 nodes per board
+ id_w : natural;
+ -- = 3; -- board node ID for the 8 FPGA nodes on a UniBoard
+ chip_id_w : natural;
+ -- = 8;
+ testio_w : natural;
testio : t_c_unb1_board_testio;
end record;
@@ -187,25 +254,38 @@ package unb1_board_pkg is
-- ADC Interface
type t_c_unb1_board_ai is record
- nof_ports : natural; -- = 4; -- Fixed 4 ADC BI port with names A, B, C, D
- nof_ovr : natural; -- = 2; -- Fixed 2 overflow signals, one for ports AB and one for ports CD
- port_w : natural; -- = 8; -- Fixed 8 bit ADC BI port width, the ADC sample width is also 8 bit
- lvds_data_rate : natural; -- = 800; -- The ADC sample rate is 800 Msps, so the LVDS rate is 800 Mbps per ADC BI data line,
- use_dpa : boolean; -- = TRUE; -- When TRUE use LVDS_RX with DPA, else used fixed IOE delays and/or lvds_clk_phase instead of DPA
- use_lvds_clk : boolean; -- = TRUE; -- When TRUE use the one or both ADC BI lvds_clk, else use the single dp_clk to capture the lvds data
- use_lvds_clk_rst : boolean; -- = FALSE; -- When TRUE then support reset pulse to ADU to align the lvds_clk to the dp_clk, else no support
- lvds_clk_phase : natural; -- = 0; -- Use PLL phase 0 for center aligned. Only for no DPA
- nof_clocks : natural; -- = 2; -- 1 --> Use ADC BI clock D or dp_clk and 32 bit port ABCD
+ -- = 4; -- Fixed 4 ADC BI port with names A, B, C, D
+ nof_ports : natural;
+ -- = 2; -- Fixed 2 overflow signals, one for ports AB and one for ports CD
+ nof_ovr : natural;
+ -- = 8; -- Fixed 8 bit ADC BI port width, the ADC sample width is also 8 bit
+ port_w : natural;
+ -- = 800; -- The ADC sample rate is 800 Msps, so the LVDS rate is 800 Mbps per ADC BI data line,
+ lvds_data_rate : natural;
+ -- = TRUE; -- When TRUE use LVDS_RX with DPA, else used fixed IOE delays and/or lvds_clk_phase instead of DPA
+ use_dpa : boolean;
+ -- = TRUE; -- When TRUE use the one or both ADC BI lvds_clk, else use the single dp_clk to capture the lvds data
+ use_lvds_clk : boolean;
+ -- = FALSE; -- When TRUE then support reset pulse to ADU to align the lvds_clk to the dp_clk, else no support
+ use_lvds_clk_rst : boolean;
+ -- = 0; -- Use PLL phase 0 for center aligned. Only for no DPA
+ lvds_clk_phase : natural;
+ -- = 2; -- 1 --> Use ADC BI clock D or dp_clk and 32 bit port ABCD
+ nof_clocks : natural;
-- 2 --> Use ADC BI clock A, D and 16 bit ports AB, CD
- lvds_deser_factor : natural; -- = 2; -- The ADC sampled data comes in with a DDR lvds_clk, so lvds_data_rate / 2
- dp_deser_factor : natural; -- = 4; -- The Data Path clock dp_clk frequency is 200 MHz, so lvds_data_rate / 4
+ -- = 2; -- The ADC sampled data comes in with a DDR lvds_clk, so lvds_data_rate / 2
+ lvds_deser_factor : natural;
+ -- = 4; -- The Data Path clock dp_clk frequency is 200 MHz, so lvds_data_rate / 4
+ dp_deser_factor : natural;
end record;
constant c_unb1_board_ai : t_c_unb1_board_ai := (4, 2, 8, 800, true, true, false, 0, 2, 2, 4);
type t_unb1_board_fw_version is record
- hi : natural; -- = 0..15
- lo : natural; -- = 0..15, firmware version is: hi.lo
+ -- = 0..15
+ hi : natural;
+ -- = 0..15, firmware version is: hi.lo
+ lo : natural;
end record;
constant c_unb1_board_fw_version : t_unb1_board_fw_version := (0, 0);
@@ -219,26 +299,41 @@ package unb1_board_pkg is
end record;
type t_unb1_board_ddr_inout is record
- dq : std_logic_vector(c_unb1_board_ci.ddr.dq_w - 1 downto 0); -- data bus
- dqs : std_logic_vector(c_unb1_board_ci.ddr.dqs_w - 1 downto 0); -- data strobe bus
+ -- data bus
+ dq : std_logic_vector(c_unb1_board_ci.ddr.dq_w - 1 downto 0);
+ -- data strobe bus
+ dqs : std_logic_vector(c_unb1_board_ci.ddr.dqs_w - 1 downto 0);
dqs_n : std_logic_vector(c_unb1_board_ci.ddr.dqs_w - 1 downto 0);
- clk : std_logic_vector(c_unb1_board_ci.ddr.clk_w - 1 downto 0); -- clock, positive edge clock
- clk_n : std_logic_vector(c_unb1_board_ci.ddr.clk_w - 1 downto 0); -- clock, negative edge clock
- scl : std_logic; -- I2C
+ -- clock, positive edge clock
+ clk : std_logic_vector(c_unb1_board_ci.ddr.clk_w - 1 downto 0);
+ -- clock, negative edge clock
+ clk_n : std_logic_vector(c_unb1_board_ci.ddr.clk_w - 1 downto 0);
+ -- I2C
+ scl : std_logic;
sda : std_logic;
end record;
type t_unb1_board_ddr_out is record
- a : std_logic_vector(c_unb1_board_ci.ddr.a_w - 1 downto 0); -- row and column address
- ba : std_logic_vector(c_unb1_board_ci.ddr.ba_w - 1 downto 0); -- bank address
- dm : std_logic_vector(c_unb1_board_ci.ddr.dm_w - 1 downto 0); -- data mask bus
- cas_n : std_logic; -- column address strobe
- ras_n : std_logic; -- row address strobe
- we_n : std_logic; -- write enable signal
- reset_n : std_logic; -- reset signal
- odt : std_logic_vector(c_unb1_board_ci.ddr.cs_w - 1 downto 0); -- on-die termination control signal
- cke : std_logic_vector(c_unb1_board_ci.ddr.cs_w - 1 downto 0); -- clock enable
- cs_n : std_logic_vector(c_unb1_board_ci.ddr.cs_w - 1 downto 0); -- chip select
+ -- row and column address
+ a : std_logic_vector(c_unb1_board_ci.ddr.a_w - 1 downto 0);
+ -- bank address
+ ba : std_logic_vector(c_unb1_board_ci.ddr.ba_w - 1 downto 0);
+ -- data mask bus
+ dm : std_logic_vector(c_unb1_board_ci.ddr.dm_w - 1 downto 0);
+ -- column address strobe
+ cas_n : std_logic;
+ -- row address strobe
+ ras_n : std_logic;
+ -- write enable signal
+ we_n : std_logic;
+ -- reset signal
+ reset_n : std_logic;
+ -- on-die termination control signal
+ odt : std_logic_vector(c_unb1_board_ci.ddr.cs_w - 1 downto 0);
+ -- clock enable
+ cke : std_logic_vector(c_unb1_board_ci.ddr.cs_w - 1 downto 0);
+ -- chip select
+ cs_n : std_logic_vector(c_unb1_board_ci.ddr.cs_w - 1 downto 0);
end record;
--CONSTANT c_unb1_board_ddr_in_rst : t_unb1_board_ddr_in := ('0', 'X');
@@ -249,20 +344,29 @@ package unb1_board_pkg is
-- . If no I2C bus arbitration or clock stretching is needed then the SCL only needs to be output.
-- . Can also be used for a PHY Management Data IO interface with serial clock MDC and serial data MDIO
type t_unb1_board_i2c_inout is record
- scl : std_logic; -- serial clock
- sda : std_logic; -- serial data
+ -- serial clock
+ scl : std_logic;
+ -- serial data
+ sda : std_logic;
end record;
-- System info
type t_c_unb1_board_system_info is record
- version : natural; -- UniBoard board HW version (2 bit value)
- id : natural; -- UniBoard FPGA node id (8 bit value)
+ -- UniBoard board HW version (2 bit value)
+ version : natural;
+ -- UniBoard FPGA node id (8 bit value)
+ id : natural;
-- Derived ID info:
- bck_id : natural; -- = id[7:3], ID part from back plane
- chip_id : natural; -- = id[2:0], ID part from UniBoard
- is_bn : natural; -- = id[2], 0 for Front Node, 1 for Back Node
- node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
- is_bn3 : natural; -- 1 for Back Node 3, else 0.
+ -- = id[7:3], ID part from back plane
+ bck_id : natural;
+ -- = id[2:0], ID part from UniBoard
+ chip_id : natural;
+ -- = id[2], 0 for Front Node, 1 for Back Node
+ is_bn : natural;
+ -- = id[1:0], node ID: 0, 1, 2 or 3
+ node_id : natural;
+ -- 1 for Back Node 3, else 0.
+ is_bn3 : natural;
end record;
function func_unb1_board_system_info(VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -306,13 +410,17 @@ package body unb1_board_pkg is
function func_unb1_board_chip_id(chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
node_type : in t_e_unb1_board_node) return std_logic_vector is
- variable v_chip_id : std_logic_vector(chip_id'range); -- [2:0]
+ -- [2:0]
+ variable v_chip_id : std_logic_vector(chip_id'range);
begin
- v_chip_id := chip_id; -- default for design that can run on either FN or BN
+ -- default for design that can run on either FN or BN
+ v_chip_id := chip_id;
if node_type = e_fn then
- v_chip_id(2) := '0'; -- design that is intended to run on a FN
+ -- design that is intended to run on a FN
+ v_chip_id(2) := '0';
elsif node_type = e_bn then
- v_chip_id(2) := '1'; -- design that is intended to run on a BN
+ -- design that is intended to run on a BN
+ v_chip_id(2) := '1';
end if;
return v_chip_id;
end;
@@ -322,8 +430,10 @@ package body unb1_board_pkg is
------------------------------------------------------------------------------
function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr is
- constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus; -- = 4 = c_unb1_board_tr_back_hw_nof_bus
- constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w; -- = 4 = c_unb1_board_tr_back_hw_bus_w
+ -- = 4 = c_unb1_board_tr_back_hw_nof_bus
+ constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus;
+ -- = 4 = c_unb1_board_tr_back_hw_bus_w
+ constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w;
variable v_out_2arr : t_unb1_board_back_sosi_2arr;
begin
@@ -336,8 +446,10 @@ package body unb1_board_pkg is
end;
function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_back_siso_2arr is
- constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus; -- = 4 = c_unb1_board_tr_back_hw_nof_bus
- constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w; -- = 4 = c_unb1_board_tr_back_hw_bus_w
+ -- = 4 = c_unb1_board_tr_back_hw_nof_bus
+ constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus;
+ -- = 4 = c_unb1_board_tr_back_hw_bus_w
+ constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w;
variable v_out_2arr : t_unb1_board_back_siso_2arr;
begin
@@ -350,8 +462,10 @@ package body unb1_board_pkg is
end;
function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_mesh_sosi_2arr is
- constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus; -- = 4 = c_unb1_board_tr_mesh_hw_nof_bus
- constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w; -- = 4 = c_unb1_board_tr_mesh_hw_bus_w
+ -- = 4 = c_unb1_board_tr_mesh_hw_nof_bus
+ constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus;
+ -- = 4 = c_unb1_board_tr_mesh_hw_bus_w
+ constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w;
variable v_out_2arr : t_unb1_board_mesh_sosi_2arr;
begin
@@ -364,8 +478,10 @@ package body unb1_board_pkg is
end;
function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_mesh_siso_2arr is
- constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus; -- = 4 = c_unb1_board_tr_mesh_hw_nof_bus
- constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w; -- = 4 = c_unb1_board_tr_mesh_hw_bus_w
+ -- = 4 = c_unb1_board_tr_mesh_hw_nof_bus
+ constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus;
+ -- = 4 = c_unb1_board_tr_mesh_hw_bus_w
+ constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w;
variable v_out_2arr : t_unb1_board_mesh_siso_2arr;
begin
@@ -382,8 +498,10 @@ package body unb1_board_pkg is
------------------------------------------------------------------------------
function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr is
- constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus; -- = 4 = c_unb1_board_tr_back_hw_nof_bus
- constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w; -- = 4 = c_unb1_board_tr_back_hw_bus_w
+ -- = 4 = c_unb1_board_tr_back_hw_nof_bus
+ constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus;
+ -- = 4 = c_unb1_board_tr_back_hw_bus_w
+ constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w;
variable v_out_2arr : t_unb1_board_back_sosi_2arr;
begin
@@ -396,8 +514,10 @@ package body unb1_board_pkg is
end;
function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_back_siso_2arr is
- constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus; -- = 4 = c_unb1_board_tr_back_hw_nof_bus
- constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w; -- = 4 = c_unb1_board_tr_back_hw_bus_w
+ -- = 4 = c_unb1_board_tr_back_hw_nof_bus
+ constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus;
+ -- = 4 = c_unb1_board_tr_back_hw_bus_w
+ constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w;
variable v_out_2arr : t_unb1_board_back_siso_2arr;
begin
@@ -410,8 +530,10 @@ package body unb1_board_pkg is
end;
function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_mesh_sosi_2arr is
- constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus; -- = 4 = c_unb1_board_tr_mesh_hw_nof_bus
- constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w; -- = 4 = c_unb1_board_tr_mesh_hw_bus_w
+ -- = 4 = c_unb1_board_tr_mesh_hw_nof_bus
+ constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus;
+ -- = 4 = c_unb1_board_tr_mesh_hw_bus_w
+ constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w;
variable v_out_2arr : t_unb1_board_mesh_sosi_2arr;
begin
@@ -424,8 +546,10 @@ package body unb1_board_pkg is
end;
function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_mesh_siso_2arr is
- constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus; -- = 4 = c_unb1_board_tr_mesh_hw_nof_bus
- constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w; -- = 4 = c_unb1_board_tr_mesh_hw_bus_w
+ -- = 4 = c_unb1_board_tr_mesh_hw_nof_bus
+ constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus;
+ -- = 4 = c_unb1_board_tr_mesh_hw_bus_w
+ constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w;
variable v_out_2arr : t_unb1_board_mesh_siso_2arr;
begin
@@ -442,8 +566,10 @@ package body unb1_board_pkg is
------------------------------------------------------------------------------
function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_mesh_sosi_2arr is
- constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus; -- = 4
- constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w; -- = 4
+ -- = 4
+ constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus;
+ -- = 4
+ constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w;
variable v_out_2arr : t_unb1_board_mesh_sosi_2arr;
begin
@@ -456,8 +582,10 @@ package body unb1_board_pkg is
end;
function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_mesh_siso_2arr is
- constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus; -- = 4
- constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w; -- = 4
+ -- = 4
+ constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus;
+ -- = 4
+ constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w;
variable v_out_2arr : t_unb1_board_mesh_siso_2arr;
begin
@@ -474,8 +602,10 @@ package body unb1_board_pkg is
------------------------------------------------------------------------------
function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_back_sosi_2arr is
- constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus; -- = 4
- constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w; -- = 4
+ -- = 4
+ constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus;
+ -- = 4
+ constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w;
variable v_out_2arr : t_unb1_board_back_sosi_2arr;
begin
@@ -488,8 +618,10 @@ package body unb1_board_pkg is
end;
function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_back_siso_2arr is
- constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus; -- = 4
- constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w; -- = 4
+ -- = 4
+ constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus;
+ -- = 4
+ constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w;
variable v_out_2arr : t_unb1_board_back_siso_2arr;
begin
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
index ac56d4d4b26382c050acbec406dfede7432a5479..2237b8f6be5ec3d850a9783967d0d4a777c6c23d 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
@@ -27,9 +27,11 @@ use i2c_lib.i2c_pkg.all;
entity unb1_board_sens is
generic (
g_sim : boolean := false;
- g_clk_freq : natural := 100 * 10**6; -- clk frequency in Hz
+ -- clk frequency in Hz
+ g_clk_freq : natural := 100 * 10**6;
g_temp_high : natural := 85;
- g_sens_nof_result : natural := 4 -- Should match nof read bytes via I2C in the unb1_board_sens_ctrl SEQUENCE list
+ -- Should match nof read bytes via I2C in the unb1_board_sens_ctrl SEQUENCE list
+ g_sens_nof_result : natural := 4
);
port (
rst : in std_logic;
@@ -47,8 +49,10 @@ end entity;
architecture str of unb1_board_sens is
-- I2C clock rate settings
- constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
- constant c_sens_comma_w : natural := 0; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
+ -- define I2C clock rate
+ constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6));
+ -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
+ constant c_sens_comma_w : natural := 0;
-- 0 = no comma time
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
index a9747754f1745d8a09223b4dc012ea48eb23212c..13fe5eb97da1364091742095a18430dcf75b990f 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
@@ -35,7 +35,8 @@ entity unb1_board_sens_ctrl is
port (
rst : in std_logic;
clk : in std_logic;
- start : in std_logic; -- pulse to start the I2C sequence to read out the sensors
+ -- pulse to start the I2C sequence to read out the sensors
+ start : in std_logic;
out_dat : out std_logic_vector(c_byte_w - 1 downto 0);
out_val : out std_logic;
in_dat : in std_logic_vector(c_byte_w - 1 downto 0);
@@ -51,15 +52,19 @@ end entity;
architecture rtl of unb1_board_sens_ctrl is
-- I2C slave addresses of the devices on the I2C bus on UniBoard
- constant FPGA_MAX1617_ADR : natural := MAX1617_ADR_LOW_LOW; -- FPGA temperature sensor, slave address is "0011000"
- constant ETH_MAX1617_ADR : natural := MAX1617_ADR_MID_LOW; -- ETH temperature sensor, slave address is "0101001"
- constant HOTSWAP_LTC4260_ADR : natural := LTC4260_ADR_LOW_LOW_LOW; -- Hot swap controller, slave address is "1000100";
+ -- FPGA temperature sensor, slave address is "0011000"
+ constant FPGA_MAX1617_ADR : natural := MAX1617_ADR_LOW_LOW;
+ -- ETH temperature sensor, slave address is "0101001"
+ constant ETH_MAX1617_ADR : natural := MAX1617_ADR_MID_LOW;
+ -- Hot swap controller, slave address is "1000100";
+ constant HOTSWAP_LTC4260_ADR : natural := LTC4260_ADR_LOW_LOW_LOW;
type t_SEQUENCE is array (natural range <>) of natural;
-- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
-- Assume clk <= 200 MHz, so 5 ns period. Hence timeout of 4000 is enough.
- constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
+ -- wait 16 * 256 = 4096 clk periods
+ constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16);
constant c_SEQ : t_SEQUENCE := (
SMBUS_READ_BYTE , FPGA_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
@@ -69,9 +74,11 @@ architecture rtl of unb1_board_sens_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
+ -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
+ );
- constant c_seq_len : natural := c_SEQ'length - 1; -- upto SMBUS_C_END, the SMBUS_C_NOP is dummy to allow sufficient seq_cnt range
+ -- upto SMBUS_C_END, the SMBUS_C_NOP is dummy to allow sufficient seq_cnt range
+ constant c_seq_len : natural := c_SEQ'length - 1;
-- The protocol list c_SEQ yields a list of g_nof_result=14 result bytes:
-- . expected SMBUS_READ_BYTE -> rdbyte, ok=0
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
index 43e27b565f8525aff904d8dad008a0f5714278f7..08c333d55e84f0e9f06804d83b3de350e3a80c2e 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
@@ -72,12 +72,16 @@ entity unb1_board_sens_reg is
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers
sens_err : in std_logic := '0';
@@ -91,12 +95,14 @@ end unb1_board_sens_reg;
architecture rtl of unb1_board_sens_reg is
-- Define the actual size of the MM slave register
- constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
+ -- +1 to fit user set temp_high one additional address
+ constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1;
-- +1 to fit sens_err in the last address
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_mm_nof_dat,
init_sl => '0');
@@ -139,14 +145,17 @@ begin
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
-- no need to capture sens_data, it is not critical if the sens_data happens to be read just before and after an I2C access occurred
if vA < g_sens_nof_result then
sla_out.rddata <= RESIZE_MEM_DATA(sens_data(vA)(c_byte_w - 1 downto 0));
elsif vA = g_sens_nof_result then
- sla_out.rddata(0) <= sens_err; -- only valid for BN3
+ -- only valid for BN3
+ sla_out.rddata(0) <= sens_err;
else
sla_out.rddata(6 downto 0) <= i_temp_high;
end if;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
index 06b60254c051f75626dc4214d5d74b4cf1c8869f..54b62de501af9f603bff1c11d679f6b861eed371 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
@@ -33,8 +33,10 @@ use technology_lib.technology_pkg.all;
entity unb1_board_system_info is
generic (
g_sim : boolean := false;
- g_fw_version : t_unb1_board_fw_version := c_unb1_board_fw_version; -- firmware version x.y (4b.4b)
- g_aux : t_c_unb1_board_aux := c_unb1_board_aux; -- aux contains the hardware version
+ -- firmware version x.y (4b.4b)
+ g_fw_version : t_unb1_board_fw_version := c_unb1_board_fw_version;
+ -- aux contains the hardware version
+ g_aux : t_c_unb1_board_aux := c_unb1_board_aux;
g_rom_version : natural := 1;
g_technology : natural := c_tech_stratixiv
);
@@ -43,11 +45,16 @@ entity unb1_board_system_info is
hw_version : in std_logic_vector(g_aux.version_w - 1 downto 0);
id : in std_logic_vector(g_aux.id_w - 1 downto 0);
info : out std_logic_vector(c_word_w - 1 downto 0);
- bck_id : out std_logic_vector(c_unb1_board_nof_uniboard_w - 1 downto 0); -- ID[7:3]
- chip_id : out std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0); -- ID[2:0]
- node_id : out std_logic_vector(c_unb1_board_nof_node_w - 1 downto 0); -- ID[1:0]
- is_bn : out std_logic; -- '1' for Back Node, else '0' for Front Node
- is_bn3 : out std_logic -- '1' for Back Node 3, else '0'.
+ -- ID[7:3]
+ bck_id : out std_logic_vector(c_unb1_board_nof_uniboard_w - 1 downto 0);
+ -- ID[2:0]
+ chip_id : out std_logic_vector(c_unb1_board_nof_chip_w - 1 downto 0);
+ -- ID[1:0]
+ node_id : out std_logic_vector(c_unb1_board_nof_node_w - 1 downto 0);
+ -- '1' for Back Node, else '0' for Front Node
+ is_bn : out std_logic;
+ -- '1' for Back Node 3, else '0'.
+ is_bn3 : out std_logic
);
end unb1_board_system_info;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
index 594354d35e7a30d3ea330b3020a46e422530eea1..72ae8900509563c94ea698b999fb233d631fdbf4 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
@@ -73,16 +73,21 @@ entity unb1_board_system_info_reg is
end unb1_board_system_info_reg;
architecture rtl of unb1_board_system_info_reg is
- constant c_nof_fixed_regs : natural := 2; -- info, use_phy
- constant c_nof_design_name_regs : natural := 13; -- design_name
- constant c_nof_stamp_regs : natural := 3; -- date, time, svn rev
- constant c_nof_design_note_regs : natural := 13; -- note
+ -- info, use_phy
+ constant c_nof_fixed_regs : natural := 2;
+ -- design_name
+ constant c_nof_design_name_regs : natural := 13;
+ -- date, time, svn rev
+ constant c_nof_stamp_regs : natural := 3;
+ -- note
+ constant c_nof_design_note_regs : natural := 13;
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs;
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_nof_regs,
init_sl => '0');
@@ -111,8 +116,10 @@ begin
-- Read access: get register value
if sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
vA := TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0));
if vA = 0 then
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
index d0e464d77e299726b0f8d7fa82147d577b6578ba..313145be27085d2726823d3cb50961e249d7104d 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
@@ -48,28 +48,39 @@ entity unb1_board_terminals_back is
g_sim : boolean := false;
g_sim_level : natural := 0;
-- System
- g_nof_bus : natural := c_unb1_board_nof_uniboard; -- = 4 Uniboard in subrack, this UniBoard and 3 other UniBoards, so each UniBoard can be indexed by logical index 3:0
+ -- = 4 Uniboard in subrack, this UniBoard and 3 other UniBoards, so each UniBoard can be indexed by logical index 3:0
+ g_nof_bus : natural := c_unb1_board_nof_uniboard;
-- User
- g_usr_use_complex : boolean := false; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ g_usr_use_complex : boolean := false;
g_usr_data_w : natural := 32;
g_usr_frame_len : natural := 20;
- g_usr_nof_streams : natural := 4; -- number of user streams per bus
+ -- number of user streams per bus
+ g_usr_nof_streams : natural := 4;
-- Phy
- g_phy_nof_serial : natural := 4; -- up to 4 serial lanes per bus
+ -- up to 4 serial lanes per bus
+ g_phy_nof_serial : natural := 4;
g_phy_gx_mbps : natural := 5000;
- g_phy_rx_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY
+ -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY
+ g_phy_rx_fifo_size : natural := c_bram_m9k_fifo_depth;
-- Tx
- g_tx_input_use_fifo : boolean := true; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
- g_tx_input_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ g_tx_input_use_fifo : boolean := true;
+ -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ g_tx_input_fifo_size : natural := c_bram_m9k_fifo_depth;
g_tx_input_fifo_fill : natural := 0;
-- Rx
- g_rx_output_use_fifo : boolean := false; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_output_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_use_fifo : boolean := false;
+ -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ g_rx_output_fifo_size : natural := c_bram_m9k_fifo_depth;
g_rx_output_fifo_fill : natural := 0;
- g_rx_timeout_w : natural := 0 -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ g_rx_timeout_w : natural := 0
);
port (
- bck_id : in std_logic_vector(c_unb1_board_nof_uniboard_w - 1 downto 0); -- [7:3]; only [1:0] required to index boards 3:0 in a subrack
+ -- [7:3]; only [1:0] required to index boards 3:0 in a subrack
+ bck_id : in std_logic_vector(c_unb1_board_nof_uniboard_w - 1 downto 0);
mm_rst : in std_logic;
mm_clk : in std_logic;
@@ -100,10 +111,13 @@ end unb1_board_terminals_back;
architecture str of unb1_board_terminals_back is
-- DP/UTH packet
- constant c_packet_data_w : natural := g_usr_data_w; -- = 32, packet data width for DP packet and for UTH packet, must be >= g_usr_data_w
+ -- = 32, packet data width for DP packet and for UTH packet, must be >= g_usr_data_w
+ constant c_packet_data_w : natural := g_usr_data_w;
- constant c_nof_bus_logical : natural := g_nof_bus; -- Indexing 3:0 so each UniBoard can be indexed by logical index
- constant c_nof_bus_serial : natural := g_nof_bus - 1; -- Indexing 2:0, only the 'other' UniBoards can be indexed
+ -- Indexing 3:0 so each UniBoard can be indexed by logical index
+ constant c_nof_bus_logical : natural := g_nof_bus;
+ -- Indexing 2:0, only the 'other' UniBoards can be indexed
+ constant c_nof_bus_serial : natural := g_nof_bus - 1;
constant c_nof_gx : natural := c_nof_bus_serial * g_phy_nof_serial;
-- unb1_board_back_select
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
index b65dc635d740a2feb41f36c9ea01d9f6f5a088b7..c2c0233e4b37759fed87c8531d2be42dd9562021 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
@@ -63,31 +63,44 @@ entity unb1_board_terminals_mesh is
g_sim : boolean := false;
g_sim_level : natural := 0;
-- System
- g_node_type : t_e_unb1_board_node := e_any; -- or e_fn, or e_bn
- g_nof_bus : natural := 4; -- one bus to each of the 4 nodes on the other side of the mesh
+ -- or e_fn, or e_bn
+ g_node_type : t_e_unb1_board_node := e_any;
+ -- one bus to each of the 4 nodes on the other side of the mesh
+ g_nof_bus : natural := 4;
-- User
- g_usr_use_complex : boolean := false; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
- g_usr_data_w : natural := 32; -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit
+ -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ g_usr_use_complex : boolean := false;
+ -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit
+ g_usr_data_w : natural := 32;
g_usr_frame_len : natural := 20;
- g_usr_nof_streams : natural := 4; -- number of user streams per bus
+ -- number of user streams per bus
+ g_usr_nof_streams : natural := 4;
-- Phy
- g_phy_nof_serial : natural := 3; -- up to 4 serial lanes per bus
+ -- up to 4 serial lanes per bus
+ g_phy_nof_serial : natural := 3;
g_phy_gx_mbps : natural := 5000;
- g_phy_rx_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY
+ -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY
+ g_phy_rx_fifo_size : natural := c_bram_m9k_fifo_depth;
g_phy_ena_reorder : boolean := true;
-- Tx
g_use_tx : boolean := true;
- g_tx_input_use_fifo : boolean := true; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
- g_tx_input_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ g_tx_input_use_fifo : boolean := true;
+ -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ g_tx_input_fifo_size : natural := c_bram_m9k_fifo_depth;
g_tx_input_fifo_fill : natural := 0;
-- Rx
g_use_rx : boolean := true;
- g_rx_output_use_fifo : boolean := true; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_output_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_use_fifo : boolean := true;
+ -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ g_rx_output_fifo_size : natural := c_bram_m9k_fifo_depth;
g_rx_output_fifo_fill : natural := 0;
- g_rx_timeout_w : natural := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ g_rx_timeout_w : natural := 0;
-- Monitoring
- g_mon_select : natural := 0; -- 0 = no SOSI data buffers monitor via MM
+ -- 0 = no SOSI data buffers monitor via MM
+ g_mon_select : natural := 0;
-- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
-- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
-- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
@@ -97,11 +110,14 @@ entity unb1_board_terminals_mesh is
g_mon_nof_words : natural := 1024;
g_mon_use_sync : boolean := true;
-- UTH
- g_uth_len_max : natural := 255; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
- g_uth_typ_ofs : natural := 256 -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ g_uth_len_max : natural := 255;
+ -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ g_uth_typ_ofs : natural := 256
);
port (
- chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0) := (others => '0'); -- [2:0]
+ -- [2:0]
+ chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0) := (others => '0');
mm_rst : in std_logic;
mm_clk : in std_logic;
@@ -113,13 +129,17 @@ entity unb1_board_terminals_mesh is
-- User interface (4 nodes)(4 input streams)
tx_usr_siso_2arr : out t_unb1_board_mesh_siso_2arr;
- tx_usr_sosi_2arr : in t_unb1_board_mesh_sosi_2arr := (others => (others => c_dp_sosi_rst)); -- Tx
+ -- Tx
+ tx_usr_sosi_2arr : in t_unb1_board_mesh_sosi_2arr := (others => (others => c_dp_sosi_rst));
rx_usr_siso_2arr : in t_unb1_board_mesh_siso_2arr := (others => (others => c_dp_siso_rdy));
- rx_usr_sosi_2arr : out t_unb1_board_mesh_sosi_2arr; -- Rx
+ -- Rx
+ rx_usr_sosi_2arr : out t_unb1_board_mesh_sosi_2arr;
-- Serial (tr_nonbonded)
- tx_serial_2arr : out t_unb1_board_mesh_sl_2arr; -- Tx
- rx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0')); -- Rx
+ -- Tx
+ tx_serial_2arr : out t_unb1_board_mesh_sl_2arr;
+ -- Rx
+ rx_serial_2arr : in t_unb1_board_mesh_sl_2arr := (others => (others => '0'));
-- MM Control
-- . tr_nonbonded
@@ -136,10 +156,12 @@ end unb1_board_terminals_mesh;
architecture str of unb1_board_terminals_mesh is
-- DP/UTH packet
- constant c_packet_data_w : natural := 32; -- fixed 32, packet data width for DP packet and for UTH packet, must be >= g_usr_data_w to avoid need for data packing
+ -- fixed 32, packet data width for DP packet and for UTH packet, must be >= g_usr_data_w to avoid need for data packing
+ constant c_packet_data_w : natural := 32;
-- tr_nonbonded
- constant c_phy_data_w : natural := 32; -- fixed 32, tr_nonbonded supports 32b for generic g_phy_gx_mbps, must be >= c_packet_data_w to avoid loosing the higher bits
+ -- fixed 32, tr_nonbonded supports 32b for generic g_phy_gx_mbps, must be >= c_packet_data_w to avoid loosing the higher bits
+ constant c_phy_data_w : natural := 32;
constant c_phy_nof_gx : natural := g_nof_bus * g_phy_nof_serial;
-- g_mon_select
@@ -161,26 +183,33 @@ architecture str of unb1_board_terminals_mesh is
-- uth terminals
signal tx_term_siso_2arr : t_unb1_board_mesh_siso_2arr;
- signal tx_term_sosi_2arr : t_unb1_board_mesh_sosi_2arr; -- Tx
+ -- Tx
+ signal tx_term_sosi_2arr : t_unb1_board_mesh_sosi_2arr;
signal rx_term_siso_2arr : t_unb1_board_mesh_siso_2arr;
- signal rx_term_sosi_2arr : t_unb1_board_mesh_sosi_2arr; -- Rx
+ -- Rx
+ signal rx_term_sosi_2arr : t_unb1_board_mesh_sosi_2arr;
-- g_mon_select
- signal mon_sosi_arr : t_dp_sosi_arr(c_mon_nof_streams - 1 downto 0); -- selected sosi for the SOSI data monitor
+ -- selected sosi for the SOSI data monitor
+ signal mon_sosi_arr : t_dp_sosi_arr(c_mon_nof_streams - 1 downto 0);
signal mon_rx_term_pkt_sosi_2arr : t_unb1_board_mesh_sosi_2arr;
signal mon_rx_term_dist_sosi_2arr : t_unb1_board_mesh_sosi_2arr;
-- g_phy_ena_reorder
signal tx_phy_siso_2arr : t_unb1_board_mesh_siso_2arr;
- signal tx_phy_sosi_2arr : t_unb1_board_mesh_sosi_2arr; -- Tx
+ -- Tx
+ signal tx_phy_sosi_2arr : t_unb1_board_mesh_sosi_2arr;
signal rx_phy_siso_2arr : t_unb1_board_mesh_siso_2arr;
- signal rx_phy_sosi_2arr : t_unb1_board_mesh_sosi_2arr; -- Rx
+ -- Rx
+ signal rx_phy_sosi_2arr : t_unb1_board_mesh_sosi_2arr;
-- tr_nonbonded
signal tx_phy_siso_arr : t_dp_siso_arr(c_phy_nof_gx - 1 downto 0);
- signal tx_phy_sosi_arr : t_dp_sosi_arr(c_phy_nof_gx - 1 downto 0); -- Tx
+ -- Tx
+ signal tx_phy_sosi_arr : t_dp_sosi_arr(c_phy_nof_gx - 1 downto 0);
signal rx_phy_siso_arr : t_dp_siso_arr(c_phy_nof_gx - 1 downto 0);
- signal rx_phy_sosi_arr : t_dp_sosi_arr(c_phy_nof_gx - 1 downto 0); -- Rx
+ -- Rx
+ signal rx_phy_sosi_arr : t_dp_sosi_arr(c_phy_nof_gx - 1 downto 0);
signal tx_serial_arr : std_logic_vector(c_phy_nof_gx - 1 downto 0);
signal rx_serial_arr : std_logic_vector(c_phy_nof_gx - 1 downto 0);
@@ -245,9 +274,12 @@ begin
u_data_buf : entity diag_lib.mms_diag_data_buffer
generic map (
g_nof_streams => c_mon_nof_streams,
- g_data_w => c_mon_data_w, -- stream data width must be <= c_word_w = 32b, the MM word width
- g_buf_nof_data => g_mon_nof_words, -- nof words per data buffer
- g_buf_use_sync => g_mon_use_sync -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+ -- stream data width must be <= c_word_w = 32b, the MM word width
+ g_data_w => c_mon_data_w,
+ -- nof words per data buffer
+ g_buf_nof_data => g_mon_nof_words,
+ -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+ g_buf_use_sync => g_mon_use_sync
)
port map (
-- System
@@ -259,7 +291,8 @@ begin
ram_data_buf_mosi => ram_diag_data_buf_mosi,
ram_data_buf_miso => ram_diag_data_buf_miso,
-- ST interface
- in_sync => dp_sync, -- input sync pulse in ST dp_clk domain that starts data buffer when g_use_in_sync = TRUE
+ -- input sync pulse in ST dp_clk domain that starts data buffer when g_use_in_sync = TRUE
+ in_sync => dp_sync,
in_sosi_arr => mon_sosi_arr
);
end generate;
@@ -329,8 +362,10 @@ begin
port map (
chip_id => chip_id,
clk => dp_clk,
- tx_usr_sosi_2arr => tx_term_sosi_2arr, -- g_use_tx
- rx_usr_siso_2arr => rx_term_siso_2arr, -- g_use_rx
+ -- g_use_tx
+ tx_usr_sosi_2arr => tx_term_sosi_2arr,
+ -- g_use_rx
+ rx_usr_siso_2arr => rx_term_siso_2arr,
tx_phy_sosi_2arr => tx_phy_sosi_2arr,
rx_phy_siso_2arr => rx_phy_siso_2arr
);
@@ -345,8 +380,10 @@ begin
clk => dp_clk,
rx_phy_sosi_2arr => rx_phy_sosi_2arr,
tx_phy_siso_2arr => tx_phy_siso_2arr,
- rx_usr_sosi_2arr => rx_term_sosi_2arr, -- g_use_rx
- tx_usr_siso_2arr => tx_term_siso_2arr -- g_use_tx
+ -- g_use_rx
+ rx_usr_sosi_2arr => rx_term_sosi_2arr,
+ -- g_use_tx
+ tx_usr_siso_2arr => tx_term_siso_2arr
);
------------------------------------------------------------------------------
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
index 5bc2d1698e2f30dff83d3194158162ed750a55a2..dfbe30d70157010fe574aab1018644aa1bcb13d5 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
@@ -37,7 +37,8 @@ entity unb1_board_wdi_extend is
port (
rst : in std_logic;
clk : in std_logic;
- pulse_ms : in std_logic; -- pulses every 1 ms
+ -- pulses every 1 ms
+ pulse_ms : in std_logic;
wdi_in : in std_logic;
wdi_out : out std_logic
);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
index 8645f86e8f80ca85685e98d3edef549b275d5a9c..1cb795eda4cf62dd1994f5451bc1d685ebb15d41 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
@@ -31,12 +31,16 @@ use common_lib.common_mem_pkg.all;
entity unb1_board_wdi_reg is
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
wdi_override : out std_logic
@@ -47,12 +51,14 @@ architecture rtl of unb1_board_wdi_reg is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 1,
init_sl => '0');
-- For safety, WDI override requires the following word to be written:
- constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
+ -- "Boot factory"
+ constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7";
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -75,7 +81,8 @@ begin
else
wdi_override <= '0';
end if;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
index ca4d940d7bb06aeace52fde1a3d53c77a8550a22..63d3c21aeca86733e932cd9f3acd84bf1c7061da 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
@@ -39,7 +39,8 @@ use common_lib.tb_common_pkg.all;
use common_lib.tb_common_mem_pkg.all;
architecture tb of tb_mms_unb1_board_sens is
- constant c_sim : boolean := true; -- FALSE;
+ -- FALSE;
+ constant c_sim : boolean := true;
constant c_repeat : natural := 2;
constant c_clk_freq : natural := 100 * 10**6;
constant c_clk_period : time := (10**9 / c_clk_freq) * 1 ns;
@@ -47,19 +48,27 @@ architecture tb of tb_mms_unb1_board_sens is
-- Model I2C sensor slaves as on the UniBoard
constant c_temp_high : natural := 85;
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard --> hot swap = 5010 mAmpere (167)
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard --> hot swap = 48000 mVolt (120)
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard --> hot swap = 5010 mAmpere (167)
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard --> hot swap = 48000 mVolt (120)
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
constant c_sens_nof_result : natural := 4 + 1;
- constant c_sens_expected : t_natural_arr(0 to c_sens_nof_result - 1) := (60, 40, 167, 120, 0); -- 4 bytes as read by c_SEQ in unb1_board_sens_ctrl + sens_err
+ -- 4 bytes as read by c_SEQ in unb1_board_sens_ctrl + sens_err
+ constant c_sens_expected : t_natural_arr(0 to c_sens_nof_result - 1) := (60, 40, 167, 120, 0);
signal tb_end : std_logic := '0';
signal clk : std_logic := '0';
@@ -80,15 +89,18 @@ begin
clk <= (not clk) or tb_end after c_clk_period / 2;
-- I2C bus
- scl <= 'H'; -- model I2C pull up
- sda <= 'H'; -- model I2C pull up, use '0' and '1' to verify sens_err
+ -- model I2C pull up
+ scl <= 'H';
+ -- model I2C pull up, use '0' and '1' to verify sens_err
+ sda <= 'H';
scl <= scl_stretch;
sens_clk_stretch : process (scl)
begin
if falling_edge(scl) then
- scl_stretch <= '0', 'Z' after 50 ns; -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ scl_stretch <= '0', 'Z' after 50 ns;
end if;
end process;
@@ -114,7 +126,8 @@ begin
-- read I2C result data
for I in 0 to c_sens_nof_result - 1 loop
- proc_mem_mm_bus_rd(I, clk, reg_miso, reg_mosi); -- read sens_data
+ -- read sens_data
+ proc_mem_mm_bus_rd(I, clk, reg_miso, reg_mosi);
end loop;
proc_common_wait_some_cycles(clk, 1000);
@@ -131,7 +144,8 @@ begin
-- Verify sensor data
p_verify : process
begin
- wait until rising_edge(clk); -- Added this line to avoid warning: (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+ -- Added this line to avoid warning: (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+ wait until rising_edge(clk);
proc_common_wait_until_high(clk, sens_val);
assert TO_UINT(sens_dat) = c_sens_expected(0) report "Wrong FPGA temperature value" severity ERROR;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
index c30e88c962f588450e0ebe8fe699809b789ffd3f..f151b5ca2641468fe4fd7ca14deba65ea5c0935d 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
@@ -34,7 +34,8 @@ entity tb_unb1_board_clk200_pll is
end tb_unb1_board_clk200_pll;
architecture tb of tb_unb1_board_clk200_pll is
- constant c_ext_clk_period : time := 5 ns; -- 200 MHz
+ -- 200 MHz
+ constant c_ext_clk_period : time := 5 ns;
constant c_clk_vec_w : natural := 6;
constant c_clk_div : natural := 32;
@@ -60,7 +61,8 @@ architecture tb of tb_unb1_board_clk200_pll is
signal dp_clk200 : std_logic;
signal dp_rst200 : std_logic;
- signal st_clk_vec : std_logic_vector(c_clk_vec_w - 1 downto 0); -- PLL c6-c1
+ -- PLL c6-c1
+ signal st_clk_vec : std_logic_vector(c_clk_vec_w - 1 downto 0);
begin
tb_end <= '0', '1' after c_ext_clk_period * 5000;
@@ -69,7 +71,8 @@ begin
dut_0 : entity work.unb1_board_clk200_pll
generic map (
- g_sel => 0, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=0 for clk200_pll.vhd
+ g_sel => 0,
-- g_sel=0 for clk200_pll.vhd
g_clk200_phase_shift => "0",
g_clk200p_phase_shift => "0"
@@ -87,7 +90,8 @@ begin
dut_45 : entity work.unb1_board_clk200_pll
generic map (
- g_sel => 0, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=0 for clk200_pll.vhd
+ g_sel => 0,
-- g_sel=0 for clk200_pll.vhd
g_clk200_phase_shift => "625",
g_clk200p_phase_shift => "625"
@@ -105,7 +109,8 @@ begin
dut_p6 : entity work.unb1_board_clk200_pll
generic map (
- g_sel => 1, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=0 for clk200_pll.vhd
+ g_sel => 1,
-- g_sel=1 for clk200_pll_p6.vhd
g_clk200_phase_shift => "0",
-- g_sel=1 for clk200_pll_p6.vhd
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
index 1eaa6aa8070c062fe3b18135e3703eea919e7181..c17866beddf1104d3bb71cc90a230804d8b82a70 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
@@ -53,10 +53,14 @@ end tb_unb1_board_mesh_reorder_bidir;
architecture tb of tb_unb1_board_mesh_reorder_bidir is
constant c_reorder : boolean := true;
- constant c_chip_id_w : natural := c_unb1_board_aux.chip_id_w; -- = 3 to fit 8 fpgas in [2:0]
- constant c_nof_node : natural := c_unb1_board_nof_node; -- = 4
- constant c_nof_bus : natural := c_unb1_board_tr.nof_bus; -- = 4
- constant c_bus_w : natural := c_unb1_board_tr.bus_w; -- = 4
+ -- = 3 to fit 8 fpgas in [2:0]
+ constant c_chip_id_w : natural := c_unb1_board_aux.chip_id_w;
+ -- = 4
+ constant c_nof_node : natural := c_unb1_board_nof_node;
+ -- = 4
+ constant c_nof_bus : natural := c_unb1_board_tr.nof_bus;
+ -- = 4
+ constant c_bus_w : natural := c_unb1_board_tr.bus_w;
constant c_repeat : natural := 3;
constant c_clk_period : time := 10 ns;
@@ -185,19 +189,27 @@ begin
gen_lanes : for K in c_bus_w - 1 downto 0 generate
-- SOSI
-- . Transmit order
- fn_tx_valid((I * c_nof_bus + J) * c_bus_w + K) <= fn_tx_usr_sosi_3arr(I)(J)(K).valid; -- FN
- bn_tx_valid((I * c_nof_bus + J) * c_bus_w + K) <= bn_tx_usr_sosi_3arr(I)(J)(K).valid; -- BN
+ -- FN
+ fn_tx_valid((I * c_nof_bus + J) * c_bus_w + K) <= fn_tx_usr_sosi_3arr(I)(J)(K).valid;
+ -- BN
+ bn_tx_valid((I * c_nof_bus + J) * c_bus_w + K) <= bn_tx_usr_sosi_3arr(I)(J)(K).valid;
-- . Receive order (compensate for the transpose)
- fn_rx_valid((J * c_nof_bus + I) * c_bus_w + K) <= fn_rx_usr_sosi_3arr(I)(J)(K).valid; -- FN
- bn_rx_valid((J * c_nof_bus + I) * c_bus_w + K) <= bn_rx_usr_sosi_3arr(I)(J)(K).valid; -- BN
+ -- FN
+ fn_rx_valid((J * c_nof_bus + I) * c_bus_w + K) <= fn_rx_usr_sosi_3arr(I)(J)(K).valid;
+ -- BN
+ bn_rx_valid((J * c_nof_bus + I) * c_bus_w + K) <= bn_rx_usr_sosi_3arr(I)(J)(K).valid;
-- SISO
-- . Transmit order
- fn_rx_ready((I * c_nof_bus + J) * c_bus_w + K) <= fn_rx_usr_siso_3arr(I)(J)(K).ready; -- FN
- bn_rx_ready((I * c_nof_bus + J) * c_bus_w + K) <= bn_rx_usr_siso_3arr(I)(J)(K).ready; -- BN
+ -- FN
+ fn_rx_ready((I * c_nof_bus + J) * c_bus_w + K) <= fn_rx_usr_siso_3arr(I)(J)(K).ready;
+ -- BN
+ bn_rx_ready((I * c_nof_bus + J) * c_bus_w + K) <= bn_rx_usr_siso_3arr(I)(J)(K).ready;
-- . Receive order (compensate for the transpose)
- fn_tx_ready((J * c_nof_bus + I) * c_bus_w + K) <= fn_tx_usr_siso_3arr(I)(J)(K).ready; -- FN
- bn_tx_ready((J * c_nof_bus + I) * c_bus_w + K) <= bn_tx_usr_siso_3arr(I)(J)(K).ready; -- BN
+ -- FN
+ fn_tx_ready((J * c_nof_bus + I) * c_bus_w + K) <= fn_tx_usr_siso_3arr(I)(J)(K).ready;
+ -- BN
+ bn_tx_ready((J * c_nof_bus + I) * c_bus_w + K) <= bn_tx_usr_siso_3arr(I)(J)(K).ready;
end generate;
end generate;
end generate;
@@ -225,21 +237,30 @@ begin
g_reorder => c_reorder
)
port map (
- chip_id => TO_UVEC(I, c_chip_id_w), -- chip id 0, 1, 2, 3
+ -- chip id 0, 1, 2, 3
+ chip_id => TO_UVEC(I, c_chip_id_w),
-- Transmit clock domain
tx_clk => clk,
- tx_usr_sosi_2arr => fn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from FN user
- tx_usr_siso_2arr => fn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to FN user
- tx_phy_sosi_2arr => fn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
- tx_phy_siso_2arr => fn_tx_phy_siso_3arr(I), -- phy siso from mesh
+ -- user sosi to phy = sosi.valid driver from FN user
+ tx_usr_sosi_2arr => fn_tx_usr_sosi_3arr(I),
+ -- user siso from phy = siso.ready result to FN user
+ tx_usr_siso_2arr => fn_tx_usr_siso_3arr(I),
+ -- phy sosi to mesh
+ tx_phy_sosi_2arr => fn_tx_phy_sosi_3arr(I),
+ -- phy siso from mesh
+ tx_phy_siso_2arr => fn_tx_phy_siso_3arr(I),
-- Receive clock domain
rx_clk => clk,
- rx_phy_sosi_2arr => fn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
- rx_phy_siso_2arr => fn_rx_phy_siso_3arr(I), -- phy siso to mesh
- rx_usr_sosi_2arr => fn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to FN user
- rx_usr_siso_2arr => fn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from FN user
+ -- phy sosi from mesh
+ rx_phy_sosi_2arr => fn_rx_phy_sosi_3arr(I),
+ -- phy siso to mesh
+ rx_phy_siso_2arr => fn_rx_phy_siso_3arr(I),
+ -- user sosi from phy = sosi.valid result to FN user
+ rx_usr_sosi_2arr => fn_rx_usr_sosi_3arr(I),
+ -- user siso to phy = siso.ready driver from FN user
+ rx_usr_siso_2arr => fn_rx_usr_siso_3arr(I)
);
end generate;
@@ -366,21 +387,30 @@ begin
g_reorder => c_reorder
)
port map (
- chip_id => TO_UVEC(c_nof_node + I, c_chip_id_w), -- chip id 4, 5, 6, 7
+ -- chip id 4, 5, 6, 7
+ chip_id => TO_UVEC(c_nof_node + I, c_chip_id_w),
-- Transmit clock domain
tx_clk => clk,
- tx_usr_sosi_2arr => bn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from BN user
- tx_usr_siso_2arr => bn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to BN user
- tx_phy_sosi_2arr => bn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
- tx_phy_siso_2arr => bn_tx_phy_siso_3arr(I), -- phy siso from mesh
+ -- user sosi to phy = sosi.valid driver from BN user
+ tx_usr_sosi_2arr => bn_tx_usr_sosi_3arr(I),
+ -- user siso from phy = siso.ready result to BN user
+ tx_usr_siso_2arr => bn_tx_usr_siso_3arr(I),
+ -- phy sosi to mesh
+ tx_phy_sosi_2arr => bn_tx_phy_sosi_3arr(I),
+ -- phy siso from mesh
+ tx_phy_siso_2arr => bn_tx_phy_siso_3arr(I),
-- Receive clock domain
rx_clk => clk,
- rx_phy_sosi_2arr => bn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
- rx_phy_siso_2arr => bn_rx_phy_siso_3arr(I), -- phy siso to mesh
- rx_usr_sosi_2arr => bn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to BN user
- rx_usr_siso_2arr => bn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from BN user
+ -- phy sosi from mesh
+ rx_phy_sosi_2arr => bn_rx_phy_sosi_3arr(I),
+ -- phy siso to mesh
+ rx_phy_siso_2arr => bn_rx_phy_siso_3arr(I),
+ -- user sosi from phy = sosi.valid result to BN user
+ rx_usr_sosi_2arr => bn_rx_usr_sosi_3arr(I),
+ -- user siso to phy = siso.ready driver from BN user
+ rx_usr_siso_2arr => bn_rx_usr_siso_3arr(I)
);
end generate;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
index de88c784052fc566fbc1eb57b3421a3d233e5bdb..9affe64b7daf04237c354ea7bfdd2ae698b8e28a 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
@@ -28,21 +28,30 @@ entity tb_unb1_board_node_ctrl is
end tb_unb1_board_node_ctrl;
architecture tb of tb_unb1_board_node_ctrl is
- constant c_scale : natural := 100; -- scale to speed up simulation
+ -- scale to speed up simulation
+ constant c_scale : natural := 100;
- constant c_xo_clk_period : time := 1 us; -- 1 MHz XO, slow XO to speed up simulation
- constant c_sys_clk_period : time := c_xo_clk_period / 5; -- 5 MHz PLL output from XO reference
+ -- 1 MHz XO, slow XO to speed up simulation
+ constant c_xo_clk_period : time := 1 us;
+ -- 5 MHz PLL output from XO reference
+ constant c_sys_clk_period : time := c_xo_clk_period / 5;
constant c_sys_locked_time : time := 10 us;
- constant c_pulse_us : natural := 5; -- nof 5 MHz clk cycles to get us period
- constant c_pulse_ms : natural := 1000 / c_scale; -- nof pulse_us pulses to get ms period
- constant c_pulse_s : natural := 1000; -- nof pulse_ms pulses to get s period
+ -- nof 5 MHz clk cycles to get us period
+ constant c_pulse_us : natural := 5;
+ -- nof pulse_us pulses to get ms period
+ constant c_pulse_ms : natural := 1000 / c_scale;
+ -- nof pulse_ms pulses to get s period
+ constant c_pulse_s : natural := 1000;
- constant c_wdi_extend_w : natural := 14; -- extend wdi by about 2**(14-1)= 8 s (as defined by c_pulse_ms)
- constant c_wdi_period : time := 1000 ms; -- wdi toggle after c_wdi_period
+ -- extend wdi by about 2**(14-1)= 8 s (as defined by c_pulse_ms)
+ constant c_wdi_extend_w : natural := 14;
+ -- wdi toggle after c_wdi_period
+ constant c_wdi_period : time := 1000 ms;
-- Use c_sw_period=40000 ms to show that the c_wdi_extend_w=5 is not enough, the WD will kick in when the sw is off during reload
- constant c_sw_period : time := 40000 ms; -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
+ -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
+ constant c_sw_period : time := 40000 ms;
-- Use c_sw_period=10000 ms to show that the c_wdi_extend_w=5 is enough, the WD will not kick in when the sw is off during reload
--CONSTANT c_sw_period : TIME := 6000 ms; -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
@@ -70,10 +79,13 @@ begin
sys_clk <= not sys_clk after c_sys_clk_period / 2;
sys_locked <= '0', '1' after c_sys_locked_time;
- wdi <= not wdi after c_wdi_period / c_scale; -- wd interrupt
- sw <= not sw after c_sw_period / c_scale; -- sw active / reload
+ -- wd interrupt
+ wdi <= not wdi after c_wdi_period / c_scale;
+ -- sw active / reload
+ sw <= not sw after c_sw_period / c_scale;
- wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
+ -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
+ wdi_in <= wdi and sw;
dut : entity work.unb1_board_node_ctrl
generic map (
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
index 59579fcd400bcbb69b4f32f9db8e55211e2480ef..9624fca85e8dcf9caa4ac54ce58543dcb9b7c7fc 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
@@ -43,7 +43,8 @@ use work.tb_unb1_board_pkg.all;
entity unb1_board_back_model_sl is
port (
- backplane_in_serial_4arr : in t_unb1_board_back_sl_4arr; -- _4arr = (UNB 3,2,1,0)(BN 3,2,1,0)(phy bus 2,1,0)(tr lane 3,2,1,0)
+ -- _4arr = (UNB 3,2,1,0)(BN 3,2,1,0)(phy bus 2,1,0)(tr lane 3,2,1,0)
+ backplane_in_serial_4arr : in t_unb1_board_back_sl_4arr;
backplane_out_serial_4arr : out t_unb1_board_back_sl_4arr
);
end unb1_board_back_model_sl;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
index 6262f52ab7711cb61a488128ea3ad22a12e0dfe7..fc1778055ab585184e1b06cfd49dc16c00e25f5b 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
@@ -33,7 +33,8 @@ use work.tb_unb1_board_pkg.all;
entity unb1_board_back_model_sosi is
port (
- backplane_in_sosi_4arr : in t_unb1_board_back_sosi_4arr; -- _4arr = (UNB 3,2,1,0)(BN 3,2,1,0)(phy bus 2,1,0)(tr lane 3,2,1,0)
+ -- _4arr = (UNB 3,2,1,0)(BN 3,2,1,0)(phy bus 2,1,0)(tr lane 3,2,1,0)
+ backplane_in_sosi_4arr : in t_unb1_board_back_sosi_4arr;
backplane_out_sosi_4arr : out t_unb1_board_back_sosi_4arr
);
end unb1_board_back_model_sosi;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
index c186f45bb476e7f843cdff7ffbc25496406a61b1..8e43eef1a3039b3390ebd17b9c91b7e46acb5aa5 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
@@ -36,7 +36,8 @@ entity unb1_board_mesh_model_siso is
);
port (
-- FN to BN
- fn0_rx_siso_2arr : in t_unb1_board_mesh_siso_2arr := (others => (others => c_dp_siso_rst)); -- _2arr = (node id 3,2,1,0)(tr lane 3,2,1,0)
+ -- _2arr = (node id 3,2,1,0)(tr lane 3,2,1,0)
+ fn0_rx_siso_2arr : in t_unb1_board_mesh_siso_2arr := (others => (others => c_dp_siso_rst));
fn1_rx_siso_2arr : in t_unb1_board_mesh_siso_2arr := (others => (others => c_dp_siso_rst));
fn2_rx_siso_2arr : in t_unb1_board_mesh_siso_2arr := (others => (others => c_dp_siso_rst));
fn3_rx_siso_2arr : in t_unb1_board_mesh_siso_2arr := (others => (others => c_dp_siso_rst));
@@ -109,46 +110,78 @@ begin
-- Actual UniBoard PCB mesh connect for transpose
gen_reorder : if g_reorder = true generate
-- BN, phy <= FN, phy
- bn0_tx_siso_2arr(0) <= fn3_rx_siso_2arr(1); -- 0,0 <= 3,1
- bn0_tx_siso_2arr(1) <= fn2_rx_siso_2arr(0); -- 0,1 <= 2,0
- bn0_tx_siso_2arr(2) <= fn1_rx_siso_2arr(0); -- 0,2 <= 1,0
- bn0_tx_siso_2arr(3) <= fn0_rx_siso_2arr(0); -- 0,3 <= 0,0
-
- bn1_tx_siso_2arr(0) <= fn3_rx_siso_2arr(0); -- 1,0 <= 3,0
- bn1_tx_siso_2arr(1) <= fn2_rx_siso_2arr(1); -- 1,1 <= 2,1
- bn1_tx_siso_2arr(2) <= fn1_rx_siso_2arr(1); -- 1,2 <= 1,1
- bn1_tx_siso_2arr(3) <= fn0_rx_siso_2arr(3); -- 1,3 <= 0,3
-
- bn2_tx_siso_2arr(0) <= fn3_rx_siso_2arr(2); -- 2,0 <= 3,2
- bn2_tx_siso_2arr(1) <= fn2_rx_siso_2arr(2); -- 2,1 <= 2,2
- bn2_tx_siso_2arr(2) <= fn0_rx_siso_2arr(2); -- 2,2 <= 0,2
- bn2_tx_siso_2arr(3) <= fn1_rx_siso_2arr(3); -- 2,3 <= 1,3
-
- bn3_tx_siso_2arr(0) <= fn3_rx_siso_2arr(3); -- 3,0 <= 3,3
- bn3_tx_siso_2arr(1) <= fn0_rx_siso_2arr(1); -- 3,1 <= 0,1
- bn3_tx_siso_2arr(2) <= fn2_rx_siso_2arr(3); -- 3,2 <= 2,3
- bn3_tx_siso_2arr(3) <= fn1_rx_siso_2arr(2); -- 3,3 <= 1,2
+ -- 0,0 <= 3,1
+ bn0_tx_siso_2arr(0) <= fn3_rx_siso_2arr(1);
+ -- 0,1 <= 2,0
+ bn0_tx_siso_2arr(1) <= fn2_rx_siso_2arr(0);
+ -- 0,2 <= 1,0
+ bn0_tx_siso_2arr(2) <= fn1_rx_siso_2arr(0);
+ -- 0,3 <= 0,0
+ bn0_tx_siso_2arr(3) <= fn0_rx_siso_2arr(0);
+
+ -- 1,0 <= 3,0
+ bn1_tx_siso_2arr(0) <= fn3_rx_siso_2arr(0);
+ -- 1,1 <= 2,1
+ bn1_tx_siso_2arr(1) <= fn2_rx_siso_2arr(1);
+ -- 1,2 <= 1,1
+ bn1_tx_siso_2arr(2) <= fn1_rx_siso_2arr(1);
+ -- 1,3 <= 0,3
+ bn1_tx_siso_2arr(3) <= fn0_rx_siso_2arr(3);
+
+ -- 2,0 <= 3,2
+ bn2_tx_siso_2arr(0) <= fn3_rx_siso_2arr(2);
+ -- 2,1 <= 2,2
+ bn2_tx_siso_2arr(1) <= fn2_rx_siso_2arr(2);
+ -- 2,2 <= 0,2
+ bn2_tx_siso_2arr(2) <= fn0_rx_siso_2arr(2);
+ -- 2,3 <= 1,3
+ bn2_tx_siso_2arr(3) <= fn1_rx_siso_2arr(3);
+
+ -- 3,0 <= 3,3
+ bn3_tx_siso_2arr(0) <= fn3_rx_siso_2arr(3);
+ -- 3,1 <= 0,1
+ bn3_tx_siso_2arr(1) <= fn0_rx_siso_2arr(1);
+ -- 3,2 <= 2,3
+ bn3_tx_siso_2arr(2) <= fn2_rx_siso_2arr(3);
+ -- 3,3 <= 1,2
+ bn3_tx_siso_2arr(3) <= fn1_rx_siso_2arr(2);
-- FN, phy <= BN, phy
- fn0_tx_siso_2arr(0) <= bn0_rx_siso_2arr(3); -- 0,0 <= 0,3
- fn0_tx_siso_2arr(1) <= bn3_rx_siso_2arr(1); -- 0,1 <= 3,1
- fn0_tx_siso_2arr(2) <= bn2_rx_siso_2arr(2); -- 0,2 <= 2,2
- fn0_tx_siso_2arr(3) <= bn1_rx_siso_2arr(3); -- 0,3 <= 1,3
-
- fn1_tx_siso_2arr(0) <= bn0_rx_siso_2arr(2); -- 1,0 <= 0,2
- fn1_tx_siso_2arr(1) <= bn1_rx_siso_2arr(2); -- 1,1 <= 1,2
- fn1_tx_siso_2arr(2) <= bn3_rx_siso_2arr(3); -- 1,2 <= 3,3
- fn1_tx_siso_2arr(3) <= bn2_rx_siso_2arr(3); -- 1,3 <= 2,3
-
- fn2_tx_siso_2arr(0) <= bn0_rx_siso_2arr(1); -- 2,0 <= 0,1
- fn2_tx_siso_2arr(1) <= bn1_rx_siso_2arr(1); -- 2,1 <= 1,1
- fn2_tx_siso_2arr(2) <= bn2_rx_siso_2arr(1); -- 2,2 <= 2,1
- fn2_tx_siso_2arr(3) <= bn3_rx_siso_2arr(2); -- 2,3 <= 3,2
-
- fn3_tx_siso_2arr(0) <= bn1_rx_siso_2arr(0); -- 3,0 <= 1,0
- fn3_tx_siso_2arr(1) <= bn0_rx_siso_2arr(0); -- 3,1 <= 0,0
- fn3_tx_siso_2arr(2) <= bn2_rx_siso_2arr(0); -- 3,2 <= 2,0
- fn3_tx_siso_2arr(3) <= bn3_rx_siso_2arr(0); -- 3,3 <= 3,0
+ -- 0,0 <= 0,3
+ fn0_tx_siso_2arr(0) <= bn0_rx_siso_2arr(3);
+ -- 0,1 <= 3,1
+ fn0_tx_siso_2arr(1) <= bn3_rx_siso_2arr(1);
+ -- 0,2 <= 2,2
+ fn0_tx_siso_2arr(2) <= bn2_rx_siso_2arr(2);
+ -- 0,3 <= 1,3
+ fn0_tx_siso_2arr(3) <= bn1_rx_siso_2arr(3);
+
+ -- 1,0 <= 0,2
+ fn1_tx_siso_2arr(0) <= bn0_rx_siso_2arr(2);
+ -- 1,1 <= 1,2
+ fn1_tx_siso_2arr(1) <= bn1_rx_siso_2arr(2);
+ -- 1,2 <= 3,3
+ fn1_tx_siso_2arr(2) <= bn3_rx_siso_2arr(3);
+ -- 1,3 <= 2,3
+ fn1_tx_siso_2arr(3) <= bn2_rx_siso_2arr(3);
+
+ -- 2,0 <= 0,1
+ fn2_tx_siso_2arr(0) <= bn0_rx_siso_2arr(1);
+ -- 2,1 <= 1,1
+ fn2_tx_siso_2arr(1) <= bn1_rx_siso_2arr(1);
+ -- 2,2 <= 2,1
+ fn2_tx_siso_2arr(2) <= bn2_rx_siso_2arr(1);
+ -- 2,3 <= 3,2
+ fn2_tx_siso_2arr(3) <= bn3_rx_siso_2arr(2);
+
+ -- 3,0 <= 1,0
+ fn3_tx_siso_2arr(0) <= bn1_rx_siso_2arr(0);
+ -- 3,1 <= 0,0
+ fn3_tx_siso_2arr(1) <= bn0_rx_siso_2arr(0);
+ -- 3,2 <= 2,0
+ fn3_tx_siso_2arr(2) <= bn2_rx_siso_2arr(0);
+ -- 3,3 <= 3,0
+ fn3_tx_siso_2arr(3) <= bn3_rx_siso_2arr(0);
end generate;
end beh;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
index 11019e63c4c6db0e5fa6280786b6ca49c7c64b18..d5caf55ac257220a09185889b3ad2b51ee334581 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
@@ -38,7 +38,8 @@ entity unb1_board_mesh_model_sl is
);
port (
-- FN to BN
- fn_tx_sl_3arr : in t_unb1_board_mesh_sl_3arr := (others => (others => (others => '0'))); -- _3arr = (node id 3,2,1,0)(bus id 3,2,1,0)(tr lane 3,2,1,0)
+ -- _3arr = (node id 3,2,1,0)(bus id 3,2,1,0)(tr lane 3,2,1,0)
+ fn_tx_sl_3arr : in t_unb1_board_mesh_sl_3arr := (others => (others => (others => '0')));
bn_rx_sl_3arr : out t_unb1_board_mesh_sl_3arr;
-- BN to FN
@@ -64,46 +65,78 @@ begin
-- Actual UniBoard PCB mesh connect for transpose
gen_reorder : if g_reorder = true generate
-- BN, phy <= FN, phy
- bn_rx_sl_3arr(0)(0) <= fn_tx_sl_3arr(3)(1); -- 0,0 <= 3,1
- bn_rx_sl_3arr(0)(1) <= fn_tx_sl_3arr(2)(0); -- 0,1 <= 2,0
- bn_rx_sl_3arr(0)(2) <= fn_tx_sl_3arr(1)(0); -- 0,2 <= 1,0
- bn_rx_sl_3arr(0)(3) <= fn_tx_sl_3arr(0)(0); -- 0,3 <= 0,0
+ -- 0,0 <= 3,1
+ bn_rx_sl_3arr(0)(0) <= fn_tx_sl_3arr(3)(1);
+ -- 0,1 <= 2,0
+ bn_rx_sl_3arr(0)(1) <= fn_tx_sl_3arr(2)(0);
+ -- 0,2 <= 1,0
+ bn_rx_sl_3arr(0)(2) <= fn_tx_sl_3arr(1)(0);
+ -- 0,3 <= 0,0
+ bn_rx_sl_3arr(0)(3) <= fn_tx_sl_3arr(0)(0);
- bn_rx_sl_3arr(1)(0) <= fn_tx_sl_3arr(3)(0); -- 1,0 <= 3,0
- bn_rx_sl_3arr(1)(1) <= fn_tx_sl_3arr(2)(1); -- 1,1 <= 2,1
- bn_rx_sl_3arr(1)(2) <= fn_tx_sl_3arr(1)(1); -- 1,2 <= 1,1
- bn_rx_sl_3arr(1)(3) <= fn_tx_sl_3arr(0)(3); -- 1,3 <= 0,3
+ -- 1,0 <= 3,0
+ bn_rx_sl_3arr(1)(0) <= fn_tx_sl_3arr(3)(0);
+ -- 1,1 <= 2,1
+ bn_rx_sl_3arr(1)(1) <= fn_tx_sl_3arr(2)(1);
+ -- 1,2 <= 1,1
+ bn_rx_sl_3arr(1)(2) <= fn_tx_sl_3arr(1)(1);
+ -- 1,3 <= 0,3
+ bn_rx_sl_3arr(1)(3) <= fn_tx_sl_3arr(0)(3);
- bn_rx_sl_3arr(2)(0) <= fn_tx_sl_3arr(3)(2); -- 2,0 <= 3,2
- bn_rx_sl_3arr(2)(1) <= fn_tx_sl_3arr(2)(2); -- 2,1 <= 2,2
- bn_rx_sl_3arr(2)(2) <= fn_tx_sl_3arr(0)(2); -- 2,2 <= 0,2
- bn_rx_sl_3arr(2)(3) <= fn_tx_sl_3arr(1)(3); -- 2,3 <= 1,3
+ -- 2,0 <= 3,2
+ bn_rx_sl_3arr(2)(0) <= fn_tx_sl_3arr(3)(2);
+ -- 2,1 <= 2,2
+ bn_rx_sl_3arr(2)(1) <= fn_tx_sl_3arr(2)(2);
+ -- 2,2 <= 0,2
+ bn_rx_sl_3arr(2)(2) <= fn_tx_sl_3arr(0)(2);
+ -- 2,3 <= 1,3
+ bn_rx_sl_3arr(2)(3) <= fn_tx_sl_3arr(1)(3);
- bn_rx_sl_3arr(3)(0) <= fn_tx_sl_3arr(3)(3); -- 3,0 <= 3,3
- bn_rx_sl_3arr(3)(1) <= fn_tx_sl_3arr(0)(1); -- 3,1 <= 0,1
- bn_rx_sl_3arr(3)(2) <= fn_tx_sl_3arr(2)(3); -- 3,2 <= 2,3
- bn_rx_sl_3arr(3)(3) <= fn_tx_sl_3arr(1)(2); -- 3,3 <= 1,2
+ -- 3,0 <= 3,3
+ bn_rx_sl_3arr(3)(0) <= fn_tx_sl_3arr(3)(3);
+ -- 3,1 <= 0,1
+ bn_rx_sl_3arr(3)(1) <= fn_tx_sl_3arr(0)(1);
+ -- 3,2 <= 2,3
+ bn_rx_sl_3arr(3)(2) <= fn_tx_sl_3arr(2)(3);
+ -- 3,3 <= 1,2
+ bn_rx_sl_3arr(3)(3) <= fn_tx_sl_3arr(1)(2);
-- FN, phy <= BN, phy
- fn_rx_sl_3arr(0)(0) <= bn_tx_sl_3arr(0)(3); -- 0,0 <= 0,3
- fn_rx_sl_3arr(0)(1) <= bn_tx_sl_3arr(3)(1); -- 0,1 <= 3,1
- fn_rx_sl_3arr(0)(2) <= bn_tx_sl_3arr(2)(2); -- 0,2 <= 2,2
- fn_rx_sl_3arr(0)(3) <= bn_tx_sl_3arr(1)(3); -- 0,3 <= 1,3
+ -- 0,0 <= 0,3
+ fn_rx_sl_3arr(0)(0) <= bn_tx_sl_3arr(0)(3);
+ -- 0,1 <= 3,1
+ fn_rx_sl_3arr(0)(1) <= bn_tx_sl_3arr(3)(1);
+ -- 0,2 <= 2,2
+ fn_rx_sl_3arr(0)(2) <= bn_tx_sl_3arr(2)(2);
+ -- 0,3 <= 1,3
+ fn_rx_sl_3arr(0)(3) <= bn_tx_sl_3arr(1)(3);
- fn_rx_sl_3arr(1)(0) <= bn_tx_sl_3arr(0)(2); -- 1,0 <= 0,2
- fn_rx_sl_3arr(1)(1) <= bn_tx_sl_3arr(1)(2); -- 1,1 <= 1,2
- fn_rx_sl_3arr(1)(2) <= bn_tx_sl_3arr(3)(3); -- 1,2 <= 3,3
- fn_rx_sl_3arr(1)(3) <= bn_tx_sl_3arr(2)(3); -- 1,3 <= 2,3
+ -- 1,0 <= 0,2
+ fn_rx_sl_3arr(1)(0) <= bn_tx_sl_3arr(0)(2);
+ -- 1,1 <= 1,2
+ fn_rx_sl_3arr(1)(1) <= bn_tx_sl_3arr(1)(2);
+ -- 1,2 <= 3,3
+ fn_rx_sl_3arr(1)(2) <= bn_tx_sl_3arr(3)(3);
+ -- 1,3 <= 2,3
+ fn_rx_sl_3arr(1)(3) <= bn_tx_sl_3arr(2)(3);
- fn_rx_sl_3arr(2)(0) <= bn_tx_sl_3arr(0)(1); -- 2,0 <= 0,1
- fn_rx_sl_3arr(2)(1) <= bn_tx_sl_3arr(1)(1); -- 2,1 <= 1,1
- fn_rx_sl_3arr(2)(2) <= bn_tx_sl_3arr(2)(1); -- 2,2 <= 2,1
- fn_rx_sl_3arr(2)(3) <= bn_tx_sl_3arr(3)(2); -- 2,3 <= 3,2
+ -- 2,0 <= 0,1
+ fn_rx_sl_3arr(2)(0) <= bn_tx_sl_3arr(0)(1);
+ -- 2,1 <= 1,1
+ fn_rx_sl_3arr(2)(1) <= bn_tx_sl_3arr(1)(1);
+ -- 2,2 <= 2,1
+ fn_rx_sl_3arr(2)(2) <= bn_tx_sl_3arr(2)(1);
+ -- 2,3 <= 3,2
+ fn_rx_sl_3arr(2)(3) <= bn_tx_sl_3arr(3)(2);
- fn_rx_sl_3arr(3)(0) <= bn_tx_sl_3arr(1)(0); -- 3,0 <= 1,0
- fn_rx_sl_3arr(3)(1) <= bn_tx_sl_3arr(0)(0); -- 3,1 <= 0,0
- fn_rx_sl_3arr(3)(2) <= bn_tx_sl_3arr(2)(0); -- 3,2 <= 2,0
- fn_rx_sl_3arr(3)(3) <= bn_tx_sl_3arr(3)(0); -- 3,3 <= 3,0
+ -- 3,0 <= 1,0
+ fn_rx_sl_3arr(3)(0) <= bn_tx_sl_3arr(1)(0);
+ -- 3,1 <= 0,0
+ fn_rx_sl_3arr(3)(1) <= bn_tx_sl_3arr(0)(0);
+ -- 3,2 <= 2,0
+ fn_rx_sl_3arr(3)(2) <= bn_tx_sl_3arr(2)(0);
+ -- 3,3 <= 3,0
+ fn_rx_sl_3arr(3)(3) <= bn_tx_sl_3arr(3)(0);
end generate;
end beh;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
index 17a37b3c881936f1a33457affc22e200b3e28df2..776dfb9644b0d71d656c2a57792e3695064b599f 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
@@ -36,7 +36,8 @@ entity unb1_board_mesh_model_sosi is
);
port (
-- FN to BN
- fn0_tx_sosi_2arr : in t_unb1_board_mesh_sosi_2arr := (others => (others => c_dp_sosi_rst)); -- _2arr = (node id 3,2,1,0)(tr lane 3,2,1,0)
+ -- _2arr = (node id 3,2,1,0)(tr lane 3,2,1,0)
+ fn0_tx_sosi_2arr : in t_unb1_board_mesh_sosi_2arr := (others => (others => c_dp_sosi_rst));
fn1_tx_sosi_2arr : in t_unb1_board_mesh_sosi_2arr := (others => (others => c_dp_sosi_rst));
fn2_tx_sosi_2arr : in t_unb1_board_mesh_sosi_2arr := (others => (others => c_dp_sosi_rst));
fn3_tx_sosi_2arr : in t_unb1_board_mesh_sosi_2arr := (others => (others => c_dp_sosi_rst));
@@ -109,46 +110,78 @@ begin
-- Actual UniBoard PCB mesh connect for transpose
gen_reorder : if g_reorder = true generate
-- BN, phy <= FN, phy
- bn0_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(1); -- 0,0 <= 3,1
- bn0_rx_sosi_2arr(1) <= fn2_tx_sosi_2arr(0); -- 0,1 <= 2,0
- bn0_rx_sosi_2arr(2) <= fn1_tx_sosi_2arr(0); -- 0,2 <= 1,0
- bn0_rx_sosi_2arr(3) <= fn0_tx_sosi_2arr(0); -- 0,3 <= 0,0
-
- bn1_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(0); -- 1,0 <= 3,0
- bn1_rx_sosi_2arr(1) <= fn2_tx_sosi_2arr(1); -- 1,1 <= 2,1
- bn1_rx_sosi_2arr(2) <= fn1_tx_sosi_2arr(1); -- 1,2 <= 1,1
- bn1_rx_sosi_2arr(3) <= fn0_tx_sosi_2arr(3); -- 1,3 <= 0,3
-
- bn2_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(2); -- 2,0 <= 3,2
- bn2_rx_sosi_2arr(1) <= fn2_tx_sosi_2arr(2); -- 2,1 <= 2,2
- bn2_rx_sosi_2arr(2) <= fn0_tx_sosi_2arr(2); -- 2,2 <= 0,2
- bn2_rx_sosi_2arr(3) <= fn1_tx_sosi_2arr(3); -- 2,3 <= 1,3
-
- bn3_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(3); -- 3,0 <= 3,3
- bn3_rx_sosi_2arr(1) <= fn0_tx_sosi_2arr(1); -- 3,1 <= 0,1
- bn3_rx_sosi_2arr(2) <= fn2_tx_sosi_2arr(3); -- 3,2 <= 2,3
- bn3_rx_sosi_2arr(3) <= fn1_tx_sosi_2arr(2); -- 3,3 <= 1,2
+ -- 0,0 <= 3,1
+ bn0_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(1);
+ -- 0,1 <= 2,0
+ bn0_rx_sosi_2arr(1) <= fn2_tx_sosi_2arr(0);
+ -- 0,2 <= 1,0
+ bn0_rx_sosi_2arr(2) <= fn1_tx_sosi_2arr(0);
+ -- 0,3 <= 0,0
+ bn0_rx_sosi_2arr(3) <= fn0_tx_sosi_2arr(0);
+
+ -- 1,0 <= 3,0
+ bn1_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(0);
+ -- 1,1 <= 2,1
+ bn1_rx_sosi_2arr(1) <= fn2_tx_sosi_2arr(1);
+ -- 1,2 <= 1,1
+ bn1_rx_sosi_2arr(2) <= fn1_tx_sosi_2arr(1);
+ -- 1,3 <= 0,3
+ bn1_rx_sosi_2arr(3) <= fn0_tx_sosi_2arr(3);
+
+ -- 2,0 <= 3,2
+ bn2_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(2);
+ -- 2,1 <= 2,2
+ bn2_rx_sosi_2arr(1) <= fn2_tx_sosi_2arr(2);
+ -- 2,2 <= 0,2
+ bn2_rx_sosi_2arr(2) <= fn0_tx_sosi_2arr(2);
+ -- 2,3 <= 1,3
+ bn2_rx_sosi_2arr(3) <= fn1_tx_sosi_2arr(3);
+
+ -- 3,0 <= 3,3
+ bn3_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(3);
+ -- 3,1 <= 0,1
+ bn3_rx_sosi_2arr(1) <= fn0_tx_sosi_2arr(1);
+ -- 3,2 <= 2,3
+ bn3_rx_sosi_2arr(2) <= fn2_tx_sosi_2arr(3);
+ -- 3,3 <= 1,2
+ bn3_rx_sosi_2arr(3) <= fn1_tx_sosi_2arr(2);
-- FN, phy <= BN, phy
- fn0_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(3); -- 0,0 <= 0,3
- fn0_rx_sosi_2arr(1) <= bn3_tx_sosi_2arr(1); -- 0,1 <= 3,1
- fn0_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(2); -- 0,2 <= 2,2
- fn0_rx_sosi_2arr(3) <= bn1_tx_sosi_2arr(3); -- 0,3 <= 1,3
-
- fn1_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(2); -- 1,0 <= 0,2
- fn1_rx_sosi_2arr(1) <= bn1_tx_sosi_2arr(2); -- 1,1 <= 1,2
- fn1_rx_sosi_2arr(2) <= bn3_tx_sosi_2arr(3); -- 1,2 <= 3,3
- fn1_rx_sosi_2arr(3) <= bn2_tx_sosi_2arr(3); -- 1,3 <= 2,3
-
- fn2_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(1); -- 2,0 <= 0,1
- fn2_rx_sosi_2arr(1) <= bn1_tx_sosi_2arr(1); -- 2,1 <= 1,1
- fn2_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(1); -- 2,2 <= 2,1
- fn2_rx_sosi_2arr(3) <= bn3_tx_sosi_2arr(2); -- 2,3 <= 3,2
-
- fn3_rx_sosi_2arr(0) <= bn1_tx_sosi_2arr(0); -- 3,0 <= 1,0
- fn3_rx_sosi_2arr(1) <= bn0_tx_sosi_2arr(0); -- 3,1 <= 0,0
- fn3_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(0); -- 3,2 <= 2,0
- fn3_rx_sosi_2arr(3) <= bn3_tx_sosi_2arr(0); -- 3,3 <= 3,0
+ -- 0,0 <= 0,3
+ fn0_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(3);
+ -- 0,1 <= 3,1
+ fn0_rx_sosi_2arr(1) <= bn3_tx_sosi_2arr(1);
+ -- 0,2 <= 2,2
+ fn0_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(2);
+ -- 0,3 <= 1,3
+ fn0_rx_sosi_2arr(3) <= bn1_tx_sosi_2arr(3);
+
+ -- 1,0 <= 0,2
+ fn1_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(2);
+ -- 1,1 <= 1,2
+ fn1_rx_sosi_2arr(1) <= bn1_tx_sosi_2arr(2);
+ -- 1,2 <= 3,3
+ fn1_rx_sosi_2arr(2) <= bn3_tx_sosi_2arr(3);
+ -- 1,3 <= 2,3
+ fn1_rx_sosi_2arr(3) <= bn2_tx_sosi_2arr(3);
+
+ -- 2,0 <= 0,1
+ fn2_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(1);
+ -- 2,1 <= 1,1
+ fn2_rx_sosi_2arr(1) <= bn1_tx_sosi_2arr(1);
+ -- 2,2 <= 2,1
+ fn2_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(1);
+ -- 2,3 <= 3,2
+ fn2_rx_sosi_2arr(3) <= bn3_tx_sosi_2arr(2);
+
+ -- 3,0 <= 1,0
+ fn3_rx_sosi_2arr(0) <= bn1_tx_sosi_2arr(0);
+ -- 3,1 <= 0,0
+ fn3_rx_sosi_2arr(1) <= bn0_tx_sosi_2arr(0);
+ -- 3,2 <= 2,0
+ fn3_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(0);
+ -- 3,3 <= 3,0
+ fn3_rx_sosi_2arr(3) <= bn3_tx_sosi_2arr(0);
end generate;
end beh;
diff --git a/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd b/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
index ebe9c5d3e787e0ac953101ca9ea487f6c94d337b..3619e7ca9e8b668d90cbaad270aeb36fbc7cddc5 100644
--- a/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
+++ b/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
@@ -33,16 +33,21 @@ entity unb2_led is
g_design_name : string := "unb2_led";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0; -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0;
g_factory_image : boolean := true
);
port (
- ETH_CLK : in std_logic; -- 125 MHz
+ -- 125 MHz
+ ETH_CLK : in std_logic;
TESTIO : inout std_logic_vector(c_unb2_board_aux.testio_w - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2_board_tr_qsfp_nof_leds - 1 downto 0)
);
@@ -51,7 +56,8 @@ end unb2_led;
architecture str of unb2_led is
-- Firmware version x.y
constant c_fw_version : t_unb2_board_fw_version := (1, 1);
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
constant c_mm_clk_freq : natural := c_unb2_board_mm_clk_freq_50M;
-- System
@@ -96,15 +102,18 @@ begin
-- xo_ethclk = ETH_CLK
-----------------------------------------------------------------------------
- i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
+ -- use the ETH_CLK pin as xo_clk
+ i_xo_ethclk <= ETH_CLK;
u_common_areset_xo : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => i_xo_ethclk,
out_rst => i_xo_rst
);
@@ -118,7 +127,8 @@ begin
i_mm_clk <= clk50;
gen_mm_clk_sim: if g_sim = true generate
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ -- 50 MHz, 20ns/2
+ clk50 <= not clk50 after 10 ns;
mm_locked <= '0', '1' after 70 ns;
end generate;
@@ -138,7 +148,8 @@ begin
u_unb2_board_node_ctrl : entity unb2_board_lib.unb2_board_node_ctrl
generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us => c_mm_clk_freq / (10**6)
)
port map (
-- MM clock domain reset
@@ -150,7 +161,8 @@ begin
-- Pulses
mm_pulse_us => OPEN,
mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
+ -- could be used to toggle a LED
+ mm_pulse_s => mm_pulse_s
);
------------------------------------------------------------------------------
@@ -161,7 +173,8 @@ begin
u_extend : common_lib.common_pulse_extend
generic map (
- g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
+ -- (2^22) / 50e6 = 0.083886 th of 1 sec
+ g_extend_w => 22
)
port map (
rst => i_mm_rst,
@@ -191,7 +204,8 @@ begin
u_extend_10Hz : common_lib.common_pulse_extend
generic map (
- g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
+ -- (2^21) / 50e6 = 0.041943 th of 1 sec
+ g_extend_w => 21
)
port map (
rst => i_mm_rst,
diff --git a/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd b/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
index 71ff33a36be4bde8faadd07cc53b7d83f610e40f..4dd614884490ed0d678df012eb28b672d75e62f6 100644
--- a/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
+++ b/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
@@ -48,18 +48,23 @@ use common_lib.tb_common_pkg.all;
entity tb_unb2_led is
generic (
g_design_name : string := "unb2_led";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Node 3
+ g_sim_node_nr : natural := 3
);
end tb_unb2_led;
architecture tb of tb_unb2_led is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
-- DUT
signal eth_clk : std_logic := '0';
@@ -69,7 +74,8 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
------------------------------------------------------------------------------
-- DUT
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
index 2bd1ab97d597736b53b76506cb5b59a2d9c06e35..ef72bb66da23d9c545c573c3d17a664120c3e650 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
@@ -32,7 +32,8 @@ use work.qsys_unb2_minimal_pkg.all;
entity mmm_unb2_minimal is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
index 305c225eae2455dcf6574d3992aa4340e2dfd4fe..0064c528852f6894e37f50ecb19c9bb8a19e7512 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
@@ -29,126 +29,246 @@ package qsys_unb2_minimal_pkg is
component qsys_unb2_minimal is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(4 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic
);
end component qsys_unb2_minimal;
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
index c0ae33a4c217ae760f46c77bea8ca1b18d5a84e8..d4d27ca7945fa73a23a7ad833db4020b4608e479 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
@@ -33,21 +33,30 @@ entity unb2_minimal is
g_design_name : string := "unb2_minimal";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0; -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0;
g_factory_image : boolean := true
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -120,12 +129,16 @@ architecture str of unb2_minimal is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
diff --git a/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
index 5f1ebd006c75218dd65ffee60766d2b82c741210..2321f5b2b92f539369a6ec187f76340483667d79 100644
--- a/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
@@ -52,23 +52,28 @@ use common_lib.tb_common_pkg.all;
entity tb_unb2_minimal is
generic (
g_design_name : string := "unb2_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Node 3
+ g_sim_node_nr : natural := 3
);
end tb_unb2_minimal;
architecture tb of tb_unb2_minimal is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb2_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -99,31 +104,46 @@ architecture tb of tb_unb2_minimal is
signal qsfp_led : std_logic_vector(c_unb2_board_tr_qsfp_nof_leds - 1 downto 0);
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
-
- PMBUS_SC <= 'H'; -- pull up
- PMBUS_SD <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+
+ -- pull up
+ PMBUS_SC <= 'H';
+ -- pull up
+ PMBUS_SD <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
index 24a8174ff6cb64308949e445ebd127229d2e1b41..ad80870eaa432310a5a2ff859e42fd0faa6d405a 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
+++ b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
@@ -30,11 +30,16 @@ entity unb2_pinning is
port (
-- GENERAL
- CLK : in std_logic; -- External system clock
- PPS : in std_logic; -- External system sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- External system clock
+ CLK : in std_logic;
+ -- External system sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- 1GbE Control Interfaces
ETH_CLK : in std_logic;
@@ -42,9 +47,12 @@ entity unb2_pinning is
ETH_SGOUT : out std_logic_vector(1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic; -- SerDes reference clock front
- SB_CLK : in std_logic; -- SerDes reference clock back
- BCK_REF_CLK : in std_logic; -- SerDes reference clock back
+ -- SerDes reference clock front
+ SA_CLK : in std_logic;
+ -- SerDes reference clock back
+ SB_CLK : in std_logic;
+ -- SerDes reference clock back
+ BCK_REF_CLK : in std_logic;
-- SO-DIMM DDR4 Memory Bank i2c (common)
MB_SCL : inout std_logic;
@@ -52,7 +60,8 @@ entity unb2_pinning is
MB_EVENT : in std_logic;
-- SO-DIMM DDR4 Memory Bank I
MB_I_RZQ : in std_logic;
- MB_I_REF_CLK : in std_logic; -- External reference clock
+ -- External reference clock
+ MB_I_REF_CLK : in std_logic;
MB_I_A : out std_logic_vector(13 downto 0);
MB_I_ACT_N : out std_logic_vector(0 downto 0);
MB_I_BA : out std_logic_vector(1 downto 0);
@@ -63,7 +72,8 @@ entity unb2_pinning is
MB_I_CK_n : out std_logic_vector(1 downto 0);
MB_I_CKE : out std_logic_vector(1 downto 0);
MB_I_CS : out std_logic_vector(1 downto 0);
- MB_I_DM : inout std_logic_vector(8 downto 0); -- !! temporarily chg to inout
+ -- !! temporarily chg to inout
+ MB_I_DM : inout std_logic_vector(8 downto 0);
MB_I_DQ : inout std_logic_vector(63 downto 0);
MB_I_DQS : inout std_logic_vector(8 downto 0);
MB_I_DQS_n : inout std_logic_vector(8 downto 0);
@@ -75,7 +85,8 @@ entity unb2_pinning is
MB_I_ALERT_N : in std_logic_vector(0 downto 0);
-- SO-DIMM DDR4 Memory Bank II
MB_II_RZQ : in std_logic;
- MB_II_REF_CLK : in std_logic; -- External reference clock
+ -- External reference clock
+ MB_II_REF_CLK : in std_logic;
MB_II_A : out std_logic_vector(13 downto 0);
MB_II_ACT_N : out std_logic_vector(0 downto 0);
MB_II_BA : out std_logic_vector(1 downto 0);
@@ -86,7 +97,8 @@ entity unb2_pinning is
MB_II_CK_n : out std_logic_vector(1 downto 0);
MB_II_CKE : out std_logic_vector(1 downto 0);
MB_II_CS : out std_logic_vector(1 downto 0);
- MB_II_DM : inout std_logic_vector(8 downto 0); -- !! temporarily chg to inout
+ -- !! temporarily chg to inout
+ MB_II_DM : inout std_logic_vector(8 downto 0);
MB_II_DQ : inout std_logic_vector(63 downto 0);
MB_II_DQS : inout std_logic_vector(8 downto 0);
MB_II_DQS_n : inout std_logic_vector(8 downto 0);
@@ -143,243 +155,430 @@ end unb2_pinning;
architecture str of unb2_pinning is
component ddr4 is
port (
- global_reset_n : in std_logic := 'X'; -- reset_n
- pll_ref_clk : in std_logic := 'X'; -- clk
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_alert_n : in std_logic_vector(0 downto 0); -- mem_alert_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par ** new in 14.0 **
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic; -- local_cal_fail
- emif_usr_reset_n : out std_logic; -- reset_n
- emif_usr_clk : out std_logic; -- clk
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address ** chg from 23 bits in 14.0 **
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount ** chg from 8 bits in 14.0 **
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic -- readdatavalid
+ -- reset_n
+ global_reset_n : in std_logic := 'X';
+ -- clk
+ pll_ref_clk : in std_logic := 'X';
+ -- oct_rzqin
+ oct_rzqin : in std_logic := 'X';
+ -- mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0);
+ -- mem_par ** new in 14.0 **
+ mem_par : out std_logic_vector(0 downto 0);
+ -- mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X');
+ -- mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- local_cal_success
+ local_cal_success : out std_logic;
+ -- local_cal_fail
+ local_cal_fail : out std_logic;
+ -- reset_n
+ emif_usr_reset_n : out std_logic;
+ -- clk
+ emif_usr_clk : out std_logic;
+ -- waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- read
+ amm_read_0 : in std_logic := 'X';
+ -- write
+ amm_write_0 : in std_logic := 'X';
+ -- address ** chg from 23 bits in 14.0 **
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X');
+ -- readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X');
+ -- burstcount ** chg from 8 bits in 14.0 **
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X');
+ -- byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X');
+ -- readdatavalid
+ amm_readdatavalid_0 : out std_logic
);
end component ddr4;
component transceiver_phy is
port (
- tx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_analogreset
- tx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_digitalreset
- rx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_analogreset
- rx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_digitalreset
- tx_cal_busy : out std_logic_vector(47 downto 0); -- tx_cal_busy
- rx_cal_busy : out std_logic_vector(47 downto 0); -- rx_cal_busy
- rx_is_lockedtodata : out std_logic_vector(47 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
- rx_cdr_refclk0 : in std_logic := 'X'; -- clk
- tx_serial_data : out std_logic_vector(47 downto 0); -- tx_serial_data
- rx_serial_data : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_serial_data
- tx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
- rx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
- tx_clkout : out std_logic_vector(47 downto 0); -- clk
- rx_clkout : out std_logic_vector(47 downto 0); -- clk
- tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_enh_data_valid
- rx_enh_data_valid : out std_logic_vector(47 downto 0); -- rx_enh_data_valid
- rx_enh_blk_lock : out std_logic_vector(47 downto 0); -- rx_enh_blk_lock
- tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X'); -- tx_parallel_data
- tx_control : in std_logic_vector(383 downto 0) := (others => 'X'); -- tx_control
- tx_err_ins : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_err_ins
- unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X'); -- unused_tx_parallel_data
- unused_tx_control : in std_logic_vector(431 downto 0) := (others => 'X'); -- unused_tx_control
- rx_parallel_data : out std_logic_vector(3071 downto 0); -- rx_parallel_data
- rx_control : out std_logic_vector(383 downto 0); -- rx_control
- unused_rx_parallel_data : out std_logic_vector(3071 downto 0); -- unused_rx_parallel_data
- unused_rx_control : out std_logic_vector(575 downto 0) -- unused_rx_control
+ -- tx_analogreset
+ tx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X');
+ -- tx_digitalreset
+ tx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X');
+ -- rx_analogreset
+ rx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X');
+ -- rx_digitalreset
+ rx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X');
+ -- tx_cal_busy
+ tx_cal_busy : out std_logic_vector(47 downto 0);
+ -- rx_cal_busy
+ rx_cal_busy : out std_logic_vector(47 downto 0);
+ -- rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(47 downto 0) := (others => 'X');
+ -- clk
+ tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => 'X');
+ -- clk
+ rx_cdr_refclk0 : in std_logic := 'X';
+ -- tx_serial_data
+ tx_serial_data : out std_logic_vector(47 downto 0);
+ -- rx_serial_data
+ rx_serial_data : in std_logic_vector(47 downto 0) := (others => 'X');
+ -- clk
+ tx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X');
+ -- clk
+ rx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X');
+ -- clk
+ tx_clkout : out std_logic_vector(47 downto 0);
+ -- clk
+ rx_clkout : out std_logic_vector(47 downto 0);
+ -- tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => 'X');
+ -- rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(47 downto 0);
+ -- rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(47 downto 0);
+ -- tx_parallel_data
+ tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X');
+ -- tx_control
+ tx_control : in std_logic_vector(383 downto 0) := (others => 'X');
+ -- tx_err_ins
+ tx_err_ins : in std_logic_vector(47 downto 0) := (others => 'X');
+ -- unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X');
+ -- unused_tx_control
+ unused_tx_control : in std_logic_vector(431 downto 0) := (others => 'X');
+ -- rx_parallel_data
+ rx_parallel_data : out std_logic_vector(3071 downto 0);
+ -- rx_control
+ rx_control : out std_logic_vector(383 downto 0);
+ -- unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(3071 downto 0);
+ -- unused_rx_control
+ unused_rx_control : out std_logic_vector(575 downto 0)
);
end component transceiver_phy;
component transceiver_phy_24channel is
port (
- tx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_analogreset
- tx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_digitalreset
- rx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_analogreset
- rx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_digitalreset
- tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy
- rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy
- rx_is_lockedtodata : out std_logic_vector(23 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
- rx_cdr_refclk0 : in std_logic := 'X'; -- clk
- tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data
- rx_serial_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_serial_data
- tx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
- rx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
- tx_clkout : out std_logic_vector(23 downto 0); -- clk
- rx_clkout : out std_logic_vector(23 downto 0); -- clk
- tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_enh_data_valid
- rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid
- rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock
- tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X'); -- tx_parallel_data
- tx_control : in std_logic_vector(191 downto 0) := (others => 'X'); -- tx_control
- tx_err_ins : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_err_ins
- unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X'); -- unused_tx_parallel_data
- unused_tx_control : in std_logic_vector(215 downto 0) := (others => 'X'); -- unused_tx_control
- rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data
- rx_control : out std_logic_vector(191 downto 0); -- rx_control
- unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data
- unused_rx_control : out std_logic_vector(287 downto 0) -- unused_rx_control
+ -- tx_analogreset
+ tx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X');
+ -- tx_digitalreset
+ tx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X');
+ -- rx_analogreset
+ rx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X');
+ -- rx_digitalreset
+ rx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X');
+ -- tx_cal_busy
+ tx_cal_busy : out std_logic_vector(23 downto 0);
+ -- rx_cal_busy
+ rx_cal_busy : out std_logic_vector(23 downto 0);
+ -- rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(23 downto 0) := (others => 'X');
+ -- clk
+ tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => 'X');
+ -- clk
+ rx_cdr_refclk0 : in std_logic := 'X';
+ -- tx_serial_data
+ tx_serial_data : out std_logic_vector(23 downto 0);
+ -- rx_serial_data
+ rx_serial_data : in std_logic_vector(23 downto 0) := (others => 'X');
+ -- clk
+ tx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X');
+ -- clk
+ rx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X');
+ -- clk
+ tx_clkout : out std_logic_vector(23 downto 0);
+ -- clk
+ rx_clkout : out std_logic_vector(23 downto 0);
+ -- tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => 'X');
+ -- rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(23 downto 0);
+ -- rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(23 downto 0);
+ -- tx_parallel_data
+ tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X');
+ -- tx_control
+ tx_control : in std_logic_vector(191 downto 0) := (others => 'X');
+ -- tx_err_ins
+ tx_err_ins : in std_logic_vector(23 downto 0) := (others => 'X');
+ -- unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X');
+ -- unused_tx_control
+ unused_tx_control : in std_logic_vector(215 downto 0) := (others => 'X');
+ -- rx_parallel_data
+ rx_parallel_data : out std_logic_vector(1535 downto 0);
+ -- rx_control
+ rx_control : out std_logic_vector(191 downto 0);
+ -- unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(1535 downto 0);
+ -- unused_rx_control
+ unused_rx_control : out std_logic_vector(287 downto 0)
);
end component transceiver_phy_24channel;
component transceiver_reset_controller is
port (
- clock : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- tx_analogreset : out std_logic_vector(47 downto 0); -- tx_analogreset
- tx_digitalreset : out std_logic_vector(47 downto 0); -- tx_digitalreset
- tx_ready : out std_logic_vector(47 downto 0); -- tx_ready
- pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
- pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
- tx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_cal_busy
- rx_analogreset : out std_logic_vector(47 downto 0); -- rx_analogreset
- rx_digitalreset : out std_logic_vector(47 downto 0); -- rx_digitalreset
- rx_ready : out std_logic_vector(47 downto 0); -- rx_ready
- rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X') -- rx_cal_busy
+ -- clk
+ clock : in std_logic := 'X';
+ -- reset
+ reset : in std_logic := 'X';
+ -- pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- tx_analogreset
+ tx_analogreset : out std_logic_vector(47 downto 0);
+ -- tx_digitalreset
+ tx_digitalreset : out std_logic_vector(47 downto 0);
+ -- tx_ready
+ tx_ready : out std_logic_vector(47 downto 0);
+ -- pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- tx_cal_busy
+ tx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X');
+ -- rx_analogreset
+ rx_analogreset : out std_logic_vector(47 downto 0);
+ -- rx_digitalreset
+ rx_digitalreset : out std_logic_vector(47 downto 0);
+ -- rx_ready
+ rx_ready : out std_logic_vector(47 downto 0);
+ -- rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => 'X');
+ -- rx_cal_busy
+ rx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X')
);
end component transceiver_reset_controller;
component transceiver_reset_controller_24 is
port (
- clock : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset
- tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset
- tx_ready : out std_logic_vector(23 downto 0); -- tx_ready
- pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
- pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
- tx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_cal_busy
- rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset
- rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset
- rx_ready : out std_logic_vector(23 downto 0); -- rx_ready
- rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X') -- rx_cal_busy
+ -- clk
+ clock : in std_logic := 'X';
+ -- reset
+ reset : in std_logic := 'X';
+ -- pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- tx_analogreset
+ tx_analogreset : out std_logic_vector(23 downto 0);
+ -- tx_digitalreset
+ tx_digitalreset : out std_logic_vector(23 downto 0);
+ -- tx_ready
+ tx_ready : out std_logic_vector(23 downto 0);
+ -- pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- tx_cal_busy
+ tx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X');
+ -- rx_analogreset
+ rx_analogreset : out std_logic_vector(23 downto 0);
+ -- rx_digitalreset
+ rx_digitalreset : out std_logic_vector(23 downto 0);
+ -- rx_ready
+ rx_ready : out std_logic_vector(23 downto 0);
+ -- rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => 'X');
+ -- rx_cal_busy
+ rx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X')
);
end component transceiver_reset_controller_24;
component transceiver_pll is
port (
- pll_powerdown : in std_logic := 'X'; -- pll_powerdown
- pll_refclk0 : in std_logic := 'X'; -- clk
- pll_locked : out std_logic; -- pll_locked
- pll_cal_busy : out std_logic; -- pll_cal_busy
- mcgb_rst : in std_logic := 'X'; -- mcgb_rst
- mcgb_serial_clk : out std_logic -- clk
+ -- pll_powerdown
+ pll_powerdown : in std_logic := 'X';
+ -- clk
+ pll_refclk0 : in std_logic := 'X';
+ -- pll_locked
+ pll_locked : out std_logic;
+ -- pll_cal_busy
+ pll_cal_busy : out std_logic;
+ -- mcgb_rst
+ mcgb_rst : in std_logic := 'X';
+ -- clk
+ mcgb_serial_clk : out std_logic
);
end component transceiver_pll;
component sys_clkctrl is
port (
- inclk : in std_logic := 'X'; -- inclk
- outclk : out std_logic -- outclk
+ -- inclk
+ inclk : in std_logic := 'X';
+ -- outclk
+ outclk : out std_logic
);
end component sys_clkctrl;
component system_pll is
port (
- refclk : in std_logic := 'X'; -- clk
+ -- clk
+ refclk : in std_logic := 'X';
rst : in std_logic := 'X';
locked : out std_logic;
- outclk_0 : out std_logic; -- outclk0
- outclk_1 : out std_logic; -- outclk1
- outclk_2 : out std_logic -- outclk2
+ -- outclk0
+ outclk_0 : out std_logic;
+ -- outclk1
+ outclk_1 : out std_logic;
+ -- outclk2
+ outclk_2 : out std_logic
);
end component system_pll;
component system_fpll is
port (
- pll_refclk0 : in std_logic := 'X'; -- clk
+ -- clk
+ pll_refclk0 : in std_logic := 'X';
pll_powerdown : in std_logic := 'X';
pll_locked : out std_logic;
pll_cal_busy : out std_logic;
- outclk0 : out std_logic; -- outclk0
- outclk1 : out std_logic; -- outclk1
- outclk2 : out std_logic -- outclk2
+ -- outclk0
+ outclk0 : out std_logic;
+ -- outclk1
+ outclk1 : out std_logic;
+ -- outclk2
+ outclk2 : out std_logic
);
end component system_fpll;
component unb2_pinning_qsys is
port (
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- avs_i2c_master_0_gs_sim_export : in std_logic := 'X'; -- export
- avs_i2c_master_0_sync_export : in std_logic := 'X'; -- export
- avs_i2c_master_0_i2c_scl_export : inout std_logic := 'X'; -- export
- avs_i2c_master_0_i2c_sda_export : inout std_logic := 'X'; -- export
- avs_i2c_master_1_gs_sim_export : in std_logic := 'X'; -- export
- avs_i2c_master_1_sync_export : in std_logic := 'X'; -- export
- avs_i2c_master_1_i2c_scl_export : inout std_logic := 'X'; -- export
- avs_i2c_master_1_i2c_sda_export : inout std_logic := 'X'; -- export
- avs_i2c_master_11_i2c_sda_export : inout std_logic := 'X'; -- export
- avs_i2c_master_11_i2c_scl_export : inout std_logic := 'X'; -- export
- avs_i2c_master_11_sync_export : in std_logic := 'X'; -- export
- avs_i2c_master_11_gs_sim_export : in std_logic := 'X'; -- export
- avs_i2c_master_10_i2c_sda_export : inout std_logic := 'X'; -- export
- avs_i2c_master_10_i2c_scl_export : inout std_logic := 'X'; -- export
- avs_i2c_master_10_sync_export : in std_logic := 'X'; -- export
- avs_i2c_master_10_gs_sim_export : in std_logic := 'X'; -- export
- avs_i2c_master_9_i2c_sda_export : inout std_logic := 'X'; -- export
- avs_i2c_master_9_i2c_scl_export : inout std_logic := 'X'; -- export
- avs_i2c_master_9_sync_export : in std_logic := 'X'; -- export
- avs_i2c_master_9_gs_sim_export : in std_logic := 'X'; -- export
- avs_i2c_master_8_i2c_sda_export : inout std_logic := 'X'; -- export
- avs_i2c_master_8_sync_export : in std_logic := 'X'; -- export
- avs_i2c_master_8_gs_sim_export : in std_logic := 'X'; -- export
- avs_i2c_master_8_i2c_scl_export : inout std_logic := 'X'; -- export
- avs_i2c_master_7_i2c_sda_export : inout std_logic := 'X'; -- export
- avs_i2c_master_7_i2c_scl_export : inout std_logic := 'X'; -- export
- avs_i2c_master_7_sync_export : in std_logic := 'X'; -- export
- avs_i2c_master_7_gs_sim_export : in std_logic := 'X'; -- export
- avs_i2c_master_6_i2c_sda_export : inout std_logic := 'X'; -- export
- avs_i2c_master_6_i2c_scl_export : inout std_logic := 'X'; -- export
- avs_i2c_master_6_sync_export : in std_logic := 'X'; -- export
- avs_i2c_master_6_gs_sim_export : in std_logic := 'X'; -- export
- avs_i2c_master_5_i2c_sda_export : inout std_logic := 'X'; -- export
- avs_i2c_master_5_i2c_scl_export : inout std_logic := 'X'; -- export
- avs_i2c_master_5_sync_export : in std_logic := 'X'; -- export
- avs_i2c_master_5_gs_sim_export : in std_logic := 'X'; -- export
- avs_i2c_master_4_i2c_sda_export : inout std_logic := 'X'; -- export
- avs_i2c_master_4_sync_export : in std_logic := 'X'; -- export
- avs_i2c_master_4_gs_sim_export : in std_logic := 'X'; -- export
- avs_i2c_master_4_i2c_scl_export : inout std_logic := 'X'; -- export
- avs_i2c_master_3_gs_sim_export : in std_logic := 'X'; -- export
- avs_i2c_master_3_sync_export : in std_logic := 'X'; -- export
- avs_i2c_master_3_i2c_scl_export : inout std_logic := 'X'; -- export
- avs_i2c_master_3_i2c_sda_export : inout std_logic := 'X'; -- export
- avs_i2c_master_2_gs_sim_export : in std_logic := 'X'; -- export
- avs_i2c_master_2_sync_export : in std_logic := 'X'; -- export
- avs_i2c_master_2_i2c_scl_export : inout std_logic := 'X'; -- export
- avs_i2c_master_2_i2c_sda_export : inout std_logic := 'X'; -- export
- eth_tse_0_serial_connection_rxp_0 : in std_logic := 'X'; -- rxp
- eth_tse_0_serial_connection_txp_0 : out std_logic; -- txp
- eth_tse_0_pcs_ref_clk_clock_connection_clk : in std_logic := 'X'; -- clk
- eth_tse_1_pcs_ref_clk_clock_connection_clk : in std_logic := 'X'; -- clk
- eth_tse_1_serial_connection_rxp_0 : in std_logic := 'X'; -- rxp
- eth_tse_1_serial_connection_txp_0 : out std_logic; -- txp
- pio_0_external_connection_export : in std_logic_vector(11 downto 0) := (others => 'X') -- export
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ avs_i2c_master_0_gs_sim_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_0_sync_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_0_i2c_scl_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_0_i2c_sda_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_1_gs_sim_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_1_sync_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_1_i2c_scl_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_1_i2c_sda_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_11_i2c_sda_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_11_i2c_scl_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_11_sync_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_11_gs_sim_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_10_i2c_sda_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_10_i2c_scl_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_10_sync_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_10_gs_sim_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_9_i2c_sda_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_9_i2c_scl_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_9_sync_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_9_gs_sim_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_8_i2c_sda_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_8_sync_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_8_gs_sim_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_8_i2c_scl_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_7_i2c_sda_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_7_i2c_scl_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_7_sync_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_7_gs_sim_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_6_i2c_sda_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_6_i2c_scl_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_6_sync_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_6_gs_sim_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_5_i2c_sda_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_5_i2c_scl_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_5_sync_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_5_gs_sim_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_4_i2c_sda_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_4_sync_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_4_gs_sim_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_4_i2c_scl_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_3_gs_sim_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_3_sync_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_3_i2c_scl_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_3_i2c_sda_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_2_gs_sim_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_2_sync_export : in std_logic := 'X';
+ -- export
+ avs_i2c_master_2_i2c_scl_export : inout std_logic := 'X';
+ -- export
+ avs_i2c_master_2_i2c_sda_export : inout std_logic := 'X';
+ -- rxp
+ eth_tse_0_serial_connection_rxp_0 : in std_logic := 'X';
+ -- txp
+ eth_tse_0_serial_connection_txp_0 : out std_logic;
+ -- clk
+ eth_tse_0_pcs_ref_clk_clock_connection_clk : in std_logic := 'X';
+ -- clk
+ eth_tse_1_pcs_ref_clk_clock_connection_clk : in std_logic := 'X';
+ -- rxp
+ eth_tse_1_serial_connection_rxp_0 : in std_logic := 'X';
+ -- txp
+ eth_tse_1_serial_connection_txp_0 : out std_logic;
+ -- export
+ pio_0_external_connection_export : in std_logic_vector(11 downto 0) := (others => 'X')
);
end component unb2_pinning_qsys;
@@ -656,7 +855,8 @@ begin
rx_cdr_refclk0 => sa_clk,
tx_serial_data => tx_serial_data_front,
rx_serial_data => rx_serial_data_front,
- tx_coreclkin => tx_serdesclk_front, -- write side clock for tx fifo
+ -- write side clock for tx fifo
+ tx_coreclkin => tx_serdesclk_front,
rx_coreclkin => tx_serdesclk_front,
tx_clkout => tx_serdesclk_front,
rx_clkout => open,
@@ -665,7 +865,8 @@ begin
rx_enh_blk_lock => open,
tx_parallel_data => dataloopback_front,
tx_control => controlloopback_front,
- tx_err_ins => (others => '0'), -- use to insert sync errors
+ -- use to insert sync errors
+ tx_err_ins => (others => '0'),
unused_tx_parallel_data => (others => '0'),
unused_tx_control => (others => '0'),
rx_parallel_data => dataloopback_front,
@@ -729,7 +930,8 @@ begin
rx_cdr_refclk0 => sb_clk,
tx_serial_data => tx_serial_data_back(47 downto 24),
rx_serial_data => rx_serial_data_back(47 downto 24),
- tx_coreclkin => tx_serdesclk_back(47 downto 24), -- write side clock for tx fifo
+ -- write side clock for tx fifo
+ tx_coreclkin => tx_serdesclk_back(47 downto 24),
rx_coreclkin => tx_serdesclk_back(47 downto 24),
tx_clkout => tx_serdesclk_back(47 downto 24),
rx_clkout => open,
@@ -738,7 +940,8 @@ begin
rx_enh_blk_lock => open,
tx_parallel_data => dataloopback_back(3071 downto 1536),
tx_control => controlloopback_back(383 downto 192),
- tx_err_ins => (others => '0'), -- use to insert sync errors
+ -- use to insert sync errors
+ tx_err_ins => (others => '0'),
unused_tx_parallel_data => (others => '0'),
unused_tx_control => (others => '0'),
rx_parallel_data => dataloopback_back(3071 downto 1536),
@@ -793,7 +996,8 @@ begin
rx_cdr_refclk0 => bck_ref_clk,
tx_serial_data => tx_serial_data_back(23 downto 0),
rx_serial_data => rx_serial_data_back(23 downto 0),
- tx_coreclkin => tx_serdesclk_back(23 downto 0), -- write side clock for tx fifo
+ -- write side clock for tx fifo
+ tx_coreclkin => tx_serdesclk_back(23 downto 0),
rx_coreclkin => tx_serdesclk_back(23 downto 0),
tx_clkout => tx_serdesclk_back(23 downto 0),
rx_clkout => open,
@@ -802,7 +1006,8 @@ begin
rx_enh_blk_lock => open,
tx_parallel_data => dataloopback_back(1535 downto 0),
tx_control => controlloopback_back(191 downto 0),
- tx_err_ins => (others => '0'), -- use to insert sync errors
+ -- use to insert sync errors
+ tx_err_ins => (others => '0'),
unused_tx_parallel_data => (others => '0'),
unused_tx_control => (others => '0'),
rx_parallel_data => dataloopback_back(1535 downto 0),
@@ -846,7 +1051,8 @@ begin
u_node_ctrl : entity unb_common_lib.unb_node_ctrl
generic map (
- g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us => c_unb_tse_clk_freq / (10**6)
)
port map (
xo_clk => ETH_clk,
@@ -857,18 +1063,22 @@ begin
st_clk => clk,
st_rst => open,
wdi_in => pout_wdi,
- wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
+ -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
+ wdi_out => WDI,
pulse_us => open,
pulse_ms => open,
- pulse_s => open -- could be used to toggle a LED
+ -- could be used to toggle a LED
+ pulse_s => open
);
reset_p <= not reset_n;
u0 : component sys_clkctrl
port map (
- inclk => CLK, -- altclkctrl_input.inclk
- outclk => CLK_buffered -- altclkctrl_output.outclk
+ -- altclkctrl_input.inclk
+ inclk => CLK,
+ -- altclkctrl_output.outclk
+ outclk => CLK_buffered
);
u_system_pll : system_pll
@@ -878,9 +1088,12 @@ begin
-- refclk => INTB,
rst => reset_p,
locked => sys_locked,
- outclk_0 => mm_clk, -- 100MHz
- outclk_1 => sys_clk, -- 300MHz
- outclk_2 => clk_125 -- 125MHz for 1ge
+ -- 100MHz
+ outclk_0 => mm_clk,
+ -- 300MHz
+ outclk_1 => sys_clk,
+ -- 125MHz for 1ge
+ outclk_2 => clk_125
);
-- u_system_pll : system_fpll
diff --git a/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd b/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
index 8f346a6f27cd7e3c42e7cd900c8702cbe0dceea8..064c323c3351b5f0c1527860a80ef62fcb8aeb29 100644
--- a/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
+++ b/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
@@ -30,11 +30,16 @@ entity unb2_singlemac is
port (
-- GENERAL
- CLK : in std_logic; -- External system clock
- PPS : in std_logic; -- External system sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- External system clock
+ CLK : in std_logic;
+ -- External system sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- 1GbE Control Interfaces
ETH_CLK : in std_logic;
@@ -42,9 +47,12 @@ entity unb2_singlemac is
ETH_SGOUT : out std_logic_vector(1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic; -- SerDes reference clock front
- SB_CLK : in std_logic; -- SerDes reference clock back
- BCK_REF_CLK : in std_logic; -- SerDes reference clock back
+ -- SerDes reference clock front
+ SA_CLK : in std_logic;
+ -- SerDes reference clock back
+ SB_CLK : in std_logic;
+ -- SerDes reference clock back
+ BCK_REF_CLK : in std_logic;
-- SO-DIMM DDR4 Memory Bank i2c (common)
-- MB_SCL : inout std_logic;
@@ -125,12 +133,16 @@ end unb2_singlemac;
architecture str of unb2_singlemac is
component system_iopll is
port (
- refclk : in std_logic := 'X'; -- clk
+ -- clk
+ refclk : in std_logic := 'X';
rst : in std_logic := 'X';
locked : out std_logic;
- outclk_0 : out std_logic; -- outclk0
- outclk_1 : out std_logic; -- outclk1
- outclk_2 : out std_logic -- outclk2
+ -- outclk0
+ outclk_0 : out std_logic;
+ -- outclk1
+ outclk_1 : out std_logic;
+ -- outclk2
+ outclk_2 : out std_logic
);
end component system_iopll;
@@ -155,44 +167,82 @@ architecture str of unb2_singlemac is
component ip_arria10_mac_10g is
port (
- csr_read : in std_logic := 'X'; -- read
- csr_write : in std_logic := 'X'; -- write
- csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- csr_readdata : out std_logic_vector(31 downto 0); -- readdata
- csr_waitrequest : out std_logic; -- waitrequest
- csr_address : in std_logic_vector(12 downto 0) := (others => 'X'); -- address
- tx_312_5_clk : in std_logic := 'X'; -- clk
- tx_156_25_clk : in std_logic := 'X'; -- clk
- rx_312_5_clk : in std_logic := 'X'; -- clk
- rx_156_25_clk : in std_logic := 'X'; -- clk
- csr_clk : in std_logic := 'X'; -- clk
- csr_rst_n : in std_logic := 'X'; -- reset_n
- tx_rst_n : in std_logic := 'X'; -- reset_n
- rx_rst_n : in std_logic := 'X'; -- reset_n
- avalon_st_tx_startofpacket : in std_logic := 'X'; -- startofpacket
- avalon_st_tx_endofpacket : in std_logic := 'X'; -- endofpacket
- avalon_st_tx_valid : in std_logic := 'X'; -- valid
- avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
- avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
- avalon_st_tx_error : in std_logic := 'X'; -- error
- avalon_st_tx_ready : out std_logic; -- ready
- avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => 'X'); -- data
- xgmii_tx : out std_logic_vector(71 downto 0); -- data
- avalon_st_txstatus_valid : out std_logic; -- valid
- avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- data
- avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- error
- xgmii_rx : in std_logic_vector(71 downto 0) := (others => 'X'); -- data
- link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0); -- data
- avalon_st_rx_data : out std_logic_vector(63 downto 0); -- data
- avalon_st_rx_startofpacket : out std_logic; -- startofpacket
- avalon_st_rx_valid : out std_logic; -- valid
- avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- empty
- avalon_st_rx_error : out std_logic_vector(5 downto 0); -- error
- avalon_st_rx_ready : in std_logic := 'X'; -- ready
- avalon_st_rx_endofpacket : out std_logic; -- endofpacket
- avalon_st_rxstatus_valid : out std_logic; -- valid
- avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- data
- avalon_st_rxstatus_error : out std_logic_vector(6 downto 0) -- error
+ -- read
+ csr_read : in std_logic := 'X';
+ -- write
+ csr_write : in std_logic := 'X';
+ -- writedata
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- readdata
+ csr_readdata : out std_logic_vector(31 downto 0);
+ -- waitrequest
+ csr_waitrequest : out std_logic;
+ -- address
+ csr_address : in std_logic_vector(12 downto 0) := (others => 'X');
+ -- clk
+ tx_312_5_clk : in std_logic := 'X';
+ -- clk
+ tx_156_25_clk : in std_logic := 'X';
+ -- clk
+ rx_312_5_clk : in std_logic := 'X';
+ -- clk
+ rx_156_25_clk : in std_logic := 'X';
+ -- clk
+ csr_clk : in std_logic := 'X';
+ -- reset_n
+ csr_rst_n : in std_logic := 'X';
+ -- reset_n
+ tx_rst_n : in std_logic := 'X';
+ -- reset_n
+ rx_rst_n : in std_logic := 'X';
+ -- startofpacket
+ avalon_st_tx_startofpacket : in std_logic := 'X';
+ -- endofpacket
+ avalon_st_tx_endofpacket : in std_logic := 'X';
+ -- valid
+ avalon_st_tx_valid : in std_logic := 'X';
+ -- data
+ avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => 'X');
+ -- empty
+ avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => 'X');
+ -- error
+ avalon_st_tx_error : in std_logic := 'X';
+ -- ready
+ avalon_st_tx_ready : out std_logic;
+ -- data
+ avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => 'X');
+ -- data
+ xgmii_tx : out std_logic_vector(71 downto 0);
+ -- valid
+ avalon_st_txstatus_valid : out std_logic;
+ -- data
+ avalon_st_txstatus_data : out std_logic_vector(39 downto 0);
+ -- error
+ avalon_st_txstatus_error : out std_logic_vector(6 downto 0);
+ -- data
+ xgmii_rx : in std_logic_vector(71 downto 0) := (others => 'X');
+ -- data
+ link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0);
+ -- data
+ avalon_st_rx_data : out std_logic_vector(63 downto 0);
+ -- startofpacket
+ avalon_st_rx_startofpacket : out std_logic;
+ -- valid
+ avalon_st_rx_valid : out std_logic;
+ -- empty
+ avalon_st_rx_empty : out std_logic_vector(2 downto 0);
+ -- error
+ avalon_st_rx_error : out std_logic_vector(5 downto 0);
+ -- ready
+ avalon_st_rx_ready : in std_logic := 'X';
+ -- endofpacket
+ avalon_st_rx_endofpacket : out std_logic;
+ -- valid
+ avalon_st_rxstatus_valid : out std_logic;
+ -- data
+ avalon_st_rxstatus_data : out std_logic_vector(39 downto 0);
+ -- error
+ avalon_st_rxstatus_error : out std_logic_vector(6 downto 0)
);
end component ip_arria10_mac_10g;
@@ -200,7 +250,8 @@ architecture str of unb2_singlemac is
constant cs_sim : std_logic := '0';
constant cs_sync : std_logic := '1';
--CONSTANT c_block_len : NATURAL := 180; -- = 1440 user bytes. Including packetizing: 1508 bytes.
- constant c_block_len : natural := 1118; -- = 8944 user bytes. Including packetizing: 9012 bytes.
+ -- = 8944 user bytes. Including packetizing: 9012 bytes.
+ constant c_block_len : natural := 1118;
-- general reset and clock signals
signal reset_n : std_logic := '0';
@@ -322,7 +373,8 @@ begin
u_node_ctrl : entity unb_common_lib.unb_node_ctrl
generic map (
- g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us => c_unb_tse_clk_freq / (10**6)
)
port map (
xo_clk => ETH_clk,
@@ -333,10 +385,12 @@ begin
st_clk => clk,
st_rst => open,
wdi_in => pout_wdi,
- wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
+ -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
+ wdi_out => WDI,
pulse_us => open,
pulse_ms => open,
- pulse_s => open -- could be used to toggle a LED
+ -- could be used to toggle a LED
+ pulse_s => open
);
reset_p <= not reset_n;
@@ -346,9 +400,12 @@ begin
refclk => ETH_CLK,
rst => reset_p,
locked => sys_locked,
- outclk_0 => mm_clk, -- 100MHz
- outclk_1 => sys_clk, -- 300MHz
- outclk_2 => clk_125 -- 125MHz for 1ge
+ -- 100MHz
+ outclk_0 => mm_clk,
+ -- 300MHz
+ outclk_1 => sys_clk,
+ -- 125MHz for 1ge
+ outclk_2 => clk_125
);
-- bidirectional and misc
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
index 3fbb7d4604baf0a97b9f0e4dfa79204d605658c5..3ea4e499a30f45793480557bdebb893f7c49d5e8 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
@@ -31,20 +31,29 @@ entity unb2_test_10GbE is
generic (
g_design_name : string := "unb2_test_10GbE";
g_design_note : string := "10GbE: 6xQSFP";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -61,9 +70,12 @@ entity unb2_test_10GbE is
ETH_SGOUT : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic; -- Clock 10GbE front (qsfp) and ring lines
- SB_CLK : in std_logic; -- Clock 10GbE back upper 24 lines
- BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic;
+ -- Clock 10GbE back upper 24 lines
+ SB_CLK : in std_logic;
+ -- Clock 10GbE back lower 24 lines
+ BCK_REF_CLK : in std_logic;
-- back transceivers
-- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
index d80b47e0e24b0d05e1cb16aa34a0f3fccc1682e2..01e8aa7e5a876fae0e2f36629e16f741ebd87dac 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
@@ -31,20 +31,29 @@ entity unb2_test_1GbE is
generic (
g_design_name : string := "unb2_test_1GbE";
g_design_note : string := "Test design with 1GbE";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
index 2eaf164405e9fa77976a5c679e6d65f5e095b7a9..0af0ebfa1f6c95688256234b6ab1a3cea4e97959 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
@@ -32,20 +32,29 @@ entity unb2_test_all is
generic (
g_design_name : string := "unb2_test_all";
g_design_note : string := "Test design with: 6xQSFP,DDR4";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -62,13 +71,18 @@ entity unb2_test_all is
ETH_SGOUT : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic; -- Clock 10GbE front (qsfp) and ring lines
- SB_CLK : in std_logic; -- Clock 10GbE back upper 24 lines
- BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic;
+ -- Clock 10GbE back upper 24 lines
+ SB_CLK : in std_logic;
+ -- Clock 10GbE back lower 24 lines
+ BCK_REF_CLK : in std_logic;
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
- MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic;
+ -- Reference clock for MB_II
+ MB_II_REF_CLK : in std_logic;
-- back transceivers
-- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
index 2443e9f95a5c7f3d10ad2d974128c933c46a957b..6d93e8e016c7f6c6b7280d259b5bd174c5f886e4 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
@@ -32,20 +32,29 @@ entity unb2_test_ddr_MB_I is
generic (
g_design_name : string := "unb2_test_ddr_MB_I";
g_design_note : string := "Test design with ddr4";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -66,7 +75,8 @@ entity unb2_test_ddr_MB_I is
ETH_SGOUT : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic;
-- SO-DIMM Memory Bank I
MB_I_IN : in t_tech_ddr4_phy_in;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
index 13039a84e05ee9e1cb8e71edbf56cf5f09a672e2..a764d4be085dcd66087c915012ef4faabdf11cc6 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
@@ -32,20 +32,29 @@ entity unb2_test_ddr_MB_II is
generic (
g_design_name : string := "unb2_test_ddr_MB_II";
g_design_note : string := "Test design with ddr4";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -66,7 +75,8 @@ entity unb2_test_ddr_MB_II is
ETH_SGOUT : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- DDR reference clocks
- MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
+ -- Reference clock for MB_II
+ MB_II_REF_CLK : in std_logic;
-- SO-DIMM Memory Bank II
MB_II_IN : in t_tech_ddr4_phy_in;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
index 9680fc8e5d5f46fea841832f2bb4bcc4dfca3c60..7180cdd1941265138588523c7e736c768eae8470 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
@@ -32,20 +32,29 @@ entity unb2_test_ddr_MB_I_II is
generic (
g_design_name : string := "unb2_test_ddr_MB_I_II";
g_design_note : string := "Test design with ddr4";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -66,8 +75,10 @@ entity unb2_test_ddr_MB_I_II is
ETH_SGOUT : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
- MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic;
+ -- Reference clock for MB_II
+ MB_II_REF_CLK : in std_logic;
-- SO-DIMM Memory Bank I
MB_I_IN : in t_tech_ddr4_phy_in;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index 0e6ff5436b8694a8ac2b36a829ca58f4d2925381..f7c78d5fbeb773cfcc10e1482b36eebd684690de 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -42,7 +42,8 @@ use work.unb2_test_pkg.all;
entity mmm_unb2_test is
generic (
- g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
+ -- FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_technology : natural := c_tech_arria10;
@@ -403,7 +404,8 @@ begin
proc_tech_tse_setup(c_tech_arria10, false, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth0_tse_miso, eth1g_eth0_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth0_reg_miso, sim_eth1g_eth0_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth0_reg_miso, sim_eth1g_eth0_reg_mosi);
sim_eth_mm_bus_switch <= '0';
wait;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 3db6393627fe5aafe9588fa02a19d351423c55a7..592fe2c3e05e198be0be5032fbb57783122bfdd0 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -30,351 +30,696 @@ package qsys_unb2_test_pkg is
component qsys_unb2_test is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_clk_export : out std_logic; -- export
- avs_eth_1_irq_export : in std_logic := 'X'; -- export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_ram_read_export : out std_logic; -- export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_ram_write_export : out std_logic; -- export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_1_reg_read_export : out std_logic; -- export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_reg_write_export : out std_logic; -- export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_reset_export : out std_logic; -- export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_tse_read_export : out std_logic; -- export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_1_tse_write_export : out std_logic; -- export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- export
- ram_diag_bg_1gbe_read_export : out std_logic; -- export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- export
- ram_diag_bg_1gbe_write_export : out std_logic; -- export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- export
- reg_diag_bg_1gbe_read_export : out std_logic; -- export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- export
- reg_diag_bg_1gbe_write_export : out std_logic; -- export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back0_clk_export : out std_logic; -- export
- reg_eth10g_back0_read_export : out std_logic; -- export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back0_reset_export : out std_logic; -- export
- reg_eth10g_back0_write_export : out std_logic; -- export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back1_clk_export : out std_logic; -- export
- reg_eth10g_back1_read_export : out std_logic; -- export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back1_reset_export : out std_logic; -- export
- reg_eth10g_back1_write_export : out std_logic; -- export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_sens_clk_export : out std_logic; -- export
- reg_fpga_sens_read_export : out std_logic; -- export
- reg_fpga_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_sens_reset_export : out std_logic; -- export
- reg_fpga_sens_write_export : out std_logic; -- export
- reg_fpga_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- export
- reg_tr_10gbe_back0_read_export : out std_logic; -- export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back0_write_export : out std_logic; -- export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- export
- reg_tr_10gbe_back1_read_export : out std_logic; -- export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back1_write_export : out std_logic; -- export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(2 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_1_clk_export : out std_logic;
+ -- export
+ avs_eth_1_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_1_ram_read_export : out std_logic;
+ -- export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_1_ram_write_export : out std_logic;
+ -- export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_1_reg_read_export : out std_logic;
+ -- export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_1_reg_write_export : out std_logic;
+ -- export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_1_reset_export : out std_logic;
+ -- export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_1_tse_read_export : out std_logic;
+ -- export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_1_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_1_tse_write_export : out std_logic;
+ -- export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0);
+ -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic;
+ -- export
+ ram_diag_bg_10gbe_read_export : out std_logic;
+ -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic;
+ -- export
+ ram_diag_bg_10gbe_write_export : out std_logic;
+ -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0);
+ -- export
+ ram_diag_bg_1gbe_clk_export : out std_logic;
+ -- export
+ ram_diag_bg_1gbe_read_export : out std_logic;
+ -- export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_bg_1gbe_reset_export : out std_logic;
+ -- export
+ ram_diag_bg_1gbe_write_export : out std_logic;
+ -- export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0);
+ -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0);
+ -- export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0);
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0);
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0);
+ -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_1gbe_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_1gbe_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_bg_10gbe_read_export : out std_logic;
+ -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_bg_10gbe_write_export : out std_logic;
+ -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_bg_1gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_bg_1gbe_read_export : out std_logic;
+ -- export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_bg_1gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_bg_1gbe_write_export : out std_logic;
+ -- export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_eth10g_back0_clk_export : out std_logic;
+ -- export
+ reg_eth10g_back0_read_export : out std_logic;
+ -- export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_eth10g_back0_reset_export : out std_logic;
+ -- export
+ reg_eth10g_back0_write_export : out std_logic;
+ -- export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_eth10g_back1_clk_export : out std_logic;
+ -- export
+ reg_eth10g_back1_read_export : out std_logic;
+ -- export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_eth10g_back1_reset_export : out std_logic;
+ -- export
+ reg_eth10g_back1_write_export : out std_logic;
+ -- export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic;
+ -- export
+ reg_eth10g_qsfp_ring_read_export : out std_logic;
+ -- export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic;
+ -- export
+ reg_eth10g_qsfp_ring_write_export : out std_logic;
+ -- export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0);
+ -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_i_read_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_i_write_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0);
+ -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0);
+ -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back0_read_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X';
+ -- export
+ reg_tr_10gbe_back0_write_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0);
+ -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back1_read_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X';
+ -- export
+ reg_tr_10gbe_back1_write_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0);
+ -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic;
+ -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic;
+ -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic;
+ -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X';
+ -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic;
+ -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic
);
end component qsys_unb2_test;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
index b025b45615e2eb7cf6660fc33fcf9c9cc9b64da5..a89cc1c17a3351b19948212f45dd42429e77b51d 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
@@ -61,9 +61,11 @@ entity udp_stream is
ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0);
-- blockgen mm
- reg_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- BG control register (one for all streams)
+ -- BG control register (one for all streams)
+ reg_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_diag_bg_miso : out t_mem_miso;
- ram_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream)
+ -- BG buffer RAM (one per stream)
+ ram_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_diag_bg_miso : out t_mem_miso;
reg_diag_tx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_diag_tx_seq_miso : out t_mem_miso;
@@ -102,8 +104,10 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
+ -- enable (disabled by default)
+ constant c_bg_ctrl : t_diag_block_gen := ('0',
+ -- enable_sync
+ '0',
TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
@@ -178,7 +182,8 @@ begin
reg_tx_seq_miso => reg_diag_tx_seq_miso
);
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
g_technology => g_technology,
@@ -317,9 +322,11 @@ begin
generic map (
g_technology => g_technology,
g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
+ -- g_data_w, --FIXME
+ g_data_w => 32,
g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
+ -- sync by reading last address of data buffer
+ g_buf_use_sync => false,
g_use_rx_seq => true
)
port map (
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index a4e2c262f85c563935ad879102395a2f2b226797..5a5ffddbaedb1fbe3f59a01eebd0b5fdf49e114a 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -41,24 +41,35 @@ entity unb2_test is
g_design_name : string := "unb2_test";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10;
- g_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
- g_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
- g_sim : boolean := false; -- Overridden by TB
+ -- DDR4 has no master or slave, so no need to check number of MB
+ g_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
+ -- DDR4 has no master or slave, so no need to check number of MB
+ g_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_sim_model_ddr : boolean := false;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0; -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0;
g_factory_image : boolean := false
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -75,13 +86,18 @@ entity unb2_test is
ETH_SGOUT : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
- SB_CLK : in std_logic := '0'; -- Clock 10GbE back upper 24 lines
- BCK_REF_CLK : in std_logic := '0'; -- Clock 10GbE back lower 24 lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
+ -- Clock 10GbE back upper 24 lines
+ SB_CLK : in std_logic := '0';
+ -- Clock 10GbE back lower 24 lines
+ BCK_REF_CLK : in std_logic := '0';
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic := '0'; -- Reference clock for MB_I
- MB_II_REF_CLK : in std_logic := '0'; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic := '0';
+ -- Reference clock for MB_II
+ MB_II_REF_CLK : in std_logic := '0';
-- back transceivers
--BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0) := (OTHERS=>'0');
@@ -143,23 +159,31 @@ architecture str of unb2_test is
constant c_mm_clk_freq : natural := c_unb2_board_mm_clk_freq_125M;
-- Revision controlled constants
- constant c_use_1GbE : boolean := false; -- g_design_name="unb2_test_1GbE" OR g_design_name="unb2_test_10GbE" OR g_design_name="unb2_test_all";
+ -- g_design_name="unb2_test_1GbE" OR g_design_name="unb2_test_10GbE" OR g_design_name="unb2_test_all";
+ constant c_use_1GbE : boolean := false;
constant c_use_10GbE : boolean := g_design_name = "unb2_test_10GbE" or g_design_name = "unb2_test_all";
constant c_use_10GbE_qsfp : boolean := c_use_10GbE;
- constant c_use_10GbE_ring : boolean := false; -- c_use_10GbE;
- constant c_use_10GbE_back0 : boolean := false; -- c_use_10GbE;
- constant c_use_10GbE_back1 : boolean := false; -- c_use_10GbE;
+ -- c_use_10GbE;
+ constant c_use_10GbE_ring : boolean := false;
+ -- c_use_10GbE;
+ constant c_use_10GbE_back0 : boolean := false;
+ -- c_use_10GbE;
+ constant c_use_10GbE_back1 : boolean := false;
constant c_use_MB_I : boolean := g_design_name = "unb2_test_ddr_MB_I" or g_design_name = "unb2_test_ddr_MB_I_II" or g_design_name = "unb2_test_all";
constant c_use_MB_II : boolean := g_design_name = "unb2_test_ddr_MB_II" or g_design_name = "unb2_test_ddr_MB_I_II" or g_design_name = "unb2_test_all";
-- transceivers
constant c_nof_qsfp : natural := c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
- constant c_nof_ring : natural := 0; -- 8;--12;--c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
- constant c_nof_back0 : natural := 0; -- c_unb2_board_tr_back.bus_w;
- constant c_nof_back1 : natural := 0; -- c_unb2_board_tr_back.bus_w;
+ -- 8;--12;--c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
+ constant c_nof_ring : natural := 0;
+ -- c_unb2_board_tr_back.bus_w;
+ constant c_nof_back0 : natural := 0;
+ -- c_unb2_board_tr_back.bus_w;
+ constant c_nof_back1 : natural := 0;
-- 1GbE
- constant c_nof_streams_1GbE : natural := sel_a_b(c_use_1GbE,1,0); -- sel_a_b(c_use_1GbE,c_unb2_board_nof_eth,0);
+ -- sel_a_b(c_use_1GbE,c_unb2_board_nof_eth,0);
+ constant c_nof_streams_1GbE : natural := sel_a_b(c_use_1GbE,1,0);
-- 10GbE
constant c_nof_streams_qsfp : natural := sel_a_b(c_use_10GbE_qsfp,c_nof_qsfp,0);
@@ -173,15 +197,22 @@ architecture str of unb2_test is
constant c_nof_ring_bus : natural := ceil_div(c_nof_streams_ring,c_unb2_board_tr_ring.bus_w);
constant c_nof_back_bus : natural := ceil_div(c_nof_streams_back0,c_unb2_board_tr_back.bus_w) + ceil_div(c_nof_streams_back1,c_unb2_board_tr_back.bus_w);
- constant c_data_w_32 : natural := c_eth_data_w; -- 1GbE
- constant c_data_w_64 : natural := c_xgmii_data_w; -- 10GbE
+ -- 1GbE
+ constant c_data_w_32 : natural := c_eth_data_w;
+ -- 10GbE
+ constant c_data_w_64 : natural := c_xgmii_data_w;
-- ddr
- constant c_ddr_ctlr_data_w : natural := func_tech_ddr_ctlr_data_w(g_ddr_MB_I); -- = 576, assume both MB_I and MB_II use the same ctlr_data_w
- constant c_ddr_dp_data_w : natural := 144; -- DDR4 with dq_w = 72, rsl = 8 so ctrl data width = 576 and therefore the mixed width FIFO ratio is 576 /144 = 4
- constant c_ddr_dp_seq_dat_w : natural := 16; -- >= 1, test sequence data width. Choose c_ddr_dp_seq_dat_w <= c_ddr_dp_data_w. The seq data gets replicated to fill c_ddr_dp_data_w.
- constant c_ddr_dp_wr_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w); -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) to make full use of M9K which have at least 256 words
- constant c_ddr_dp_rd_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w); -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) or factors of 2 more to fit max number of read bursts
+ -- = 576, assume both MB_I and MB_II use the same ctlr_data_w
+ constant c_ddr_ctlr_data_w : natural := func_tech_ddr_ctlr_data_w(g_ddr_MB_I);
+ -- DDR4 with dq_w = 72, rsl = 8 so ctrl data width = 576 and therefore the mixed width FIFO ratio is 576 /144 = 4
+ constant c_ddr_dp_data_w : natural := 144;
+ -- >= 1, test sequence data width. Choose c_ddr_dp_seq_dat_w <= c_ddr_dp_data_w. The seq data gets replicated to fill c_ddr_dp_data_w.
+ constant c_ddr_dp_seq_dat_w : natural := 16;
+ -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) to make full use of M9K which have at least 256 words
+ constant c_ddr_dp_wr_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w);
+ -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) or factors of 2 more to fit max number of read bursts
+ constant c_ddr_dp_rd_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w);
constant c_ddr_db_buf_nof_data : natural := 1024;
constant c_ddr_mixed_width_ratio : natural := ratio2(c_ddr_ctlr_data_w, c_ddr_dp_data_w);
@@ -189,11 +220,14 @@ architecture str of unb2_test is
constant c_bg_block_size : natural := 900;
constant c_bg_gapsize_1GbE : natural := 1000;
constant c_bg_gapsize_10GbE : natural := 100;
- constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
+ -- 200000*(900+100) = 200000000 cycles = 1 second
+ constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000);
constant c_use_jumbo_frames : boolean := false;
- constant c_def_1GbE_block_size : natural := 20; -- 0 first so we have time to set RX demux reg in dest. node
- constant c_def_10GbE_block_size : natural := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
+ -- 0 first so we have time to set RX demux reg in dest. node
+ constant c_def_1GbE_block_size : natural := 20;
+ -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
+ constant c_def_10GbE_block_size : natural := 700;
constant c_max_frame_len : natural := sel_a_b(c_use_jumbo_frames, 9018, 1518);
constant c_nof_header_bytes : natural := field_slv_len(c_hdr_field_arr) / c_byte_w;
@@ -262,22 +296,30 @@ architecture str of unb2_test is
-- eth1g ch0
signal eth1g_eth0_mm_rst : std_logic;
- signal eth1g_eth0_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_eth0_tse_mosi : t_mem_mosi;
signal eth1g_eth0_tse_miso : t_mem_miso;
- signal eth1g_eth0_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_eth0_reg_mosi : t_mem_mosi;
signal eth1g_eth0_reg_miso : t_mem_miso;
- signal eth1g_eth0_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_eth0_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_eth0_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_eth0_ram_mosi : t_mem_mosi;
signal eth1g_eth0_ram_miso : t_mem_miso;
-- eth1g ch1
signal eth1g_eth1_mm_rst : std_logic;
- signal eth1g_eth1_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_eth1_tse_mosi : t_mem_mosi;
signal eth1g_eth1_tse_miso : t_mem_miso;
- signal eth1g_eth1_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_eth1_reg_mosi : t_mem_mosi;
signal eth1g_eth1_reg_miso : t_mem_miso;
- signal eth1g_eth1_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_eth1_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_eth1_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_eth1_ram_mosi : t_mem_mosi;
signal eth1g_eth1_ram_miso : t_mem_miso;
-- EPCS read
@@ -581,9 +623,12 @@ begin
g_hdr_field_arr => c_hdr_field_arr,
g_nof_streams_1GbE => c_unb2_board_nof_eth,
g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
- g_nof_streams_ring => 24, -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
- g_nof_streams_back0 => 24, -- c_unb2_board_tr_back.bus_w,
- g_nof_streams_back1 => 24 -- c_unb2_board_tr_back.bus_w
+ -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
+ g_nof_streams_ring => 24,
+ -- c_unb2_board_tr_back.bus_w,
+ g_nof_streams_back0 => 24,
+ -- c_unb2_board_tr_back.bus_w
+ g_nof_streams_back1 => 24
)
port map(
mm_rst => mm_rst,
@@ -611,7 +656,8 @@ begin
-- FPGA sensors
reg_fpga_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_sens_miso => reg_fpga_temp_sens_miso, -- FIXME:
+ -- FIXME:
+ reg_fpga_sens_miso => reg_fpga_temp_sens_miso,
--reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
--reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
--reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
@@ -868,7 +914,8 @@ begin
reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
);
- u_tr_10GbE_qsfp_and_ring: entity unb2_board_10gbe_lib.unb2_board_10gbe -- QSFP and Ring lines
+ -- QSFP and Ring lines
+ u_tr_10GbE_qsfp_and_ring: entity unb2_board_10gbe_lib.unb2_board_10gbe
generic map (
g_sim => g_sim,
g_sim_level => 1,
@@ -1025,7 +1072,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M)
)
port map (
rst => dp_rst,
@@ -1066,7 +1114,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
@@ -1099,7 +1148,8 @@ begin
-- DIAG data buffer
g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ -- nof words per data buffer
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data
)
port map (
---------------------------------------------------------------------------
@@ -1108,7 +1158,8 @@ begin
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+ -- use alternative external clock or externally connect to ctlr_clk_out
+ dp_clk => dp_clk,
---------------------------------------------------------------------------
-- IO_DDR
@@ -1121,11 +1172,14 @@ begin
ctlr_clk_out => ddr_I_clk200,
ctlr_rst_out => ddr_I_rst200,
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+ -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_clk_in => ddr_I_clk200,
+ -- connect ctlr_rst_out to ctlr_rst_in at top level
+ ctlr_rst_in => ddr_I_rst200,
-- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ -- register for DDR controller status info
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi,
reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-- Write / read FIFO status for monitoring purposes (in dp_clk domain)
@@ -1176,7 +1230,8 @@ begin
-- DIAG data buffer
g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ -- nof words per data buffer
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data
)
port map (
---------------------------------------------------------------------------
@@ -1185,7 +1240,8 @@ begin
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+ -- use alternative external clock or externally connect to ctlr_clk_out
+ dp_clk => dp_clk,
---------------------------------------------------------------------------
-- IO_DDR
@@ -1198,11 +1254,14 @@ begin
ctlr_clk_out => ddr_II_clk200,
ctlr_rst_out => ddr_II_rst200,
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+ -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_clk_in => ddr_II_clk200,
+ -- connect ctlr_rst_out to ctlr_rst_in at top level
+ ctlr_rst_in => ddr_II_rst200,
-- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ -- register for DDR controller status info
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi,
reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-- Write / read FIFO status for monitoring purposes (in dp_clk domain)
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
index da3fbc3dc0c7e427c802c985f802c95fa7b931eb..ae6bcd809b6334cd6cbc58978ed01eea165fd986 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
@@ -28,15 +28,18 @@ use common_lib.common_field_pkg.all;
package unb2_test_pkg is
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
- constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ -- Total header bits = 384 = 6 64b words
+ constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2;
+ -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
@@ -47,7 +50,8 @@ package unb2_test_pkg is
( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
diff --git a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
index 3fca57d0e88f3ca7b41acfec566ff13c9183f83c..3aef910c7c95ab3c5df422293565b30e1fa4493c 100644
--- a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
@@ -62,24 +62,34 @@ end tb_unb2_test;
architecture tb of tb_unb2_test is
constant c_sim : boolean := true;
- constant c_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
- constant c_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
-
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- DDR4 has no master or slave, so no need to check number of MB
+ constant c_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
+ -- DDR4 has no master or slave, so no need to check number of MB
+ constant c_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
+
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb2_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644 MHz
- constant c_sb_clk_period : time := tech_pll_clk_644_period; -- 644 MHz
- constant c_bck_ref_clk_period : time := tech_pll_clk_644_period; -- 644 MHz
- constant c_mb_I_ref_clk_period : time := 40 ns; -- 25 MHz
- constant c_mb_II_ref_clk_period : time := 40 ns; -- 25 MHz
+ -- 644 MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
+ -- 644 MHz
+ constant c_sb_clk_period : time := tech_pll_clk_644_period;
+ -- 644 MHz
+ constant c_bck_ref_clk_period : time := tech_pll_clk_644_period;
+ -- 25 MHz
+ constant c_mb_I_ref_clk_period : time := 40 ns;
+ -- 25 MHz
+ constant c_mb_II_ref_clk_period : time := 40 ns;
constant c_pps_period : natural := 1000;
-- DUT
@@ -105,8 +115,10 @@ architecture tb of tb_unb2_test is
signal qsfp_led : std_logic_vector(c_unb2_board_tr_qsfp_nof_leds - 1 downto 0);
-- DDR reference clocks
- signal mb_I_ref_clk : std_logic := '1'; -- Reference clock for MB_I
- signal mb_II_ref_clk : std_logic := '1'; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ signal mb_I_ref_clk : std_logic := '1';
+ -- Reference clock for MB_II
+ signal mb_II_ref_clk : std_logic := '1';
-- DDR4 PHY interface
signal MB_I_IN : t_tech_ddr4_phy_in;
@@ -136,33 +148,51 @@ architecture tb of tb_unb2_test is
signal si_lpbk_8 : std_logic_vector(c_unb2_board_tr_back.bus_w - 1 downto 0);
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- sa_clk <= not sa_clk after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
- sb_clk <= not sb_clk after c_sb_clk_period / 2; -- Serial Gigabit IO sb clock (644 MHz)
- bck_ref_clk <= not bck_ref_clk after c_bck_ref_clk_period / 2; -- Serial Gigabit IO bck_ref clock (644 MHz)
- mb_I_ref_clk <= not mb_I_ref_clk after c_mb_I_ref_clk_period / 2; -- MB I reference clock (25 MHz)
- mb_II_ref_clk <= not mb_II_ref_clk after c_mb_II_ref_clk_period / 2; -- MB II reference clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ sa_clk <= not sa_clk after c_sa_clk_period / 2;
+ -- Serial Gigabit IO sb clock (644 MHz)
+ sb_clk <= not sb_clk after c_sb_clk_period / 2;
+ -- Serial Gigabit IO bck_ref clock (644 MHz)
+ bck_ref_clk <= not bck_ref_clk after c_bck_ref_clk_period / 2;
+ -- MB I reference clock (25 MHz)
+ mb_I_ref_clk <= not mb_I_ref_clk after c_mb_I_ref_clk_period / 2;
+ -- MB II reference clock (25 MHz)
+ mb_II_ref_clk <= not mb_II_ref_clk after c_mb_II_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index 8a4c6bd89ad9db59424e1cbddfbcb0bf8b468f41..38ba93db7ca14618b8b1b68074609d41a3be9809 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -44,12 +44,14 @@ entity ctrl_unb2_board is
g_technology : natural := c_tech_arria10;
g_sim : boolean := false;
g_design_name : string := "UNUSED";
- g_fw_version : t_unb2_board_fw_version := (0, 0); -- firmware version x.y
+ -- firmware version x.y
+ g_fw_version : t_unb2_board_fw_version := (0, 0);
g_stamp_date : natural := 0;
g_stamp_time : natural := 0;
g_stamp_svn : natural := 0;
g_design_note : string := "UNUSED";
- g_base_ip : std_logic_vector(16 - 1 downto 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy
+ -- Base IP address used by unb_osy: 10.99.xx.yy
+ g_base_ip : std_logic_vector(16 - 1 downto 0) := X"0A63";
g_mm_clk_freq : natural := c_unb2_board_mm_clk_freq_125M;
g_eth_clk_freq : natural := c_unb2_board_eth_clk_freq_125M;
g_tse_clk_buf : boolean := false;
@@ -93,7 +95,8 @@ entity ctrl_unb2_board is
-- STRING := "4688" = 3750+ 938 = 337.5
-- STRING := "4844" = 3750+1094 = 348.75
-- STRING := "5000" = 3750+1250 = 360
- g_dp_clk_phase : string := "0"; -- phase offset for PLL c0, typically any phase is fine, do not use 225 +-30 degrees because there the PPS edge occurs
+ -- phase offset for PLL c0, typically any phase is fine, do not use 225 +-30 degrees because there the PPS edge occurs
+ g_dp_clk_phase : string := "0";
----------------------------------------------------------------------------
-- 1GbE UDP offload
@@ -105,8 +108,10 @@ entity ctrl_unb2_board is
-- Auxiliary Interface
----------------------------------------------------------------------------
g_fpga_temp_high : natural := 85;
- g_app_led_red : boolean := false; -- when TRUE use external LED control via app_led_red
- g_app_led_green : boolean := false; -- when TRUE use external LED control via app_led_green
+ -- when TRUE use external LED control via app_led_red
+ g_app_led_red : boolean := false;
+ -- when TRUE use external LED control via app_led_green
+ g_app_led_green : boolean := false;
g_aux : t_c_unb2_board_aux := c_unb2_board_aux;
g_factory_image : boolean := false;
@@ -119,33 +124,49 @@ entity ctrl_unb2_board is
-- System
cs_sim : out std_logic;
- xo_ethclk : out std_logic; -- 125 MHz ETH_CLK
- xo_rst : out std_logic; -- reset in ETH_CLK domain released after few cycles
+ -- 125 MHz ETH_CLK
+ xo_ethclk : out std_logic;
+ -- reset in ETH_CLK domain released after few cycles
+ xo_rst : out std_logic;
xo_rst_n : out std_logic;
- ext_clk200 : out std_logic; -- 200 MHz CLK
- ext_rst200 : out std_logic; -- reset in CLK clock domain released after mm_rst
-
- mm_clk : out std_logic; -- MM clock from xo_ethclk PLL
- mm_rst : out std_logic; -- reset in MM clock domain released after xo_ethclk PLL locked
-
- dp_rst : out std_logic; -- reset in DP clock domain released after mm_rst and after CLK PLL locked in case g_dp_clk_use_pll=TRUE
- dp_clk : out std_logic; -- 200 MHz DP clock from CLK system clock direct or via CLK PLL dependent on g_dp_clk_use_pll
- dp_pps : out std_logic; -- PPS in dp_clk domain
- dp_rst_in : in std_logic; -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
- dp_clk_in : in std_logic; -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
-
- mb_I_ref_rst : out std_logic; -- reset in MB_I_REF_CLK domain released after mm_rst
- mb_II_ref_rst : out std_logic; -- reset in MB_II_REF_CLK domain released after mm_rst
-
- this_chip_id : out std_logic_vector(c_unb2_board_nof_chip_w - 1 downto 0); -- [1:0], so range 0-3 for PN
- this_bck_id : out std_logic_vector(c_unb2_board_nof_uniboard_w - 1 downto 0); -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
+ -- 200 MHz CLK
+ ext_clk200 : out std_logic;
+ -- reset in CLK clock domain released after mm_rst
+ ext_rst200 : out std_logic;
+
+ -- MM clock from xo_ethclk PLL
+ mm_clk : out std_logic;
+ -- reset in MM clock domain released after xo_ethclk PLL locked
+ mm_rst : out std_logic;
+
+ -- reset in DP clock domain released after mm_rst and after CLK PLL locked in case g_dp_clk_use_pll=TRUE
+ dp_rst : out std_logic;
+ -- 200 MHz DP clock from CLK system clock direct or via CLK PLL dependent on g_dp_clk_use_pll
+ dp_clk : out std_logic;
+ -- PPS in dp_clk domain
+ dp_pps : out std_logic;
+ -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
+ dp_rst_in : in std_logic;
+ -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
+ dp_clk_in : in std_logic;
+
+ -- reset in MB_I_REF_CLK domain released after mm_rst
+ mb_I_ref_rst : out std_logic;
+ -- reset in MB_II_REF_CLK domain released after mm_rst
+ mb_II_ref_rst : out std_logic;
+
+ -- [1:0], so range 0-3 for PN
+ this_chip_id : out std_logic_vector(c_unb2_board_nof_chip_w - 1 downto 0);
+ -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
+ this_bck_id : out std_logic_vector(c_unb2_board_nof_uniboard_w - 1 downto 0);
app_led_red : in std_logic := '0';
app_led_green : in std_logic := '1';
-- PIOs
- pout_wdi : in std_logic; -- Toggled by unb_osy; can be overriden by reg_wdi.
+ -- Toggled by unb_osy; can be overriden by reg_wdi.
+ pout_wdi : in std_logic;
-- Manual WDI override
reg_wdi_mosi : in t_mem_mosi := c_mem_mosi_rst;
@@ -197,12 +218,16 @@ entity ctrl_unb2_board is
-- eth1g control&monitoring
eth1g_mm_rst : in std_logic;
- eth1g_tse_mosi : in t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ eth1g_tse_mosi : in t_mem_mosi;
eth1g_tse_miso : out t_mem_miso;
- eth1g_reg_mosi : in t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ eth1g_reg_mosi : in t_mem_mosi;
eth1g_reg_miso : out t_mem_miso;
- eth1g_reg_interrupt : out std_logic; -- Interrupt
- eth1g_ram_mosi : in t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ eth1g_reg_interrupt : out std_logic;
+ -- ETH rx frame and tx frame memory
+ eth1g_ram_mosi : in t_mem_mosi;
eth1g_ram_miso : out t_mem_miso;
-- eth1g UDP streaming ports
@@ -215,11 +240,16 @@ entity ctrl_unb2_board is
-- >>> Ctrl FPGA pins
--
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(g_aux.version_w - 1 downto 0);
@@ -236,20 +266,25 @@ entity ctrl_unb2_board is
PMBUS_ALERT : in std_logic := '0';
-- DDR reference clock domains reset creation
- MB_I_REF_CLK : in std_logic := '0'; -- 25 MHz
- MB_II_REF_CLK : in std_logic := '0'; -- 25 MHz
+ -- 25 MHz
+ MB_I_REF_CLK : in std_logic := '0';
+ -- 25 MHz
+ MB_II_REF_CLK : in std_logic := '0';
-- 1GbE Control Interface
- ETH_CLK : in std_logic; -- 125 MHz
+ -- 125 MHz
+ ETH_CLK : in std_logic;
ETH_SGIN : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0) := (others => '0');
ETH_SGOUT : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0)
);
end ctrl_unb2_board;
architecture str of ctrl_unb2_board is
- constant c_rom_version : natural := 1; -- Only increment when something changes to the register map of rom_system_info.
+ -- Only increment when something changes to the register map of rom_system_info.
+ constant c_rom_version : natural := 1;
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
-- Clock and reset
signal i_ext_clk200 : std_logic;
@@ -305,22 +340,27 @@ begin
INTA <= 'Z';
INTB <= 'Z';
- TESTIO <= (others => 'Z'); -- Leave unused INOUT tri-state
+ -- Leave unused INOUT tri-state
+ TESTIO <= (others => 'Z');
- ext_pps <= PPS; -- use more special name for PPS pin signal to ease searching for it in editor
+ -- use more special name for PPS pin signal to ease searching for it in editor
+ ext_pps <= PPS;
-----------------------------------------------------------------------------
-- ext_clk200 = CLK
-----------------------------------------------------------------------------
- i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
+ -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
+ i_ext_clk200 <= CLK;
u_common_areset_ext : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => i_ext_clk200,
out_rst => ext_rst200
);
@@ -329,15 +369,18 @@ begin
-- xo_ethclk = ETH_CLK
-----------------------------------------------------------------------------
- i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
+ -- use the ETH_CLK pin as xo_clk
+ i_xo_ethclk <= ETH_CLK;
u_common_areset_xo : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => i_xo_ethclk,
out_rst => i_xo_rst
);
@@ -349,22 +392,26 @@ begin
u_common_areset_mb_I : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ -- release reset some clock cycles after i_mm_rst went low
+ in_rst => i_mm_rst,
clk => MB_I_REF_CLK,
out_rst => mb_I_ref_rst
);
u_common_areset_mb_II : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ -- release reset some clock cycles after i_mm_rst went low
+ in_rst => i_mm_rst,
clk => MB_II_REF_CLK,
out_rst => mb_II_ref_rst
);
@@ -383,7 +430,8 @@ begin
g_delay_len => c_reset_len
)
port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ -- release reset some clock cycles after i_mm_rst went low
+ in_rst => i_mm_rst,
clk => dp_clk_in,
out_rst => dp_rst
);
@@ -400,7 +448,8 @@ begin
port map (
arst => i_mm_rst,
clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
+ -- = c0
+ st_clk200 => dp_clk,
st_rst200 => dp_rst
);
end generate;
@@ -414,7 +463,8 @@ begin
g_delay_len => c_reset_len
)
port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ -- release reset some clock cycles after i_mm_rst went low
+ in_rst => i_mm_rst,
clk => dp_clk_in,
out_rst => dp_rst
);
@@ -431,14 +481,20 @@ begin
clk125 when g_mm_clk_freq = c_unb2_board_mm_clk_freq_125M else
clk100 when g_mm_clk_freq = c_unb2_board_mm_clk_freq_100M else
clk50 when g_mm_clk_freq = c_unb2_board_mm_clk_freq_50M else
- clk50; -- default
+ -- default
+ clk50;
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
- mm_sim_clk <= not mm_sim_clk after 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
+ -- 20 MHz, 50ns/2
+ epcs_clk <= not epcs_clk after 25 ns;
+ -- 50 MHz, 20ns/2
+ clk50 <= not clk50 after 10 ns;
+ -- 100 MHz, 10ns/2
+ clk100 <= not clk100 after 5 ns;
+ -- 125 MHz, 8ns/2
+ clk125 <= not clk125 after 4 ns;
+ -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
+ mm_sim_clk <= not mm_sim_clk after 50 ns;
mm_locked <= '0', '1' after 70 ns;
end generate;
@@ -461,7 +517,8 @@ begin
u_unb2_board_node_ctrl : entity work.unb2_board_node_ctrl
generic map (
- g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us => g_mm_clk_freq / (10**6)
)
port map (
-- MM clock domain reset
@@ -470,11 +527,13 @@ begin
mm_rst => i_mm_rst,
-- WDI extend
mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ mm_wdi_out => mm_wdi,
-- Pulses
mm_pulse_us => OPEN,
mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
+ -- could be used to toggle a LED
+ mm_pulse_s => mm_pulse_s
);
-----------------------------------------------------------------------------
@@ -635,7 +694,8 @@ begin
mm_clk => i_mm_clk,
st_rst => dp_rst_in,
st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+ -- with unknown but constant phase to st_clk
+ pps_ext => ext_pps,
-- Memory-mapped clock domain
reg_mosi => reg_ppsh_mosi,
@@ -649,7 +709,8 @@ begin
-- I2C control for UniBoard sensors
------------------------------------------------------------------------------
- mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_ms; -- speed up in simulation
+ -- speed up in simulation
+ mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_ms;
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
generic map (
@@ -675,7 +736,8 @@ begin
generic map (
g_sim => g_sim,
g_pmbus => true,
- g_clk_freq => 8 * 10**6 -- I2C bus run at ~300kHz @ mm_clk=50MHz
+ -- I2C bus run at ~300kHz @ mm_clk=50MHz
+ g_clk_freq => 8 * 10**6
)
port map (
-- Clocks and reset
@@ -704,7 +766,8 @@ begin
mm_clk => i_mm_clk,
--mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
- mm_start => '1', -- this works
+ -- this works
+ mm_start => '1',
-- Memory-mapped clock domain
reg_temp_mosi => reg_fpga_temp_sens_mosi,
@@ -761,15 +824,19 @@ begin
u_eth : entity eth_lib.eth
generic map (
g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ -- Last two bytes set by board/FPGA ID.
+ g_init_ip_address => g_base_ip & X"0000",
g_cross_clock_domain => g_udp_offload,
g_frm_discard_en => true
)
port map (
-- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
+ -- use reset from QSYS
+ mm_rst => eth1g_mm_rst,
+ -- use mm_clk direct
+ mm_clk => i_mm_clk,
+ -- 125 MHz clock
+ eth_clk => i_tse_clk,
st_rst => eth1g_st_rst,
st_clk => eth1g_st_clk,
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
index f8a10253cf5088c77b01be22f6249b4f2881e0cb..763167c934dea02110fee30b1f62f21438fcc29d 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
@@ -32,18 +32,23 @@ entity mms_unb2_board_sens is
generic (
g_sim : boolean := false;
g_pmbus : boolean := false;
- g_clk_freq : natural := 100 * 10**6; -- clk frequency in Hz
+ -- clk frequency in Hz
+ g_clk_freq : natural := 100 * 10**6;
g_temp_high : natural := 85
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
mm_start : in std_logic;
-- Memory-mapped clock domain
- reg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
- reg_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ reg_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ -- actual ranges defined by c_mm_reg
+ reg_miso : out t_mem_miso;
-- i2c bus
scl : inout std_logic := 'Z';
@@ -55,8 +60,10 @@ entity mms_unb2_board_sens is
end mms_unb2_board_sens;
architecture str of mms_unb2_board_sens is
- constant c_sens_nof_result : natural := 4; -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
- constant c_temp_high_w : natural := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+ -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
+ constant c_sens_nof_result : natural := 4;
+ -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+ constant c_temp_high_w : natural := 7;
signal sens_err : std_logic;
signal sens_data : t_slv_8_arr(0 to c_sens_nof_result - 1);
@@ -78,7 +85,8 @@ begin
sla_out => reg_miso,
-- MM registers
- sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ sens_err => sens_err,
sens_data => sens_data,
-- Max temp threshold
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
index 8116249508a7900047234ce33af9b17cac31ab6b..a4af766e438edde09bcc2efdc3265227d7d86331 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -31,13 +31,15 @@ entity mms_unb2_board_system_info is
g_sim : boolean := false;
g_technology : natural := c_tech_arria10;
g_design_name : string;
- g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version; -- firmware version x.y
+ -- firmware version x.y
+ g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version;
g_stamp_date : natural := 0;
g_stamp_time : natural := 0;
g_stamp_svn : natural := 0;
g_design_note : string := "";
g_rom_version : natural := 1;
- g_aux : t_c_unb2_board_aux := c_unb2_board_aux -- aux contains the hardware version
+ -- aux contains the hardware version
+ g_aux : t_c_unb2_board_aux := c_unb2_board_aux
);
port (
mm_rst : in std_logic;
@@ -72,12 +74,14 @@ architecture str of mms_unb2_board_system_info is
-- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
- constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
+ -- 2^10 = 1024 addresses * 32 bits = 4 kiB
+ constant c_rom_addr_w : natural := 10;
constant c_mm_rom : t_c_mem := (latency => 1,
adr_w => c_rom_addr_w,
dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ -- = 2**adr_w
+ nof_dat => 2**c_rom_addr_w,
init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
index 9697e2b7f1f752ba2a41427bec97e98a72ec56b9..194bc14fe69c4d649dda21b52abec5601a5de656 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -37,15 +37,21 @@ entity mms_unb2_fpga_sens is
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
mm_start : in std_logic;
-- Memory-mapped clock domain
- reg_temp_mosi : in t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
- reg_temp_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
- reg_voltage_mosi : in t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
- reg_voltage_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ reg_temp_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ -- actual ranges defined by c_mm_reg
+ reg_temp_miso : out t_mem_miso;
+ -- actual ranges defined by c_mm_reg
+ reg_voltage_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ -- actual ranges defined by c_mm_reg
+ reg_voltage_miso : out t_mem_miso;
-- Temperature alarm output
temp_alarm : out std_logic
@@ -53,8 +59,10 @@ entity mms_unb2_fpga_sens is
end mms_unb2_fpga_sens;
architecture str of mms_unb2_fpga_sens is
- constant c_sens_nof_result : natural := 1; --
- constant c_temp_high_w : natural := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+ --
+ constant c_sens_nof_result : natural := 1;
+ -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+ constant c_temp_high_w : natural := 7;
signal sens_err : std_logic;
signal sens_data : t_slv_8_arr(0 to c_sens_nof_result - 1);
@@ -111,5 +119,6 @@ begin
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
-- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
- temp_alarm <= '0'; -- <= '1' WHEN (SIGNED(sens_data(0)) > SIGNED('0' & temp_high)) ELSE '0';
+ -- <= '1' WHEN (SIGNED(sens_data(0)) > SIGNED('0' & temp_high)) ELSE '0';
+ temp_alarm <= '0';
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
index 48fad46da5c7c879188216a074787a6333284c9b..46b0dfbea15361c9644648ff54cac9b1d8d9d8ab 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
@@ -41,12 +41,17 @@ entity unb2_board_clk125_pll is
);
port (
arst : in std_logic := '0';
- clk125 : in std_logic := '0'; -- connect to UniBoard ETH_clk pin (125 MHz)
+ -- connect to UniBoard ETH_clk pin (125 MHz)
+ clk125 : in std_logic := '0';
- c0_clk20 : out std_logic; -- PLL c0
- c1_clk50 : out std_logic; -- PLL c1
- c2_clk100 : out std_logic; -- PLL c2
- c3_clk125 : out std_logic; -- PLL c3
+ -- PLL c0
+ c0_clk20 : out std_logic;
+ -- PLL c1
+ c1_clk50 : out std_logic;
+ -- PLL c2
+ c2_clk100 : out std_logic;
+ -- PLL c3
+ c3_clk125 : out std_logic;
pll_locked : out std_logic
);
end unb2_board_clk125_pll;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
index 9ca4ebe75e78f0da81b3f430987fdcaf05726dee..e4445bbe7195b5725733ec242ad7f68963d65cdc 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
@@ -95,20 +95,27 @@ entity unb2_board_clk200_pll is
g_technology : natural := c_tech_arria10;
g_use_clkbuf : boolean := true;
g_use_fpll : boolean := false;
- g_operation_mode : string := "NORMAL"; -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
- g_clk200_phase_shift : string := "0"; -- default use 0 degrees, see clk200_pll.vhd for other phase values
- g_clk200p_phase_shift : string := "0" -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
+ g_operation_mode : string := "NORMAL";
+ -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ g_clk200_phase_shift : string := "0";
+ -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ g_clk200p_phase_shift : string := "0"
);
port (
-- It depends on g_sel which outputs are actually available
-- . common
arst : in std_logic := '0';
- clk200 : in std_logic := '0'; -- connect to UniBoard CLK pin
- st_clk200 : out std_logic; -- PLL c0 = g_clk200_phase_shift degrees phase offset to input clk200
+ -- connect to UniBoard CLK pin
+ clk200 : in std_logic := '0';
+ -- PLL c0 = g_clk200_phase_shift degrees phase offset to input clk200
+ st_clk200 : out std_logic;
st_rst200 : out std_logic;
- st_clk200p : out std_logic; -- PLL c1 = g_clk200p_phase_shift degrees phase offset to input clk200 (see clk200_pll.vhd from MegaWizard)
+ -- PLL c1 = g_clk200p_phase_shift degrees phase offset to input clk200 (see clk200_pll.vhd from MegaWizard)
+ st_clk200p : out std_logic;
st_rst200p : out std_logic;
- st_clk400 : out std_logic; -- PLL c2 = 0 degrees phase offset to input clk200
+ -- PLL c2 = 0 degrees phase offset to input clk200
+ st_clk400 : out std_logic;
st_rst400 : out std_logic
);
end unb2_board_clk200_pll;
@@ -171,10 +178,14 @@ begin
)
port map (
areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
+ -- 200 MHz
+ inclk0 => clk200buf,
+ -- 200 MHz
+ c0 => i_st_clk200,
+ -- 200 MHz shifted 90 degrees
+ c1 => i_st_clk200p,
+ -- 400 MHz
+ c2 => i_st_clk400,
locked => st_locked
);
end generate;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
index 70d83befad5f22b82c1e67a22ed53b6e41810b3f..45400d2a83c3042f695e86d6ee4f76fddb738e97 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
@@ -39,12 +39,17 @@ entity unb2_board_clk25_pll is
);
port (
arst : in std_logic := '0';
- clk25 : in std_logic := '0'; -- connect to UniBoard ETH_clk pin (25 MHz)
+ -- connect to UniBoard ETH_clk pin (25 MHz)
+ clk25 : in std_logic := '0';
- c0_clk20 : out std_logic; -- PLL c0
- c1_clk50 : out std_logic; -- PLL c1
- c2_clk100 : out std_logic; -- PLL c2
- c3_clk125 : out std_logic; -- PLL c3
+ -- PLL c0
+ c0_clk20 : out std_logic;
+ -- PLL c1
+ c1_clk50 : out std_logic;
+ -- PLL c2
+ c2_clk100 : out std_logic;
+ -- PLL c3
+ c3_clk125 : out std_logic;
pll_locked : out std_logic
);
end unb2_board_clk25_pll;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
index 4bacebe5afdc117f5c7fa3e7c72c887bfcc81cf9..b564130e9b17da04fa5313699ec5ddc2b558d4dd 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
@@ -33,20 +33,27 @@ use common_lib.common_pkg.all;
entity unb2_board_clk_rst is
port (
-- Reference clock and reset to SOPC system PLL
- xo_clk : in std_logic; -- reference XO clock (e.g. 25 MHz also use by PLL in SOPC)
- xo_rst_n : out std_logic; -- NOT xo_rst (e.g. to reset the SOPC with NIOS2 uP)
+ -- reference XO clock (e.g. 25 MHz also use by PLL in SOPC)
+ xo_clk : in std_logic;
+ -- NOT xo_rst (e.g. to reset the SOPC with NIOS2 uP)
+ xo_rst_n : out std_logic;
-- System clock and locked from SOPC system PLL
- sys_clk : in std_logic; -- system clock derived from the reference XO clock (e.g. 125 MHz by a PLL from SOPC with NIOS2 uP)
- sys_locked : in std_logic; -- system clock PLL locked
- sys_rst : out std_logic -- system reset released some cycles after the system clock PLL has in locked
+ -- system clock derived from the reference XO clock (e.g. 125 MHz by a PLL from SOPC with NIOS2 uP)
+ sys_clk : in std_logic;
+ -- system clock PLL locked
+ sys_locked : in std_logic;
+ -- system reset released some cycles after the system clock PLL has in locked
+ sys_rst : out std_logic
);
end unb2_board_clk_rst;
architecture str of unb2_board_clk_rst is
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
-- XO clock domain
- signal xo_rst : std_logic; -- initial reset released after some XO clock cycles
+ -- initial reset released after some XO clock cycles
+ signal xo_rst : std_logic;
-- SYS clock domain
signal sys_locked_n : std_logic;
@@ -56,11 +63,13 @@ begin
u_common_areset_xo : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => xo_clk,
out_rst => xo_rst
);
@@ -70,11 +79,13 @@ begin
u_common_areset_sys : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ -- release reset after some clock cycles when the PLL has locked
+ in_rst => sys_locked_n,
clk => sys_clk,
out_rst => sys_rst
);
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
index b37cfbaf8f11db1f8998aab9844b0589d93c76f4..bdb40e5f538af57e72b735c37d306540bd6fa226 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
@@ -32,30 +32,43 @@ use common_lib.common_pkg.all;
entity unb2_board_node_ctrl is
generic (
- g_pulse_us : natural := 125; -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- g_pulse_ms : natural := 1000; -- nof pulse_us pulses to get ms period (fixed, use less to speed up simulation)
- g_pulse_s : natural := 1000; -- nof pulse_ms pulses to get s period (fixed, use less to speed up simulation)
- g_wdi_extend_w : natural := 14 -- extend the mm_wdi_in by toggling the mm_wdi_out for about 2**(14-1)= 8 s more
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us : natural := 125;
+ -- nof pulse_us pulses to get ms period (fixed, use less to speed up simulation)
+ g_pulse_ms : natural := 1000;
+ -- nof pulse_ms pulses to get s period (fixed, use less to speed up simulation)
+ g_pulse_s : natural := 1000;
+ -- extend the mm_wdi_in by toggling the mm_wdi_out for about 2**(14-1)= 8 s more
+ g_wdi_extend_w : natural := 14
);
port (
-- MM clock domain reset
- mm_clk : in std_logic; -- MM clock
- mm_locked : in std_logic := '1'; -- MM clock PLL locked (or use default '1')
- mm_rst : out std_logic; -- MM reset released after MM clock PLL has locked
+ -- MM clock
+ mm_clk : in std_logic;
+ -- MM clock PLL locked (or use default '1')
+ mm_locked : in std_logic := '1';
+ -- MM reset released after MM clock PLL has locked
+ mm_rst : out std_logic;
-- WDI extend
- mm_wdi_in : in std_logic; -- from software running on the NIOS2 in the SOPC design
- mm_wdi_out : out std_logic; -- to FPGA pin
+ -- from software running on the NIOS2 in the SOPC design
+ mm_wdi_in : in std_logic;
+ -- to FPGA pin
+ mm_wdi_out : out std_logic;
-- Pulses
- mm_pulse_us : out std_logic; -- pulses every us
- mm_pulse_ms : out std_logic; -- pulses every ms
- mm_pulse_s : out std_logic -- pulses every s
+ -- pulses every us
+ mm_pulse_us : out std_logic;
+ -- pulses every ms
+ mm_pulse_ms : out std_logic;
+ -- pulses every s
+ mm_pulse_s : out std_logic
);
end unb2_board_node_ctrl;
architecture str of unb2_board_node_ctrl is
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
signal mm_locked_n : std_logic;
signal i_mm_rst : std_logic;
@@ -68,11 +81,13 @@ begin
u_common_areset_mm : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ -- release reset after some clock cycles when the PLL has locked
+ in_rst => mm_locked_n,
clk => mm_clk,
out_rst => i_mm_rst
);
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
index aa42e0627dc1bfdf127e7b0e0fec5afdf9881fc2..6cb65eead6a029f0e424e7a1b4c5506f5267f224 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
@@ -45,122 +45,172 @@ package unb2_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
-- *_dat_w : The default MM data width is c_word_w=32, otherwise it is specified in the record
type t_c_unb2_board_peripherals_mm_reg is record
- cross_clock_domain : boolean; -- = TRUE -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ -- = TRUE -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ cross_clock_domain : boolean;
-- 1GbE
- reg_tse_adr_w : natural; -- = 10 -- = c_tse_byte_addr_w from tse_pkg.vhd
- reg_eth_adr_w : natural; -- = 4 -- = c_eth_reg_addr_w from eth_pkg.vhd
- ram_eth_adr_w : natural; -- = 10 -- = c_eth_ram_addr_w from eth_pkg.vhd
+ -- = 10 -- = c_tse_byte_addr_w from tse_pkg.vhd
+ reg_tse_adr_w : natural;
+ -- = 4 -- = c_eth_reg_addr_w from eth_pkg.vhd
+ reg_eth_adr_w : natural;
+ -- = 10 -- = c_eth_ram_addr_w from eth_pkg.vhd
+ ram_eth_adr_w : natural;
-- pi_system_info (first word of reg_unb_system_info_adr_w is backwards compatible with the original single word PIO system info)
- reg_unb_system_info_adr_w : natural; -- = 5 -- fixed, from c_mm_reg in unb_system_info_reg
- rom_unb_system_info_adr_w : natural; -- = 10 -- fixed, from c_mm_rom in mms_unb_system_info
+ -- = 5 -- fixed, from c_mm_reg in unb_system_info_reg
+ reg_unb_system_info_adr_w : natural;
+ -- = 10 -- fixed, from c_mm_rom in mms_unb_system_info
+ rom_unb_system_info_adr_w : natural;
-- pi_reg_common
- reg_common_adr_w : natural; -- = 1 -- fixed, from c_mem_reg in mms_common_reg
+ -- = 1 -- fixed, from c_mem_reg in mms_common_reg
+ reg_common_adr_w : natural;
-- pi_ppsh
- reg_ppsh_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in ppsh_reg
+ -- = 1 -- fixed, from c_mm_reg in ppsh_reg
+ reg_ppsh_adr_w : natural;
-- pi_unb_sens
- reg_unb_sens_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in unb_sens_reg
+ -- = 3 -- fixed, from c_mm_reg in unb_sens_reg
+ reg_unb_sens_adr_w : natural;
-- pi_dpmm
- reg_dpmm_data_adr_w : natural; -- = 1 -- fixed, see dp_fifo_to_mm.vhd
- reg_dpmm_ctrl_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_fifo_to_mm_reg.vhd
+ -- = 1 -- fixed, see dp_fifo_to_mm.vhd
+ reg_dpmm_data_adr_w : natural;
+ -- = 1 -- fixed, from c_mm_reg in dp_fifo_to_mm_reg.vhd
+ reg_dpmm_ctrl_adr_w : natural;
-- pi_mmdp
- reg_mmdp_data_adr_w : natural; -- = 1 -- fixed, see dp_fifo_from_mm.vhd
- reg_mmdp_ctrl_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_fifo_from_mm_reg.vhd
+ -- = 1 -- fixed, see dp_fifo_from_mm.vhd
+ reg_mmdp_data_adr_w : natural;
+ -- = 1 -- fixed, from c_mm_reg in dp_fifo_from_mm_reg.vhd
+ reg_mmdp_ctrl_adr_w : natural;
-- pi_dp_ram_from_mm
- reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
+ -- = 1 -- fixed, see dp_ram_from_mm.vhd
+ reg_dp_ram_from_mm_adr_w : natural;
-- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
-- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
- reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
+ -- = 3 -- fixed, from c_mm_reg in epcs_reg
+ reg_epcs_adr_w : natural;
-- pi_remu
- reg_remu_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in remu_reg
+ -- = 3 -- fixed, from c_mm_reg in remu_reg
+ reg_remu_adr_w : natural;
-- pi_ddr
-- pi_ddr_capture (uses DP-MM read FIFO for data access)
- reg_ddr_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in ddr_reg
+ -- = 3 -- fixed, from c_mm_reg in ddr_reg
+ reg_ddr_adr_w : natural;
-- pi_io_ddr
- reg_io_ddr_adr_w : natural; -- = 16 -- fixed, from c_mm_reg in io_ddr (3) and in io_ddr_reg (8) that get multiplexed in on addresses 0..2, 8..15
+ -- = 16 -- fixed, from c_mm_reg in io_ddr (3) and in io_ddr_reg (8) that get multiplexed in on addresses 0..2, 8..15
+ reg_io_ddr_adr_w : natural;
-- pi_tr_nonbonded
- reg_tr_nonbonded_adr_w : natural; -- = 4 -- fixed, from c_mm_reg in tr_nonbonded_reg
+ -- = 4 -- fixed, from c_mm_reg in tr_nonbonded_reg
+ reg_tr_nonbonded_adr_w : natural;
-- pi_diagnostics
- reg_diagnostics_adr_w : natural; -- = 6 -- fixed, from c_mm_reg in diagnostics_reg
+ -- = 6 -- fixed, from c_mm_reg in diagnostics_reg
+ reg_diagnostics_adr_w : natural;
-- pi_dp_throttle
- reg_dp_throttle_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in dp_throttle_reg
+ -- = 2 -- fixed, from c_mm_reg in dp_throttle_reg
+ reg_dp_throttle_adr_w : natural;
-- pi_bsn_source
- reg_bsn_source_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in dp_bsn_source_reg.vhd
+ -- = 2 -- fixed, from c_mm_reg in dp_bsn_source_reg.vhd
+ reg_bsn_source_adr_w : natural;
-- pi_bsn_schedurer
- reg_bsn_scheduler_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_bsn_scheduler_reg.vhd
+ -- = 1 -- fixed, from c_mm_reg in dp_bsn_scheduler_reg.vhd
+ reg_bsn_scheduler_adr_w : natural;
-- pi_bsn_monitor
- reg_bsn_monitor_adr_w : natural; -- = 4 -- fixed, from c_mm_reg in dp_bsn_monitor_reg.vhd
+ -- = 4 -- fixed, from c_mm_reg in dp_bsn_monitor_reg.vhd
+ reg_bsn_monitor_adr_w : natural;
-- pi_aduh_quad (defaults for ADU)
- reg_adc_quad_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in aduh_quad_reg.vhd
+ -- = 3 -- fixed, from c_mm_reg in aduh_quad_reg.vhd
+ reg_adc_quad_adr_w : natural;
-- pi_aduh_i2c_commander (defaults for ADU)
- reg_i2c_commander_adr_w : natural; -- = 6 -- = c_i2c_cmdr_aduh_i2c_mm.control_adr_w, from i2c_commander_aduh_pkg, used to pass on commander_adr_w
- ram_i2c_protocol_adr_w : natural; -- = 13 -- = c_i2c_cmdr_aduh_i2c_mm.protocol_adr_w, from i2c_commander_aduh_pkg
- ram_i2c_result_adr_w : natural; -- = 12 -- = c_i2c_cmdr_aduh_i2c_mm.result_adr_w, from i2c_commander_aduh_pkg
+ -- = 6 -- = c_i2c_cmdr_aduh_i2c_mm.control_adr_w, from i2c_commander_aduh_pkg, used to pass on commander_adr_w
+ reg_i2c_commander_adr_w : natural;
+ -- = 13 -- = c_i2c_cmdr_aduh_i2c_mm.protocol_adr_w, from i2c_commander_aduh_pkg
+ ram_i2c_protocol_adr_w : natural;
+ -- = 12 -- = c_i2c_cmdr_aduh_i2c_mm.result_adr_w, from i2c_commander_aduh_pkg
+ ram_i2c_result_adr_w : natural;
-- pi_aduh_monitor (defaults for ADU or WG used in bn_capture)
- reg_aduh_mon_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in aduh_monitor_reg.vhd
- ram_aduh_mon_dat_w : natural; -- = 32 -- = c_sp_data_w, see node_bn_capture.vhd
- ram_aduh_mon_adr_w : natural; -- = 8 -- = ceil_log2(c_bn_capture.sp.monitor_buffer_nof_samples/c_wideband_factor), see node_bn_capture.vhd
+ -- = 2 -- fixed, from c_mm_reg in aduh_monitor_reg.vhd
+ reg_aduh_mon_adr_w : natural;
+ -- = 32 -- = c_sp_data_w, see node_bn_capture.vhd
+ ram_aduh_mon_dat_w : natural;
+ -- = 8 -- = ceil_log2(c_bn_capture.sp.monitor_buffer_nof_samples/c_wideband_factor), see node_bn_capture.vhd
+ ram_aduh_mon_adr_w : natural;
-- pi_diag_wg_wideband.py (defaults for WG used in bn_capture)
- reg_diag_wg_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in diag_wg_wideband_reg
- ram_diag_wg_dat_w : natural; -- = 8 -- defined here, see bn_capture_input.vhd
- ram_diag_wg_adr_w : natural; -- = 10 -- defined here, see bn_capture_input.vhd
+ -- = 2 -- fixed, from c_mm_reg in diag_wg_wideband_reg
+ reg_diag_wg_adr_w : natural;
+ -- = 8 -- defined here, see bn_capture_input.vhd
+ ram_diag_wg_dat_w : natural;
+ -- = 10 -- defined here, see bn_capture_input.vhd
+ ram_diag_wg_adr_w : natural;
-- pi_diag_data_buffer.py
- ram_diag_db_nof_buf : natural; -- = 16
- ram_diag_db_buf_size : natural; -- = 1024
- ram_diag_db_adr_w : natural; -- = 14 -- = ram_diag_db_nof_buf*ceil_log2(ram_diag_db_buf_size)
- reg_diag_db_adr_w : natural; -- = 5 -- 32 words for 16 streams max
+ -- = 16
+ ram_diag_db_nof_buf : natural;
+ -- = 1024
+ ram_diag_db_buf_size : natural;
+ -- = 14 -- = ram_diag_db_nof_buf*ceil_log2(ram_diag_db_buf_size)
+ ram_diag_db_adr_w : natural;
+ -- = 5 -- 32 words for 16 streams max
+ reg_diag_db_adr_w : natural;
-- pi_diag_block_gen (defaults when used with the BF for Apertif)
- reg_diag_bg_adr_w : natural; -- = 3
- ram_diag_bg_adr_w : natural; -- = 11 -- = ceil_log2(c_bf.nof_subbands*c_bf.nof_signal_paths/c_bf.nof_input_streams = 24*64/16 = 96) + ceil_log2(c_bf.nof_input_streams = 16)
+ -- = 3
+ reg_diag_bg_adr_w : natural;
+ -- = 11 -- = ceil_log2(c_bf.nof_subbands*c_bf.nof_signal_paths/c_bf.nof_input_streams = 24*64/16 = 96) + ceil_log2(c_bf.nof_input_streams = 16)
+ ram_diag_bg_adr_w : natural;
-- pi_diag_tx_seq.py
- reg_diag_tx_seq_w : natural; -- = 2
+ -- = 2
+ reg_diag_tx_seq_w : natural;
-- pi_diag_tx_seq.py
- reg_diag_rx_seq_w : natural; -- = 3
+ -- = 3
+ reg_diag_rx_seq_w : natural;
-- pi_bf_bf (defaults for the BF for Apertif)
- reg_bf_offsets_adr_w : natural; -- = 5 -- = ceil_log2(c_bf.nof_offsets = 6) + ceil_log2(c_bf.nof_bf_units = 4)
- ram_bf_weights_adr_w : natural; -- = 16 -- = ceil_log2(c_bf.nof_bf_units*c_bf.nof_signal_paths*c_bf.nof_weights = 4 * 64 * 256 = 65536)
- ram_st_sst_bf_adr_w : natural; -- = 11 -- = ceil_log2(c_bf.nof_bf_units*c_bf.stat_data_sz*c_bf.nof_weights = 4 * 2 * 256 = 2048)
+ -- = 5 -- = ceil_log2(c_bf.nof_offsets = 6) + ceil_log2(c_bf.nof_bf_units = 4)
+ reg_bf_offsets_adr_w : natural;
+ -- = 16 -- = ceil_log2(c_bf.nof_bf_units*c_bf.nof_signal_paths*c_bf.nof_weights = 4 * 64 * 256 = 65536)
+ ram_bf_weights_adr_w : natural;
+ -- = 11 -- = ceil_log2(c_bf.nof_bf_units*c_bf.stat_data_sz*c_bf.nof_weights = 4 * 2 * 256 = 2048)
+ ram_st_sst_bf_adr_w : natural;
-- pi_mdio
- reg_mdio_adr_w : natural; -- = 3
+ -- = 3
+ reg_mdio_adr_w : natural;
-- dp_offload
- reg_dp_offload_tx_adr_w : natural; -- = 1
+ -- = 1
+ reg_dp_offload_tx_adr_w : natural;
-- pi_unb_fpga_sensors
- reg_fpga_temp_sens_adr_w : natural; -- = 3
- reg_fpga_voltage_sens_adr_w : natural; -- = 4
+ -- = 3
+ reg_fpga_temp_sens_adr_w : natural;
+ -- = 4
+ reg_fpga_voltage_sens_adr_w : natural;
-- pi_unb_pmbus
- reg_unb_pmbus_adr_w : natural; -- = 5
+ -- = 5
+ reg_unb_pmbus_adr_w : natural;
end record;
constant c_unb2_board_peripherals_mm_reg_default : t_c_unb2_board_peripherals_mm_reg := (true, 10, 4, 10, 5, 10, 1, 1, 3, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1, 3, 4, 5);
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
index 20f69332252ac3a14fc387c19ee4aae9ffb0b673..d2057c9f252acb96244ec761530a1f13b779d94a 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
@@ -28,32 +28,50 @@ use dp_lib.dp_stream_pkg.all;
package unb2_board_pkg is
-- UniBoard
- constant c_unb2_board_nof_node : natural := 4; -- number of nodes on UniBoard
- constant c_unb2_board_nof_node_w : natural := 2; -- = ceil_log2(c_unb2_board_nof_node)
- constant c_unb2_board_nof_chip : natural := c_unb2_board_nof_node; -- = 4
- constant c_unb2_board_nof_chip_w : natural := 2; -- = ceil_log2(c_unb2_board_nof_chip)
- constant c_unb2_board_nof_ddr : natural := 2; -- each node has 2 DDR modules
+ -- number of nodes on UniBoard
+ constant c_unb2_board_nof_node : natural := 4;
+ -- = ceil_log2(c_unb2_board_nof_node)
+ constant c_unb2_board_nof_node_w : natural := 2;
+ -- = 4
+ constant c_unb2_board_nof_chip : natural := c_unb2_board_nof_node;
+ -- = ceil_log2(c_unb2_board_nof_chip)
+ constant c_unb2_board_nof_chip_w : natural := 2;
+ -- each node has 2 DDR modules
+ constant c_unb2_board_nof_ddr : natural := 2;
-- Subrack
- constant c_unb2_board_nof_uniboard : natural := 4; -- nof UniBoard in a subrack
- constant c_unb2_board_nof_uniboard_w : natural := 6; -- Only 2 required for 4 boards; full width is 6.
+ -- nof UniBoard in a subrack
+ constant c_unb2_board_nof_uniboard : natural := 4;
+ -- Only 2 required for 4 boards; full width is 6.
+ constant c_unb2_board_nof_uniboard_w : natural := 6;
-- Clock frequencies
- constant c_unb2_board_ext_clk_freq_200M : natural := 200 * 10**6; -- external clock, SMA clock
- constant c_unb2_board_eth_clk_freq_25M : natural := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
- constant c_unb2_board_eth_clk_freq_125M : natural := 125 * 10**6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
- constant c_unb2_board_tse_clk_freq : natural := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
- constant c_unb2_board_cal_clk_freq : natural := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_25M : natural := 25 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_50M : natural := 50 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_100M : natural := 100 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_125M : natural := 125 * 10**6; -- clock derived from ETH_clk by PLL
+ -- external clock, SMA clock
+ constant c_unb2_board_ext_clk_freq_200M : natural := 200 * 10**6;
+ -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
+ constant c_unb2_board_eth_clk_freq_25M : natural := 25 * 10**6;
+ -- fixed 125 MHz ETH XO clock used as direct clock for TSE
+ constant c_unb2_board_eth_clk_freq_125M : natural := 125 * 10**6;
+ -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
+ constant c_unb2_board_tse_clk_freq : natural := 125 * 10**6;
+ -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
+ constant c_unb2_board_cal_clk_freq : natural := 40 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_25M : natural := 25 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_50M : natural := 50 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_100M : natural := 100 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_125M : natural := 125 * 10**6;
-- I2C
- constant c_unb2_board_reg_sens_adr_w : natural := 3; -- must match ceil_log2(c_mm_nof_dat) in unb2_board_sens_reg.vhd
+ -- must match ceil_log2(c_mm_nof_dat) in unb2_board_sens_reg.vhd
+ constant c_unb2_board_reg_sens_adr_w : natural := 3;
-- ETH
- constant c_unb2_board_nof_eth : natural := 2; -- number of ETH channels per node
+ -- number of ETH channels per node
+ constant c_unb2_board_nof_eth : natural := 2;
-- CONSTANT RECORD DECLARATIONS ---------------------------------------------
@@ -72,15 +90,19 @@ package unb2_board_pkg is
end record;
--CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (2, 24, 3); -- per node: 2 buses with 24 channels
- constant c_unb2_board_tr_back : t_c_unb2_board_tr := (1, 24, 3); -- per node: 1 buses with 24 channels (testing)
+ -- per node: 1 buses with 24 channels (testing)
+ constant c_unb2_board_tr_back : t_c_unb2_board_tr := (1, 24, 3);
--CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (2, 12, 3); -- per node: 2 buses with 24 channels (testing)
--CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (2, 4, 3); -- per node: 2 buses with 24 channels (testing)
- constant c_unb2_board_tr_ring : t_c_unb2_board_tr := (2, 12, 0); -- per node: 2 buses with 12 channels
+ -- per node: 2 buses with 12 channels
+ constant c_unb2_board_tr_ring : t_c_unb2_board_tr := (2, 12, 0);
--CONSTANT c_unb2_board_tr_ring : t_c_unb2_board_tr := (2, 4, 0); -- per node: 2 buses with 12 channels (testing)
- constant c_unb2_board_tr_qsfp : t_c_unb2_board_tr := (6, 4, 6); -- per node: 6 buses with 4 channels
- constant c_unb2_board_tr_qsfp_nof_leds : natural := c_unb2_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
+ -- per node: 6 buses with 4 channels
+ constant c_unb2_board_tr_qsfp : t_c_unb2_board_tr := (6, 4, 6);
+ -- 2 leds per qsfp
+ constant c_unb2_board_tr_qsfp_nof_leds : natural := c_unb2_board_tr_qsfp.nof_bus * 2;
type t_unb2_board_qsfp_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2_board_tr_qsfp.bus_w - 1 downto 0);
type t_unb2_board_ring_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2_board_tr_ring.bus_w - 1 downto 0);
@@ -90,12 +112,18 @@ package unb2_board_pkg is
-- Test IO Interface
type t_c_unb2_board_testio is record
- tst_w : natural; -- = nof tst = 2; [tst_w-1 +tst_lo : tst_lo] = [5:4],
- led_w : natural; -- = nof led = 2; [led_w-1 +led_lo : led_lo] = [3:2],
- jmp_w : natural; -- = nof jmp = 2; [jmp_w-1 +jmp_lo : jmp_lo] = [1:0],
- tst_lo : natural; -- = 2;
- led_lo : natural; -- = 2;
- jmp_lo : natural; -- = 0;
+ -- = nof tst = 2; [tst_w-1 +tst_lo : tst_lo] = [5:4],
+ tst_w : natural;
+ -- = nof led = 2; [led_w-1 +led_lo : led_lo] = [3:2],
+ led_w : natural;
+ -- = nof jmp = 2; [jmp_w-1 +jmp_lo : jmp_lo] = [1:0],
+ jmp_w : natural;
+ -- = 2;
+ tst_lo : natural;
+ -- = 2;
+ led_lo : natural;
+ -- = 0;
+ jmp_lo : natural;
end record;
constant c_unb2_board_testio : t_c_unb2_board_testio := (2, 2, 2, 2, 2, 0);
@@ -103,10 +131,14 @@ package unb2_board_pkg is
constant c_unb2_board_testio_led_red : natural := c_unb2_board_testio.led_lo + 1;
type t_c_unb2_board_aux is record
- version_w : natural; -- = 2;
- id_w : natural; -- = 8; -- 6+2 bits wide = total node ID for up to 64 UniBoards in a system and 4 nodes per board
- chip_id_w : natural; -- = 2; -- board node ID for the 4 FPGA nodes on a UniBoard
- testio_w : natural; -- = 6;
+ -- = 2;
+ version_w : natural;
+ -- = 8; -- 6+2 bits wide = total node ID for up to 64 UniBoards in a system and 4 nodes per board
+ id_w : natural;
+ -- = 2; -- board node ID for the 4 FPGA nodes on a UniBoard
+ chip_id_w : natural;
+ -- = 6;
+ testio_w : natural;
testio : t_c_unb2_board_testio;
end record;
@@ -115,8 +147,10 @@ package unb2_board_pkg is
type t_e_unb2_board_node is (e_any);
type t_unb2_board_fw_version is record
- hi : natural; -- = 0..15
- lo : natural; -- = 0..15, firmware version is: hi.lo
+ -- = 0..15
+ hi : natural;
+ -- = 0..15, firmware version is: hi.lo
+ lo : natural;
end record;
constant c_unb2_board_fw_version : t_unb2_board_fw_version := (0, 0);
@@ -127,19 +161,27 @@ package unb2_board_pkg is
-- . If no I2C bus arbitration or clock stretching is needed then the SCL only needs to be output.
-- . Can also be used for a PHY Management Data IO interface with serial clock MDC and serial data MDIO
type t_unb2_board_i2c_inout is record
- scl : std_logic; -- serial clock
- sda : std_logic; -- serial data
+ -- serial clock
+ scl : std_logic;
+ -- serial data
+ sda : std_logic;
end record;
-- System info
type t_c_unb2_board_system_info is record
- version : natural; -- UniBoard board HW version (2 bit value)
- id : natural; -- UniBoard FPGA node id (8 bit value)
+ -- UniBoard board HW version (2 bit value)
+ version : natural;
+ -- UniBoard FPGA node id (8 bit value)
+ id : natural;
-- Derived ID info:
- bck_id : natural; -- = id[7:2], ID part from back plane
- chip_id : natural; -- = id[1:0], ID part from UniBoard
- node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
- is_node2 : natural; -- 1 for Node 2, else 0.
+ -- = id[7:2], ID part from back plane
+ bck_id : natural;
+ -- = id[1:0], ID part from UniBoard
+ chip_id : natural;
+ -- = id[1:0], node ID: 0, 1, 2 or 3
+ node_id : natural;
+ -- 1 for Node 2, else 0.
+ is_node2 : natural;
end record;
function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
index 45987424f355bbc7e5349362e411a7b0c149e1f6..9347fe88b4c15c6882dd3ce38f5b3b4301c9612d 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
@@ -35,7 +35,8 @@ entity unb2_board_pmbus_ctrl is
port (
rst : in std_logic;
clk : in std_logic;
- start : in std_logic; -- pulse to start the I2C sequence to read out the sensors
+ -- pulse to start the I2C sequence to read out the sensors
+ start : in std_logic;
out_dat : out std_logic_vector(c_byte_w - 1 downto 0);
out_val : out std_logic;
in_dat : in std_logic_vector(c_byte_w - 1 downto 0);
@@ -68,7 +69,8 @@ architecture rtl of unb2_board_pmbus_ctrl is
-- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
-- Assume clk <= 200 MHz, so 5 ns period. Hence timeout of 4000 is enough.
- constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
+ -- wait 16 * 256 = 4096 clk periods
+ constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16);
constant c_SEQ : t_SEQUENCE := (
-- SMBUS_READ_BYTE , LOC_POWER_CORE, LP_VOUT_MODE,
@@ -107,9 +109,11 @@ architecture rtl of unb2_board_pmbus_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
+ -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
+ );
- constant c_seq_len : natural := c_SEQ'length - 1; -- upto SMBUS_C_END, the SMBUS_C_NOP is dummy to allow sufficient seq_cnt range
+ -- upto SMBUS_C_END, the SMBUS_C_NOP is dummy to allow sufficient seq_cnt range
+ constant c_seq_len : natural := c_SEQ'length - 1;
-- The protocol list c_SEQ yields a list of g_nof_result=14 result bytes:
-- . expected SMBUS_READ_BYTE -> rdbyte, ok=0
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
index db1d2a02523b0507df351a6a312d529c7a741251..5c99c08d8f6f97ef8d3c6de77db7e4ef0ee2d701 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
@@ -66,10 +66,14 @@ use dp_lib.dp_stream_pkg.all;
entity unb2_board_qsfp_leds is
generic (
- g_sim : boolean := false; -- when true speed up led toggling in simulation
- g_factory_image : boolean := false; -- distinguish factory image and user images
- g_nof_qsfp : natural := 6; -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us : natural := 200 -- nof clk cycles to get us period
+ -- when true speed up led toggling in simulation
+ g_sim : boolean := false;
+ -- distinguish factory image and user images
+ g_factory_image : boolean := false;
+ -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_nof_qsfp : natural := 6;
+ -- nof clk cycles to get us period
+ g_pulse_us : natural := 200
);
port (
rst : in std_logic;
@@ -89,8 +93,10 @@ entity unb2_board_qsfp_leds is
end unb2_board_qsfp_leds;
architecture str of unb2_board_qsfp_leds is
- constant c_nof_ms : natural := sel_a_b(g_sim, 1, 100); -- force off for c_nof_ms and then on for at least c_nof_ms
- constant c_nof_lanes : natural := g_nof_qsfp * c_quad; -- number of transceiver lanes, fixed 4 per Quad-SFP cage
+ -- force off for c_nof_ms and then on for at least c_nof_ms
+ constant c_nof_ms : natural := sel_a_b(g_sim, 1, 100);
+ -- number of transceiver lanes, fixed 4 per Quad-SFP cage
+ constant c_nof_lanes : natural := g_nof_qsfp * c_quad;
signal i_pulse_ms : std_logic;
signal i_pulse_s : std_logic;
@@ -108,9 +114,12 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ -- nof clk cycles to get us period
+ g_pulse_us => g_pulse_us,
+ -- nof pulse_us pulses to get ms period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000),
+ -- nof pulse_ms pulses to get s period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000)
)
port map (
rst => rst,
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
index 18a16b5aaba0e355cf70850c8564d86ccc50cdaa..dd622223f41fb03c7e52106bfabab455ee679639 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
@@ -28,9 +28,11 @@ entity unb2_board_sens is
generic (
g_sim : boolean := false;
g_pmbus : boolean := false;
- g_clk_freq : natural := 100 * 10**6; -- clk frequency in Hz
+ -- clk frequency in Hz
+ g_clk_freq : natural := 100 * 10**6;
g_temp_high : natural := 85;
- g_sens_nof_result : natural := 4 -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
+ -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
+ g_sens_nof_result : natural := 4
);
port (
rst : in std_logic;
@@ -48,8 +50,10 @@ end entity;
architecture str of unb2_board_sens is
-- I2C clock rate settings
- constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
- constant c_sens_comma_w : natural := 0; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
+ -- define I2C clock rate
+ constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6));
+ -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
+ constant c_sens_comma_w : natural := 0;
-- 0 = no comma time
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
index da90d846f87364a7d68931a44fd5d93028a51c8d..56e91f4201b37e760e2d1830e58e5f8710c0bc31 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
@@ -35,7 +35,8 @@ entity unb2_board_sens_ctrl is
port (
rst : in std_logic;
clk : in std_logic;
- start : in std_logic; -- pulse to start the I2C sequence to read out the sensors
+ -- pulse to start the I2C sequence to read out the sensors
+ start : in std_logic;
out_dat : out std_logic_vector(c_byte_w - 1 downto 0);
out_val : out std_logic;
in_dat : in std_logic_vector(c_byte_w - 1 downto 0);
@@ -51,14 +52,17 @@ end entity;
architecture rtl of unb2_board_sens_ctrl is
-- I2C slave addresses of the devices on the I2C bus on UniBoard
- constant ETH_MAX1617_ADR : natural := 16#29#; -- ETH temperature sensor
- constant FPGA_TMP451_ADR : natural := 16#4C#; -- FPGA temperature sensor
+ -- ETH temperature sensor
+ constant ETH_MAX1617_ADR : natural := 16#29#;
+ -- FPGA temperature sensor
+ constant FPGA_TMP451_ADR : natural := 16#4C#;
type t_SEQUENCE is array (natural range <>) of natural;
-- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
-- Assume clk <= 200 MHz, so 5 ns period. Hence timeout of 4000 is enough.
- constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
+ -- wait 16 * 256 = 4096 clk periods
+ constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16);
constant c_SEQ : t_SEQUENCE := (
SMBUS_READ_BYTE , ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
@@ -69,9 +73,11 @@ architecture rtl of unb2_board_sens_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
+ -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
+ );
- constant c_seq_len : natural := c_SEQ'length - 1; -- upto SMBUS_C_END, the SMBUS_C_NOP is dummy to allow sufficient seq_cnt range
+ -- upto SMBUS_C_END, the SMBUS_C_NOP is dummy to allow sufficient seq_cnt range
+ constant c_seq_len : natural := c_SEQ'length - 1;
-- The protocol list c_SEQ yields a list of g_nof_result=14 result bytes:
-- . expected SMBUS_READ_BYTE -> rdbyte, ok=0
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
index 9790dc3ea0f4d588f779a2cbbc1b52487596c100..e3a5015a6c5a89fb5e2548c9a8d42a1391b887aa 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
@@ -72,12 +72,16 @@ entity unb2_board_sens_reg is
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers
sens_err : in std_logic := '0';
@@ -91,12 +95,14 @@ end unb2_board_sens_reg;
architecture rtl of unb2_board_sens_reg is
-- Define the actual size of the MM slave register
- constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
+ -- +1 to fit user set temp_high one additional address
+ constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1;
-- +1 to fit sens_err in the last address
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_mm_nof_dat,
init_sl => '0');
@@ -139,14 +145,17 @@ begin
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
-- no need to capture sens_data, it is not critical if the sens_data happens to be read just before and after an I2C access occurred
if vA < g_sens_nof_result then
sla_out.rddata <= RESIZE_MEM_DATA(sens_data(vA)(c_byte_w - 1 downto 0));
elsif vA = g_sens_nof_result then
- sla_out.rddata(0) <= sens_err; -- only valid for node2
+ -- only valid for node2
+ sla_out.rddata(0) <= sens_err;
else
sla_out.rddata(6 downto 0) <= i_temp_high;
end if;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
index c3958aa4075c5c30ba82ba3ebb60a095c07d8833..46d445a6ed908106f3cd3a4b832d81bd948985ae 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
@@ -33,8 +33,10 @@ use technology_lib.technology_pkg.all;
entity unb2_board_system_info is
generic (
g_sim : boolean := false;
- g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version; -- firmware version x.y (4b.4b)
- g_aux : t_c_unb2_board_aux := c_unb2_board_aux; -- aux contains the hardware version
+ -- firmware version x.y (4b.4b)
+ g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version;
+ -- aux contains the hardware version
+ g_aux : t_c_unb2_board_aux := c_unb2_board_aux;
g_rom_version: natural := 1;
g_technology : natural := c_tech_arria10
);
@@ -43,10 +45,14 @@ entity unb2_board_system_info is
hw_version : in std_logic_vector(g_aux.version_w - 1 downto 0);
id : in std_logic_vector(g_aux.id_w - 1 downto 0);
info : out std_logic_vector(c_word_w - 1 downto 0);
- bck_id : out std_logic_vector(c_unb2_board_nof_uniboard_w - 1 downto 0); -- ID[7:2]
- chip_id : out std_logic_vector(c_unb2_board_nof_chip_w - 1 downto 0); -- ID[1:0]
- node_id : out std_logic_vector(c_unb2_board_nof_node_w - 1 downto 0); -- ID[1:0]
- is_node2 : out std_logic -- '1' for Node 2, else '0'.
+ -- ID[7:2]
+ bck_id : out std_logic_vector(c_unb2_board_nof_uniboard_w - 1 downto 0);
+ -- ID[1:0]
+ chip_id : out std_logic_vector(c_unb2_board_nof_chip_w - 1 downto 0);
+ -- ID[1:0]
+ node_id : out std_logic_vector(c_unb2_board_nof_node_w - 1 downto 0);
+ -- '1' for Node 2, else '0'.
+ is_node2 : out std_logic
);
end unb2_board_system_info;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
index 2b7a13332c5803c8e7a09da72b6fbb027358d1e5..a5de5323e9efb9fce7aa969756effee14d999175 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -72,21 +72,27 @@ entity unb2_board_system_info_reg is
end unb2_board_system_info_reg;
architecture rtl of unb2_board_system_info_reg is
- constant c_nof_fixed_regs : natural := 2; -- info, use_phy
- constant c_nof_design_name_regs : natural := 13; -- design_name
- constant c_nof_stamp_regs : natural := 3; -- date, time, svn rev
- constant c_nof_design_note_regs : natural := 13; -- note
+ -- info, use_phy
+ constant c_nof_fixed_regs : natural := 2;
+ -- design_name
+ constant c_nof_design_name_regs : natural := 13;
+ -- date, time, svn rev
+ constant c_nof_stamp_regs : natural := 3;
+ -- note
+ constant c_nof_design_note_regs : natural := 13;
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs;
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_nof_regs,
init_sl => '0');
constant c_use_phy_w : natural := 8;
- constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
+ -- Unused but keep for compatibillity
+ constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0');
constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
@@ -103,8 +109,10 @@ begin
-- Read access: get register value
if sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
vA := TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0));
if vA = 0 then
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
index e09adb5ff956c56a6a0ad91728c26da6f7fd03e3..a21c7de01379cc56010c89b8d0f5d47bc382d14a 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
@@ -37,7 +37,8 @@ entity unb2_board_wdi_extend is
port (
rst : in std_logic;
clk : in std_logic;
- pulse_ms : in std_logic; -- pulses every 1 ms
+ -- pulses every 1 ms
+ pulse_ms : in std_logic;
wdi_in : in std_logic;
wdi_out : out std_logic
);
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
index fa05af1d4f06f94cf92b05921391eaadd7b20ab7..5566944d7ac79f99cdc039ee8f0b994a06b48d0f 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
@@ -31,12 +31,16 @@ use common_lib.common_mem_pkg.all;
entity unb2_board_wdi_reg is
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
wdi_override : out std_logic
@@ -47,12 +51,14 @@ architecture rtl of unb2_board_wdi_reg is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 1,
init_sl => '0');
-- For safety, WDI override requires the following word to be written:
- constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
+ -- "Boot factory"
+ constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7";
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -75,7 +81,8 @@ begin
else
wdi_override <= '0';
end if;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
index 049c7da72e89a2425d552442030f2e3bf2964138..b3c014a6b25a859a372316d7f0f001937101441f 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
@@ -38,16 +38,22 @@ entity unb2_fpga_sens_reg is
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
start : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_temp_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_temp_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_temp_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_temp_out : out t_mem_miso;
- sla_voltage_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_voltage_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_voltage_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_voltage_out : out t_mem_miso;
-- MM registers
--sens_err : IN STD_LOGIC := '0';
@@ -61,7 +67,8 @@ end unb2_fpga_sens_reg;
architecture str of unb2_fpga_sens_reg is
--SIGNAL i_temp_high : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
- temp_high <= (others => '0'); -- i_temp_high;
+ -- i_temp_high;
+ temp_high <= (others => '0');
u_fpga_sense: entity fpga_sense_lib.fpga_sense
generic map (
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index 3449629f924542e11912156b5b8a71b0cbca0838..2b266f7b1b5ee61e1264fe427acdbf819270fa7d 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -39,7 +39,8 @@ use common_lib.tb_common_pkg.all;
use common_lib.tb_common_mem_pkg.all;
architecture tb of tb_mms_unb2_board_sens is
- constant c_sim : boolean := true; -- FALSE;
+ -- FALSE;
+ constant c_sim : boolean := true;
constant c_repeat : natural := 2;
constant c_clk_freq : natural := 100 * 10**6;
constant c_clk_period : time := (10**9 / c_clk_freq) * 1 ns;
@@ -47,19 +48,27 @@ architecture tb of tb_mms_unb2_board_sens is
-- Model I2C sensor slaves as on the UniBoard
constant c_temp_high : natural := 85;
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard --> hot swap = 5010 mAmpere (167)
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard --> hot swap = 48000 mVolt (120)
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard --> hot swap = 5010 mAmpere (167)
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard --> hot swap = 48000 mVolt (120)
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
constant c_sens_nof_result : natural := 4 + 1;
- constant c_sens_expected : t_natural_arr(0 to c_sens_nof_result - 1) := (60, 40, 167, 120, 0); -- 4 bytes as read by c_SEQ in unb2_board_sens_ctrl + sens_err
+ -- 4 bytes as read by c_SEQ in unb2_board_sens_ctrl + sens_err
+ constant c_sens_expected : t_natural_arr(0 to c_sens_nof_result - 1) := (60, 40, 167, 120, 0);
signal tb_end : std_logic := '0';
signal clk : std_logic := '0';
@@ -80,15 +89,18 @@ begin
clk <= (not clk) or tb_end after c_clk_period / 2;
-- I2C bus
- scl <= 'H'; -- model I2C pull up
- sda <= 'H'; -- model I2C pull up, use '0' and '1' to verify sens_err
+ -- model I2C pull up
+ scl <= 'H';
+ -- model I2C pull up, use '0' and '1' to verify sens_err
+ sda <= 'H';
scl <= scl_stretch;
sens_clk_stretch : process (scl)
begin
if falling_edge(scl) then
- scl_stretch <= '0', 'Z' after 50 ns; -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ scl_stretch <= '0', 'Z' after 50 ns;
end if;
end process;
@@ -114,7 +126,8 @@ begin
-- read I2C result data
for I in 0 to c_sens_nof_result - 1 loop
- proc_mem_mm_bus_rd(I, clk, reg_miso, reg_mosi); -- read sens_data
+ -- read sens_data
+ proc_mem_mm_bus_rd(I, clk, reg_miso, reg_mosi);
end loop;
proc_common_wait_some_cycles(clk, 1000);
@@ -131,7 +144,8 @@ begin
-- Verify sensor data
p_verify : process
begin
- wait until rising_edge(clk); -- Added this line to avoid warning: (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+ -- Added this line to avoid warning: (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+ wait until rising_edge(clk);
proc_common_wait_until_high(clk, sens_val);
assert TO_UINT(sens_dat) = c_sens_expected(0) report "Wrong FPGA temperature value" severity ERROR;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
index bd1504ec133b48c2ee0a1855949db6f37474baa8..0d0226a3a48790a33871cfa9af9889971318ab99 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
@@ -34,7 +34,8 @@ entity tb_unb2_board_clk125_pll is
end tb_unb2_board_clk125_pll;
architecture tb of tb_unb2_board_clk125_pll is
- constant c_ext_clk_period : time := 8 ns; -- 125 MHz
+ -- 125 MHz
+ constant c_ext_clk_period : time := 8 ns;
signal tb_end : std_logic := '0';
signal ext_clk : std_logic := '0';
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
index ae4e087f1ebbb885fdc524cf39c36ecfaae6575c..f98378e81605659d66785575deb3aa169b325e87 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
@@ -34,7 +34,8 @@ entity tb_unb2_board_clk200_pll is
end tb_unb2_board_clk200_pll;
architecture tb of tb_unb2_board_clk200_pll is
- constant c_ext_clk_period : time := 5 ns; -- 200 MHz
+ -- 200 MHz
+ constant c_ext_clk_period : time := 5 ns;
constant c_clk_vec_w : natural := 6;
constant c_clk_div : natural := 32;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
index b8ea88958d0d5715d52945bb2c636f11ca860615..b0890241ff7278a9e7a7934acc39b98606fcc0ce 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
@@ -34,7 +34,8 @@ entity tb_unb2_board_clk25_pll is
end tb_unb2_board_clk25_pll;
architecture tb of tb_unb2_board_clk25_pll is
- constant c_ext_clk_period : time := 40 ns; -- 25 MHz
+ -- 25 MHz
+ constant c_ext_clk_period : time := 40 ns;
signal tb_end : std_logic := '0';
signal ext_clk : std_logic := '0';
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
index 1d6125db58dc61776f1aa9f906a18959ecabfcde..726f258c911cea94a772e1fea69a0d9f78d8eace 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
@@ -28,21 +28,30 @@ entity tb_unb2_board_node_ctrl is
end tb_unb2_board_node_ctrl;
architecture tb of tb_unb2_board_node_ctrl is
- constant c_scale : natural := 100; -- scale to speed up simulation
+ -- scale to speed up simulation
+ constant c_scale : natural := 100;
- constant c_xo_clk_period : time := 1 us; -- 1 MHz XO, slow XO to speed up simulation
- constant c_mm_clk_period : time := c_xo_clk_period / 5; -- 5 MHz PLL output from XO reference
+ -- 1 MHz XO, slow XO to speed up simulation
+ constant c_xo_clk_period : time := 1 us;
+ -- 5 MHz PLL output from XO reference
+ constant c_mm_clk_period : time := c_xo_clk_period / 5;
constant c_mm_locked_time : time := 10 us;
- constant c_pulse_us : natural := 5; -- nof 5 MHz clk cycles to get us period
- constant c_pulse_ms : natural := 1000 / c_scale; -- nof pulse_us pulses to get ms period
- constant c_pulse_s : natural := 1000; -- nof pulse_ms pulses to get s period
+ -- nof 5 MHz clk cycles to get us period
+ constant c_pulse_us : natural := 5;
+ -- nof pulse_us pulses to get ms period
+ constant c_pulse_ms : natural := 1000 / c_scale;
+ -- nof pulse_ms pulses to get s period
+ constant c_pulse_s : natural := 1000;
- constant c_wdi_extend_w : natural := 14; -- extend wdi by about 2**(14-1)= 8 s (as defined by c_pulse_ms)
- constant c_wdi_period : time := 1000 ms; -- wdi toggle after c_wdi_period
+ -- extend wdi by about 2**(14-1)= 8 s (as defined by c_pulse_ms)
+ constant c_wdi_extend_w : natural := 14;
+ -- wdi toggle after c_wdi_period
+ constant c_wdi_period : time := 1000 ms;
-- Use c_sw_period=40000 ms to show that the c_wdi_extend_w=5 is not enough, the WD will kick in when the sw is off during reload
- constant c_sw_period : time := 40000 ms; -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
+ -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
+ constant c_sw_period : time := 40000 ms;
-- Use c_sw_period=10000 ms to show that the c_wdi_extend_w=5 is enough, the WD will not kick in when the sw is off during reload
--CONSTANT c_sw_period : TIME := 6000 ms; -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
@@ -65,10 +74,13 @@ begin
mm_clk <= not mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_locked_time;
- wdi <= not wdi after c_wdi_period / c_scale; -- wd interrupt
- sw <= not sw after c_sw_period / c_scale; -- sw active / reload
+ -- wd interrupt
+ wdi <= not wdi after c_wdi_period / c_scale;
+ -- sw active / reload
+ sw <= not sw after c_sw_period / c_scale;
- wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
+ -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
+ wdi_in <= wdi and sw;
dut : entity work.unb2_board_node_ctrl
generic map (
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
index 2a4f41e54767bb5b341bc1677d6083e49cee22ff..581a320642ccd6e516f1fff723614c1383a0a1e2 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
@@ -140,10 +140,14 @@ begin
u_unb2_factory_qsfp_leds : entity work.unb2_board_qsfp_leds
generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ -- when true speed up led toggling in simulation
+ g_sim => true,
+ -- distinguish factory image and user images
+ g_factory_image => true,
+ -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_nof_qsfp => c_nof_qsfp,
+ -- nof clk cycles to get us period
+ g_pulse_us => c_nof_clk_per_us
)
port map (
rst => rst,
@@ -163,10 +167,14 @@ begin
u_unb2_user_qsfp_leds : entity work.unb2_board_qsfp_leds
generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ -- when true speed up led toggling in simulation
+ g_sim => true,
+ -- distinguish factory image and user images
+ g_factory_image => false,
+ -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_nof_qsfp => c_nof_qsfp,
+ -- nof clk cycles to get us period
+ g_pulse_us => c_nof_clk_per_us
)
port map (
rst => rst,
diff --git a/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
index 24d2ecc45e73c420bdd45d639c7d0ce09edbc2ad..fe28b02650f10eaee12bbcebc6a613de32a03891 100644
--- a/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
+++ b/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
@@ -31,12 +31,16 @@ use work.unb2_board_pkg.all;
entity unb2_board_10gbe is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 1; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 1;
g_technology : natural := c_tech_arria10;
g_nof_macs : natural;
- g_tx_fifo_fill : natural := 10; -- Release tx packet only when sufficiently data is available,
- g_tx_fifo_size : natural := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
- g_rx_fifo_size : natural := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ -- Release tx packet only when sufficiently data is available,
+ g_tx_fifo_fill : natural := 10;
+ -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ g_tx_fifo_size : natural := 256;
+ -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ g_rx_fifo_size : natural := 256;
g_word_alignment_padding : boolean := false
);
port (
@@ -49,7 +53,8 @@ entity unb2_board_10gbe is
reg_mac_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_mac_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi := c_mem_mosi_rst; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_eth10g_miso : out t_mem_miso;
-- DP interface
@@ -98,9 +103,12 @@ begin
port map (
-- Transceiver PLL reference clock
tr_ref_clk_644 => tr_ref_clk,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => tr_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => tr_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156,
-- MM interface
mm_rst => mm_rst,
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
index f2b16a715495109a68ad8c1939b70094532de969..711af13379348cd2940da746fc85f444665d1b11 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
@@ -1,90 +1,172 @@
component ddr4_micron46_mbIIskew is
port (
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic; -- readdatavalid
- mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
- mmr_slave_read_0 : in std_logic := 'X'; -- read
- mmr_slave_write_0 : in std_logic := 'X'; -- write
- mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
- mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
- mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
- mmr_slave_readdatavalid_0 : out std_logic; -- readdatavalid
- emif_usr_clk : out std_logic; -- clk
- emif_usr_reset_n : out std_logic; -- reset_n
- global_reset_n : in std_logic := 'X'; -- reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- pll_ref_clk : in std_logic := 'X'; -- clk
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic -- local_cal_fail
+ -- waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- read
+ amm_read_0 : in std_logic := 'X';
+ -- write
+ amm_write_0 : in std_logic := 'X';
+ -- address
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X');
+ -- readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X');
+ -- burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X');
+ -- byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X');
+ -- readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- waitrequest
+ mmr_slave_waitrequest_0 : out std_logic;
+ -- read
+ mmr_slave_read_0 : in std_logic := 'X';
+ -- write
+ mmr_slave_write_0 : in std_logic := 'X';
+ -- address
+ mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X');
+ -- readdata
+ mmr_slave_readdata_0 : out std_logic_vector(31 downto 0);
+ -- writedata
+ mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- burstcount
+ mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X');
+ -- beginbursttransfer
+ mmr_slave_beginbursttransfer_0 : in std_logic := 'X';
+ -- readdatavalid
+ mmr_slave_readdatavalid_0 : out std_logic;
+ -- clk
+ emif_usr_clk : out std_logic;
+ -- reset_n
+ emif_usr_reset_n : out std_logic;
+ -- reset_n
+ global_reset_n : in std_logic := 'X';
+ -- mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X');
+ -- mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- oct_rzqin
+ oct_rzqin : in std_logic := 'X';
+ -- clk
+ pll_ref_clk : in std_logic := 'X';
+ -- local_cal_success
+ local_cal_success : out std_logic;
+ -- local_cal_fail
+ local_cal_fail : out std_logic
);
end component ddr4_micron46_mbIIskew;
u0 : component ddr4_micron46_mbIIskew
port map (
- amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
- amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
- amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
- amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
- amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
- amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
- amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
- mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
- mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
- mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
- mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
- mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
- mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
- mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
- mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
- mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0, -- .readdatavalid
- emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
- emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
- global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
- mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
- mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
- mem_a => CONNECTED_TO_mem_a, -- .mem_a
- mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
- mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
- mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
- mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
- mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
- mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
- mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
- mem_par => CONNECTED_TO_mem_par, -- .mem_par
- mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
- mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
- mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
- mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
- mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
- oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
- local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_0.waitrequest_n
+ amm_ready_0 => CONNECTED_TO_amm_ready_0,
+ -- .read
+ amm_read_0 => CONNECTED_TO_amm_read_0,
+ -- .write
+ amm_write_0 => CONNECTED_TO_amm_write_0,
+ -- .address
+ amm_address_0 => CONNECTED_TO_amm_address_0,
+ -- .readdata
+ amm_readdata_0 => CONNECTED_TO_amm_readdata_0,
+ -- .writedata
+ amm_writedata_0 => CONNECTED_TO_amm_writedata_0,
+ -- .burstcount
+ amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0,
+ -- .byteenable
+ amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0,
+ -- .readdatavalid
+ amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0,
+ -- ctrl_mmr_slave_0.waitrequest
+ mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0,
+ -- .read
+ mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0,
+ -- .write
+ mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0,
+ -- .address
+ mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0,
+ -- .readdata
+ mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0,
+ -- .writedata
+ mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0,
+ -- .burstcount
+ mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0,
+ -- .beginbursttransfer
+ mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0,
+ -- .readdatavalid
+ mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0,
+ -- emif_usr_clk.clk
+ emif_usr_clk => CONNECTED_TO_emif_usr_clk,
+ -- emif_usr_reset_n.reset_n
+ emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n,
+ -- global_reset_n.reset_n
+ global_reset_n => CONNECTED_TO_global_reset_n,
+ -- mem.mem_ck
+ mem_ck => CONNECTED_TO_mem_ck,
+ -- .mem_ck_n
+ mem_ck_n => CONNECTED_TO_mem_ck_n,
+ -- .mem_a
+ mem_a => CONNECTED_TO_mem_a,
+ -- .mem_act_n
+ mem_act_n => CONNECTED_TO_mem_act_n,
+ -- .mem_ba
+ mem_ba => CONNECTED_TO_mem_ba,
+ -- .mem_bg
+ mem_bg => CONNECTED_TO_mem_bg,
+ -- .mem_cke
+ mem_cke => CONNECTED_TO_mem_cke,
+ -- .mem_cs_n
+ mem_cs_n => CONNECTED_TO_mem_cs_n,
+ -- .mem_odt
+ mem_odt => CONNECTED_TO_mem_odt,
+ -- .mem_reset_n
+ mem_reset_n => CONNECTED_TO_mem_reset_n,
+ -- .mem_par
+ mem_par => CONNECTED_TO_mem_par,
+ -- .mem_alert_n
+ mem_alert_n => CONNECTED_TO_mem_alert_n,
+ -- .mem_dqs
+ mem_dqs => CONNECTED_TO_mem_dqs,
+ -- .mem_dqs_n
+ mem_dqs_n => CONNECTED_TO_mem_dqs_n,
+ -- .mem_dq
+ mem_dq => CONNECTED_TO_mem_dq,
+ -- .mem_dbi_n
+ mem_dbi_n => CONNECTED_TO_mem_dbi_n,
+ -- oct.oct_rzqin
+ oct_rzqin => CONNECTED_TO_oct_rzqin,
+ -- pll_ref_clk.clk
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk,
+ -- status.local_cal_success
+ local_cal_success => CONNECTED_TO_local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => CONNECTED_TO_local_cal_fail
);
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
index c028fced708026eff114f3297a08f0c515850074..47ad08a91a1ab43c07db2fd093150b1a22202081 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
@@ -1,90 +1,172 @@
component ddr4_micron46_mbIskew is
port (
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic; -- readdatavalid
- mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
- mmr_slave_read_0 : in std_logic := 'X'; -- read
- mmr_slave_write_0 : in std_logic := 'X'; -- write
- mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
- mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
- mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
- mmr_slave_readdatavalid_0 : out std_logic; -- readdatavalid
- emif_usr_clk : out std_logic; -- clk
- emif_usr_reset_n : out std_logic; -- reset_n
- global_reset_n : in std_logic := 'X'; -- reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- pll_ref_clk : in std_logic := 'X'; -- clk
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic -- local_cal_fail
+ -- waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- read
+ amm_read_0 : in std_logic := 'X';
+ -- write
+ amm_write_0 : in std_logic := 'X';
+ -- address
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X');
+ -- readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X');
+ -- burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X');
+ -- byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X');
+ -- readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- waitrequest
+ mmr_slave_waitrequest_0 : out std_logic;
+ -- read
+ mmr_slave_read_0 : in std_logic := 'X';
+ -- write
+ mmr_slave_write_0 : in std_logic := 'X';
+ -- address
+ mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X');
+ -- readdata
+ mmr_slave_readdata_0 : out std_logic_vector(31 downto 0);
+ -- writedata
+ mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- burstcount
+ mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X');
+ -- beginbursttransfer
+ mmr_slave_beginbursttransfer_0 : in std_logic := 'X';
+ -- readdatavalid
+ mmr_slave_readdatavalid_0 : out std_logic;
+ -- clk
+ emif_usr_clk : out std_logic;
+ -- reset_n
+ emif_usr_reset_n : out std_logic;
+ -- reset_n
+ global_reset_n : in std_logic := 'X';
+ -- mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X');
+ -- mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- oct_rzqin
+ oct_rzqin : in std_logic := 'X';
+ -- clk
+ pll_ref_clk : in std_logic := 'X';
+ -- local_cal_success
+ local_cal_success : out std_logic;
+ -- local_cal_fail
+ local_cal_fail : out std_logic
);
end component ddr4_micron46_mbIskew;
u0 : component ddr4_micron46_mbIskew
port map (
- amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
- amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
- amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
- amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
- amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
- amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
- amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
- mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
- mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
- mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
- mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
- mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
- mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
- mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
- mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
- mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0, -- .readdatavalid
- emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
- emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
- global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
- mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
- mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
- mem_a => CONNECTED_TO_mem_a, -- .mem_a
- mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
- mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
- mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
- mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
- mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
- mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
- mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
- mem_par => CONNECTED_TO_mem_par, -- .mem_par
- mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
- mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
- mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
- mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
- mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
- oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
- local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_0.waitrequest_n
+ amm_ready_0 => CONNECTED_TO_amm_ready_0,
+ -- .read
+ amm_read_0 => CONNECTED_TO_amm_read_0,
+ -- .write
+ amm_write_0 => CONNECTED_TO_amm_write_0,
+ -- .address
+ amm_address_0 => CONNECTED_TO_amm_address_0,
+ -- .readdata
+ amm_readdata_0 => CONNECTED_TO_amm_readdata_0,
+ -- .writedata
+ amm_writedata_0 => CONNECTED_TO_amm_writedata_0,
+ -- .burstcount
+ amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0,
+ -- .byteenable
+ amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0,
+ -- .readdatavalid
+ amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0,
+ -- ctrl_mmr_slave_0.waitrequest
+ mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0,
+ -- .read
+ mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0,
+ -- .write
+ mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0,
+ -- .address
+ mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0,
+ -- .readdata
+ mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0,
+ -- .writedata
+ mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0,
+ -- .burstcount
+ mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0,
+ -- .beginbursttransfer
+ mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0,
+ -- .readdatavalid
+ mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0,
+ -- emif_usr_clk.clk
+ emif_usr_clk => CONNECTED_TO_emif_usr_clk,
+ -- emif_usr_reset_n.reset_n
+ emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n,
+ -- global_reset_n.reset_n
+ global_reset_n => CONNECTED_TO_global_reset_n,
+ -- mem.mem_ck
+ mem_ck => CONNECTED_TO_mem_ck,
+ -- .mem_ck_n
+ mem_ck_n => CONNECTED_TO_mem_ck_n,
+ -- .mem_a
+ mem_a => CONNECTED_TO_mem_a,
+ -- .mem_act_n
+ mem_act_n => CONNECTED_TO_mem_act_n,
+ -- .mem_ba
+ mem_ba => CONNECTED_TO_mem_ba,
+ -- .mem_bg
+ mem_bg => CONNECTED_TO_mem_bg,
+ -- .mem_cke
+ mem_cke => CONNECTED_TO_mem_cke,
+ -- .mem_cs_n
+ mem_cs_n => CONNECTED_TO_mem_cs_n,
+ -- .mem_odt
+ mem_odt => CONNECTED_TO_mem_odt,
+ -- .mem_reset_n
+ mem_reset_n => CONNECTED_TO_mem_reset_n,
+ -- .mem_par
+ mem_par => CONNECTED_TO_mem_par,
+ -- .mem_alert_n
+ mem_alert_n => CONNECTED_TO_mem_alert_n,
+ -- .mem_dqs
+ mem_dqs => CONNECTED_TO_mem_dqs,
+ -- .mem_dqs_n
+ mem_dqs_n => CONNECTED_TO_mem_dqs_n,
+ -- .mem_dq
+ mem_dq => CONNECTED_TO_mem_dq,
+ -- .mem_dbi_n
+ mem_dbi_n => CONNECTED_TO_mem_dbi_n,
+ -- oct.oct_rzqin
+ oct_rzqin => CONNECTED_TO_oct_rzqin,
+ -- pll_ref_clk.clk
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk,
+ -- status.local_cal_success
+ local_cal_success => CONNECTED_TO_local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => CONNECTED_TO_local_cal_fail
);
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
index f1ce0394dc61a6390274e086ee406a1851c0acb0..877d322e905272461c6313edb7ec06513ccb8125 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
@@ -32,7 +32,8 @@ use work.qsys_unb2a_heater_pkg.all;
entity mmm_unb2a_heater is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
index b60792517e855717caef9e115180635f2a54d2bf..e0efc35680edef4c8fd30840592b41c3715c9db5 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
@@ -29,133 +29,260 @@ package qsys_unb2a_heater_pkg is
component qsys_unb2a_heater is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_reset_export : out std_logic -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic;
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_heater_read_export : out std_logic;
+ -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_heater_write_export : out std_logic;
+ -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_heater_clk_export : out std_logic;
+ -- export
+ reg_heater_reset_export : out std_logic
);
end component qsys_unb2a_heater;
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
index 5c298a90dc10e64e4061ee6f27663ba742bab6f9..6048159e708e1cc4b3c7e4154bc75e443f61ae09 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
@@ -34,21 +34,30 @@ entity unb2a_heater is
g_design_name : string := "unb2a_heater";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e3sge3;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0; -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0;
g_factory_image : boolean := false
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -121,12 +130,16 @@ architecture str of unb2a_heater is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -173,7 +186,8 @@ begin
g_mm_clk_freq => c_mm_clk_freq,
g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
g_aux => c_unb2_board_aux,
- g_tse_clk_buf => false, -- TRUE,
+ -- TRUE,
+ g_tse_clk_buf => false,
g_factory_image => g_factory_image
)
port map (
@@ -361,7 +375,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
@@ -385,7 +400,8 @@ begin
g_technology => g_technology,
--g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
--g_nof_mac4 => 630 --
- g_nof_mac4 => 736 -- 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
+ -- 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
+ g_nof_mac4 => 736
)
port map (
mm_rst => mm_rst,
diff --git a/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
index 16c91fe7540da69df83e96af141730e13484a3c9..10468f4ff92e3f547393493af5b0c2b330b23e03 100644
--- a/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
@@ -52,23 +52,28 @@ use common_lib.tb_common_pkg.all;
entity tb_unb2a_heater is
generic (
g_design_name : string := "unb2a_heater";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Node 3
+ g_sim_node_nr : natural := 3
);
end tb_unb2a_heater;
architecture tb of tb_unb2a_heater is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb2_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -99,31 +104,46 @@ architecture tb of tb_unb2a_heater is
signal qsfp_led : std_logic_vector(c_unb2_board_tr_qsfp_nof_leds - 1 downto 0);
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
-
- PMBUS_SC <= 'H'; -- pull up
- PMBUS_SD <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+
+ -- pull up
+ PMBUS_SC <= 'H';
+ -- pull up
+ PMBUS_SD <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd b/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
index 4290c6d733f4a7085f678a1d48faca2ef9196844..006d16b8fa86a1988975cf76080e56d591de008f 100644
--- a/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
+++ b/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
@@ -33,16 +33,21 @@ entity unb2a_led is
g_design_name : string := "unb2a_led";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e3sge3;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0; -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0;
g_factory_image : boolean := true
);
port (
- ETH_CLK : in std_logic; -- 125 MHz
+ -- 125 MHz
+ ETH_CLK : in std_logic;
TESTIO : inout std_logic_vector(c_unb2_board_aux.testio_w - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2_board_tr_qsfp_nof_leds - 1 downto 0)
);
@@ -51,7 +56,8 @@ end unb2a_led;
architecture str of unb2a_led is
-- Firmware version x.y
constant c_fw_version : t_unb2_board_fw_version := (1, 1);
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
constant c_mm_clk_freq : natural := c_unb2_board_mm_clk_freq_50M;
-- System
@@ -96,15 +102,18 @@ begin
-- xo_ethclk = ETH_CLK
-----------------------------------------------------------------------------
- i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
+ -- use the ETH_CLK pin as xo_clk
+ i_xo_ethclk <= ETH_CLK;
u_common_areset_xo : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => i_xo_ethclk,
out_rst => i_xo_rst
);
@@ -118,7 +127,8 @@ begin
i_mm_clk <= clk50;
gen_mm_clk_sim: if g_sim = true generate
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ -- 50 MHz, 20ns/2
+ clk50 <= not clk50 after 10 ns;
mm_locked <= '0', '1' after 70 ns;
end generate;
@@ -138,7 +148,8 @@ begin
u_unb2a_board_node_ctrl : entity unb2a_board_lib.unb2_board_node_ctrl
generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us => c_mm_clk_freq / (10**6)
)
port map (
-- MM clock domain reset
@@ -150,7 +161,8 @@ begin
-- Pulses
mm_pulse_us => OPEN,
mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
+ -- could be used to toggle a LED
+ mm_pulse_s => mm_pulse_s
);
------------------------------------------------------------------------------
@@ -161,7 +173,8 @@ begin
u_extend : entity common_lib.common_pulse_extend
generic map (
- g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
+ -- (2^22) / 50e6 = 0.083886 th of 1 sec
+ g_extend_w => 22
)
port map (
rst => i_mm_rst,
@@ -191,7 +204,8 @@ begin
u_extend_10Hz : entity common_lib.common_pulse_extend
generic map (
- g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
+ -- (2^21) / 50e6 = 0.041943 th of 1 sec
+ g_extend_w => 21
)
port map (
rst => i_mm_rst,
diff --git a/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd b/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
index 4e604241be67822b45600364a912743390aec8aa..981eda63b47850d924fc6d26054d0fd6a3ad97c5 100644
--- a/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
+++ b/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
@@ -48,18 +48,23 @@ use common_lib.tb_common_pkg.all;
entity tb_unb2a_led is
generic (
g_design_name : string := "unb2a_led";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Node 3
+ g_sim_node_nr : natural := 3
);
end tb_unb2a_led;
architecture tb of tb_unb2a_led is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
-- DUT
signal eth_clk : std_logic := '0';
@@ -69,7 +74,8 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
------------------------------------------------------------------------------
-- DUT
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
index 2a634cb5632302f7c4fca1240baf02519ad780cc..ac7a78b0bf2ebdf28b6e5d123b0e868b0a0ff8cf 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
@@ -32,7 +32,8 @@ use work.qsys_unb2a_minimal_pkg.all;
entity mmm_unb2a_minimal is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
index 6897ea10bfdf03e5d40e7f2c1d7a4d618ada9160..9ae8a6eb374d31672bee42035501ae6773cf8797 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
@@ -29,126 +29,246 @@ package qsys_unb2a_minimal_pkg is
component qsys_unb2a_minimal is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic
);
end component qsys_unb2a_minimal;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
index ea1f2090f826ec063406aeb77ede160913651c0f..cad83cbc48168c278dc64465d5d0335ba80d2ec0 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
@@ -33,21 +33,30 @@ entity unb2a_minimal is
g_design_name : string := "unb2a_minimal";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e3sge3;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0; -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0;
g_factory_image : boolean := true
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -120,12 +129,16 @@ architecture str of unb2a_minimal is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -351,7 +364,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
diff --git a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
index 6f8ae35cfe579d513b79e2dcab5f944ebc4d484d..b1717e52b5d47025a3873034d0872a5fdb755906 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
@@ -54,23 +54,28 @@ use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
entity tb_unb2a_minimal is
generic (
g_design_name : string := "unb2a_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Node 3
+ g_sim_node_nr : natural := 3
);
end tb_unb2a_minimal;
architecture tb of tb_unb2a_minimal is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb2_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -101,33 +106,48 @@ architecture tb of tb_unb2a_minimal is
signal qsfp_led : std_logic_vector(c_unb2_board_tr_qsfp_nof_leds - 1 downto 0);
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
constant c_pmbus_tcvr0_address : std_logic_vector(6 downto 0) := TO_UVEC(I2C_UNB2_PMB_TCVR0_BMR461_ADR, 7);
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
-
- PMBUS_SC <= 'H'; -- pull up
- PMBUS_SD <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+
+ -- pull up
+ PMBUS_SC <= 'H';
+ -- pull up
+ PMBUS_SD <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
index bbcc7c1c0f2542aabfe38115e8c1fcea9feaa6ff..52c2a35106daeebbb3193d4c9a4f303778cc8069 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
@@ -31,20 +31,29 @@ entity unb2a_test_10GbE is
generic (
g_design_name : string := "unb2a_test_10GbE";
g_design_note : string := "10GbE: all QSFPs";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -61,9 +70,12 @@ entity unb2a_test_10GbE is
ETH_SGOUT : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic; -- Clock 10GbE front (qsfp) and ring lines
- SB_CLK : in std_logic; -- Clock 10GbE back upper 24 lines
- BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic;
+ -- Clock 10GbE back upper 24 lines
+ SB_CLK : in std_logic;
+ -- Clock 10GbE back lower 24 lines
+ BCK_REF_CLK : in std_logic;
-- back transceivers
-- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
index d326502fefb6a118e511aa62ae030c5a6ff00fae..82dcc3b188fc3d52989c316e6017a0373497f535 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
@@ -31,20 +31,29 @@ entity unb2a_test_1GbE is
generic (
g_design_name : string := "unb2a_test_1GbE";
g_design_note : string := "Test design with 1GbE";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
index 3f78a1a9417af8293d22b4d3d1ee4a644a46b2bb..0af402c2b55dbfdc48e363876e56adae3ce90d78 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
@@ -32,20 +32,29 @@ entity unb2a_test_all is
generic (
g_design_name : string := "unb2a_test_all";
g_design_note : string := "Test design with: 6xQSFP,DDR4";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -62,13 +71,18 @@ entity unb2a_test_all is
ETH_SGOUT : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic; -- Clock 10GbE front (qsfp) and ring lines
- SB_CLK : in std_logic; -- Clock 10GbE back upper 24 lines
- BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic;
+ -- Clock 10GbE back upper 24 lines
+ SB_CLK : in std_logic;
+ -- Clock 10GbE back lower 24 lines
+ BCK_REF_CLK : in std_logic;
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
- MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic;
+ -- Reference clock for MB_II
+ MB_II_REF_CLK : in std_logic;
-- back transceivers
-- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
index 7f6bcc8d641644078cdd129bbb6d2c638a0c94ed..7a33f89856da7e43106c669caaa54ed6101e6204 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
@@ -32,20 +32,29 @@ entity unb2a_test_ddr_MB_I is
generic (
g_design_name : string := "unb2a_test_ddr_MB_I";
g_design_note : string := "Test design with ddr4";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -66,7 +75,8 @@ entity unb2a_test_ddr_MB_I is
ETH_SGOUT : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic;
-- SO-DIMM Memory Bank I
MB_I_IN : in t_tech_ddr4_phy_in;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
index 45225efbb730d73c0748f64cf82136088e54adb1..4e439e2af7e4a4eaa1253c1cc64bbd06d9883418 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
@@ -32,20 +32,29 @@ entity unb2a_test_ddr_MB_II is
generic (
g_design_name : string := "unb2a_test_ddr_MB_II";
g_design_note : string := "Test design with ddr4";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -66,7 +75,8 @@ entity unb2a_test_ddr_MB_II is
ETH_SGOUT : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- DDR reference clocks
- MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
+ -- Reference clock for MB_II
+ MB_II_REF_CLK : in std_logic;
-- SO-DIMM Memory Bank II
MB_II_IN : in t_tech_ddr4_phy_in;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
index a6f576bdf924b428376ed1e7f639da238f856878..09ca68b8f2a7804de05120341f894787ce86a312 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
@@ -32,20 +32,29 @@ entity unb2a_test_ddr_MB_I_II is
generic (
g_design_name : string := "unb2a_test_ddr_MB_I_II";
g_design_note : string := "Test design with ddr4";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -66,8 +75,10 @@ entity unb2a_test_ddr_MB_I_II is
ETH_SGOUT : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
- MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic;
+ -- Reference clock for MB_II
+ MB_II_REF_CLK : in std_logic;
-- SO-DIMM Memory Bank I
MB_I_IN : in t_tech_ddr4_phy_in;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
index 262091355adb479dc226846baa15fb29cc297e0e..f3c2bbc901ecb0e38cf89d87339e93e89a533e99 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
@@ -42,7 +42,8 @@ use work.unb2a_test_pkg.all;
entity mmm_unb2a_test is
generic (
- g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
+ -- FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_technology : natural := c_tech_arria10_e3sge3;
@@ -412,7 +413,8 @@ begin
proc_tech_tse_setup(c_tech_arria10_e3sge3, false, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth0_tse_miso, eth1g_eth0_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth0_reg_miso, sim_eth1g_eth0_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth0_reg_miso, sim_eth1g_eth0_reg_mosi);
sim_eth_mm_bus_switch <= '0';
wait;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
index 1a5006c92d75968729f9fc849d656f8f42f90f68..236a4078d0d3ea5512c9213bd81ba5e1a33414ad 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
@@ -30,366 +30,726 @@ package qsys_unb2a_test_pkg is
component qsys_unb2a_test is
port (
- avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
- avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
- avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
- avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
- avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
- avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
- avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
- avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
- avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
- avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
- avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
- avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
- avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
- avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
- avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
- avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
- avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
- avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
- avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
- avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
- clk_clk : in std_logic := '0'; -- clk.clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
- pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
- pio_pps_read_export : out std_logic; -- pio_pps_read.export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
- pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
- pio_pps_write_export : out std_logic; -- pio_pps_write.export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
- pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
- pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
- pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
- pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
- pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
- ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
- ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
- ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
- ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
- reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
- reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
- reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
- reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- reg_diag_data_buffer_10gbe_address.export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
- reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
- reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
- reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
- reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
- reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
- reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
- reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
- reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
- reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
- reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
- reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
- reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back0_address.export
- reg_eth10g_back0_clk_export : out std_logic; -- reg_eth10g_back0_clk.export
- reg_eth10g_back0_read_export : out std_logic; -- reg_eth10g_back0_read.export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back0_readdata.export
- reg_eth10g_back0_reset_export : out std_logic; -- reg_eth10g_back0_reset.export
- reg_eth10g_back0_write_export : out std_logic; -- reg_eth10g_back0_write.export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back0_writedata.export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back1_address.export
- reg_eth10g_back1_clk_export : out std_logic; -- reg_eth10g_back1_clk.export
- reg_eth10g_back1_read_export : out std_logic; -- reg_eth10g_back1_read.export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back1_readdata.export
- reg_eth10g_back1_reset_export : out std_logic; -- reg_eth10g_back1_reset.export
- reg_eth10g_back1_write_export : out std_logic; -- reg_eth10g_back1_write.export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back1_writedata.export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- reg_eth10g_qsfp_ring_address.export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- reg_eth10g_qsfp_ring_clk.export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- reg_eth10g_qsfp_ring_read.export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_qsfp_ring_readdata.export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- reg_eth10g_qsfp_ring_reset.export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- reg_eth10g_qsfp_ring_write.export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_qsfp_ring_writedata.export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- reg_fpga_temp_sens_address.export
- reg_fpga_temp_sens_clk_export : out std_logic; -- reg_fpga_temp_sens_clk.export
- reg_fpga_temp_sens_read_export : out std_logic; -- reg_fpga_temp_sens_read.export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_temp_sens_readdata.export
- reg_fpga_temp_sens_reset_export : out std_logic; -- reg_fpga_temp_sens_reset.export
- reg_fpga_temp_sens_write_export : out std_logic; -- reg_fpga_temp_sens_write.export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_temp_sens_writedata.export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- reg_fpga_voltage_sens_address.export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- reg_fpga_voltage_sens_clk.export
- reg_fpga_voltage_sens_read_export : out std_logic; -- reg_fpga_voltage_sens_read.export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_voltage_sens_readdata.export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- reg_fpga_voltage_sens_reset.export
- reg_fpga_voltage_sens_write_export : out std_logic; -- reg_fpga_voltage_sens_write.export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_voltage_sens_writedata.export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
- reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
- reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
- reg_10gbase_r_24_address_export : out std_logic_vector(14 downto 0); -- reg_10gbase_r_24_address.export
- reg_10gbase_r_24_clk_export : out std_logic; -- reg_10gbase_r_24_clk.export
- reg_10gbase_r_24_read_export : out std_logic; -- reg_10gbase_r_24_read.export
- reg_10gbase_r_24_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_10gbase_r_24_readdata.export
- reg_10gbase_r_24_reset_export : out std_logic; -- reg_10gbase_r_24_reset.export
- reg_10gbase_r_24_waitrequest_export : in std_logic := '0'; -- reg_10gbase_r_24_waitrequest.export
- reg_10gbase_r_24_write_export : out std_logic; -- reg_10gbase_r_24_write.export
- reg_10gbase_r_24_writedata_export : out std_logic_vector(31 downto 0); -- reg_10gbase_r_24_writedata.export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
- reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
- reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
- reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
- reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
- reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
- reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
- reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
- reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
- reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
- reg_remu_read_export : out std_logic; -- reg_remu_read.export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
- reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
- reg_remu_write_export : out std_logic; -- reg_remu_write.export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
- reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
- reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
- reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
- reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- reg_unb_pmbus_address.export
- reg_unb_pmbus_clk_export : out std_logic; -- reg_unb_pmbus_clk.export
- reg_unb_pmbus_read_export : out std_logic; -- reg_unb_pmbus_read.export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_pmbus_readdata.export
- reg_unb_pmbus_reset_export : out std_logic; -- reg_unb_pmbus_reset.export
- reg_unb_pmbus_write_export : out std_logic; -- reg_unb_pmbus_write.export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_pmbus_writedata.export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- reg_unb_sens_address.export
- reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
- reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
- reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
- reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
- reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
- reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
- reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
- reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
- reset_reset_n : in std_logic := '0'; -- reset.reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
- rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
- rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
- rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
- rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
+ -- avs_eth_0_clk.export
+ avs_eth_0_clk_export : out std_logic;
+ -- avs_eth_0_irq.export
+ avs_eth_0_irq_export : in std_logic := '0';
+ -- avs_eth_0_ram_address.export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- avs_eth_0_ram_read.export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- avs_eth_0_ram_readdata.export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- avs_eth_0_ram_write.export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- avs_eth_0_ram_writedata.export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- avs_eth_0_reg_address.export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- avs_eth_0_reg_read.export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- avs_eth_0_reg_readdata.export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- avs_eth_0_reg_write.export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- avs_eth_0_reg_writedata.export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- avs_eth_0_reset.export
+ avs_eth_0_reset_export : out std_logic;
+ -- avs_eth_0_tse_address.export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- avs_eth_0_tse_read.export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- avs_eth_0_tse_readdata.export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- avs_eth_0_tse_waitrequest.export
+ avs_eth_0_tse_waitrequest_export : in std_logic := '0';
+ -- avs_eth_0_tse_write.export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- avs_eth_0_tse_writedata.export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- avs_eth_1_clk.export
+ avs_eth_1_clk_export : out std_logic;
+ -- avs_eth_1_irq.export
+ avs_eth_1_irq_export : in std_logic := '0';
+ -- avs_eth_1_ram_address.export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0);
+ -- avs_eth_1_ram_read.export
+ avs_eth_1_ram_read_export : out std_logic;
+ -- avs_eth_1_ram_readdata.export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- avs_eth_1_ram_write.export
+ avs_eth_1_ram_write_export : out std_logic;
+ -- avs_eth_1_ram_writedata.export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- avs_eth_1_reg_address.export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0);
+ -- avs_eth_1_reg_read.export
+ avs_eth_1_reg_read_export : out std_logic;
+ -- avs_eth_1_reg_readdata.export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- avs_eth_1_reg_write.export
+ avs_eth_1_reg_write_export : out std_logic;
+ -- avs_eth_1_reg_writedata.export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- avs_eth_1_reset.export
+ avs_eth_1_reset_export : out std_logic;
+ -- avs_eth_1_tse_address.export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0);
+ -- avs_eth_1_tse_read.export
+ avs_eth_1_tse_read_export : out std_logic;
+ -- avs_eth_1_tse_readdata.export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- avs_eth_1_tse_waitrequest.export
+ avs_eth_1_tse_waitrequest_export : in std_logic := '0';
+ -- avs_eth_1_tse_write.export
+ avs_eth_1_tse_write_export : out std_logic;
+ -- avs_eth_1_tse_writedata.export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk.clk
+ clk_clk : in std_logic := '0';
+ -- pio_pps_address.export
+ pio_pps_address_export : out std_logic_vector(0 downto 0);
+ -- pio_pps_clk.export
+ pio_pps_clk_export : out std_logic;
+ -- pio_pps_read.export
+ pio_pps_read_export : out std_logic;
+ -- pio_pps_readdata.export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- pio_pps_reset.export
+ pio_pps_reset_export : out std_logic;
+ -- pio_pps_write.export
+ pio_pps_write_export : out std_logic;
+ -- pio_pps_writedata.export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- pio_system_info_address.export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- pio_system_info_clk.export
+ pio_system_info_clk_export : out std_logic;
+ -- pio_system_info_read.export
+ pio_system_info_read_export : out std_logic;
+ -- pio_system_info_readdata.export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- pio_system_info_reset.export
+ pio_system_info_reset_export : out std_logic;
+ -- pio_system_info_write.export
+ pio_system_info_write_export : out std_logic;
+ -- pio_system_info_writedata.export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- pio_wdi_external_connection.export
+ pio_wdi_external_connection_export : out std_logic;
+ -- ram_diag_bg_10gbe_address.export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0);
+ -- ram_diag_bg_10gbe_clk.export
+ ram_diag_bg_10gbe_clk_export : out std_logic;
+ -- ram_diag_bg_10gbe_read.export
+ ram_diag_bg_10gbe_read_export : out std_logic;
+ -- ram_diag_bg_10gbe_readdata.export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- ram_diag_bg_10gbe_reset.export
+ ram_diag_bg_10gbe_reset_export : out std_logic;
+ -- ram_diag_bg_10gbe_write.export
+ ram_diag_bg_10gbe_write_export : out std_logic;
+ -- ram_diag_bg_10gbe_writedata.export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- ram_diag_bg_1gbe_address.export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0);
+ -- ram_diag_bg_1gbe_clk.export
+ ram_diag_bg_1gbe_clk_export : out std_logic;
+ -- ram_diag_bg_1gbe_read.export
+ ram_diag_bg_1gbe_read_export : out std_logic;
+ -- ram_diag_bg_1gbe_readdata.export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- ram_diag_bg_1gbe_reset.export
+ ram_diag_bg_1gbe_reset_export : out std_logic;
+ -- ram_diag_bg_1gbe_write.export
+ ram_diag_bg_1gbe_write_export : out std_logic;
+ -- ram_diag_bg_1gbe_writedata.export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- ram_diag_data_buffer_10gbe_address.export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0);
+ -- ram_diag_data_buffer_10gbe_clk.export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic;
+ -- ram_diag_data_buffer_10gbe_read.export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic;
+ -- ram_diag_data_buffer_10gbe_readdata.export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- ram_diag_data_buffer_10gbe_reset.export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic;
+ -- ram_diag_data_buffer_10gbe_write.export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic;
+ -- ram_diag_data_buffer_10gbe_writedata.export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- ram_diag_data_buffer_1gbe_address.export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0);
+ -- ram_diag_data_buffer_1gbe_clk.export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic;
+ -- ram_diag_data_buffer_1gbe_read.export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic;
+ -- ram_diag_data_buffer_1gbe_readdata.export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- ram_diag_data_buffer_1gbe_reset.export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic;
+ -- ram_diag_data_buffer_1gbe_write.export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic;
+ -- ram_diag_data_buffer_1gbe_writedata.export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- ram_diag_data_buffer_ddr_mb_i_address.export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0);
+ -- ram_diag_data_buffer_ddr_mb_i_clk.export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_i_read.export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_i_readdata.export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- ram_diag_data_buffer_ddr_mb_i_reset.export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_i_write.export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_i_writedata.export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- ram_diag_data_buffer_ddr_mb_ii_address.export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0);
+ -- ram_diag_data_buffer_ddr_mb_ii_clk.export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_ii_read.export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- ram_diag_data_buffer_ddr_mb_ii_reset.export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_ii_write.export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_bsn_monitor_10gbe_address.export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0);
+ -- reg_bsn_monitor_10gbe_clk.export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic;
+ -- reg_bsn_monitor_10gbe_read.export
+ reg_bsn_monitor_10gbe_read_export : out std_logic;
+ -- reg_bsn_monitor_10gbe_readdata.export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_bsn_monitor_10gbe_reset.export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic;
+ -- reg_bsn_monitor_10gbe_write.export
+ reg_bsn_monitor_10gbe_write_export : out std_logic;
+ -- reg_bsn_monitor_10gbe_writedata.export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_bsn_monitor_1gbe_address.export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0);
+ -- reg_bsn_monitor_1gbe_clk.export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic;
+ -- reg_bsn_monitor_1gbe_read.export
+ reg_bsn_monitor_1gbe_read_export : out std_logic;
+ -- reg_bsn_monitor_1gbe_readdata.export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_bsn_monitor_1gbe_reset.export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic;
+ -- reg_bsn_monitor_1gbe_write.export
+ reg_bsn_monitor_1gbe_write_export : out std_logic;
+ -- reg_bsn_monitor_1gbe_writedata.export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_bg_10gbe_address.export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0);
+ -- reg_diag_bg_10gbe_clk.export
+ reg_diag_bg_10gbe_clk_export : out std_logic;
+ -- reg_diag_bg_10gbe_read.export
+ reg_diag_bg_10gbe_read_export : out std_logic;
+ -- reg_diag_bg_10gbe_readdata.export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_bg_10gbe_reset.export
+ reg_diag_bg_10gbe_reset_export : out std_logic;
+ -- reg_diag_bg_10gbe_write.export
+ reg_diag_bg_10gbe_write_export : out std_logic;
+ -- reg_diag_bg_10gbe_writedata.export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_bg_1gbe_address.export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0);
+ -- reg_diag_bg_1gbe_clk.export
+ reg_diag_bg_1gbe_clk_export : out std_logic;
+ -- reg_diag_bg_1gbe_read.export
+ reg_diag_bg_1gbe_read_export : out std_logic;
+ -- reg_diag_bg_1gbe_readdata.export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_bg_1gbe_reset.export
+ reg_diag_bg_1gbe_reset_export : out std_logic;
+ -- reg_diag_bg_1gbe_write.export
+ reg_diag_bg_1gbe_write_export : out std_logic;
+ -- reg_diag_bg_1gbe_writedata.export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_data_buffer_10gbe_address.export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0);
+ -- reg_diag_data_buffer_10gbe_clk.export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic;
+ -- reg_diag_data_buffer_10gbe_read.export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic;
+ -- reg_diag_data_buffer_10gbe_readdata.export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_data_buffer_10gbe_reset.export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic;
+ -- reg_diag_data_buffer_10gbe_write.export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic;
+ -- reg_diag_data_buffer_10gbe_writedata.export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_data_buffer_1gbe_address.export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0);
+ -- reg_diag_data_buffer_1gbe_clk.export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic;
+ -- reg_diag_data_buffer_1gbe_read.export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic;
+ -- reg_diag_data_buffer_1gbe_readdata.export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_data_buffer_1gbe_reset.export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic;
+ -- reg_diag_data_buffer_1gbe_write.export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic;
+ -- reg_diag_data_buffer_1gbe_writedata.export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_data_buffer_ddr_mb_i_address.export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0);
+ -- reg_diag_data_buffer_ddr_mb_i_clk.export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_i_read.export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_i_readdata.export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_data_buffer_ddr_mb_i_reset.export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_i_write.export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_i_writedata.export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_data_buffer_ddr_mb_ii_address.export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0);
+ -- reg_diag_data_buffer_ddr_mb_ii_clk.export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_ii_read.export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_data_buffer_ddr_mb_ii_reset.export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_ii_write.export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_rx_seq_10gbe_address.export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0);
+ -- reg_diag_rx_seq_10gbe_clk.export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic;
+ -- reg_diag_rx_seq_10gbe_read.export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic;
+ -- reg_diag_rx_seq_10gbe_readdata.export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_rx_seq_10gbe_reset.export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic;
+ -- reg_diag_rx_seq_10gbe_write.export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic;
+ -- reg_diag_rx_seq_10gbe_writedata.export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_rx_seq_1gbe_address.export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0);
+ -- reg_diag_rx_seq_1gbe_clk.export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic;
+ -- reg_diag_rx_seq_1gbe_read.export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic;
+ -- reg_diag_rx_seq_1gbe_readdata.export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_rx_seq_1gbe_reset.export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic;
+ -- reg_diag_rx_seq_1gbe_write.export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic;
+ -- reg_diag_rx_seq_1gbe_writedata.export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_rx_seq_ddr_mb_i_address.export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0);
+ -- reg_diag_rx_seq_ddr_mb_i_clk.export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_i_read.export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_i_readdata.export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_rx_seq_ddr_mb_i_reset.export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_i_write.export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_i_writedata.export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_rx_seq_ddr_mb_ii_address.export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0);
+ -- reg_diag_rx_seq_ddr_mb_ii_clk.export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_ii_read.export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_rx_seq_ddr_mb_ii_reset.export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_ii_write.export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_tx_seq_10gbe_address.export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0);
+ -- reg_diag_tx_seq_10gbe_clk.export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic;
+ -- reg_diag_tx_seq_10gbe_read.export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic;
+ -- reg_diag_tx_seq_10gbe_readdata.export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_tx_seq_10gbe_reset.export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic;
+ -- reg_diag_tx_seq_10gbe_write.export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic;
+ -- reg_diag_tx_seq_10gbe_writedata.export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_tx_seq_1gbe_address.export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0);
+ -- reg_diag_tx_seq_1gbe_clk.export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic;
+ -- reg_diag_tx_seq_1gbe_read.export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic;
+ -- reg_diag_tx_seq_1gbe_readdata.export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_tx_seq_1gbe_reset.export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic;
+ -- reg_diag_tx_seq_1gbe_write.export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic;
+ -- reg_diag_tx_seq_1gbe_writedata.export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_tx_seq_ddr_mb_i_address.export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0);
+ -- reg_diag_tx_seq_ddr_mb_i_clk.export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_i_read.export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_i_readdata.export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_tx_seq_ddr_mb_i_reset.export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_i_write.export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_i_writedata.export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_tx_seq_ddr_mb_ii_address.export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0);
+ -- reg_diag_tx_seq_ddr_mb_ii_clk.export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_ii_read.export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_tx_seq_ddr_mb_ii_reset.export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_ii_write.export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_dpmm_ctrl_address.export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- reg_dpmm_ctrl_clk.export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- reg_dpmm_ctrl_read.export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- reg_dpmm_ctrl_readdata.export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_dpmm_ctrl_reset.export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- reg_dpmm_ctrl_write.export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- reg_dpmm_ctrl_writedata.export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_dpmm_data_address.export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- reg_dpmm_data_clk.export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- reg_dpmm_data_read.export
+ reg_dpmm_data_read_export : out std_logic;
+ -- reg_dpmm_data_readdata.export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_dpmm_data_reset.export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- reg_dpmm_data_write.export
+ reg_dpmm_data_write_export : out std_logic;
+ -- reg_dpmm_data_writedata.export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_epcs_address.export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- reg_epcs_clk.export
+ reg_epcs_clk_export : out std_logic;
+ -- reg_epcs_read.export
+ reg_epcs_read_export : out std_logic;
+ -- reg_epcs_readdata.export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_epcs_reset.export
+ reg_epcs_reset_export : out std_logic;
+ -- reg_epcs_write.export
+ reg_epcs_write_export : out std_logic;
+ -- reg_epcs_writedata.export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_eth10g_back0_address.export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0);
+ -- reg_eth10g_back0_clk.export
+ reg_eth10g_back0_clk_export : out std_logic;
+ -- reg_eth10g_back0_read.export
+ reg_eth10g_back0_read_export : out std_logic;
+ -- reg_eth10g_back0_readdata.export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_eth10g_back0_reset.export
+ reg_eth10g_back0_reset_export : out std_logic;
+ -- reg_eth10g_back0_write.export
+ reg_eth10g_back0_write_export : out std_logic;
+ -- reg_eth10g_back0_writedata.export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_eth10g_back1_address.export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0);
+ -- reg_eth10g_back1_clk.export
+ reg_eth10g_back1_clk_export : out std_logic;
+ -- reg_eth10g_back1_read.export
+ reg_eth10g_back1_read_export : out std_logic;
+ -- reg_eth10g_back1_readdata.export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_eth10g_back1_reset.export
+ reg_eth10g_back1_reset_export : out std_logic;
+ -- reg_eth10g_back1_write.export
+ reg_eth10g_back1_write_export : out std_logic;
+ -- reg_eth10g_back1_writedata.export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_eth10g_qsfp_ring_address.export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0);
+ -- reg_eth10g_qsfp_ring_clk.export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic;
+ -- reg_eth10g_qsfp_ring_read.export
+ reg_eth10g_qsfp_ring_read_export : out std_logic;
+ -- reg_eth10g_qsfp_ring_readdata.export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_eth10g_qsfp_ring_reset.export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic;
+ -- reg_eth10g_qsfp_ring_write.export
+ reg_eth10g_qsfp_ring_write_export : out std_logic;
+ -- reg_eth10g_qsfp_ring_writedata.export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_fpga_temp_sens_address.export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- reg_fpga_temp_sens_clk.export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- reg_fpga_temp_sens_read.export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- reg_fpga_temp_sens_readdata.export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_fpga_temp_sens_reset.export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- reg_fpga_temp_sens_write.export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- reg_fpga_temp_sens_writedata.export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_fpga_voltage_sens_address.export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- reg_fpga_voltage_sens_clk.export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- reg_fpga_voltage_sens_read.export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- reg_fpga_voltage_sens_readdata.export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_fpga_voltage_sens_reset.export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- reg_fpga_voltage_sens_write.export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- reg_fpga_voltage_sens_writedata.export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_io_ddr_mb_i_address.export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0);
+ -- reg_io_ddr_mb_i_clk.export
+ reg_io_ddr_mb_i_clk_export : out std_logic;
+ -- reg_io_ddr_mb_i_read.export
+ reg_io_ddr_mb_i_read_export : out std_logic;
+ -- reg_io_ddr_mb_i_readdata.export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_io_ddr_mb_i_reset.export
+ reg_io_ddr_mb_i_reset_export : out std_logic;
+ -- reg_io_ddr_mb_i_write.export
+ reg_io_ddr_mb_i_write_export : out std_logic;
+ -- reg_io_ddr_mb_i_writedata.export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_io_ddr_mb_ii_address.export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0);
+ -- reg_io_ddr_mb_ii_clk.export
+ reg_io_ddr_mb_ii_clk_export : out std_logic;
+ -- reg_io_ddr_mb_ii_read.export
+ reg_io_ddr_mb_ii_read_export : out std_logic;
+ -- reg_io_ddr_mb_ii_readdata.export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_io_ddr_mb_ii_reset.export
+ reg_io_ddr_mb_ii_reset_export : out std_logic;
+ -- reg_io_ddr_mb_ii_write.export
+ reg_io_ddr_mb_ii_write_export : out std_logic;
+ -- reg_io_ddr_mb_ii_writedata.export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_10gbase_r_24_address.export
+ reg_10gbase_r_24_address_export : out std_logic_vector(14 downto 0);
+ -- reg_10gbase_r_24_clk.export
+ reg_10gbase_r_24_clk_export : out std_logic;
+ -- reg_10gbase_r_24_read.export
+ reg_10gbase_r_24_read_export : out std_logic;
+ -- reg_10gbase_r_24_readdata.export
+ reg_10gbase_r_24_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_10gbase_r_24_reset.export
+ reg_10gbase_r_24_reset_export : out std_logic;
+ -- reg_10gbase_r_24_waitrequest.export
+ reg_10gbase_r_24_waitrequest_export : in std_logic := '0';
+ -- reg_10gbase_r_24_write.export
+ reg_10gbase_r_24_write_export : out std_logic;
+ -- reg_10gbase_r_24_writedata.export
+ reg_10gbase_r_24_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_mmdp_ctrl_address.export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- reg_mmdp_ctrl_clk.export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- reg_mmdp_ctrl_read.export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- reg_mmdp_ctrl_readdata.export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_mmdp_ctrl_reset.export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- reg_mmdp_ctrl_write.export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- reg_mmdp_ctrl_writedata.export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_mmdp_data_address.export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- reg_mmdp_data_clk.export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- reg_mmdp_data_read.export
+ reg_mmdp_data_read_export : out std_logic;
+ -- reg_mmdp_data_readdata.export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_mmdp_data_reset.export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- reg_mmdp_data_write.export
+ reg_mmdp_data_write_export : out std_logic;
+ -- reg_mmdp_data_writedata.export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_remu_address.export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- reg_remu_clk.export
+ reg_remu_clk_export : out std_logic;
+ -- reg_remu_read.export
+ reg_remu_read_export : out std_logic;
+ -- reg_remu_readdata.export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_remu_reset.export
+ reg_remu_reset_export : out std_logic;
+ -- reg_remu_write.export
+ reg_remu_write_export : out std_logic;
+ -- reg_remu_writedata.export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_tr_10gbe_back0_address.export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0);
+ -- reg_tr_10gbe_back0_clk.export
+ reg_tr_10gbe_back0_clk_export : out std_logic;
+ -- reg_tr_10gbe_back0_read.export
+ reg_tr_10gbe_back0_read_export : out std_logic;
+ -- reg_tr_10gbe_back0_readdata.export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_tr_10gbe_back0_reset.export
+ reg_tr_10gbe_back0_reset_export : out std_logic;
+ -- reg_tr_10gbe_back0_waitrequest.export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0';
+ -- reg_tr_10gbe_back0_write.export
+ reg_tr_10gbe_back0_write_export : out std_logic;
+ -- reg_tr_10gbe_back0_writedata.export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_tr_10gbe_back1_address.export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0);
+ -- reg_tr_10gbe_back1_clk.export
+ reg_tr_10gbe_back1_clk_export : out std_logic;
+ -- reg_tr_10gbe_back1_read.export
+ reg_tr_10gbe_back1_read_export : out std_logic;
+ -- reg_tr_10gbe_back1_readdata.export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_tr_10gbe_back1_reset.export
+ reg_tr_10gbe_back1_reset_export : out std_logic;
+ -- reg_tr_10gbe_back1_waitrequest.export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0';
+ -- reg_tr_10gbe_back1_write.export
+ reg_tr_10gbe_back1_write_export : out std_logic;
+ -- reg_tr_10gbe_back1_writedata.export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_tr_10gbe_qsfp_ring_address.export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0);
+ -- reg_tr_10gbe_qsfp_ring_clk.export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic;
+ -- reg_tr_10gbe_qsfp_ring_read.export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic;
+ -- reg_tr_10gbe_qsfp_ring_readdata.export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_tr_10gbe_qsfp_ring_reset.export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic;
+ -- reg_tr_10gbe_qsfp_ring_waitrequest.export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0';
+ -- reg_tr_10gbe_qsfp_ring_write.export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic;
+ -- reg_tr_10gbe_qsfp_ring_writedata.export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_unb_pmbus_address.export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- reg_unb_pmbus_clk.export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- reg_unb_pmbus_read.export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- reg_unb_pmbus_readdata.export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_unb_pmbus_reset.export
+ reg_unb_pmbus_reset_export : out std_logic;
+ -- reg_unb_pmbus_write.export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- reg_unb_pmbus_writedata.export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_unb_sens_address.export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- reg_unb_sens_clk.export
+ reg_unb_sens_clk_export : out std_logic;
+ -- reg_unb_sens_read.export
+ reg_unb_sens_read_export : out std_logic;
+ -- reg_unb_sens_readdata.export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_unb_sens_reset.export
+ reg_unb_sens_reset_export : out std_logic;
+ -- reg_unb_sens_write.export
+ reg_unb_sens_write_export : out std_logic;
+ -- reg_unb_sens_writedata.export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_wdi_address.export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- reg_wdi_clk.export
+ reg_wdi_clk_export : out std_logic;
+ -- reg_wdi_read.export
+ reg_wdi_read_export : out std_logic;
+ -- reg_wdi_readdata.export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_wdi_reset.export
+ reg_wdi_reset_export : out std_logic;
+ -- reg_wdi_write.export
+ reg_wdi_write_export : out std_logic;
+ -- reg_wdi_writedata.export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset.reset_n
+ reset_reset_n : in std_logic := '0';
+ -- rom_system_info_address.export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ -- rom_system_info_clk.export
+ rom_system_info_clk_export : out std_logic;
+ -- rom_system_info_read.export
+ rom_system_info_read_export : out std_logic;
+ -- rom_system_info_readdata.export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- rom_system_info_reset.export
+ rom_system_info_reset_export : out std_logic;
+ -- rom_system_info_write.export
+ rom_system_info_write_export : out std_logic;
+ -- rom_system_info_writedata.export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0)
);
end component qsys_unb2a_test;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
index 1784bbb118a15525eff62cb4869aba6a45da3f93..462088e7166fad3b752d403de27bfc5b480c7844 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
@@ -61,9 +61,11 @@ entity udp_stream is
ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0);
-- blockgen mm
- reg_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- BG control register (one for all streams)
+ -- BG control register (one for all streams)
+ reg_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_diag_bg_miso : out t_mem_miso;
- ram_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream)
+ -- BG buffer RAM (one per stream)
+ ram_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_diag_bg_miso : out t_mem_miso;
reg_diag_tx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_diag_tx_seq_miso : out t_mem_miso;
@@ -102,8 +104,10 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
+ -- enable (disabled by default)
+ constant c_bg_ctrl : t_diag_block_gen := ('0',
+ -- enable_sync
+ '0',
TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
@@ -178,7 +182,8 @@ begin
reg_tx_seq_miso => reg_diag_tx_seq_miso
);
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
g_technology => g_technology,
@@ -318,9 +323,11 @@ begin
generic map (
g_technology => g_technology,
g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
+ -- g_data_w, --FIXME
+ g_data_w => 32,
g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
+ -- sync by reading last address of data buffer
+ g_buf_use_sync => false,
g_use_rx_seq => true
)
port map (
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
index 73f726f8a9557e0bf3dd2f5c30c5fe6ba386ea37..cd719d7cff06f786c80672f473020f28f4709ac5 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
@@ -41,24 +41,35 @@ entity unb2a_test is
g_design_name : string := "unb2a_test";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e3sge3;
- g_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
- g_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
- g_sim : boolean := false; -- Overridden by TB
+ -- DDR4 has no master or slave, so no need to check number of MB
+ g_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_8g_1600m;
+ -- DDR4 has no master or slave, so no need to check number of MB
+ g_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_8g_1600m;
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_sim_model_ddr : boolean := false;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0; -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0;
g_factory_image : boolean := false
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
@@ -75,13 +86,18 @@ entity unb2a_test is
ETH_SGOUT : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
- SB_CLK : in std_logic := '0'; -- Clock 10GbE back upper 24 lines
- BCK_REF_CLK : in std_logic := '0'; -- Clock 10GbE back lower 24 lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
+ -- Clock 10GbE back upper 24 lines
+ SB_CLK : in std_logic := '0';
+ -- Clock 10GbE back lower 24 lines
+ BCK_REF_CLK : in std_logic := '0';
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic := '0'; -- Reference clock for MB_I
- MB_II_REF_CLK : in std_logic := '0'; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic := '0';
+ -- Reference clock for MB_II
+ MB_II_REF_CLK : in std_logic := '0';
-- back transceivers
--BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0) := (OTHERS=>'0');
@@ -143,23 +159,31 @@ architecture str of unb2a_test is
constant c_mm_clk_freq : natural := c_unb2_board_mm_clk_freq_125M;
-- Revision controlled constants
- constant c_use_1GbE : boolean := false; -- g_design_name="unb2a_test_1GbE" OR g_design_name="unb2a_test_10GbE" OR g_design_name="unb2a_test_all";
+ -- g_design_name="unb2a_test_1GbE" OR g_design_name="unb2a_test_10GbE" OR g_design_name="unb2a_test_all";
+ constant c_use_1GbE : boolean := false;
constant c_use_10GbE : boolean := g_design_name = "unb2a_test_10GbE" or g_design_name = "unb2a_test_all";
constant c_use_10GbE_qsfp : boolean := c_use_10GbE;
- constant c_use_10GbE_ring : boolean := false; -- c_use_10GbE;
- constant c_use_10GbE_back0 : boolean := false; -- c_use_10GbE;
- constant c_use_10GbE_back1 : boolean := false; -- c_use_10GbE;
+ -- c_use_10GbE;
+ constant c_use_10GbE_ring : boolean := false;
+ -- c_use_10GbE;
+ constant c_use_10GbE_back0 : boolean := false;
+ -- c_use_10GbE;
+ constant c_use_10GbE_back1 : boolean := false;
constant c_use_MB_I : boolean := g_design_name = "unb2a_test_ddr_MB_I" or g_design_name = "unb2a_test_ddr_MB_I_II" or g_design_name = "unb2a_test_all";
constant c_use_MB_II : boolean := g_design_name = "unb2a_test_ddr_MB_II" or g_design_name = "unb2a_test_ddr_MB_I_II" or g_design_name = "unb2a_test_all";
-- transceivers
constant c_nof_qsfp : natural := c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
- constant c_nof_ring : natural := 0; -- 8;--12;--c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
- constant c_nof_back0 : natural := 0; -- c_unb2_board_tr_back.bus_w;
- constant c_nof_back1 : natural := 0; -- c_unb2_board_tr_back.bus_w;
+ -- 8;--12;--c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
+ constant c_nof_ring : natural := 0;
+ -- c_unb2_board_tr_back.bus_w;
+ constant c_nof_back0 : natural := 0;
+ -- c_unb2_board_tr_back.bus_w;
+ constant c_nof_back1 : natural := 0;
-- 1GbE
- constant c_nof_streams_1GbE : natural := sel_a_b(c_use_1GbE,1,0); -- sel_a_b(c_use_1GbE,c_unb2_board_nof_eth,0);
+ -- sel_a_b(c_use_1GbE,c_unb2_board_nof_eth,0);
+ constant c_nof_streams_1GbE : natural := sel_a_b(c_use_1GbE,1,0);
-- 10GbE
constant c_nof_streams_qsfp : natural := sel_a_b(c_use_10GbE_qsfp,c_nof_qsfp,0);
@@ -173,15 +197,22 @@ architecture str of unb2a_test is
constant c_nof_ring_bus : natural := ceil_div(c_nof_streams_ring,c_unb2_board_tr_ring.bus_w);
constant c_nof_back_bus : natural := ceil_div(c_nof_streams_back0,c_unb2_board_tr_back.bus_w) + ceil_div(c_nof_streams_back1,c_unb2_board_tr_back.bus_w);
- constant c_data_w_32 : natural := c_eth_data_w; -- 1GbE
- constant c_data_w_64 : natural := c_xgmii_data_w; -- 10GbE
+ -- 1GbE
+ constant c_data_w_32 : natural := c_eth_data_w;
+ -- 10GbE
+ constant c_data_w_64 : natural := c_xgmii_data_w;
-- ddr
- constant c_ddr_ctlr_data_w : natural := func_tech_ddr_ctlr_data_w(g_ddr_MB_I); -- = 576, assume both MB_I and MB_II use the same ctlr_data_w
- constant c_ddr_dp_data_w : natural := 144; -- DDR4 with dq_w = 72, rsl = 8 so ctrl data width = 576 and therefore the mixed width FIFO ratio is 576 /144 = 4
- constant c_ddr_dp_seq_dat_w : natural := 16; -- >= 1, test sequence data width. Choose c_ddr_dp_seq_dat_w <= c_ddr_dp_data_w. The seq data gets replicated to fill c_ddr_dp_data_w.
- constant c_ddr_dp_wr_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w); -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) to make full use of M9K which have at least 256 words
- constant c_ddr_dp_rd_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w); -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) or factors of 2 more to fit max number of read bursts
+ -- = 576, assume both MB_I and MB_II use the same ctlr_data_w
+ constant c_ddr_ctlr_data_w : natural := func_tech_ddr_ctlr_data_w(g_ddr_MB_I);
+ -- DDR4 with dq_w = 72, rsl = 8 so ctrl data width = 576 and therefore the mixed width FIFO ratio is 576 /144 = 4
+ constant c_ddr_dp_data_w : natural := 144;
+ -- >= 1, test sequence data width. Choose c_ddr_dp_seq_dat_w <= c_ddr_dp_data_w. The seq data gets replicated to fill c_ddr_dp_data_w.
+ constant c_ddr_dp_seq_dat_w : natural := 16;
+ -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) to make full use of M9K which have at least 256 words
+ constant c_ddr_dp_wr_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w);
+ -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) or factors of 2 more to fit max number of read bursts
+ constant c_ddr_dp_rd_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w);
constant c_ddr_db_buf_nof_data : natural := 1024;
constant c_ddr_mixed_width_ratio : natural := ratio2(c_ddr_ctlr_data_w, c_ddr_dp_data_w);
@@ -189,11 +220,14 @@ architecture str of unb2a_test is
constant c_bg_block_size : natural := 900;
constant c_bg_gapsize_1GbE : natural := 1000;
constant c_bg_gapsize_10GbE : natural := 100;
- constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
+ -- 200000*(900+100) = 200000000 cycles = 1 second
+ constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000);
constant c_use_jumbo_frames : boolean := false;
- constant c_def_1GbE_block_size : natural := 20; -- 0 first so we have time to set RX demux reg in dest. node
- constant c_def_10GbE_block_size : natural := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
+ -- 0 first so we have time to set RX demux reg in dest. node
+ constant c_def_1GbE_block_size : natural := 20;
+ -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
+ constant c_def_10GbE_block_size : natural := 700;
constant c_max_frame_len : natural := sel_a_b(c_use_jumbo_frames, 9018, 1518);
constant c_nof_header_bytes : natural := field_slv_len(c_hdr_field_arr) / c_byte_w;
@@ -262,22 +296,30 @@ architecture str of unb2a_test is
-- eth1g ch0
signal eth1g_eth0_mm_rst : std_logic;
- signal eth1g_eth0_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_eth0_tse_mosi : t_mem_mosi;
signal eth1g_eth0_tse_miso : t_mem_miso;
- signal eth1g_eth0_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_eth0_reg_mosi : t_mem_mosi;
signal eth1g_eth0_reg_miso : t_mem_miso;
- signal eth1g_eth0_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_eth0_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_eth0_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_eth0_ram_mosi : t_mem_mosi;
signal eth1g_eth0_ram_miso : t_mem_miso;
-- eth1g ch1
signal eth1g_eth1_mm_rst : std_logic;
- signal eth1g_eth1_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_eth1_tse_mosi : t_mem_mosi;
signal eth1g_eth1_tse_miso : t_mem_miso;
- signal eth1g_eth1_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_eth1_reg_mosi : t_mem_mosi;
signal eth1g_eth1_reg_miso : t_mem_miso;
- signal eth1g_eth1_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_eth1_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_eth1_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_eth1_ram_mosi : t_mem_mosi;
signal eth1g_eth1_ram_miso : t_mem_miso;
-- EPCS read
@@ -584,9 +626,12 @@ begin
g_hdr_field_arr => c_hdr_field_arr,
g_nof_streams_1GbE => c_unb2_board_nof_eth,
g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
- g_nof_streams_ring => 24, -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
- g_nof_streams_back0 => 24, -- c_unb2_board_tr_back.bus_w,
- g_nof_streams_back1 => 24 -- c_unb2_board_tr_back.bus_w
+ -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
+ g_nof_streams_ring => 24,
+ -- c_unb2_board_tr_back.bus_w,
+ g_nof_streams_back0 => 24,
+ -- c_unb2_board_tr_back.bus_w
+ g_nof_streams_back1 => 24
)
port map(
mm_rst => mm_rst,
@@ -879,7 +924,8 @@ begin
reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
);
- u_tr_10GbE_qsfp_and_ring: entity unb2a_board_10gbe_lib.unb2_board_10gbe -- QSFP and Ring lines
+ -- QSFP and Ring lines
+ u_tr_10GbE_qsfp_and_ring: entity unb2a_board_10gbe_lib.unb2_board_10gbe
generic map (
g_sim => g_sim,
g_sim_level => 1,
@@ -1039,7 +1085,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M)
)
port map (
rst => dp_rst,
@@ -1078,7 +1125,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
@@ -1111,7 +1159,8 @@ begin
-- DIAG data buffer
g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ -- nof words per data buffer
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data
)
port map (
---------------------------------------------------------------------------
@@ -1120,7 +1169,8 @@ begin
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+ -- use alternative external clock or externally connect to ctlr_clk_out
+ dp_clk => dp_clk,
---------------------------------------------------------------------------
-- IO_DDR
@@ -1133,11 +1183,14 @@ begin
ctlr_clk_out => ddr_I_clk200,
ctlr_rst_out => ddr_I_rst200,
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+ -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_clk_in => ddr_I_clk200,
+ -- connect ctlr_rst_out to ctlr_rst_in at top level
+ ctlr_rst_in => ddr_I_rst200,
-- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ -- register for DDR controller status info
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi,
reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-- Write / read FIFO status for monitoring purposes (in dp_clk domain)
@@ -1188,7 +1241,8 @@ begin
-- DIAG data buffer
g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ -- nof words per data buffer
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data
)
port map (
---------------------------------------------------------------------------
@@ -1197,7 +1251,8 @@ begin
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+ -- use alternative external clock or externally connect to ctlr_clk_out
+ dp_clk => dp_clk,
---------------------------------------------------------------------------
-- IO_DDR
@@ -1210,11 +1265,14 @@ begin
ctlr_clk_out => ddr_II_clk200,
ctlr_rst_out => ddr_II_rst200,
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+ -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_clk_in => ddr_II_clk200,
+ -- connect ctlr_rst_out to ctlr_rst_in at top level
+ ctlr_rst_in => ddr_II_rst200,
-- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ -- register for DDR controller status info
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi,
reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-- Write / read FIFO status for monitoring purposes (in dp_clk domain)
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
index b3bb5004d9a3571a7699de756f01fa9f7c2188c3..f2e3d4df952350c4980860826b60397b44f58758 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
@@ -28,15 +28,18 @@ use common_lib.common_field_pkg.all;
package unb2a_test_pkg is
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
- constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ -- Total header bits = 384 = 6 64b words
+ constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2;
+ -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
@@ -47,7 +50,8 @@ package unb2a_test_pkg is
( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
diff --git a/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
index 819942904d1b93c6625ca6826dd11e4e79bc2b42..b655cb538d573a0e1c014b79aebe645bf8a40410 100644
--- a/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
@@ -62,24 +62,34 @@ end tb_unb2a_test;
architecture tb of tb_unb2a_test is
constant c_sim : boolean := true;
- constant c_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
- constant c_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
-
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- DDR4 has no master or slave, so no need to check number of MB
+ constant c_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
+ -- DDR4 has no master or slave, so no need to check number of MB
+ constant c_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
+
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb2_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644 MHz
- constant c_sb_clk_period : time := tech_pll_clk_644_period; -- 644 MHz
- constant c_bck_ref_clk_period : time := tech_pll_clk_644_period; -- 644 MHz
- constant c_mb_I_ref_clk_period : time := 40 ns; -- 25 MHz
- constant c_mb_II_ref_clk_period : time := 40 ns; -- 25 MHz
+ -- 644 MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
+ -- 644 MHz
+ constant c_sb_clk_period : time := tech_pll_clk_644_period;
+ -- 644 MHz
+ constant c_bck_ref_clk_period : time := tech_pll_clk_644_period;
+ -- 25 MHz
+ constant c_mb_I_ref_clk_period : time := 40 ns;
+ -- 25 MHz
+ constant c_mb_II_ref_clk_period : time := 40 ns;
constant c_pps_period : natural := 1000;
-- DUT
@@ -105,8 +115,10 @@ architecture tb of tb_unb2a_test is
signal qsfp_led : std_logic_vector(c_unb2_board_tr_qsfp_nof_leds - 1 downto 0);
-- DDR reference clocks
- signal mb_I_ref_clk : std_logic := '1'; -- Reference clock for MB_I
- signal mb_II_ref_clk : std_logic := '1'; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ signal mb_I_ref_clk : std_logic := '1';
+ -- Reference clock for MB_II
+ signal mb_II_ref_clk : std_logic := '1';
-- DDR4 PHY interface
signal MB_I_IN : t_tech_ddr4_phy_in;
@@ -136,33 +148,51 @@ architecture tb of tb_unb2a_test is
signal si_lpbk_8 : std_logic_vector(c_unb2_board_tr_back.bus_w - 1 downto 0);
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- sa_clk <= not sa_clk after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
- sb_clk <= not sb_clk after c_sb_clk_period / 2; -- Serial Gigabit IO sb clock (644 MHz)
- bck_ref_clk <= not bck_ref_clk after c_bck_ref_clk_period / 2; -- Serial Gigabit IO bck_ref clock (644 MHz)
- mb_I_ref_clk <= not mb_I_ref_clk after c_mb_I_ref_clk_period / 2; -- MB I reference clock (25 MHz)
- mb_II_ref_clk <= not mb_II_ref_clk after c_mb_II_ref_clk_period / 2; -- MB II reference clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ sa_clk <= not sa_clk after c_sa_clk_period / 2;
+ -- Serial Gigabit IO sb clock (644 MHz)
+ sb_clk <= not sb_clk after c_sb_clk_period / 2;
+ -- Serial Gigabit IO bck_ref clock (644 MHz)
+ bck_ref_clk <= not bck_ref_clk after c_bck_ref_clk_period / 2;
+ -- MB I reference clock (25 MHz)
+ mb_I_ref_clk <= not mb_I_ref_clk after c_mb_I_ref_clk_period / 2;
+ -- MB II reference clock (25 MHz)
+ mb_II_ref_clk <= not mb_II_ref_clk after c_mb_II_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
index 2f62140372553a4993ae19a4fad7e85e5493390d..3ef5659535e4c8d5d14c393f2e263e938f3ac297 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
@@ -44,12 +44,14 @@ entity ctrl_unb2_board is
g_technology : natural := c_tech_arria10;
g_sim : boolean := false;
g_design_name : string := "UNUSED";
- g_fw_version : t_unb2_board_fw_version := (0, 0); -- firmware version x.y
+ -- firmware version x.y
+ g_fw_version : t_unb2_board_fw_version := (0, 0);
g_stamp_date : natural := 0;
g_stamp_time : natural := 0;
g_stamp_svn : natural := 0;
g_design_note : string := "UNUSED";
- g_base_ip : std_logic_vector(16 - 1 downto 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy
+ -- Base IP address used by unb_osy: 10.99.xx.yy
+ g_base_ip : std_logic_vector(16 - 1 downto 0) := X"0A63";
g_mm_clk_freq : natural := c_unb2_board_mm_clk_freq_125M;
g_eth_clk_freq : natural := c_unb2_board_eth_clk_freq_125M;
g_tse_clk_buf : boolean := false;
@@ -93,7 +95,8 @@ entity ctrl_unb2_board is
-- STRING := "4688" = 3750+ 938 = 337.5
-- STRING := "4844" = 3750+1094 = 348.75
-- STRING := "5000" = 3750+1250 = 360
- g_dp_clk_phase : string := "0"; -- phase offset for PLL c0, typically any phase is fine, do not use 225 +-30 degrees because there the PPS edge occurs
+ -- phase offset for PLL c0, typically any phase is fine, do not use 225 +-30 degrees because there the PPS edge occurs
+ g_dp_clk_phase : string := "0";
----------------------------------------------------------------------------
-- 1GbE UDP offload
@@ -105,14 +108,18 @@ entity ctrl_unb2_board is
-- Auxiliary Interface
----------------------------------------------------------------------------
g_fpga_temp_high : natural := 85;
- g_app_led_red : boolean := false; -- when TRUE use external LED control via app_led_red
- g_app_led_green : boolean := false; -- when TRUE use external LED control via app_led_green
+ -- when TRUE use external LED control via app_led_red
+ g_app_led_red : boolean := false;
+ -- when TRUE use external LED control via app_led_green
+ g_app_led_green : boolean := false;
g_aux : t_c_unb2_board_aux := c_unb2_board_aux;
g_factory_image : boolean := false;
g_protect_addr_range: boolean := false;
- g_protected_addr_lo : natural := 0; -- Byte address
- g_protected_addr_hi : natural := 41943039 -- Byte address, for UniBoard1 this is 640 sectors*256 pages*256 bytes -1 = 41943039
+ -- Byte address
+ g_protected_addr_lo : natural := 0;
+ -- Byte address, for UniBoard1 this is 640 sectors*256 pages*256 bytes -1 = 41943039
+ g_protected_addr_hi : natural := 41943039
);
port (
--
@@ -121,33 +128,49 @@ entity ctrl_unb2_board is
-- System
cs_sim : out std_logic;
- xo_ethclk : out std_logic; -- 125 MHz ETH_CLK
- xo_rst : out std_logic; -- reset in ETH_CLK domain released after few cycles
+ -- 125 MHz ETH_CLK
+ xo_ethclk : out std_logic;
+ -- reset in ETH_CLK domain released after few cycles
+ xo_rst : out std_logic;
xo_rst_n : out std_logic;
- ext_clk200 : out std_logic; -- 200 MHz CLK
- ext_rst200 : out std_logic; -- reset in CLK clock domain released after mm_rst
-
- mm_clk : out std_logic; -- MM clock from xo_ethclk PLL
- mm_rst : out std_logic; -- reset in MM clock domain released after xo_ethclk PLL locked
-
- dp_rst : out std_logic; -- reset in DP clock domain released after mm_rst and after CLK PLL locked in case g_dp_clk_use_pll=TRUE
- dp_clk : out std_logic; -- 200 MHz DP clock from CLK system clock direct or via CLK PLL dependent on g_dp_clk_use_pll
- dp_pps : out std_logic; -- PPS in dp_clk domain
- dp_rst_in : in std_logic; -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
- dp_clk_in : in std_logic; -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
-
- mb_I_ref_rst : out std_logic; -- reset in MB_I_REF_CLK domain released after mm_rst
- mb_II_ref_rst : out std_logic; -- reset in MB_II_REF_CLK domain released after mm_rst
-
- this_chip_id : out std_logic_vector(c_unb2_board_nof_chip_w - 1 downto 0); -- [1:0], so range 0-3 for PN
- this_bck_id : out std_logic_vector(c_unb2_board_nof_uniboard_w - 1 downto 0); -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
+ -- 200 MHz CLK
+ ext_clk200 : out std_logic;
+ -- reset in CLK clock domain released after mm_rst
+ ext_rst200 : out std_logic;
+
+ -- MM clock from xo_ethclk PLL
+ mm_clk : out std_logic;
+ -- reset in MM clock domain released after xo_ethclk PLL locked
+ mm_rst : out std_logic;
+
+ -- reset in DP clock domain released after mm_rst and after CLK PLL locked in case g_dp_clk_use_pll=TRUE
+ dp_rst : out std_logic;
+ -- 200 MHz DP clock from CLK system clock direct or via CLK PLL dependent on g_dp_clk_use_pll
+ dp_clk : out std_logic;
+ -- PPS in dp_clk domain
+ dp_pps : out std_logic;
+ -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
+ dp_rst_in : in std_logic;
+ -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
+ dp_clk_in : in std_logic;
+
+ -- reset in MB_I_REF_CLK domain released after mm_rst
+ mb_I_ref_rst : out std_logic;
+ -- reset in MB_II_REF_CLK domain released after mm_rst
+ mb_II_ref_rst : out std_logic;
+
+ -- [1:0], so range 0-3 for PN
+ this_chip_id : out std_logic_vector(c_unb2_board_nof_chip_w - 1 downto 0);
+ -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
+ this_bck_id : out std_logic_vector(c_unb2_board_nof_uniboard_w - 1 downto 0);
app_led_red : in std_logic := '0';
app_led_green : in std_logic := '1';
-- PIOs
- pout_wdi : in std_logic; -- Toggled by unb_osy; can be overriden by reg_wdi.
+ -- Toggled by unb_osy; can be overriden by reg_wdi.
+ pout_wdi : in std_logic;
-- Manual WDI override
reg_wdi_mosi : in t_mem_mosi := c_mem_mosi_rst;
@@ -199,12 +222,16 @@ entity ctrl_unb2_board is
-- eth1g control&monitoring
eth1g_mm_rst : in std_logic;
- eth1g_tse_mosi : in t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ eth1g_tse_mosi : in t_mem_mosi;
eth1g_tse_miso : out t_mem_miso;
- eth1g_reg_mosi : in t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ eth1g_reg_mosi : in t_mem_mosi;
eth1g_reg_miso : out t_mem_miso;
- eth1g_reg_interrupt : out std_logic; -- Interrupt
- eth1g_ram_mosi : in t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ eth1g_reg_interrupt : out std_logic;
+ -- ETH rx frame and tx frame memory
+ eth1g_ram_mosi : in t_mem_mosi;
eth1g_ram_miso : out t_mem_miso;
-- eth1g UDP streaming ports
@@ -217,11 +244,16 @@ entity ctrl_unb2_board is
-- >>> Ctrl FPGA pins
--
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(g_aux.version_w - 1 downto 0);
@@ -238,20 +270,25 @@ entity ctrl_unb2_board is
PMBUS_ALERT : in std_logic := '0';
-- DDR reference clock domains reset creation
- MB_I_REF_CLK : in std_logic := '0'; -- 25 MHz
- MB_II_REF_CLK : in std_logic := '0'; -- 25 MHz
+ -- 25 MHz
+ MB_I_REF_CLK : in std_logic := '0';
+ -- 25 MHz
+ MB_II_REF_CLK : in std_logic := '0';
-- 1GbE Control Interface
- ETH_CLK : in std_logic; -- 125 MHz
+ -- 125 MHz
+ ETH_CLK : in std_logic;
ETH_SGIN : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0) := (others => '0');
ETH_SGOUT : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0)
);
end ctrl_unb2_board;
architecture str of ctrl_unb2_board is
- constant c_rom_version : natural := 1; -- Only increment when something changes to the register map of rom_system_info.
+ -- Only increment when something changes to the register map of rom_system_info.
+ constant c_rom_version : natural := 1;
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
constant c_mm_clk_freq : natural := sel_a_b(g_sim = false,g_mm_clk_freq,c_unb2_board_mm_clk_freq_10M);
-- Clock and reset
@@ -317,22 +354,27 @@ begin
INTA <= 'Z';
INTB <= 'Z';
- TESTIO <= (others => 'Z'); -- Leave unused INOUT tri-state
+ -- Leave unused INOUT tri-state
+ TESTIO <= (others => 'Z');
- ext_pps <= PPS; -- use more special name for PPS pin signal to ease searching for it in editor
+ -- use more special name for PPS pin signal to ease searching for it in editor
+ ext_pps <= PPS;
-----------------------------------------------------------------------------
-- ext_clk200 = CLK
-----------------------------------------------------------------------------
- i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
+ -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
+ i_ext_clk200 <= CLK;
u_common_areset_ext : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => i_ext_clk200,
out_rst => ext_rst200
);
@@ -341,15 +383,18 @@ begin
-- xo_ethclk = ETH_CLK
-----------------------------------------------------------------------------
- i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
+ -- use the ETH_CLK pin as xo_clk
+ i_xo_ethclk <= ETH_CLK;
u_common_areset_xo : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => i_xo_ethclk,
out_rst => i_xo_rst
);
@@ -361,22 +406,26 @@ begin
u_common_areset_mb_I : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ -- release reset some clock cycles after i_mm_rst went low
+ in_rst => i_mm_rst,
clk => MB_I_REF_CLK,
out_rst => mb_I_ref_rst
);
u_common_areset_mb_II : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ -- release reset some clock cycles after i_mm_rst went low
+ in_rst => i_mm_rst,
clk => MB_II_REF_CLK,
out_rst => mb_II_ref_rst
);
@@ -401,7 +450,8 @@ begin
port map (
arst => i_mm_rst,
clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
+ -- = c0
+ st_clk200 => dp_clk,
st_rst200 => common_areset_in_rst
);
end generate;
@@ -412,7 +462,8 @@ begin
g_delay_len => c_reset_len
)
port map (
- in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
+ -- release reset some clock cycles after i_mm_rst went low
+ in_rst => common_areset_in_rst,
clk => dp_clk_in,
out_rst => dp_rst
);
@@ -427,14 +478,20 @@ begin
clk125 when g_mm_clk_freq = c_unb2_board_mm_clk_freq_125M else
clk100 when g_mm_clk_freq = c_unb2_board_mm_clk_freq_100M else
clk50 when g_mm_clk_freq = c_unb2_board_mm_clk_freq_50M else
- clk50; -- default
+ -- default
+ clk50;
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
- mm_sim_clk <= not mm_sim_clk after 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
+ -- 20 MHz, 50ns/2
+ epcs_clk <= not epcs_clk after 25 ns;
+ -- 50 MHz, 20ns/2
+ clk50 <= not clk50 after 10 ns;
+ -- 100 MHz, 10ns/2
+ clk100 <= not clk100 after 5 ns;
+ -- 125 MHz, 8ns/2
+ clk125 <= not clk125 after 4 ns;
+ -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
+ mm_sim_clk <= not mm_sim_clk after 50 ns;
mm_locked <= '0', '1' after 70 ns;
end generate;
@@ -457,7 +514,8 @@ begin
u_unb2_board_node_ctrl : entity work.unb2_board_node_ctrl
generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us => c_mm_clk_freq / (10**6)
)
port map (
-- MM clock domain reset
@@ -466,11 +524,13 @@ begin
mm_rst => i_mm_rst,
-- WDI extend
mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ mm_wdi_out => mm_wdi,
-- Pulses
mm_pulse_us => OPEN,
mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
+ -- could be used to toggle a LED
+ mm_pulse_s => mm_pulse_s
);
-----------------------------------------------------------------------------
@@ -633,7 +693,8 @@ begin
mm_clk => i_mm_clk,
st_rst => dp_rst_in,
st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+ -- with unknown but constant phase to st_clk
+ pps_ext => ext_pps,
-- Memory-mapped clock domain
reg_mosi => reg_ppsh_mosi,
@@ -647,7 +708,8 @@ begin
-- I2C control for UniBoard sensors
------------------------------------------------------------------------------
- mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_s; -- mm_pulse_ms; ms pulse comes before the end of the I2C frame, this results in an overflow in simulation -- speed up in simulation
+ -- mm_pulse_ms; ms pulse comes before the end of the I2C frame, this results in an overflow in simulation -- speed up in simulation
+ mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_s;
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
generic map (
@@ -707,7 +769,8 @@ begin
mm_clk => i_mm_clk,
--mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
- mm_start => '1', -- this works
+ -- this works
+ mm_start => '1',
-- Memory-mapped clock domain
reg_temp_mosi => reg_fpga_temp_sens_mosi,
@@ -764,15 +827,19 @@ begin
u_eth : entity eth_lib.eth
generic map (
g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ -- Last two bytes set by board/FPGA ID.
+ g_init_ip_address => g_base_ip & X"0000",
g_cross_clock_domain => g_udp_offload,
g_frm_discard_en => true
)
port map (
-- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
+ -- use reset from QSYS
+ mm_rst => eth1g_mm_rst,
+ -- use mm_clk direct
+ mm_clk => i_mm_clk,
+ -- 125 MHz clock
+ eth_clk => i_tse_clk,
st_rst => eth1g_st_rst,
st_clk => eth1g_st_clk,
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
index f3276e71962da4539f3196a98d0488c0e136745b..0ff97341971729f677e053f0bdd988c44a0effed 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
@@ -32,20 +32,26 @@ entity mms_unb2_board_sens is
generic (
g_sim : boolean := false;
g_i2c_peripheral : natural;
- g_sens_nof_result : natural; -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
- g_clk_freq : natural := 100 * 10**6; -- clk frequency in Hz
+ -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
+ g_sens_nof_result : natural;
+ -- clk frequency in Hz
+ g_clk_freq : natural := 100 * 10**6;
g_temp_high : natural := 85;
g_comma_w : natural := 0
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
mm_start : in std_logic;
-- Memory-mapped clock domain
- reg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
- reg_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ reg_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ -- actual ranges defined by c_mm_reg
+ reg_miso : out t_mem_miso;
-- i2c bus
scl : inout std_logic := 'Z';
@@ -57,7 +63,8 @@ entity mms_unb2_board_sens is
end mms_unb2_board_sens;
architecture str of mms_unb2_board_sens is
- constant c_temp_high_w : natural := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+ -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+ constant c_temp_high_w : natural := 7;
signal sens_err : std_logic;
signal sens_data : t_slv_8_arr(0 to g_sens_nof_result - 1);
@@ -79,7 +86,8 @@ begin
sla_out => reg_miso,
-- MM registers
- sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ sens_err => sens_err,
sens_data => sens_data,
-- Max temp threshold
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
index 8116249508a7900047234ce33af9b17cac31ab6b..a4af766e438edde09bcc2efdc3265227d7d86331 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -31,13 +31,15 @@ entity mms_unb2_board_system_info is
g_sim : boolean := false;
g_technology : natural := c_tech_arria10;
g_design_name : string;
- g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version; -- firmware version x.y
+ -- firmware version x.y
+ g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version;
g_stamp_date : natural := 0;
g_stamp_time : natural := 0;
g_stamp_svn : natural := 0;
g_design_note : string := "";
g_rom_version : natural := 1;
- g_aux : t_c_unb2_board_aux := c_unb2_board_aux -- aux contains the hardware version
+ -- aux contains the hardware version
+ g_aux : t_c_unb2_board_aux := c_unb2_board_aux
);
port (
mm_rst : in std_logic;
@@ -72,12 +74,14 @@ architecture str of mms_unb2_board_system_info is
-- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
- constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
+ -- 2^10 = 1024 addresses * 32 bits = 4 kiB
+ constant c_rom_addr_w : natural := 10;
constant c_mm_rom : t_c_mem := (latency => 1,
adr_w => c_rom_addr_w,
dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ -- = 2**adr_w
+ nof_dat => 2**c_rom_addr_w,
init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
index 9697e2b7f1f752ba2a41427bec97e98a72ec56b9..194bc14fe69c4d649dda21b52abec5601a5de656 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -37,15 +37,21 @@ entity mms_unb2_fpga_sens is
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
mm_start : in std_logic;
-- Memory-mapped clock domain
- reg_temp_mosi : in t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
- reg_temp_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
- reg_voltage_mosi : in t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
- reg_voltage_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ reg_temp_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ -- actual ranges defined by c_mm_reg
+ reg_temp_miso : out t_mem_miso;
+ -- actual ranges defined by c_mm_reg
+ reg_voltage_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ -- actual ranges defined by c_mm_reg
+ reg_voltage_miso : out t_mem_miso;
-- Temperature alarm output
temp_alarm : out std_logic
@@ -53,8 +59,10 @@ entity mms_unb2_fpga_sens is
end mms_unb2_fpga_sens;
architecture str of mms_unb2_fpga_sens is
- constant c_sens_nof_result : natural := 1; --
- constant c_temp_high_w : natural := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+ --
+ constant c_sens_nof_result : natural := 1;
+ -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+ constant c_temp_high_w : natural := 7;
signal sens_err : std_logic;
signal sens_data : t_slv_8_arr(0 to c_sens_nof_result - 1);
@@ -111,5 +119,6 @@ begin
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
-- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
- temp_alarm <= '0'; -- <= '1' WHEN (SIGNED(sens_data(0)) > SIGNED('0' & temp_high)) ELSE '0';
+ -- <= '1' WHEN (SIGNED(sens_data(0)) > SIGNED('0' & temp_high)) ELSE '0';
+ temp_alarm <= '0';
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
index 48fad46da5c7c879188216a074787a6333284c9b..46b0dfbea15361c9644648ff54cac9b1d8d9d8ab 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
@@ -41,12 +41,17 @@ entity unb2_board_clk125_pll is
);
port (
arst : in std_logic := '0';
- clk125 : in std_logic := '0'; -- connect to UniBoard ETH_clk pin (125 MHz)
+ -- connect to UniBoard ETH_clk pin (125 MHz)
+ clk125 : in std_logic := '0';
- c0_clk20 : out std_logic; -- PLL c0
- c1_clk50 : out std_logic; -- PLL c1
- c2_clk100 : out std_logic; -- PLL c2
- c3_clk125 : out std_logic; -- PLL c3
+ -- PLL c0
+ c0_clk20 : out std_logic;
+ -- PLL c1
+ c1_clk50 : out std_logic;
+ -- PLL c2
+ c2_clk100 : out std_logic;
+ -- PLL c3
+ c3_clk125 : out std_logic;
pll_locked : out std_logic
);
end unb2_board_clk125_pll;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
index 9ca4ebe75e78f0da81b3f430987fdcaf05726dee..e4445bbe7195b5725733ec242ad7f68963d65cdc 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
@@ -95,20 +95,27 @@ entity unb2_board_clk200_pll is
g_technology : natural := c_tech_arria10;
g_use_clkbuf : boolean := true;
g_use_fpll : boolean := false;
- g_operation_mode : string := "NORMAL"; -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
- g_clk200_phase_shift : string := "0"; -- default use 0 degrees, see clk200_pll.vhd for other phase values
- g_clk200p_phase_shift : string := "0" -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
+ g_operation_mode : string := "NORMAL";
+ -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ g_clk200_phase_shift : string := "0";
+ -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ g_clk200p_phase_shift : string := "0"
);
port (
-- It depends on g_sel which outputs are actually available
-- . common
arst : in std_logic := '0';
- clk200 : in std_logic := '0'; -- connect to UniBoard CLK pin
- st_clk200 : out std_logic; -- PLL c0 = g_clk200_phase_shift degrees phase offset to input clk200
+ -- connect to UniBoard CLK pin
+ clk200 : in std_logic := '0';
+ -- PLL c0 = g_clk200_phase_shift degrees phase offset to input clk200
+ st_clk200 : out std_logic;
st_rst200 : out std_logic;
- st_clk200p : out std_logic; -- PLL c1 = g_clk200p_phase_shift degrees phase offset to input clk200 (see clk200_pll.vhd from MegaWizard)
+ -- PLL c1 = g_clk200p_phase_shift degrees phase offset to input clk200 (see clk200_pll.vhd from MegaWizard)
+ st_clk200p : out std_logic;
st_rst200p : out std_logic;
- st_clk400 : out std_logic; -- PLL c2 = 0 degrees phase offset to input clk200
+ -- PLL c2 = 0 degrees phase offset to input clk200
+ st_clk400 : out std_logic;
st_rst400 : out std_logic
);
end unb2_board_clk200_pll;
@@ -171,10 +178,14 @@ begin
)
port map (
areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
+ -- 200 MHz
+ inclk0 => clk200buf,
+ -- 200 MHz
+ c0 => i_st_clk200,
+ -- 200 MHz shifted 90 degrees
+ c1 => i_st_clk200p,
+ -- 400 MHz
+ c2 => i_st_clk400,
locked => st_locked
);
end generate;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
index 70d83befad5f22b82c1e67a22ed53b6e41810b3f..45400d2a83c3042f695e86d6ee4f76fddb738e97 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
@@ -39,12 +39,17 @@ entity unb2_board_clk25_pll is
);
port (
arst : in std_logic := '0';
- clk25 : in std_logic := '0'; -- connect to UniBoard ETH_clk pin (25 MHz)
+ -- connect to UniBoard ETH_clk pin (25 MHz)
+ clk25 : in std_logic := '0';
- c0_clk20 : out std_logic; -- PLL c0
- c1_clk50 : out std_logic; -- PLL c1
- c2_clk100 : out std_logic; -- PLL c2
- c3_clk125 : out std_logic; -- PLL c3
+ -- PLL c0
+ c0_clk20 : out std_logic;
+ -- PLL c1
+ c1_clk50 : out std_logic;
+ -- PLL c2
+ c2_clk100 : out std_logic;
+ -- PLL c3
+ c3_clk125 : out std_logic;
pll_locked : out std_logic
);
end unb2_board_clk25_pll;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
index 4bacebe5afdc117f5c7fa3e7c72c887bfcc81cf9..b564130e9b17da04fa5313699ec5ddc2b558d4dd 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
@@ -33,20 +33,27 @@ use common_lib.common_pkg.all;
entity unb2_board_clk_rst is
port (
-- Reference clock and reset to SOPC system PLL
- xo_clk : in std_logic; -- reference XO clock (e.g. 25 MHz also use by PLL in SOPC)
- xo_rst_n : out std_logic; -- NOT xo_rst (e.g. to reset the SOPC with NIOS2 uP)
+ -- reference XO clock (e.g. 25 MHz also use by PLL in SOPC)
+ xo_clk : in std_logic;
+ -- NOT xo_rst (e.g. to reset the SOPC with NIOS2 uP)
+ xo_rst_n : out std_logic;
-- System clock and locked from SOPC system PLL
- sys_clk : in std_logic; -- system clock derived from the reference XO clock (e.g. 125 MHz by a PLL from SOPC with NIOS2 uP)
- sys_locked : in std_logic; -- system clock PLL locked
- sys_rst : out std_logic -- system reset released some cycles after the system clock PLL has in locked
+ -- system clock derived from the reference XO clock (e.g. 125 MHz by a PLL from SOPC with NIOS2 uP)
+ sys_clk : in std_logic;
+ -- system clock PLL locked
+ sys_locked : in std_logic;
+ -- system reset released some cycles after the system clock PLL has in locked
+ sys_rst : out std_logic
);
end unb2_board_clk_rst;
architecture str of unb2_board_clk_rst is
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
-- XO clock domain
- signal xo_rst : std_logic; -- initial reset released after some XO clock cycles
+ -- initial reset released after some XO clock cycles
+ signal xo_rst : std_logic;
-- SYS clock domain
signal sys_locked_n : std_logic;
@@ -56,11 +63,13 @@ begin
u_common_areset_xo : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => xo_clk,
out_rst => xo_rst
);
@@ -70,11 +79,13 @@ begin
u_common_areset_sys : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ -- release reset after some clock cycles when the PLL has locked
+ in_rst => sys_locked_n,
clk => sys_clk,
out_rst => sys_rst
);
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
index 226d6091e3a666822673eee57b30d41e244cb5cc..ec8e674be239e810de70668dee8cec55546fe640 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
@@ -34,7 +34,8 @@ entity unb2_board_hmc_ctrl is
port (
rst : in std_logic;
clk : in std_logic;
- start : in std_logic; -- pulse to start the I2C sequence to read out the sensors
+ -- pulse to start the I2C sequence to read out the sensors
+ start : in std_logic;
out_dat : out std_logic_vector(c_byte_w - 1 downto 0);
out_val : out std_logic;
in_dat : in std_logic_vector(c_byte_w - 1 downto 0);
@@ -53,15 +54,18 @@ architecture rtl of unb2_board_hmc_ctrl is
-- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
-- Assume clk <= 200 MHz, so 5 ns period. Hence timeout of 4000 is enough.
- constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
+ -- wait 16 * 256 = 4096 clk periods
+ constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16);
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
+ -- RX supply
+ SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
+ -- TX supply
+ SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
index b37cfbaf8f11db1f8998aab9844b0589d93c76f4..bdb40e5f538af57e72b735c37d306540bd6fa226 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
@@ -32,30 +32,43 @@ use common_lib.common_pkg.all;
entity unb2_board_node_ctrl is
generic (
- g_pulse_us : natural := 125; -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- g_pulse_ms : natural := 1000; -- nof pulse_us pulses to get ms period (fixed, use less to speed up simulation)
- g_pulse_s : natural := 1000; -- nof pulse_ms pulses to get s period (fixed, use less to speed up simulation)
- g_wdi_extend_w : natural := 14 -- extend the mm_wdi_in by toggling the mm_wdi_out for about 2**(14-1)= 8 s more
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us : natural := 125;
+ -- nof pulse_us pulses to get ms period (fixed, use less to speed up simulation)
+ g_pulse_ms : natural := 1000;
+ -- nof pulse_ms pulses to get s period (fixed, use less to speed up simulation)
+ g_pulse_s : natural := 1000;
+ -- extend the mm_wdi_in by toggling the mm_wdi_out for about 2**(14-1)= 8 s more
+ g_wdi_extend_w : natural := 14
);
port (
-- MM clock domain reset
- mm_clk : in std_logic; -- MM clock
- mm_locked : in std_logic := '1'; -- MM clock PLL locked (or use default '1')
- mm_rst : out std_logic; -- MM reset released after MM clock PLL has locked
+ -- MM clock
+ mm_clk : in std_logic;
+ -- MM clock PLL locked (or use default '1')
+ mm_locked : in std_logic := '1';
+ -- MM reset released after MM clock PLL has locked
+ mm_rst : out std_logic;
-- WDI extend
- mm_wdi_in : in std_logic; -- from software running on the NIOS2 in the SOPC design
- mm_wdi_out : out std_logic; -- to FPGA pin
+ -- from software running on the NIOS2 in the SOPC design
+ mm_wdi_in : in std_logic;
+ -- to FPGA pin
+ mm_wdi_out : out std_logic;
-- Pulses
- mm_pulse_us : out std_logic; -- pulses every us
- mm_pulse_ms : out std_logic; -- pulses every ms
- mm_pulse_s : out std_logic -- pulses every s
+ -- pulses every us
+ mm_pulse_us : out std_logic;
+ -- pulses every ms
+ mm_pulse_ms : out std_logic;
+ -- pulses every s
+ mm_pulse_s : out std_logic
);
end unb2_board_node_ctrl;
architecture str of unb2_board_node_ctrl is
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
signal mm_locked_n : std_logic;
signal i_mm_rst : std_logic;
@@ -68,11 +81,13 @@ begin
u_common_areset_mm : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ -- release reset after some clock cycles when the PLL has locked
+ in_rst => mm_locked_n,
clk => mm_clk,
out_rst => i_mm_rst
);
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
index a936b7c0e6942cd9da490062dece4fb4710ee815..e4a0215d009e323b6860532ab9a13c56c5c84807 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
@@ -45,122 +45,172 @@ package unb2_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
-- *_dat_w : The default MM data width is c_word_w=32, otherwise it is specified in the record
type t_c_unb2_board_peripherals_mm_reg is record
- cross_clock_domain : boolean; -- = TRUE -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ -- = TRUE -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ cross_clock_domain : boolean;
-- 1GbE
- reg_tse_adr_w : natural; -- = 10 -- = c_tse_byte_addr_w from tse_pkg.vhd
- reg_eth_adr_w : natural; -- = 4 -- = c_eth_reg_addr_w from eth_pkg.vhd
- ram_eth_adr_w : natural; -- = 10 -- = c_eth_ram_addr_w from eth_pkg.vhd
+ -- = 10 -- = c_tse_byte_addr_w from tse_pkg.vhd
+ reg_tse_adr_w : natural;
+ -- = 4 -- = c_eth_reg_addr_w from eth_pkg.vhd
+ reg_eth_adr_w : natural;
+ -- = 10 -- = c_eth_ram_addr_w from eth_pkg.vhd
+ ram_eth_adr_w : natural;
-- pi_system_info (first word of reg_unb_system_info_adr_w is backwards compatible with the original single word PIO system info)
- reg_unb_system_info_adr_w : natural; -- = 5 -- fixed, from c_mm_reg in unb_system_info_reg
- rom_unb_system_info_adr_w : natural; -- = 10 -- fixed, from c_mm_rom in mms_unb_system_info
+ -- = 5 -- fixed, from c_mm_reg in unb_system_info_reg
+ reg_unb_system_info_adr_w : natural;
+ -- = 10 -- fixed, from c_mm_rom in mms_unb_system_info
+ rom_unb_system_info_adr_w : natural;
-- pi_reg_common
- reg_common_adr_w : natural; -- = 1 -- fixed, from c_mem_reg in mms_common_reg
+ -- = 1 -- fixed, from c_mem_reg in mms_common_reg
+ reg_common_adr_w : natural;
-- pi_ppsh
- reg_ppsh_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in ppsh_reg
+ -- = 1 -- fixed, from c_mm_reg in ppsh_reg
+ reg_ppsh_adr_w : natural;
-- pi_unb_sens
- reg_unb_sens_adr_w : natural; -- = 6 -- fixed, from c_mm_reg in unb_sens_reg
+ -- = 6 -- fixed, from c_mm_reg in unb_sens_reg
+ reg_unb_sens_adr_w : natural;
-- pi_dpmm
- reg_dpmm_data_adr_w : natural; -- = 1 -- fixed, see dp_fifo_to_mm.vhd
- reg_dpmm_ctrl_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_fifo_to_mm_reg.vhd
+ -- = 1 -- fixed, see dp_fifo_to_mm.vhd
+ reg_dpmm_data_adr_w : natural;
+ -- = 1 -- fixed, from c_mm_reg in dp_fifo_to_mm_reg.vhd
+ reg_dpmm_ctrl_adr_w : natural;
-- pi_mmdp
- reg_mmdp_data_adr_w : natural; -- = 1 -- fixed, see dp_fifo_from_mm.vhd
- reg_mmdp_ctrl_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_fifo_from_mm_reg.vhd
+ -- = 1 -- fixed, see dp_fifo_from_mm.vhd
+ reg_mmdp_data_adr_w : natural;
+ -- = 1 -- fixed, from c_mm_reg in dp_fifo_from_mm_reg.vhd
+ reg_mmdp_ctrl_adr_w : natural;
-- pi_dp_ram_from_mm
- reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
+ -- = 1 -- fixed, see dp_ram_from_mm.vhd
+ reg_dp_ram_from_mm_adr_w : natural;
-- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
-- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
- reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
+ -- = 3 -- fixed, from c_mm_reg in epcs_reg
+ reg_epcs_adr_w : natural;
-- pi_remu
- reg_remu_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in remu_reg
+ -- = 3 -- fixed, from c_mm_reg in remu_reg
+ reg_remu_adr_w : natural;
-- pi_ddr
-- pi_ddr_capture (uses DP-MM read FIFO for data access)
- reg_ddr_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in ddr_reg
+ -- = 3 -- fixed, from c_mm_reg in ddr_reg
+ reg_ddr_adr_w : natural;
-- pi_io_ddr
- reg_io_ddr_adr_w : natural; -- = 16 -- fixed, from c_mm_reg in io_ddr (3) and in io_ddr_reg (8) that get multiplexed in on addresses 0..2, 8..15
+ -- = 16 -- fixed, from c_mm_reg in io_ddr (3) and in io_ddr_reg (8) that get multiplexed in on addresses 0..2, 8..15
+ reg_io_ddr_adr_w : natural;
-- pi_tr_nonbonded
- reg_tr_nonbonded_adr_w : natural; -- = 4 -- fixed, from c_mm_reg in tr_nonbonded_reg
+ -- = 4 -- fixed, from c_mm_reg in tr_nonbonded_reg
+ reg_tr_nonbonded_adr_w : natural;
-- pi_diagnostics
- reg_diagnostics_adr_w : natural; -- = 6 -- fixed, from c_mm_reg in diagnostics_reg
+ -- = 6 -- fixed, from c_mm_reg in diagnostics_reg
+ reg_diagnostics_adr_w : natural;
-- pi_dp_throttle
- reg_dp_throttle_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in dp_throttle_reg
+ -- = 2 -- fixed, from c_mm_reg in dp_throttle_reg
+ reg_dp_throttle_adr_w : natural;
-- pi_bsn_source
- reg_bsn_source_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in dp_bsn_source_reg.vhd
+ -- = 2 -- fixed, from c_mm_reg in dp_bsn_source_reg.vhd
+ reg_bsn_source_adr_w : natural;
-- pi_bsn_schedurer
- reg_bsn_scheduler_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_bsn_scheduler_reg.vhd
+ -- = 1 -- fixed, from c_mm_reg in dp_bsn_scheduler_reg.vhd
+ reg_bsn_scheduler_adr_w : natural;
-- pi_bsn_monitor
- reg_bsn_monitor_adr_w : natural; -- = 4 -- fixed, from c_mm_reg in dp_bsn_monitor_reg.vhd
+ -- = 4 -- fixed, from c_mm_reg in dp_bsn_monitor_reg.vhd
+ reg_bsn_monitor_adr_w : natural;
-- pi_aduh_quad (defaults for ADU)
- reg_adc_quad_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in aduh_quad_reg.vhd
+ -- = 3 -- fixed, from c_mm_reg in aduh_quad_reg.vhd
+ reg_adc_quad_adr_w : natural;
-- pi_aduh_i2c_commander (defaults for ADU)
- reg_i2c_commander_adr_w : natural; -- = 6 -- = c_i2c_cmdr_aduh_i2c_mm.control_adr_w, from i2c_commander_aduh_pkg, used to pass on commander_adr_w
- ram_i2c_protocol_adr_w : natural; -- = 13 -- = c_i2c_cmdr_aduh_i2c_mm.protocol_adr_w, from i2c_commander_aduh_pkg
- ram_i2c_result_adr_w : natural; -- = 12 -- = c_i2c_cmdr_aduh_i2c_mm.result_adr_w, from i2c_commander_aduh_pkg
+ -- = 6 -- = c_i2c_cmdr_aduh_i2c_mm.control_adr_w, from i2c_commander_aduh_pkg, used to pass on commander_adr_w
+ reg_i2c_commander_adr_w : natural;
+ -- = 13 -- = c_i2c_cmdr_aduh_i2c_mm.protocol_adr_w, from i2c_commander_aduh_pkg
+ ram_i2c_protocol_adr_w : natural;
+ -- = 12 -- = c_i2c_cmdr_aduh_i2c_mm.result_adr_w, from i2c_commander_aduh_pkg
+ ram_i2c_result_adr_w : natural;
-- pi_aduh_monitor (defaults for ADU or WG used in bn_capture)
- reg_aduh_mon_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in aduh_monitor_reg.vhd
- ram_aduh_mon_dat_w : natural; -- = 32 -- = c_sp_data_w, see node_bn_capture.vhd
- ram_aduh_mon_adr_w : natural; -- = 8 -- = ceil_log2(c_bn_capture.sp.monitor_buffer_nof_samples/c_wideband_factor), see node_bn_capture.vhd
+ -- = 2 -- fixed, from c_mm_reg in aduh_monitor_reg.vhd
+ reg_aduh_mon_adr_w : natural;
+ -- = 32 -- = c_sp_data_w, see node_bn_capture.vhd
+ ram_aduh_mon_dat_w : natural;
+ -- = 8 -- = ceil_log2(c_bn_capture.sp.monitor_buffer_nof_samples/c_wideband_factor), see node_bn_capture.vhd
+ ram_aduh_mon_adr_w : natural;
-- pi_diag_wg_wideband.py (defaults for WG used in bn_capture)
- reg_diag_wg_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in diag_wg_wideband_reg
- ram_diag_wg_dat_w : natural; -- = 8 -- defined here, see bn_capture_input.vhd
- ram_diag_wg_adr_w : natural; -- = 10 -- defined here, see bn_capture_input.vhd
+ -- = 2 -- fixed, from c_mm_reg in diag_wg_wideband_reg
+ reg_diag_wg_adr_w : natural;
+ -- = 8 -- defined here, see bn_capture_input.vhd
+ ram_diag_wg_dat_w : natural;
+ -- = 10 -- defined here, see bn_capture_input.vhd
+ ram_diag_wg_adr_w : natural;
-- pi_diag_data_buffer.py
- ram_diag_db_nof_buf : natural; -- = 16
- ram_diag_db_buf_size : natural; -- = 1024
- ram_diag_db_adr_w : natural; -- = 14 -- = ram_diag_db_nof_buf*ceil_log2(ram_diag_db_buf_size)
- reg_diag_db_adr_w : natural; -- = 5 -- 32 words for 16 streams max
+ -- = 16
+ ram_diag_db_nof_buf : natural;
+ -- = 1024
+ ram_diag_db_buf_size : natural;
+ -- = 14 -- = ram_diag_db_nof_buf*ceil_log2(ram_diag_db_buf_size)
+ ram_diag_db_adr_w : natural;
+ -- = 5 -- 32 words for 16 streams max
+ reg_diag_db_adr_w : natural;
-- pi_diag_block_gen (defaults when used with the BF for Apertif)
- reg_diag_bg_adr_w : natural; -- = 3
- ram_diag_bg_adr_w : natural; -- = 11 -- = ceil_log2(c_bf.nof_subbands*c_bf.nof_signal_paths/c_bf.nof_input_streams = 24*64/16 = 96) + ceil_log2(c_bf.nof_input_streams = 16)
+ -- = 3
+ reg_diag_bg_adr_w : natural;
+ -- = 11 -- = ceil_log2(c_bf.nof_subbands*c_bf.nof_signal_paths/c_bf.nof_input_streams = 24*64/16 = 96) + ceil_log2(c_bf.nof_input_streams = 16)
+ ram_diag_bg_adr_w : natural;
-- pi_diag_tx_seq.py
- reg_diag_tx_seq_w : natural; -- = 2
+ -- = 2
+ reg_diag_tx_seq_w : natural;
-- pi_diag_tx_seq.py
- reg_diag_rx_seq_w : natural; -- = 3
+ -- = 3
+ reg_diag_rx_seq_w : natural;
-- pi_bf_bf (defaults for the BF for Apertif)
- reg_bf_offsets_adr_w : natural; -- = 5 -- = ceil_log2(c_bf.nof_offsets = 6) + ceil_log2(c_bf.nof_bf_units = 4)
- ram_bf_weights_adr_w : natural; -- = 16 -- = ceil_log2(c_bf.nof_bf_units*c_bf.nof_signal_paths*c_bf.nof_weights = 4 * 64 * 256 = 65536)
- ram_st_sst_bf_adr_w : natural; -- = 11 -- = ceil_log2(c_bf.nof_bf_units*c_bf.stat_data_sz*c_bf.nof_weights = 4 * 2 * 256 = 2048)
+ -- = 5 -- = ceil_log2(c_bf.nof_offsets = 6) + ceil_log2(c_bf.nof_bf_units = 4)
+ reg_bf_offsets_adr_w : natural;
+ -- = 16 -- = ceil_log2(c_bf.nof_bf_units*c_bf.nof_signal_paths*c_bf.nof_weights = 4 * 64 * 256 = 65536)
+ ram_bf_weights_adr_w : natural;
+ -- = 11 -- = ceil_log2(c_bf.nof_bf_units*c_bf.stat_data_sz*c_bf.nof_weights = 4 * 2 * 256 = 2048)
+ ram_st_sst_bf_adr_w : natural;
-- pi_mdio
- reg_mdio_adr_w : natural; -- = 3
+ -- = 3
+ reg_mdio_adr_w : natural;
-- dp_offload
- reg_dp_offload_tx_adr_w : natural; -- = 1
+ -- = 1
+ reg_dp_offload_tx_adr_w : natural;
-- pi_unb_fpga_sensors
- reg_fpga_temp_sens_adr_w : natural; -- = 3
- reg_fpga_voltage_sens_adr_w : natural; -- = 4
+ -- = 3
+ reg_fpga_temp_sens_adr_w : natural;
+ -- = 4
+ reg_fpga_voltage_sens_adr_w : natural;
-- pi_unb_pmbus
- reg_unb_pmbus_adr_w : natural; -- = 6
+ -- = 6
+ reg_unb_pmbus_adr_w : natural;
end record;
constant c_unb2_board_peripherals_mm_reg_default : t_c_unb2_board_peripherals_mm_reg := (true, 10, 4, 10, 5, 10, 1, 1, 6, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1, 3, 4, 6);
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
index 081135d117cace5d448362750f4499d99563a5d8..dbdaf3c9533e968845708301659f3cfa53765d66 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
@@ -28,37 +28,56 @@ use dp_lib.dp_stream_pkg.all;
package unb2_board_pkg is
-- UniBoard
- constant c_unb2_board_nof_node : natural := 4; -- number of nodes on UniBoard
- constant c_unb2_board_nof_node_w : natural := 2; -- = ceil_log2(c_unb2_board_nof_node)
- constant c_unb2_board_nof_chip : natural := c_unb2_board_nof_node; -- = 4
- constant c_unb2_board_nof_chip_w : natural := 2; -- = ceil_log2(c_unb2_board_nof_chip)
- constant c_unb2_board_nof_ddr : natural := 2; -- each node has 2 DDR modules
+ -- number of nodes on UniBoard
+ constant c_unb2_board_nof_node : natural := 4;
+ -- = ceil_log2(c_unb2_board_nof_node)
+ constant c_unb2_board_nof_node_w : natural := 2;
+ -- = 4
+ constant c_unb2_board_nof_chip : natural := c_unb2_board_nof_node;
+ -- = ceil_log2(c_unb2_board_nof_chip)
+ constant c_unb2_board_nof_chip_w : natural := 2;
+ -- each node has 2 DDR modules
+ constant c_unb2_board_nof_ddr : natural := 2;
-- Subrack
- constant c_unb2_board_nof_uniboard : natural := 4; -- nof UniBoard in a subrack
- constant c_unb2_board_nof_uniboard_w : natural := 6; -- Only 2 required for 4 boards; full width is 6.
+ -- nof UniBoard in a subrack
+ constant c_unb2_board_nof_uniboard : natural := 4;
+ -- Only 2 required for 4 boards; full width is 6.
+ constant c_unb2_board_nof_uniboard_w : natural := 6;
-- Clock frequencies
- constant c_unb2_board_ext_clk_freq_200M : natural := 200 * 10**6; -- external clock, SMA clock
- constant c_unb2_board_eth_clk_freq_25M : natural := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
- constant c_unb2_board_eth_clk_freq_125M : natural := 125 * 10**6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
- constant c_unb2_board_tse_clk_freq : natural := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
- constant c_unb2_board_cal_clk_freq : natural := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_10M : natural := 10 * 10**6; -- clock when g_sim=TRUE
- constant c_unb2_board_mm_clk_freq_25M : natural := 25 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_50M : natural := 50 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_100M : natural := 100 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_125M : natural := 125 * 10**6; -- clock derived from ETH_clk by PLL
+ -- external clock, SMA clock
+ constant c_unb2_board_ext_clk_freq_200M : natural := 200 * 10**6;
+ -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
+ constant c_unb2_board_eth_clk_freq_25M : natural := 25 * 10**6;
+ -- fixed 125 MHz ETH XO clock used as direct clock for TSE
+ constant c_unb2_board_eth_clk_freq_125M : natural := 125 * 10**6;
+ -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
+ constant c_unb2_board_tse_clk_freq : natural := 125 * 10**6;
+ -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
+ constant c_unb2_board_cal_clk_freq : natural := 40 * 10**6;
+ -- clock when g_sim=TRUE
+ constant c_unb2_board_mm_clk_freq_10M : natural := 10 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_25M : natural := 25 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_50M : natural := 50 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_100M : natural := 100 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_125M : natural := 125 * 10**6;
-- I2C
- constant c_unb2_board_reg_sens_adr_w : natural := 3; -- must match ceil_log2(c_mm_nof_dat) in unb2_board_sens_reg.vhd
+ -- must match ceil_log2(c_mm_nof_dat) in unb2_board_sens_reg.vhd
+ constant c_unb2_board_reg_sens_adr_w : natural := 3;
constant c_i2c_peripheral_sens : natural := 0;
constant c_i2c_peripheral_pmbus : natural := 1;
constant c_i2c_peripheral_hmc : natural := 2;
-- ETH
- constant c_unb2_board_nof_eth : natural := 2; -- number of ETH channels per node
+ -- number of ETH channels per node
+ constant c_unb2_board_nof_eth : natural := 2;
-- CONSTANT RECORD DECLARATIONS ---------------------------------------------
@@ -77,15 +96,19 @@ package unb2_board_pkg is
end record;
--CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (2, 24, 3); -- per node: 2 buses with 24 channels
- constant c_unb2_board_tr_back : t_c_unb2_board_tr := (1, 24, 3); -- per node: 1 buses with 24 channels (testing)
+ -- per node: 1 buses with 24 channels (testing)
+ constant c_unb2_board_tr_back : t_c_unb2_board_tr := (1, 24, 3);
--CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (2, 12, 3); -- per node: 2 buses with 24 channels (testing)
--CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (2, 4, 3); -- per node: 2 buses with 24 channels (testing)
- constant c_unb2_board_tr_ring : t_c_unb2_board_tr := (2, 12, 0); -- per node: 2 buses with 12 channels
+ -- per node: 2 buses with 12 channels
+ constant c_unb2_board_tr_ring : t_c_unb2_board_tr := (2, 12, 0);
--CONSTANT c_unb2_board_tr_ring : t_c_unb2_board_tr := (2, 4, 0); -- per node: 2 buses with 12 channels (testing)
- constant c_unb2_board_tr_qsfp : t_c_unb2_board_tr := (6, 4, 6); -- per node: 6 buses with 4 channels
- constant c_unb2_board_tr_qsfp_nof_leds : natural := c_unb2_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
+ -- per node: 6 buses with 4 channels
+ constant c_unb2_board_tr_qsfp : t_c_unb2_board_tr := (6, 4, 6);
+ -- 2 leds per qsfp
+ constant c_unb2_board_tr_qsfp_nof_leds : natural := c_unb2_board_tr_qsfp.nof_bus * 2;
type t_unb2_board_qsfp_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2_board_tr_qsfp.bus_w - 1 downto 0);
type t_unb2_board_ring_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2_board_tr_ring.bus_w - 1 downto 0);
@@ -95,12 +118,18 @@ package unb2_board_pkg is
-- Test IO Interface
type t_c_unb2_board_testio is record
- tst_w : natural; -- = nof tst = 2; [tst_w-1 +tst_lo : tst_lo] = [5:4],
- led_w : natural; -- = nof led = 2; [led_w-1 +led_lo : led_lo] = [3:2],
- jmp_w : natural; -- = nof jmp = 2; [jmp_w-1 +jmp_lo : jmp_lo] = [1:0],
- tst_lo : natural; -- = 2;
- led_lo : natural; -- = 2;
- jmp_lo : natural; -- = 0;
+ -- = nof tst = 2; [tst_w-1 +tst_lo : tst_lo] = [5:4],
+ tst_w : natural;
+ -- = nof led = 2; [led_w-1 +led_lo : led_lo] = [3:2],
+ led_w : natural;
+ -- = nof jmp = 2; [jmp_w-1 +jmp_lo : jmp_lo] = [1:0],
+ jmp_w : natural;
+ -- = 2;
+ tst_lo : natural;
+ -- = 2;
+ led_lo : natural;
+ -- = 0;
+ jmp_lo : natural;
end record;
constant c_unb2_board_testio : t_c_unb2_board_testio := (2, 2, 2, 2, 2, 0);
@@ -108,10 +137,14 @@ package unb2_board_pkg is
constant c_unb2_board_testio_led_red : natural := c_unb2_board_testio.led_lo + 1;
type t_c_unb2_board_aux is record
- version_w : natural; -- = 2;
- id_w : natural; -- = 8; -- 6+2 bits wide = total node ID for up to 64 UniBoards in a system and 4 nodes per board
- chip_id_w : natural; -- = 2; -- board node ID for the 4 FPGA nodes on a UniBoard
- testio_w : natural; -- = 6;
+ -- = 2;
+ version_w : natural;
+ -- = 8; -- 6+2 bits wide = total node ID for up to 64 UniBoards in a system and 4 nodes per board
+ id_w : natural;
+ -- = 2; -- board node ID for the 4 FPGA nodes on a UniBoard
+ chip_id_w : natural;
+ -- = 6;
+ testio_w : natural;
testio : t_c_unb2_board_testio;
end record;
@@ -120,8 +153,10 @@ package unb2_board_pkg is
type t_e_unb2_board_node is (e_any);
type t_unb2_board_fw_version is record
- hi : natural; -- = 0..15
- lo : natural; -- = 0..15, firmware version is: hi.lo
+ -- = 0..15
+ hi : natural;
+ -- = 0..15, firmware version is: hi.lo
+ lo : natural;
end record;
constant c_unb2_board_fw_version : t_unb2_board_fw_version := (0, 0);
@@ -132,19 +167,27 @@ package unb2_board_pkg is
-- . If no I2C bus arbitration or clock stretching is needed then the SCL only needs to be output.
-- . Can also be used for a PHY Management Data IO interface with serial clock MDC and serial data MDIO
type t_unb2_board_i2c_inout is record
- scl : std_logic; -- serial clock
- sda : std_logic; -- serial data
+ -- serial clock
+ scl : std_logic;
+ -- serial data
+ sda : std_logic;
end record;
-- System info
type t_c_unb2_board_system_info is record
- version : natural; -- UniBoard board HW version (2 bit value)
- id : natural; -- UniBoard FPGA node id (8 bit value)
+ -- UniBoard board HW version (2 bit value)
+ version : natural;
+ -- UniBoard FPGA node id (8 bit value)
+ id : natural;
-- Derived ID info:
- bck_id : natural; -- = id[7:2], ID part from back plane
- chip_id : natural; -- = id[1:0], ID part from UniBoard
- node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
- is_node2 : natural; -- 1 for Node 2, else 0.
+ -- = id[7:2], ID part from back plane
+ bck_id : natural;
+ -- = id[1:0], ID part from UniBoard
+ chip_id : natural;
+ -- = id[1:0], node ID: 0, 1, 2 or 3
+ node_id : natural;
+ -- 1 for Node 2, else 0.
+ is_node2 : natural;
end record;
function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
index efe7114174765639425ad726eff2c665d6c350ed..428e719af6c9ab93ce6e99d25332fc5e79431cd6 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
@@ -34,7 +34,8 @@ entity unb2_board_pmbus_ctrl is
port (
rst : in std_logic;
clk : in std_logic;
- start : in std_logic; -- pulse to start the I2C sequence to read out the sensors
+ -- pulse to start the I2C sequence to read out the sensors
+ start : in std_logic;
out_dat : out std_logic_vector(c_byte_w - 1 downto 0);
out_val : out std_logic;
in_dat : in std_logic_vector(c_byte_w - 1 downto 0);
@@ -53,15 +54,18 @@ architecture rtl of unb2_board_pmbus_ctrl is
-- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
-- Assume clk <= 200 MHz, so 5 ns period. Hence timeout of 4000 is enough.
- constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
+ -- wait 16 * 256 = 4096 clk periods
+ constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16);
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
+ -- RX supply
+ SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
+ -- TX supply
+ SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
index db1d2a02523b0507df351a6a312d529c7a741251..5c99c08d8f6f97ef8d3c6de77db7e4ef0ee2d701 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
@@ -66,10 +66,14 @@ use dp_lib.dp_stream_pkg.all;
entity unb2_board_qsfp_leds is
generic (
- g_sim : boolean := false; -- when true speed up led toggling in simulation
- g_factory_image : boolean := false; -- distinguish factory image and user images
- g_nof_qsfp : natural := 6; -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us : natural := 200 -- nof clk cycles to get us period
+ -- when true speed up led toggling in simulation
+ g_sim : boolean := false;
+ -- distinguish factory image and user images
+ g_factory_image : boolean := false;
+ -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_nof_qsfp : natural := 6;
+ -- nof clk cycles to get us period
+ g_pulse_us : natural := 200
);
port (
rst : in std_logic;
@@ -89,8 +93,10 @@ entity unb2_board_qsfp_leds is
end unb2_board_qsfp_leds;
architecture str of unb2_board_qsfp_leds is
- constant c_nof_ms : natural := sel_a_b(g_sim, 1, 100); -- force off for c_nof_ms and then on for at least c_nof_ms
- constant c_nof_lanes : natural := g_nof_qsfp * c_quad; -- number of transceiver lanes, fixed 4 per Quad-SFP cage
+ -- force off for c_nof_ms and then on for at least c_nof_ms
+ constant c_nof_ms : natural := sel_a_b(g_sim, 1, 100);
+ -- number of transceiver lanes, fixed 4 per Quad-SFP cage
+ constant c_nof_lanes : natural := g_nof_qsfp * c_quad;
signal i_pulse_ms : std_logic;
signal i_pulse_s : std_logic;
@@ -108,9 +114,12 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ -- nof clk cycles to get us period
+ g_pulse_us => g_pulse_us,
+ -- nof pulse_us pulses to get ms period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000),
+ -- nof pulse_ms pulses to get s period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000)
)
port map (
rst => rst,
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
index 877028aa9cafa4b330899aaf95b5b6d92c69e7f7..bd5017aeb33424029e0540535ff4849ae257267c 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
@@ -29,9 +29,11 @@ entity unb2_board_sens is
generic (
g_sim : boolean := false;
g_i2c_peripheral : natural;
- g_clk_freq : natural := 100 * 10**6; -- clk frequency in Hz
+ -- clk frequency in Hz
+ g_clk_freq : natural := 100 * 10**6;
g_temp_high : natural := 85;
- g_sens_nof_result : natural; -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
+ -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
+ g_sens_nof_result : natural;
g_comma_w : natural := 0
);
port (
@@ -50,7 +52,8 @@ end entity;
architecture str of unb2_board_sens is
-- I2C clock rate settings
- constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
+ -- define I2C clock rate
+ constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6));
--CONSTANT c_sens_comma_w : NATURAL := 13; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
-- 0 = no comma time
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
index 9da0c246c199f3d96b40c90dda720db9f370a1f9..ff8fc0d74b5e7938bf23a4869fe2140e97e5a0c6 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
@@ -36,7 +36,8 @@ entity unb2_board_sens_ctrl is
port (
rst : in std_logic;
clk : in std_logic;
- start : in std_logic; -- pulse to start the I2C sequence to read out the sensors
+ -- pulse to start the I2C sequence to read out the sensors
+ start : in std_logic;
out_dat : out std_logic_vector(c_byte_w - 1 downto 0);
out_val : out std_logic;
in_dat : in std_logic_vector(c_byte_w - 1 downto 0);
@@ -57,17 +58,23 @@ architecture rtl of unb2_board_sens_ctrl is
constant TMP451_REM_HI : natural := 16#01#;
constant TMP451_REM_LO : natural := 16#10#;
- constant CAT24C02_ADR_00 : natural := 16#00#; -- should contain 'H'
- constant CAT24C02_ADR_01 : natural := 16#01#; -- should contain 'a'
- constant CAT24C02_ADR_02 : natural := 16#02#; -- should contain 'r'
- constant CAT24C02_ADR_03 : natural := 16#03#; -- should contain 'r'
- constant CAT24C02_ADR_04 : natural := 16#04#; -- should contain 'o'
+ -- should contain 'H'
+ constant CAT24C02_ADR_00 : natural := 16#00#;
+ -- should contain 'a'
+ constant CAT24C02_ADR_01 : natural := 16#01#;
+ -- should contain 'r'
+ constant CAT24C02_ADR_02 : natural := 16#02#;
+ -- should contain 'r'
+ constant CAT24C02_ADR_03 : natural := 16#03#;
+ -- should contain 'o'
+ constant CAT24C02_ADR_04 : natural := 16#04#;
type t_SEQUENCE is array (natural range <>) of natural;
-- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
-- Assume clk <= 200 MHz, so 5 ns period. Hence timeout of 4000 is enough.
- constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
+ -- wait 16 * 256 = 4096 clk periods
+ constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16);
constant c_SEQ : t_SEQUENCE := (
SMBUS_READ_BYTE , I2C_UNB2_SENS_EEPROM_CAT24C02_ADR, CAT24C02_ADR_00,
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
index 9790dc3ea0f4d588f779a2cbbc1b52487596c100..e3a5015a6c5a89fb5e2548c9a8d42a1391b887aa 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
@@ -72,12 +72,16 @@ entity unb2_board_sens_reg is
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers
sens_err : in std_logic := '0';
@@ -91,12 +95,14 @@ end unb2_board_sens_reg;
architecture rtl of unb2_board_sens_reg is
-- Define the actual size of the MM slave register
- constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
+ -- +1 to fit user set temp_high one additional address
+ constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1;
-- +1 to fit sens_err in the last address
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_mm_nof_dat,
init_sl => '0');
@@ -139,14 +145,17 @@ begin
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
-- no need to capture sens_data, it is not critical if the sens_data happens to be read just before and after an I2C access occurred
if vA < g_sens_nof_result then
sla_out.rddata <= RESIZE_MEM_DATA(sens_data(vA)(c_byte_w - 1 downto 0));
elsif vA = g_sens_nof_result then
- sla_out.rddata(0) <= sens_err; -- only valid for node2
+ -- only valid for node2
+ sla_out.rddata(0) <= sens_err;
else
sla_out.rddata(6 downto 0) <= i_temp_high;
end if;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
index c3958aa4075c5c30ba82ba3ebb60a095c07d8833..46d445a6ed908106f3cd3a4b832d81bd948985ae 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
@@ -33,8 +33,10 @@ use technology_lib.technology_pkg.all;
entity unb2_board_system_info is
generic (
g_sim : boolean := false;
- g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version; -- firmware version x.y (4b.4b)
- g_aux : t_c_unb2_board_aux := c_unb2_board_aux; -- aux contains the hardware version
+ -- firmware version x.y (4b.4b)
+ g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version;
+ -- aux contains the hardware version
+ g_aux : t_c_unb2_board_aux := c_unb2_board_aux;
g_rom_version: natural := 1;
g_technology : natural := c_tech_arria10
);
@@ -43,10 +45,14 @@ entity unb2_board_system_info is
hw_version : in std_logic_vector(g_aux.version_w - 1 downto 0);
id : in std_logic_vector(g_aux.id_w - 1 downto 0);
info : out std_logic_vector(c_word_w - 1 downto 0);
- bck_id : out std_logic_vector(c_unb2_board_nof_uniboard_w - 1 downto 0); -- ID[7:2]
- chip_id : out std_logic_vector(c_unb2_board_nof_chip_w - 1 downto 0); -- ID[1:0]
- node_id : out std_logic_vector(c_unb2_board_nof_node_w - 1 downto 0); -- ID[1:0]
- is_node2 : out std_logic -- '1' for Node 2, else '0'.
+ -- ID[7:2]
+ bck_id : out std_logic_vector(c_unb2_board_nof_uniboard_w - 1 downto 0);
+ -- ID[1:0]
+ chip_id : out std_logic_vector(c_unb2_board_nof_chip_w - 1 downto 0);
+ -- ID[1:0]
+ node_id : out std_logic_vector(c_unb2_board_nof_node_w - 1 downto 0);
+ -- '1' for Node 2, else '0'.
+ is_node2 : out std_logic
);
end unb2_board_system_info;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
index 2b7a13332c5803c8e7a09da72b6fbb027358d1e5..a5de5323e9efb9fce7aa969756effee14d999175 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -72,21 +72,27 @@ entity unb2_board_system_info_reg is
end unb2_board_system_info_reg;
architecture rtl of unb2_board_system_info_reg is
- constant c_nof_fixed_regs : natural := 2; -- info, use_phy
- constant c_nof_design_name_regs : natural := 13; -- design_name
- constant c_nof_stamp_regs : natural := 3; -- date, time, svn rev
- constant c_nof_design_note_regs : natural := 13; -- note
+ -- info, use_phy
+ constant c_nof_fixed_regs : natural := 2;
+ -- design_name
+ constant c_nof_design_name_regs : natural := 13;
+ -- date, time, svn rev
+ constant c_nof_stamp_regs : natural := 3;
+ -- note
+ constant c_nof_design_note_regs : natural := 13;
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs;
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_nof_regs,
init_sl => '0');
constant c_use_phy_w : natural := 8;
- constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
+ -- Unused but keep for compatibillity
+ constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0');
constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
@@ -103,8 +109,10 @@ begin
-- Read access: get register value
if sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
vA := TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0));
if vA = 0 then
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
index e09adb5ff956c56a6a0ad91728c26da6f7fd03e3..a21c7de01379cc56010c89b8d0f5d47bc382d14a 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
@@ -37,7 +37,8 @@ entity unb2_board_wdi_extend is
port (
rst : in std_logic;
clk : in std_logic;
- pulse_ms : in std_logic; -- pulses every 1 ms
+ -- pulses every 1 ms
+ pulse_ms : in std_logic;
wdi_in : in std_logic;
wdi_out : out std_logic
);
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
index fa05af1d4f06f94cf92b05921391eaadd7b20ab7..5566944d7ac79f99cdc039ee8f0b994a06b48d0f 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
@@ -31,12 +31,16 @@ use common_lib.common_mem_pkg.all;
entity unb2_board_wdi_reg is
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
wdi_override : out std_logic
@@ -47,12 +51,14 @@ architecture rtl of unb2_board_wdi_reg is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 1,
init_sl => '0');
-- For safety, WDI override requires the following word to be written:
- constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
+ -- "Boot factory"
+ constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7";
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -75,7 +81,8 @@ begin
else
wdi_override <= '0';
end if;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
index 049c7da72e89a2425d552442030f2e3bf2964138..b3c014a6b25a859a372316d7f0f001937101441f 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
@@ -38,16 +38,22 @@ entity unb2_fpga_sens_reg is
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
start : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_temp_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_temp_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_temp_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_temp_out : out t_mem_miso;
- sla_voltage_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_voltage_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_voltage_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_voltage_out : out t_mem_miso;
-- MM registers
--sens_err : IN STD_LOGIC := '0';
@@ -61,7 +67,8 @@ end unb2_fpga_sens_reg;
architecture str of unb2_fpga_sens_reg is
--SIGNAL i_temp_high : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
- temp_high <= (others => '0'); -- i_temp_high;
+ -- i_temp_high;
+ temp_high <= (others => '0');
u_fpga_sense: entity fpga_sense_lib.fpga_sense
generic map (
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index a91ab0e90c9610711bd7a345d391b1dd8092e692..0fc1d97471de193741b402414bb05aba4c136555 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -40,7 +40,8 @@ use common_lib.tb_common_mem_pkg.all;
use work.unb2_board_pkg.all;
architecture tb of tb_mms_unb2_board_sens is
- constant c_sim : boolean := true; -- FALSE;
+ -- FALSE;
+ constant c_sim : boolean := true;
constant c_repeat : natural := 2;
constant c_clk_freq : natural := 100 * 10**6;
constant c_clk_period : time := (10**9 / c_clk_freq) * 1 ns;
@@ -48,19 +49,27 @@ architecture tb of tb_mms_unb2_board_sens is
-- Model I2C sensor slaves as on the UniBoard
constant c_temp_high : natural := 85;
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard --> hot swap = 5010 mAmpere (167)
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard --> hot swap = 48000 mVolt (120)
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard --> hot swap = 5010 mAmpere (167)
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard --> hot swap = 48000 mVolt (120)
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
constant c_sens_nof_result : natural := 4 + 1;
- constant c_sens_expected : t_natural_arr(0 to c_sens_nof_result - 1) := (60, 40, 167, 120, 0); -- 4 bytes as read by c_SEQ in unb2_board_sens_ctrl + sens_err
+ -- 4 bytes as read by c_SEQ in unb2_board_sens_ctrl + sens_err
+ constant c_sens_expected : t_natural_arr(0 to c_sens_nof_result - 1) := (60, 40, 167, 120, 0);
signal tb_end : std_logic := '0';
signal clk : std_logic := '0';
@@ -81,15 +90,18 @@ begin
clk <= (not clk) or tb_end after c_clk_period / 2;
-- I2C bus
- scl <= 'H'; -- model I2C pull up
- sda <= 'H'; -- model I2C pull up, use '0' and '1' to verify sens_err
+ -- model I2C pull up
+ scl <= 'H';
+ -- model I2C pull up, use '0' and '1' to verify sens_err
+ sda <= 'H';
scl <= scl_stretch;
sens_clk_stretch : process (scl)
begin
if falling_edge(scl) then
- scl_stretch <= '0', 'Z' after 50 ns; -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ scl_stretch <= '0', 'Z' after 50 ns;
end if;
end process;
@@ -115,7 +127,8 @@ begin
-- read I2C result data
for I in 0 to c_sens_nof_result - 1 loop
- proc_mem_mm_bus_rd(I, clk, reg_miso, reg_mosi); -- read sens_data
+ -- read sens_data
+ proc_mem_mm_bus_rd(I, clk, reg_miso, reg_mosi);
end loop;
proc_common_wait_some_cycles(clk, 1000);
@@ -132,7 +145,8 @@ begin
-- Verify sensor data
p_verify : process
begin
- wait until rising_edge(clk); -- Added this line to avoid warning: (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+ -- Added this line to avoid warning: (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+ wait until rising_edge(clk);
proc_common_wait_until_high(clk, sens_val);
assert TO_UINT(sens_dat) = c_sens_expected(0) report "Wrong FPGA temperature value" severity ERROR;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
index bd1504ec133b48c2ee0a1855949db6f37474baa8..0d0226a3a48790a33871cfa9af9889971318ab99 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
@@ -34,7 +34,8 @@ entity tb_unb2_board_clk125_pll is
end tb_unb2_board_clk125_pll;
architecture tb of tb_unb2_board_clk125_pll is
- constant c_ext_clk_period : time := 8 ns; -- 125 MHz
+ -- 125 MHz
+ constant c_ext_clk_period : time := 8 ns;
signal tb_end : std_logic := '0';
signal ext_clk : std_logic := '0';
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
index ae4e087f1ebbb885fdc524cf39c36ecfaae6575c..f98378e81605659d66785575deb3aa169b325e87 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
@@ -34,7 +34,8 @@ entity tb_unb2_board_clk200_pll is
end tb_unb2_board_clk200_pll;
architecture tb of tb_unb2_board_clk200_pll is
- constant c_ext_clk_period : time := 5 ns; -- 200 MHz
+ -- 200 MHz
+ constant c_ext_clk_period : time := 5 ns;
constant c_clk_vec_w : natural := 6;
constant c_clk_div : natural := 32;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
index b8ea88958d0d5715d52945bb2c636f11ca860615..b0890241ff7278a9e7a7934acc39b98606fcc0ce 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
@@ -34,7 +34,8 @@ entity tb_unb2_board_clk25_pll is
end tb_unb2_board_clk25_pll;
architecture tb of tb_unb2_board_clk25_pll is
- constant c_ext_clk_period : time := 40 ns; -- 25 MHz
+ -- 25 MHz
+ constant c_ext_clk_period : time := 40 ns;
signal tb_end : std_logic := '0';
signal ext_clk : std_logic := '0';
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
index 1d6125db58dc61776f1aa9f906a18959ecabfcde..726f258c911cea94a772e1fea69a0d9f78d8eace 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
@@ -28,21 +28,30 @@ entity tb_unb2_board_node_ctrl is
end tb_unb2_board_node_ctrl;
architecture tb of tb_unb2_board_node_ctrl is
- constant c_scale : natural := 100; -- scale to speed up simulation
+ -- scale to speed up simulation
+ constant c_scale : natural := 100;
- constant c_xo_clk_period : time := 1 us; -- 1 MHz XO, slow XO to speed up simulation
- constant c_mm_clk_period : time := c_xo_clk_period / 5; -- 5 MHz PLL output from XO reference
+ -- 1 MHz XO, slow XO to speed up simulation
+ constant c_xo_clk_period : time := 1 us;
+ -- 5 MHz PLL output from XO reference
+ constant c_mm_clk_period : time := c_xo_clk_period / 5;
constant c_mm_locked_time : time := 10 us;
- constant c_pulse_us : natural := 5; -- nof 5 MHz clk cycles to get us period
- constant c_pulse_ms : natural := 1000 / c_scale; -- nof pulse_us pulses to get ms period
- constant c_pulse_s : natural := 1000; -- nof pulse_ms pulses to get s period
+ -- nof 5 MHz clk cycles to get us period
+ constant c_pulse_us : natural := 5;
+ -- nof pulse_us pulses to get ms period
+ constant c_pulse_ms : natural := 1000 / c_scale;
+ -- nof pulse_ms pulses to get s period
+ constant c_pulse_s : natural := 1000;
- constant c_wdi_extend_w : natural := 14; -- extend wdi by about 2**(14-1)= 8 s (as defined by c_pulse_ms)
- constant c_wdi_period : time := 1000 ms; -- wdi toggle after c_wdi_period
+ -- extend wdi by about 2**(14-1)= 8 s (as defined by c_pulse_ms)
+ constant c_wdi_extend_w : natural := 14;
+ -- wdi toggle after c_wdi_period
+ constant c_wdi_period : time := 1000 ms;
-- Use c_sw_period=40000 ms to show that the c_wdi_extend_w=5 is not enough, the WD will kick in when the sw is off during reload
- constant c_sw_period : time := 40000 ms; -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
+ -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
+ constant c_sw_period : time := 40000 ms;
-- Use c_sw_period=10000 ms to show that the c_wdi_extend_w=5 is enough, the WD will not kick in when the sw is off during reload
--CONSTANT c_sw_period : TIME := 6000 ms; -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
@@ -65,10 +74,13 @@ begin
mm_clk <= not mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_locked_time;
- wdi <= not wdi after c_wdi_period / c_scale; -- wd interrupt
- sw <= not sw after c_sw_period / c_scale; -- sw active / reload
+ -- wd interrupt
+ wdi <= not wdi after c_wdi_period / c_scale;
+ -- sw active / reload
+ sw <= not sw after c_sw_period / c_scale;
- wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
+ -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
+ wdi_in <= wdi and sw;
dut : entity work.unb2_board_node_ctrl
generic map (
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
index 2a4f41e54767bb5b341bc1677d6083e49cee22ff..581a320642ccd6e516f1fff723614c1383a0a1e2 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
@@ -140,10 +140,14 @@ begin
u_unb2_factory_qsfp_leds : entity work.unb2_board_qsfp_leds
generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ -- when true speed up led toggling in simulation
+ g_sim => true,
+ -- distinguish factory image and user images
+ g_factory_image => true,
+ -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_nof_qsfp => c_nof_qsfp,
+ -- nof clk cycles to get us period
+ g_pulse_us => c_nof_clk_per_us
)
port map (
rst => rst,
@@ -163,10 +167,14 @@ begin
u_unb2_user_qsfp_leds : entity work.unb2_board_qsfp_leds
generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ -- when true speed up led toggling in simulation
+ g_sim => true,
+ -- distinguish factory image and user images
+ g_factory_image => false,
+ -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_nof_qsfp => c_nof_qsfp,
+ -- nof clk cycles to get us period
+ g_pulse_us => c_nof_clk_per_us
)
port map (
rst => rst,
diff --git a/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
index 1abc9ae0a3a1e55644b88e23af49158714ea4835..f8ab4b8585ada66bdee9ab16d7fb6726e7cf2bb3 100644
--- a/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
@@ -30,12 +30,16 @@ use technology_lib.technology_pkg.all;
entity unb2_board_10gbe is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 1; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 1;
g_technology : natural := c_tech_arria10;
g_nof_macs : natural;
- g_tx_fifo_fill : natural := 10; -- Release tx packet only when sufficiently data is available,
- g_tx_fifo_size : natural := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
- g_rx_fifo_size : natural := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ -- Release tx packet only when sufficiently data is available,
+ g_tx_fifo_fill : natural := 10;
+ -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ g_tx_fifo_size : natural := 256;
+ -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ g_rx_fifo_size : natural := 256;
g_word_alignment_padding : boolean := false
);
port (
@@ -48,7 +52,8 @@ entity unb2_board_10gbe is
reg_mac_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_mac_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi := c_mem_mosi_rst; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_eth10g_miso : out t_mem_miso;
reg_10gbase_r_24_mosi : in t_mem_mosi := c_mem_mosi_rst;
@@ -100,9 +105,12 @@ begin
port map (
-- Transceiver PLL reference clock
tr_ref_clk_644 => tr_ref_clk,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => tr_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => tr_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156,
-- MM interface
mm_rst => mm_rst,
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
index 4b7405306f3ac123a1f109107a81d09bce051d17..10315e489a624ef6db574d81eb421fd7683d1b63 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
@@ -43,21 +43,32 @@ entity unb2b_arp_ping is
g_design_name : string := "unb2b_arp_ping";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e1sg;
- g_sim : boolean := false; -- Overridden by TB
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision id -- set by QSF
- g_factory_image : boolean := false; -- TRUE;
+ -- Overridden by TB
+ g_sim : boolean := false;
+ -- 0 = use IP; 1 = use fast serdes model;
+ g_sim_level : natural := 0;
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision id -- set by QSF
+ g_revision_id : string := "";
+ -- TRUE;
+ g_factory_image : boolean := false;
g_protect_addr_range: boolean := false
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -132,12 +143,16 @@ architecture str of unb2b_arp_ping is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -166,8 +181,10 @@ architecture str of unb2b_arp_ping is
-- Node info
-- . Base address as used by unb_osy
- constant c_base_ip : std_logic_vector(c_16 - 1 downto 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy
- constant c_base_mac : std_logic_vector(c_32 - 1 downto 0) := X"00228608"; -- Base MAC address used by unb_osy:
+ -- Base IP address used by unb_osy: 10.99.xx.yy
+ constant c_base_ip : std_logic_vector(c_16 - 1 downto 0) := X"0A63";
+ -- Base MAC address used by unb_osy:
+ constant c_base_mac : std_logic_vector(c_32 - 1 downto 0) := X"00228608";
signal system_info : t_c_unb2b_board_system_info;
signal back_id : std_logic_vector(c_8 - 1 downto 0);
@@ -177,9 +194,12 @@ architecture str of unb2b_arp_ping is
signal src_mac : std_logic_vector(c_network_eth_mac_slv'range);
begin
system_info <= func_unb2b_board_system_info(VERSION, ID);
- back_id <= to_uvec(system_info.bck_id, c_8); -- xx = bck_id
- node_id_ip <= to_uvec(system_info.node_id + 1, c_8); -- yy = node_id +1 to avoid reserved 00
- node_id_mac <= to_uvec(system_info.node_id, c_8); -- yy = node_id
+ -- xx = bck_id
+ back_id <= to_uvec(system_info.bck_id, c_8);
+ -- yy = node_id +1 to avoid reserved 00
+ node_id_ip <= to_uvec(system_info.node_id + 1, c_8);
+ -- yy = node_id
+ node_id_mac <= to_uvec(system_info.node_id, c_8);
src_ip <= c_base_ip & back_id & node_id_ip;
src_mac <= c_base_mac & back_id & node_id_mac;
@@ -201,8 +221,10 @@ begin
g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
g_aux => c_unb2b_board_aux,
g_factory_image => g_factory_image,
- g_udp_offload => g_sim, -- use g_udp_offload to enable ETH instance in simulation
- g_udp_offload_nof_streams => 3, -- use g_udp_offload, but no UDP offload streams
+ -- use g_udp_offload to enable ETH instance in simulation
+ g_udp_offload => g_sim,
+ -- use g_udp_offload, but no UDP offload streams
+ g_udp_offload_nof_streams => 3,
g_protect_addr_range => g_protect_addr_range,
g_app_led_red => true,
g_app_led_green => true
@@ -362,7 +384,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
index e5066695940d5c016c797f682f075981cb035c43..04699804a7420fb99e8150cf2554ea8af8617bdb 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
@@ -59,9 +59,12 @@ entity tb_eth1g is
generic (
g_technology_dut : natural := c_tech_select_default;
g_technology_lcu : natural := c_tech_select_default;
- g_frm_discard_en : boolean := false; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
- g_flush_test_en : boolean := false; -- when TRUE send many large frames to enforce flush in eth_buffer
- g_tb_end : boolean := true; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+ g_frm_discard_en : boolean := false;
+ -- when TRUE send many large frames to enforce flush in eth_buffer
+ g_flush_test_en : boolean := false;
+ -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ g_tb_end : boolean := true;
-- g_data_type = c_tb_tech_tse_data_type_symbols = 0
-- g_data_type = c_tb_tech_tse_data_type_counter = 1
-- g_data_type = c_tb_tech_tse_data_type_arp = 2
@@ -75,28 +78,37 @@ entity tb_eth1g is
end tb_eth1g;
architecture tb of tb_eth1g is
- constant sys_clk_period : time := 10 ns; -- 100 MHz
- constant eth_clk_period : time := 8 ns; -- 125 MHz
+ -- 100 MHz
+ constant sys_clk_period : time := 10 ns;
+ -- 125 MHz
+ constant eth_clk_period : time := 8 ns;
constant cable_delay : time := 12 ns;
- constant c_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ constant c_cross_clock_domain : boolean := true;
-- TSE constants
constant c_promis_en : boolean := false;
- constant c_tx_ready_latency : natural := c_tech_tse_tx_ready_latency; -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
- constant c_nof_tx_not_valid : natural := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
+ constant c_tx_ready_latency : natural := c_tech_tse_tx_ready_latency;
+ -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ constant c_nof_tx_not_valid : natural := 0;
-- Payload user data
- constant c_tb_nof_data : natural := 0; -- nof UDP user data, nof ping padding data
- constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data; -- nof IP data,
+ -- nof UDP user data, nof ping padding data
+ constant c_tb_nof_data : natural := 0;
+ -- nof IP data,
+ constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data;
-- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
- constant c_tb_reply_payload : boolean := true; -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
+ -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
+ constant c_tb_reply_payload : boolean := true;
-- Packet headers
-- . Ethernet header
constant c_lcu_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"10FA01020300";
- constant c_dut_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ -- = 12-34-56-78-9A-BC
+ constant c_dut_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"123456789ABC";
constant c_dut_src_mac_hi : natural := TO_UINT(c_dut_src_mac(c_network_eth_mac_addr_w - 1 downto c_word_w));
constant c_dut_src_mac_lo : natural := TO_UINT(c_dut_src_mac( c_word_w - 1 downto 0));
-- support only ARP and IPv4 over ETH
@@ -109,12 +121,16 @@ architecture tb of tb_eth1g is
constant c_discard_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
src_mac => c_lcu_src_mac,
eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w));
- constant c_exp_eth_header : t_network_eth_header := (dst_mac => c_tx_eth_header.src_mac, -- \/
- src_mac => c_tx_eth_header.dst_mac, -- /\
- eth_type => c_tx_eth_header.eth_type); -- =
+ -- \/
+ constant c_exp_eth_header : t_network_eth_header := (dst_mac => c_tx_eth_header.src_mac,
+ -- /\
+ src_mac => c_tx_eth_header.dst_mac,
+ -- =
+ eth_type => c_tx_eth_header.eth_type);
-- . IP header
- constant c_lcu_ip_addr : natural := 16#05060708#; -- = 05:06:07:08
+ -- = 05:06:07:08
+ constant c_lcu_ip_addr : natural := 16#05060708#;
constant c_dut_ip_addr : natural := 16#01020304#;
constant c_tb_ip_total_length : natural := c_network_ip_total_length + c_tb_ip_nof_data;
@@ -131,22 +147,35 @@ architecture tb of tb_eth1g is
fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
- header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
+ -- init value (or try 0xEBBD = 60349)
+ header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w),
src_ip_addr => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
dst_ip_addr => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w));
- constant c_exp_ip_header : t_network_ip_header := (version => c_tx_ip_header.version, -- =
- header_length => c_tx_ip_header.header_length, -- =
- services => c_tx_ip_header.services, -- =
- total_length => c_tx_ip_header.total_length, -- =
- identification => c_tx_ip_header.identification, -- =
- flags => c_tx_ip_header.flags, -- =
- fragment_offset => c_tx_ip_header.fragment_offset, -- =
- time_to_live => c_tx_ip_header.time_to_live, -- =
- protocol => c_tx_ip_header.protocol, -- =
- header_checksum => c_tx_ip_header.header_checksum, -- init value
- src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
- dst_ip_addr => c_tx_ip_header.src_ip_addr); -- /\
+ -- =
+ constant c_exp_ip_header : t_network_ip_header := (version => c_tx_ip_header.version,
+ -- =
+ header_length => c_tx_ip_header.header_length,
+ -- =
+ services => c_tx_ip_header.services,
+ -- =
+ total_length => c_tx_ip_header.total_length,
+ -- =
+ identification => c_tx_ip_header.identification,
+ -- =
+ flags => c_tx_ip_header.flags,
+ -- =
+ fragment_offset => c_tx_ip_header.fragment_offset,
+ -- =
+ time_to_live => c_tx_ip_header.time_to_live,
+ -- =
+ protocol => c_tx_ip_header.protocol,
+ -- init value
+ header_checksum => c_tx_ip_header.header_checksum,
+ -- \/
+ src_ip_addr => c_tx_ip_header.dst_ip_addr,
+ -- /\
+ dst_ip_addr => c_tx_ip_header.src_ip_addr);
-- . ARP packet
constant c_tx_arp_packet : t_network_arp_packet := (htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
@@ -163,58 +192,89 @@ architecture tb of tb_eth1g is
ptype => c_tx_arp_packet.ptype,
hlen => c_tx_arp_packet.hlen,
plen => c_tx_arp_packet.plen,
- oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
- sha => c_tx_arp_packet.tha, -- \/
- spa => c_tx_arp_packet.tpa, -- /\ \/
- tha => c_tx_arp_packet.sha, -- / \ /\
- tpa => c_tx_arp_packet.spa); -- / \
+ -- reply
+ oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w),
+ -- \/
+ sha => c_tx_arp_packet.tha,
+ -- /\ \/
+ spa => c_tx_arp_packet.tpa,
+ -- / \ /\
+ tha => c_tx_arp_packet.sha,
+ -- / \
+ tpa => c_tx_arp_packet.spa);
-- . ICMP header
- constant c_tx_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w), -- ping request
+ -- ping request
+ constant c_tx_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w),
code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
- checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
+ -- init value
+ checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w),
id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
- constant c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
+ -- ping reply
+ constant c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w),
code => c_tx_icmp_header.code,
- checksum => c_tx_icmp_header.checksum, -- init value
+ -- init value
+ checksum => c_tx_icmp_header.checksum,
id => c_tx_icmp_header.id,
sequence => c_tx_icmp_header.sequence);
-- . UDP header
- constant c_dut_udp_port_ctrl : natural := 11; -- ETH demux UDP for control
- constant c_dut_udp_port_st0 : natural := 57; -- ETH demux UDP port 0
- constant c_dut_udp_port_st1 : natural := 58; -- ETH demux UDP port 1
- constant c_dut_udp_port_st2 : natural := 59; -- ETH demux UDP port 2
- constant c_dut_udp_port_en : natural := 16#10000#; -- ETH demux UDP port enable bit 16
- constant c_lcu_udp_port : natural := 10; -- UDP port used for src_port
- constant c_dut_udp_port_st : natural := c_dut_udp_port_st0; -- UDP port used for dst_port
+ -- ETH demux UDP for control
+ constant c_dut_udp_port_ctrl : natural := 11;
+ -- ETH demux UDP port 0
+ constant c_dut_udp_port_st0 : natural := 57;
+ -- ETH demux UDP port 1
+ constant c_dut_udp_port_st1 : natural := 58;
+ -- ETH demux UDP port 2
+ constant c_dut_udp_port_st2 : natural := 59;
+ -- ETH demux UDP port enable bit 16
+ constant c_dut_udp_port_en : natural := 16#10000#;
+ -- UDP port used for src_port
+ constant c_lcu_udp_port : natural := 10;
+ -- UDP port used for dst_port
+ constant c_dut_udp_port_st : natural := c_dut_udp_port_st0;
constant c_tb_udp_total_length : natural := c_network_udp_total_length + c_tb_nof_data;
constant c_tx_udp_header : t_network_udp_header := (src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
- dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
+ -- or use c_dut_udp_port_st#
+ dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w),
total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
- checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
-
- constant c_exp_udp_header : t_network_udp_header := (src_port => c_tx_udp_header.dst_port, -- \/
- dst_port => c_tx_udp_header.src_port, -- /\
- total_length => c_tx_udp_header.total_length, -- =
- checksum => c_tx_udp_header.checksum); -- init value
-
- signal tx_total_header : t_network_total_header; -- transmitted packet header
- signal discard_total_header: t_network_total_header; -- transmitted packet header for to be discarded packet
- signal exp_total_header : t_network_total_header; -- expected received packet header
+ -- init value
+ checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w));
+
+ -- \/
+ constant c_exp_udp_header : t_network_udp_header := (src_port => c_tx_udp_header.dst_port,
+ -- /\
+ dst_port => c_tx_udp_header.src_port,
+ -- =
+ total_length => c_tx_udp_header.total_length,
+ -- init value
+ checksum => c_tx_udp_header.checksum);
+
+ -- transmitted packet header
+ signal tx_total_header : t_network_total_header;
+ -- transmitted packet header for to be discarded packet
+ signal discard_total_header: t_network_total_header;
+ -- expected received packet header
+ signal exp_total_header : t_network_total_header;
-- ETH control
constant c_dut_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
constant c_dut_control_tx_en : natural := 2**c_eth_mm_reg_control_bi.tx_en;
-- Clocks and reset
- signal eth_clk : std_logic := '0'; -- tse reference clock
- signal sys_clk : std_logic := '0'; -- system clock
- signal st_clk : std_logic; -- stream clock
- signal st_rst : std_logic := '1'; -- reset synchronous with st_clk
- signal mm_clk : std_logic; -- memory-mapped bus clock
- signal mm_rst : std_logic := '1'; -- reset synchronous with mm_clk
+ -- tse reference clock
+ signal eth_clk : std_logic := '0';
+ -- system clock
+ signal sys_clk : std_logic := '0';
+ -- stream clock
+ signal st_clk : std_logic;
+ -- reset synchronous with st_clk
+ signal st_rst : std_logic := '1';
+ -- memory-mapped bus clock
+ signal mm_clk : std_logic;
+ -- reset synchronous with mm_clk
+ signal mm_rst : std_logic := '1';
-- ETH TSE interface
signal dut_tse_init : std_logic := '1';
@@ -271,8 +331,10 @@ architecture tb of tb_eth1g is
begin
-- run 50 us
- eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
- sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
+ -- TSE reference clock
+ eth_clk <= not eth_clk after eth_clk_period / 2;
+ -- System clock
+ sys_clk <= not sys_clk after sys_clk_period / 2;
mm_clk <= sys_clk;
st_clk <= sys_clk;
@@ -343,20 +405,28 @@ begin
while mm_rst = '1' loop wait until rising_edge(mm_clk); end loop;
-- Setup the DEMUX UDP
- proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 0, c_dut_udp_port_en + c_dut_udp_port_st0, mm_clk, eth_reg_miso, eth_reg_mosi); -- UDP port stream 0
- proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 1, c_dut_udp_port_en + c_dut_udp_port_st1, mm_clk, eth_reg_miso, eth_reg_mosi); -- UDP port stream 1
- proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 2, c_dut_udp_port_en + c_dut_udp_port_st2, mm_clk, eth_reg_miso, eth_reg_mosi); -- UDP port stream 2
+ -- UDP port stream 0
+ proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 0, c_dut_udp_port_en + c_dut_udp_port_st0, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- UDP port stream 1
+ proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 1, c_dut_udp_port_en + c_dut_udp_port_st1, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- UDP port stream 2
+ proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 2, c_dut_udp_port_en + c_dut_udp_port_st2, mm_clk, eth_reg_miso, eth_reg_mosi);
proc_mem_mm_bus_rd(c_eth_reg_demux_wi + 0, mm_clk, eth_reg_miso, eth_reg_mosi);
proc_mem_mm_bus_rd(c_eth_reg_demux_wi + 1, mm_clk, eth_reg_miso, eth_reg_mosi);
proc_mem_mm_bus_rd(c_eth_reg_demux_wi + 2, mm_clk, eth_reg_miso, eth_reg_mosi);
-- Setup the RX config
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 0, c_dut_src_mac_lo, mm_clk, eth_reg_miso, eth_reg_mosi); -- control MAC address lo word
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 1, c_dut_src_mac_hi, mm_clk, eth_reg_miso, eth_reg_mosi); -- control MAC address hi halfword
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 2, c_dut_ip_addr, mm_clk, eth_reg_miso, eth_reg_mosi); -- control IP address
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 3, c_dut_udp_port_ctrl, mm_clk, eth_reg_miso, eth_reg_mosi); -- control UDP port
+ -- control MAC address lo word
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 0, c_dut_src_mac_lo, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- control MAC address hi halfword
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 1, c_dut_src_mac_hi, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- control IP address
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 2, c_dut_ip_addr, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- control UDP port
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 3, c_dut_udp_port_ctrl, mm_clk, eth_reg_miso, eth_reg_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_dut_control_rx_en, mm_clk, eth_reg_miso, eth_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_dut_control_rx_en, mm_clk, eth_reg_miso, eth_reg_mosi);
dut_eth_init <= '0';
-- Wait for TSE init
@@ -369,15 +439,18 @@ begin
-- wait for rx_avail interrupt
if eth_reg_interrupt = '1' then
-- read status register to read the status
- proc_mem_mm_bus_rd(c_eth_reg_status_wi + 0, mm_clk, eth_reg_miso, eth_reg_mosi); -- read result available in eth_mm_reg_status
+ -- read result available in eth_mm_reg_status
+ proc_mem_mm_bus_rd(c_eth_reg_status_wi + 0, mm_clk, eth_reg_miso, eth_reg_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
eth_mm_reg_status <= func_eth_mm_reg_status(eth_reg_miso.rddata);
wait until rising_edge(mm_clk);
-- write status register to acknowledge the interrupt
- proc_mem_mm_bus_wr(c_eth_reg_status_wi + 0, 0, mm_clk, eth_reg_miso, eth_reg_mosi); -- void value
+ -- void value
+ proc_mem_mm_bus_wr(c_eth_reg_status_wi + 0, 0, mm_clk, eth_reg_miso, eth_reg_mosi);
-- prepare control register for response
if c_tb_reply_payload = true then
- eth_mm_reg_control.tx_nof_words <= INCR_UVEC(eth_mm_reg_status.rx_nof_words, -1); -- -1 to skip the CRC word for the response
+ -- -1 to skip the CRC word for the response
+ eth_mm_reg_control.tx_nof_words <= INCR_UVEC(eth_mm_reg_status.rx_nof_words, -1);
eth_mm_reg_control.tx_empty <= eth_mm_reg_status.rx_empty;
else
eth_mm_reg_control.tx_nof_words <= TO_UVEC(c_network_total_header_32b_nof_words, c_eth_max_frame_nof_words_w);
@@ -402,7 +475,8 @@ begin
v_eth_control_word := func_eth_mm_reg_control(eth_mm_reg_control);
proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, TO_UINT(v_eth_control_word), mm_clk, eth_reg_miso, eth_reg_mosi);
-- write continue register to make the ETH module continue
- proc_mem_mm_bus_wr(c_eth_reg_continue_wi, 0, mm_clk, eth_reg_miso, eth_reg_mosi); -- void value
+ -- void value
+ proc_mem_mm_bus_wr(c_eth_reg_continue_wi, 0, mm_clk, eth_reg_miso, eth_reg_mosi);
end if;
wait until rising_edge(mm_clk);
end loop;
@@ -441,7 +515,8 @@ begin
lcu_tx_sosi.empty <= (others => '0');
lcu_tx_sosi.err <= (others => '0');
-- . MAC specific
- lcu_tx_mac_in.crc_fwd <= '0'; -- when '0' then TSE MAC generates the TX CRC field
+ -- when '0' then TSE MAC generates the TX CRC field
+ lcu_tx_mac_in.crc_fwd <= '0';
while lcu_init /= '0' loop wait until rising_edge(st_clk); end loop;
for I in 0 to 9 loop wait until rising_edge(st_clk); end loop;
@@ -610,7 +685,8 @@ begin
rx_timeout <= rx_timeout + 1;
if lcu_rx_sosi.valid = '1' then
rx_timeout <= 0;
- elsif rx_timeout > 5000 then -- sufficiently large value determined by trial
+ -- sufficiently large value determined by trial
+ elsif rx_timeout > 5000 then
rx_end <= '1';
end if;
wait until rising_edge(st_clk);
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
index ce140222f1027601e53316b1a3479af8727686f2..da4c6d52f0b40afdb5eddd72c30f180e8fc18787 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
@@ -43,7 +43,8 @@ architecture tb of tb_tb_eth1g is
constant c_technology_lcu : natural := c_tech_select_default;
constant c_tb_end_vec : std_logic_vector(15 downto 0) := (others => '1');
- signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ -- sufficiently long to fit all tb instances
+ signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec;
signal tb_end : std_logic := '0';
begin
-- g_technology_dut : NATURAL := c_tech_select_default;
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
index 7acf42ed8e04c75dc18ba3b005bbfcc6e48bbc9a..244547b5f16835f125a9cd1359e1a24ca99b956f 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
@@ -58,15 +58,18 @@ use technology_lib.technology_select_pkg.all;
entity tb_unb2b_arp_ping is
generic (
- g_frm_discard_en : boolean := false; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
- g_flush_test_en : boolean := false; -- when TRUE send many large frames to enforce flush in eth_buffer
+ -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+ g_frm_discard_en : boolean := false;
+ -- when TRUE send many large frames to enforce flush in eth_buffer
+ g_flush_test_en : boolean := false;
-- g_data_type = c_tb_tech_tse_data_type_symbols = 0
-- g_data_type = c_tb_tech_tse_data_type_counter = 1
-- g_data_type = c_tb_tech_tse_data_type_arp = 2
-- g_data_type = c_tb_tech_tse_data_type_ping = 3
-- g_data_type = c_tb_tech_tse_data_type_udp = 4
g_data_type : natural := c_tb_tech_tse_data_type_ping;
- g_tb_end : boolean := true -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ g_tb_end : boolean := true
);
port (
tb_end : out std_logic
@@ -74,21 +77,31 @@ entity tb_unb2b_arp_ping is
end tb_unb2b_arp_ping;
architecture tb of tb_unb2b_arp_ping is
- constant c_sim : boolean := false; -- TRUE;
- constant c_sim_level : natural := 1; -- 0 = use IP; 1 = use fast serdes model;
-
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- TRUE;
+ constant c_sim : boolean := false;
+ -- 0 = use IP; 1 = use fast serdes model;
+ constant c_sim_level : natural := 1;
+
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb2b_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2b_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
- constant c_cable_delay : time := 12 ns; -- 12 ns;
- constant c_clk_period : time := 5 ns; -- 200 MHz
- constant c_st_clk_period : time := 5 ns; -- 200 MHz
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz
- constant c_tse_clk_period : time := 8 ns; -- 125 MHz
- constant c_mm_clk_period : time := 10 ns; -- 100 MHz
+ -- 12 ns;
+ constant c_cable_delay : time := 12 ns;
+ -- 200 MHz
+ constant c_clk_period : time := 5 ns;
+ -- 200 MHz
+ constant c_st_clk_period : time := 5 ns;
+ -- 125 MHz
+ constant c_eth_clk_period : time := 8 ns;
+ -- 125 MHz
+ constant c_tse_clk_period : time := 8 ns;
+ -- 100 MHz
+ constant c_mm_clk_period : time := 10 ns;
constant c_pps_period : natural := 1000;
-----------------------------------------------------------------------------
@@ -96,16 +109,20 @@ architecture tb of tb_unb2b_arp_ping is
-----------------------------------------------------------------------------
-- Base address as used by unb_osy
- constant c_base_ip : std_logic_vector(c_16 - 1 downto 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy
- constant c_base_mac : std_logic_vector(c_32 - 1 downto 0) := X"00228608"; -- Base MAC address used by unb_osy: 00228608_xx_yy
+ -- Base IP address used by unb_osy: 10.99.xx.yy
+ constant c_base_ip : std_logic_vector(c_16 - 1 downto 0) := X"0A63";
+ -- Base MAC address used by unb_osy: 00228608_xx_yy
+ constant c_base_mac : std_logic_vector(c_32 - 1 downto 0) := X"00228608";
-- Network addresses
constant c_dut_src_ip : std_logic_vector(c_network_ip_addr_slv'range) := c_base_ip & TO_UVEC(c_unb_nr, c_8) & TO_UVEC(c_node_nr + 1, c_8);
constant c_dut_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_base_mac & TO_UVEC(c_unb_nr, c_8) & TO_UVEC(c_node_nr, c_8);
-- Clocks and reset
- signal sys_clk : std_logic := '0'; -- system clock
- signal eth_clk : std_logic := '0'; -- eth / tse reference clock
+ -- system clock
+ signal sys_clk : std_logic := '0';
+ -- eth / tse reference clock
+ signal eth_clk : std_logic := '0';
-- DUT
signal pps : std_logic := '0';
@@ -145,10 +162,13 @@ architecture tb of tb_unb2b_arp_ping is
constant c_lcu_src_ip : std_logic_vector(c_network_ip_addr_slv'range) := X"05060708";
constant c_lcu_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"10FA01020300";
- signal tse_clk : std_logic := '0'; -- tse reference clock
- signal st_clk : std_logic := '0'; -- stream clock
+ -- tse reference clock
+ signal tse_clk : std_logic := '0';
+ -- stream clock
+ signal st_clk : std_logic := '0';
signal st_rst : std_logic := '1';
- signal mm_clk : std_logic := '0'; -- MM bus clock
+ -- MM bus clock
+ signal mm_clk : std_logic := '0';
signal mm_rst : std_logic := '1';
-- TSE interface
@@ -167,7 +187,8 @@ architecture tb of tb_unb2b_arp_ping is
signal lcu_led : t_tech_tse_led;
-- TSE constants
- constant c_tx_ready_latency : natural := c_tech_tse_tx_ready_latency; -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
+ -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
+ constant c_tx_ready_latency : natural := c_tech_tse_tx_ready_latency;
constant c_promis_en : boolean := false;
-----------------------------------------------------------------------------
@@ -180,15 +201,20 @@ architecture tb of tb_unb2b_arp_ping is
signal tx_pkt_cnt : natural := 0;
signal rx_pkt_cnt : natural := 0;
signal rx_pkt_discarded_cnt: natural := 0;
- signal rx_pkt_flushed_cnt : std_logic_vector(c_word_w - 1 downto 0) := (others => '0'); -- maintained in DUT, but not accessible in tb
+ -- maintained in DUT, but not accessible in tb
+ signal rx_pkt_flushed_cnt : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
- constant c_nof_tx_not_valid : natural := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ constant c_nof_tx_not_valid : natural := 0;
-- Payload user data
- constant c_tb_nof_data : natural := 0; -- nof UDP user data, nof ping padding data
- constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data; -- nof IP data,
+ -- nof UDP user data, nof ping padding data
+ constant c_tb_nof_data : natural := 0;
+ -- nof IP data,
+ constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data;
-- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
- constant c_tb_reply_payload : boolean := true; -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
+ -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
+ constant c_tb_reply_payload : boolean := true;
-- Packet headers
-- support only ARP and IPv4 over ETH
@@ -201,9 +227,12 @@ architecture tb of tb_unb2b_arp_ping is
constant c_discard_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
src_mac => c_lcu_src_mac,
eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w));
- constant c_exp_eth_header : t_network_eth_header := (dst_mac => c_tx_eth_header.src_mac, -- \/
- src_mac => c_tx_eth_header.dst_mac, -- /\
- eth_type => c_tx_eth_header.eth_type); -- =
+ -- \/
+ constant c_exp_eth_header : t_network_eth_header := (dst_mac => c_tx_eth_header.src_mac,
+ -- /\
+ src_mac => c_tx_eth_header.dst_mac,
+ -- =
+ eth_type => c_tx_eth_header.eth_type);
-- . IP header
constant c_tb_ip_total_length : natural := c_network_ip_total_length + c_tb_ip_nof_data;
@@ -221,22 +250,35 @@ architecture tb of tb_unb2b_arp_ping is
fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
- header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
+ -- init value (or try 0xEBBD = 60349)
+ header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w),
src_ip_addr => c_lcu_src_ip,
dst_ip_addr => c_dut_src_ip);
- constant c_exp_ip_header : t_network_ip_header := (version => c_tx_ip_header.version, -- =
- header_length => c_tx_ip_header.header_length, -- =
- services => c_tx_ip_header.services, -- =
- total_length => c_tx_ip_header.total_length, -- =
- identification => c_tx_ip_header.identification, -- =
- flags => c_tx_ip_header.flags, -- =
- fragment_offset => c_tx_ip_header.fragment_offset, -- =
- time_to_live => c_tx_ip_header.time_to_live, -- =
- protocol => c_tx_ip_header.protocol, -- =
- header_checksum => c_tx_ip_header.header_checksum, -- init value
- src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
- dst_ip_addr => c_tx_ip_header.src_ip_addr); -- /\
+ -- =
+ constant c_exp_ip_header : t_network_ip_header := (version => c_tx_ip_header.version,
+ -- =
+ header_length => c_tx_ip_header.header_length,
+ -- =
+ services => c_tx_ip_header.services,
+ -- =
+ total_length => c_tx_ip_header.total_length,
+ -- =
+ identification => c_tx_ip_header.identification,
+ -- =
+ flags => c_tx_ip_header.flags,
+ -- =
+ fragment_offset => c_tx_ip_header.fragment_offset,
+ -- =
+ time_to_live => c_tx_ip_header.time_to_live,
+ -- =
+ protocol => c_tx_ip_header.protocol,
+ -- init value
+ header_checksum => c_tx_ip_header.header_checksum,
+ -- \/
+ src_ip_addr => c_tx_ip_header.dst_ip_addr,
+ -- /\
+ dst_ip_addr => c_tx_ip_header.src_ip_addr);
-- . ARP packet
constant c_tx_arp_packet : t_network_arp_packet := (htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
@@ -253,62 +295,90 @@ architecture tb of tb_unb2b_arp_ping is
ptype => c_tx_arp_packet.ptype,
hlen => c_tx_arp_packet.hlen,
plen => c_tx_arp_packet.plen,
- oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
- sha => c_tx_arp_packet.tha, -- \/
- spa => c_tx_arp_packet.tpa, -- /\ \/
- tha => c_tx_arp_packet.sha, -- / \ /\
- tpa => c_tx_arp_packet.spa); -- / \
+ -- reply
+ oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w),
+ -- \/
+ sha => c_tx_arp_packet.tha,
+ -- /\ \/
+ spa => c_tx_arp_packet.tpa,
+ -- / \ /\
+ tha => c_tx_arp_packet.sha,
+ -- / \
+ tpa => c_tx_arp_packet.spa);
-- . ICMP header
- constant c_tx_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w), -- ping request
+ -- ping request
+ constant c_tx_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w),
code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
- checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
+ -- init value
+ checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w),
id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
- constant c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
+ -- ping reply
+ constant c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w),
code => c_tx_icmp_header.code,
- checksum => c_tx_icmp_header.checksum, -- init value
+ -- init value
+ checksum => c_tx_icmp_header.checksum,
id => c_tx_icmp_header.id,
sequence => c_tx_icmp_header.sequence);
-- . UDP header
- constant c_dut_udp_port_ctrl : natural := 11; -- ETH demux UDP for control
- constant c_lcu_udp_port : natural := 10; -- UDP port used for src_port
+ -- ETH demux UDP for control
+ constant c_dut_udp_port_ctrl : natural := 11;
+ -- UDP port used for src_port
+ constant c_lcu_udp_port : natural := 10;
constant c_tb_udp_total_length : natural := c_network_udp_total_length + c_tb_nof_data;
constant c_tx_udp_header : t_network_udp_header := (src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
- dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
+ -- or use c_dut_udp_port_st#
+ dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w),
total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
- checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
-
- constant c_exp_udp_header : t_network_udp_header := (src_port => c_tx_udp_header.dst_port, -- \/
- dst_port => c_tx_udp_header.src_port, -- /\
- total_length => c_tx_udp_header.total_length, -- =
- checksum => c_tx_udp_header.checksum); -- init value
-
- signal tx_total_header : t_network_total_header; -- transmitted packet header
- signal discard_total_header: t_network_total_header; -- transmitted packet header for to be discarded packet
- signal exp_total_header : t_network_total_header; -- expected received packet header
+ -- init value
+ checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w));
+
+ -- \/
+ constant c_exp_udp_header : t_network_udp_header := (src_port => c_tx_udp_header.dst_port,
+ -- /\
+ dst_port => c_tx_udp_header.src_port,
+ -- =
+ total_length => c_tx_udp_header.total_length,
+ -- init value
+ checksum => c_tx_udp_header.checksum);
+
+ -- transmitted packet header
+ signal tx_total_header : t_network_total_header;
+ -- transmitted packet header for to be discarded packet
+ signal discard_total_header: t_network_total_header;
+ -- expected received packet header
+ signal exp_total_header : t_network_total_header;
begin
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
- sys_clk <= not sys_clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
+ -- External clock (200 MHz)
+ sys_clk <= not sys_clk after c_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
-- External PPS
proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, sys_clk, pps);
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
- PMBUS_SC <= 'H'; -- pull up
- PMBUS_SD <= 'H'; -- pull up
+ -- pull up
+ PMBUS_SC <= 'H';
+ -- pull up
+ PMBUS_SD <= 'H';
u_dut : entity work.unb2b_arp_ping
generic map (
@@ -356,9 +426,12 @@ begin
-- LCU Ethernet model
------------------------------------------------------------------------------
- tse_clk <= not tse_clk after c_tse_clk_period / 2; -- TSE clock for LCU model
- st_clk <= not st_clk after c_st_clk_period / 2; -- System clock for LCU model
- mm_clk <= not mm_clk after c_mm_clk_period / 2; -- MM clock for LCU model
+ -- TSE clock for LCU model
+ tse_clk <= not tse_clk after c_tse_clk_period / 2;
+ -- System clock for LCU model
+ st_clk <= not st_clk after c_st_clk_period / 2;
+ -- MM clock for LCU model
+ mm_clk <= not mm_clk after c_mm_clk_period / 2;
st_rst <= '1', '0' after 10 * c_st_clk_period;
mm_rst <= '1', '0' after 10 * c_mm_clk_period;
@@ -445,7 +518,8 @@ begin
-- . Avalon ST
lcu_tx_sosi <= c_dp_sosi_rst;
-- . MAC specific
- lcu_tx_mac_in.crc_fwd <= '0'; -- when '0' then TSE MAC generates the TX CRC field
+ -- when '0' then TSE MAC generates the TX CRC field
+ lcu_tx_mac_in.crc_fwd <= '0';
while lcu_init /= '0' loop wait until rising_edge(st_clk); end loop;
@@ -538,7 +612,8 @@ begin
rx_timeout <= rx_timeout + 1;
if lcu_rx_sosi.valid = '1' then
rx_timeout <= 0;
- elsif rx_timeout > 5000 then -- sufficiently large value determined by trial
+ -- sufficiently large value determined by trial
+ elsif rx_timeout > 5000 then
rx_end <= '1';
end if;
wait until rising_edge(st_clk);
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
index ccfa91c51360b894621e7c726d976f3ca44be5c8..7d7b3b783e6134cbd6bdd5d86b3842da6c1ef5fd 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
@@ -32,7 +32,8 @@ use work.qsys_unb2b_heater_pkg.all;
entity mmm_unb2b_heater is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
index b36fb7ceda0540405cad0b725787029d599db6c2..c7fe109cd8420fdfc5021687369931a9a0a72a72 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
@@ -28,133 +28,260 @@ package qsys_unb2b_heater_pkg is
-----------------------------------------------------------------------------
component qsys_unb2b_heater is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_reset_export : out std_logic; -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_heater_clk_export : out std_logic;
+ -- export
+ reg_heater_read_export : out std_logic;
+ -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_heater_reset_export : out std_logic;
+ -- export
+ reg_heater_write_export : out std_logic;
+ -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic;
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0)
);
end component qsys_unb2b_heater;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
index be12b6758a30a849d1b19047b11e49d489991e88..c9b8280150546af00155ca166503a53ec8e5c7cf 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
@@ -34,21 +34,30 @@ entity unb2b_heater is
g_design_name : string := "unb2b_heater";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e1sg;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- GIT revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- GIT revision -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := false
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -121,12 +130,16 @@ architecture str of unb2b_heater is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -174,7 +187,8 @@ begin
g_dp_clk_use_pll => true,
g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
g_aux => c_unb2b_board_aux,
- g_tse_clk_buf => false, -- TRUE,
+ -- TRUE,
+ g_tse_clk_buf => false,
g_factory_image => g_factory_image
)
port map (
@@ -362,7 +376,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
@@ -386,10 +401,14 @@ begin
g_technology => g_technology,
--g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
--g_nof_mac4 => 630 --
- g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
- g_pipeline => 72, -- max 72
- g_nof_ram => 4, -- max 4
- g_nof_logic => 24 -- max 24
+ -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
+ g_nof_mac4 => 736,
+ -- max 72
+ g_pipeline => 72,
+ -- max 4
+ g_nof_ram => 4,
+ -- max 24
+ g_nof_logic => 24
)
port map (
mm_rst => mm_rst,
diff --git a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
index aec05451addeae374aa66e1819b2f275f8230316..291d4a57f26307c901ff160ed7c5a24910c9e87e 100644
--- a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
@@ -52,23 +52,28 @@ use common_lib.tb_common_pkg.all;
entity tb_unb2b_heater is
generic (
g_design_name : string := "unb2b_heater";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Node 3
+ g_sim_node_nr : natural := 3
);
end tb_unb2b_heater;
architecture tb of tb_unb2b_heater is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb2b_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2b_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -99,31 +104,46 @@ architecture tb of tb_unb2b_heater is
signal qsfp_led : std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
-
- PMBUS_SC <= 'H'; -- pull up
- PMBUS_SD <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+
+ -- pull up
+ PMBUS_SC <= 'H';
+ -- pull up
+ PMBUS_SD <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
index 1188b1f4a3a8c3bda14f3b6fb3aaf6912e8d9d4f..b7ce0936ddd4e7588a1b5f74260d4097c6b49f0c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
@@ -1,18 +1,28 @@
component altjesd_ss_RX_corepll is
port (
- locked : out std_logic; -- export
- outclk_0 : out std_logic; -- clk
- outclk_1 : out std_logic; -- clk
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X' -- reset
+ -- export
+ locked : out std_logic;
+ -- clk
+ outclk_0 : out std_logic;
+ -- clk
+ outclk_1 : out std_logic;
+ -- clk
+ refclk : in std_logic := 'X';
+ -- reset
+ rst : in std_logic := 'X'
);
end component altjesd_ss_RX_corepll;
u0 : component altjesd_ss_RX_corepll
port map (
- locked => CONNECTED_TO_locked, -- locked.export
- outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk
- outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
- refclk => CONNECTED_TO_refclk, -- refclk.clk
- rst => CONNECTED_TO_rst -- reset.reset
+ -- locked.export
+ locked => CONNECTED_TO_locked,
+ -- outclk0.clk
+ outclk_0 => CONNECTED_TO_outclk_0,
+ -- outclk1.clk
+ outclk_1 => CONNECTED_TO_outclk_1,
+ -- refclk.clk
+ refclk => CONNECTED_TO_refclk,
+ -- reset.reset
+ rst => CONNECTED_TO_rst
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
index 4d125d7d6b09eb801f54521d54896e4cd0d3f452..9fda67c683ff13c98207b6d9e9980eef2f59c440 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
@@ -1,14 +1,20 @@
component altjesd_ss_RX_frame_reset is
port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
+ -- clk
+ clk : in std_logic := 'X';
+ -- reset_n
+ in_reset_n : in std_logic := 'X';
+ -- reset_n
+ out_reset_n : out std_logic
);
end component altjesd_ss_RX_frame_reset;
u0 : component altjesd_ss_RX_frame_reset
port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ -- clk.clk
+ clk => CONNECTED_TO_clk,
+ -- in_reset.reset_n
+ in_reset_n => CONNECTED_TO_in_reset_n,
+ -- out_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
index 2fdfadb51af42decdc595af06f6653c82f64f67b..336f3eca87c925d56495622485633f8c04fd47c0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
@@ -1,14 +1,20 @@
component altjesd_ss_RX_link_reset is
port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
+ -- clk
+ clk : in std_logic := 'X';
+ -- reset_n
+ in_reset_n : in std_logic := 'X';
+ -- reset_n
+ out_reset_n : out std_logic
);
end component altjesd_ss_RX_link_reset;
u0 : component altjesd_ss_RX_link_reset
port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ -- clk.clk
+ clk => CONNECTED_TO_clk,
+ -- in_reset.reset_n
+ in_reset_n => CONNECTED_TO_in_reset_n,
+ -- out_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
index f5e2ba1f77a9a3ef8e6ec47a9929ad820950c0a3..d82290055d9312efd9c4a8a5c301a6ff7b7ca81e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
@@ -57,26 +57,46 @@
DSRT_QUALCNT_9 : integer := 0
);
port (
- av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_read : in std_logic := 'X'; -- read
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_write : in std_logic := 'X'; -- write
- irq : out std_logic; -- irq
- clk : in std_logic := 'X'; -- clk
- csr_reset : in std_logic := 'X'; -- reset
- reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
- reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
- reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
- reset_in0 : in std_logic := 'X'; -- reset
- reset_out0 : out std_logic; -- reset
- reset_out1 : out std_logic; -- reset
- reset_out2 : out std_logic; -- reset
- reset_out3 : out std_logic; -- reset
- reset_out4 : out std_logic; -- reset
- reset_out5 : out std_logic; -- reset
- reset_out6 : out std_logic; -- reset
- reset_out7 : out std_logic -- reset
+ -- address
+ av_address : in std_logic_vector(7 downto 0) := (others => 'X');
+ -- readdata
+ av_readdata : out std_logic_vector(31 downto 0);
+ -- read
+ av_read : in std_logic := 'X';
+ -- writedata
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- write
+ av_write : in std_logic := 'X';
+ -- irq
+ irq : out std_logic;
+ -- clk
+ clk : in std_logic := 'X';
+ -- reset
+ csr_reset : in std_logic := 'X';
+ -- reset1_dsrt_qual
+ reset1_dsrt_qual : in std_logic := 'X';
+ -- reset2_dsrt_qual
+ reset2_dsrt_qual : in std_logic := 'X';
+ -- reset5_dsrt_qual
+ reset5_dsrt_qual : in std_logic := 'X';
+ -- reset
+ reset_in0 : in std_logic := 'X';
+ -- reset
+ reset_out0 : out std_logic;
+ -- reset
+ reset_out1 : out std_logic;
+ -- reset
+ reset_out2 : out std_logic;
+ -- reset
+ reset_out3 : out std_logic;
+ -- reset
+ reset_out4 : out std_logic;
+ -- reset
+ reset_out5 : out std_logic;
+ -- reset
+ reset_out6 : out std_logic;
+ -- reset
+ reset_out7 : out std_logic
);
end component altjesd_ss_RX_reset_seq;
@@ -139,24 +159,44 @@
DSRT_QUALCNT_9 => INTEGER_VALUE_FOR_DSRT_QUALCNT_9
)
port map (
- av_address => CONNECTED_TO_av_address, -- av_csr.address
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_read => CONNECTED_TO_av_read, -- .read
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_write => CONNECTED_TO_av_write, -- .write
- irq => CONNECTED_TO_irq, -- av_csr_irq.irq
- clk => CONNECTED_TO_clk, -- clk.clk
- csr_reset => CONNECTED_TO_csr_reset, -- csr_reset.reset
- reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual, -- reset1_dsrt_qual.reset1_dsrt_qual
- reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual, -- reset2_dsrt_qual.reset2_dsrt_qual
- reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual, -- reset5_dsrt_qual.reset5_dsrt_qual
- reset_in0 => CONNECTED_TO_reset_in0, -- reset_in0.reset
- reset_out0 => CONNECTED_TO_reset_out0, -- reset_out0.reset
- reset_out1 => CONNECTED_TO_reset_out1, -- reset_out1.reset
- reset_out2 => CONNECTED_TO_reset_out2, -- reset_out2.reset
- reset_out3 => CONNECTED_TO_reset_out3, -- reset_out3.reset
- reset_out4 => CONNECTED_TO_reset_out4, -- reset_out4.reset
- reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
- reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
- reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
+ -- av_csr.address
+ av_address => CONNECTED_TO_av_address,
+ -- .readdata
+ av_readdata => CONNECTED_TO_av_readdata,
+ -- .read
+ av_read => CONNECTED_TO_av_read,
+ -- .writedata
+ av_writedata => CONNECTED_TO_av_writedata,
+ -- .write
+ av_write => CONNECTED_TO_av_write,
+ -- av_csr_irq.irq
+ irq => CONNECTED_TO_irq,
+ -- clk.clk
+ clk => CONNECTED_TO_clk,
+ -- csr_reset.reset
+ csr_reset => CONNECTED_TO_csr_reset,
+ -- reset1_dsrt_qual.reset1_dsrt_qual
+ reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual,
+ -- reset2_dsrt_qual.reset2_dsrt_qual
+ reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual,
+ -- reset5_dsrt_qual.reset5_dsrt_qual
+ reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual,
+ -- reset_in0.reset
+ reset_in0 => CONNECTED_TO_reset_in0,
+ -- reset_out0.reset
+ reset_out0 => CONNECTED_TO_reset_out0,
+ -- reset_out1.reset
+ reset_out1 => CONNECTED_TO_reset_out1,
+ -- reset_out2.reset
+ reset_out2 => CONNECTED_TO_reset_out2,
+ -- reset_out3.reset
+ reset_out3 => CONNECTED_TO_reset_out3,
+ -- reset_out4.reset
+ reset_out4 => CONNECTED_TO_reset_out4,
+ -- reset_out5.reset
+ reset_out5 => CONNECTED_TO_reset_out5,
+ -- reset_out6.reset
+ reset_out6 => CONNECTED_TO_reset_out6,
+ -- reset_out7.reset
+ reset_out7 => CONNECTED_TO_reset_out7
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
index e49f93a337e01a20a39b99a717881d143e0d0970..be9a3ab81e0cc487e0702a6540bcfb852224350a 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
@@ -1,24 +1,40 @@
component altjesd_ss_RX_xcvr_reset_control is
port (
- clock : in std_logic := 'X'; -- clk
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- reset : in std_logic := 'X'; -- reset
- rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_cal_busy
- rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_ready : out std_logic_vector(0 downto 0) -- rx_ready
+ -- clk
+ clock : in std_logic := 'X';
+ -- pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- reset
+ reset : in std_logic := 'X';
+ -- rx_analogreset
+ rx_analogreset : out std_logic_vector(0 downto 0);
+ -- rx_cal_busy
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_digitalreset
+ rx_digitalreset : out std_logic_vector(0 downto 0);
+ -- rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_ready
+ rx_ready : out std_logic_vector(0 downto 0)
);
end component altjesd_ss_RX_xcvr_reset_control;
u0 : component altjesd_ss_RX_xcvr_reset_control
port map (
- clock => CONNECTED_TO_clock, -- clock.clk
- pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
- reset => CONNECTED_TO_reset, -- reset.reset
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
+ -- clock.clk
+ clock => CONNECTED_TO_clock,
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown => CONNECTED_TO_pll_powerdown,
+ -- reset.reset
+ reset => CONNECTED_TO_reset,
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset => CONNECTED_TO_rx_analogreset,
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy,
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset,
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata,
+ -- rx_ready.rx_ready
+ rx_ready => CONNECTED_TO_rx_ready
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
index af64e251092b8abe7083a94e7070e5407b77a322..2165664a8324ad2243939f6ecb9790c64ad106c9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
@@ -1,16 +1,24 @@
component device_clk is
port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
+ -- clk
+ clk_out : out std_logic;
+ -- clk
+ in_clk : in std_logic := 'X';
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- reset_n
+ reset_n_out : out std_logic
);
end component device_clk;
u0 : component device_clk
port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ -- clk.clk
+ clk_out => CONNECTED_TO_clk_out,
+ -- clk_in.clk
+ in_clk => CONNECTED_TO_in_clk,
+ -- clk_in_reset.reset_n
+ reset_n => CONNECTED_TO_reset_n,
+ -- clk_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
index 26992b63a4edbecaa5e2a236b47a7c62d9e417d4..aba66e80db7e08b17ffde24c9240f7a88a2eb12b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
@@ -1,16 +1,24 @@
component frame_clk is
port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
+ -- clk
+ clk_out : out std_logic;
+ -- clk
+ in_clk : in std_logic := 'X';
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- reset_n
+ reset_n_out : out std_logic
);
end component frame_clk;
u0 : component frame_clk
port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ -- clk.clk
+ clk_out => CONNECTED_TO_clk_out,
+ -- clk_in.clk
+ in_clk => CONNECTED_TO_in_clk,
+ -- clk_in_reset.reset_n
+ reset_n => CONNECTED_TO_reset_n,
+ -- clk_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
index 745dc1937c6fff32fda95a03e5bd47b88e8206b7..494729cac4145ec82cd0ad822bb8486c0610d4f7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
@@ -1,100 +1,192 @@
component jesd is
port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
+ -- export
+ alldev_lane_aligned : in std_logic := 'X';
+ -- export
+ csr_cf : out std_logic_vector(4 downto 0);
+ -- export
+ csr_cs : out std_logic_vector(1 downto 0);
+ -- export
+ csr_f : out std_logic_vector(7 downto 0);
+ -- export
+ csr_hd : out std_logic;
+ -- export
+ csr_k : out std_logic_vector(4 downto 0);
+ -- export
+ csr_l : out std_logic_vector(4 downto 0);
+ -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0);
+ -- export
+ csr_m : out std_logic_vector(7 downto 0);
+ -- export
+ csr_n : out std_logic_vector(4 downto 0);
+ -- export
+ csr_np : out std_logic_vector(4 downto 0);
+ -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0);
+ -- export
+ csr_s : out std_logic_vector(4 downto 0);
+ -- export
+ dev_lane_aligned : out std_logic;
+ -- export
+ dev_sync_n : out std_logic;
+ -- chipselect
+ jesd204_rx_avs_chipselect : in std_logic := 'X';
+ -- address
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X');
+ -- read
+ jesd204_rx_avs_read : in std_logic := 'X';
+ -- readdata
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0);
+ -- waitrequest
+ jesd204_rx_avs_waitrequest : out std_logic;
+ -- write
+ jesd204_rx_avs_write : in std_logic := 'X';
+ -- writedata
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- clk
+ jesd204_rx_avs_clk : in std_logic := 'X';
+ -- reset_n
+ jesd204_rx_avs_rst_n : in std_logic := 'X';
+ -- export
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_frame_error : in std_logic := 'X';
+ -- irq
+ jesd204_rx_int : out std_logic;
+ -- data
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0);
+ -- valid
+ jesd204_rx_link_valid : out std_logic;
+ -- ready
+ jesd204_rx_link_ready : in std_logic := 'X';
+ -- clk
+ pll_ref_clk : in std_logic := 'X';
+ -- rx_analogreset
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_cal_busy
+ rx_cal_busy : out std_logic_vector(0 downto 0);
+ -- rx_digitalreset
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_is_lockedtodata
+ rx_islockedtodata : out std_logic_vector(0 downto 0);
+ -- rx_serial_data
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- clk
+ rxlink_clk : in std_logic := 'X';
+ -- reset_n
+ rxlink_rst_n_reset_n : in std_logic := 'X';
+ -- export
+ rxphy_clk : out std_logic_vector(0 downto 0);
+ -- export
+ sof : out std_logic_vector(3 downto 0);
+ -- export
+ somf : out std_logic_vector(3 downto 0);
+ -- export
+ sysref : in std_logic := 'X'
);
end component jesd;
u0 : component jesd
port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
+ -- alldev_lane_aligned.export
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned,
+ -- csr_cf.export
+ csr_cf => CONNECTED_TO_csr_cf,
+ -- csr_cs.export
+ csr_cs => CONNECTED_TO_csr_cs,
+ -- csr_f.export
+ csr_f => CONNECTED_TO_csr_f,
+ -- csr_hd.export
+ csr_hd => CONNECTED_TO_csr_hd,
+ -- csr_k.export
+ csr_k => CONNECTED_TO_csr_k,
+ -- csr_l.export
+ csr_l => CONNECTED_TO_csr_l,
+ -- csr_lane_powerdown.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown,
+ -- csr_m.export
+ csr_m => CONNECTED_TO_csr_m,
+ -- csr_n.export
+ csr_n => CONNECTED_TO_csr_n,
+ -- csr_np.export
+ csr_np => CONNECTED_TO_csr_np,
+ -- csr_rx_testmode.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode,
+ -- csr_s.export
+ csr_s => CONNECTED_TO_csr_s,
+ -- dev_lane_aligned.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned,
+ -- dev_sync_n.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n,
+ -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect,
+ -- .address
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address,
+ -- .read
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read,
+ -- .readdata
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata,
+ -- .waitrequest
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest,
+ -- .write
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write,
+ -- .writedata
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata,
+ -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk,
+ -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n,
+ -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data,
+ -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid,
+ -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr,
+ -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect,
+ -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data,
+ -- jesd204_rx_frame_error.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error,
+ -- jesd204_rx_int.irq
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int,
+ -- jesd204_rx_link.data
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data,
+ -- .valid
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid,
+ -- .ready
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready,
+ -- pll_ref_clk.clk
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk,
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset => CONNECTED_TO_rx_analogreset,
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy,
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset,
+ -- rx_islockedtodata.rx_is_lockedtodata
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata,
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data => CONNECTED_TO_rx_serial_data,
+ -- rxlink_clk.clk
+ rxlink_clk => CONNECTED_TO_rxlink_clk,
+ -- rxlink_rst_n.reset_n
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n,
+ -- rxphy_clk.export
+ rxphy_clk => CONNECTED_TO_rxphy_clk,
+ -- sof.export
+ sof => CONNECTED_TO_sof,
+ -- somf.export
+ somf => CONNECTED_TO_somf,
+ -- sysref.export
+ sysref => CONNECTED_TO_sysref
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
index acbc33a2d1959920765b1866572b908d153acbc2..f9a8f8fead903f01137de49be095efefb20186a4 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
@@ -1,16 +1,24 @@
component link_clk is
port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
+ -- clk
+ clk_out : out std_logic;
+ -- clk
+ in_clk : in std_logic := 'X';
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- reset_n
+ reset_n_out : out std_logic
);
end component link_clk;
u0 : component link_clk
port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ -- clk.clk
+ clk_out => CONNECTED_TO_clk_out,
+ -- clk_in.clk
+ in_clk => CONNECTED_TO_in_clk,
+ -- clk_in_reset.reset_n
+ reset_n => CONNECTED_TO_reset_n,
+ -- clk_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
index 42aae3ddf073f5dfbfee338c2139ed38675a6a2a..6e69a1fd8b1889422a42619413dda427f7f601ee 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_avs_common_mm_0;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
index 4ddaf7fa7d6f6d85a966525b9dd908dbdae955a3..441d19627c7c74f9c643381a4382b89a19adb50d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_avs_common_mm_1;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
index d648f26fb1cb1a3e9c804714afad5c500ffa4798..048d776d65de66af1f7b85555885b9324efb707b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
@@ -45,25 +45,30 @@ entity avs2_eth_coe is
mms_tse_write : in std_logic;
mms_tse_read : in std_logic;
mms_tse_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_tse_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 0
- mms_tse_waitrequest : out std_logic; -- necessary because read latency is 0
+ -- read latency is 0
+ mms_tse_readdata : out std_logic_vector(c_word_w - 1 downto 0);
+ -- necessary because read latency is 0
+ mms_tse_waitrequest : out std_logic;
-- ETH registers
mms_reg_address : in std_logic_vector(c_eth_reg_addr_w - 1 downto 0);
mms_reg_write : in std_logic;
mms_reg_read : in std_logic;
mms_reg_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_reg_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 1
+ -- read latency is 1
+ mms_reg_readdata : out std_logic_vector(c_word_w - 1 downto 0);
-- ETH packet RAM
mms_ram_address : in std_logic_vector(c_eth_ram_addr_w - 1 downto 0);
mms_ram_write : in std_logic;
mms_ram_read : in std_logic;
mms_ram_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_ram_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 2
+ -- read latency is 2
+ mms_ram_readdata : out std_logic_vector(c_word_w - 1 downto 0);
-- Interrupt Sender interface
- ins_interrupt_irq : out std_logic; -- relates to the ETH registers port
+ -- relates to the ETH registers port
+ ins_interrupt_irq : out std_logic;
----------------------------------------------------------------------------
-- User side
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
index e879f1b9edecdcf0c9866d6359c01c0b6a645338..11d1cb80798696dd2c17cc8cf7ab10c9285e3daf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
@@ -57,27 +57,38 @@ package common_network_layers_pkg is
constant c_network_eth_mac_addr_w : natural := c_network_eth_mac_addr_len * c_8;
constant c_network_eth_type_len : natural := 2;
constant c_network_eth_type_w : natural := c_network_eth_type_len * c_8;
- constant c_network_eth_header_len : natural := 2 * c_network_eth_mac_addr_len + c_network_eth_type_len; -- = 14
+ -- = 14
+ constant c_network_eth_header_len : natural := 2 * c_network_eth_mac_addr_len + c_network_eth_type_len;
constant c_network_eth_payload_min : natural := 46;
constant c_network_eth_payload_max : natural := 1500;
constant c_network_eth_payload_jumbo_max : natural := 9000;
constant c_network_eth_crc_len : natural := 4;
constant c_network_eth_crc_w : natural := c_network_eth_crc_len * c_8;
- constant c_network_eth_gap_len : natural := 12; -- IPG = interpacket gap, minimum idle period between transmission of Ethernet packets
- constant c_network_eth_frame_max : natural := c_network_eth_header_len + c_network_eth_payload_max + c_network_eth_crc_len; -- = 1518
- constant c_network_eth_frame_jumbo_max : natural := c_network_eth_header_len + c_network_eth_payload_jumbo_max + c_network_eth_crc_len; -- = 9018
+ -- IPG = interpacket gap, minimum idle period between transmission of Ethernet packets
+ constant c_network_eth_gap_len : natural := 12;
+ -- = 1518
+ constant c_network_eth_frame_max : natural := c_network_eth_header_len + c_network_eth_payload_max + c_network_eth_crc_len;
+ -- = 9018
+ constant c_network_eth_frame_jumbo_max : natural := c_network_eth_header_len + c_network_eth_payload_jumbo_max + c_network_eth_crc_len;
-- default field values
- constant c_network_eth_preamble : natural := 5; -- nibble "0101"
- constant c_network_eth_frame_delimiter : natural := 13; -- nibble "1101"
+ -- nibble "0101"
+ constant c_network_eth_preamble : natural := 5;
+ -- nibble "1101"
+ constant c_network_eth_frame_delimiter : natural := 13;
-- useful field values
- constant c_network_eth_mac_slv : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := (others => 'X'); -- Ethernet MAC slv RANGE
- constant c_network_eth_bc_mac : std_logic_vector(c_network_eth_mac_slv'range) := (others => '1'); -- Broadcast destination MAC
-
- constant c_network_eth_type_slv : std_logic_vector(c_network_eth_type_w - 1 downto 0) := (others => 'X'); -- Ethernet TYPE slv RANGE
- constant c_network_eth_type_arp : natural := 16#0806#; -- ARP = Address Resolution Prorotol
- constant c_network_eth_type_ip : natural := 16#0800#; -- IPv4 = Internet Protocol, Version 4
+ -- Ethernet MAC slv RANGE
+ constant c_network_eth_mac_slv : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := (others => 'X');
+ -- Broadcast destination MAC
+ constant c_network_eth_bc_mac : std_logic_vector(c_network_eth_mac_slv'range) := (others => '1');
+
+ -- Ethernet TYPE slv RANGE
+ constant c_network_eth_type_slv : std_logic_vector(c_network_eth_type_w - 1 downto 0) := (others => 'X');
+ -- ARP = Address Resolution Prorotol
+ constant c_network_eth_type_arp : natural := 16#0806#;
+ -- IPv4 = Internet Protocol, Version 4
+ constant c_network_eth_type_ip : natural := 16#0800#;
type t_network_eth_header is record
dst_mac : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
@@ -111,8 +122,10 @@ package common_network_layers_pkg is
--
-- field widths in bits '_w' or in bytes '_len'
- constant c_network_ip_version_w : natural := 4; -- 4-bit field
- constant c_network_ip_header_length_w : natural := 4; -- 4-bit field
+ -- 4-bit field
+ constant c_network_ip_version_w : natural := 4;
+ -- 4-bit field
+ constant c_network_ip_header_length_w : natural := 4;
constant c_network_ip_version_header_len : natural := 1;
constant c_network_ip_version_header_w : natural := c_network_ip_version_header_len * c_8;
constant c_network_ip_services_len : natural := 1;
@@ -121,8 +134,10 @@ package common_network_layers_pkg is
constant c_network_ip_total_length_w : natural := c_network_ip_total_length_len * c_8;
constant c_network_ip_identification_len : natural := 2;
constant c_network_ip_identification_w : natural := c_network_ip_identification_len * c_8;
- constant c_network_ip_flags_w : natural := 3; -- 3-bit field
- constant c_network_ip_fragment_offset_w : natural := 13; -- 13-bit field
+ -- 3-bit field
+ constant c_network_ip_flags_w : natural := 3;
+ -- 13-bit field
+ constant c_network_ip_fragment_offset_w : natural := 13;
constant c_network_ip_flags_fragment_len : natural := 2;
constant c_network_ip_flags_fragment_w : natural := c_network_ip_flags_fragment_len * c_8;
constant c_network_ip_time_to_live_len : natural := 1;
@@ -142,36 +157,61 @@ package common_network_layers_pkg is
c_network_ip_addr_len;
-- = c_network_ip_header_length * c_word_sz = 20
-- default field values
- constant c_network_ip_version : natural := 4; -- 4 = IPv4,
- constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
- constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
- constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
- constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
- constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
- constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
- constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
- constant c_network_ip_header_checksum : natural := 0; -- init value
+ -- 4 = IPv4,
+ constant c_network_ip_version : natural := 4;
+ -- 5 = nof words in the header, no options field support
+ constant c_network_ip_header_length : natural := 5;
+ -- 0 = default, use default on transmit, ignore on receive, copy on reply
+ constant c_network_ip_services : natural := 0;
+ -- >= 20, nof bytes in entire datagram including header and data
+ constant c_network_ip_total_length : natural := 20;
+ -- identification number, copy on reply
+ constant c_network_ip_identification : natural := 0;
+ -- 2 = don't fragment and this is the last fragment
+ constant c_network_ip_flags : natural := 2;
+ -- 0 = first fragment
+ constant c_network_ip_fragment_offset : natural := 0;
+ -- number of hops until the packet will be discarded
+ constant c_network_ip_time_to_live : natural := 127;
+ -- init value
+ constant c_network_ip_header_checksum : natural := 0;
-- useful field values
- constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
- constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
- constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
+ -- IP protocol slv RANGE
+ constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X');
+ -- UDP = User Datagram Protocol (for board control and streaming data)
+ constant c_network_ip_protocol_udp : natural := 17;
+ -- ICMP = Internet Control Message Protocol (for ping)
+ constant c_network_ip_protocol_icmp : natural := 1;
- constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
+ -- IP address slv RANGE
+ constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X');
type t_network_ip_header is record
- version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
- header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
- services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
- total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
- identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
- flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
- fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
- time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
- protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
- header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
- src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ -- 4 bit
+ version : std_logic_vector(c_network_ip_version_w - 1 downto 0);
+ -- 4 bit
+ header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0);
+ -- 1 octet
+ services : std_logic_vector(c_network_ip_services_w - 1 downto 0);
+ -- 2 octet
+ total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0);
+ -- 2 octet
+ identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0);
+ -- 3 bit
+ flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0);
+ -- 13 bit
+ fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0);
+ -- 1 octet
+ time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0);
+ -- 1 octet
+ protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0);
+ -- 2 octet
+ header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0);
+ -- 4 octet
+ src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- 4 octet
+ dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
end record;
constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
@@ -223,27 +263,44 @@ package common_network_layers_pkg is
-- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
- constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
- constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
- constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
- constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
- constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
- constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
+ -- Hardware type, 1=ethernet
+ constant c_network_arp_htype : natural := 1;
+ -- Protocol type, do ARP for IPv4
+ constant c_network_arp_ptype : natural := c_network_eth_type_ip;
+ -- Hardware length = 6
+ constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len;
+ -- Protocol length = 4
+ constant c_network_arp_plen : natural := c_network_ip_addr_len;
+ -- Operator, 1=request
+ constant c_network_arp_oper_request : natural := 1;
+ -- Operator, 2=reply
+ constant c_network_arp_oper_reply : natural := 2;
-- useful field values
- constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
- constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
+ -- Broadcast destination MAC
+ constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac;
+ -- Broadcast target hardware address
+ constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac;
type t_network_arp_packet is record
- htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
- ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
- hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
- plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
- oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
- sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
- spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
- tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
- tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
+ -- 2 octet
+ htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0);
+ -- 2 octet
+ ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0);
+ -- 1 octet
+ hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0);
+ -- 1 octet
+ plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0);
+ -- 2 octet
+ oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0);
+ -- 6 octet, Sender Hardware Address
+ sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ -- 4 octet, Sender Protocol Address
+ spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- 6 octet, Target Hardware Address
+ tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ -- 4 octet, Target Protocol Address
+ tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
end record;
constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
@@ -283,21 +340,32 @@ package common_network_layers_pkg is
c_network_icmp_id_len + c_network_icmp_sequence_len;
-- default field values
- constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
- constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
- constant c_network_icmp_checksum : natural := 0; -- init value
+ -- 8 = echo request
+ constant c_network_icmp_msg_type_request : natural := 8;
+ -- 8 = echo reply (ping)
+ constant c_network_icmp_msg_type_reply : natural := 0;
+ -- init value
+ constant c_network_icmp_checksum : natural := 0;
-- useful field values
- constant c_network_icmp_code : natural := 0; -- default
- constant c_network_icmp_id : natural := 3; -- arbitrary value
- constant c_network_icmp_sequence : natural := 4; -- arbitrary value
+ -- default
+ constant c_network_icmp_code : natural := 0;
+ -- arbitrary value
+ constant c_network_icmp_id : natural := 3;
+ -- arbitrary value
+ constant c_network_icmp_sequence : natural := 4;
type t_network_icmp_header is record
- msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
- code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
- checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
- id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
- sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
+ -- 1 octet
+ msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0);
+ -- 1 octet
+ code : std_logic_vector(c_network_icmp_code_w - 1 downto 0);
+ -- 2 octet
+ checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0);
+ -- 2 octet
+ id : std_logic_vector(c_network_icmp_id_w - 1 downto 0);
+ -- 2 octet
+ sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0);
end record;
constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
@@ -328,23 +396,33 @@ package common_network_layers_pkg is
-- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+ -- 8
+ c_network_udp_total_length_len + c_network_udp_checksum_len;
-- default field values
- constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
- constant c_network_udp_checksum : natural := 0; -- init value
+ -- >= 8, nof bytes in entire datagram including header and data
+ constant c_network_udp_total_length : natural := 8;
+ -- init value
+ constant c_network_udp_checksum : natural := 0;
-- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
- constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
- constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
- constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
+ -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
+ constant c_network_udp_port_dhcp_in : natural := 68;
+ -- DHCP to server
+ constant c_network_udp_port_dhcp_out : natural := 67;
+ -- UDP port slv RANGE
+ constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X');
type t_network_udp_header is record
- src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
- checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
+ -- 2 octet
+ src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- 2 octet
+ dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- 2 octet
+ total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0);
+ -- 2 octet
+ checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0);
end record;
constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index 4bd7e15cc8fdafe0a37772e3eaedca527d52c4bf..33e9a782ae790b7c4c71516d23a87c8acd5a53bf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -61,8 +61,10 @@ package common_pkg is
constant c_octet_w : natural := 8;
constant c_halfword_w : natural := c_byte_w * c_halfword_sz;
constant c_word_w : natural := c_byte_w * c_word_sz;
- constant c_integer_w : natural := 32; -- unfortunately VHDL integer type is limited to 32 bit values
- constant c_natural_w : natural := c_integer_w - 1; -- unfortunately VHDL natural type is limited to 31 bit values (0 and the positive subset of the VHDL integer type0
+ -- unfortunately VHDL integer type is limited to 32 bit values
+ constant c_integer_w : natural := 32;
+ -- unfortunately VHDL natural type is limited to 31 bit values (0 and the positive subset of the VHDL integer type0
+ constant c_natural_w : natural := c_integer_w - 1;
constant c_longword_w : natural := c_byte_w * c_longword_sz;
-- logic
@@ -80,30 +82,46 @@ package common_pkg is
constant c_slv10 : std_logic_vector(255 downto 0) := c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10;
-- math
- constant c_nof_complex : natural := 2; -- Real and imaginary part of complex number
- constant c_sign_w : natural := 1; -- Sign bit, can be used to skip one of the double sign bits of a product
- constant c_sum_of_prod_w : natural := 1; -- Bit growth for sum of 2 products, can be used in case complex multiply has normalized real and imag inputs instead of normalized amplitude inputs
+ -- Real and imaginary part of complex number
+ constant c_nof_complex : natural := 2;
+ -- Sign bit, can be used to skip one of the double sign bits of a product
+ constant c_sign_w : natural := 1;
+ -- Bit growth for sum of 2 products, can be used in case complex multiply has normalized real and imag inputs instead of normalized amplitude inputs
+ constant c_sum_of_prod_w : natural := 1;
-- FF, block RAM, FIFO
- constant c_meta_delay_len : natural := 3; -- default nof flipflops (FF) in meta stability recovery delay line (e.g. for clock domain crossing)
- constant c_meta_fifo_depth : natural := 16; -- default use 16 word deep FIFO to cross clock domain, typically > 2*c_meta_delay_len or >~ 8 is enough
+ -- default nof flipflops (FF) in meta stability recovery delay line (e.g. for clock domain crossing)
+ constant c_meta_delay_len : natural := 3;
+ -- default use 16 word deep FIFO to cross clock domain, typically > 2*c_meta_delay_len or >~ 8 is enough
+ constant c_meta_fifo_depth : natural := 16;
- constant c_bram_m9k_nof_bits : natural := 1024 * 9; -- size of 1 Altera M9K block RAM in bits
- constant c_bram_m9k_max_w : natural := 36; -- maximum width of 1 Altera M9K block RAM, so the size is then 256 words of 36 bits
- constant c_bram_m9k_fifo_depth : natural := c_bram_m9k_nof_bits / c_bram_m9k_max_w; -- using a smaller FIFO depth than this leaves part of the RAM unused
+ -- size of 1 Altera M9K block RAM in bits
+ constant c_bram_m9k_nof_bits : natural := 1024 * 9;
+ -- maximum width of 1 Altera M9K block RAM, so the size is then 256 words of 36 bits
+ constant c_bram_m9k_max_w : natural := 36;
+ -- using a smaller FIFO depth than this leaves part of the RAM unused
+ constant c_bram_m9k_fifo_depth : natural := c_bram_m9k_nof_bits / c_bram_m9k_max_w;
- constant c_fifo_afull_margin : natural := 4; -- default or minimal FIFO almost full margin
+ -- default or minimal FIFO almost full margin
+ constant c_fifo_afull_margin : natural := 4;
-- DSP
- constant c_dsp_mult_w : natural := 18; -- Width of the embedded multipliers in Stratix IV
+ -- Width of the embedded multipliers in Stratix IV
+ constant c_dsp_mult_w : natural := 18;
-- TYPE DECLARATIONS --------------------------------------------------------
- type t_boolean_arr is array (integer range <>) of boolean; -- INTEGER left index starts default at -2**31
- type t_integer_arr is array (integer range <>) of integer; -- INTEGER left index starts default at -2**31
- type t_natural_arr is array (integer range <>) of natural; -- INTEGER left index starts default at -2**31
- type t_nat_boolean_arr is array (natural range <>) of boolean; -- NATURAL left index starts default at 0
- type t_nat_integer_arr is array (natural range <>) of integer; -- NATURAL left index starts default at 0
- type t_nat_natural_arr is array (natural range <>) of natural; -- NATURAL left index starts default at 0
+ -- INTEGER left index starts default at -2**31
+ type t_boolean_arr is array (integer range <>) of boolean;
+ -- INTEGER left index starts default at -2**31
+ type t_integer_arr is array (integer range <>) of integer;
+ -- INTEGER left index starts default at -2**31
+ type t_natural_arr is array (integer range <>) of natural;
+ -- NATURAL left index starts default at 0
+ type t_nat_boolean_arr is array (natural range <>) of boolean;
+ -- NATURAL left index starts default at 0
+ type t_nat_integer_arr is array (natural range <>) of integer;
+ -- NATURAL left index starts default at 0
+ type t_nat_natural_arr is array (natural range <>) of natural;
type t_sl_arr is array (integer range <>) of std_logic;
type t_slv_1_arr is array (integer range <>) of std_logic_vector(0 downto 0);
type t_slv_2_arr is array (integer range <>) of std_logic_vector(1 downto 0);
@@ -122,8 +140,10 @@ package common_pkg is
type t_slv_512_arr is array (integer range <>) of std_logic_vector(511 downto 0);
type t_slv_1024_arr is array (integer range <>) of std_logic_vector(1023 downto 0);
- constant c_boolean_arr : t_boolean_arr := (true, false); -- array all possible values that can be iterated over
- constant c_nat_boolean_arr : t_nat_boolean_arr := (true, false); -- array all possible values that can be iterated over
+ -- array all possible values that can be iterated over
+ constant c_boolean_arr : t_boolean_arr := (true, false);
+ -- array all possible values that can be iterated over
+ constant c_nat_boolean_arr : t_nat_boolean_arr := (true, false);
type t_integer_matrix is array (integer range <>, integer range <>) of integer;
type t_boolean_matrix is array (integer range <>, integer range <>) of boolean;
@@ -151,61 +171,87 @@ package common_pkg is
type t_sys_rce is record
rst : std_logic;
clk : std_logic;
- clken : std_logic; -- := '1';
+ -- := '1';
+ clken : std_logic;
end record;
type t_sys_ce is record
clk : std_logic;
- clken : std_logic; -- := '1';
+ -- := '1';
+ clken : std_logic;
end record;
-- FUNCTION DECLARATIONS ----------------------------------------------------
-- All functions assume [high downto low] input ranges
- function pow2(n : natural) return natural; -- = 2**n
- function ceil_pow2(n : integer) return natural; -- = 2**n, returns 1 for n<0
+ -- = 2**n
+ function pow2(n : natural) return natural;
+ -- = 2**n, returns 1 for n<0
+ function ceil_pow2(n : integer) return natural;
- function true_log2(n : natural) return natural; -- true_log2(n) = log2(n)
- function ceil_log2(n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ -- true_log2(n) = log2(n)
+ function true_log2(n : natural) return natural;
+ -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ function ceil_log2(n : natural) return natural;
function floor_log10(n : natural) return natural;
- function is_pow2(n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
- function true_log_pow2(n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
-
- function ratio( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
- function ratio2(n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
-
- function ceil_div( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
- function ceil_value( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
- function floor_value(n, d : natural) return natural; -- floor_value = (n/d) * d
+ -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
+ function is_pow2(n : natural) return boolean;
+ -- 2**true_log2(n), return power of 2 that is >= n
+ function true_log_pow2(n : natural) return natural;
+
+ -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
+ function ratio( n, d : natural) return natural;
+ -- return integer ratio of n/m or m/n, whichever is the largest
+ function ratio2(n, m : natural) return natural;
+
+ -- ceil_div = n/d + (n MOD d)/=0
+ function ceil_div( n, d : natural) return natural;
+ -- ceil_value = ceil_div(n, d) * d
+ function ceil_value( n, d : natural) return natural;
+ -- floor_value = (n/d) * d
+ function floor_value(n, d : natural) return natural;
function ceil_div( n : unsigned; d: natural) return unsigned;
function ceil_value( n : unsigned; d: natural) return unsigned;
function floor_value(n : unsigned; d: natural) return unsigned;
- function slv(n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
- function sl( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
+ -- standard logic to 1 element standard logic vector
+ function slv(n: in std_logic) return std_logic_vector;
+ -- 1 element standard logic vector to standard logic
+ function sl( n: in std_logic_vector) return std_logic;
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr;
function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr;
function to_integer_arr(n : t_natural_arr) return t_integer_arr;
function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr;
function to_slv_32_arr( n : t_integer_arr) return t_slv_32_arr;
function to_slv_32_arr( n : t_natural_arr) return t_slv_32_arr;
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
- function vector_and(slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
- function vector_or( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
- function vector_xor(slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
-
- function andv(slv : std_logic_vector) return std_logic; -- alias of vector_and
- function orv( slv : std_logic_vector) return std_logic; -- alias of vector_or
- function xorv(slv : std_logic_vector) return std_logic; -- alias of vector_xor
-
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
- function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
+ -- Core operation tree function for vector "AND", "OR", "XOR"
+ function vector_tree(slv : std_logic_vector; operation : string) return std_logic;
+ -- '1' when all slv bits are '1' else '0'
+ function vector_and(slv : std_logic_vector) return std_logic;
+ -- '0' when all slv bits are '0' else '1'
+ function vector_or( slv : std_logic_vector) return std_logic;
+ -- '1' when the slv has an odd number of '1' bits else '0'
+ function vector_xor(slv : std_logic_vector) return std_logic;
+ -- Returns slv when it contains one hot bit, else returns 0.
+ function vector_one_hot(slv : std_logic_vector) return std_logic_vector;
+
+ -- alias of vector_and
+ function andv(slv : std_logic_vector) return std_logic;
+ -- alias of vector_or
+ function orv( slv : std_logic_vector) return std_logic;
+ -- alias of vector_xor
+ function xorv(slv : std_logic_vector) return std_logic;
+
+ -- '1' when all matrix bits are '1' else '0'
+ function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic;
+ -- '0' when all matrix bits are '0' else '1'
+ function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic;
function smallest(n, m : integer) return integer;
function smallest(n, m, l : integer) return integer;
@@ -214,34 +260,51 @@ package common_pkg is
function largest(n, m : integer) return integer;
function largest(n : t_natural_arr) return natural;
- function func_sum( n : t_natural_arr) return natural; -- sum of all elements in array
+ -- sum of all elements in array
+ function func_sum( n : t_natural_arr) return natural;
function func_sum( n : t_nat_natural_arr) return natural;
- function func_product(n : t_natural_arr) return natural; -- product of all elements in array
+ -- product of all elements in array
+ function func_product(n : t_natural_arr) return natural;
function func_product(n : t_nat_natural_arr) return natural;
- function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
- function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
- function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
-
- function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
- function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
- function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
- function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
-
- function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
- function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
- function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
-
- function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
- function "/" (L : t_natural_arr; R : positive) return t_natural_arr; -- element wise division
- function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
+ -- element wise sum
+ function "+" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise sum
+ function "+" (L : t_natural_arr; R : integer) return t_natural_arr;
+ -- element wise sum
+ function "+" (L : integer; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise subtract
+ function "-" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise subtract, support negative result
+ function "-" (L, R: t_natural_arr) return t_integer_arr;
+ -- element wise subtract
+ function "-" (L : t_natural_arr; R : integer) return t_natural_arr;
+ -- element wise subtract
+ function "-" (L : integer; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise product
+ function "*" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise product
+ function "*" (L : t_natural_arr; R : natural) return t_natural_arr;
+ -- element wise product
+ function "*" (L : natural; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise division
+ function "/" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise division
+ function "/" (L : t_natural_arr; R : positive) return t_natural_arr;
+ -- element wise division
+ function "/" (L : natural; R : t_natural_arr) return t_natural_arr;
function is_true(a : std_logic) return boolean;
function is_true(a : std_logic) return natural;
function is_true(a : boolean) return std_logic;
function is_true(a : boolean) return natural;
- function is_true(a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
- function is_true(a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
+ -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true(a : integer) return boolean;
+ -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true(a : integer) return std_logic;
function sel_a_b(sel, a, b : boolean) return boolean;
function sel_a_b(sel, a, b : integer) return integer;
@@ -263,46 +326,79 @@ package common_pkg is
function sel_a_b(sel : boolean; a, b : severity_level) return severity_level;
-- sel_n() index sel = 0, 1, 2, ... will return a, b, c, ...
- function sel_n(sel : natural; a, b, c : boolean) return boolean; -- 3
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean; -- 4
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
-
- function sel_n(sel : natural; a, b, c : integer) return integer; -- 3
- function sel_n(sel : natural; a, b, c, d : integer) return integer; -- 4
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
-
- function sel_n(sel : natural; a, b : string) return string; -- 2
- function sel_n(sel : natural; a, b, c : string) return string; -- 3
- function sel_n(sel : natural; a, b, c, d : string) return string; -- 4
- function sel_n(sel : natural; a, b, c, d, e : string) return string; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
+ -- 3
+ function sel_n(sel : natural; a, b, c : boolean) return boolean;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : boolean) return boolean;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean;
+
+ -- 3
+ function sel_n(sel : natural; a, b, c : integer) return integer;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : integer) return integer;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : integer) return integer;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer;
+
+ -- 2
+ function sel_n(sel : natural; a, b : string) return string;
+ -- 3
+ function sel_n(sel : natural; a, b, c : string) return string;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : string) return string;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : string) return string;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : string) return string;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string;
+
+ -- useful to init a unconstrained array of size 1
+ function array_init(init : std_logic; nof : natural) return std_logic_vector;
+ -- useful to init a unconstrained array of size 1
+ function array_init(init, nof : natural) return t_natural_arr;
+ -- useful to init a unconstrained array of size 1
+ function array_init(init, nof : natural) return t_nat_natural_arr;
+ -- useful to init an array with incrementing numbers
+ function array_init(init, nof, incr : natural) return t_natural_arr;
function array_init(init, nof, incr : natural) return t_nat_natural_arr;
function array_init(init, nof, incr : integer) return t_slv_16_arr;
function array_init(init, nof, incr : integer) return t_slv_32_arr;
- function array_init(init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
- function array_init(init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
- function array_sinit(init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+ -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_init(init, nof, width : natural) return std_logic_vector;
+ -- useful to init an unconstrained std_logic_vector with incrementing content
+ function array_init(init, nof, width, incr : natural) return std_logic_vector;
+ -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_sinit(init : integer; nof, width : natural) return std_logic_vector;
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
+ -- initialize all elements in t_slv_64_matrix to value k
+ function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix;
-- Concatenate two or more STD_LOGIC_VECTORs into a single STD_LOGIC_VECTOR or extract one of them from a concatenated STD_LOGIC_VECTOR
function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
@@ -324,13 +420,15 @@ package common_pkg is
function func_slv_extract( use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
function func_slv_extract( use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function TO_UINT(vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ function TO_UINT(vec : std_logic_vector) return natural;
function TO_SINT(vec : std_logic_vector) return integer;
function TO_UVEC(dec, w : natural) return std_logic_vector;
function TO_SVEC(dec, w : integer) return std_logic_vector;
- function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
+ -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
+ function TO_SVEC_32(dec : integer) return std_logic_vector;
-- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
@@ -338,81 +436,132 @@ package common_pkg is
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
-- happens for RESIZE of UNSIGNED. Therefor this is what the RESIZE_NUM for SIGNED and the RESIZE_SVEC do
-- and better not use RESIZE for SIGNED anymore.
- function RESIZE_NUM( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
- function RESIZE_NUM( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
- function RESIZE_UINT(u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
- function RESIZE_SINT(s : integer; w : natural) return integer; -- extend sign bit or keep LS part
-
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
+ -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
+ function RESIZE_NUM( u : unsigned; w : natural) return unsigned;
+ -- extend sign bit or keep LS part
+ function RESIZE_NUM( s : signed; w : natural) return signed;
+ -- left extend with '0' into slv
+ function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector;
+ -- left extend with '0' or keep LS part
+ function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector;
+ -- extend sign bit or keep LS part
+ function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector;
+ -- left extend with '0' or keep LS part
+ function RESIZE_UINT(u : integer; w : natural) return integer;
+ -- extend sign bit or keep LS part
+ function RESIZE_SINT(s : integer; w : natural) return integer;
+
+ -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector;
+ -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector;
function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
-- Used in common_add_sub.vhd
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
-
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
-
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
-
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
+ -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
+ function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
+ function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
+ function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
+ function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+
+ -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+
+ -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
+ function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer;
+ -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
+ function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer;
+
+ -- < 0 shift left, > 0 shift right
+ function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector;
+ -- < 0 shift left, > 0 shift right
+ function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector;
function offset_binary(a : std_logic_vector) return std_logic_vector;
- function truncate( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function scale( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
- function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
- function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
- function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
-
- function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
- function s_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
- function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
- function u_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
-
- function u_to_s(u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
- function s_to_u(s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
-
- function u_wrap(u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
- function s_wrap(s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
-
- function u_clip(u : natural; max : natural) return natural; -- if s < max return s, else return n
- function s_clip(s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
- function s_clip(s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
-
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
- function hton(a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
- function ntoh(a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
-
- function flip(a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
- function flip(a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ -- remove n LSBits from vec, so result has width vec'LENGTH-n
+ function truncate( vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- remove n LSBits from vec and then resize to width w
+ function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- idem for signed values
+ function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- add n '0' LSBits to vec
+ function scale( vec : std_logic_vector; n: natural) return std_logic_vector;
+ -- add n '0' LSBits to vec and then resize to width w
+ function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- idem for signed values
+ function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- when b=TRUE then truncate to width w, else resize to width w
+ function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector;
+ -- idem for signed values
+ function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector;
+
+ -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
+ function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector;
+ -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
+ function s_round( vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- idem but round up to +infinity (s_round_up = u_round)
+ function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector;
+ -- idem but round up to +infinity (s_round_up = u_round)
+ function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- idem round up for unsigned values
+ function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector;
+ -- idem round up for unsigned values
+ function u_round( vec : std_logic_vector; n : natural) return std_logic_vector;
+
+ -- interpret w bit unsigned u as w bit signed, and remove any MSbits
+ function u_to_s(u : natural; w : natural) return integer;
+ -- interpret w bit signed s as w bit unsigned, and remove any MSbits
+ function s_to_u(s : integer; w : natural) return natural;
+
+ -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
+ function u_wrap(u : natural; w : natural) return natural;
+ -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
+ function s_wrap(s : integer; w : natural) return integer;
+
+ -- if s < max return s, else return n
+ function u_clip(u : natural; max : natural) return natural;
+ -- if s <= min return min, else if s >= max return max, else return s
+ function s_clip(s : integer; max : natural; min : integer) return integer;
+ -- if s <= -max return -max, else if s >= max return max, else return s
+ function s_clip(s : integer; max : natural ) return integer;
+
+ -- convert endianity from host to network, sz in symbols of width w
+ function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector;
+ -- convert endianity from host to network, sz in bytes
+ function hton(a : std_logic_vector; sz : natural) return std_logic_vector;
+ -- convert endianity from host to network, for all bytes in a
+ function hton(a : std_logic_vector ) return std_logic_vector;
+ -- convert endianity from network to host, sz in bytes, ntoh() = hton()
+ function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector;
+ -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
+ function ntoh(a : std_logic_vector ) return std_logic_vector;
+
+ -- bit flip a vector, map a[h:0] to [0:h]
+ function flip(a : std_logic_vector) return std_logic_vector;
+ -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ function flip(a, w : natural) return natural;
function flip(a : t_slv_32_arr) return t_slv_32_arr;
function flip(a : t_integer_arr) return t_integer_arr;
function flip(a : t_natural_arr) return t_natural_arr;
function flip(a : t_nat_natural_arr) return t_nat_natural_arr;
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
- function transpose(a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
+ -- transpose a vector, map a[i*row+j] to output index [j*col+i]
+ function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector;
+ -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose(a, row, col : natural) return natural;
function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
@@ -499,9 +648,11 @@ package body common_pkg is
-- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
- return 0; -- Get NULL array
+ -- Get NULL array
+ return 0;
elsif n = 1 then
- return 1; -- avoid NULL array
+ -- avoid NULL array
+ return 1;
else
return true_log2(n);
end if;
@@ -553,7 +704,8 @@ package body common_pkg is
function ceil_div(n : unsigned; d: natural) return unsigned is
begin
- return n / d + sel_a_b(n mod d = 0, 0, 1); -- "/" returns same width as n
+ -- "/" returns same width as n
+ return n / d + sel_a_b(n mod d = 0, 0, 1);
end;
function ceil_value(n : unsigned; d: natural) return unsigned is
@@ -561,7 +713,8 @@ package body common_pkg is
variable p : unsigned(2 * w - 1 downto 0);
begin
p := ceil_div(n, d) * d;
- return p(w - 1 downto 0); -- return same width as n
+ -- return same width as n
+ return p(w - 1 downto 0);
end;
function floor_value(n : unsigned; d: natural) return unsigned is
@@ -569,7 +722,8 @@ package body common_pkg is
variable p : unsigned(2 * w - 1 downto 0);
begin
p := (n / d) * d;
- return p(w - 1 downto 0); -- return same width as n
+ -- return same width as n
+ return p(w - 1 downto 0);
end;
function slv(n: in std_logic) return std_logic_vector is
@@ -664,7 +818,8 @@ package body common_pkg is
-- Instead use binary tree to determine result with smallest combinatorial delay that depends on log2(slv'LENGTH)
constant c_slv_w : natural := slv'length;
constant c_nof_stages : natural := ceil_log2(c_slv_w);
- constant c_w : natural := 2**c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ constant c_w : natural := 2**c_nof_stages;
type t_stage_arr is array (-1 to c_nof_stages - 1) of std_logic_vector(c_w - 1 downto 0);
variable v_stage_arr : t_stage_arr;
variable v_result : std_logic := '0';
@@ -676,7 +831,8 @@ package body common_pkg is
else
assert true report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
end if;
- v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
+ -- any unused input c_w : c_slv_w bits have void default value
+ v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv;
for J in 0 to c_nof_stages - 1 loop
for I in 0 to c_w / (2**(J + 1)) - 1 loop
if operation = "AND" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
@@ -738,7 +894,8 @@ package body common_pkg is
end;
function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic is
- variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
+ -- map to fixed range
+ variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat;
variable v_result : std_logic := '1';
begin
for I in 0 to wi - 1 loop
@@ -750,7 +907,8 @@ package body common_pkg is
end;
function matrix_or(mat : t_sl_matrix; wi, wj : natural) return std_logic is
- variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
+ -- map to fixed range
+ variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat;
variable v_result : std_logic := '0';
begin
for I in 0 to wi - 1 loop
@@ -1513,7 +1671,8 @@ package body common_pkg is
if use_f = true then v_lo := v_lo + f_w; end if;
when others => report "Unknown common_pkg func_slv_extract argument" severity FAILURE;
end case;
- return vec(v_w - 1 + v_lo downto v_lo); -- extracted slv
+ -- extracted slv
+ return vec(v_w - 1 + v_lo downto v_lo);
end func_slv_extract;
function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
@@ -1576,9 +1735,11 @@ package body common_pkg is
begin
-- extend sign bit or keep LS part
if w > s'length then
- return resize(s, w); -- extend sign bit
+ -- extend sign bit
+ return resize(s, w);
else
- return signed(resize(unsigned(s), w)); -- keep LSbits (= vec[w-1:0])
+ -- keep LSbits (= vec[w-1:0])
+ return signed(resize(unsigned(s), w));
end if;
end;
@@ -1627,10 +1788,12 @@ package body common_pkg is
begin
if dec < 0 then
v_dec := -dec;
- return std_logic_vector(unsigned(vec) - v_dec); -- uses function "-" (L : UNSIGNED, R : NATURAL), there is no function + with R : INTEGER argument
+ -- uses function "-" (L : UNSIGNED, R : NATURAL), there is no function + with R : INTEGER argument
+ return std_logic_vector(unsigned(vec) - v_dec);
else
v_dec := dec;
- return std_logic_vector(unsigned(vec) + v_dec); -- uses function "+" (L : UNSIGNED, R : NATURAL)
+ -- uses function "+" (L : UNSIGNED, R : NATURAL)
+ return std_logic_vector(unsigned(vec) + v_dec);
end if;
end;
@@ -1642,7 +1805,8 @@ package body common_pkg is
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
variable v_dec : integer;
begin
- return std_logic_vector(signed(vec) + v_dec); -- uses function "+" (L : SIGNED, R : INTEGER)
+ -- uses function "+" (L : SIGNED, R : INTEGER)
+ return std_logic_vector(signed(vec) + v_dec);
end;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector is
@@ -1703,18 +1867,22 @@ package body common_pkg is
function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
- return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift)); -- fill zeros from right
+ -- fill zeros from right
+ return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift));
else
- return std_logic_vector(SHIFT_RIGHT(unsigned(vec), shift)); -- fill zeros from left
+ -- fill zeros from left
+ return std_logic_vector(SHIFT_RIGHT(unsigned(vec), shift));
end if;
end;
function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
- return std_logic_vector(SHIFT_LEFT(signed(vec), -shift)); -- same as SHIFT_LEFT for UNSIGNED
+ -- same as SHIFT_LEFT for UNSIGNED
+ return std_logic_vector(SHIFT_LEFT(signed(vec), -shift));
else
- return std_logic_vector(SHIFT_RIGHT(signed(vec), shift)); -- extend sign
+ -- extend sign
+ return std_logic_vector(SHIFT_RIGHT(signed(vec), shift));
end if;
end;
@@ -1738,7 +1906,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ v_res(v_res'high) := not v_res(v_res'high);
return v_res;
end;
@@ -1748,7 +1917,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ -- keep MS part
+ v_res := v_vec(c_vec_w - 1 downto n);
return v_res;
end;
@@ -1758,8 +1928,10 @@ package body common_pkg is
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_trunc := truncate(vec, n); -- first keep MS part
- v_res := RESIZE_UVEC(v_trunc, w); -- then keep LS part or left extend with '0'
+ -- first keep MS part
+ v_trunc := truncate(vec, n);
+ -- then keep LS part or left extend with '0'
+ v_res := RESIZE_UVEC(v_trunc, w);
return v_res;
end;
@@ -1769,8 +1941,10 @@ package body common_pkg is
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_trunc := truncate(vec, n); -- first keep MS part
- v_res := RESIZE_SVEC(v_trunc, w); -- then keep sign bit and LS part or left extend sign bit
+ -- first keep MS part
+ v_trunc := truncate(vec, n);
+ -- then keep sign bit and LS part or left extend sign bit
+ v_res := RESIZE_SVEC(v_trunc, w);
return v_res;
end;
@@ -1779,7 +1953,8 @@ package body common_pkg is
constant c_scale_w : natural := c_vec_w + n;
variable v_res : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
begin
- v_res(c_scale_w - 1 downto n) := vec; -- scale by adding n zero bits at the right
+ -- scale by adding n zero bits at the right
+ v_res(c_scale_w - 1 downto n) := vec;
return v_res;
end;
@@ -1789,8 +1964,10 @@ package body common_pkg is
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_scale(c_scale_w - 1 downto n) := vec; -- first scale by adding n zero bits at the right
- v_res := RESIZE_UVEC(v_scale, w); -- then keep LS part or left extend with '0'
+ -- first scale by adding n zero bits at the right
+ v_scale(c_scale_w - 1 downto n) := vec;
+ -- then keep LS part or left extend with '0'
+ v_res := RESIZE_UVEC(v_scale, w);
return v_res;
end;
@@ -1800,8 +1977,10 @@ package body common_pkg is
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_scale(c_scale_w - 1 downto n) := vec; -- first scale by adding n zero bits at the right
- v_res := RESIZE_SVEC(v_scale, w); -- then keep LS part or left extend sign bit
+ -- first scale by adding n zero bits at the right
+ v_scale(c_scale_w - 1 downto n) := vec;
+ -- then keep LS part or left extend sign bit
+ v_res := RESIZE_SVEC(v_scale, w);
return v_res;
end;
@@ -1854,32 +2033,40 @@ package body common_pkg is
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
constant c_one : signed(c_in_w - 1 downto 0) := to_signed(1, c_in_w);
- constant c_half : signed(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1); -- = 2**(n-1)
- constant c_max : signed(c_in_w - 1 downto 0) := signed('0' & c_slv1(c_in_w - 2 downto 0)) - c_half; -- = 2**(c_in_w-1)-1 - c_half
- constant c_clip : signed(c_out_w - 1 downto 0) := signed('0' & c_slv1(c_out_w - 2 downto 0)); -- = 2**(c_out_w-1)-1
+ -- = 2**(n-1)
+ constant c_half : signed(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1);
+ -- = 2**(c_in_w-1)-1 - c_half
+ constant c_max : signed(c_in_w - 1 downto 0) := signed('0' & c_slv1(c_in_w - 2 downto 0)) - c_half;
+ -- = 2**(c_out_w-1)-1
+ constant c_clip : signed(c_out_w - 1 downto 0) := signed('0' & c_slv1(c_out_w - 2 downto 0));
variable v_in : signed(c_in_w - 1 downto 0);
variable v_out : signed(c_out_w - 1 downto 0);
begin
v_in := signed(vec);
if n > 0 then
if clip = true and v_in > c_max then
- v_out := c_clip; -- Round clip to maximum positive to avoid wrap to negative
+ -- Round clip to maximum positive to avoid wrap to negative
+ v_out := c_clip;
else
if vec(vec'high) = '0' then
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half + 0, n), c_out_w); -- Round up for positive
+ -- Round up for positive
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half + 0, n), c_out_w);
else
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half - 1, n), c_out_w); -- Round down for negative
+ -- Round down for negative
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half - 1, n), c_out_w);
end if;
end if;
else
- v_out := RESIZE_NUM(v_in, c_out_w); -- NOP
+ -- NOP
+ v_out := RESIZE_NUM(v_in, c_out_w);
end if;
return std_logic_vector(v_out);
end;
function s_round(vec : std_logic_vector; n : natural) return std_logic_vector is
begin
- return s_round(vec, n, false); -- no round clip
+ -- no round clip
+ return s_round(vec, n, false);
end;
-- An alternative is to always round up, also for negative numbers (i.e. s_round_up = u_round).
@@ -1890,7 +2077,8 @@ package body common_pkg is
function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector is
begin
- return u_round(vec, n, false); -- no round clip
+ -- no round clip
+ return u_round(vec, n, false);
end;
-- Unsigned numbers are round up (almost same as s_round, but without the else on negative vec)
@@ -1899,50 +2087,61 @@ package body common_pkg is
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
constant c_one : unsigned(c_in_w - 1 downto 0) := to_unsigned(1, c_in_w);
- constant c_half : unsigned(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1); -- = 2**(n-1)
- constant c_max : unsigned(c_in_w - 1 downto 0) := unsigned(c_slv1(c_in_w - 1 downto 0)) - c_half; -- = 2**c_in_w-1 - c_half
- constant c_clip : unsigned(c_out_w - 1 downto 0) := unsigned(c_slv1(c_out_w - 1 downto 0)); -- = 2**c_out_w-1
+ -- = 2**(n-1)
+ constant c_half : unsigned(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1);
+ -- = 2**c_in_w-1 - c_half
+ constant c_max : unsigned(c_in_w - 1 downto 0) := unsigned(c_slv1(c_in_w - 1 downto 0)) - c_half;
+ -- = 2**c_out_w-1
+ constant c_clip : unsigned(c_out_w - 1 downto 0) := unsigned(c_slv1(c_out_w - 1 downto 0));
variable v_in : unsigned(c_in_w - 1 downto 0);
variable v_out : unsigned(c_out_w - 1 downto 0);
begin
v_in := unsigned(vec);
if n > 0 then
if clip = true and v_in > c_max then
- v_out := c_clip; -- Round clip to +max to avoid wrap to 0
+ -- Round clip to +max to avoid wrap to 0
+ v_out := c_clip;
else
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half, n), c_out_w); -- Round up
+ -- Round up
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half, n), c_out_w);
end if;
else
- v_out := RESIZE_NUM(v_in, c_out_w); -- NOP
+ -- NOP
+ v_out := RESIZE_NUM(v_in, c_out_w);
end if;
return std_logic_vector(v_out);
end;
function u_round(vec : std_logic_vector; n : natural) return std_logic_vector is
begin
- return u_round(vec, n, false); -- no round clip
+ -- no round clip
+ return u_round(vec, n, false);
end;
function u_to_s(u : natural; w : natural) return integer is
- variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32);
begin
return TO_SINT(v_u(w - 1 downto 0));
end;
function s_to_u(s : integer; w : natural) return natural is
- variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32);
begin
return TO_UINT(v_s(w - 1 downto 0));
end;
function u_wrap(u : natural; w : natural) return natural is
- variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32);
begin
return TO_UINT(v_u(w - 1 downto 0));
end;
function s_wrap(s : integer; w : natural) return integer is
- variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32);
begin
return TO_SINT(v_s(w - 1 downto 0));
end;
@@ -1975,8 +2174,10 @@ package body common_pkg is
end;
function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector is
- variable v_a : std_logic_vector(a'length - 1 downto 0) := a; -- map a to range [h:0]
- variable v_b : std_logic_vector(a'length - 1 downto 0) := a; -- default b = a
+ -- map a to range [h:0]
+ variable v_a : std_logic_vector(a'length - 1 downto 0) := a;
+ -- default b = a
+ variable v_b : std_logic_vector(a'length - 1 downto 0) := a;
variable vL : natural;
variable vK : natural;
begin
@@ -1992,23 +2193,27 @@ package body common_pkg is
function hton(a : std_logic_vector; sz : natural) return std_logic_vector is
begin
- return hton(a, c_byte_w, sz); -- symbol width w = c_byte_w = 8
+ -- symbol width w = c_byte_w = 8
+ return hton(a, c_byte_w, sz);
end function;
function hton(a : std_logic_vector) return std_logic_vector is
constant c_sz : natural := a'length / c_byte_w;
begin
- return hton(a, c_byte_w, c_sz); -- symbol width w = c_byte_w = 8
+ -- symbol width w = c_byte_w = 8
+ return hton(a, c_byte_w, c_sz);
end function;
function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector is
begin
- return hton(a, sz); -- i.e. ntoh() = hton()
+ -- i.e. ntoh() = hton()
+ return hton(a, sz);
end function;
function ntoh(a : std_logic_vector) return std_logic_vector is
begin
- return hton(a); -- i.e. ntoh() = hton()
+ -- i.e. ntoh() = hton()
+ return hton(a);
end function;
function flip(a : std_logic_vector) return std_logic_vector is
@@ -2070,17 +2275,21 @@ package body common_pkg is
variable vIn : std_logic_vector(a'length - 1 downto 0);
variable vOut : std_logic_vector(a'length - 1 downto 0);
begin
- vIn := a; -- map input vector to h:0 range
- vOut := vIn; -- default leave any unused MSbits the same
+ -- map input vector to h:0 range
+ vIn := a;
+ -- default leave any unused MSbits the same
+ vOut := vIn;
for J in 0 to row - 1 loop
for I in 0 to col - 1 loop
- vOut(J * col + I) := vIn(I * row + J); -- transpose vector, map input index [i*row+j] to output index [j*col+i]
+ -- transpose vector, map input index [i*row+j] to output index [j*col+i]
+ vOut(J * col + I) := vIn(I * row + J);
end loop;
end loop;
return vOut;
end function;
- function transpose(a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
+ -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose(a, row, col : natural) return natural is
variable vI : natural;
variable vJ : natural;
begin
@@ -2089,16 +2298,20 @@ package body common_pkg is
return vJ * col + vI;
end;
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
+ -- Calculate input_w in multiples as close as possible to max_out_w
+ function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is
-- Examples: split_w(256, 8, 32) = 32; split_w(16, 8, 32) = 16; split_w(72, 8, 32) = 18; -- Input_w must be multiple of 2.
variable r: natural;
begin
r := input_w;
- for i in 1 to ceil_log2(input_w) loop -- Useless to divide the number beyond this
+ -- Useless to divide the number beyond this
+ for i in 1 to ceil_log2(input_w) loop
if r <= max_out_w and r >= min_out_w then
return r;
- elsif i = ceil_log2(input_w) then -- last iteration
- return 0; -- Indicates wrong values were used
+ -- last iteration
+ elsif i = ceil_log2(input_w) then
+ -- Indicates wrong values were used
+ return 0;
end if;
r := r / 2;
end loop;
@@ -2197,8 +2410,10 @@ package body common_pkg is
variable v_odd : boolean;
variable v_even : boolean;
begin
- v_odd := (I mod 2 = 1) and (J mod 2 = 1); -- for odd stage at each odd row
- v_even := (I mod 2 = 0) and (J mod 2 = 0); -- for even stage at each even row
+ -- for odd stage at each odd row
+ v_odd := (I mod 2 = 1) and (J mod 2 = 1);
+ -- for even stage at each even row
+ v_even := (I mod 2 = 0) and (J mod 2 = 0);
return v_odd or v_even;
end func_common_reorder2_is_there;
@@ -2228,7 +2443,8 @@ package body common_pkg is
-- for the active two port reorder cells use the setting at index v_K from the select setting array
v_nof_odd_stages := I / 2;
v_nof_even_stages := (I - 1) / 2;
- v_offset := (J - 1) / 2; -- suits both odd stage and even stage
+ -- suits both odd stage and even stage
+ v_offset := (J - 1) / 2;
v_K := v_nof_odd_stages * c_nof_reorder2_per_odd_stage + v_nof_even_stages * c_nof_reorder2_per_even_stage + v_offset;
end if;
return v_K;
@@ -2237,7 +2453,8 @@ package body common_pkg is
-- Get the select setting for the reorder2 cell on stage I and row J in a reorder network with N stages
function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural is
constant c_nof_select : natural := select_arr'length;
- constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
+ -- force range downto 0
+ constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr;
variable v_sel : natural;
variable v_K : integer;
begin
@@ -2252,11 +2469,13 @@ package body common_pkg is
-- Determine the inverse of a reorder network by using two reorder networks in series
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr is
constant c_nof_select : natural := select_arr'length;
- constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
+ -- force range downto 0
+ constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr;
variable v_sel : natural;
variable v_Ki : integer;
variable v_Ii : natural;
- variable v_inverse_arr : t_natural_arr(2 * c_nof_select - 1 downto 0) := (others => 0); -- default set identity for the reorder2 cells in both reorder instances
+ -- default set identity for the reorder2 cells in both reorder instances
+ variable v_inverse_arr : t_natural_arr(2 * c_nof_select - 1 downto 0) := (others => 0);
begin
-- the inverse select consists of inverse_in reorder and inverse_out reorder in series
if N mod 2 = 1 then
@@ -2276,7 +2495,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ -- stage 1 of the inverse_out reorder
+ v_Ki := c_nof_select + K;
v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index 7b6d1a2da0ec2558d87aa708358be0b79c70944d..dc48b2f8f8d20d5ee0c491104976d7126bb80f02 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -48,35 +48,59 @@ package dp_stream_pkg is
-- This grouping is useful for functions that operate on a t_dp_sosi signal.
-- * The info fields are valid at the sop or at the eop, but typically they hold their last active value to avoid unnessary
-- toggling and to ease viewing in the wave window.
- constant c_dp_stream_bsn_w : natural := 64; -- 64 is sufficient to count blocks of data for years
- constant c_dp_stream_data_w : natural := 768; -- 72 is sufficient for max word 8 * 9-bit. 576 supports half rate DDR4 bus data width. The current 768 is enough for wide single clock SLVs (e.g. headers)
- constant c_dp_stream_dsp_data_w : natural := 64; -- 64 is sufficient for DSP data, including complex power accumulates
- constant c_dp_stream_empty_w : natural := 16; -- 8 is sufficient for max 256 symbols per data word, still use 16 bit to be able to count c_dp_stream_data_w in bits
- constant c_dp_stream_channel_w : natural := 32; -- 32 is sufficient for several levels of hierarchy in mapping types of streams on to channels
- constant c_dp_stream_error_w : natural := 32; -- 32 is sufficient for several levels of hierarchy in mapping error numbers, e.g. 32 different one-hot encoded errors, bit [0] = 0 = OK
-
- constant c_dp_stream_ok : natural := 0; -- SOSI err field OK value
- constant c_dp_stream_err : natural := 1; -- SOSI err field error value /= OK
-
- constant c_dp_stream_rl : natural := 1; -- SISO default data path stream ready latency RL = 1
-
- type t_dp_siso is record -- Source In or Sink Out
- ready : std_logic; -- fine cycle based flow control using ready latency RL >= 0
- xon : std_logic; -- coarse typically block based flow control using xon/xoff
+ -- 64 is sufficient to count blocks of data for years
+ constant c_dp_stream_bsn_w : natural := 64;
+ -- 72 is sufficient for max word 8 * 9-bit. 576 supports half rate DDR4 bus data width. The current 768 is enough for wide single clock SLVs (e.g. headers)
+ constant c_dp_stream_data_w : natural := 768;
+ -- 64 is sufficient for DSP data, including complex power accumulates
+ constant c_dp_stream_dsp_data_w : natural := 64;
+ -- 8 is sufficient for max 256 symbols per data word, still use 16 bit to be able to count c_dp_stream_data_w in bits
+ constant c_dp_stream_empty_w : natural := 16;
+ -- 32 is sufficient for several levels of hierarchy in mapping types of streams on to channels
+ constant c_dp_stream_channel_w : natural := 32;
+ -- 32 is sufficient for several levels of hierarchy in mapping error numbers, e.g. 32 different one-hot encoded errors, bit [0] = 0 = OK
+ constant c_dp_stream_error_w : natural := 32;
+
+ -- SOSI err field OK value
+ constant c_dp_stream_ok : natural := 0;
+ -- SOSI err field error value /= OK
+ constant c_dp_stream_err : natural := 1;
+
+ -- SISO default data path stream ready latency RL = 1
+ constant c_dp_stream_rl : natural := 1;
+
+ -- Source In or Sink Out
+ type t_dp_siso is record
+ -- fine cycle based flow control using ready latency RL >= 0
+ ready : std_logic;
+ -- coarse typically block based flow control using xon/xoff
+ xon : std_logic;
end record;
- type t_dp_sosi is record -- Source Out or Sink In
- sync : std_logic; -- ctrl
- bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0); -- info at sop (block sequence number)
- data : std_logic_vector(c_dp_stream_data_w - 1 downto 0); -- data
- re : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0); -- data
- im : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0); -- data
- valid : std_logic; -- ctrl
- sop : std_logic; -- ctrl
- eop : std_logic; -- ctrl
- empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0); -- info at eop
- channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0); -- info at sop
- err : std_logic_vector(c_dp_stream_error_w - 1 downto 0); -- info at eop (name field 'err' to avoid the 'error' keyword)
+ -- Source Out or Sink In
+ type t_dp_sosi is record
+ -- ctrl
+ sync : std_logic;
+ -- info at sop (block sequence number)
+ bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ -- data
+ data : std_logic_vector(c_dp_stream_data_w - 1 downto 0);
+ -- data
+ re : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0);
+ -- data
+ im : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0);
+ -- ctrl
+ valid : std_logic;
+ -- ctrl
+ sop : std_logic;
+ -- ctrl
+ eop : std_logic;
+ -- info at eop
+ empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0);
+ -- info at sop
+ channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0);
+ -- info at eop (name field 'err' to avoid the 'error' keyword)
+ err : std_logic_vector(c_dp_stream_error_w - 1 downto 0);
end record;
-- Initialise signal declarations with c_dp_stream_rst/rdy to ease the interpretation of slv fields with unused bits
@@ -240,29 +264,43 @@ package dp_stream_pkg is
-- signed data in the simulation wave window it is easier to use sign extension in the record field. Therefore TO_DP_SDATA
-- and RESIZE_DP_SDATA are defined as well.
function TO_DP_BSN( n : natural) return std_logic_vector;
- function TO_DP_DATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
- function TO_DP_SDATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
- function TO_DP_UDATA( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector; -- for re and im fields, signed data
- function TO_DP_DSP_UDATA(n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
+ -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
+ function TO_DP_DATA( n : integer) return std_logic_vector;
+ -- use integer to support 32 bit range and signed
+ function TO_DP_SDATA( n : integer) return std_logic_vector;
+ -- alias of TO_DP_DATA()
+ function TO_DP_UDATA( n : integer) return std_logic_vector;
+ -- for re and im fields, signed data
+ function TO_DP_DSP_DATA(n : integer) return std_logic_vector;
+ -- for re and im fields, unsigned data (useful to carry indices)
+ function TO_DP_DSP_UDATA(n: integer) return std_logic_vector;
function TO_DP_EMPTY( n : natural) return std_logic_vector;
function TO_DP_CHANNEL( n : natural) return std_logic_vector;
function TO_DP_ERROR( n : natural) return std_logic_vector;
function RESIZE_DP_BSN( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
- function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
- function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
+ -- set unused MSBits to '0'
+ function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector;
+ -- sign extend unused MSBits
+ function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector;
+ -- set unused MSBits to 'X'
+ function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector;
+ -- sign extend unused MSBits of re and im fields
+ function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_EMPTY( vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_CHANNEL( vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_ERROR( vec : std_logic_vector) return std_logic_vector;
- function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
- function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
+ -- unsigned vec(w-1:0) + dec
+ function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
+ -- signed vec(w-1:0) + dec
+ function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
+ -- signed vec(w-1:0) + dec
+ function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
- function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+ -- replicate seq as often as fits in c_dp_stream_data_w
+ function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector;
+ -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+ function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector;
function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
@@ -332,12 +370,16 @@ package dp_stream_pkg is
-- Functions to combinatorially handle channels
-- Note that the *_select and *_remove function are equivalent to dp_demux with g_combined=TRUE
- function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
+ -- select channel nr, add the channel field
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
+ -- select channel nr, skip the channel field
+ function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
+ -- skip channel nr
+ function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
-- Functions to combinatorially handle the error field
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
+ -- force err = 0, is OK
+ function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi;
-- Functions to combinatorially handle the BSN field
function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
@@ -359,11 +401,15 @@ package dp_stream_pkg is
-- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
-- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ -- data_order_im_re = TRUE
+ function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi;
+ -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi;
function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ -- data_order_im_re = TRUE
+ function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi;
+ -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
@@ -373,8 +419,10 @@ package dp_stream_pkg is
function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
-- Concatenate the data and complex re,im fields from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
+ -- Concat SOSI_ARR data into single SOSI
+ function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi;
+ -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr;
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
-- . data_representation = "SIGNED" treat sosi.data field as signed
@@ -389,8 +437,10 @@ package dp_stream_pkg is
function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
-- Deconcatenate data and complex re,im fields from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
+ -- Deconcat SOSI data
+ function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr;
+ -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso;
end dp_stream_pkg;
@@ -431,7 +481,8 @@ package body dp_stream_pkg is
signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
- ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
+ -- SLV is used as an array: nof_streams*(0..c_ready_latency)
+ ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready;
end loop;
-- Register siso.ready in c_ready_latency registers
if rising_edge(clk) then
@@ -578,11 +629,14 @@ package body dp_stream_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0);
begin
v_data := RESIZE_UVEC(data, c_vec_w);
- v_seq := v_data(seq_w - 1 downto 0); -- low data part is the v_seq
- v_vec(seq_w - 1 downto 0) := v_seq; -- keep v_seq at low part of return value
+ -- low data part is the v_seq
+ v_seq := v_data(seq_w - 1 downto 0);
+ -- keep v_seq at low part of return value
+ v_vec(seq_w - 1 downto 0) := v_seq;
if c_nof_replications > 1 then
for I in 1 to c_nof_replications - 1 loop
- v_vec((I + 1) * seq_w - 1 downto I * seq_w) := v_data((I + 1) * seq_w - 1 downto I * seq_w) xor v_seq; -- set return bit to '1' for high part data bits that do not match low part v_seq
+ -- set return bit to '1' for high part data bits that do not match low part v_seq
+ v_vec((I + 1) * seq_w - 1 downto I * seq_w) := v_data((I + 1) * seq_w - 1 downto I * seq_w) xor v_seq;
end loop;
end if;
return v_vec(c_data_w - 1 downto 0);
@@ -612,8 +666,10 @@ package body dp_stream_pkg is
begin
assert nof_symbols_from_tail < vN report "func_dp_data_shift_first : no symbols from head" severity FAILURE;
-- use the other sosi from head_sosi
- v_sosi := head_sosi; -- I = nof_symbols_from_tail = 0
- for I in 1 to vN - 1 loop -- I > 0
+ -- I = nof_symbols_from_tail = 0
+ v_sosi := head_sosi;
+ -- I > 0
+ for I in 1 to vN - 1 loop
if nof_symbols_from_tail = I then
v_sosi.data(I * symbol_w - 1 downto 0) := tail_sosi.data(vN * symbol_w - 1 downto (vN - I) * symbol_w);
end if;
@@ -635,15 +691,18 @@ package body dp_stream_pkg is
end if;
-- use sosi data from both if 0 < nof_symbols_from_this < nof_symbols_per_data (i.e. 0 < I < vN)
- if vK < nof_symbols_per_data then -- I = vK = nof_symbols_from_this < vN
+ -- I = vK = nof_symbols_from_this < vN
+ if vK < nof_symbols_per_data then
-- Implementation using variable vK directly instead of via I in a LOOP
-- IF vK > 0 THEN
-- v_sosi.data(vN*symbol_w-1 DOWNTO vK*symbol_w) := prev_sosi.data((vN-vK)*symbol_w-1 DOWNTO 0);
-- v_sosi.data( vK*symbol_w-1 DOWNTO 0) := this_sosi.data( vN *symbol_w-1 DOWNTO (vN-vK)*symbol_w);
-- END IF;
-- Implementaion using LOOP vK rather than VARIABLE vK directly as index to help synthesis and avoid potential multiplier
- v_sosi.data := prev_sosi.data; -- I = vK = nof_symbols_from_this = 0
- for I in 1 to vN - 1 loop -- I = vK = nof_symbols_from_this > 0
+ -- I = vK = nof_symbols_from_this = 0
+ v_sosi.data := prev_sosi.data;
+ -- I = vK = nof_symbols_from_this > 0
+ for I in 1 to vN - 1 loop
if vK = I then
v_sosi.data(vN * symbol_w - 1 downto I * symbol_w) := prev_sosi.data((vN - I) * symbol_w - 1 downto 0);
v_sosi.data( I * symbol_w - 1 downto 0) := this_sosi.data( vN * symbol_w - 1 downto (vN - I) * symbol_w);
@@ -723,7 +782,8 @@ package body dp_stream_pkg is
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '1');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -738,14 +798,17 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_and(v_vec); -- return AND of the masked input fields
+ -- return AND of the masked input fields
+ return vector_and(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_and;
function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '1');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -762,9 +825,11 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_and(v_vec); -- return AND of the masked input fields
+ -- return AND of the masked input fields
+ return vector_and(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_and;
@@ -781,7 +846,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_and;
function func_dp_stream_arr_or(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '0');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -796,14 +862,17 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_or(v_vec); -- return OR of the masked input fields
+ -- return OR of the masked input fields
+ return vector_or(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_or;
function func_dp_stream_arr_or(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '0');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -820,9 +889,11 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_or(v_vec); -- return OR of the masked input fields
+ -- return OR of the masked input fields
+ return vector_or(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_or;
@@ -840,8 +911,10 @@ package body dp_stream_pkg is
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
- variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
- variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
+ -- default
+ variable v_dp : t_dp_siso_arr(dp'range) := dp;
+ -- map to ensure same range as for dp
+ variable v_slv : std_logic_vector(dp'range) := slv;
begin
for I in dp'range loop
if str = "READY" then v_dp(I).ready := v_slv(I);
@@ -853,8 +926,10 @@ package body dp_stream_pkg is
end func_dp_stream_arr_set;
function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- default
- variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
+ -- default
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
+ -- map to ensure same range as for dp
+ variable v_slv : std_logic_vector(dp'range) := slv;
begin
for I in dp'range loop
if str = "VALID" then v_dp(I).valid := v_slv(I);
@@ -1046,29 +1121,40 @@ package body dp_stream_pkg is
-- Functions to combinatorially hold the data fields and to set or reset the info and control fields in an sosi array
function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- v_dp := func_dp_stream_arr_set_info( v_dp, info); -- set sosi info
- v_dp := func_dp_stream_arr_set_control(v_dp, ctrl); -- set sosi ctrl
+ -- set sosi info
+ v_dp := func_dp_stream_arr_set_info( v_dp, info);
+ -- set sosi ctrl
+ v_dp := func_dp_stream_arr_set_control(v_dp, ctrl);
return v_dp;
end func_dp_stream_arr_combine_data_info_ctrl;
function func_dp_stream_arr_set_info(dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- set sosi info
- v_dp(I).bsn := info.bsn; -- sop
- v_dp(I).channel := info.channel; -- sop
- v_dp(I).empty := info.empty; -- eop
- v_dp(I).err := info.err; -- eop
+ -- set sosi info
+ for I in dp'range loop
+ -- sop
+ v_dp(I).bsn := info.bsn;
+ -- sop
+ v_dp(I).channel := info.channel;
+ -- eop
+ v_dp(I).empty := info.empty;
+ -- eop
+ v_dp(I).err := info.err;
end loop;
return v_dp;
end func_dp_stream_arr_set_info;
function func_dp_stream_arr_set_control(dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- set sosi control
+ -- set sosi control
+ for I in dp'range loop
v_dp(I).valid := ctrl.valid;
v_dp(I).sop := ctrl.sop;
v_dp(I).eop := ctrl.eop;
@@ -1078,9 +1164,11 @@ package body dp_stream_pkg is
end func_dp_stream_arr_set_control;
function func_dp_stream_arr_reset_control(dp : t_dp_sosi_arr) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- reset sosi control
+ -- reset sosi control
+ for I in dp'range loop
v_dp(I).valid := '0';
v_dp(I).sop := '0';
v_dp(I).eop := '0';
@@ -1090,7 +1178,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_reset_control;
function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi is
- variable v_dp : t_dp_sosi := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi := dp;
begin
-- reset sosi control
v_dp.valid := '0';
@@ -1102,7 +1191,8 @@ package body dp_stream_pkg is
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
- variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0'); -- init max v_bsn with minimum value
+ -- init max v_bsn with minimum value
+ variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0');
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1121,7 +1211,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_bsn_max;
function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
- variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1'); -- init min v_bsn with maximum value
+ -- init min v_bsn with maximum value
+ variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1');
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1142,7 +1233,8 @@ package body dp_stream_pkg is
-- Function to copy the BSN number of one valid stream to all other streams.
function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1200,10 +1292,12 @@ package body dp_stream_pkg is
end func_dp_stream_bsn_set;
function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
- variable v_rec : t_dp_sosi := data; -- Sosi data fields
+ -- Sosi data fields
+ variable v_rec : t_dp_sosi := data;
begin
-- Combine sosi data with the sosi info fields
- v_rec.sync := info.sync and data.sop; -- force sync only active at data.sop
+ -- force sync only active at data.sop
+ v_rec.sync := info.sync and data.sop;
v_rec.bsn := info.bsn;
v_rec.channel := info.channel;
v_rec.empty := info.empty;
@@ -1215,7 +1309,8 @@ package body dp_stream_pkg is
variable v_rec : t_dp_sosi_integer;
begin
v_rec.sync := slv_sosi.sync;
- v_rec.bsn := TO_UINT(slv_sosi.bsn(30 downto 0)); -- NATURAL'width = 31 bit
+ -- NATURAL'width = 31 bit
+ v_rec.bsn := TO_UINT(slv_sosi.bsn(30 downto 0));
v_rec.data := TO_SINT(slv_sosi.data(w - 1 downto 0));
v_rec.re := TO_SINT(slv_sosi.re(w - 1 downto 0));
v_rec.im := TO_SINT(slv_sosi.im(w - 1 downto 0));
@@ -1333,7 +1428,8 @@ package body dp_stream_pkg is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
- v_dp_arr(i) := func_dp_stream_complex_to_data(dp_arr(i), data_w, nof_data, data_order_im_re); -- nof_data per stream is 1
+ -- nof_data per stream is 1
+ v_dp_arr(i) := func_dp_stream_complex_to_data(dp_arr(i), data_w, nof_data, data_order_im_re);
end loop;
return v_dp_arr;
end;
@@ -1352,7 +1448,8 @@ package body dp_stream_pkg is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
- v_dp_arr(i) := func_dp_stream_data_to_complex(dp_arr(i), data_w, nof_data, data_order_im_re); -- nof_data per stream is 1
+ -- nof_data per stream is 1
+ v_dp_arr(i) := func_dp_stream_data_to_complex(dp_arr(i), data_w, nof_data, data_order_im_re);
end loop;
return v_dp_arr;
end;
@@ -1383,7 +1480,8 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
+ -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is
variable v_snk_out_arr : t_dp_siso_arr(nof_streams - 1 downto 0);
begin
for i in v_snk_out_arr'range loop
@@ -1398,7 +1496,8 @@ package body dp_stream_pkg is
constant c_compl_out_w : natural := out_w / 2;
variable v_src_out : t_dp_sosi := snk_in;
variable v_in_data : std_logic_vector(in_w - 1 downto 0);
- variable v_out_data : std_logic_vector(out_w - 1 downto 0) := (others => '0'); -- default set sosi.data to 0
+ -- default set sosi.data to 0
+ variable v_out_data : std_logic_vector(out_w - 1 downto 0) := (others => '0');
begin
v_src_out := snk_in;
v_src_out.data := (others => '0');
@@ -1406,10 +1505,12 @@ package body dp_stream_pkg is
v_src_out.im := (others => '0');
for i in 0 to nof_data - 1 loop
v_in_data := snk_in.data((i + 1) * in_w - 1 downto i * in_w);
- if data_representation = "UNSIGNED" then -- treat data as unsigned
+ -- treat data as unsigned
+ if data_representation = "UNSIGNED" then
v_out_data := RESIZE_UVEC(v_in_data, out_w);
else
- if data_representation = "SIGNED" then -- treat data as signed
+ -- treat data as signed
+ if data_representation = "SIGNED" then
v_out_data := RESIZE_SVEC(v_in_data, out_w);
else
-- treat data as complex
@@ -1467,7 +1568,8 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
+ -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is
begin
return src_out_arr(0);
end;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
index 103667575791b885ea6d707accd5dc6c04bcb535..86bd5f3ed9ef2f109669b4576b60ab58651ee0f0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
@@ -29,29 +29,39 @@ use dp_lib.dp_stream_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
- constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
- constant c_eth_empty_w : natural := c_tech_tse_empty_w; -- = ceil_log2(c_word_sz) = 2;
- constant c_eth_error_w : natural := c_tech_tse_error_w; -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
-
- constant c_eth_rx_ready_latency : natural := c_tech_tse_rx_ready_latency; -- = 2 = default when FIFO is used
- constant c_eth_tx_ready_latency : natural := c_tech_tse_tx_ready_latency; -- = 0, c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
- constant c_eth_ready_latency : natural := 1; -- = 1, fixed ETH module internal RL
+ -- = c_word_w
+ constant c_eth_data_w : natural := c_tech_tse_data_w;
+ -- = ceil_log2(c_word_sz) = 2;
+ constant c_eth_empty_w : natural := c_tech_tse_empty_w;
+ -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
+ constant c_eth_error_w : natural := c_tech_tse_error_w;
+
+ -- = 2 = default when FIFO is used
+ constant c_eth_rx_ready_latency : natural := c_tech_tse_rx_ready_latency;
+ -- = 0, c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
+ constant c_eth_tx_ready_latency : natural := c_tech_tse_tx_ready_latency;
+ -- = 1, fixed ETH module internal RL
+ constant c_eth_ready_latency : natural := 1;
-- Maximum feasible frame size
- constant c_eth_max_frame_sz : natural := 1024 * 9; -- 9 kByte fits 9020 = word align (2) + eth header (14) + maximum jumbo payload (9000) + CRC (4)
+ -- 9 kByte fits 9020 = word align (2) + eth header (14) + maximum jumbo payload (9000) + CRC (4)
+ constant c_eth_max_frame_sz : natural := 1024 * 9;
constant c_eth_max_frame_nof_words : natural := c_eth_max_frame_sz / c_word_sz;
- constant c_eth_max_frame_nof_words_w : natural := ceil_log2(c_eth_max_frame_nof_words); -- = 12 bit
+ -- = 12 bit
+ constant c_eth_max_frame_nof_words_w : natural := ceil_log2(c_eth_max_frame_nof_words);
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
-- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
- constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
+ -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
+ constant c_eth_frame_sz : natural := 1024 * 2;
-- when the module is used in an Nios II SOPC system
-- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
- constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
+ -- >= 9 bit, <= 12 bit
+ constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words);
type t_eth_data_arr is array (integer range <>) of std_logic_vector(c_eth_data_w - 1 downto 0);
@@ -79,8 +89,10 @@ package eth_pkg is
-- Definitions for eth demux udp
------------------------------------------------------------------------------
- constant c_eth_nof_udp_ports : natural := 4; -- support 2, 4, 8, ... UDP off-load ports
- constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1); -- + 1 for all other packets that go to the default port
+ -- support 2, 4, 8, ... UDP off-load ports
+ constant c_eth_nof_udp_ports : natural := 4;
+ -- + 1 for all other packets that go to the default port
+ constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1);
constant c_eth_nof_channels : natural := 2**c_eth_channel_w;
------------------------------------------------------------------------------
@@ -103,30 +115,46 @@ package eth_pkg is
-- . write/read back registers
type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
type t_eth_mm_reg_demux is record
- udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
- udp_ports : t_eth_demux_ports_arr; -- [15:0]
+ -- [16]
+ udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports);
+ -- [15:0]
+ udp_ports : t_eth_demux_ports_arr;
end record;
type t_eth_mm_reg_config is record
- udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- [15:0]
- ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- [31:0]
- mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- [15:0], [31:0]
+ -- [15:0]
+ udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- [31:0]
+ ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- [15:0], [31:0]
+ mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
end record;
type t_eth_mm_reg_control is record
- tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_request : std_logic; -- 1 bit
- tx_en : std_logic; -- 1 bit
- rx_en : std_logic; -- 1 bit
+ -- 12 bit
+ tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0);
+ -- 2 bit
+ tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0);
+ -- 1 bit
+ tx_request : std_logic;
+ -- 1 bit
+ tx_en : std_logic;
+ -- 1 bit
+ rx_en : std_logic;
end record;
- type t_eth_mm_reg_control_bi is record -- bit indices
- tx_nof_words : natural; -- [26:18]
- tx_empty : natural; -- [17:16]
- tx_request : natural; -- [2]
- tx_en : natural; -- [1]
- rx_en : natural; -- [0]
+ -- bit indices
+ type t_eth_mm_reg_control_bi is record
+ -- [26:18]
+ tx_nof_words : natural;
+ -- [17:16]
+ tx_empty : natural;
+ -- [2]
+ tx_request : natural;
+ -- [1]
+ tx_en : natural;
+ -- [0]
+ rx_en : natural;
end record;
constant c_eth_mm_reg_control_bi : t_eth_mm_reg_control_bi := (18, 16, 2, 1, 0);
@@ -146,36 +174,58 @@ package eth_pkg is
eth_mac_error : std_logic_vector(c_eth_error_w - 1 downto 0);
end record;
- type t_eth_mm_reg_frame_bi is record -- bit indices
- is_dhcp : natural; -- [15]
- is_udp_ctrl_port : natural; -- [14]
- is_udp : natural; -- [13]
- is_icmp : natural; -- [12]
- ip_address_match : natural; -- [11]
- ip_checksum_is_ok : natural; -- [10]
- is_ip : natural; -- [9]
- is_arp : natural; -- [8]
- mac_address_match : natural; -- [7]
- eth_mac_error : natural; -- [6] not used, [5:0] = TSE MAC error
+ -- bit indices
+ type t_eth_mm_reg_frame_bi is record
+ -- [15]
+ is_dhcp : natural;
+ -- [14]
+ is_udp_ctrl_port : natural;
+ -- [13]
+ is_udp : natural;
+ -- [12]
+ is_icmp : natural;
+ -- [11]
+ ip_address_match : natural;
+ -- [10]
+ ip_checksum_is_ok : natural;
+ -- [9]
+ is_ip : natural;
+ -- [8]
+ is_arp : natural;
+ -- [7]
+ mac_address_match : natural;
+ -- [6] not used, [5:0] = TSE MAC error
+ eth_mac_error : natural;
end record;
constant c_eth_mm_reg_frame_bi : t_eth_mm_reg_frame_bi := (15, 14, 13, 12, 11, 10, 9, 8, 7, 0);
constant c_eth_mm_reg_frame_rst : t_eth_mm_reg_frame := ('0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'));
type t_eth_mm_reg_status is record
- rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_avail : std_logic; -- 1 bit
- tx_done : std_logic; -- 1 bit
- rx_avail : std_logic; -- 1 bit
+ -- 12 bit
+ rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0);
+ -- 2 bit
+ rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0);
+ -- 1 bit
+ tx_avail : std_logic;
+ -- 1 bit
+ tx_done : std_logic;
+ -- 1 bit
+ rx_avail : std_logic;
end record;
- type t_eth_mm_reg_status_bi is record -- bit indices
- rx_nof_words : natural; -- [26:18]
- rx_empty : natural; -- [17:16]
- tx_avail : natural; -- [2]
- tx_done : natural; -- [1]
- rx_avail : natural; -- [0]
+ -- bit indices
+ type t_eth_mm_reg_status_bi is record
+ -- [26:18]
+ rx_nof_words : natural;
+ -- [17:16]
+ rx_empty : natural;
+ -- [2]
+ tx_avail : natural;
+ -- [1]
+ tx_done : natural;
+ -- [0]
+ rx_avail : natural;
end record;
constant c_eth_mm_reg_status_bi : t_eth_mm_reg_status_bi := (18, 16, 2, 1, 0);
@@ -202,7 +252,8 @@ package eth_pkg is
c_eth_reg_control_nof_words +
c_eth_reg_frame_nof_words +
c_eth_reg_status_nof_words;
- constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
+ -- + 1 for c_eth_continue_wi
+ constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1);
------------------------------------------------------------------------------
-- Definitions for ETH Rx packet buffer and Tx packet buffer
@@ -223,8 +274,10 @@ package body eth_pkg is
begin
-- Demux UDP MM registers
for I in 1 to c_eth_nof_udp_ports loop
- v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w); -- [16] = UDP port enable
- v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w); -- [15:0] = UDP port number
+ -- [16] = UDP port enable
+ v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w);
+ -- [15:0] = UDP port number
+ v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w);
end loop;
return v_reg;
@@ -233,10 +286,13 @@ package body eth_pkg is
function func_eth_mm_reg_demux(mm_reg : t_eth_mm_reg_demux) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_demux_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
+ -- rsvd
+ v_reg := (others => '0');
for I in 1 to c_eth_nof_udp_ports loop
- v_reg(c_network_udp_port_w + (I - 1) * c_word_w) := mm_reg.udp_ports_en(I); -- [16] = UDP port enable
- v_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w) := mm_reg.udp_ports(I); -- [15:0] = UDP port number
+ -- [16] = UDP port enable
+ v_reg(c_network_udp_port_w + (I - 1) * c_word_w) := mm_reg.udp_ports_en(I);
+ -- [15:0] = UDP port number
+ v_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w) := mm_reg.udp_ports(I);
end loop;
return v_reg;
end func_eth_mm_reg_demux;
@@ -245,21 +301,30 @@ package body eth_pkg is
function func_eth_mm_reg_config(mm_reg : std_logic_vector) return t_eth_mm_reg_config is
variable v_reg : t_eth_mm_reg_config;
begin
- v_reg.udp_port := mm_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w); -- [15:0] = control UDP port number
- v_reg.ip_address := mm_reg( 3 * c_word_w - 1 downto 2 * c_word_w); -- [31:0] = this node IP address
- v_reg.mac_address(47 downto 32) := mm_reg( c_halfword_w + c_word_w - 1 downto c_word_w); -- [47:32] = this node MAC address
- v_reg.mac_address(31 downto 0) := mm_reg( c_word_w - 1 downto 0); -- [31:0] = this node MAC address
+ -- [15:0] = control UDP port number
+ v_reg.udp_port := mm_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w);
+ -- [31:0] = this node IP address
+ v_reg.ip_address := mm_reg( 3 * c_word_w - 1 downto 2 * c_word_w);
+ -- [47:32] = this node MAC address
+ v_reg.mac_address(47 downto 32) := mm_reg( c_halfword_w + c_word_w - 1 downto c_word_w);
+ -- [31:0] = this node MAC address
+ v_reg.mac_address(31 downto 0) := mm_reg( c_word_w - 1 downto 0);
return v_reg;
end func_eth_mm_reg_config;
function func_eth_mm_reg_config(mm_reg : t_eth_mm_reg_config) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_config_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w) := mm_reg.udp_port; -- [15:0] = control UDP port number
- v_reg( 3 * c_word_w - 1 downto 2 * c_word_w) := mm_reg.ip_address; -- [31:0] = this node IP address
- v_reg( c_halfword_w + c_word_w - 1 downto c_word_w) := mm_reg.mac_address(47 downto 32); -- [47:32] = this node MAC address
- v_reg( c_word_w - 1 downto 0) := mm_reg.mac_address(31 downto 0); -- [31:0] = this node MAC address
+ -- rsvd
+ v_reg := (others => '0');
+ -- [15:0] = control UDP port number
+ v_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w) := mm_reg.udp_port;
+ -- [31:0] = this node IP address
+ v_reg( 3 * c_word_w - 1 downto 2 * c_word_w) := mm_reg.ip_address;
+ -- [47:32] = this node MAC address
+ v_reg( c_halfword_w + c_word_w - 1 downto c_word_w) := mm_reg.mac_address(47 downto 32);
+ -- [31:0] = this node MAC address
+ v_reg( c_word_w - 1 downto 0) := mm_reg.mac_address(31 downto 0);
return v_reg;
end func_eth_mm_reg_config;
@@ -267,23 +332,34 @@ package body eth_pkg is
function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control is
variable v_reg : t_eth_mm_reg_control;
begin
- v_reg.tx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
- v_reg.tx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16); -- [17:16]
- v_reg.tx_request := mm_reg( 2); -- [2]
- v_reg.tx_en := mm_reg( 1); -- [1]
- v_reg.rx_en := mm_reg( 0); -- [0]
+ -- [29:18]
+ v_reg.tx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16);
+ -- [17:16]
+ v_reg.tx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16);
+ -- [2]
+ v_reg.tx_request := mm_reg( 2);
+ -- [1]
+ v_reg.tx_en := mm_reg( 1);
+ -- [0]
+ v_reg.rx_en := mm_reg( 0);
return v_reg;
end func_eth_mm_reg_control;
function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_control_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.tx_nof_words; -- [29:18]
- v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.tx_empty; -- [17:16]
- v_reg( 2) := mm_reg.tx_request; -- [2]
- v_reg( 1) := mm_reg.tx_en; -- [1]
- v_reg( 0) := mm_reg.rx_en; -- [0]
+ -- rsvd
+ v_reg := (others => '0');
+ -- [29:18]
+ v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.tx_nof_words;
+ -- [17:16]
+ v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.tx_empty;
+ -- [2]
+ v_reg( 2) := mm_reg.tx_request;
+ -- [1]
+ v_reg( 1) := mm_reg.tx_en;
+ -- [0]
+ v_reg( 0) := mm_reg.rx_en;
return v_reg;
end func_eth_mm_reg_control;
@@ -291,33 +367,54 @@ package body eth_pkg is
function func_eth_mm_reg_frame(mm_reg : std_logic_vector) return t_eth_mm_reg_frame is
variable v_reg : t_eth_mm_reg_frame;
begin
- v_reg.is_dhcp := mm_reg( c_byte_w + 7); -- [15]
- v_reg.is_udp_ctrl_port := mm_reg( c_byte_w + 6); -- [14]
- v_reg.is_udp := mm_reg( c_byte_w + 5); -- [13]
- v_reg.is_icmp := mm_reg( c_byte_w + 4); -- [12]
- v_reg.ip_address_match := mm_reg( c_byte_w + 3); -- [11]
- v_reg.ip_checksum_is_ok := mm_reg( c_byte_w + 2); -- [10]
- v_reg.is_ip := mm_reg( c_byte_w + 1); -- [9]
- v_reg.is_arp := mm_reg( c_byte_w + 0); -- [8]
- v_reg.mac_address_match := mm_reg( c_byte_w - 1); -- [7]
- v_reg.eth_mac_error := mm_reg(c_eth_error_w - 1 downto 0); -- [7] not used, [5:0] = TSE MAC error
+ -- [15]
+ v_reg.is_dhcp := mm_reg( c_byte_w + 7);
+ -- [14]
+ v_reg.is_udp_ctrl_port := mm_reg( c_byte_w + 6);
+ -- [13]
+ v_reg.is_udp := mm_reg( c_byte_w + 5);
+ -- [12]
+ v_reg.is_icmp := mm_reg( c_byte_w + 4);
+ -- [11]
+ v_reg.ip_address_match := mm_reg( c_byte_w + 3);
+ -- [10]
+ v_reg.ip_checksum_is_ok := mm_reg( c_byte_w + 2);
+ -- [9]
+ v_reg.is_ip := mm_reg( c_byte_w + 1);
+ -- [8]
+ v_reg.is_arp := mm_reg( c_byte_w + 0);
+ -- [7]
+ v_reg.mac_address_match := mm_reg( c_byte_w - 1);
+ -- [7] not used, [5:0] = TSE MAC error
+ v_reg.eth_mac_error := mm_reg(c_eth_error_w - 1 downto 0);
return v_reg;
end func_eth_mm_reg_frame;
function func_eth_mm_reg_frame(mm_reg : t_eth_mm_reg_frame) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_frame_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg( c_byte_w + 7) := mm_reg.is_dhcp; -- [15]
- v_reg( c_byte_w + 6) := mm_reg.is_udp_ctrl_port; -- [14]
- v_reg( c_byte_w + 5) := mm_reg.is_udp; -- [13]
- v_reg( c_byte_w + 4) := mm_reg.is_icmp; -- [12]
- v_reg( c_byte_w + 3) := mm_reg.ip_address_match; -- [11]
- v_reg( c_byte_w + 2) := mm_reg.ip_checksum_is_ok; -- [10]
- v_reg( c_byte_w + 1) := mm_reg.is_ip; -- [9]
- v_reg( c_byte_w + 0) := mm_reg.is_arp; -- [8]
- v_reg( c_byte_w - 1) := mm_reg.mac_address_match; -- [7]
- v_reg(c_eth_error_w - 1 downto 0) := mm_reg.eth_mac_error; -- [6] not used, [5:0] = TSE MAC error
+ -- rsvd
+ v_reg := (others => '0');
+ -- [15]
+ v_reg( c_byte_w + 7) := mm_reg.is_dhcp;
+ -- [14]
+ v_reg( c_byte_w + 6) := mm_reg.is_udp_ctrl_port;
+ -- [13]
+ v_reg( c_byte_w + 5) := mm_reg.is_udp;
+ -- [12]
+ v_reg( c_byte_w + 4) := mm_reg.is_icmp;
+ -- [11]
+ v_reg( c_byte_w + 3) := mm_reg.ip_address_match;
+ -- [10]
+ v_reg( c_byte_w + 2) := mm_reg.ip_checksum_is_ok;
+ -- [9]
+ v_reg( c_byte_w + 1) := mm_reg.is_ip;
+ -- [8]
+ v_reg( c_byte_w + 0) := mm_reg.is_arp;
+ -- [7]
+ v_reg( c_byte_w - 1) := mm_reg.mac_address_match;
+ -- [6] not used, [5:0] = TSE MAC error
+ v_reg(c_eth_error_w - 1 downto 0) := mm_reg.eth_mac_error;
return v_reg;
end func_eth_mm_reg_frame;
@@ -325,23 +422,34 @@ package body eth_pkg is
function func_eth_mm_reg_status(mm_reg : std_logic_vector) return t_eth_mm_reg_status is
variable v_reg : t_eth_mm_reg_status;
begin
- v_reg.rx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
- v_reg.rx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16); -- [17:16]
- v_reg.tx_avail := mm_reg( 2); -- [2]
- v_reg.tx_done := mm_reg( 1); -- [1]
- v_reg.rx_avail := mm_reg( 0); -- [0]
+ -- [29:18]
+ v_reg.rx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16);
+ -- [17:16]
+ v_reg.rx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16);
+ -- [2]
+ v_reg.tx_avail := mm_reg( 2);
+ -- [1]
+ v_reg.tx_done := mm_reg( 1);
+ -- [0]
+ v_reg.rx_avail := mm_reg( 0);
return v_reg;
end func_eth_mm_reg_status;
function func_eth_mm_reg_status(mm_reg : t_eth_mm_reg_status) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_status_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.rx_nof_words; -- [29:18]
- v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.rx_empty; -- [17:16]
- v_reg( 2) := mm_reg.tx_avail; -- [2]
- v_reg( 1) := mm_reg.tx_done; -- [1]
- v_reg( 0) := mm_reg.rx_avail; -- [0]
+ -- rsvd
+ v_reg := (others => '0');
+ -- [29:18]
+ v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.rx_nof_words;
+ -- [17:16]
+ v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.rx_empty;
+ -- [2]
+ v_reg( 2) := mm_reg.tx_avail;
+ -- [1]
+ v_reg( 1) := mm_reg.tx_done;
+ -- [0]
+ v_reg( 0) := mm_reg.rx_avail;
return v_reg;
end func_eth_mm_reg_status;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
index 177eb750c7386763043b7282d1bfb4b3a3fc6636..ada21504435ae1849069b8859e9aad66318061d1 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
@@ -25,19 +25,28 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
package tech_tse_pkg is
- constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
+ -- = max 256 MAC registers
+ constant c_tech_tse_reg_addr_w : natural := 8;
constant c_tech_tse_byte_addr_w : natural := c_tech_tse_reg_addr_w + 2;
- constant c_tech_tse_byte_addr_pcs_offset : natural := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
- constant c_tech_tse_data_w : natural := c_word_w; -- = 32
+ -- table 4.8, 4.9 in ug_ethernet.pdf
+ constant c_tech_tse_byte_addr_pcs_offset : natural := 16#200#;
+ -- = 32
+ constant c_tech_tse_data_w : natural := c_word_w;
- constant c_tech_tse_symbol_w : natural := c_byte_w; -- = 8
- constant c_tech_tse_symbol_max : natural := 2**c_tech_tse_symbol_w - 1; -- = 255
- constant c_tech_tse_symbols_per_beat : natural := c_tech_tse_data_w / c_tech_tse_symbol_w; -- = 4
+ -- = 8
+ constant c_tech_tse_symbol_w : natural := c_byte_w;
+ -- = 255
+ constant c_tech_tse_symbol_max : natural := 2**c_tech_tse_symbol_w - 1;
+ -- = 4
+ constant c_tech_tse_symbols_per_beat : natural := c_tech_tse_data_w / c_tech_tse_symbol_w;
- constant c_tech_tse_pcs_reg_addr_w : natural := 5; -- = max 32 PCS registers
- constant c_tech_tse_pcs_halfword_addr_w : natural := c_tech_tse_pcs_reg_addr_w + 1; -- table 4.17 in ug_ethernet.pdf
+ -- = max 32 PCS registers
+ constant c_tech_tse_pcs_reg_addr_w : natural := 5;
+ -- table 4.17 in ug_ethernet.pdf
+ constant c_tech_tse_pcs_halfword_addr_w : natural := c_tech_tse_pcs_reg_addr_w + 1;
constant c_tech_tse_pcs_byte_addr_w : natural := c_tech_tse_pcs_reg_addr_w + 2;
- constant c_tech_tse_pcs_data_w : natural := c_halfword_w; -- = 16;
+ -- = 16;
+ constant c_tech_tse_pcs_data_w : natural := c_halfword_w;
constant c_tech_tse_empty_w : natural := 2;
constant c_tech_tse_tx_error_w : natural := 1;
@@ -46,11 +55,15 @@ package tech_tse_pkg is
constant c_tech_tse_err_stat_w : natural := 18;
constant c_tech_tse_frm_type_w : natural := 4;
- constant c_tech_tse_rx_ready_latency : natural := 2; -- 2 = default when FIFO is used
- constant c_tech_tse_tx_ready_latency : natural := 1; -- c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
+ -- 2 = default when FIFO is used
+ constant c_tech_tse_rx_ready_latency : natural := 2;
+ -- c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
+ constant c_tech_tse_tx_ready_latency : natural := 1;
- constant c_tech_tse_tx_fifo_depth : natural := 256; -- nof words for Tx FIFO
- constant c_tech_tse_rx_fifo_depth : natural := 256; -- nof words for Rx FIFO
+ -- nof words for Tx FIFO
+ constant c_tech_tse_tx_fifo_depth : natural := 256;
+ -- nof words for Rx FIFO
+ constant c_tech_tse_rx_fifo_depth : natural := 256;
type t_tech_tse_tx_mac is record
-- Tx MAC inputs
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
index d648f26fb1cb1a3e9c804714afad5c500ffa4798..048d776d65de66af1f7b85555885b9324efb707b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
@@ -45,25 +45,30 @@ entity avs2_eth_coe is
mms_tse_write : in std_logic;
mms_tse_read : in std_logic;
mms_tse_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_tse_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 0
- mms_tse_waitrequest : out std_logic; -- necessary because read latency is 0
+ -- read latency is 0
+ mms_tse_readdata : out std_logic_vector(c_word_w - 1 downto 0);
+ -- necessary because read latency is 0
+ mms_tse_waitrequest : out std_logic;
-- ETH registers
mms_reg_address : in std_logic_vector(c_eth_reg_addr_w - 1 downto 0);
mms_reg_write : in std_logic;
mms_reg_read : in std_logic;
mms_reg_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_reg_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 1
+ -- read latency is 1
+ mms_reg_readdata : out std_logic_vector(c_word_w - 1 downto 0);
-- ETH packet RAM
mms_ram_address : in std_logic_vector(c_eth_ram_addr_w - 1 downto 0);
mms_ram_write : in std_logic;
mms_ram_read : in std_logic;
mms_ram_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_ram_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 2
+ -- read latency is 2
+ mms_ram_readdata : out std_logic_vector(c_word_w - 1 downto 0);
-- Interrupt Sender interface
- ins_interrupt_irq : out std_logic; -- relates to the ETH registers port
+ -- relates to the ETH registers port
+ ins_interrupt_irq : out std_logic;
----------------------------------------------------------------------------
-- User side
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
index e879f1b9edecdcf0c9866d6359c01c0b6a645338..11d1cb80798696dd2c17cc8cf7ab10c9285e3daf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
@@ -57,27 +57,38 @@ package common_network_layers_pkg is
constant c_network_eth_mac_addr_w : natural := c_network_eth_mac_addr_len * c_8;
constant c_network_eth_type_len : natural := 2;
constant c_network_eth_type_w : natural := c_network_eth_type_len * c_8;
- constant c_network_eth_header_len : natural := 2 * c_network_eth_mac_addr_len + c_network_eth_type_len; -- = 14
+ -- = 14
+ constant c_network_eth_header_len : natural := 2 * c_network_eth_mac_addr_len + c_network_eth_type_len;
constant c_network_eth_payload_min : natural := 46;
constant c_network_eth_payload_max : natural := 1500;
constant c_network_eth_payload_jumbo_max : natural := 9000;
constant c_network_eth_crc_len : natural := 4;
constant c_network_eth_crc_w : natural := c_network_eth_crc_len * c_8;
- constant c_network_eth_gap_len : natural := 12; -- IPG = interpacket gap, minimum idle period between transmission of Ethernet packets
- constant c_network_eth_frame_max : natural := c_network_eth_header_len + c_network_eth_payload_max + c_network_eth_crc_len; -- = 1518
- constant c_network_eth_frame_jumbo_max : natural := c_network_eth_header_len + c_network_eth_payload_jumbo_max + c_network_eth_crc_len; -- = 9018
+ -- IPG = interpacket gap, minimum idle period between transmission of Ethernet packets
+ constant c_network_eth_gap_len : natural := 12;
+ -- = 1518
+ constant c_network_eth_frame_max : natural := c_network_eth_header_len + c_network_eth_payload_max + c_network_eth_crc_len;
+ -- = 9018
+ constant c_network_eth_frame_jumbo_max : natural := c_network_eth_header_len + c_network_eth_payload_jumbo_max + c_network_eth_crc_len;
-- default field values
- constant c_network_eth_preamble : natural := 5; -- nibble "0101"
- constant c_network_eth_frame_delimiter : natural := 13; -- nibble "1101"
+ -- nibble "0101"
+ constant c_network_eth_preamble : natural := 5;
+ -- nibble "1101"
+ constant c_network_eth_frame_delimiter : natural := 13;
-- useful field values
- constant c_network_eth_mac_slv : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := (others => 'X'); -- Ethernet MAC slv RANGE
- constant c_network_eth_bc_mac : std_logic_vector(c_network_eth_mac_slv'range) := (others => '1'); -- Broadcast destination MAC
-
- constant c_network_eth_type_slv : std_logic_vector(c_network_eth_type_w - 1 downto 0) := (others => 'X'); -- Ethernet TYPE slv RANGE
- constant c_network_eth_type_arp : natural := 16#0806#; -- ARP = Address Resolution Prorotol
- constant c_network_eth_type_ip : natural := 16#0800#; -- IPv4 = Internet Protocol, Version 4
+ -- Ethernet MAC slv RANGE
+ constant c_network_eth_mac_slv : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := (others => 'X');
+ -- Broadcast destination MAC
+ constant c_network_eth_bc_mac : std_logic_vector(c_network_eth_mac_slv'range) := (others => '1');
+
+ -- Ethernet TYPE slv RANGE
+ constant c_network_eth_type_slv : std_logic_vector(c_network_eth_type_w - 1 downto 0) := (others => 'X');
+ -- ARP = Address Resolution Prorotol
+ constant c_network_eth_type_arp : natural := 16#0806#;
+ -- IPv4 = Internet Protocol, Version 4
+ constant c_network_eth_type_ip : natural := 16#0800#;
type t_network_eth_header is record
dst_mac : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
@@ -111,8 +122,10 @@ package common_network_layers_pkg is
--
-- field widths in bits '_w' or in bytes '_len'
- constant c_network_ip_version_w : natural := 4; -- 4-bit field
- constant c_network_ip_header_length_w : natural := 4; -- 4-bit field
+ -- 4-bit field
+ constant c_network_ip_version_w : natural := 4;
+ -- 4-bit field
+ constant c_network_ip_header_length_w : natural := 4;
constant c_network_ip_version_header_len : natural := 1;
constant c_network_ip_version_header_w : natural := c_network_ip_version_header_len * c_8;
constant c_network_ip_services_len : natural := 1;
@@ -121,8 +134,10 @@ package common_network_layers_pkg is
constant c_network_ip_total_length_w : natural := c_network_ip_total_length_len * c_8;
constant c_network_ip_identification_len : natural := 2;
constant c_network_ip_identification_w : natural := c_network_ip_identification_len * c_8;
- constant c_network_ip_flags_w : natural := 3; -- 3-bit field
- constant c_network_ip_fragment_offset_w : natural := 13; -- 13-bit field
+ -- 3-bit field
+ constant c_network_ip_flags_w : natural := 3;
+ -- 13-bit field
+ constant c_network_ip_fragment_offset_w : natural := 13;
constant c_network_ip_flags_fragment_len : natural := 2;
constant c_network_ip_flags_fragment_w : natural := c_network_ip_flags_fragment_len * c_8;
constant c_network_ip_time_to_live_len : natural := 1;
@@ -142,36 +157,61 @@ package common_network_layers_pkg is
c_network_ip_addr_len;
-- = c_network_ip_header_length * c_word_sz = 20
-- default field values
- constant c_network_ip_version : natural := 4; -- 4 = IPv4,
- constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
- constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
- constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
- constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
- constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
- constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
- constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
- constant c_network_ip_header_checksum : natural := 0; -- init value
+ -- 4 = IPv4,
+ constant c_network_ip_version : natural := 4;
+ -- 5 = nof words in the header, no options field support
+ constant c_network_ip_header_length : natural := 5;
+ -- 0 = default, use default on transmit, ignore on receive, copy on reply
+ constant c_network_ip_services : natural := 0;
+ -- >= 20, nof bytes in entire datagram including header and data
+ constant c_network_ip_total_length : natural := 20;
+ -- identification number, copy on reply
+ constant c_network_ip_identification : natural := 0;
+ -- 2 = don't fragment and this is the last fragment
+ constant c_network_ip_flags : natural := 2;
+ -- 0 = first fragment
+ constant c_network_ip_fragment_offset : natural := 0;
+ -- number of hops until the packet will be discarded
+ constant c_network_ip_time_to_live : natural := 127;
+ -- init value
+ constant c_network_ip_header_checksum : natural := 0;
-- useful field values
- constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
- constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
- constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
+ -- IP protocol slv RANGE
+ constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X');
+ -- UDP = User Datagram Protocol (for board control and streaming data)
+ constant c_network_ip_protocol_udp : natural := 17;
+ -- ICMP = Internet Control Message Protocol (for ping)
+ constant c_network_ip_protocol_icmp : natural := 1;
- constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
+ -- IP address slv RANGE
+ constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X');
type t_network_ip_header is record
- version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
- header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
- services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
- total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
- identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
- flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
- fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
- time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
- protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
- header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
- src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ -- 4 bit
+ version : std_logic_vector(c_network_ip_version_w - 1 downto 0);
+ -- 4 bit
+ header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0);
+ -- 1 octet
+ services : std_logic_vector(c_network_ip_services_w - 1 downto 0);
+ -- 2 octet
+ total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0);
+ -- 2 octet
+ identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0);
+ -- 3 bit
+ flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0);
+ -- 13 bit
+ fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0);
+ -- 1 octet
+ time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0);
+ -- 1 octet
+ protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0);
+ -- 2 octet
+ header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0);
+ -- 4 octet
+ src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- 4 octet
+ dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
end record;
constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
@@ -223,27 +263,44 @@ package common_network_layers_pkg is
-- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
- constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
- constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
- constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
- constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
- constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
- constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
+ -- Hardware type, 1=ethernet
+ constant c_network_arp_htype : natural := 1;
+ -- Protocol type, do ARP for IPv4
+ constant c_network_arp_ptype : natural := c_network_eth_type_ip;
+ -- Hardware length = 6
+ constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len;
+ -- Protocol length = 4
+ constant c_network_arp_plen : natural := c_network_ip_addr_len;
+ -- Operator, 1=request
+ constant c_network_arp_oper_request : natural := 1;
+ -- Operator, 2=reply
+ constant c_network_arp_oper_reply : natural := 2;
-- useful field values
- constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
- constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
+ -- Broadcast destination MAC
+ constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac;
+ -- Broadcast target hardware address
+ constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac;
type t_network_arp_packet is record
- htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
- ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
- hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
- plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
- oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
- sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
- spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
- tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
- tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
+ -- 2 octet
+ htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0);
+ -- 2 octet
+ ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0);
+ -- 1 octet
+ hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0);
+ -- 1 octet
+ plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0);
+ -- 2 octet
+ oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0);
+ -- 6 octet, Sender Hardware Address
+ sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ -- 4 octet, Sender Protocol Address
+ spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- 6 octet, Target Hardware Address
+ tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ -- 4 octet, Target Protocol Address
+ tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
end record;
constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
@@ -283,21 +340,32 @@ package common_network_layers_pkg is
c_network_icmp_id_len + c_network_icmp_sequence_len;
-- default field values
- constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
- constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
- constant c_network_icmp_checksum : natural := 0; -- init value
+ -- 8 = echo request
+ constant c_network_icmp_msg_type_request : natural := 8;
+ -- 8 = echo reply (ping)
+ constant c_network_icmp_msg_type_reply : natural := 0;
+ -- init value
+ constant c_network_icmp_checksum : natural := 0;
-- useful field values
- constant c_network_icmp_code : natural := 0; -- default
- constant c_network_icmp_id : natural := 3; -- arbitrary value
- constant c_network_icmp_sequence : natural := 4; -- arbitrary value
+ -- default
+ constant c_network_icmp_code : natural := 0;
+ -- arbitrary value
+ constant c_network_icmp_id : natural := 3;
+ -- arbitrary value
+ constant c_network_icmp_sequence : natural := 4;
type t_network_icmp_header is record
- msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
- code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
- checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
- id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
- sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
+ -- 1 octet
+ msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0);
+ -- 1 octet
+ code : std_logic_vector(c_network_icmp_code_w - 1 downto 0);
+ -- 2 octet
+ checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0);
+ -- 2 octet
+ id : std_logic_vector(c_network_icmp_id_w - 1 downto 0);
+ -- 2 octet
+ sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0);
end record;
constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
@@ -328,23 +396,33 @@ package common_network_layers_pkg is
-- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+ -- 8
+ c_network_udp_total_length_len + c_network_udp_checksum_len;
-- default field values
- constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
- constant c_network_udp_checksum : natural := 0; -- init value
+ -- >= 8, nof bytes in entire datagram including header and data
+ constant c_network_udp_total_length : natural := 8;
+ -- init value
+ constant c_network_udp_checksum : natural := 0;
-- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
- constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
- constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
- constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
+ -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
+ constant c_network_udp_port_dhcp_in : natural := 68;
+ -- DHCP to server
+ constant c_network_udp_port_dhcp_out : natural := 67;
+ -- UDP port slv RANGE
+ constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X');
type t_network_udp_header is record
- src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
- checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
+ -- 2 octet
+ src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- 2 octet
+ dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- 2 octet
+ total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0);
+ -- 2 octet
+ checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0);
end record;
constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index 4bd7e15cc8fdafe0a37772e3eaedca527d52c4bf..33e9a782ae790b7c4c71516d23a87c8acd5a53bf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -61,8 +61,10 @@ package common_pkg is
constant c_octet_w : natural := 8;
constant c_halfword_w : natural := c_byte_w * c_halfword_sz;
constant c_word_w : natural := c_byte_w * c_word_sz;
- constant c_integer_w : natural := 32; -- unfortunately VHDL integer type is limited to 32 bit values
- constant c_natural_w : natural := c_integer_w - 1; -- unfortunately VHDL natural type is limited to 31 bit values (0 and the positive subset of the VHDL integer type0
+ -- unfortunately VHDL integer type is limited to 32 bit values
+ constant c_integer_w : natural := 32;
+ -- unfortunately VHDL natural type is limited to 31 bit values (0 and the positive subset of the VHDL integer type0
+ constant c_natural_w : natural := c_integer_w - 1;
constant c_longword_w : natural := c_byte_w * c_longword_sz;
-- logic
@@ -80,30 +82,46 @@ package common_pkg is
constant c_slv10 : std_logic_vector(255 downto 0) := c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10;
-- math
- constant c_nof_complex : natural := 2; -- Real and imaginary part of complex number
- constant c_sign_w : natural := 1; -- Sign bit, can be used to skip one of the double sign bits of a product
- constant c_sum_of_prod_w : natural := 1; -- Bit growth for sum of 2 products, can be used in case complex multiply has normalized real and imag inputs instead of normalized amplitude inputs
+ -- Real and imaginary part of complex number
+ constant c_nof_complex : natural := 2;
+ -- Sign bit, can be used to skip one of the double sign bits of a product
+ constant c_sign_w : natural := 1;
+ -- Bit growth for sum of 2 products, can be used in case complex multiply has normalized real and imag inputs instead of normalized amplitude inputs
+ constant c_sum_of_prod_w : natural := 1;
-- FF, block RAM, FIFO
- constant c_meta_delay_len : natural := 3; -- default nof flipflops (FF) in meta stability recovery delay line (e.g. for clock domain crossing)
- constant c_meta_fifo_depth : natural := 16; -- default use 16 word deep FIFO to cross clock domain, typically > 2*c_meta_delay_len or >~ 8 is enough
+ -- default nof flipflops (FF) in meta stability recovery delay line (e.g. for clock domain crossing)
+ constant c_meta_delay_len : natural := 3;
+ -- default use 16 word deep FIFO to cross clock domain, typically > 2*c_meta_delay_len or >~ 8 is enough
+ constant c_meta_fifo_depth : natural := 16;
- constant c_bram_m9k_nof_bits : natural := 1024 * 9; -- size of 1 Altera M9K block RAM in bits
- constant c_bram_m9k_max_w : natural := 36; -- maximum width of 1 Altera M9K block RAM, so the size is then 256 words of 36 bits
- constant c_bram_m9k_fifo_depth : natural := c_bram_m9k_nof_bits / c_bram_m9k_max_w; -- using a smaller FIFO depth than this leaves part of the RAM unused
+ -- size of 1 Altera M9K block RAM in bits
+ constant c_bram_m9k_nof_bits : natural := 1024 * 9;
+ -- maximum width of 1 Altera M9K block RAM, so the size is then 256 words of 36 bits
+ constant c_bram_m9k_max_w : natural := 36;
+ -- using a smaller FIFO depth than this leaves part of the RAM unused
+ constant c_bram_m9k_fifo_depth : natural := c_bram_m9k_nof_bits / c_bram_m9k_max_w;
- constant c_fifo_afull_margin : natural := 4; -- default or minimal FIFO almost full margin
+ -- default or minimal FIFO almost full margin
+ constant c_fifo_afull_margin : natural := 4;
-- DSP
- constant c_dsp_mult_w : natural := 18; -- Width of the embedded multipliers in Stratix IV
+ -- Width of the embedded multipliers in Stratix IV
+ constant c_dsp_mult_w : natural := 18;
-- TYPE DECLARATIONS --------------------------------------------------------
- type t_boolean_arr is array (integer range <>) of boolean; -- INTEGER left index starts default at -2**31
- type t_integer_arr is array (integer range <>) of integer; -- INTEGER left index starts default at -2**31
- type t_natural_arr is array (integer range <>) of natural; -- INTEGER left index starts default at -2**31
- type t_nat_boolean_arr is array (natural range <>) of boolean; -- NATURAL left index starts default at 0
- type t_nat_integer_arr is array (natural range <>) of integer; -- NATURAL left index starts default at 0
- type t_nat_natural_arr is array (natural range <>) of natural; -- NATURAL left index starts default at 0
+ -- INTEGER left index starts default at -2**31
+ type t_boolean_arr is array (integer range <>) of boolean;
+ -- INTEGER left index starts default at -2**31
+ type t_integer_arr is array (integer range <>) of integer;
+ -- INTEGER left index starts default at -2**31
+ type t_natural_arr is array (integer range <>) of natural;
+ -- NATURAL left index starts default at 0
+ type t_nat_boolean_arr is array (natural range <>) of boolean;
+ -- NATURAL left index starts default at 0
+ type t_nat_integer_arr is array (natural range <>) of integer;
+ -- NATURAL left index starts default at 0
+ type t_nat_natural_arr is array (natural range <>) of natural;
type t_sl_arr is array (integer range <>) of std_logic;
type t_slv_1_arr is array (integer range <>) of std_logic_vector(0 downto 0);
type t_slv_2_arr is array (integer range <>) of std_logic_vector(1 downto 0);
@@ -122,8 +140,10 @@ package common_pkg is
type t_slv_512_arr is array (integer range <>) of std_logic_vector(511 downto 0);
type t_slv_1024_arr is array (integer range <>) of std_logic_vector(1023 downto 0);
- constant c_boolean_arr : t_boolean_arr := (true, false); -- array all possible values that can be iterated over
- constant c_nat_boolean_arr : t_nat_boolean_arr := (true, false); -- array all possible values that can be iterated over
+ -- array all possible values that can be iterated over
+ constant c_boolean_arr : t_boolean_arr := (true, false);
+ -- array all possible values that can be iterated over
+ constant c_nat_boolean_arr : t_nat_boolean_arr := (true, false);
type t_integer_matrix is array (integer range <>, integer range <>) of integer;
type t_boolean_matrix is array (integer range <>, integer range <>) of boolean;
@@ -151,61 +171,87 @@ package common_pkg is
type t_sys_rce is record
rst : std_logic;
clk : std_logic;
- clken : std_logic; -- := '1';
+ -- := '1';
+ clken : std_logic;
end record;
type t_sys_ce is record
clk : std_logic;
- clken : std_logic; -- := '1';
+ -- := '1';
+ clken : std_logic;
end record;
-- FUNCTION DECLARATIONS ----------------------------------------------------
-- All functions assume [high downto low] input ranges
- function pow2(n : natural) return natural; -- = 2**n
- function ceil_pow2(n : integer) return natural; -- = 2**n, returns 1 for n<0
+ -- = 2**n
+ function pow2(n : natural) return natural;
+ -- = 2**n, returns 1 for n<0
+ function ceil_pow2(n : integer) return natural;
- function true_log2(n : natural) return natural; -- true_log2(n) = log2(n)
- function ceil_log2(n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ -- true_log2(n) = log2(n)
+ function true_log2(n : natural) return natural;
+ -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ function ceil_log2(n : natural) return natural;
function floor_log10(n : natural) return natural;
- function is_pow2(n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
- function true_log_pow2(n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
-
- function ratio( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
- function ratio2(n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
-
- function ceil_div( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
- function ceil_value( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
- function floor_value(n, d : natural) return natural; -- floor_value = (n/d) * d
+ -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
+ function is_pow2(n : natural) return boolean;
+ -- 2**true_log2(n), return power of 2 that is >= n
+ function true_log_pow2(n : natural) return natural;
+
+ -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
+ function ratio( n, d : natural) return natural;
+ -- return integer ratio of n/m or m/n, whichever is the largest
+ function ratio2(n, m : natural) return natural;
+
+ -- ceil_div = n/d + (n MOD d)/=0
+ function ceil_div( n, d : natural) return natural;
+ -- ceil_value = ceil_div(n, d) * d
+ function ceil_value( n, d : natural) return natural;
+ -- floor_value = (n/d) * d
+ function floor_value(n, d : natural) return natural;
function ceil_div( n : unsigned; d: natural) return unsigned;
function ceil_value( n : unsigned; d: natural) return unsigned;
function floor_value(n : unsigned; d: natural) return unsigned;
- function slv(n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
- function sl( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
+ -- standard logic to 1 element standard logic vector
+ function slv(n: in std_logic) return std_logic_vector;
+ -- 1 element standard logic vector to standard logic
+ function sl( n: in std_logic_vector) return std_logic;
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr;
function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr;
function to_integer_arr(n : t_natural_arr) return t_integer_arr;
function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr;
function to_slv_32_arr( n : t_integer_arr) return t_slv_32_arr;
function to_slv_32_arr( n : t_natural_arr) return t_slv_32_arr;
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
- function vector_and(slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
- function vector_or( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
- function vector_xor(slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
-
- function andv(slv : std_logic_vector) return std_logic; -- alias of vector_and
- function orv( slv : std_logic_vector) return std_logic; -- alias of vector_or
- function xorv(slv : std_logic_vector) return std_logic; -- alias of vector_xor
-
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
- function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
+ -- Core operation tree function for vector "AND", "OR", "XOR"
+ function vector_tree(slv : std_logic_vector; operation : string) return std_logic;
+ -- '1' when all slv bits are '1' else '0'
+ function vector_and(slv : std_logic_vector) return std_logic;
+ -- '0' when all slv bits are '0' else '1'
+ function vector_or( slv : std_logic_vector) return std_logic;
+ -- '1' when the slv has an odd number of '1' bits else '0'
+ function vector_xor(slv : std_logic_vector) return std_logic;
+ -- Returns slv when it contains one hot bit, else returns 0.
+ function vector_one_hot(slv : std_logic_vector) return std_logic_vector;
+
+ -- alias of vector_and
+ function andv(slv : std_logic_vector) return std_logic;
+ -- alias of vector_or
+ function orv( slv : std_logic_vector) return std_logic;
+ -- alias of vector_xor
+ function xorv(slv : std_logic_vector) return std_logic;
+
+ -- '1' when all matrix bits are '1' else '0'
+ function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic;
+ -- '0' when all matrix bits are '0' else '1'
+ function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic;
function smallest(n, m : integer) return integer;
function smallest(n, m, l : integer) return integer;
@@ -214,34 +260,51 @@ package common_pkg is
function largest(n, m : integer) return integer;
function largest(n : t_natural_arr) return natural;
- function func_sum( n : t_natural_arr) return natural; -- sum of all elements in array
+ -- sum of all elements in array
+ function func_sum( n : t_natural_arr) return natural;
function func_sum( n : t_nat_natural_arr) return natural;
- function func_product(n : t_natural_arr) return natural; -- product of all elements in array
+ -- product of all elements in array
+ function func_product(n : t_natural_arr) return natural;
function func_product(n : t_nat_natural_arr) return natural;
- function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
- function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
- function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
-
- function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
- function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
- function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
- function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
-
- function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
- function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
- function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
-
- function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
- function "/" (L : t_natural_arr; R : positive) return t_natural_arr; -- element wise division
- function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
+ -- element wise sum
+ function "+" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise sum
+ function "+" (L : t_natural_arr; R : integer) return t_natural_arr;
+ -- element wise sum
+ function "+" (L : integer; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise subtract
+ function "-" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise subtract, support negative result
+ function "-" (L, R: t_natural_arr) return t_integer_arr;
+ -- element wise subtract
+ function "-" (L : t_natural_arr; R : integer) return t_natural_arr;
+ -- element wise subtract
+ function "-" (L : integer; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise product
+ function "*" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise product
+ function "*" (L : t_natural_arr; R : natural) return t_natural_arr;
+ -- element wise product
+ function "*" (L : natural; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise division
+ function "/" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise division
+ function "/" (L : t_natural_arr; R : positive) return t_natural_arr;
+ -- element wise division
+ function "/" (L : natural; R : t_natural_arr) return t_natural_arr;
function is_true(a : std_logic) return boolean;
function is_true(a : std_logic) return natural;
function is_true(a : boolean) return std_logic;
function is_true(a : boolean) return natural;
- function is_true(a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
- function is_true(a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
+ -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true(a : integer) return boolean;
+ -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true(a : integer) return std_logic;
function sel_a_b(sel, a, b : boolean) return boolean;
function sel_a_b(sel, a, b : integer) return integer;
@@ -263,46 +326,79 @@ package common_pkg is
function sel_a_b(sel : boolean; a, b : severity_level) return severity_level;
-- sel_n() index sel = 0, 1, 2, ... will return a, b, c, ...
- function sel_n(sel : natural; a, b, c : boolean) return boolean; -- 3
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean; -- 4
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
-
- function sel_n(sel : natural; a, b, c : integer) return integer; -- 3
- function sel_n(sel : natural; a, b, c, d : integer) return integer; -- 4
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
-
- function sel_n(sel : natural; a, b : string) return string; -- 2
- function sel_n(sel : natural; a, b, c : string) return string; -- 3
- function sel_n(sel : natural; a, b, c, d : string) return string; -- 4
- function sel_n(sel : natural; a, b, c, d, e : string) return string; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
+ -- 3
+ function sel_n(sel : natural; a, b, c : boolean) return boolean;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : boolean) return boolean;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean;
+
+ -- 3
+ function sel_n(sel : natural; a, b, c : integer) return integer;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : integer) return integer;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : integer) return integer;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer;
+
+ -- 2
+ function sel_n(sel : natural; a, b : string) return string;
+ -- 3
+ function sel_n(sel : natural; a, b, c : string) return string;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : string) return string;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : string) return string;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : string) return string;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string;
+
+ -- useful to init a unconstrained array of size 1
+ function array_init(init : std_logic; nof : natural) return std_logic_vector;
+ -- useful to init a unconstrained array of size 1
+ function array_init(init, nof : natural) return t_natural_arr;
+ -- useful to init a unconstrained array of size 1
+ function array_init(init, nof : natural) return t_nat_natural_arr;
+ -- useful to init an array with incrementing numbers
+ function array_init(init, nof, incr : natural) return t_natural_arr;
function array_init(init, nof, incr : natural) return t_nat_natural_arr;
function array_init(init, nof, incr : integer) return t_slv_16_arr;
function array_init(init, nof, incr : integer) return t_slv_32_arr;
- function array_init(init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
- function array_init(init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
- function array_sinit(init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+ -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_init(init, nof, width : natural) return std_logic_vector;
+ -- useful to init an unconstrained std_logic_vector with incrementing content
+ function array_init(init, nof, width, incr : natural) return std_logic_vector;
+ -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_sinit(init : integer; nof, width : natural) return std_logic_vector;
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
+ -- initialize all elements in t_slv_64_matrix to value k
+ function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix;
-- Concatenate two or more STD_LOGIC_VECTORs into a single STD_LOGIC_VECTOR or extract one of them from a concatenated STD_LOGIC_VECTOR
function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
@@ -324,13 +420,15 @@ package common_pkg is
function func_slv_extract( use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
function func_slv_extract( use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function TO_UINT(vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ function TO_UINT(vec : std_logic_vector) return natural;
function TO_SINT(vec : std_logic_vector) return integer;
function TO_UVEC(dec, w : natural) return std_logic_vector;
function TO_SVEC(dec, w : integer) return std_logic_vector;
- function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
+ -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
+ function TO_SVEC_32(dec : integer) return std_logic_vector;
-- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
@@ -338,81 +436,132 @@ package common_pkg is
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
-- happens for RESIZE of UNSIGNED. Therefor this is what the RESIZE_NUM for SIGNED and the RESIZE_SVEC do
-- and better not use RESIZE for SIGNED anymore.
- function RESIZE_NUM( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
- function RESIZE_NUM( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
- function RESIZE_UINT(u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
- function RESIZE_SINT(s : integer; w : natural) return integer; -- extend sign bit or keep LS part
-
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
+ -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
+ function RESIZE_NUM( u : unsigned; w : natural) return unsigned;
+ -- extend sign bit or keep LS part
+ function RESIZE_NUM( s : signed; w : natural) return signed;
+ -- left extend with '0' into slv
+ function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector;
+ -- left extend with '0' or keep LS part
+ function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector;
+ -- extend sign bit or keep LS part
+ function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector;
+ -- left extend with '0' or keep LS part
+ function RESIZE_UINT(u : integer; w : natural) return integer;
+ -- extend sign bit or keep LS part
+ function RESIZE_SINT(s : integer; w : natural) return integer;
+
+ -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector;
+ -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector;
function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
-- Used in common_add_sub.vhd
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
-
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
-
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
-
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
+ -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
+ function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
+ function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
+ function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
+ function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+
+ -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+
+ -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
+ function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer;
+ -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
+ function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer;
+
+ -- < 0 shift left, > 0 shift right
+ function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector;
+ -- < 0 shift left, > 0 shift right
+ function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector;
function offset_binary(a : std_logic_vector) return std_logic_vector;
- function truncate( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function scale( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
- function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
- function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
- function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
-
- function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
- function s_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
- function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
- function u_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
-
- function u_to_s(u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
- function s_to_u(s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
-
- function u_wrap(u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
- function s_wrap(s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
-
- function u_clip(u : natural; max : natural) return natural; -- if s < max return s, else return n
- function s_clip(s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
- function s_clip(s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
-
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
- function hton(a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
- function ntoh(a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
-
- function flip(a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
- function flip(a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ -- remove n LSBits from vec, so result has width vec'LENGTH-n
+ function truncate( vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- remove n LSBits from vec and then resize to width w
+ function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- idem for signed values
+ function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- add n '0' LSBits to vec
+ function scale( vec : std_logic_vector; n: natural) return std_logic_vector;
+ -- add n '0' LSBits to vec and then resize to width w
+ function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- idem for signed values
+ function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- when b=TRUE then truncate to width w, else resize to width w
+ function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector;
+ -- idem for signed values
+ function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector;
+
+ -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
+ function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector;
+ -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
+ function s_round( vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- idem but round up to +infinity (s_round_up = u_round)
+ function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector;
+ -- idem but round up to +infinity (s_round_up = u_round)
+ function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- idem round up for unsigned values
+ function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector;
+ -- idem round up for unsigned values
+ function u_round( vec : std_logic_vector; n : natural) return std_logic_vector;
+
+ -- interpret w bit unsigned u as w bit signed, and remove any MSbits
+ function u_to_s(u : natural; w : natural) return integer;
+ -- interpret w bit signed s as w bit unsigned, and remove any MSbits
+ function s_to_u(s : integer; w : natural) return natural;
+
+ -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
+ function u_wrap(u : natural; w : natural) return natural;
+ -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
+ function s_wrap(s : integer; w : natural) return integer;
+
+ -- if s < max return s, else return n
+ function u_clip(u : natural; max : natural) return natural;
+ -- if s <= min return min, else if s >= max return max, else return s
+ function s_clip(s : integer; max : natural; min : integer) return integer;
+ -- if s <= -max return -max, else if s >= max return max, else return s
+ function s_clip(s : integer; max : natural ) return integer;
+
+ -- convert endianity from host to network, sz in symbols of width w
+ function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector;
+ -- convert endianity from host to network, sz in bytes
+ function hton(a : std_logic_vector; sz : natural) return std_logic_vector;
+ -- convert endianity from host to network, for all bytes in a
+ function hton(a : std_logic_vector ) return std_logic_vector;
+ -- convert endianity from network to host, sz in bytes, ntoh() = hton()
+ function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector;
+ -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
+ function ntoh(a : std_logic_vector ) return std_logic_vector;
+
+ -- bit flip a vector, map a[h:0] to [0:h]
+ function flip(a : std_logic_vector) return std_logic_vector;
+ -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ function flip(a, w : natural) return natural;
function flip(a : t_slv_32_arr) return t_slv_32_arr;
function flip(a : t_integer_arr) return t_integer_arr;
function flip(a : t_natural_arr) return t_natural_arr;
function flip(a : t_nat_natural_arr) return t_nat_natural_arr;
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
- function transpose(a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
+ -- transpose a vector, map a[i*row+j] to output index [j*col+i]
+ function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector;
+ -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose(a, row, col : natural) return natural;
function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
@@ -499,9 +648,11 @@ package body common_pkg is
-- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
- return 0; -- Get NULL array
+ -- Get NULL array
+ return 0;
elsif n = 1 then
- return 1; -- avoid NULL array
+ -- avoid NULL array
+ return 1;
else
return true_log2(n);
end if;
@@ -553,7 +704,8 @@ package body common_pkg is
function ceil_div(n : unsigned; d: natural) return unsigned is
begin
- return n / d + sel_a_b(n mod d = 0, 0, 1); -- "/" returns same width as n
+ -- "/" returns same width as n
+ return n / d + sel_a_b(n mod d = 0, 0, 1);
end;
function ceil_value(n : unsigned; d: natural) return unsigned is
@@ -561,7 +713,8 @@ package body common_pkg is
variable p : unsigned(2 * w - 1 downto 0);
begin
p := ceil_div(n, d) * d;
- return p(w - 1 downto 0); -- return same width as n
+ -- return same width as n
+ return p(w - 1 downto 0);
end;
function floor_value(n : unsigned; d: natural) return unsigned is
@@ -569,7 +722,8 @@ package body common_pkg is
variable p : unsigned(2 * w - 1 downto 0);
begin
p := (n / d) * d;
- return p(w - 1 downto 0); -- return same width as n
+ -- return same width as n
+ return p(w - 1 downto 0);
end;
function slv(n: in std_logic) return std_logic_vector is
@@ -664,7 +818,8 @@ package body common_pkg is
-- Instead use binary tree to determine result with smallest combinatorial delay that depends on log2(slv'LENGTH)
constant c_slv_w : natural := slv'length;
constant c_nof_stages : natural := ceil_log2(c_slv_w);
- constant c_w : natural := 2**c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ constant c_w : natural := 2**c_nof_stages;
type t_stage_arr is array (-1 to c_nof_stages - 1) of std_logic_vector(c_w - 1 downto 0);
variable v_stage_arr : t_stage_arr;
variable v_result : std_logic := '0';
@@ -676,7 +831,8 @@ package body common_pkg is
else
assert true report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
end if;
- v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
+ -- any unused input c_w : c_slv_w bits have void default value
+ v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv;
for J in 0 to c_nof_stages - 1 loop
for I in 0 to c_w / (2**(J + 1)) - 1 loop
if operation = "AND" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
@@ -738,7 +894,8 @@ package body common_pkg is
end;
function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic is
- variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
+ -- map to fixed range
+ variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat;
variable v_result : std_logic := '1';
begin
for I in 0 to wi - 1 loop
@@ -750,7 +907,8 @@ package body common_pkg is
end;
function matrix_or(mat : t_sl_matrix; wi, wj : natural) return std_logic is
- variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
+ -- map to fixed range
+ variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat;
variable v_result : std_logic := '0';
begin
for I in 0 to wi - 1 loop
@@ -1513,7 +1671,8 @@ package body common_pkg is
if use_f = true then v_lo := v_lo + f_w; end if;
when others => report "Unknown common_pkg func_slv_extract argument" severity FAILURE;
end case;
- return vec(v_w - 1 + v_lo downto v_lo); -- extracted slv
+ -- extracted slv
+ return vec(v_w - 1 + v_lo downto v_lo);
end func_slv_extract;
function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
@@ -1576,9 +1735,11 @@ package body common_pkg is
begin
-- extend sign bit or keep LS part
if w > s'length then
- return resize(s, w); -- extend sign bit
+ -- extend sign bit
+ return resize(s, w);
else
- return signed(resize(unsigned(s), w)); -- keep LSbits (= vec[w-1:0])
+ -- keep LSbits (= vec[w-1:0])
+ return signed(resize(unsigned(s), w));
end if;
end;
@@ -1627,10 +1788,12 @@ package body common_pkg is
begin
if dec < 0 then
v_dec := -dec;
- return std_logic_vector(unsigned(vec) - v_dec); -- uses function "-" (L : UNSIGNED, R : NATURAL), there is no function + with R : INTEGER argument
+ -- uses function "-" (L : UNSIGNED, R : NATURAL), there is no function + with R : INTEGER argument
+ return std_logic_vector(unsigned(vec) - v_dec);
else
v_dec := dec;
- return std_logic_vector(unsigned(vec) + v_dec); -- uses function "+" (L : UNSIGNED, R : NATURAL)
+ -- uses function "+" (L : UNSIGNED, R : NATURAL)
+ return std_logic_vector(unsigned(vec) + v_dec);
end if;
end;
@@ -1642,7 +1805,8 @@ package body common_pkg is
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
variable v_dec : integer;
begin
- return std_logic_vector(signed(vec) + v_dec); -- uses function "+" (L : SIGNED, R : INTEGER)
+ -- uses function "+" (L : SIGNED, R : INTEGER)
+ return std_logic_vector(signed(vec) + v_dec);
end;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector is
@@ -1703,18 +1867,22 @@ package body common_pkg is
function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
- return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift)); -- fill zeros from right
+ -- fill zeros from right
+ return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift));
else
- return std_logic_vector(SHIFT_RIGHT(unsigned(vec), shift)); -- fill zeros from left
+ -- fill zeros from left
+ return std_logic_vector(SHIFT_RIGHT(unsigned(vec), shift));
end if;
end;
function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
- return std_logic_vector(SHIFT_LEFT(signed(vec), -shift)); -- same as SHIFT_LEFT for UNSIGNED
+ -- same as SHIFT_LEFT for UNSIGNED
+ return std_logic_vector(SHIFT_LEFT(signed(vec), -shift));
else
- return std_logic_vector(SHIFT_RIGHT(signed(vec), shift)); -- extend sign
+ -- extend sign
+ return std_logic_vector(SHIFT_RIGHT(signed(vec), shift));
end if;
end;
@@ -1738,7 +1906,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ v_res(v_res'high) := not v_res(v_res'high);
return v_res;
end;
@@ -1748,7 +1917,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ -- keep MS part
+ v_res := v_vec(c_vec_w - 1 downto n);
return v_res;
end;
@@ -1758,8 +1928,10 @@ package body common_pkg is
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_trunc := truncate(vec, n); -- first keep MS part
- v_res := RESIZE_UVEC(v_trunc, w); -- then keep LS part or left extend with '0'
+ -- first keep MS part
+ v_trunc := truncate(vec, n);
+ -- then keep LS part or left extend with '0'
+ v_res := RESIZE_UVEC(v_trunc, w);
return v_res;
end;
@@ -1769,8 +1941,10 @@ package body common_pkg is
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_trunc := truncate(vec, n); -- first keep MS part
- v_res := RESIZE_SVEC(v_trunc, w); -- then keep sign bit and LS part or left extend sign bit
+ -- first keep MS part
+ v_trunc := truncate(vec, n);
+ -- then keep sign bit and LS part or left extend sign bit
+ v_res := RESIZE_SVEC(v_trunc, w);
return v_res;
end;
@@ -1779,7 +1953,8 @@ package body common_pkg is
constant c_scale_w : natural := c_vec_w + n;
variable v_res : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
begin
- v_res(c_scale_w - 1 downto n) := vec; -- scale by adding n zero bits at the right
+ -- scale by adding n zero bits at the right
+ v_res(c_scale_w - 1 downto n) := vec;
return v_res;
end;
@@ -1789,8 +1964,10 @@ package body common_pkg is
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_scale(c_scale_w - 1 downto n) := vec; -- first scale by adding n zero bits at the right
- v_res := RESIZE_UVEC(v_scale, w); -- then keep LS part or left extend with '0'
+ -- first scale by adding n zero bits at the right
+ v_scale(c_scale_w - 1 downto n) := vec;
+ -- then keep LS part or left extend with '0'
+ v_res := RESIZE_UVEC(v_scale, w);
return v_res;
end;
@@ -1800,8 +1977,10 @@ package body common_pkg is
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_scale(c_scale_w - 1 downto n) := vec; -- first scale by adding n zero bits at the right
- v_res := RESIZE_SVEC(v_scale, w); -- then keep LS part or left extend sign bit
+ -- first scale by adding n zero bits at the right
+ v_scale(c_scale_w - 1 downto n) := vec;
+ -- then keep LS part or left extend sign bit
+ v_res := RESIZE_SVEC(v_scale, w);
return v_res;
end;
@@ -1854,32 +2033,40 @@ package body common_pkg is
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
constant c_one : signed(c_in_w - 1 downto 0) := to_signed(1, c_in_w);
- constant c_half : signed(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1); -- = 2**(n-1)
- constant c_max : signed(c_in_w - 1 downto 0) := signed('0' & c_slv1(c_in_w - 2 downto 0)) - c_half; -- = 2**(c_in_w-1)-1 - c_half
- constant c_clip : signed(c_out_w - 1 downto 0) := signed('0' & c_slv1(c_out_w - 2 downto 0)); -- = 2**(c_out_w-1)-1
+ -- = 2**(n-1)
+ constant c_half : signed(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1);
+ -- = 2**(c_in_w-1)-1 - c_half
+ constant c_max : signed(c_in_w - 1 downto 0) := signed('0' & c_slv1(c_in_w - 2 downto 0)) - c_half;
+ -- = 2**(c_out_w-1)-1
+ constant c_clip : signed(c_out_w - 1 downto 0) := signed('0' & c_slv1(c_out_w - 2 downto 0));
variable v_in : signed(c_in_w - 1 downto 0);
variable v_out : signed(c_out_w - 1 downto 0);
begin
v_in := signed(vec);
if n > 0 then
if clip = true and v_in > c_max then
- v_out := c_clip; -- Round clip to maximum positive to avoid wrap to negative
+ -- Round clip to maximum positive to avoid wrap to negative
+ v_out := c_clip;
else
if vec(vec'high) = '0' then
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half + 0, n), c_out_w); -- Round up for positive
+ -- Round up for positive
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half + 0, n), c_out_w);
else
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half - 1, n), c_out_w); -- Round down for negative
+ -- Round down for negative
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half - 1, n), c_out_w);
end if;
end if;
else
- v_out := RESIZE_NUM(v_in, c_out_w); -- NOP
+ -- NOP
+ v_out := RESIZE_NUM(v_in, c_out_w);
end if;
return std_logic_vector(v_out);
end;
function s_round(vec : std_logic_vector; n : natural) return std_logic_vector is
begin
- return s_round(vec, n, false); -- no round clip
+ -- no round clip
+ return s_round(vec, n, false);
end;
-- An alternative is to always round up, also for negative numbers (i.e. s_round_up = u_round).
@@ -1890,7 +2077,8 @@ package body common_pkg is
function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector is
begin
- return u_round(vec, n, false); -- no round clip
+ -- no round clip
+ return u_round(vec, n, false);
end;
-- Unsigned numbers are round up (almost same as s_round, but without the else on negative vec)
@@ -1899,50 +2087,61 @@ package body common_pkg is
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
constant c_one : unsigned(c_in_w - 1 downto 0) := to_unsigned(1, c_in_w);
- constant c_half : unsigned(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1); -- = 2**(n-1)
- constant c_max : unsigned(c_in_w - 1 downto 0) := unsigned(c_slv1(c_in_w - 1 downto 0)) - c_half; -- = 2**c_in_w-1 - c_half
- constant c_clip : unsigned(c_out_w - 1 downto 0) := unsigned(c_slv1(c_out_w - 1 downto 0)); -- = 2**c_out_w-1
+ -- = 2**(n-1)
+ constant c_half : unsigned(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1);
+ -- = 2**c_in_w-1 - c_half
+ constant c_max : unsigned(c_in_w - 1 downto 0) := unsigned(c_slv1(c_in_w - 1 downto 0)) - c_half;
+ -- = 2**c_out_w-1
+ constant c_clip : unsigned(c_out_w - 1 downto 0) := unsigned(c_slv1(c_out_w - 1 downto 0));
variable v_in : unsigned(c_in_w - 1 downto 0);
variable v_out : unsigned(c_out_w - 1 downto 0);
begin
v_in := unsigned(vec);
if n > 0 then
if clip = true and v_in > c_max then
- v_out := c_clip; -- Round clip to +max to avoid wrap to 0
+ -- Round clip to +max to avoid wrap to 0
+ v_out := c_clip;
else
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half, n), c_out_w); -- Round up
+ -- Round up
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half, n), c_out_w);
end if;
else
- v_out := RESIZE_NUM(v_in, c_out_w); -- NOP
+ -- NOP
+ v_out := RESIZE_NUM(v_in, c_out_w);
end if;
return std_logic_vector(v_out);
end;
function u_round(vec : std_logic_vector; n : natural) return std_logic_vector is
begin
- return u_round(vec, n, false); -- no round clip
+ -- no round clip
+ return u_round(vec, n, false);
end;
function u_to_s(u : natural; w : natural) return integer is
- variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32);
begin
return TO_SINT(v_u(w - 1 downto 0));
end;
function s_to_u(s : integer; w : natural) return natural is
- variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32);
begin
return TO_UINT(v_s(w - 1 downto 0));
end;
function u_wrap(u : natural; w : natural) return natural is
- variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32);
begin
return TO_UINT(v_u(w - 1 downto 0));
end;
function s_wrap(s : integer; w : natural) return integer is
- variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32);
begin
return TO_SINT(v_s(w - 1 downto 0));
end;
@@ -1975,8 +2174,10 @@ package body common_pkg is
end;
function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector is
- variable v_a : std_logic_vector(a'length - 1 downto 0) := a; -- map a to range [h:0]
- variable v_b : std_logic_vector(a'length - 1 downto 0) := a; -- default b = a
+ -- map a to range [h:0]
+ variable v_a : std_logic_vector(a'length - 1 downto 0) := a;
+ -- default b = a
+ variable v_b : std_logic_vector(a'length - 1 downto 0) := a;
variable vL : natural;
variable vK : natural;
begin
@@ -1992,23 +2193,27 @@ package body common_pkg is
function hton(a : std_logic_vector; sz : natural) return std_logic_vector is
begin
- return hton(a, c_byte_w, sz); -- symbol width w = c_byte_w = 8
+ -- symbol width w = c_byte_w = 8
+ return hton(a, c_byte_w, sz);
end function;
function hton(a : std_logic_vector) return std_logic_vector is
constant c_sz : natural := a'length / c_byte_w;
begin
- return hton(a, c_byte_w, c_sz); -- symbol width w = c_byte_w = 8
+ -- symbol width w = c_byte_w = 8
+ return hton(a, c_byte_w, c_sz);
end function;
function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector is
begin
- return hton(a, sz); -- i.e. ntoh() = hton()
+ -- i.e. ntoh() = hton()
+ return hton(a, sz);
end function;
function ntoh(a : std_logic_vector) return std_logic_vector is
begin
- return hton(a); -- i.e. ntoh() = hton()
+ -- i.e. ntoh() = hton()
+ return hton(a);
end function;
function flip(a : std_logic_vector) return std_logic_vector is
@@ -2070,17 +2275,21 @@ package body common_pkg is
variable vIn : std_logic_vector(a'length - 1 downto 0);
variable vOut : std_logic_vector(a'length - 1 downto 0);
begin
- vIn := a; -- map input vector to h:0 range
- vOut := vIn; -- default leave any unused MSbits the same
+ -- map input vector to h:0 range
+ vIn := a;
+ -- default leave any unused MSbits the same
+ vOut := vIn;
for J in 0 to row - 1 loop
for I in 0 to col - 1 loop
- vOut(J * col + I) := vIn(I * row + J); -- transpose vector, map input index [i*row+j] to output index [j*col+i]
+ -- transpose vector, map input index [i*row+j] to output index [j*col+i]
+ vOut(J * col + I) := vIn(I * row + J);
end loop;
end loop;
return vOut;
end function;
- function transpose(a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
+ -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose(a, row, col : natural) return natural is
variable vI : natural;
variable vJ : natural;
begin
@@ -2089,16 +2298,20 @@ package body common_pkg is
return vJ * col + vI;
end;
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
+ -- Calculate input_w in multiples as close as possible to max_out_w
+ function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is
-- Examples: split_w(256, 8, 32) = 32; split_w(16, 8, 32) = 16; split_w(72, 8, 32) = 18; -- Input_w must be multiple of 2.
variable r: natural;
begin
r := input_w;
- for i in 1 to ceil_log2(input_w) loop -- Useless to divide the number beyond this
+ -- Useless to divide the number beyond this
+ for i in 1 to ceil_log2(input_w) loop
if r <= max_out_w and r >= min_out_w then
return r;
- elsif i = ceil_log2(input_w) then -- last iteration
- return 0; -- Indicates wrong values were used
+ -- last iteration
+ elsif i = ceil_log2(input_w) then
+ -- Indicates wrong values were used
+ return 0;
end if;
r := r / 2;
end loop;
@@ -2197,8 +2410,10 @@ package body common_pkg is
variable v_odd : boolean;
variable v_even : boolean;
begin
- v_odd := (I mod 2 = 1) and (J mod 2 = 1); -- for odd stage at each odd row
- v_even := (I mod 2 = 0) and (J mod 2 = 0); -- for even stage at each even row
+ -- for odd stage at each odd row
+ v_odd := (I mod 2 = 1) and (J mod 2 = 1);
+ -- for even stage at each even row
+ v_even := (I mod 2 = 0) and (J mod 2 = 0);
return v_odd or v_even;
end func_common_reorder2_is_there;
@@ -2228,7 +2443,8 @@ package body common_pkg is
-- for the active two port reorder cells use the setting at index v_K from the select setting array
v_nof_odd_stages := I / 2;
v_nof_even_stages := (I - 1) / 2;
- v_offset := (J - 1) / 2; -- suits both odd stage and even stage
+ -- suits both odd stage and even stage
+ v_offset := (J - 1) / 2;
v_K := v_nof_odd_stages * c_nof_reorder2_per_odd_stage + v_nof_even_stages * c_nof_reorder2_per_even_stage + v_offset;
end if;
return v_K;
@@ -2237,7 +2453,8 @@ package body common_pkg is
-- Get the select setting for the reorder2 cell on stage I and row J in a reorder network with N stages
function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural is
constant c_nof_select : natural := select_arr'length;
- constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
+ -- force range downto 0
+ constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr;
variable v_sel : natural;
variable v_K : integer;
begin
@@ -2252,11 +2469,13 @@ package body common_pkg is
-- Determine the inverse of a reorder network by using two reorder networks in series
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr is
constant c_nof_select : natural := select_arr'length;
- constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
+ -- force range downto 0
+ constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr;
variable v_sel : natural;
variable v_Ki : integer;
variable v_Ii : natural;
- variable v_inverse_arr : t_natural_arr(2 * c_nof_select - 1 downto 0) := (others => 0); -- default set identity for the reorder2 cells in both reorder instances
+ -- default set identity for the reorder2 cells in both reorder instances
+ variable v_inverse_arr : t_natural_arr(2 * c_nof_select - 1 downto 0) := (others => 0);
begin
-- the inverse select consists of inverse_in reorder and inverse_out reorder in series
if N mod 2 = 1 then
@@ -2276,7 +2495,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ -- stage 1 of the inverse_out reorder
+ v_Ki := c_nof_select + K;
v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index 7b6d1a2da0ec2558d87aa708358be0b79c70944d..dc48b2f8f8d20d5ee0c491104976d7126bb80f02 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -48,35 +48,59 @@ package dp_stream_pkg is
-- This grouping is useful for functions that operate on a t_dp_sosi signal.
-- * The info fields are valid at the sop or at the eop, but typically they hold their last active value to avoid unnessary
-- toggling and to ease viewing in the wave window.
- constant c_dp_stream_bsn_w : natural := 64; -- 64 is sufficient to count blocks of data for years
- constant c_dp_stream_data_w : natural := 768; -- 72 is sufficient for max word 8 * 9-bit. 576 supports half rate DDR4 bus data width. The current 768 is enough for wide single clock SLVs (e.g. headers)
- constant c_dp_stream_dsp_data_w : natural := 64; -- 64 is sufficient for DSP data, including complex power accumulates
- constant c_dp_stream_empty_w : natural := 16; -- 8 is sufficient for max 256 symbols per data word, still use 16 bit to be able to count c_dp_stream_data_w in bits
- constant c_dp_stream_channel_w : natural := 32; -- 32 is sufficient for several levels of hierarchy in mapping types of streams on to channels
- constant c_dp_stream_error_w : natural := 32; -- 32 is sufficient for several levels of hierarchy in mapping error numbers, e.g. 32 different one-hot encoded errors, bit [0] = 0 = OK
-
- constant c_dp_stream_ok : natural := 0; -- SOSI err field OK value
- constant c_dp_stream_err : natural := 1; -- SOSI err field error value /= OK
-
- constant c_dp_stream_rl : natural := 1; -- SISO default data path stream ready latency RL = 1
-
- type t_dp_siso is record -- Source In or Sink Out
- ready : std_logic; -- fine cycle based flow control using ready latency RL >= 0
- xon : std_logic; -- coarse typically block based flow control using xon/xoff
+ -- 64 is sufficient to count blocks of data for years
+ constant c_dp_stream_bsn_w : natural := 64;
+ -- 72 is sufficient for max word 8 * 9-bit. 576 supports half rate DDR4 bus data width. The current 768 is enough for wide single clock SLVs (e.g. headers)
+ constant c_dp_stream_data_w : natural := 768;
+ -- 64 is sufficient for DSP data, including complex power accumulates
+ constant c_dp_stream_dsp_data_w : natural := 64;
+ -- 8 is sufficient for max 256 symbols per data word, still use 16 bit to be able to count c_dp_stream_data_w in bits
+ constant c_dp_stream_empty_w : natural := 16;
+ -- 32 is sufficient for several levels of hierarchy in mapping types of streams on to channels
+ constant c_dp_stream_channel_w : natural := 32;
+ -- 32 is sufficient for several levels of hierarchy in mapping error numbers, e.g. 32 different one-hot encoded errors, bit [0] = 0 = OK
+ constant c_dp_stream_error_w : natural := 32;
+
+ -- SOSI err field OK value
+ constant c_dp_stream_ok : natural := 0;
+ -- SOSI err field error value /= OK
+ constant c_dp_stream_err : natural := 1;
+
+ -- SISO default data path stream ready latency RL = 1
+ constant c_dp_stream_rl : natural := 1;
+
+ -- Source In or Sink Out
+ type t_dp_siso is record
+ -- fine cycle based flow control using ready latency RL >= 0
+ ready : std_logic;
+ -- coarse typically block based flow control using xon/xoff
+ xon : std_logic;
end record;
- type t_dp_sosi is record -- Source Out or Sink In
- sync : std_logic; -- ctrl
- bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0); -- info at sop (block sequence number)
- data : std_logic_vector(c_dp_stream_data_w - 1 downto 0); -- data
- re : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0); -- data
- im : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0); -- data
- valid : std_logic; -- ctrl
- sop : std_logic; -- ctrl
- eop : std_logic; -- ctrl
- empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0); -- info at eop
- channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0); -- info at sop
- err : std_logic_vector(c_dp_stream_error_w - 1 downto 0); -- info at eop (name field 'err' to avoid the 'error' keyword)
+ -- Source Out or Sink In
+ type t_dp_sosi is record
+ -- ctrl
+ sync : std_logic;
+ -- info at sop (block sequence number)
+ bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ -- data
+ data : std_logic_vector(c_dp_stream_data_w - 1 downto 0);
+ -- data
+ re : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0);
+ -- data
+ im : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0);
+ -- ctrl
+ valid : std_logic;
+ -- ctrl
+ sop : std_logic;
+ -- ctrl
+ eop : std_logic;
+ -- info at eop
+ empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0);
+ -- info at sop
+ channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0);
+ -- info at eop (name field 'err' to avoid the 'error' keyword)
+ err : std_logic_vector(c_dp_stream_error_w - 1 downto 0);
end record;
-- Initialise signal declarations with c_dp_stream_rst/rdy to ease the interpretation of slv fields with unused bits
@@ -240,29 +264,43 @@ package dp_stream_pkg is
-- signed data in the simulation wave window it is easier to use sign extension in the record field. Therefore TO_DP_SDATA
-- and RESIZE_DP_SDATA are defined as well.
function TO_DP_BSN( n : natural) return std_logic_vector;
- function TO_DP_DATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
- function TO_DP_SDATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
- function TO_DP_UDATA( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector; -- for re and im fields, signed data
- function TO_DP_DSP_UDATA(n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
+ -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
+ function TO_DP_DATA( n : integer) return std_logic_vector;
+ -- use integer to support 32 bit range and signed
+ function TO_DP_SDATA( n : integer) return std_logic_vector;
+ -- alias of TO_DP_DATA()
+ function TO_DP_UDATA( n : integer) return std_logic_vector;
+ -- for re and im fields, signed data
+ function TO_DP_DSP_DATA(n : integer) return std_logic_vector;
+ -- for re and im fields, unsigned data (useful to carry indices)
+ function TO_DP_DSP_UDATA(n: integer) return std_logic_vector;
function TO_DP_EMPTY( n : natural) return std_logic_vector;
function TO_DP_CHANNEL( n : natural) return std_logic_vector;
function TO_DP_ERROR( n : natural) return std_logic_vector;
function RESIZE_DP_BSN( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
- function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
- function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
+ -- set unused MSBits to '0'
+ function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector;
+ -- sign extend unused MSBits
+ function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector;
+ -- set unused MSBits to 'X'
+ function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector;
+ -- sign extend unused MSBits of re and im fields
+ function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_EMPTY( vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_CHANNEL( vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_ERROR( vec : std_logic_vector) return std_logic_vector;
- function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
- function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
+ -- unsigned vec(w-1:0) + dec
+ function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
+ -- signed vec(w-1:0) + dec
+ function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
+ -- signed vec(w-1:0) + dec
+ function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
- function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+ -- replicate seq as often as fits in c_dp_stream_data_w
+ function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector;
+ -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+ function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector;
function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
@@ -332,12 +370,16 @@ package dp_stream_pkg is
-- Functions to combinatorially handle channels
-- Note that the *_select and *_remove function are equivalent to dp_demux with g_combined=TRUE
- function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
+ -- select channel nr, add the channel field
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
+ -- select channel nr, skip the channel field
+ function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
+ -- skip channel nr
+ function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
-- Functions to combinatorially handle the error field
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
+ -- force err = 0, is OK
+ function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi;
-- Functions to combinatorially handle the BSN field
function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
@@ -359,11 +401,15 @@ package dp_stream_pkg is
-- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
-- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ -- data_order_im_re = TRUE
+ function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi;
+ -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi;
function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ -- data_order_im_re = TRUE
+ function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi;
+ -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
@@ -373,8 +419,10 @@ package dp_stream_pkg is
function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
-- Concatenate the data and complex re,im fields from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
+ -- Concat SOSI_ARR data into single SOSI
+ function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi;
+ -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr;
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
-- . data_representation = "SIGNED" treat sosi.data field as signed
@@ -389,8 +437,10 @@ package dp_stream_pkg is
function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
-- Deconcatenate data and complex re,im fields from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
+ -- Deconcat SOSI data
+ function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr;
+ -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso;
end dp_stream_pkg;
@@ -431,7 +481,8 @@ package body dp_stream_pkg is
signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
- ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
+ -- SLV is used as an array: nof_streams*(0..c_ready_latency)
+ ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready;
end loop;
-- Register siso.ready in c_ready_latency registers
if rising_edge(clk) then
@@ -578,11 +629,14 @@ package body dp_stream_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0);
begin
v_data := RESIZE_UVEC(data, c_vec_w);
- v_seq := v_data(seq_w - 1 downto 0); -- low data part is the v_seq
- v_vec(seq_w - 1 downto 0) := v_seq; -- keep v_seq at low part of return value
+ -- low data part is the v_seq
+ v_seq := v_data(seq_w - 1 downto 0);
+ -- keep v_seq at low part of return value
+ v_vec(seq_w - 1 downto 0) := v_seq;
if c_nof_replications > 1 then
for I in 1 to c_nof_replications - 1 loop
- v_vec((I + 1) * seq_w - 1 downto I * seq_w) := v_data((I + 1) * seq_w - 1 downto I * seq_w) xor v_seq; -- set return bit to '1' for high part data bits that do not match low part v_seq
+ -- set return bit to '1' for high part data bits that do not match low part v_seq
+ v_vec((I + 1) * seq_w - 1 downto I * seq_w) := v_data((I + 1) * seq_w - 1 downto I * seq_w) xor v_seq;
end loop;
end if;
return v_vec(c_data_w - 1 downto 0);
@@ -612,8 +666,10 @@ package body dp_stream_pkg is
begin
assert nof_symbols_from_tail < vN report "func_dp_data_shift_first : no symbols from head" severity FAILURE;
-- use the other sosi from head_sosi
- v_sosi := head_sosi; -- I = nof_symbols_from_tail = 0
- for I in 1 to vN - 1 loop -- I > 0
+ -- I = nof_symbols_from_tail = 0
+ v_sosi := head_sosi;
+ -- I > 0
+ for I in 1 to vN - 1 loop
if nof_symbols_from_tail = I then
v_sosi.data(I * symbol_w - 1 downto 0) := tail_sosi.data(vN * symbol_w - 1 downto (vN - I) * symbol_w);
end if;
@@ -635,15 +691,18 @@ package body dp_stream_pkg is
end if;
-- use sosi data from both if 0 < nof_symbols_from_this < nof_symbols_per_data (i.e. 0 < I < vN)
- if vK < nof_symbols_per_data then -- I = vK = nof_symbols_from_this < vN
+ -- I = vK = nof_symbols_from_this < vN
+ if vK < nof_symbols_per_data then
-- Implementation using variable vK directly instead of via I in a LOOP
-- IF vK > 0 THEN
-- v_sosi.data(vN*symbol_w-1 DOWNTO vK*symbol_w) := prev_sosi.data((vN-vK)*symbol_w-1 DOWNTO 0);
-- v_sosi.data( vK*symbol_w-1 DOWNTO 0) := this_sosi.data( vN *symbol_w-1 DOWNTO (vN-vK)*symbol_w);
-- END IF;
-- Implementaion using LOOP vK rather than VARIABLE vK directly as index to help synthesis and avoid potential multiplier
- v_sosi.data := prev_sosi.data; -- I = vK = nof_symbols_from_this = 0
- for I in 1 to vN - 1 loop -- I = vK = nof_symbols_from_this > 0
+ -- I = vK = nof_symbols_from_this = 0
+ v_sosi.data := prev_sosi.data;
+ -- I = vK = nof_symbols_from_this > 0
+ for I in 1 to vN - 1 loop
if vK = I then
v_sosi.data(vN * symbol_w - 1 downto I * symbol_w) := prev_sosi.data((vN - I) * symbol_w - 1 downto 0);
v_sosi.data( I * symbol_w - 1 downto 0) := this_sosi.data( vN * symbol_w - 1 downto (vN - I) * symbol_w);
@@ -723,7 +782,8 @@ package body dp_stream_pkg is
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '1');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -738,14 +798,17 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_and(v_vec); -- return AND of the masked input fields
+ -- return AND of the masked input fields
+ return vector_and(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_and;
function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '1');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -762,9 +825,11 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_and(v_vec); -- return AND of the masked input fields
+ -- return AND of the masked input fields
+ return vector_and(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_and;
@@ -781,7 +846,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_and;
function func_dp_stream_arr_or(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '0');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -796,14 +862,17 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_or(v_vec); -- return OR of the masked input fields
+ -- return OR of the masked input fields
+ return vector_or(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_or;
function func_dp_stream_arr_or(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '0');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -820,9 +889,11 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_or(v_vec); -- return OR of the masked input fields
+ -- return OR of the masked input fields
+ return vector_or(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_or;
@@ -840,8 +911,10 @@ package body dp_stream_pkg is
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
- variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
- variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
+ -- default
+ variable v_dp : t_dp_siso_arr(dp'range) := dp;
+ -- map to ensure same range as for dp
+ variable v_slv : std_logic_vector(dp'range) := slv;
begin
for I in dp'range loop
if str = "READY" then v_dp(I).ready := v_slv(I);
@@ -853,8 +926,10 @@ package body dp_stream_pkg is
end func_dp_stream_arr_set;
function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- default
- variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
+ -- default
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
+ -- map to ensure same range as for dp
+ variable v_slv : std_logic_vector(dp'range) := slv;
begin
for I in dp'range loop
if str = "VALID" then v_dp(I).valid := v_slv(I);
@@ -1046,29 +1121,40 @@ package body dp_stream_pkg is
-- Functions to combinatorially hold the data fields and to set or reset the info and control fields in an sosi array
function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- v_dp := func_dp_stream_arr_set_info( v_dp, info); -- set sosi info
- v_dp := func_dp_stream_arr_set_control(v_dp, ctrl); -- set sosi ctrl
+ -- set sosi info
+ v_dp := func_dp_stream_arr_set_info( v_dp, info);
+ -- set sosi ctrl
+ v_dp := func_dp_stream_arr_set_control(v_dp, ctrl);
return v_dp;
end func_dp_stream_arr_combine_data_info_ctrl;
function func_dp_stream_arr_set_info(dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- set sosi info
- v_dp(I).bsn := info.bsn; -- sop
- v_dp(I).channel := info.channel; -- sop
- v_dp(I).empty := info.empty; -- eop
- v_dp(I).err := info.err; -- eop
+ -- set sosi info
+ for I in dp'range loop
+ -- sop
+ v_dp(I).bsn := info.bsn;
+ -- sop
+ v_dp(I).channel := info.channel;
+ -- eop
+ v_dp(I).empty := info.empty;
+ -- eop
+ v_dp(I).err := info.err;
end loop;
return v_dp;
end func_dp_stream_arr_set_info;
function func_dp_stream_arr_set_control(dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- set sosi control
+ -- set sosi control
+ for I in dp'range loop
v_dp(I).valid := ctrl.valid;
v_dp(I).sop := ctrl.sop;
v_dp(I).eop := ctrl.eop;
@@ -1078,9 +1164,11 @@ package body dp_stream_pkg is
end func_dp_stream_arr_set_control;
function func_dp_stream_arr_reset_control(dp : t_dp_sosi_arr) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- reset sosi control
+ -- reset sosi control
+ for I in dp'range loop
v_dp(I).valid := '0';
v_dp(I).sop := '0';
v_dp(I).eop := '0';
@@ -1090,7 +1178,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_reset_control;
function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi is
- variable v_dp : t_dp_sosi := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi := dp;
begin
-- reset sosi control
v_dp.valid := '0';
@@ -1102,7 +1191,8 @@ package body dp_stream_pkg is
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
- variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0'); -- init max v_bsn with minimum value
+ -- init max v_bsn with minimum value
+ variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0');
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1121,7 +1211,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_bsn_max;
function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
- variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1'); -- init min v_bsn with maximum value
+ -- init min v_bsn with maximum value
+ variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1');
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1142,7 +1233,8 @@ package body dp_stream_pkg is
-- Function to copy the BSN number of one valid stream to all other streams.
function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1200,10 +1292,12 @@ package body dp_stream_pkg is
end func_dp_stream_bsn_set;
function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
- variable v_rec : t_dp_sosi := data; -- Sosi data fields
+ -- Sosi data fields
+ variable v_rec : t_dp_sosi := data;
begin
-- Combine sosi data with the sosi info fields
- v_rec.sync := info.sync and data.sop; -- force sync only active at data.sop
+ -- force sync only active at data.sop
+ v_rec.sync := info.sync and data.sop;
v_rec.bsn := info.bsn;
v_rec.channel := info.channel;
v_rec.empty := info.empty;
@@ -1215,7 +1309,8 @@ package body dp_stream_pkg is
variable v_rec : t_dp_sosi_integer;
begin
v_rec.sync := slv_sosi.sync;
- v_rec.bsn := TO_UINT(slv_sosi.bsn(30 downto 0)); -- NATURAL'width = 31 bit
+ -- NATURAL'width = 31 bit
+ v_rec.bsn := TO_UINT(slv_sosi.bsn(30 downto 0));
v_rec.data := TO_SINT(slv_sosi.data(w - 1 downto 0));
v_rec.re := TO_SINT(slv_sosi.re(w - 1 downto 0));
v_rec.im := TO_SINT(slv_sosi.im(w - 1 downto 0));
@@ -1333,7 +1428,8 @@ package body dp_stream_pkg is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
- v_dp_arr(i) := func_dp_stream_complex_to_data(dp_arr(i), data_w, nof_data, data_order_im_re); -- nof_data per stream is 1
+ -- nof_data per stream is 1
+ v_dp_arr(i) := func_dp_stream_complex_to_data(dp_arr(i), data_w, nof_data, data_order_im_re);
end loop;
return v_dp_arr;
end;
@@ -1352,7 +1448,8 @@ package body dp_stream_pkg is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
- v_dp_arr(i) := func_dp_stream_data_to_complex(dp_arr(i), data_w, nof_data, data_order_im_re); -- nof_data per stream is 1
+ -- nof_data per stream is 1
+ v_dp_arr(i) := func_dp_stream_data_to_complex(dp_arr(i), data_w, nof_data, data_order_im_re);
end loop;
return v_dp_arr;
end;
@@ -1383,7 +1480,8 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
+ -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is
variable v_snk_out_arr : t_dp_siso_arr(nof_streams - 1 downto 0);
begin
for i in v_snk_out_arr'range loop
@@ -1398,7 +1496,8 @@ package body dp_stream_pkg is
constant c_compl_out_w : natural := out_w / 2;
variable v_src_out : t_dp_sosi := snk_in;
variable v_in_data : std_logic_vector(in_w - 1 downto 0);
- variable v_out_data : std_logic_vector(out_w - 1 downto 0) := (others => '0'); -- default set sosi.data to 0
+ -- default set sosi.data to 0
+ variable v_out_data : std_logic_vector(out_w - 1 downto 0) := (others => '0');
begin
v_src_out := snk_in;
v_src_out.data := (others => '0');
@@ -1406,10 +1505,12 @@ package body dp_stream_pkg is
v_src_out.im := (others => '0');
for i in 0 to nof_data - 1 loop
v_in_data := snk_in.data((i + 1) * in_w - 1 downto i * in_w);
- if data_representation = "UNSIGNED" then -- treat data as unsigned
+ -- treat data as unsigned
+ if data_representation = "UNSIGNED" then
v_out_data := RESIZE_UVEC(v_in_data, out_w);
else
- if data_representation = "SIGNED" then -- treat data as signed
+ -- treat data as signed
+ if data_representation = "SIGNED" then
v_out_data := RESIZE_SVEC(v_in_data, out_w);
else
-- treat data as complex
@@ -1467,7 +1568,8 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
+ -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is
begin
return src_out_arr(0);
end;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
index 103667575791b885ea6d707accd5dc6c04bcb535..86bd5f3ed9ef2f109669b4576b60ab58651ee0f0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
@@ -29,29 +29,39 @@ use dp_lib.dp_stream_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
- constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
- constant c_eth_empty_w : natural := c_tech_tse_empty_w; -- = ceil_log2(c_word_sz) = 2;
- constant c_eth_error_w : natural := c_tech_tse_error_w; -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
-
- constant c_eth_rx_ready_latency : natural := c_tech_tse_rx_ready_latency; -- = 2 = default when FIFO is used
- constant c_eth_tx_ready_latency : natural := c_tech_tse_tx_ready_latency; -- = 0, c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
- constant c_eth_ready_latency : natural := 1; -- = 1, fixed ETH module internal RL
+ -- = c_word_w
+ constant c_eth_data_w : natural := c_tech_tse_data_w;
+ -- = ceil_log2(c_word_sz) = 2;
+ constant c_eth_empty_w : natural := c_tech_tse_empty_w;
+ -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
+ constant c_eth_error_w : natural := c_tech_tse_error_w;
+
+ -- = 2 = default when FIFO is used
+ constant c_eth_rx_ready_latency : natural := c_tech_tse_rx_ready_latency;
+ -- = 0, c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
+ constant c_eth_tx_ready_latency : natural := c_tech_tse_tx_ready_latency;
+ -- = 1, fixed ETH module internal RL
+ constant c_eth_ready_latency : natural := 1;
-- Maximum feasible frame size
- constant c_eth_max_frame_sz : natural := 1024 * 9; -- 9 kByte fits 9020 = word align (2) + eth header (14) + maximum jumbo payload (9000) + CRC (4)
+ -- 9 kByte fits 9020 = word align (2) + eth header (14) + maximum jumbo payload (9000) + CRC (4)
+ constant c_eth_max_frame_sz : natural := 1024 * 9;
constant c_eth_max_frame_nof_words : natural := c_eth_max_frame_sz / c_word_sz;
- constant c_eth_max_frame_nof_words_w : natural := ceil_log2(c_eth_max_frame_nof_words); -- = 12 bit
+ -- = 12 bit
+ constant c_eth_max_frame_nof_words_w : natural := ceil_log2(c_eth_max_frame_nof_words);
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
-- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
- constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
+ -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
+ constant c_eth_frame_sz : natural := 1024 * 2;
-- when the module is used in an Nios II SOPC system
-- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
- constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
+ -- >= 9 bit, <= 12 bit
+ constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words);
type t_eth_data_arr is array (integer range <>) of std_logic_vector(c_eth_data_w - 1 downto 0);
@@ -79,8 +89,10 @@ package eth_pkg is
-- Definitions for eth demux udp
------------------------------------------------------------------------------
- constant c_eth_nof_udp_ports : natural := 4; -- support 2, 4, 8, ... UDP off-load ports
- constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1); -- + 1 for all other packets that go to the default port
+ -- support 2, 4, 8, ... UDP off-load ports
+ constant c_eth_nof_udp_ports : natural := 4;
+ -- + 1 for all other packets that go to the default port
+ constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1);
constant c_eth_nof_channels : natural := 2**c_eth_channel_w;
------------------------------------------------------------------------------
@@ -103,30 +115,46 @@ package eth_pkg is
-- . write/read back registers
type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
type t_eth_mm_reg_demux is record
- udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
- udp_ports : t_eth_demux_ports_arr; -- [15:0]
+ -- [16]
+ udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports);
+ -- [15:0]
+ udp_ports : t_eth_demux_ports_arr;
end record;
type t_eth_mm_reg_config is record
- udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- [15:0]
- ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- [31:0]
- mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- [15:0], [31:0]
+ -- [15:0]
+ udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- [31:0]
+ ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- [15:0], [31:0]
+ mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
end record;
type t_eth_mm_reg_control is record
- tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_request : std_logic; -- 1 bit
- tx_en : std_logic; -- 1 bit
- rx_en : std_logic; -- 1 bit
+ -- 12 bit
+ tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0);
+ -- 2 bit
+ tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0);
+ -- 1 bit
+ tx_request : std_logic;
+ -- 1 bit
+ tx_en : std_logic;
+ -- 1 bit
+ rx_en : std_logic;
end record;
- type t_eth_mm_reg_control_bi is record -- bit indices
- tx_nof_words : natural; -- [26:18]
- tx_empty : natural; -- [17:16]
- tx_request : natural; -- [2]
- tx_en : natural; -- [1]
- rx_en : natural; -- [0]
+ -- bit indices
+ type t_eth_mm_reg_control_bi is record
+ -- [26:18]
+ tx_nof_words : natural;
+ -- [17:16]
+ tx_empty : natural;
+ -- [2]
+ tx_request : natural;
+ -- [1]
+ tx_en : natural;
+ -- [0]
+ rx_en : natural;
end record;
constant c_eth_mm_reg_control_bi : t_eth_mm_reg_control_bi := (18, 16, 2, 1, 0);
@@ -146,36 +174,58 @@ package eth_pkg is
eth_mac_error : std_logic_vector(c_eth_error_w - 1 downto 0);
end record;
- type t_eth_mm_reg_frame_bi is record -- bit indices
- is_dhcp : natural; -- [15]
- is_udp_ctrl_port : natural; -- [14]
- is_udp : natural; -- [13]
- is_icmp : natural; -- [12]
- ip_address_match : natural; -- [11]
- ip_checksum_is_ok : natural; -- [10]
- is_ip : natural; -- [9]
- is_arp : natural; -- [8]
- mac_address_match : natural; -- [7]
- eth_mac_error : natural; -- [6] not used, [5:0] = TSE MAC error
+ -- bit indices
+ type t_eth_mm_reg_frame_bi is record
+ -- [15]
+ is_dhcp : natural;
+ -- [14]
+ is_udp_ctrl_port : natural;
+ -- [13]
+ is_udp : natural;
+ -- [12]
+ is_icmp : natural;
+ -- [11]
+ ip_address_match : natural;
+ -- [10]
+ ip_checksum_is_ok : natural;
+ -- [9]
+ is_ip : natural;
+ -- [8]
+ is_arp : natural;
+ -- [7]
+ mac_address_match : natural;
+ -- [6] not used, [5:0] = TSE MAC error
+ eth_mac_error : natural;
end record;
constant c_eth_mm_reg_frame_bi : t_eth_mm_reg_frame_bi := (15, 14, 13, 12, 11, 10, 9, 8, 7, 0);
constant c_eth_mm_reg_frame_rst : t_eth_mm_reg_frame := ('0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'));
type t_eth_mm_reg_status is record
- rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_avail : std_logic; -- 1 bit
- tx_done : std_logic; -- 1 bit
- rx_avail : std_logic; -- 1 bit
+ -- 12 bit
+ rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0);
+ -- 2 bit
+ rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0);
+ -- 1 bit
+ tx_avail : std_logic;
+ -- 1 bit
+ tx_done : std_logic;
+ -- 1 bit
+ rx_avail : std_logic;
end record;
- type t_eth_mm_reg_status_bi is record -- bit indices
- rx_nof_words : natural; -- [26:18]
- rx_empty : natural; -- [17:16]
- tx_avail : natural; -- [2]
- tx_done : natural; -- [1]
- rx_avail : natural; -- [0]
+ -- bit indices
+ type t_eth_mm_reg_status_bi is record
+ -- [26:18]
+ rx_nof_words : natural;
+ -- [17:16]
+ rx_empty : natural;
+ -- [2]
+ tx_avail : natural;
+ -- [1]
+ tx_done : natural;
+ -- [0]
+ rx_avail : natural;
end record;
constant c_eth_mm_reg_status_bi : t_eth_mm_reg_status_bi := (18, 16, 2, 1, 0);
@@ -202,7 +252,8 @@ package eth_pkg is
c_eth_reg_control_nof_words +
c_eth_reg_frame_nof_words +
c_eth_reg_status_nof_words;
- constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
+ -- + 1 for c_eth_continue_wi
+ constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1);
------------------------------------------------------------------------------
-- Definitions for ETH Rx packet buffer and Tx packet buffer
@@ -223,8 +274,10 @@ package body eth_pkg is
begin
-- Demux UDP MM registers
for I in 1 to c_eth_nof_udp_ports loop
- v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w); -- [16] = UDP port enable
- v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w); -- [15:0] = UDP port number
+ -- [16] = UDP port enable
+ v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w);
+ -- [15:0] = UDP port number
+ v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w);
end loop;
return v_reg;
@@ -233,10 +286,13 @@ package body eth_pkg is
function func_eth_mm_reg_demux(mm_reg : t_eth_mm_reg_demux) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_demux_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
+ -- rsvd
+ v_reg := (others => '0');
for I in 1 to c_eth_nof_udp_ports loop
- v_reg(c_network_udp_port_w + (I - 1) * c_word_w) := mm_reg.udp_ports_en(I); -- [16] = UDP port enable
- v_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w) := mm_reg.udp_ports(I); -- [15:0] = UDP port number
+ -- [16] = UDP port enable
+ v_reg(c_network_udp_port_w + (I - 1) * c_word_w) := mm_reg.udp_ports_en(I);
+ -- [15:0] = UDP port number
+ v_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w) := mm_reg.udp_ports(I);
end loop;
return v_reg;
end func_eth_mm_reg_demux;
@@ -245,21 +301,30 @@ package body eth_pkg is
function func_eth_mm_reg_config(mm_reg : std_logic_vector) return t_eth_mm_reg_config is
variable v_reg : t_eth_mm_reg_config;
begin
- v_reg.udp_port := mm_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w); -- [15:0] = control UDP port number
- v_reg.ip_address := mm_reg( 3 * c_word_w - 1 downto 2 * c_word_w); -- [31:0] = this node IP address
- v_reg.mac_address(47 downto 32) := mm_reg( c_halfword_w + c_word_w - 1 downto c_word_w); -- [47:32] = this node MAC address
- v_reg.mac_address(31 downto 0) := mm_reg( c_word_w - 1 downto 0); -- [31:0] = this node MAC address
+ -- [15:0] = control UDP port number
+ v_reg.udp_port := mm_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w);
+ -- [31:0] = this node IP address
+ v_reg.ip_address := mm_reg( 3 * c_word_w - 1 downto 2 * c_word_w);
+ -- [47:32] = this node MAC address
+ v_reg.mac_address(47 downto 32) := mm_reg( c_halfword_w + c_word_w - 1 downto c_word_w);
+ -- [31:0] = this node MAC address
+ v_reg.mac_address(31 downto 0) := mm_reg( c_word_w - 1 downto 0);
return v_reg;
end func_eth_mm_reg_config;
function func_eth_mm_reg_config(mm_reg : t_eth_mm_reg_config) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_config_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w) := mm_reg.udp_port; -- [15:0] = control UDP port number
- v_reg( 3 * c_word_w - 1 downto 2 * c_word_w) := mm_reg.ip_address; -- [31:0] = this node IP address
- v_reg( c_halfword_w + c_word_w - 1 downto c_word_w) := mm_reg.mac_address(47 downto 32); -- [47:32] = this node MAC address
- v_reg( c_word_w - 1 downto 0) := mm_reg.mac_address(31 downto 0); -- [31:0] = this node MAC address
+ -- rsvd
+ v_reg := (others => '0');
+ -- [15:0] = control UDP port number
+ v_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w) := mm_reg.udp_port;
+ -- [31:0] = this node IP address
+ v_reg( 3 * c_word_w - 1 downto 2 * c_word_w) := mm_reg.ip_address;
+ -- [47:32] = this node MAC address
+ v_reg( c_halfword_w + c_word_w - 1 downto c_word_w) := mm_reg.mac_address(47 downto 32);
+ -- [31:0] = this node MAC address
+ v_reg( c_word_w - 1 downto 0) := mm_reg.mac_address(31 downto 0);
return v_reg;
end func_eth_mm_reg_config;
@@ -267,23 +332,34 @@ package body eth_pkg is
function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control is
variable v_reg : t_eth_mm_reg_control;
begin
- v_reg.tx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
- v_reg.tx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16); -- [17:16]
- v_reg.tx_request := mm_reg( 2); -- [2]
- v_reg.tx_en := mm_reg( 1); -- [1]
- v_reg.rx_en := mm_reg( 0); -- [0]
+ -- [29:18]
+ v_reg.tx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16);
+ -- [17:16]
+ v_reg.tx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16);
+ -- [2]
+ v_reg.tx_request := mm_reg( 2);
+ -- [1]
+ v_reg.tx_en := mm_reg( 1);
+ -- [0]
+ v_reg.rx_en := mm_reg( 0);
return v_reg;
end func_eth_mm_reg_control;
function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_control_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.tx_nof_words; -- [29:18]
- v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.tx_empty; -- [17:16]
- v_reg( 2) := mm_reg.tx_request; -- [2]
- v_reg( 1) := mm_reg.tx_en; -- [1]
- v_reg( 0) := mm_reg.rx_en; -- [0]
+ -- rsvd
+ v_reg := (others => '0');
+ -- [29:18]
+ v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.tx_nof_words;
+ -- [17:16]
+ v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.tx_empty;
+ -- [2]
+ v_reg( 2) := mm_reg.tx_request;
+ -- [1]
+ v_reg( 1) := mm_reg.tx_en;
+ -- [0]
+ v_reg( 0) := mm_reg.rx_en;
return v_reg;
end func_eth_mm_reg_control;
@@ -291,33 +367,54 @@ package body eth_pkg is
function func_eth_mm_reg_frame(mm_reg : std_logic_vector) return t_eth_mm_reg_frame is
variable v_reg : t_eth_mm_reg_frame;
begin
- v_reg.is_dhcp := mm_reg( c_byte_w + 7); -- [15]
- v_reg.is_udp_ctrl_port := mm_reg( c_byte_w + 6); -- [14]
- v_reg.is_udp := mm_reg( c_byte_w + 5); -- [13]
- v_reg.is_icmp := mm_reg( c_byte_w + 4); -- [12]
- v_reg.ip_address_match := mm_reg( c_byte_w + 3); -- [11]
- v_reg.ip_checksum_is_ok := mm_reg( c_byte_w + 2); -- [10]
- v_reg.is_ip := mm_reg( c_byte_w + 1); -- [9]
- v_reg.is_arp := mm_reg( c_byte_w + 0); -- [8]
- v_reg.mac_address_match := mm_reg( c_byte_w - 1); -- [7]
- v_reg.eth_mac_error := mm_reg(c_eth_error_w - 1 downto 0); -- [7] not used, [5:0] = TSE MAC error
+ -- [15]
+ v_reg.is_dhcp := mm_reg( c_byte_w + 7);
+ -- [14]
+ v_reg.is_udp_ctrl_port := mm_reg( c_byte_w + 6);
+ -- [13]
+ v_reg.is_udp := mm_reg( c_byte_w + 5);
+ -- [12]
+ v_reg.is_icmp := mm_reg( c_byte_w + 4);
+ -- [11]
+ v_reg.ip_address_match := mm_reg( c_byte_w + 3);
+ -- [10]
+ v_reg.ip_checksum_is_ok := mm_reg( c_byte_w + 2);
+ -- [9]
+ v_reg.is_ip := mm_reg( c_byte_w + 1);
+ -- [8]
+ v_reg.is_arp := mm_reg( c_byte_w + 0);
+ -- [7]
+ v_reg.mac_address_match := mm_reg( c_byte_w - 1);
+ -- [7] not used, [5:0] = TSE MAC error
+ v_reg.eth_mac_error := mm_reg(c_eth_error_w - 1 downto 0);
return v_reg;
end func_eth_mm_reg_frame;
function func_eth_mm_reg_frame(mm_reg : t_eth_mm_reg_frame) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_frame_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg( c_byte_w + 7) := mm_reg.is_dhcp; -- [15]
- v_reg( c_byte_w + 6) := mm_reg.is_udp_ctrl_port; -- [14]
- v_reg( c_byte_w + 5) := mm_reg.is_udp; -- [13]
- v_reg( c_byte_w + 4) := mm_reg.is_icmp; -- [12]
- v_reg( c_byte_w + 3) := mm_reg.ip_address_match; -- [11]
- v_reg( c_byte_w + 2) := mm_reg.ip_checksum_is_ok; -- [10]
- v_reg( c_byte_w + 1) := mm_reg.is_ip; -- [9]
- v_reg( c_byte_w + 0) := mm_reg.is_arp; -- [8]
- v_reg( c_byte_w - 1) := mm_reg.mac_address_match; -- [7]
- v_reg(c_eth_error_w - 1 downto 0) := mm_reg.eth_mac_error; -- [6] not used, [5:0] = TSE MAC error
+ -- rsvd
+ v_reg := (others => '0');
+ -- [15]
+ v_reg( c_byte_w + 7) := mm_reg.is_dhcp;
+ -- [14]
+ v_reg( c_byte_w + 6) := mm_reg.is_udp_ctrl_port;
+ -- [13]
+ v_reg( c_byte_w + 5) := mm_reg.is_udp;
+ -- [12]
+ v_reg( c_byte_w + 4) := mm_reg.is_icmp;
+ -- [11]
+ v_reg( c_byte_w + 3) := mm_reg.ip_address_match;
+ -- [10]
+ v_reg( c_byte_w + 2) := mm_reg.ip_checksum_is_ok;
+ -- [9]
+ v_reg( c_byte_w + 1) := mm_reg.is_ip;
+ -- [8]
+ v_reg( c_byte_w + 0) := mm_reg.is_arp;
+ -- [7]
+ v_reg( c_byte_w - 1) := mm_reg.mac_address_match;
+ -- [6] not used, [5:0] = TSE MAC error
+ v_reg(c_eth_error_w - 1 downto 0) := mm_reg.eth_mac_error;
return v_reg;
end func_eth_mm_reg_frame;
@@ -325,23 +422,34 @@ package body eth_pkg is
function func_eth_mm_reg_status(mm_reg : std_logic_vector) return t_eth_mm_reg_status is
variable v_reg : t_eth_mm_reg_status;
begin
- v_reg.rx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
- v_reg.rx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16); -- [17:16]
- v_reg.tx_avail := mm_reg( 2); -- [2]
- v_reg.tx_done := mm_reg( 1); -- [1]
- v_reg.rx_avail := mm_reg( 0); -- [0]
+ -- [29:18]
+ v_reg.rx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16);
+ -- [17:16]
+ v_reg.rx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16);
+ -- [2]
+ v_reg.tx_avail := mm_reg( 2);
+ -- [1]
+ v_reg.tx_done := mm_reg( 1);
+ -- [0]
+ v_reg.rx_avail := mm_reg( 0);
return v_reg;
end func_eth_mm_reg_status;
function func_eth_mm_reg_status(mm_reg : t_eth_mm_reg_status) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_status_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.rx_nof_words; -- [29:18]
- v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.rx_empty; -- [17:16]
- v_reg( 2) := mm_reg.tx_avail; -- [2]
- v_reg( 1) := mm_reg.tx_done; -- [1]
- v_reg( 0) := mm_reg.rx_avail; -- [0]
+ -- rsvd
+ v_reg := (others => '0');
+ -- [29:18]
+ v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.rx_nof_words;
+ -- [17:16]
+ v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.rx_empty;
+ -- [2]
+ v_reg( 2) := mm_reg.tx_avail;
+ -- [1]
+ v_reg( 1) := mm_reg.tx_done;
+ -- [0]
+ v_reg( 0) := mm_reg.rx_avail;
return v_reg;
end func_eth_mm_reg_status;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
index 177eb750c7386763043b7282d1bfb4b3a3fc6636..ada21504435ae1849069b8859e9aad66318061d1 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
@@ -25,19 +25,28 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
package tech_tse_pkg is
- constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
+ -- = max 256 MAC registers
+ constant c_tech_tse_reg_addr_w : natural := 8;
constant c_tech_tse_byte_addr_w : natural := c_tech_tse_reg_addr_w + 2;
- constant c_tech_tse_byte_addr_pcs_offset : natural := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
- constant c_tech_tse_data_w : natural := c_word_w; -- = 32
+ -- table 4.8, 4.9 in ug_ethernet.pdf
+ constant c_tech_tse_byte_addr_pcs_offset : natural := 16#200#;
+ -- = 32
+ constant c_tech_tse_data_w : natural := c_word_w;
- constant c_tech_tse_symbol_w : natural := c_byte_w; -- = 8
- constant c_tech_tse_symbol_max : natural := 2**c_tech_tse_symbol_w - 1; -- = 255
- constant c_tech_tse_symbols_per_beat : natural := c_tech_tse_data_w / c_tech_tse_symbol_w; -- = 4
+ -- = 8
+ constant c_tech_tse_symbol_w : natural := c_byte_w;
+ -- = 255
+ constant c_tech_tse_symbol_max : natural := 2**c_tech_tse_symbol_w - 1;
+ -- = 4
+ constant c_tech_tse_symbols_per_beat : natural := c_tech_tse_data_w / c_tech_tse_symbol_w;
- constant c_tech_tse_pcs_reg_addr_w : natural := 5; -- = max 32 PCS registers
- constant c_tech_tse_pcs_halfword_addr_w : natural := c_tech_tse_pcs_reg_addr_w + 1; -- table 4.17 in ug_ethernet.pdf
+ -- = max 32 PCS registers
+ constant c_tech_tse_pcs_reg_addr_w : natural := 5;
+ -- table 4.17 in ug_ethernet.pdf
+ constant c_tech_tse_pcs_halfword_addr_w : natural := c_tech_tse_pcs_reg_addr_w + 1;
constant c_tech_tse_pcs_byte_addr_w : natural := c_tech_tse_pcs_reg_addr_w + 2;
- constant c_tech_tse_pcs_data_w : natural := c_halfword_w; -- = 16;
+ -- = 16;
+ constant c_tech_tse_pcs_data_w : natural := c_halfword_w;
constant c_tech_tse_empty_w : natural := 2;
constant c_tech_tse_tx_error_w : natural := 1;
@@ -46,11 +55,15 @@ package tech_tse_pkg is
constant c_tech_tse_err_stat_w : natural := 18;
constant c_tech_tse_frm_type_w : natural := 4;
- constant c_tech_tse_rx_ready_latency : natural := 2; -- 2 = default when FIFO is used
- constant c_tech_tse_tx_ready_latency : natural := 1; -- c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
+ -- 2 = default when FIFO is used
+ constant c_tech_tse_rx_ready_latency : natural := 2;
+ -- c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
+ constant c_tech_tse_tx_ready_latency : natural := 1;
- constant c_tech_tse_tx_fifo_depth : natural := 256; -- nof words for Tx FIFO
- constant c_tech_tse_rx_fifo_depth : natural := 256; -- nof words for Rx FIFO
+ -- nof words for Tx FIFO
+ constant c_tech_tse_tx_fifo_depth : natural := 256;
+ -- nof words for Rx FIFO
+ constant c_tech_tse_rx_fifo_depth : natural := 256;
type t_tech_tse_tx_mac is record
-- Tx MAC inputs
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
index 06df7d37f4b4ceeb07d517f45c42b0cfa1cac3f2..9a85eb333d9be54b8cf2161d1fc1162280487fd2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
@@ -1,84 +1,160 @@
component qsys_unb2b_minimal_avs_eth_0 is
port (
- coe_clk_export : out std_logic; -- export
- ins_interrupt_irq : out std_logic; -- irq
- coe_irq_export : in std_logic := 'X'; -- export
- csi_mm_clk : in std_logic := 'X'; -- clk
- csi_mm_reset : in std_logic := 'X'; -- reset
- mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_ram_write : in std_logic := 'X'; -- write
- mms_ram_read : in std_logic := 'X'; -- read
- mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_ram_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
- mms_reg_write : in std_logic := 'X'; -- write
- mms_reg_read : in std_logic := 'X'; -- read
- mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_reg_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_tse_write : in std_logic := 'X'; -- write
- mms_tse_read : in std_logic := 'X'; -- read
- mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_tse_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_waitrequest : out std_logic; -- waitrequest
- coe_ram_address_export : out std_logic_vector(9 downto 0); -- export
- coe_ram_read_export : out std_logic; -- export
- coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_write_export : out std_logic; -- export
- coe_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reg_address_export : out std_logic_vector(3 downto 0); -- export
- coe_reg_read_export : out std_logic; -- export
- coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reg_write_export : out std_logic; -- export
- coe_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reset_export : out std_logic; -- export
- coe_tse_address_export : out std_logic_vector(9 downto 0); -- export
- coe_tse_read_export : out std_logic; -- export
- coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_tse_waitrequest_export : in std_logic := 'X'; -- export
- coe_tse_write_export : out std_logic; -- export
- coe_tse_writedata_export : out std_logic_vector(31 downto 0) -- export
+ -- export
+ coe_clk_export : out std_logic;
+ -- irq
+ ins_interrupt_irq : out std_logic;
+ -- export
+ coe_irq_export : in std_logic := 'X';
+ -- clk
+ csi_mm_clk : in std_logic := 'X';
+ -- reset
+ csi_mm_reset : in std_logic := 'X';
+ -- address
+ mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X');
+ -- write
+ mms_ram_write : in std_logic := 'X';
+ -- read
+ mms_ram_read : in std_logic := 'X';
+ -- writedata
+ mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- readdata
+ mms_ram_readdata : out std_logic_vector(31 downto 0);
+ -- address
+ mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- write
+ mms_reg_write : in std_logic := 'X';
+ -- read
+ mms_reg_read : in std_logic := 'X';
+ -- writedata
+ mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- readdata
+ mms_reg_readdata : out std_logic_vector(31 downto 0);
+ -- address
+ mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X');
+ -- write
+ mms_tse_write : in std_logic := 'X';
+ -- read
+ mms_tse_read : in std_logic := 'X';
+ -- writedata
+ mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- readdata
+ mms_tse_readdata : out std_logic_vector(31 downto 0);
+ -- waitrequest
+ mms_tse_waitrequest : out std_logic;
+ -- export
+ coe_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ coe_ram_read_export : out std_logic;
+ -- export
+ coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_ram_write_export : out std_logic;
+ -- export
+ coe_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ coe_reg_read_export : out std_logic;
+ -- export
+ coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_reg_write_export : out std_logic;
+ -- export
+ coe_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reset_export : out std_logic;
+ -- export
+ coe_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ coe_tse_read_export : out std_logic;
+ -- export
+ coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ coe_tse_write_export : out std_logic;
+ -- export
+ coe_tse_writedata_export : out std_logic_vector(31 downto 0)
);
end component qsys_unb2b_minimal_avs_eth_0;
u0 : component qsys_unb2b_minimal_avs_eth_0
port map (
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq, -- interrupt.irq
- coe_irq_export => CONNECTED_TO_coe_irq_export, -- irq.export
- csi_mm_clk => CONNECTED_TO_csi_mm_clk, -- mm.clk
- csi_mm_reset => CONNECTED_TO_csi_mm_reset, -- mm_reset.reset
- mms_ram_address => CONNECTED_TO_mms_ram_address, -- mms_ram.address
- mms_ram_write => CONNECTED_TO_mms_ram_write, -- .write
- mms_ram_read => CONNECTED_TO_mms_ram_read, -- .read
- mms_ram_writedata => CONNECTED_TO_mms_ram_writedata, -- .writedata
- mms_ram_readdata => CONNECTED_TO_mms_ram_readdata, -- .readdata
- mms_reg_address => CONNECTED_TO_mms_reg_address, -- mms_reg.address
- mms_reg_write => CONNECTED_TO_mms_reg_write, -- .write
- mms_reg_read => CONNECTED_TO_mms_reg_read, -- .read
- mms_reg_writedata => CONNECTED_TO_mms_reg_writedata, -- .writedata
- mms_reg_readdata => CONNECTED_TO_mms_reg_readdata, -- .readdata
- mms_tse_address => CONNECTED_TO_mms_tse_address, -- mms_tse.address
- mms_tse_write => CONNECTED_TO_mms_tse_write, -- .write
- mms_tse_read => CONNECTED_TO_mms_tse_read, -- .read
- mms_tse_writedata => CONNECTED_TO_mms_tse_writedata, -- .writedata
- mms_tse_readdata => CONNECTED_TO_mms_tse_readdata, -- .readdata
- mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest, -- .waitrequest
- coe_ram_address_export => CONNECTED_TO_coe_ram_address_export, -- ram_address.export
- coe_ram_read_export => CONNECTED_TO_coe_ram_read_export, -- ram_read.export
- coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export, -- ram_readdata.export
- coe_ram_write_export => CONNECTED_TO_coe_ram_write_export, -- ram_write.export
- coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export, -- ram_writedata.export
- coe_reg_address_export => CONNECTED_TO_coe_reg_address_export, -- reg_address.export
- coe_reg_read_export => CONNECTED_TO_coe_reg_read_export, -- reg_read.export
- coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export, -- reg_readdata.export
- coe_reg_write_export => CONNECTED_TO_coe_reg_write_export, -- reg_write.export
- coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export, -- reg_writedata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- coe_tse_address_export => CONNECTED_TO_coe_tse_address_export, -- tse_address.export
- coe_tse_read_export => CONNECTED_TO_coe_tse_read_export, -- tse_read.export
- coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export, -- tse_readdata.export
- coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
- coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
- coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- interrupt.irq
+ ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq,
+ -- irq.export
+ coe_irq_export => CONNECTED_TO_coe_irq_export,
+ -- mm.clk
+ csi_mm_clk => CONNECTED_TO_csi_mm_clk,
+ -- mm_reset.reset
+ csi_mm_reset => CONNECTED_TO_csi_mm_reset,
+ -- mms_ram.address
+ mms_ram_address => CONNECTED_TO_mms_ram_address,
+ -- .write
+ mms_ram_write => CONNECTED_TO_mms_ram_write,
+ -- .read
+ mms_ram_read => CONNECTED_TO_mms_ram_read,
+ -- .writedata
+ mms_ram_writedata => CONNECTED_TO_mms_ram_writedata,
+ -- .readdata
+ mms_ram_readdata => CONNECTED_TO_mms_ram_readdata,
+ -- mms_reg.address
+ mms_reg_address => CONNECTED_TO_mms_reg_address,
+ -- .write
+ mms_reg_write => CONNECTED_TO_mms_reg_write,
+ -- .read
+ mms_reg_read => CONNECTED_TO_mms_reg_read,
+ -- .writedata
+ mms_reg_writedata => CONNECTED_TO_mms_reg_writedata,
+ -- .readdata
+ mms_reg_readdata => CONNECTED_TO_mms_reg_readdata,
+ -- mms_tse.address
+ mms_tse_address => CONNECTED_TO_mms_tse_address,
+ -- .write
+ mms_tse_write => CONNECTED_TO_mms_tse_write,
+ -- .read
+ mms_tse_read => CONNECTED_TO_mms_tse_read,
+ -- .writedata
+ mms_tse_writedata => CONNECTED_TO_mms_tse_writedata,
+ -- .readdata
+ mms_tse_readdata => CONNECTED_TO_mms_tse_readdata,
+ -- .waitrequest
+ mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest,
+ -- ram_address.export
+ coe_ram_address_export => CONNECTED_TO_coe_ram_address_export,
+ -- ram_read.export
+ coe_ram_read_export => CONNECTED_TO_coe_ram_read_export,
+ -- ram_readdata.export
+ coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export,
+ -- ram_write.export
+ coe_ram_write_export => CONNECTED_TO_coe_ram_write_export,
+ -- ram_writedata.export
+ coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export,
+ -- reg_address.export
+ coe_reg_address_export => CONNECTED_TO_coe_reg_address_export,
+ -- reg_read.export
+ coe_reg_read_export => CONNECTED_TO_coe_reg_read_export,
+ -- reg_readdata.export
+ coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export,
+ -- reg_write.export
+ coe_reg_write_export => CONNECTED_TO_coe_reg_write_export,
+ -- reg_writedata.export
+ coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- tse_address.export
+ coe_tse_address_export => CONNECTED_TO_coe_tse_address_export,
+ -- tse_read.export
+ coe_tse_read_export => CONNECTED_TO_coe_tse_read_export,
+ -- tse_readdata.export
+ coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export,
+ -- tse_waitrequest.export
+ coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export,
+ -- tse_write.export
+ coe_tse_write_export => CONNECTED_TO_coe_tse_write_export,
+ -- tse_writedata.export
+ coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
index fafd41bbfa80eae91afc0da3d18e2f4b799f6a95..7a1137fb1ee7d1624d7bb3f6d2fe54ed91502252 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
@@ -1,16 +1,24 @@
component qsys_unb2b_minimal_clk_0 is
port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
+ -- clk
+ clk_out : out std_logic;
+ -- clk
+ in_clk : in std_logic := 'X';
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- reset_n
+ reset_n_out : out std_logic
);
end component qsys_unb2b_minimal_clk_0;
u0 : component qsys_unb2b_minimal_clk_0
port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ -- clk.clk
+ clk_out => CONNECTED_TO_clk_out,
+ -- clk_in.clk
+ in_clk => CONNECTED_TO_in_clk,
+ -- clk_in_reset.reset_n
+ reset_n => CONNECTED_TO_reset_n,
+ -- clk_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
index 38fce9676fd1136ba002d70216e0ae804269cd9f..ce3af1016d3b93cea26457f43df6edd09734e79d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
@@ -1,60 +1,112 @@
component qsys_unb2b_minimal_cpu_0 is
port (
- clk : in std_logic := 'X'; -- clk
- dummy_ci_port : out std_logic; -- readra
- d_address : out std_logic_vector(19 downto 0); -- address
- d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
- d_read : out std_logic; -- read
- d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- d_waitrequest : in std_logic := 'X'; -- waitrequest
- d_write : out std_logic; -- write
- d_writedata : out std_logic_vector(31 downto 0); -- writedata
- debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
- debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
- debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
- debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
- debug_mem_slave_read : in std_logic := 'X'; -- read
- debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
- debug_mem_slave_waitrequest : out std_logic; -- waitrequest
- debug_mem_slave_write : in std_logic := 'X'; -- write
- debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- debug_reset_request : out std_logic; -- reset
- i_address : out std_logic_vector(17 downto 0); -- address
- i_read : out std_logic; -- read
- i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- i_waitrequest : in std_logic := 'X'; -- waitrequest
- irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- reset_req : in std_logic := 'X' -- reset_req
+ -- clk
+ clk : in std_logic := 'X';
+ -- readra
+ dummy_ci_port : out std_logic;
+ -- address
+ d_address : out std_logic_vector(19 downto 0);
+ -- byteenable
+ d_byteenable : out std_logic_vector(3 downto 0);
+ -- read
+ d_read : out std_logic;
+ -- readdata
+ d_readdata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- waitrequest
+ d_waitrequest : in std_logic := 'X';
+ -- write
+ d_write : out std_logic;
+ -- writedata
+ d_writedata : out std_logic_vector(31 downto 0);
+ -- debugaccess
+ debug_mem_slave_debugaccess_to_roms : out std_logic;
+ -- address
+ debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X');
+ -- byteenable
+ debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- debugaccess
+ debug_mem_slave_debugaccess : in std_logic := 'X';
+ -- read
+ debug_mem_slave_read : in std_logic := 'X';
+ -- readdata
+ debug_mem_slave_readdata : out std_logic_vector(31 downto 0);
+ -- waitrequest
+ debug_mem_slave_waitrequest : out std_logic;
+ -- write
+ debug_mem_slave_write : in std_logic := 'X';
+ -- writedata
+ debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- reset
+ debug_reset_request : out std_logic;
+ -- address
+ i_address : out std_logic_vector(17 downto 0);
+ -- read
+ i_read : out std_logic;
+ -- readdata
+ i_readdata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- waitrequest
+ i_waitrequest : in std_logic := 'X';
+ -- irq
+ irq : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- reset_req
+ reset_req : in std_logic := 'X'
);
end component qsys_unb2b_minimal_cpu_0;
u0 : component qsys_unb2b_minimal_cpu_0
port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
- d_address => CONNECTED_TO_d_address, -- data_master.address
- d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
- d_read => CONNECTED_TO_d_read, -- .read
- d_readdata => CONNECTED_TO_d_readdata, -- .readdata
- d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
- d_write => CONNECTED_TO_d_write, -- .write
- d_writedata => CONNECTED_TO_d_writedata, -- .writedata
- debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
- debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
- debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
- debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
- debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
- debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
- debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
- debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
- debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
- debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
- i_address => CONNECTED_TO_i_address, -- instruction_master.address
- i_read => CONNECTED_TO_i_read, -- .read
- i_readdata => CONNECTED_TO_i_readdata, -- .readdata
- i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- reset_req => CONNECTED_TO_reset_req -- .reset_req
+ -- clk.clk
+ clk => CONNECTED_TO_clk,
+ -- custom_instruction_master.readra
+ dummy_ci_port => CONNECTED_TO_dummy_ci_port,
+ -- data_master.address
+ d_address => CONNECTED_TO_d_address,
+ -- .byteenable
+ d_byteenable => CONNECTED_TO_d_byteenable,
+ -- .read
+ d_read => CONNECTED_TO_d_read,
+ -- .readdata
+ d_readdata => CONNECTED_TO_d_readdata,
+ -- .waitrequest
+ d_waitrequest => CONNECTED_TO_d_waitrequest,
+ -- .write
+ d_write => CONNECTED_TO_d_write,
+ -- .writedata
+ d_writedata => CONNECTED_TO_d_writedata,
+ -- .debugaccess
+ debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms,
+ -- debug_mem_slave.address
+ debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address,
+ -- .byteenable
+ debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable,
+ -- .debugaccess
+ debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess,
+ -- .read
+ debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read,
+ -- .readdata
+ debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata,
+ -- .waitrequest
+ debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest,
+ -- .write
+ debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write,
+ -- .writedata
+ debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata,
+ -- debug_reset_request.reset
+ debug_reset_request => CONNECTED_TO_debug_reset_request,
+ -- instruction_master.address
+ i_address => CONNECTED_TO_i_address,
+ -- .read
+ i_read => CONNECTED_TO_i_read,
+ -- .readdata
+ i_readdata => CONNECTED_TO_i_readdata,
+ -- .waitrequest
+ i_waitrequest => CONNECTED_TO_i_waitrequest,
+ -- irq.irq
+ irq => CONNECTED_TO_irq,
+ -- reset.reset_n
+ reset_n => CONNECTED_TO_reset_n,
+ -- .reset_req
+ reset_req => CONNECTED_TO_reset_req
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
index c76f427acbe4d282fd1db94d2af4ffdce37d9027..7907cbe1445b3078ee1487926d59879c64d018cc 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
@@ -1,100 +1,192 @@
component qsys_unb2b_minimal_jesd204 is
port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
+ -- export
+ alldev_lane_aligned : in std_logic := 'X';
+ -- export
+ csr_cf : out std_logic_vector(4 downto 0);
+ -- export
+ csr_cs : out std_logic_vector(1 downto 0);
+ -- export
+ csr_f : out std_logic_vector(7 downto 0);
+ -- export
+ csr_hd : out std_logic;
+ -- export
+ csr_k : out std_logic_vector(4 downto 0);
+ -- export
+ csr_l : out std_logic_vector(4 downto 0);
+ -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0);
+ -- export
+ csr_m : out std_logic_vector(7 downto 0);
+ -- export
+ csr_n : out std_logic_vector(4 downto 0);
+ -- export
+ csr_np : out std_logic_vector(4 downto 0);
+ -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0);
+ -- export
+ csr_s : out std_logic_vector(4 downto 0);
+ -- export
+ dev_lane_aligned : out std_logic;
+ -- export
+ dev_sync_n : out std_logic;
+ -- chipselect
+ jesd204_rx_avs_chipselect : in std_logic := 'X';
+ -- address
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X');
+ -- read
+ jesd204_rx_avs_read : in std_logic := 'X';
+ -- readdata
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0);
+ -- waitrequest
+ jesd204_rx_avs_waitrequest : out std_logic;
+ -- write
+ jesd204_rx_avs_write : in std_logic := 'X';
+ -- writedata
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- clk
+ jesd204_rx_avs_clk : in std_logic := 'X';
+ -- reset_n
+ jesd204_rx_avs_rst_n : in std_logic := 'X';
+ -- export
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_frame_error : in std_logic := 'X';
+ -- irq
+ jesd204_rx_int : out std_logic;
+ -- data
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0);
+ -- valid
+ jesd204_rx_link_valid : out std_logic;
+ -- ready
+ jesd204_rx_link_ready : in std_logic := 'X';
+ -- clk
+ pll_ref_clk : in std_logic := 'X';
+ -- rx_analogreset
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_cal_busy
+ rx_cal_busy : out std_logic_vector(0 downto 0);
+ -- rx_digitalreset
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_is_lockedtodata
+ rx_islockedtodata : out std_logic_vector(0 downto 0);
+ -- rx_serial_data
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- clk
+ rxlink_clk : in std_logic := 'X';
+ -- reset_n
+ rxlink_rst_n_reset_n : in std_logic := 'X';
+ -- export
+ rxphy_clk : out std_logic_vector(0 downto 0);
+ -- export
+ sof : out std_logic_vector(3 downto 0);
+ -- export
+ somf : out std_logic_vector(3 downto 0);
+ -- export
+ sysref : in std_logic := 'X'
);
end component qsys_unb2b_minimal_jesd204;
u0 : component qsys_unb2b_minimal_jesd204
port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
+ -- alldev_lane_aligned.export
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned,
+ -- csr_cf.export
+ csr_cf => CONNECTED_TO_csr_cf,
+ -- csr_cs.export
+ csr_cs => CONNECTED_TO_csr_cs,
+ -- csr_f.export
+ csr_f => CONNECTED_TO_csr_f,
+ -- csr_hd.export
+ csr_hd => CONNECTED_TO_csr_hd,
+ -- csr_k.export
+ csr_k => CONNECTED_TO_csr_k,
+ -- csr_l.export
+ csr_l => CONNECTED_TO_csr_l,
+ -- csr_lane_powerdown.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown,
+ -- csr_m.export
+ csr_m => CONNECTED_TO_csr_m,
+ -- csr_n.export
+ csr_n => CONNECTED_TO_csr_n,
+ -- csr_np.export
+ csr_np => CONNECTED_TO_csr_np,
+ -- csr_rx_testmode.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode,
+ -- csr_s.export
+ csr_s => CONNECTED_TO_csr_s,
+ -- dev_lane_aligned.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned,
+ -- dev_sync_n.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n,
+ -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect,
+ -- .address
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address,
+ -- .read
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read,
+ -- .readdata
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata,
+ -- .waitrequest
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest,
+ -- .write
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write,
+ -- .writedata
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata,
+ -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk,
+ -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n,
+ -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data,
+ -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid,
+ -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr,
+ -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect,
+ -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data,
+ -- jesd204_rx_frame_error.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error,
+ -- jesd204_rx_int.irq
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int,
+ -- jesd204_rx_link.data
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data,
+ -- .valid
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid,
+ -- .ready
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready,
+ -- pll_ref_clk.clk
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk,
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset => CONNECTED_TO_rx_analogreset,
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy,
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset,
+ -- rx_islockedtodata.rx_is_lockedtodata
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata,
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data => CONNECTED_TO_rx_serial_data,
+ -- rxlink_clk.clk
+ rxlink_clk => CONNECTED_TO_rxlink_clk,
+ -- rxlink_rst_n.reset_n
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n,
+ -- rxphy_clk.export
+ rxphy_clk => CONNECTED_TO_rxphy_clk,
+ -- sof.export
+ sof => CONNECTED_TO_sof,
+ -- somf.export
+ somf => CONNECTED_TO_somf,
+ -- sysref.export
+ sysref => CONNECTED_TO_sysref
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
index bc11c57e416cd6de852d448d82730d0e93d92791..49260e639cf8400d7bd28a33c4095c6a5ce39014 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
@@ -1,28 +1,48 @@
component qsys_unb2b_minimal_jtag_uart_0 is
port (
- av_chipselect : in std_logic := 'X'; -- chipselect
- av_address : in std_logic := 'X'; -- address
- av_read_n : in std_logic := 'X'; -- read_n
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_write_n : in std_logic := 'X'; -- write_n
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_waitrequest : out std_logic; -- waitrequest
- clk : in std_logic := 'X'; -- clk
- av_irq : out std_logic; -- irq
- rst_n : in std_logic := 'X' -- reset_n
+ -- chipselect
+ av_chipselect : in std_logic := 'X';
+ -- address
+ av_address : in std_logic := 'X';
+ -- read_n
+ av_read_n : in std_logic := 'X';
+ -- readdata
+ av_readdata : out std_logic_vector(31 downto 0);
+ -- write_n
+ av_write_n : in std_logic := 'X';
+ -- writedata
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- waitrequest
+ av_waitrequest : out std_logic;
+ -- clk
+ clk : in std_logic := 'X';
+ -- irq
+ av_irq : out std_logic;
+ -- reset_n
+ rst_n : in std_logic := 'X'
);
end component qsys_unb2b_minimal_jtag_uart_0;
u0 : component qsys_unb2b_minimal_jtag_uart_0
port map (
- av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
- av_address => CONNECTED_TO_av_address, -- .address
- av_read_n => CONNECTED_TO_av_read_n, -- .read_n
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_write_n => CONNECTED_TO_av_write_n, -- .write_n
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
- clk => CONNECTED_TO_clk, -- clk.clk
- av_irq => CONNECTED_TO_av_irq, -- irq.irq
- rst_n => CONNECTED_TO_rst_n -- reset.reset_n
+ -- avalon_jtag_slave.chipselect
+ av_chipselect => CONNECTED_TO_av_chipselect,
+ -- .address
+ av_address => CONNECTED_TO_av_address,
+ -- .read_n
+ av_read_n => CONNECTED_TO_av_read_n,
+ -- .readdata
+ av_readdata => CONNECTED_TO_av_readdata,
+ -- .write_n
+ av_write_n => CONNECTED_TO_av_write_n,
+ -- .writedata
+ av_writedata => CONNECTED_TO_av_writedata,
+ -- .waitrequest
+ av_waitrequest => CONNECTED_TO_av_waitrequest,
+ -- clk.clk
+ clk => CONNECTED_TO_clk,
+ -- irq.irq
+ av_irq => CONNECTED_TO_av_irq,
+ -- reset.reset_n
+ rst_n => CONNECTED_TO_rst_n
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
index f453120efc4f037dc4efbc07b42a93186450fe1d..0f577a2f63cf1f10cd5a119d56b14c7162d3e2b6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
@@ -1,28 +1,48 @@
component qsys_unb2b_minimal_onchip_memory2_0 is
port (
- clk : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- reset_req : in std_logic := 'X'; -- reset_req
- address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
- clken : in std_logic := 'X'; -- clken
- chipselect : in std_logic := 'X'; -- chipselect
- write : in std_logic := 'X'; -- write
- readdata : out std_logic_vector(31 downto 0); -- readdata
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
+ -- clk
+ clk : in std_logic := 'X';
+ -- reset
+ reset : in std_logic := 'X';
+ -- reset_req
+ reset_req : in std_logic := 'X';
+ -- address
+ address : in std_logic_vector(14 downto 0) := (others => 'X');
+ -- clken
+ clken : in std_logic := 'X';
+ -- chipselect
+ chipselect : in std_logic := 'X';
+ -- write
+ write : in std_logic := 'X';
+ -- readdata
+ readdata : out std_logic_vector(31 downto 0);
+ -- writedata
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- byteenable
+ byteenable : in std_logic_vector(3 downto 0) := (others => 'X')
);
end component qsys_unb2b_minimal_onchip_memory2_0;
u0 : component qsys_unb2b_minimal_onchip_memory2_0
port map (
- clk => CONNECTED_TO_clk, -- clk1.clk
- reset => CONNECTED_TO_reset, -- reset1.reset
- reset_req => CONNECTED_TO_reset_req, -- .reset_req
- address => CONNECTED_TO_address, -- s1.address
- clken => CONNECTED_TO_clken, -- .clken
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write => CONNECTED_TO_write, -- .write
- readdata => CONNECTED_TO_readdata, -- .readdata
- writedata => CONNECTED_TO_writedata, -- .writedata
- byteenable => CONNECTED_TO_byteenable -- .byteenable
+ -- clk1.clk
+ clk => CONNECTED_TO_clk,
+ -- reset1.reset
+ reset => CONNECTED_TO_reset,
+ -- .reset_req
+ reset_req => CONNECTED_TO_reset_req,
+ -- s1.address
+ address => CONNECTED_TO_address,
+ -- .clken
+ clken => CONNECTED_TO_clken,
+ -- .chipselect
+ chipselect => CONNECTED_TO_chipselect,
+ -- .write
+ write => CONNECTED_TO_write,
+ -- .readdata
+ readdata => CONNECTED_TO_readdata,
+ -- .writedata
+ writedata => CONNECTED_TO_writedata,
+ -- .byteenable
+ byteenable => CONNECTED_TO_byteenable
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
index 580187433d6ad3516adc8f3613297cd106f122a7..b17847229b01e7609d4b13e411ef62fd233e2ed0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_pio_pps;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
index b05a01d44469adf2ce2a5524f755a45e93ee3b55..8469f7c897471d0d4920cde1932b898c48e2184d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_pio_system_info;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
index 4639e141f52b87b436009b6f01944420186ed973..2050a6446f527e4b71f2bde2a1e901b18c675eb2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
@@ -1,24 +1,40 @@
component qsys_unb2b_minimal_pio_wdi is
port (
- clk : in std_logic := 'X'; -- clk
- out_port : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
- write_n : in std_logic := 'X'; -- write_n
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- chipselect : in std_logic := 'X'; -- chipselect
- readdata : out std_logic_vector(31 downto 0) -- readdata
+ -- clk
+ clk : in std_logic := 'X';
+ -- export
+ out_port : out std_logic;
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- address
+ address : in std_logic_vector(1 downto 0) := (others => 'X');
+ -- write_n
+ write_n : in std_logic := 'X';
+ -- writedata
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- chipselect
+ chipselect : in std_logic := 'X';
+ -- readdata
+ readdata : out std_logic_vector(31 downto 0)
);
end component qsys_unb2b_minimal_pio_wdi;
u0 : component qsys_unb2b_minimal_pio_wdi
port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- out_port => CONNECTED_TO_out_port, -- external_connection.export
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- write_n => CONNECTED_TO_write_n, -- .write_n
- writedata => CONNECTED_TO_writedata, -- .writedata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- readdata => CONNECTED_TO_readdata -- .readdata
+ -- clk.clk
+ clk => CONNECTED_TO_clk,
+ -- external_connection.export
+ out_port => CONNECTED_TO_out_port,
+ -- reset.reset_n
+ reset_n => CONNECTED_TO_reset_n,
+ -- s1.address
+ address => CONNECTED_TO_address,
+ -- .write_n
+ write_n => CONNECTED_TO_write_n,
+ -- .writedata
+ writedata => CONNECTED_TO_writedata,
+ -- .chipselect
+ chipselect => CONNECTED_TO_chipselect,
+ -- .readdata
+ readdata => CONNECTED_TO_readdata
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
index ec324643910e8ec28eea3841bf69396535f66ce8..29a64f659bdd5af5c4e45fae32a972fd3b9fd5dd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_dpmm_ctrl;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
index 902a48132b9b35e040acf2ea2bdc5803e567864e..3000423c22e59f95864c1c781ec2fa66e62fd0d8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_dpmm_data;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
index b7e771b662f1b2279fb0a2605ad86648a3821987..e49bc2a4531e7e370ff87a9e5112af9e53ee2ff9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_epcs;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
index 170f85ed587a093a331bd7da8153feb63a78358e..3c1f1809bbdaa6e3afa7af959fb69426373759fb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_fpga_temp_sens;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
index 495dae0b21c808c2f09bc98a269f98a22332116b..81c18715bcc965231b82d775a1a2423a5afb8a96 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_fpga_voltage_sens;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
index e099a81cd1f19acfb178d8108c3a40c275935b38..b9ec3f8e7c9d49e1c05a2d665f8ebcb0205c6a79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_mmdp_ctrl;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
index d25eb92a9c789a0a393083008b9dd982889f184e..c8f66632ab44c2323d7c0468e41059aa650a33dc 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_mmdp_data;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
index 837cb45819d6d993ab0e2ec2cd835b1f69bd1365..63dd733e011f3fe35b43b76fc78de59ae9954141 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_remu;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
index b97ef222ecfeac9b9cdc0609f289add83696334d..9878fc8fdf4c00e8aa50404866ef33fb77037e80 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_unb_pmbus;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
index 1871be2f741a5f58a41c9f333411b3b210fec9e6..444d691a7c1fb9cb1365e67588d5b0bc603c05c4 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_unb_sens;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
index 229a2d315e14744572cd30efdc1e44a03cb55744..13883c7092de7b4039e337b9f927be8f063d9c44 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_wdi;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
index ae35f2bd1988023e11957c39257a521354f840f8..f4259cc612790dbe727994802a97a8c23dfdd834 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_rom_system_info;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
index ff04a90d2be254067a63715a1ab244263a405a8f..2f8c520e1f781d748592eb9785ceb3f7dae1c9e9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
@@ -1,24 +1,40 @@
component qsys_unb2b_minimal_timer_0 is
port (
- clk : in std_logic := 'X'; -- clk
- irq : out std_logic; -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
- writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
- readdata : out std_logic_vector(15 downto 0); -- readdata
- chipselect : in std_logic := 'X'; -- chipselect
- write_n : in std_logic := 'X' -- write_n
+ -- clk
+ clk : in std_logic := 'X';
+ -- irq
+ irq : out std_logic;
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- address
+ address : in std_logic_vector(2 downto 0) := (others => 'X');
+ -- writedata
+ writedata : in std_logic_vector(15 downto 0) := (others => 'X');
+ -- readdata
+ readdata : out std_logic_vector(15 downto 0);
+ -- chipselect
+ chipselect : in std_logic := 'X';
+ -- write_n
+ write_n : in std_logic := 'X'
);
end component qsys_unb2b_minimal_timer_0;
u0 : component qsys_unb2b_minimal_timer_0
port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- writedata => CONNECTED_TO_writedata, -- .writedata
- readdata => CONNECTED_TO_readdata, -- .readdata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write_n => CONNECTED_TO_write_n -- .write_n
+ -- clk.clk
+ clk => CONNECTED_TO_clk,
+ -- irq.irq
+ irq => CONNECTED_TO_irq,
+ -- reset.reset_n
+ reset_n => CONNECTED_TO_reset_n,
+ -- s1.address
+ address => CONNECTED_TO_address,
+ -- .writedata
+ writedata => CONNECTED_TO_writedata,
+ -- .readdata
+ readdata => CONNECTED_TO_readdata,
+ -- .chipselect
+ chipselect => CONNECTED_TO_chipselect,
+ -- .write_n
+ write_n => CONNECTED_TO_write_n
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
index 5e0e90fde0e616c1acf47f212484ceb92e1baddf..ec61f1d33038f60dd573210f7471b18539d1dd44 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
@@ -35,21 +35,29 @@ entity unb2b_jesd_node0 is
g_design_name : string := "unb2b_jesd_node0";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e1sg;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0; -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0;
g_protect_addr_range: boolean := false
);
port (
-- GENERAL
-- CLK : IN STD_LOGIC; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
index 1188b1f4a3a8c3bda14f3b6fb3aaf6912e8d9d4f..b7ce0936ddd4e7588a1b5f74260d4097c6b49f0c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
@@ -1,18 +1,28 @@
component altjesd_ss_RX_corepll is
port (
- locked : out std_logic; -- export
- outclk_0 : out std_logic; -- clk
- outclk_1 : out std_logic; -- clk
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X' -- reset
+ -- export
+ locked : out std_logic;
+ -- clk
+ outclk_0 : out std_logic;
+ -- clk
+ outclk_1 : out std_logic;
+ -- clk
+ refclk : in std_logic := 'X';
+ -- reset
+ rst : in std_logic := 'X'
);
end component altjesd_ss_RX_corepll;
u0 : component altjesd_ss_RX_corepll
port map (
- locked => CONNECTED_TO_locked, -- locked.export
- outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk
- outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
- refclk => CONNECTED_TO_refclk, -- refclk.clk
- rst => CONNECTED_TO_rst -- reset.reset
+ -- locked.export
+ locked => CONNECTED_TO_locked,
+ -- outclk0.clk
+ outclk_0 => CONNECTED_TO_outclk_0,
+ -- outclk1.clk
+ outclk_1 => CONNECTED_TO_outclk_1,
+ -- refclk.clk
+ refclk => CONNECTED_TO_refclk,
+ -- reset.reset
+ rst => CONNECTED_TO_rst
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
index 4d125d7d6b09eb801f54521d54896e4cd0d3f452..9fda67c683ff13c98207b6d9e9980eef2f59c440 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
@@ -1,14 +1,20 @@
component altjesd_ss_RX_frame_reset is
port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
+ -- clk
+ clk : in std_logic := 'X';
+ -- reset_n
+ in_reset_n : in std_logic := 'X';
+ -- reset_n
+ out_reset_n : out std_logic
);
end component altjesd_ss_RX_frame_reset;
u0 : component altjesd_ss_RX_frame_reset
port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ -- clk.clk
+ clk => CONNECTED_TO_clk,
+ -- in_reset.reset_n
+ in_reset_n => CONNECTED_TO_in_reset_n,
+ -- out_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
index 2fdfadb51af42decdc595af06f6653c82f64f67b..336f3eca87c925d56495622485633f8c04fd47c0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
@@ -1,14 +1,20 @@
component altjesd_ss_RX_link_reset is
port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
+ -- clk
+ clk : in std_logic := 'X';
+ -- reset_n
+ in_reset_n : in std_logic := 'X';
+ -- reset_n
+ out_reset_n : out std_logic
);
end component altjesd_ss_RX_link_reset;
u0 : component altjesd_ss_RX_link_reset
port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ -- clk.clk
+ clk => CONNECTED_TO_clk,
+ -- in_reset.reset_n
+ in_reset_n => CONNECTED_TO_in_reset_n,
+ -- out_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
index f5e2ba1f77a9a3ef8e6ec47a9929ad820950c0a3..d82290055d9312efd9c4a8a5c301a6ff7b7ca81e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
@@ -57,26 +57,46 @@
DSRT_QUALCNT_9 : integer := 0
);
port (
- av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_read : in std_logic := 'X'; -- read
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_write : in std_logic := 'X'; -- write
- irq : out std_logic; -- irq
- clk : in std_logic := 'X'; -- clk
- csr_reset : in std_logic := 'X'; -- reset
- reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
- reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
- reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
- reset_in0 : in std_logic := 'X'; -- reset
- reset_out0 : out std_logic; -- reset
- reset_out1 : out std_logic; -- reset
- reset_out2 : out std_logic; -- reset
- reset_out3 : out std_logic; -- reset
- reset_out4 : out std_logic; -- reset
- reset_out5 : out std_logic; -- reset
- reset_out6 : out std_logic; -- reset
- reset_out7 : out std_logic -- reset
+ -- address
+ av_address : in std_logic_vector(7 downto 0) := (others => 'X');
+ -- readdata
+ av_readdata : out std_logic_vector(31 downto 0);
+ -- read
+ av_read : in std_logic := 'X';
+ -- writedata
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- write
+ av_write : in std_logic := 'X';
+ -- irq
+ irq : out std_logic;
+ -- clk
+ clk : in std_logic := 'X';
+ -- reset
+ csr_reset : in std_logic := 'X';
+ -- reset1_dsrt_qual
+ reset1_dsrt_qual : in std_logic := 'X';
+ -- reset2_dsrt_qual
+ reset2_dsrt_qual : in std_logic := 'X';
+ -- reset5_dsrt_qual
+ reset5_dsrt_qual : in std_logic := 'X';
+ -- reset
+ reset_in0 : in std_logic := 'X';
+ -- reset
+ reset_out0 : out std_logic;
+ -- reset
+ reset_out1 : out std_logic;
+ -- reset
+ reset_out2 : out std_logic;
+ -- reset
+ reset_out3 : out std_logic;
+ -- reset
+ reset_out4 : out std_logic;
+ -- reset
+ reset_out5 : out std_logic;
+ -- reset
+ reset_out6 : out std_logic;
+ -- reset
+ reset_out7 : out std_logic
);
end component altjesd_ss_RX_reset_seq;
@@ -139,24 +159,44 @@
DSRT_QUALCNT_9 => INTEGER_VALUE_FOR_DSRT_QUALCNT_9
)
port map (
- av_address => CONNECTED_TO_av_address, -- av_csr.address
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_read => CONNECTED_TO_av_read, -- .read
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_write => CONNECTED_TO_av_write, -- .write
- irq => CONNECTED_TO_irq, -- av_csr_irq.irq
- clk => CONNECTED_TO_clk, -- clk.clk
- csr_reset => CONNECTED_TO_csr_reset, -- csr_reset.reset
- reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual, -- reset1_dsrt_qual.reset1_dsrt_qual
- reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual, -- reset2_dsrt_qual.reset2_dsrt_qual
- reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual, -- reset5_dsrt_qual.reset5_dsrt_qual
- reset_in0 => CONNECTED_TO_reset_in0, -- reset_in0.reset
- reset_out0 => CONNECTED_TO_reset_out0, -- reset_out0.reset
- reset_out1 => CONNECTED_TO_reset_out1, -- reset_out1.reset
- reset_out2 => CONNECTED_TO_reset_out2, -- reset_out2.reset
- reset_out3 => CONNECTED_TO_reset_out3, -- reset_out3.reset
- reset_out4 => CONNECTED_TO_reset_out4, -- reset_out4.reset
- reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
- reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
- reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
+ -- av_csr.address
+ av_address => CONNECTED_TO_av_address,
+ -- .readdata
+ av_readdata => CONNECTED_TO_av_readdata,
+ -- .read
+ av_read => CONNECTED_TO_av_read,
+ -- .writedata
+ av_writedata => CONNECTED_TO_av_writedata,
+ -- .write
+ av_write => CONNECTED_TO_av_write,
+ -- av_csr_irq.irq
+ irq => CONNECTED_TO_irq,
+ -- clk.clk
+ clk => CONNECTED_TO_clk,
+ -- csr_reset.reset
+ csr_reset => CONNECTED_TO_csr_reset,
+ -- reset1_dsrt_qual.reset1_dsrt_qual
+ reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual,
+ -- reset2_dsrt_qual.reset2_dsrt_qual
+ reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual,
+ -- reset5_dsrt_qual.reset5_dsrt_qual
+ reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual,
+ -- reset_in0.reset
+ reset_in0 => CONNECTED_TO_reset_in0,
+ -- reset_out0.reset
+ reset_out0 => CONNECTED_TO_reset_out0,
+ -- reset_out1.reset
+ reset_out1 => CONNECTED_TO_reset_out1,
+ -- reset_out2.reset
+ reset_out2 => CONNECTED_TO_reset_out2,
+ -- reset_out3.reset
+ reset_out3 => CONNECTED_TO_reset_out3,
+ -- reset_out4.reset
+ reset_out4 => CONNECTED_TO_reset_out4,
+ -- reset_out5.reset
+ reset_out5 => CONNECTED_TO_reset_out5,
+ -- reset_out6.reset
+ reset_out6 => CONNECTED_TO_reset_out6,
+ -- reset_out7.reset
+ reset_out7 => CONNECTED_TO_reset_out7
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
index e49f93a337e01a20a39b99a717881d143e0d0970..be9a3ab81e0cc487e0702a6540bcfb852224350a 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
@@ -1,24 +1,40 @@
component altjesd_ss_RX_xcvr_reset_control is
port (
- clock : in std_logic := 'X'; -- clk
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- reset : in std_logic := 'X'; -- reset
- rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_cal_busy
- rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_ready : out std_logic_vector(0 downto 0) -- rx_ready
+ -- clk
+ clock : in std_logic := 'X';
+ -- pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- reset
+ reset : in std_logic := 'X';
+ -- rx_analogreset
+ rx_analogreset : out std_logic_vector(0 downto 0);
+ -- rx_cal_busy
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_digitalreset
+ rx_digitalreset : out std_logic_vector(0 downto 0);
+ -- rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_ready
+ rx_ready : out std_logic_vector(0 downto 0)
);
end component altjesd_ss_RX_xcvr_reset_control;
u0 : component altjesd_ss_RX_xcvr_reset_control
port map (
- clock => CONNECTED_TO_clock, -- clock.clk
- pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
- reset => CONNECTED_TO_reset, -- reset.reset
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
+ -- clock.clk
+ clock => CONNECTED_TO_clock,
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown => CONNECTED_TO_pll_powerdown,
+ -- reset.reset
+ reset => CONNECTED_TO_reset,
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset => CONNECTED_TO_rx_analogreset,
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy,
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset,
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata,
+ -- rx_ready.rx_ready
+ rx_ready => CONNECTED_TO_rx_ready
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
index af64e251092b8abe7083a94e7070e5407b77a322..2165664a8324ad2243939f6ecb9790c64ad106c9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
@@ -1,16 +1,24 @@
component device_clk is
port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
+ -- clk
+ clk_out : out std_logic;
+ -- clk
+ in_clk : in std_logic := 'X';
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- reset_n
+ reset_n_out : out std_logic
);
end component device_clk;
u0 : component device_clk
port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ -- clk.clk
+ clk_out => CONNECTED_TO_clk_out,
+ -- clk_in.clk
+ in_clk => CONNECTED_TO_in_clk,
+ -- clk_in_reset.reset_n
+ reset_n => CONNECTED_TO_reset_n,
+ -- clk_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
index 26992b63a4edbecaa5e2a236b47a7c62d9e417d4..aba66e80db7e08b17ffde24c9240f7a88a2eb12b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
@@ -1,16 +1,24 @@
component frame_clk is
port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
+ -- clk
+ clk_out : out std_logic;
+ -- clk
+ in_clk : in std_logic := 'X';
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- reset_n
+ reset_n_out : out std_logic
);
end component frame_clk;
u0 : component frame_clk
port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ -- clk.clk
+ clk_out => CONNECTED_TO_clk_out,
+ -- clk_in.clk
+ in_clk => CONNECTED_TO_in_clk,
+ -- clk_in_reset.reset_n
+ reset_n => CONNECTED_TO_reset_n,
+ -- clk_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
index 745dc1937c6fff32fda95a03e5bd47b88e8206b7..494729cac4145ec82cd0ad822bb8486c0610d4f7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
@@ -1,100 +1,192 @@
component jesd is
port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
+ -- export
+ alldev_lane_aligned : in std_logic := 'X';
+ -- export
+ csr_cf : out std_logic_vector(4 downto 0);
+ -- export
+ csr_cs : out std_logic_vector(1 downto 0);
+ -- export
+ csr_f : out std_logic_vector(7 downto 0);
+ -- export
+ csr_hd : out std_logic;
+ -- export
+ csr_k : out std_logic_vector(4 downto 0);
+ -- export
+ csr_l : out std_logic_vector(4 downto 0);
+ -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0);
+ -- export
+ csr_m : out std_logic_vector(7 downto 0);
+ -- export
+ csr_n : out std_logic_vector(4 downto 0);
+ -- export
+ csr_np : out std_logic_vector(4 downto 0);
+ -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0);
+ -- export
+ csr_s : out std_logic_vector(4 downto 0);
+ -- export
+ dev_lane_aligned : out std_logic;
+ -- export
+ dev_sync_n : out std_logic;
+ -- chipselect
+ jesd204_rx_avs_chipselect : in std_logic := 'X';
+ -- address
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X');
+ -- read
+ jesd204_rx_avs_read : in std_logic := 'X';
+ -- readdata
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0);
+ -- waitrequest
+ jesd204_rx_avs_waitrequest : out std_logic;
+ -- write
+ jesd204_rx_avs_write : in std_logic := 'X';
+ -- writedata
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- clk
+ jesd204_rx_avs_clk : in std_logic := 'X';
+ -- reset_n
+ jesd204_rx_avs_rst_n : in std_logic := 'X';
+ -- export
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_frame_error : in std_logic := 'X';
+ -- irq
+ jesd204_rx_int : out std_logic;
+ -- data
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0);
+ -- valid
+ jesd204_rx_link_valid : out std_logic;
+ -- ready
+ jesd204_rx_link_ready : in std_logic := 'X';
+ -- clk
+ pll_ref_clk : in std_logic := 'X';
+ -- rx_analogreset
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_cal_busy
+ rx_cal_busy : out std_logic_vector(0 downto 0);
+ -- rx_digitalreset
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_is_lockedtodata
+ rx_islockedtodata : out std_logic_vector(0 downto 0);
+ -- rx_serial_data
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- clk
+ rxlink_clk : in std_logic := 'X';
+ -- reset_n
+ rxlink_rst_n_reset_n : in std_logic := 'X';
+ -- export
+ rxphy_clk : out std_logic_vector(0 downto 0);
+ -- export
+ sof : out std_logic_vector(3 downto 0);
+ -- export
+ somf : out std_logic_vector(3 downto 0);
+ -- export
+ sysref : in std_logic := 'X'
);
end component jesd;
u0 : component jesd
port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
+ -- alldev_lane_aligned.export
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned,
+ -- csr_cf.export
+ csr_cf => CONNECTED_TO_csr_cf,
+ -- csr_cs.export
+ csr_cs => CONNECTED_TO_csr_cs,
+ -- csr_f.export
+ csr_f => CONNECTED_TO_csr_f,
+ -- csr_hd.export
+ csr_hd => CONNECTED_TO_csr_hd,
+ -- csr_k.export
+ csr_k => CONNECTED_TO_csr_k,
+ -- csr_l.export
+ csr_l => CONNECTED_TO_csr_l,
+ -- csr_lane_powerdown.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown,
+ -- csr_m.export
+ csr_m => CONNECTED_TO_csr_m,
+ -- csr_n.export
+ csr_n => CONNECTED_TO_csr_n,
+ -- csr_np.export
+ csr_np => CONNECTED_TO_csr_np,
+ -- csr_rx_testmode.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode,
+ -- csr_s.export
+ csr_s => CONNECTED_TO_csr_s,
+ -- dev_lane_aligned.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned,
+ -- dev_sync_n.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n,
+ -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect,
+ -- .address
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address,
+ -- .read
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read,
+ -- .readdata
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata,
+ -- .waitrequest
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest,
+ -- .write
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write,
+ -- .writedata
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata,
+ -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk,
+ -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n,
+ -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data,
+ -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid,
+ -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr,
+ -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect,
+ -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data,
+ -- jesd204_rx_frame_error.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error,
+ -- jesd204_rx_int.irq
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int,
+ -- jesd204_rx_link.data
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data,
+ -- .valid
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid,
+ -- .ready
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready,
+ -- pll_ref_clk.clk
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk,
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset => CONNECTED_TO_rx_analogreset,
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy,
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset,
+ -- rx_islockedtodata.rx_is_lockedtodata
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata,
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data => CONNECTED_TO_rx_serial_data,
+ -- rxlink_clk.clk
+ rxlink_clk => CONNECTED_TO_rxlink_clk,
+ -- rxlink_rst_n.reset_n
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n,
+ -- rxphy_clk.export
+ rxphy_clk => CONNECTED_TO_rxphy_clk,
+ -- sof.export
+ sof => CONNECTED_TO_sof,
+ -- somf.export
+ somf => CONNECTED_TO_somf,
+ -- sysref.export
+ sysref => CONNECTED_TO_sysref
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
index acbc33a2d1959920765b1866572b908d153acbc2..f9a8f8fead903f01137de49be095efefb20186a4 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
@@ -1,16 +1,24 @@
component link_clk is
port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
+ -- clk
+ clk_out : out std_logic;
+ -- clk
+ in_clk : in std_logic := 'X';
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- reset_n
+ reset_n_out : out std_logic
);
end component link_clk;
u0 : component link_clk
port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ -- clk.clk
+ clk_out => CONNECTED_TO_clk_out,
+ -- clk_in.clk
+ in_clk => CONNECTED_TO_in_clk,
+ -- clk_in_reset.reset_n
+ reset_n => CONNECTED_TO_reset_n,
+ -- clk_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
index 42aae3ddf073f5dfbfee338c2139ed38675a6a2a..6e69a1fd8b1889422a42619413dda427f7f601ee 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_avs_common_mm_0;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
index 4ddaf7fa7d6f6d85a966525b9dd908dbdae955a3..441d19627c7c74f9c643381a4382b89a19adb50d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_avs_common_mm_1;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
index d648f26fb1cb1a3e9c804714afad5c500ffa4798..048d776d65de66af1f7b85555885b9324efb707b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
@@ -45,25 +45,30 @@ entity avs2_eth_coe is
mms_tse_write : in std_logic;
mms_tse_read : in std_logic;
mms_tse_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_tse_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 0
- mms_tse_waitrequest : out std_logic; -- necessary because read latency is 0
+ -- read latency is 0
+ mms_tse_readdata : out std_logic_vector(c_word_w - 1 downto 0);
+ -- necessary because read latency is 0
+ mms_tse_waitrequest : out std_logic;
-- ETH registers
mms_reg_address : in std_logic_vector(c_eth_reg_addr_w - 1 downto 0);
mms_reg_write : in std_logic;
mms_reg_read : in std_logic;
mms_reg_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_reg_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 1
+ -- read latency is 1
+ mms_reg_readdata : out std_logic_vector(c_word_w - 1 downto 0);
-- ETH packet RAM
mms_ram_address : in std_logic_vector(c_eth_ram_addr_w - 1 downto 0);
mms_ram_write : in std_logic;
mms_ram_read : in std_logic;
mms_ram_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_ram_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 2
+ -- read latency is 2
+ mms_ram_readdata : out std_logic_vector(c_word_w - 1 downto 0);
-- Interrupt Sender interface
- ins_interrupt_irq : out std_logic; -- relates to the ETH registers port
+ -- relates to the ETH registers port
+ ins_interrupt_irq : out std_logic;
----------------------------------------------------------------------------
-- User side
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
index e879f1b9edecdcf0c9866d6359c01c0b6a645338..11d1cb80798696dd2c17cc8cf7ab10c9285e3daf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
@@ -57,27 +57,38 @@ package common_network_layers_pkg is
constant c_network_eth_mac_addr_w : natural := c_network_eth_mac_addr_len * c_8;
constant c_network_eth_type_len : natural := 2;
constant c_network_eth_type_w : natural := c_network_eth_type_len * c_8;
- constant c_network_eth_header_len : natural := 2 * c_network_eth_mac_addr_len + c_network_eth_type_len; -- = 14
+ -- = 14
+ constant c_network_eth_header_len : natural := 2 * c_network_eth_mac_addr_len + c_network_eth_type_len;
constant c_network_eth_payload_min : natural := 46;
constant c_network_eth_payload_max : natural := 1500;
constant c_network_eth_payload_jumbo_max : natural := 9000;
constant c_network_eth_crc_len : natural := 4;
constant c_network_eth_crc_w : natural := c_network_eth_crc_len * c_8;
- constant c_network_eth_gap_len : natural := 12; -- IPG = interpacket gap, minimum idle period between transmission of Ethernet packets
- constant c_network_eth_frame_max : natural := c_network_eth_header_len + c_network_eth_payload_max + c_network_eth_crc_len; -- = 1518
- constant c_network_eth_frame_jumbo_max : natural := c_network_eth_header_len + c_network_eth_payload_jumbo_max + c_network_eth_crc_len; -- = 9018
+ -- IPG = interpacket gap, minimum idle period between transmission of Ethernet packets
+ constant c_network_eth_gap_len : natural := 12;
+ -- = 1518
+ constant c_network_eth_frame_max : natural := c_network_eth_header_len + c_network_eth_payload_max + c_network_eth_crc_len;
+ -- = 9018
+ constant c_network_eth_frame_jumbo_max : natural := c_network_eth_header_len + c_network_eth_payload_jumbo_max + c_network_eth_crc_len;
-- default field values
- constant c_network_eth_preamble : natural := 5; -- nibble "0101"
- constant c_network_eth_frame_delimiter : natural := 13; -- nibble "1101"
+ -- nibble "0101"
+ constant c_network_eth_preamble : natural := 5;
+ -- nibble "1101"
+ constant c_network_eth_frame_delimiter : natural := 13;
-- useful field values
- constant c_network_eth_mac_slv : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := (others => 'X'); -- Ethernet MAC slv RANGE
- constant c_network_eth_bc_mac : std_logic_vector(c_network_eth_mac_slv'range) := (others => '1'); -- Broadcast destination MAC
-
- constant c_network_eth_type_slv : std_logic_vector(c_network_eth_type_w - 1 downto 0) := (others => 'X'); -- Ethernet TYPE slv RANGE
- constant c_network_eth_type_arp : natural := 16#0806#; -- ARP = Address Resolution Prorotol
- constant c_network_eth_type_ip : natural := 16#0800#; -- IPv4 = Internet Protocol, Version 4
+ -- Ethernet MAC slv RANGE
+ constant c_network_eth_mac_slv : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := (others => 'X');
+ -- Broadcast destination MAC
+ constant c_network_eth_bc_mac : std_logic_vector(c_network_eth_mac_slv'range) := (others => '1');
+
+ -- Ethernet TYPE slv RANGE
+ constant c_network_eth_type_slv : std_logic_vector(c_network_eth_type_w - 1 downto 0) := (others => 'X');
+ -- ARP = Address Resolution Prorotol
+ constant c_network_eth_type_arp : natural := 16#0806#;
+ -- IPv4 = Internet Protocol, Version 4
+ constant c_network_eth_type_ip : natural := 16#0800#;
type t_network_eth_header is record
dst_mac : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
@@ -111,8 +122,10 @@ package common_network_layers_pkg is
--
-- field widths in bits '_w' or in bytes '_len'
- constant c_network_ip_version_w : natural := 4; -- 4-bit field
- constant c_network_ip_header_length_w : natural := 4; -- 4-bit field
+ -- 4-bit field
+ constant c_network_ip_version_w : natural := 4;
+ -- 4-bit field
+ constant c_network_ip_header_length_w : natural := 4;
constant c_network_ip_version_header_len : natural := 1;
constant c_network_ip_version_header_w : natural := c_network_ip_version_header_len * c_8;
constant c_network_ip_services_len : natural := 1;
@@ -121,8 +134,10 @@ package common_network_layers_pkg is
constant c_network_ip_total_length_w : natural := c_network_ip_total_length_len * c_8;
constant c_network_ip_identification_len : natural := 2;
constant c_network_ip_identification_w : natural := c_network_ip_identification_len * c_8;
- constant c_network_ip_flags_w : natural := 3; -- 3-bit field
- constant c_network_ip_fragment_offset_w : natural := 13; -- 13-bit field
+ -- 3-bit field
+ constant c_network_ip_flags_w : natural := 3;
+ -- 13-bit field
+ constant c_network_ip_fragment_offset_w : natural := 13;
constant c_network_ip_flags_fragment_len : natural := 2;
constant c_network_ip_flags_fragment_w : natural := c_network_ip_flags_fragment_len * c_8;
constant c_network_ip_time_to_live_len : natural := 1;
@@ -142,36 +157,61 @@ package common_network_layers_pkg is
c_network_ip_addr_len;
-- = c_network_ip_header_length * c_word_sz = 20
-- default field values
- constant c_network_ip_version : natural := 4; -- 4 = IPv4,
- constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
- constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
- constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
- constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
- constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
- constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
- constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
- constant c_network_ip_header_checksum : natural := 0; -- init value
+ -- 4 = IPv4,
+ constant c_network_ip_version : natural := 4;
+ -- 5 = nof words in the header, no options field support
+ constant c_network_ip_header_length : natural := 5;
+ -- 0 = default, use default on transmit, ignore on receive, copy on reply
+ constant c_network_ip_services : natural := 0;
+ -- >= 20, nof bytes in entire datagram including header and data
+ constant c_network_ip_total_length : natural := 20;
+ -- identification number, copy on reply
+ constant c_network_ip_identification : natural := 0;
+ -- 2 = don't fragment and this is the last fragment
+ constant c_network_ip_flags : natural := 2;
+ -- 0 = first fragment
+ constant c_network_ip_fragment_offset : natural := 0;
+ -- number of hops until the packet will be discarded
+ constant c_network_ip_time_to_live : natural := 127;
+ -- init value
+ constant c_network_ip_header_checksum : natural := 0;
-- useful field values
- constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
- constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
- constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
+ -- IP protocol slv RANGE
+ constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X');
+ -- UDP = User Datagram Protocol (for board control and streaming data)
+ constant c_network_ip_protocol_udp : natural := 17;
+ -- ICMP = Internet Control Message Protocol (for ping)
+ constant c_network_ip_protocol_icmp : natural := 1;
- constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
+ -- IP address slv RANGE
+ constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X');
type t_network_ip_header is record
- version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
- header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
- services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
- total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
- identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
- flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
- fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
- time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
- protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
- header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
- src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ -- 4 bit
+ version : std_logic_vector(c_network_ip_version_w - 1 downto 0);
+ -- 4 bit
+ header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0);
+ -- 1 octet
+ services : std_logic_vector(c_network_ip_services_w - 1 downto 0);
+ -- 2 octet
+ total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0);
+ -- 2 octet
+ identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0);
+ -- 3 bit
+ flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0);
+ -- 13 bit
+ fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0);
+ -- 1 octet
+ time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0);
+ -- 1 octet
+ protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0);
+ -- 2 octet
+ header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0);
+ -- 4 octet
+ src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- 4 octet
+ dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
end record;
constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
@@ -223,27 +263,44 @@ package common_network_layers_pkg is
-- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
- constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
- constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
- constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
- constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
- constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
- constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
+ -- Hardware type, 1=ethernet
+ constant c_network_arp_htype : natural := 1;
+ -- Protocol type, do ARP for IPv4
+ constant c_network_arp_ptype : natural := c_network_eth_type_ip;
+ -- Hardware length = 6
+ constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len;
+ -- Protocol length = 4
+ constant c_network_arp_plen : natural := c_network_ip_addr_len;
+ -- Operator, 1=request
+ constant c_network_arp_oper_request : natural := 1;
+ -- Operator, 2=reply
+ constant c_network_arp_oper_reply : natural := 2;
-- useful field values
- constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
- constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
+ -- Broadcast destination MAC
+ constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac;
+ -- Broadcast target hardware address
+ constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac;
type t_network_arp_packet is record
- htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
- ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
- hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
- plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
- oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
- sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
- spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
- tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
- tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
+ -- 2 octet
+ htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0);
+ -- 2 octet
+ ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0);
+ -- 1 octet
+ hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0);
+ -- 1 octet
+ plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0);
+ -- 2 octet
+ oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0);
+ -- 6 octet, Sender Hardware Address
+ sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ -- 4 octet, Sender Protocol Address
+ spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- 6 octet, Target Hardware Address
+ tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ -- 4 octet, Target Protocol Address
+ tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
end record;
constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
@@ -283,21 +340,32 @@ package common_network_layers_pkg is
c_network_icmp_id_len + c_network_icmp_sequence_len;
-- default field values
- constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
- constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
- constant c_network_icmp_checksum : natural := 0; -- init value
+ -- 8 = echo request
+ constant c_network_icmp_msg_type_request : natural := 8;
+ -- 8 = echo reply (ping)
+ constant c_network_icmp_msg_type_reply : natural := 0;
+ -- init value
+ constant c_network_icmp_checksum : natural := 0;
-- useful field values
- constant c_network_icmp_code : natural := 0; -- default
- constant c_network_icmp_id : natural := 3; -- arbitrary value
- constant c_network_icmp_sequence : natural := 4; -- arbitrary value
+ -- default
+ constant c_network_icmp_code : natural := 0;
+ -- arbitrary value
+ constant c_network_icmp_id : natural := 3;
+ -- arbitrary value
+ constant c_network_icmp_sequence : natural := 4;
type t_network_icmp_header is record
- msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
- code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
- checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
- id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
- sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
+ -- 1 octet
+ msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0);
+ -- 1 octet
+ code : std_logic_vector(c_network_icmp_code_w - 1 downto 0);
+ -- 2 octet
+ checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0);
+ -- 2 octet
+ id : std_logic_vector(c_network_icmp_id_w - 1 downto 0);
+ -- 2 octet
+ sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0);
end record;
constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
@@ -328,23 +396,33 @@ package common_network_layers_pkg is
-- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+ -- 8
+ c_network_udp_total_length_len + c_network_udp_checksum_len;
-- default field values
- constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
- constant c_network_udp_checksum : natural := 0; -- init value
+ -- >= 8, nof bytes in entire datagram including header and data
+ constant c_network_udp_total_length : natural := 8;
+ -- init value
+ constant c_network_udp_checksum : natural := 0;
-- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
- constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
- constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
- constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
+ -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
+ constant c_network_udp_port_dhcp_in : natural := 68;
+ -- DHCP to server
+ constant c_network_udp_port_dhcp_out : natural := 67;
+ -- UDP port slv RANGE
+ constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X');
type t_network_udp_header is record
- src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
- checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
+ -- 2 octet
+ src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- 2 octet
+ dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- 2 octet
+ total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0);
+ -- 2 octet
+ checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0);
end record;
constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index 4bd7e15cc8fdafe0a37772e3eaedca527d52c4bf..33e9a782ae790b7c4c71516d23a87c8acd5a53bf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -61,8 +61,10 @@ package common_pkg is
constant c_octet_w : natural := 8;
constant c_halfword_w : natural := c_byte_w * c_halfword_sz;
constant c_word_w : natural := c_byte_w * c_word_sz;
- constant c_integer_w : natural := 32; -- unfortunately VHDL integer type is limited to 32 bit values
- constant c_natural_w : natural := c_integer_w - 1; -- unfortunately VHDL natural type is limited to 31 bit values (0 and the positive subset of the VHDL integer type0
+ -- unfortunately VHDL integer type is limited to 32 bit values
+ constant c_integer_w : natural := 32;
+ -- unfortunately VHDL natural type is limited to 31 bit values (0 and the positive subset of the VHDL integer type0
+ constant c_natural_w : natural := c_integer_w - 1;
constant c_longword_w : natural := c_byte_w * c_longword_sz;
-- logic
@@ -80,30 +82,46 @@ package common_pkg is
constant c_slv10 : std_logic_vector(255 downto 0) := c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10;
-- math
- constant c_nof_complex : natural := 2; -- Real and imaginary part of complex number
- constant c_sign_w : natural := 1; -- Sign bit, can be used to skip one of the double sign bits of a product
- constant c_sum_of_prod_w : natural := 1; -- Bit growth for sum of 2 products, can be used in case complex multiply has normalized real and imag inputs instead of normalized amplitude inputs
+ -- Real and imaginary part of complex number
+ constant c_nof_complex : natural := 2;
+ -- Sign bit, can be used to skip one of the double sign bits of a product
+ constant c_sign_w : natural := 1;
+ -- Bit growth for sum of 2 products, can be used in case complex multiply has normalized real and imag inputs instead of normalized amplitude inputs
+ constant c_sum_of_prod_w : natural := 1;
-- FF, block RAM, FIFO
- constant c_meta_delay_len : natural := 3; -- default nof flipflops (FF) in meta stability recovery delay line (e.g. for clock domain crossing)
- constant c_meta_fifo_depth : natural := 16; -- default use 16 word deep FIFO to cross clock domain, typically > 2*c_meta_delay_len or >~ 8 is enough
+ -- default nof flipflops (FF) in meta stability recovery delay line (e.g. for clock domain crossing)
+ constant c_meta_delay_len : natural := 3;
+ -- default use 16 word deep FIFO to cross clock domain, typically > 2*c_meta_delay_len or >~ 8 is enough
+ constant c_meta_fifo_depth : natural := 16;
- constant c_bram_m9k_nof_bits : natural := 1024 * 9; -- size of 1 Altera M9K block RAM in bits
- constant c_bram_m9k_max_w : natural := 36; -- maximum width of 1 Altera M9K block RAM, so the size is then 256 words of 36 bits
- constant c_bram_m9k_fifo_depth : natural := c_bram_m9k_nof_bits / c_bram_m9k_max_w; -- using a smaller FIFO depth than this leaves part of the RAM unused
+ -- size of 1 Altera M9K block RAM in bits
+ constant c_bram_m9k_nof_bits : natural := 1024 * 9;
+ -- maximum width of 1 Altera M9K block RAM, so the size is then 256 words of 36 bits
+ constant c_bram_m9k_max_w : natural := 36;
+ -- using a smaller FIFO depth than this leaves part of the RAM unused
+ constant c_bram_m9k_fifo_depth : natural := c_bram_m9k_nof_bits / c_bram_m9k_max_w;
- constant c_fifo_afull_margin : natural := 4; -- default or minimal FIFO almost full margin
+ -- default or minimal FIFO almost full margin
+ constant c_fifo_afull_margin : natural := 4;
-- DSP
- constant c_dsp_mult_w : natural := 18; -- Width of the embedded multipliers in Stratix IV
+ -- Width of the embedded multipliers in Stratix IV
+ constant c_dsp_mult_w : natural := 18;
-- TYPE DECLARATIONS --------------------------------------------------------
- type t_boolean_arr is array (integer range <>) of boolean; -- INTEGER left index starts default at -2**31
- type t_integer_arr is array (integer range <>) of integer; -- INTEGER left index starts default at -2**31
- type t_natural_arr is array (integer range <>) of natural; -- INTEGER left index starts default at -2**31
- type t_nat_boolean_arr is array (natural range <>) of boolean; -- NATURAL left index starts default at 0
- type t_nat_integer_arr is array (natural range <>) of integer; -- NATURAL left index starts default at 0
- type t_nat_natural_arr is array (natural range <>) of natural; -- NATURAL left index starts default at 0
+ -- INTEGER left index starts default at -2**31
+ type t_boolean_arr is array (integer range <>) of boolean;
+ -- INTEGER left index starts default at -2**31
+ type t_integer_arr is array (integer range <>) of integer;
+ -- INTEGER left index starts default at -2**31
+ type t_natural_arr is array (integer range <>) of natural;
+ -- NATURAL left index starts default at 0
+ type t_nat_boolean_arr is array (natural range <>) of boolean;
+ -- NATURAL left index starts default at 0
+ type t_nat_integer_arr is array (natural range <>) of integer;
+ -- NATURAL left index starts default at 0
+ type t_nat_natural_arr is array (natural range <>) of natural;
type t_sl_arr is array (integer range <>) of std_logic;
type t_slv_1_arr is array (integer range <>) of std_logic_vector(0 downto 0);
type t_slv_2_arr is array (integer range <>) of std_logic_vector(1 downto 0);
@@ -122,8 +140,10 @@ package common_pkg is
type t_slv_512_arr is array (integer range <>) of std_logic_vector(511 downto 0);
type t_slv_1024_arr is array (integer range <>) of std_logic_vector(1023 downto 0);
- constant c_boolean_arr : t_boolean_arr := (true, false); -- array all possible values that can be iterated over
- constant c_nat_boolean_arr : t_nat_boolean_arr := (true, false); -- array all possible values that can be iterated over
+ -- array all possible values that can be iterated over
+ constant c_boolean_arr : t_boolean_arr := (true, false);
+ -- array all possible values that can be iterated over
+ constant c_nat_boolean_arr : t_nat_boolean_arr := (true, false);
type t_integer_matrix is array (integer range <>, integer range <>) of integer;
type t_boolean_matrix is array (integer range <>, integer range <>) of boolean;
@@ -151,61 +171,87 @@ package common_pkg is
type t_sys_rce is record
rst : std_logic;
clk : std_logic;
- clken : std_logic; -- := '1';
+ -- := '1';
+ clken : std_logic;
end record;
type t_sys_ce is record
clk : std_logic;
- clken : std_logic; -- := '1';
+ -- := '1';
+ clken : std_logic;
end record;
-- FUNCTION DECLARATIONS ----------------------------------------------------
-- All functions assume [high downto low] input ranges
- function pow2(n : natural) return natural; -- = 2**n
- function ceil_pow2(n : integer) return natural; -- = 2**n, returns 1 for n<0
+ -- = 2**n
+ function pow2(n : natural) return natural;
+ -- = 2**n, returns 1 for n<0
+ function ceil_pow2(n : integer) return natural;
- function true_log2(n : natural) return natural; -- true_log2(n) = log2(n)
- function ceil_log2(n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ -- true_log2(n) = log2(n)
+ function true_log2(n : natural) return natural;
+ -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ function ceil_log2(n : natural) return natural;
function floor_log10(n : natural) return natural;
- function is_pow2(n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
- function true_log_pow2(n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
-
- function ratio( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
- function ratio2(n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
-
- function ceil_div( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
- function ceil_value( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
- function floor_value(n, d : natural) return natural; -- floor_value = (n/d) * d
+ -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
+ function is_pow2(n : natural) return boolean;
+ -- 2**true_log2(n), return power of 2 that is >= n
+ function true_log_pow2(n : natural) return natural;
+
+ -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
+ function ratio( n, d : natural) return natural;
+ -- return integer ratio of n/m or m/n, whichever is the largest
+ function ratio2(n, m : natural) return natural;
+
+ -- ceil_div = n/d + (n MOD d)/=0
+ function ceil_div( n, d : natural) return natural;
+ -- ceil_value = ceil_div(n, d) * d
+ function ceil_value( n, d : natural) return natural;
+ -- floor_value = (n/d) * d
+ function floor_value(n, d : natural) return natural;
function ceil_div( n : unsigned; d: natural) return unsigned;
function ceil_value( n : unsigned; d: natural) return unsigned;
function floor_value(n : unsigned; d: natural) return unsigned;
- function slv(n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
- function sl( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
+ -- standard logic to 1 element standard logic vector
+ function slv(n: in std_logic) return std_logic_vector;
+ -- 1 element standard logic vector to standard logic
+ function sl( n: in std_logic_vector) return std_logic;
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr;
function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr;
function to_integer_arr(n : t_natural_arr) return t_integer_arr;
function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr;
function to_slv_32_arr( n : t_integer_arr) return t_slv_32_arr;
function to_slv_32_arr( n : t_natural_arr) return t_slv_32_arr;
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
- function vector_and(slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
- function vector_or( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
- function vector_xor(slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
-
- function andv(slv : std_logic_vector) return std_logic; -- alias of vector_and
- function orv( slv : std_logic_vector) return std_logic; -- alias of vector_or
- function xorv(slv : std_logic_vector) return std_logic; -- alias of vector_xor
-
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
- function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
+ -- Core operation tree function for vector "AND", "OR", "XOR"
+ function vector_tree(slv : std_logic_vector; operation : string) return std_logic;
+ -- '1' when all slv bits are '1' else '0'
+ function vector_and(slv : std_logic_vector) return std_logic;
+ -- '0' when all slv bits are '0' else '1'
+ function vector_or( slv : std_logic_vector) return std_logic;
+ -- '1' when the slv has an odd number of '1' bits else '0'
+ function vector_xor(slv : std_logic_vector) return std_logic;
+ -- Returns slv when it contains one hot bit, else returns 0.
+ function vector_one_hot(slv : std_logic_vector) return std_logic_vector;
+
+ -- alias of vector_and
+ function andv(slv : std_logic_vector) return std_logic;
+ -- alias of vector_or
+ function orv( slv : std_logic_vector) return std_logic;
+ -- alias of vector_xor
+ function xorv(slv : std_logic_vector) return std_logic;
+
+ -- '1' when all matrix bits are '1' else '0'
+ function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic;
+ -- '0' when all matrix bits are '0' else '1'
+ function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic;
function smallest(n, m : integer) return integer;
function smallest(n, m, l : integer) return integer;
@@ -214,34 +260,51 @@ package common_pkg is
function largest(n, m : integer) return integer;
function largest(n : t_natural_arr) return natural;
- function func_sum( n : t_natural_arr) return natural; -- sum of all elements in array
+ -- sum of all elements in array
+ function func_sum( n : t_natural_arr) return natural;
function func_sum( n : t_nat_natural_arr) return natural;
- function func_product(n : t_natural_arr) return natural; -- product of all elements in array
+ -- product of all elements in array
+ function func_product(n : t_natural_arr) return natural;
function func_product(n : t_nat_natural_arr) return natural;
- function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
- function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
- function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
-
- function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
- function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
- function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
- function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
-
- function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
- function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
- function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
-
- function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
- function "/" (L : t_natural_arr; R : positive) return t_natural_arr; -- element wise division
- function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
+ -- element wise sum
+ function "+" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise sum
+ function "+" (L : t_natural_arr; R : integer) return t_natural_arr;
+ -- element wise sum
+ function "+" (L : integer; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise subtract
+ function "-" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise subtract, support negative result
+ function "-" (L, R: t_natural_arr) return t_integer_arr;
+ -- element wise subtract
+ function "-" (L : t_natural_arr; R : integer) return t_natural_arr;
+ -- element wise subtract
+ function "-" (L : integer; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise product
+ function "*" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise product
+ function "*" (L : t_natural_arr; R : natural) return t_natural_arr;
+ -- element wise product
+ function "*" (L : natural; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise division
+ function "/" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise division
+ function "/" (L : t_natural_arr; R : positive) return t_natural_arr;
+ -- element wise division
+ function "/" (L : natural; R : t_natural_arr) return t_natural_arr;
function is_true(a : std_logic) return boolean;
function is_true(a : std_logic) return natural;
function is_true(a : boolean) return std_logic;
function is_true(a : boolean) return natural;
- function is_true(a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
- function is_true(a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
+ -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true(a : integer) return boolean;
+ -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true(a : integer) return std_logic;
function sel_a_b(sel, a, b : boolean) return boolean;
function sel_a_b(sel, a, b : integer) return integer;
@@ -263,46 +326,79 @@ package common_pkg is
function sel_a_b(sel : boolean; a, b : severity_level) return severity_level;
-- sel_n() index sel = 0, 1, 2, ... will return a, b, c, ...
- function sel_n(sel : natural; a, b, c : boolean) return boolean; -- 3
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean; -- 4
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
-
- function sel_n(sel : natural; a, b, c : integer) return integer; -- 3
- function sel_n(sel : natural; a, b, c, d : integer) return integer; -- 4
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
-
- function sel_n(sel : natural; a, b : string) return string; -- 2
- function sel_n(sel : natural; a, b, c : string) return string; -- 3
- function sel_n(sel : natural; a, b, c, d : string) return string; -- 4
- function sel_n(sel : natural; a, b, c, d, e : string) return string; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
+ -- 3
+ function sel_n(sel : natural; a, b, c : boolean) return boolean;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : boolean) return boolean;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean;
+
+ -- 3
+ function sel_n(sel : natural; a, b, c : integer) return integer;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : integer) return integer;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : integer) return integer;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer;
+
+ -- 2
+ function sel_n(sel : natural; a, b : string) return string;
+ -- 3
+ function sel_n(sel : natural; a, b, c : string) return string;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : string) return string;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : string) return string;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : string) return string;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string;
+
+ -- useful to init a unconstrained array of size 1
+ function array_init(init : std_logic; nof : natural) return std_logic_vector;
+ -- useful to init a unconstrained array of size 1
+ function array_init(init, nof : natural) return t_natural_arr;
+ -- useful to init a unconstrained array of size 1
+ function array_init(init, nof : natural) return t_nat_natural_arr;
+ -- useful to init an array with incrementing numbers
+ function array_init(init, nof, incr : natural) return t_natural_arr;
function array_init(init, nof, incr : natural) return t_nat_natural_arr;
function array_init(init, nof, incr : integer) return t_slv_16_arr;
function array_init(init, nof, incr : integer) return t_slv_32_arr;
- function array_init(init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
- function array_init(init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
- function array_sinit(init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+ -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_init(init, nof, width : natural) return std_logic_vector;
+ -- useful to init an unconstrained std_logic_vector with incrementing content
+ function array_init(init, nof, width, incr : natural) return std_logic_vector;
+ -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_sinit(init : integer; nof, width : natural) return std_logic_vector;
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
+ -- initialize all elements in t_slv_64_matrix to value k
+ function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix;
-- Concatenate two or more STD_LOGIC_VECTORs into a single STD_LOGIC_VECTOR or extract one of them from a concatenated STD_LOGIC_VECTOR
function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
@@ -324,13 +420,15 @@ package common_pkg is
function func_slv_extract( use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
function func_slv_extract( use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function TO_UINT(vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ function TO_UINT(vec : std_logic_vector) return natural;
function TO_SINT(vec : std_logic_vector) return integer;
function TO_UVEC(dec, w : natural) return std_logic_vector;
function TO_SVEC(dec, w : integer) return std_logic_vector;
- function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
+ -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
+ function TO_SVEC_32(dec : integer) return std_logic_vector;
-- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
@@ -338,81 +436,132 @@ package common_pkg is
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
-- happens for RESIZE of UNSIGNED. Therefor this is what the RESIZE_NUM for SIGNED and the RESIZE_SVEC do
-- and better not use RESIZE for SIGNED anymore.
- function RESIZE_NUM( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
- function RESIZE_NUM( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
- function RESIZE_UINT(u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
- function RESIZE_SINT(s : integer; w : natural) return integer; -- extend sign bit or keep LS part
-
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
+ -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
+ function RESIZE_NUM( u : unsigned; w : natural) return unsigned;
+ -- extend sign bit or keep LS part
+ function RESIZE_NUM( s : signed; w : natural) return signed;
+ -- left extend with '0' into slv
+ function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector;
+ -- left extend with '0' or keep LS part
+ function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector;
+ -- extend sign bit or keep LS part
+ function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector;
+ -- left extend with '0' or keep LS part
+ function RESIZE_UINT(u : integer; w : natural) return integer;
+ -- extend sign bit or keep LS part
+ function RESIZE_SINT(s : integer; w : natural) return integer;
+
+ -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector;
+ -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector;
function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
-- Used in common_add_sub.vhd
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
-
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
-
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
-
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
+ -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
+ function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
+ function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
+ function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
+ function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+
+ -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+
+ -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
+ function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer;
+ -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
+ function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer;
+
+ -- < 0 shift left, > 0 shift right
+ function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector;
+ -- < 0 shift left, > 0 shift right
+ function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector;
function offset_binary(a : std_logic_vector) return std_logic_vector;
- function truncate( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function scale( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
- function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
- function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
- function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
-
- function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
- function s_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
- function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
- function u_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
-
- function u_to_s(u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
- function s_to_u(s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
-
- function u_wrap(u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
- function s_wrap(s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
-
- function u_clip(u : natural; max : natural) return natural; -- if s < max return s, else return n
- function s_clip(s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
- function s_clip(s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
-
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
- function hton(a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
- function ntoh(a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
-
- function flip(a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
- function flip(a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ -- remove n LSBits from vec, so result has width vec'LENGTH-n
+ function truncate( vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- remove n LSBits from vec and then resize to width w
+ function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- idem for signed values
+ function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- add n '0' LSBits to vec
+ function scale( vec : std_logic_vector; n: natural) return std_logic_vector;
+ -- add n '0' LSBits to vec and then resize to width w
+ function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- idem for signed values
+ function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- when b=TRUE then truncate to width w, else resize to width w
+ function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector;
+ -- idem for signed values
+ function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector;
+
+ -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
+ function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector;
+ -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
+ function s_round( vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- idem but round up to +infinity (s_round_up = u_round)
+ function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector;
+ -- idem but round up to +infinity (s_round_up = u_round)
+ function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- idem round up for unsigned values
+ function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector;
+ -- idem round up for unsigned values
+ function u_round( vec : std_logic_vector; n : natural) return std_logic_vector;
+
+ -- interpret w bit unsigned u as w bit signed, and remove any MSbits
+ function u_to_s(u : natural; w : natural) return integer;
+ -- interpret w bit signed s as w bit unsigned, and remove any MSbits
+ function s_to_u(s : integer; w : natural) return natural;
+
+ -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
+ function u_wrap(u : natural; w : natural) return natural;
+ -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
+ function s_wrap(s : integer; w : natural) return integer;
+
+ -- if s < max return s, else return n
+ function u_clip(u : natural; max : natural) return natural;
+ -- if s <= min return min, else if s >= max return max, else return s
+ function s_clip(s : integer; max : natural; min : integer) return integer;
+ -- if s <= -max return -max, else if s >= max return max, else return s
+ function s_clip(s : integer; max : natural ) return integer;
+
+ -- convert endianity from host to network, sz in symbols of width w
+ function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector;
+ -- convert endianity from host to network, sz in bytes
+ function hton(a : std_logic_vector; sz : natural) return std_logic_vector;
+ -- convert endianity from host to network, for all bytes in a
+ function hton(a : std_logic_vector ) return std_logic_vector;
+ -- convert endianity from network to host, sz in bytes, ntoh() = hton()
+ function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector;
+ -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
+ function ntoh(a : std_logic_vector ) return std_logic_vector;
+
+ -- bit flip a vector, map a[h:0] to [0:h]
+ function flip(a : std_logic_vector) return std_logic_vector;
+ -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ function flip(a, w : natural) return natural;
function flip(a : t_slv_32_arr) return t_slv_32_arr;
function flip(a : t_integer_arr) return t_integer_arr;
function flip(a : t_natural_arr) return t_natural_arr;
function flip(a : t_nat_natural_arr) return t_nat_natural_arr;
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
- function transpose(a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
+ -- transpose a vector, map a[i*row+j] to output index [j*col+i]
+ function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector;
+ -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose(a, row, col : natural) return natural;
function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
@@ -499,9 +648,11 @@ package body common_pkg is
-- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
- return 0; -- Get NULL array
+ -- Get NULL array
+ return 0;
elsif n = 1 then
- return 1; -- avoid NULL array
+ -- avoid NULL array
+ return 1;
else
return true_log2(n);
end if;
@@ -553,7 +704,8 @@ package body common_pkg is
function ceil_div(n : unsigned; d: natural) return unsigned is
begin
- return n / d + sel_a_b(n mod d = 0, 0, 1); -- "/" returns same width as n
+ -- "/" returns same width as n
+ return n / d + sel_a_b(n mod d = 0, 0, 1);
end;
function ceil_value(n : unsigned; d: natural) return unsigned is
@@ -561,7 +713,8 @@ package body common_pkg is
variable p : unsigned(2 * w - 1 downto 0);
begin
p := ceil_div(n, d) * d;
- return p(w - 1 downto 0); -- return same width as n
+ -- return same width as n
+ return p(w - 1 downto 0);
end;
function floor_value(n : unsigned; d: natural) return unsigned is
@@ -569,7 +722,8 @@ package body common_pkg is
variable p : unsigned(2 * w - 1 downto 0);
begin
p := (n / d) * d;
- return p(w - 1 downto 0); -- return same width as n
+ -- return same width as n
+ return p(w - 1 downto 0);
end;
function slv(n: in std_logic) return std_logic_vector is
@@ -664,7 +818,8 @@ package body common_pkg is
-- Instead use binary tree to determine result with smallest combinatorial delay that depends on log2(slv'LENGTH)
constant c_slv_w : natural := slv'length;
constant c_nof_stages : natural := ceil_log2(c_slv_w);
- constant c_w : natural := 2**c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ constant c_w : natural := 2**c_nof_stages;
type t_stage_arr is array (-1 to c_nof_stages - 1) of std_logic_vector(c_w - 1 downto 0);
variable v_stage_arr : t_stage_arr;
variable v_result : std_logic := '0';
@@ -676,7 +831,8 @@ package body common_pkg is
else
assert true report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
end if;
- v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
+ -- any unused input c_w : c_slv_w bits have void default value
+ v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv;
for J in 0 to c_nof_stages - 1 loop
for I in 0 to c_w / (2**(J + 1)) - 1 loop
if operation = "AND" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
@@ -738,7 +894,8 @@ package body common_pkg is
end;
function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic is
- variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
+ -- map to fixed range
+ variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat;
variable v_result : std_logic := '1';
begin
for I in 0 to wi - 1 loop
@@ -750,7 +907,8 @@ package body common_pkg is
end;
function matrix_or(mat : t_sl_matrix; wi, wj : natural) return std_logic is
- variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
+ -- map to fixed range
+ variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat;
variable v_result : std_logic := '0';
begin
for I in 0 to wi - 1 loop
@@ -1513,7 +1671,8 @@ package body common_pkg is
if use_f = true then v_lo := v_lo + f_w; end if;
when others => report "Unknown common_pkg func_slv_extract argument" severity FAILURE;
end case;
- return vec(v_w - 1 + v_lo downto v_lo); -- extracted slv
+ -- extracted slv
+ return vec(v_w - 1 + v_lo downto v_lo);
end func_slv_extract;
function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
@@ -1576,9 +1735,11 @@ package body common_pkg is
begin
-- extend sign bit or keep LS part
if w > s'length then
- return resize(s, w); -- extend sign bit
+ -- extend sign bit
+ return resize(s, w);
else
- return signed(resize(unsigned(s), w)); -- keep LSbits (= vec[w-1:0])
+ -- keep LSbits (= vec[w-1:0])
+ return signed(resize(unsigned(s), w));
end if;
end;
@@ -1627,10 +1788,12 @@ package body common_pkg is
begin
if dec < 0 then
v_dec := -dec;
- return std_logic_vector(unsigned(vec) - v_dec); -- uses function "-" (L : UNSIGNED, R : NATURAL), there is no function + with R : INTEGER argument
+ -- uses function "-" (L : UNSIGNED, R : NATURAL), there is no function + with R : INTEGER argument
+ return std_logic_vector(unsigned(vec) - v_dec);
else
v_dec := dec;
- return std_logic_vector(unsigned(vec) + v_dec); -- uses function "+" (L : UNSIGNED, R : NATURAL)
+ -- uses function "+" (L : UNSIGNED, R : NATURAL)
+ return std_logic_vector(unsigned(vec) + v_dec);
end if;
end;
@@ -1642,7 +1805,8 @@ package body common_pkg is
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
variable v_dec : integer;
begin
- return std_logic_vector(signed(vec) + v_dec); -- uses function "+" (L : SIGNED, R : INTEGER)
+ -- uses function "+" (L : SIGNED, R : INTEGER)
+ return std_logic_vector(signed(vec) + v_dec);
end;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector is
@@ -1703,18 +1867,22 @@ package body common_pkg is
function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
- return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift)); -- fill zeros from right
+ -- fill zeros from right
+ return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift));
else
- return std_logic_vector(SHIFT_RIGHT(unsigned(vec), shift)); -- fill zeros from left
+ -- fill zeros from left
+ return std_logic_vector(SHIFT_RIGHT(unsigned(vec), shift));
end if;
end;
function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
- return std_logic_vector(SHIFT_LEFT(signed(vec), -shift)); -- same as SHIFT_LEFT for UNSIGNED
+ -- same as SHIFT_LEFT for UNSIGNED
+ return std_logic_vector(SHIFT_LEFT(signed(vec), -shift));
else
- return std_logic_vector(SHIFT_RIGHT(signed(vec), shift)); -- extend sign
+ -- extend sign
+ return std_logic_vector(SHIFT_RIGHT(signed(vec), shift));
end if;
end;
@@ -1738,7 +1906,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ v_res(v_res'high) := not v_res(v_res'high);
return v_res;
end;
@@ -1748,7 +1917,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ -- keep MS part
+ v_res := v_vec(c_vec_w - 1 downto n);
return v_res;
end;
@@ -1758,8 +1928,10 @@ package body common_pkg is
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_trunc := truncate(vec, n); -- first keep MS part
- v_res := RESIZE_UVEC(v_trunc, w); -- then keep LS part or left extend with '0'
+ -- first keep MS part
+ v_trunc := truncate(vec, n);
+ -- then keep LS part or left extend with '0'
+ v_res := RESIZE_UVEC(v_trunc, w);
return v_res;
end;
@@ -1769,8 +1941,10 @@ package body common_pkg is
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_trunc := truncate(vec, n); -- first keep MS part
- v_res := RESIZE_SVEC(v_trunc, w); -- then keep sign bit and LS part or left extend sign bit
+ -- first keep MS part
+ v_trunc := truncate(vec, n);
+ -- then keep sign bit and LS part or left extend sign bit
+ v_res := RESIZE_SVEC(v_trunc, w);
return v_res;
end;
@@ -1779,7 +1953,8 @@ package body common_pkg is
constant c_scale_w : natural := c_vec_w + n;
variable v_res : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
begin
- v_res(c_scale_w - 1 downto n) := vec; -- scale by adding n zero bits at the right
+ -- scale by adding n zero bits at the right
+ v_res(c_scale_w - 1 downto n) := vec;
return v_res;
end;
@@ -1789,8 +1964,10 @@ package body common_pkg is
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_scale(c_scale_w - 1 downto n) := vec; -- first scale by adding n zero bits at the right
- v_res := RESIZE_UVEC(v_scale, w); -- then keep LS part or left extend with '0'
+ -- first scale by adding n zero bits at the right
+ v_scale(c_scale_w - 1 downto n) := vec;
+ -- then keep LS part or left extend with '0'
+ v_res := RESIZE_UVEC(v_scale, w);
return v_res;
end;
@@ -1800,8 +1977,10 @@ package body common_pkg is
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_scale(c_scale_w - 1 downto n) := vec; -- first scale by adding n zero bits at the right
- v_res := RESIZE_SVEC(v_scale, w); -- then keep LS part or left extend sign bit
+ -- first scale by adding n zero bits at the right
+ v_scale(c_scale_w - 1 downto n) := vec;
+ -- then keep LS part or left extend sign bit
+ v_res := RESIZE_SVEC(v_scale, w);
return v_res;
end;
@@ -1854,32 +2033,40 @@ package body common_pkg is
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
constant c_one : signed(c_in_w - 1 downto 0) := to_signed(1, c_in_w);
- constant c_half : signed(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1); -- = 2**(n-1)
- constant c_max : signed(c_in_w - 1 downto 0) := signed('0' & c_slv1(c_in_w - 2 downto 0)) - c_half; -- = 2**(c_in_w-1)-1 - c_half
- constant c_clip : signed(c_out_w - 1 downto 0) := signed('0' & c_slv1(c_out_w - 2 downto 0)); -- = 2**(c_out_w-1)-1
+ -- = 2**(n-1)
+ constant c_half : signed(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1);
+ -- = 2**(c_in_w-1)-1 - c_half
+ constant c_max : signed(c_in_w - 1 downto 0) := signed('0' & c_slv1(c_in_w - 2 downto 0)) - c_half;
+ -- = 2**(c_out_w-1)-1
+ constant c_clip : signed(c_out_w - 1 downto 0) := signed('0' & c_slv1(c_out_w - 2 downto 0));
variable v_in : signed(c_in_w - 1 downto 0);
variable v_out : signed(c_out_w - 1 downto 0);
begin
v_in := signed(vec);
if n > 0 then
if clip = true and v_in > c_max then
- v_out := c_clip; -- Round clip to maximum positive to avoid wrap to negative
+ -- Round clip to maximum positive to avoid wrap to negative
+ v_out := c_clip;
else
if vec(vec'high) = '0' then
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half + 0, n), c_out_w); -- Round up for positive
+ -- Round up for positive
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half + 0, n), c_out_w);
else
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half - 1, n), c_out_w); -- Round down for negative
+ -- Round down for negative
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half - 1, n), c_out_w);
end if;
end if;
else
- v_out := RESIZE_NUM(v_in, c_out_w); -- NOP
+ -- NOP
+ v_out := RESIZE_NUM(v_in, c_out_w);
end if;
return std_logic_vector(v_out);
end;
function s_round(vec : std_logic_vector; n : natural) return std_logic_vector is
begin
- return s_round(vec, n, false); -- no round clip
+ -- no round clip
+ return s_round(vec, n, false);
end;
-- An alternative is to always round up, also for negative numbers (i.e. s_round_up = u_round).
@@ -1890,7 +2077,8 @@ package body common_pkg is
function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector is
begin
- return u_round(vec, n, false); -- no round clip
+ -- no round clip
+ return u_round(vec, n, false);
end;
-- Unsigned numbers are round up (almost same as s_round, but without the else on negative vec)
@@ -1899,50 +2087,61 @@ package body common_pkg is
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
constant c_one : unsigned(c_in_w - 1 downto 0) := to_unsigned(1, c_in_w);
- constant c_half : unsigned(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1); -- = 2**(n-1)
- constant c_max : unsigned(c_in_w - 1 downto 0) := unsigned(c_slv1(c_in_w - 1 downto 0)) - c_half; -- = 2**c_in_w-1 - c_half
- constant c_clip : unsigned(c_out_w - 1 downto 0) := unsigned(c_slv1(c_out_w - 1 downto 0)); -- = 2**c_out_w-1
+ -- = 2**(n-1)
+ constant c_half : unsigned(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1);
+ -- = 2**c_in_w-1 - c_half
+ constant c_max : unsigned(c_in_w - 1 downto 0) := unsigned(c_slv1(c_in_w - 1 downto 0)) - c_half;
+ -- = 2**c_out_w-1
+ constant c_clip : unsigned(c_out_w - 1 downto 0) := unsigned(c_slv1(c_out_w - 1 downto 0));
variable v_in : unsigned(c_in_w - 1 downto 0);
variable v_out : unsigned(c_out_w - 1 downto 0);
begin
v_in := unsigned(vec);
if n > 0 then
if clip = true and v_in > c_max then
- v_out := c_clip; -- Round clip to +max to avoid wrap to 0
+ -- Round clip to +max to avoid wrap to 0
+ v_out := c_clip;
else
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half, n), c_out_w); -- Round up
+ -- Round up
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half, n), c_out_w);
end if;
else
- v_out := RESIZE_NUM(v_in, c_out_w); -- NOP
+ -- NOP
+ v_out := RESIZE_NUM(v_in, c_out_w);
end if;
return std_logic_vector(v_out);
end;
function u_round(vec : std_logic_vector; n : natural) return std_logic_vector is
begin
- return u_round(vec, n, false); -- no round clip
+ -- no round clip
+ return u_round(vec, n, false);
end;
function u_to_s(u : natural; w : natural) return integer is
- variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32);
begin
return TO_SINT(v_u(w - 1 downto 0));
end;
function s_to_u(s : integer; w : natural) return natural is
- variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32);
begin
return TO_UINT(v_s(w - 1 downto 0));
end;
function u_wrap(u : natural; w : natural) return natural is
- variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32);
begin
return TO_UINT(v_u(w - 1 downto 0));
end;
function s_wrap(s : integer; w : natural) return integer is
- variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32);
begin
return TO_SINT(v_s(w - 1 downto 0));
end;
@@ -1975,8 +2174,10 @@ package body common_pkg is
end;
function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector is
- variable v_a : std_logic_vector(a'length - 1 downto 0) := a; -- map a to range [h:0]
- variable v_b : std_logic_vector(a'length - 1 downto 0) := a; -- default b = a
+ -- map a to range [h:0]
+ variable v_a : std_logic_vector(a'length - 1 downto 0) := a;
+ -- default b = a
+ variable v_b : std_logic_vector(a'length - 1 downto 0) := a;
variable vL : natural;
variable vK : natural;
begin
@@ -1992,23 +2193,27 @@ package body common_pkg is
function hton(a : std_logic_vector; sz : natural) return std_logic_vector is
begin
- return hton(a, c_byte_w, sz); -- symbol width w = c_byte_w = 8
+ -- symbol width w = c_byte_w = 8
+ return hton(a, c_byte_w, sz);
end function;
function hton(a : std_logic_vector) return std_logic_vector is
constant c_sz : natural := a'length / c_byte_w;
begin
- return hton(a, c_byte_w, c_sz); -- symbol width w = c_byte_w = 8
+ -- symbol width w = c_byte_w = 8
+ return hton(a, c_byte_w, c_sz);
end function;
function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector is
begin
- return hton(a, sz); -- i.e. ntoh() = hton()
+ -- i.e. ntoh() = hton()
+ return hton(a, sz);
end function;
function ntoh(a : std_logic_vector) return std_logic_vector is
begin
- return hton(a); -- i.e. ntoh() = hton()
+ -- i.e. ntoh() = hton()
+ return hton(a);
end function;
function flip(a : std_logic_vector) return std_logic_vector is
@@ -2070,17 +2275,21 @@ package body common_pkg is
variable vIn : std_logic_vector(a'length - 1 downto 0);
variable vOut : std_logic_vector(a'length - 1 downto 0);
begin
- vIn := a; -- map input vector to h:0 range
- vOut := vIn; -- default leave any unused MSbits the same
+ -- map input vector to h:0 range
+ vIn := a;
+ -- default leave any unused MSbits the same
+ vOut := vIn;
for J in 0 to row - 1 loop
for I in 0 to col - 1 loop
- vOut(J * col + I) := vIn(I * row + J); -- transpose vector, map input index [i*row+j] to output index [j*col+i]
+ -- transpose vector, map input index [i*row+j] to output index [j*col+i]
+ vOut(J * col + I) := vIn(I * row + J);
end loop;
end loop;
return vOut;
end function;
- function transpose(a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
+ -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose(a, row, col : natural) return natural is
variable vI : natural;
variable vJ : natural;
begin
@@ -2089,16 +2298,20 @@ package body common_pkg is
return vJ * col + vI;
end;
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
+ -- Calculate input_w in multiples as close as possible to max_out_w
+ function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is
-- Examples: split_w(256, 8, 32) = 32; split_w(16, 8, 32) = 16; split_w(72, 8, 32) = 18; -- Input_w must be multiple of 2.
variable r: natural;
begin
r := input_w;
- for i in 1 to ceil_log2(input_w) loop -- Useless to divide the number beyond this
+ -- Useless to divide the number beyond this
+ for i in 1 to ceil_log2(input_w) loop
if r <= max_out_w and r >= min_out_w then
return r;
- elsif i = ceil_log2(input_w) then -- last iteration
- return 0; -- Indicates wrong values were used
+ -- last iteration
+ elsif i = ceil_log2(input_w) then
+ -- Indicates wrong values were used
+ return 0;
end if;
r := r / 2;
end loop;
@@ -2197,8 +2410,10 @@ package body common_pkg is
variable v_odd : boolean;
variable v_even : boolean;
begin
- v_odd := (I mod 2 = 1) and (J mod 2 = 1); -- for odd stage at each odd row
- v_even := (I mod 2 = 0) and (J mod 2 = 0); -- for even stage at each even row
+ -- for odd stage at each odd row
+ v_odd := (I mod 2 = 1) and (J mod 2 = 1);
+ -- for even stage at each even row
+ v_even := (I mod 2 = 0) and (J mod 2 = 0);
return v_odd or v_even;
end func_common_reorder2_is_there;
@@ -2228,7 +2443,8 @@ package body common_pkg is
-- for the active two port reorder cells use the setting at index v_K from the select setting array
v_nof_odd_stages := I / 2;
v_nof_even_stages := (I - 1) / 2;
- v_offset := (J - 1) / 2; -- suits both odd stage and even stage
+ -- suits both odd stage and even stage
+ v_offset := (J - 1) / 2;
v_K := v_nof_odd_stages * c_nof_reorder2_per_odd_stage + v_nof_even_stages * c_nof_reorder2_per_even_stage + v_offset;
end if;
return v_K;
@@ -2237,7 +2453,8 @@ package body common_pkg is
-- Get the select setting for the reorder2 cell on stage I and row J in a reorder network with N stages
function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural is
constant c_nof_select : natural := select_arr'length;
- constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
+ -- force range downto 0
+ constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr;
variable v_sel : natural;
variable v_K : integer;
begin
@@ -2252,11 +2469,13 @@ package body common_pkg is
-- Determine the inverse of a reorder network by using two reorder networks in series
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr is
constant c_nof_select : natural := select_arr'length;
- constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
+ -- force range downto 0
+ constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr;
variable v_sel : natural;
variable v_Ki : integer;
variable v_Ii : natural;
- variable v_inverse_arr : t_natural_arr(2 * c_nof_select - 1 downto 0) := (others => 0); -- default set identity for the reorder2 cells in both reorder instances
+ -- default set identity for the reorder2 cells in both reorder instances
+ variable v_inverse_arr : t_natural_arr(2 * c_nof_select - 1 downto 0) := (others => 0);
begin
-- the inverse select consists of inverse_in reorder and inverse_out reorder in series
if N mod 2 = 1 then
@@ -2276,7 +2495,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ -- stage 1 of the inverse_out reorder
+ v_Ki := c_nof_select + K;
v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index 7b6d1a2da0ec2558d87aa708358be0b79c70944d..dc48b2f8f8d20d5ee0c491104976d7126bb80f02 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -48,35 +48,59 @@ package dp_stream_pkg is
-- This grouping is useful for functions that operate on a t_dp_sosi signal.
-- * The info fields are valid at the sop or at the eop, but typically they hold their last active value to avoid unnessary
-- toggling and to ease viewing in the wave window.
- constant c_dp_stream_bsn_w : natural := 64; -- 64 is sufficient to count blocks of data for years
- constant c_dp_stream_data_w : natural := 768; -- 72 is sufficient for max word 8 * 9-bit. 576 supports half rate DDR4 bus data width. The current 768 is enough for wide single clock SLVs (e.g. headers)
- constant c_dp_stream_dsp_data_w : natural := 64; -- 64 is sufficient for DSP data, including complex power accumulates
- constant c_dp_stream_empty_w : natural := 16; -- 8 is sufficient for max 256 symbols per data word, still use 16 bit to be able to count c_dp_stream_data_w in bits
- constant c_dp_stream_channel_w : natural := 32; -- 32 is sufficient for several levels of hierarchy in mapping types of streams on to channels
- constant c_dp_stream_error_w : natural := 32; -- 32 is sufficient for several levels of hierarchy in mapping error numbers, e.g. 32 different one-hot encoded errors, bit [0] = 0 = OK
-
- constant c_dp_stream_ok : natural := 0; -- SOSI err field OK value
- constant c_dp_stream_err : natural := 1; -- SOSI err field error value /= OK
-
- constant c_dp_stream_rl : natural := 1; -- SISO default data path stream ready latency RL = 1
-
- type t_dp_siso is record -- Source In or Sink Out
- ready : std_logic; -- fine cycle based flow control using ready latency RL >= 0
- xon : std_logic; -- coarse typically block based flow control using xon/xoff
+ -- 64 is sufficient to count blocks of data for years
+ constant c_dp_stream_bsn_w : natural := 64;
+ -- 72 is sufficient for max word 8 * 9-bit. 576 supports half rate DDR4 bus data width. The current 768 is enough for wide single clock SLVs (e.g. headers)
+ constant c_dp_stream_data_w : natural := 768;
+ -- 64 is sufficient for DSP data, including complex power accumulates
+ constant c_dp_stream_dsp_data_w : natural := 64;
+ -- 8 is sufficient for max 256 symbols per data word, still use 16 bit to be able to count c_dp_stream_data_w in bits
+ constant c_dp_stream_empty_w : natural := 16;
+ -- 32 is sufficient for several levels of hierarchy in mapping types of streams on to channels
+ constant c_dp_stream_channel_w : natural := 32;
+ -- 32 is sufficient for several levels of hierarchy in mapping error numbers, e.g. 32 different one-hot encoded errors, bit [0] = 0 = OK
+ constant c_dp_stream_error_w : natural := 32;
+
+ -- SOSI err field OK value
+ constant c_dp_stream_ok : natural := 0;
+ -- SOSI err field error value /= OK
+ constant c_dp_stream_err : natural := 1;
+
+ -- SISO default data path stream ready latency RL = 1
+ constant c_dp_stream_rl : natural := 1;
+
+ -- Source In or Sink Out
+ type t_dp_siso is record
+ -- fine cycle based flow control using ready latency RL >= 0
+ ready : std_logic;
+ -- coarse typically block based flow control using xon/xoff
+ xon : std_logic;
end record;
- type t_dp_sosi is record -- Source Out or Sink In
- sync : std_logic; -- ctrl
- bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0); -- info at sop (block sequence number)
- data : std_logic_vector(c_dp_stream_data_w - 1 downto 0); -- data
- re : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0); -- data
- im : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0); -- data
- valid : std_logic; -- ctrl
- sop : std_logic; -- ctrl
- eop : std_logic; -- ctrl
- empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0); -- info at eop
- channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0); -- info at sop
- err : std_logic_vector(c_dp_stream_error_w - 1 downto 0); -- info at eop (name field 'err' to avoid the 'error' keyword)
+ -- Source Out or Sink In
+ type t_dp_sosi is record
+ -- ctrl
+ sync : std_logic;
+ -- info at sop (block sequence number)
+ bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ -- data
+ data : std_logic_vector(c_dp_stream_data_w - 1 downto 0);
+ -- data
+ re : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0);
+ -- data
+ im : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0);
+ -- ctrl
+ valid : std_logic;
+ -- ctrl
+ sop : std_logic;
+ -- ctrl
+ eop : std_logic;
+ -- info at eop
+ empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0);
+ -- info at sop
+ channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0);
+ -- info at eop (name field 'err' to avoid the 'error' keyword)
+ err : std_logic_vector(c_dp_stream_error_w - 1 downto 0);
end record;
-- Initialise signal declarations with c_dp_stream_rst/rdy to ease the interpretation of slv fields with unused bits
@@ -240,29 +264,43 @@ package dp_stream_pkg is
-- signed data in the simulation wave window it is easier to use sign extension in the record field. Therefore TO_DP_SDATA
-- and RESIZE_DP_SDATA are defined as well.
function TO_DP_BSN( n : natural) return std_logic_vector;
- function TO_DP_DATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
- function TO_DP_SDATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
- function TO_DP_UDATA( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector; -- for re and im fields, signed data
- function TO_DP_DSP_UDATA(n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
+ -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
+ function TO_DP_DATA( n : integer) return std_logic_vector;
+ -- use integer to support 32 bit range and signed
+ function TO_DP_SDATA( n : integer) return std_logic_vector;
+ -- alias of TO_DP_DATA()
+ function TO_DP_UDATA( n : integer) return std_logic_vector;
+ -- for re and im fields, signed data
+ function TO_DP_DSP_DATA(n : integer) return std_logic_vector;
+ -- for re and im fields, unsigned data (useful to carry indices)
+ function TO_DP_DSP_UDATA(n: integer) return std_logic_vector;
function TO_DP_EMPTY( n : natural) return std_logic_vector;
function TO_DP_CHANNEL( n : natural) return std_logic_vector;
function TO_DP_ERROR( n : natural) return std_logic_vector;
function RESIZE_DP_BSN( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
- function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
- function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
+ -- set unused MSBits to '0'
+ function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector;
+ -- sign extend unused MSBits
+ function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector;
+ -- set unused MSBits to 'X'
+ function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector;
+ -- sign extend unused MSBits of re and im fields
+ function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_EMPTY( vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_CHANNEL( vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_ERROR( vec : std_logic_vector) return std_logic_vector;
- function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
- function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
+ -- unsigned vec(w-1:0) + dec
+ function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
+ -- signed vec(w-1:0) + dec
+ function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
+ -- signed vec(w-1:0) + dec
+ function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
- function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+ -- replicate seq as often as fits in c_dp_stream_data_w
+ function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector;
+ -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+ function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector;
function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
@@ -332,12 +370,16 @@ package dp_stream_pkg is
-- Functions to combinatorially handle channels
-- Note that the *_select and *_remove function are equivalent to dp_demux with g_combined=TRUE
- function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
+ -- select channel nr, add the channel field
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
+ -- select channel nr, skip the channel field
+ function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
+ -- skip channel nr
+ function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
-- Functions to combinatorially handle the error field
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
+ -- force err = 0, is OK
+ function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi;
-- Functions to combinatorially handle the BSN field
function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
@@ -359,11 +401,15 @@ package dp_stream_pkg is
-- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
-- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ -- data_order_im_re = TRUE
+ function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi;
+ -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi;
function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ -- data_order_im_re = TRUE
+ function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi;
+ -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
@@ -373,8 +419,10 @@ package dp_stream_pkg is
function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
-- Concatenate the data and complex re,im fields from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
+ -- Concat SOSI_ARR data into single SOSI
+ function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi;
+ -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr;
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
-- . data_representation = "SIGNED" treat sosi.data field as signed
@@ -389,8 +437,10 @@ package dp_stream_pkg is
function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
-- Deconcatenate data and complex re,im fields from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
+ -- Deconcat SOSI data
+ function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr;
+ -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso;
end dp_stream_pkg;
@@ -431,7 +481,8 @@ package body dp_stream_pkg is
signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
- ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
+ -- SLV is used as an array: nof_streams*(0..c_ready_latency)
+ ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready;
end loop;
-- Register siso.ready in c_ready_latency registers
if rising_edge(clk) then
@@ -578,11 +629,14 @@ package body dp_stream_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0);
begin
v_data := RESIZE_UVEC(data, c_vec_w);
- v_seq := v_data(seq_w - 1 downto 0); -- low data part is the v_seq
- v_vec(seq_w - 1 downto 0) := v_seq; -- keep v_seq at low part of return value
+ -- low data part is the v_seq
+ v_seq := v_data(seq_w - 1 downto 0);
+ -- keep v_seq at low part of return value
+ v_vec(seq_w - 1 downto 0) := v_seq;
if c_nof_replications > 1 then
for I in 1 to c_nof_replications - 1 loop
- v_vec((I + 1) * seq_w - 1 downto I * seq_w) := v_data((I + 1) * seq_w - 1 downto I * seq_w) xor v_seq; -- set return bit to '1' for high part data bits that do not match low part v_seq
+ -- set return bit to '1' for high part data bits that do not match low part v_seq
+ v_vec((I + 1) * seq_w - 1 downto I * seq_w) := v_data((I + 1) * seq_w - 1 downto I * seq_w) xor v_seq;
end loop;
end if;
return v_vec(c_data_w - 1 downto 0);
@@ -612,8 +666,10 @@ package body dp_stream_pkg is
begin
assert nof_symbols_from_tail < vN report "func_dp_data_shift_first : no symbols from head" severity FAILURE;
-- use the other sosi from head_sosi
- v_sosi := head_sosi; -- I = nof_symbols_from_tail = 0
- for I in 1 to vN - 1 loop -- I > 0
+ -- I = nof_symbols_from_tail = 0
+ v_sosi := head_sosi;
+ -- I > 0
+ for I in 1 to vN - 1 loop
if nof_symbols_from_tail = I then
v_sosi.data(I * symbol_w - 1 downto 0) := tail_sosi.data(vN * symbol_w - 1 downto (vN - I) * symbol_w);
end if;
@@ -635,15 +691,18 @@ package body dp_stream_pkg is
end if;
-- use sosi data from both if 0 < nof_symbols_from_this < nof_symbols_per_data (i.e. 0 < I < vN)
- if vK < nof_symbols_per_data then -- I = vK = nof_symbols_from_this < vN
+ -- I = vK = nof_symbols_from_this < vN
+ if vK < nof_symbols_per_data then
-- Implementation using variable vK directly instead of via I in a LOOP
-- IF vK > 0 THEN
-- v_sosi.data(vN*symbol_w-1 DOWNTO vK*symbol_w) := prev_sosi.data((vN-vK)*symbol_w-1 DOWNTO 0);
-- v_sosi.data( vK*symbol_w-1 DOWNTO 0) := this_sosi.data( vN *symbol_w-1 DOWNTO (vN-vK)*symbol_w);
-- END IF;
-- Implementaion using LOOP vK rather than VARIABLE vK directly as index to help synthesis and avoid potential multiplier
- v_sosi.data := prev_sosi.data; -- I = vK = nof_symbols_from_this = 0
- for I in 1 to vN - 1 loop -- I = vK = nof_symbols_from_this > 0
+ -- I = vK = nof_symbols_from_this = 0
+ v_sosi.data := prev_sosi.data;
+ -- I = vK = nof_symbols_from_this > 0
+ for I in 1 to vN - 1 loop
if vK = I then
v_sosi.data(vN * symbol_w - 1 downto I * symbol_w) := prev_sosi.data((vN - I) * symbol_w - 1 downto 0);
v_sosi.data( I * symbol_w - 1 downto 0) := this_sosi.data( vN * symbol_w - 1 downto (vN - I) * symbol_w);
@@ -723,7 +782,8 @@ package body dp_stream_pkg is
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '1');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -738,14 +798,17 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_and(v_vec); -- return AND of the masked input fields
+ -- return AND of the masked input fields
+ return vector_and(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_and;
function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '1');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -762,9 +825,11 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_and(v_vec); -- return AND of the masked input fields
+ -- return AND of the masked input fields
+ return vector_and(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_and;
@@ -781,7 +846,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_and;
function func_dp_stream_arr_or(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '0');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -796,14 +862,17 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_or(v_vec); -- return OR of the masked input fields
+ -- return OR of the masked input fields
+ return vector_or(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_or;
function func_dp_stream_arr_or(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '0');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -820,9 +889,11 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_or(v_vec); -- return OR of the masked input fields
+ -- return OR of the masked input fields
+ return vector_or(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_or;
@@ -840,8 +911,10 @@ package body dp_stream_pkg is
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
- variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
- variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
+ -- default
+ variable v_dp : t_dp_siso_arr(dp'range) := dp;
+ -- map to ensure same range as for dp
+ variable v_slv : std_logic_vector(dp'range) := slv;
begin
for I in dp'range loop
if str = "READY" then v_dp(I).ready := v_slv(I);
@@ -853,8 +926,10 @@ package body dp_stream_pkg is
end func_dp_stream_arr_set;
function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- default
- variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
+ -- default
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
+ -- map to ensure same range as for dp
+ variable v_slv : std_logic_vector(dp'range) := slv;
begin
for I in dp'range loop
if str = "VALID" then v_dp(I).valid := v_slv(I);
@@ -1046,29 +1121,40 @@ package body dp_stream_pkg is
-- Functions to combinatorially hold the data fields and to set or reset the info and control fields in an sosi array
function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- v_dp := func_dp_stream_arr_set_info( v_dp, info); -- set sosi info
- v_dp := func_dp_stream_arr_set_control(v_dp, ctrl); -- set sosi ctrl
+ -- set sosi info
+ v_dp := func_dp_stream_arr_set_info( v_dp, info);
+ -- set sosi ctrl
+ v_dp := func_dp_stream_arr_set_control(v_dp, ctrl);
return v_dp;
end func_dp_stream_arr_combine_data_info_ctrl;
function func_dp_stream_arr_set_info(dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- set sosi info
- v_dp(I).bsn := info.bsn; -- sop
- v_dp(I).channel := info.channel; -- sop
- v_dp(I).empty := info.empty; -- eop
- v_dp(I).err := info.err; -- eop
+ -- set sosi info
+ for I in dp'range loop
+ -- sop
+ v_dp(I).bsn := info.bsn;
+ -- sop
+ v_dp(I).channel := info.channel;
+ -- eop
+ v_dp(I).empty := info.empty;
+ -- eop
+ v_dp(I).err := info.err;
end loop;
return v_dp;
end func_dp_stream_arr_set_info;
function func_dp_stream_arr_set_control(dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- set sosi control
+ -- set sosi control
+ for I in dp'range loop
v_dp(I).valid := ctrl.valid;
v_dp(I).sop := ctrl.sop;
v_dp(I).eop := ctrl.eop;
@@ -1078,9 +1164,11 @@ package body dp_stream_pkg is
end func_dp_stream_arr_set_control;
function func_dp_stream_arr_reset_control(dp : t_dp_sosi_arr) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- reset sosi control
+ -- reset sosi control
+ for I in dp'range loop
v_dp(I).valid := '0';
v_dp(I).sop := '0';
v_dp(I).eop := '0';
@@ -1090,7 +1178,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_reset_control;
function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi is
- variable v_dp : t_dp_sosi := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi := dp;
begin
-- reset sosi control
v_dp.valid := '0';
@@ -1102,7 +1191,8 @@ package body dp_stream_pkg is
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
- variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0'); -- init max v_bsn with minimum value
+ -- init max v_bsn with minimum value
+ variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0');
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1121,7 +1211,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_bsn_max;
function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
- variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1'); -- init min v_bsn with maximum value
+ -- init min v_bsn with maximum value
+ variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1');
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1142,7 +1233,8 @@ package body dp_stream_pkg is
-- Function to copy the BSN number of one valid stream to all other streams.
function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1200,10 +1292,12 @@ package body dp_stream_pkg is
end func_dp_stream_bsn_set;
function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
- variable v_rec : t_dp_sosi := data; -- Sosi data fields
+ -- Sosi data fields
+ variable v_rec : t_dp_sosi := data;
begin
-- Combine sosi data with the sosi info fields
- v_rec.sync := info.sync and data.sop; -- force sync only active at data.sop
+ -- force sync only active at data.sop
+ v_rec.sync := info.sync and data.sop;
v_rec.bsn := info.bsn;
v_rec.channel := info.channel;
v_rec.empty := info.empty;
@@ -1215,7 +1309,8 @@ package body dp_stream_pkg is
variable v_rec : t_dp_sosi_integer;
begin
v_rec.sync := slv_sosi.sync;
- v_rec.bsn := TO_UINT(slv_sosi.bsn(30 downto 0)); -- NATURAL'width = 31 bit
+ -- NATURAL'width = 31 bit
+ v_rec.bsn := TO_UINT(slv_sosi.bsn(30 downto 0));
v_rec.data := TO_SINT(slv_sosi.data(w - 1 downto 0));
v_rec.re := TO_SINT(slv_sosi.re(w - 1 downto 0));
v_rec.im := TO_SINT(slv_sosi.im(w - 1 downto 0));
@@ -1333,7 +1428,8 @@ package body dp_stream_pkg is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
- v_dp_arr(i) := func_dp_stream_complex_to_data(dp_arr(i), data_w, nof_data, data_order_im_re); -- nof_data per stream is 1
+ -- nof_data per stream is 1
+ v_dp_arr(i) := func_dp_stream_complex_to_data(dp_arr(i), data_w, nof_data, data_order_im_re);
end loop;
return v_dp_arr;
end;
@@ -1352,7 +1448,8 @@ package body dp_stream_pkg is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
- v_dp_arr(i) := func_dp_stream_data_to_complex(dp_arr(i), data_w, nof_data, data_order_im_re); -- nof_data per stream is 1
+ -- nof_data per stream is 1
+ v_dp_arr(i) := func_dp_stream_data_to_complex(dp_arr(i), data_w, nof_data, data_order_im_re);
end loop;
return v_dp_arr;
end;
@@ -1383,7 +1480,8 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
+ -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is
variable v_snk_out_arr : t_dp_siso_arr(nof_streams - 1 downto 0);
begin
for i in v_snk_out_arr'range loop
@@ -1398,7 +1496,8 @@ package body dp_stream_pkg is
constant c_compl_out_w : natural := out_w / 2;
variable v_src_out : t_dp_sosi := snk_in;
variable v_in_data : std_logic_vector(in_w - 1 downto 0);
- variable v_out_data : std_logic_vector(out_w - 1 downto 0) := (others => '0'); -- default set sosi.data to 0
+ -- default set sosi.data to 0
+ variable v_out_data : std_logic_vector(out_w - 1 downto 0) := (others => '0');
begin
v_src_out := snk_in;
v_src_out.data := (others => '0');
@@ -1406,10 +1505,12 @@ package body dp_stream_pkg is
v_src_out.im := (others => '0');
for i in 0 to nof_data - 1 loop
v_in_data := snk_in.data((i + 1) * in_w - 1 downto i * in_w);
- if data_representation = "UNSIGNED" then -- treat data as unsigned
+ -- treat data as unsigned
+ if data_representation = "UNSIGNED" then
v_out_data := RESIZE_UVEC(v_in_data, out_w);
else
- if data_representation = "SIGNED" then -- treat data as signed
+ -- treat data as signed
+ if data_representation = "SIGNED" then
v_out_data := RESIZE_SVEC(v_in_data, out_w);
else
-- treat data as complex
@@ -1467,7 +1568,8 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
+ -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is
begin
return src_out_arr(0);
end;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
index 103667575791b885ea6d707accd5dc6c04bcb535..86bd5f3ed9ef2f109669b4576b60ab58651ee0f0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
@@ -29,29 +29,39 @@ use dp_lib.dp_stream_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
- constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
- constant c_eth_empty_w : natural := c_tech_tse_empty_w; -- = ceil_log2(c_word_sz) = 2;
- constant c_eth_error_w : natural := c_tech_tse_error_w; -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
-
- constant c_eth_rx_ready_latency : natural := c_tech_tse_rx_ready_latency; -- = 2 = default when FIFO is used
- constant c_eth_tx_ready_latency : natural := c_tech_tse_tx_ready_latency; -- = 0, c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
- constant c_eth_ready_latency : natural := 1; -- = 1, fixed ETH module internal RL
+ -- = c_word_w
+ constant c_eth_data_w : natural := c_tech_tse_data_w;
+ -- = ceil_log2(c_word_sz) = 2;
+ constant c_eth_empty_w : natural := c_tech_tse_empty_w;
+ -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
+ constant c_eth_error_w : natural := c_tech_tse_error_w;
+
+ -- = 2 = default when FIFO is used
+ constant c_eth_rx_ready_latency : natural := c_tech_tse_rx_ready_latency;
+ -- = 0, c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
+ constant c_eth_tx_ready_latency : natural := c_tech_tse_tx_ready_latency;
+ -- = 1, fixed ETH module internal RL
+ constant c_eth_ready_latency : natural := 1;
-- Maximum feasible frame size
- constant c_eth_max_frame_sz : natural := 1024 * 9; -- 9 kByte fits 9020 = word align (2) + eth header (14) + maximum jumbo payload (9000) + CRC (4)
+ -- 9 kByte fits 9020 = word align (2) + eth header (14) + maximum jumbo payload (9000) + CRC (4)
+ constant c_eth_max_frame_sz : natural := 1024 * 9;
constant c_eth_max_frame_nof_words : natural := c_eth_max_frame_sz / c_word_sz;
- constant c_eth_max_frame_nof_words_w : natural := ceil_log2(c_eth_max_frame_nof_words); -- = 12 bit
+ -- = 12 bit
+ constant c_eth_max_frame_nof_words_w : natural := ceil_log2(c_eth_max_frame_nof_words);
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
-- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
- constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
+ -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
+ constant c_eth_frame_sz : natural := 1024 * 2;
-- when the module is used in an Nios II SOPC system
-- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
- constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
+ -- >= 9 bit, <= 12 bit
+ constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words);
type t_eth_data_arr is array (integer range <>) of std_logic_vector(c_eth_data_w - 1 downto 0);
@@ -79,8 +89,10 @@ package eth_pkg is
-- Definitions for eth demux udp
------------------------------------------------------------------------------
- constant c_eth_nof_udp_ports : natural := 4; -- support 2, 4, 8, ... UDP off-load ports
- constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1); -- + 1 for all other packets that go to the default port
+ -- support 2, 4, 8, ... UDP off-load ports
+ constant c_eth_nof_udp_ports : natural := 4;
+ -- + 1 for all other packets that go to the default port
+ constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1);
constant c_eth_nof_channels : natural := 2**c_eth_channel_w;
------------------------------------------------------------------------------
@@ -103,30 +115,46 @@ package eth_pkg is
-- . write/read back registers
type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
type t_eth_mm_reg_demux is record
- udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
- udp_ports : t_eth_demux_ports_arr; -- [15:0]
+ -- [16]
+ udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports);
+ -- [15:0]
+ udp_ports : t_eth_demux_ports_arr;
end record;
type t_eth_mm_reg_config is record
- udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- [15:0]
- ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- [31:0]
- mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- [15:0], [31:0]
+ -- [15:0]
+ udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- [31:0]
+ ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- [15:0], [31:0]
+ mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
end record;
type t_eth_mm_reg_control is record
- tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_request : std_logic; -- 1 bit
- tx_en : std_logic; -- 1 bit
- rx_en : std_logic; -- 1 bit
+ -- 12 bit
+ tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0);
+ -- 2 bit
+ tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0);
+ -- 1 bit
+ tx_request : std_logic;
+ -- 1 bit
+ tx_en : std_logic;
+ -- 1 bit
+ rx_en : std_logic;
end record;
- type t_eth_mm_reg_control_bi is record -- bit indices
- tx_nof_words : natural; -- [26:18]
- tx_empty : natural; -- [17:16]
- tx_request : natural; -- [2]
- tx_en : natural; -- [1]
- rx_en : natural; -- [0]
+ -- bit indices
+ type t_eth_mm_reg_control_bi is record
+ -- [26:18]
+ tx_nof_words : natural;
+ -- [17:16]
+ tx_empty : natural;
+ -- [2]
+ tx_request : natural;
+ -- [1]
+ tx_en : natural;
+ -- [0]
+ rx_en : natural;
end record;
constant c_eth_mm_reg_control_bi : t_eth_mm_reg_control_bi := (18, 16, 2, 1, 0);
@@ -146,36 +174,58 @@ package eth_pkg is
eth_mac_error : std_logic_vector(c_eth_error_w - 1 downto 0);
end record;
- type t_eth_mm_reg_frame_bi is record -- bit indices
- is_dhcp : natural; -- [15]
- is_udp_ctrl_port : natural; -- [14]
- is_udp : natural; -- [13]
- is_icmp : natural; -- [12]
- ip_address_match : natural; -- [11]
- ip_checksum_is_ok : natural; -- [10]
- is_ip : natural; -- [9]
- is_arp : natural; -- [8]
- mac_address_match : natural; -- [7]
- eth_mac_error : natural; -- [6] not used, [5:0] = TSE MAC error
+ -- bit indices
+ type t_eth_mm_reg_frame_bi is record
+ -- [15]
+ is_dhcp : natural;
+ -- [14]
+ is_udp_ctrl_port : natural;
+ -- [13]
+ is_udp : natural;
+ -- [12]
+ is_icmp : natural;
+ -- [11]
+ ip_address_match : natural;
+ -- [10]
+ ip_checksum_is_ok : natural;
+ -- [9]
+ is_ip : natural;
+ -- [8]
+ is_arp : natural;
+ -- [7]
+ mac_address_match : natural;
+ -- [6] not used, [5:0] = TSE MAC error
+ eth_mac_error : natural;
end record;
constant c_eth_mm_reg_frame_bi : t_eth_mm_reg_frame_bi := (15, 14, 13, 12, 11, 10, 9, 8, 7, 0);
constant c_eth_mm_reg_frame_rst : t_eth_mm_reg_frame := ('0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'));
type t_eth_mm_reg_status is record
- rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_avail : std_logic; -- 1 bit
- tx_done : std_logic; -- 1 bit
- rx_avail : std_logic; -- 1 bit
+ -- 12 bit
+ rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0);
+ -- 2 bit
+ rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0);
+ -- 1 bit
+ tx_avail : std_logic;
+ -- 1 bit
+ tx_done : std_logic;
+ -- 1 bit
+ rx_avail : std_logic;
end record;
- type t_eth_mm_reg_status_bi is record -- bit indices
- rx_nof_words : natural; -- [26:18]
- rx_empty : natural; -- [17:16]
- tx_avail : natural; -- [2]
- tx_done : natural; -- [1]
- rx_avail : natural; -- [0]
+ -- bit indices
+ type t_eth_mm_reg_status_bi is record
+ -- [26:18]
+ rx_nof_words : natural;
+ -- [17:16]
+ rx_empty : natural;
+ -- [2]
+ tx_avail : natural;
+ -- [1]
+ tx_done : natural;
+ -- [0]
+ rx_avail : natural;
end record;
constant c_eth_mm_reg_status_bi : t_eth_mm_reg_status_bi := (18, 16, 2, 1, 0);
@@ -202,7 +252,8 @@ package eth_pkg is
c_eth_reg_control_nof_words +
c_eth_reg_frame_nof_words +
c_eth_reg_status_nof_words;
- constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
+ -- + 1 for c_eth_continue_wi
+ constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1);
------------------------------------------------------------------------------
-- Definitions for ETH Rx packet buffer and Tx packet buffer
@@ -223,8 +274,10 @@ package body eth_pkg is
begin
-- Demux UDP MM registers
for I in 1 to c_eth_nof_udp_ports loop
- v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w); -- [16] = UDP port enable
- v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w); -- [15:0] = UDP port number
+ -- [16] = UDP port enable
+ v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w);
+ -- [15:0] = UDP port number
+ v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w);
end loop;
return v_reg;
@@ -233,10 +286,13 @@ package body eth_pkg is
function func_eth_mm_reg_demux(mm_reg : t_eth_mm_reg_demux) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_demux_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
+ -- rsvd
+ v_reg := (others => '0');
for I in 1 to c_eth_nof_udp_ports loop
- v_reg(c_network_udp_port_w + (I - 1) * c_word_w) := mm_reg.udp_ports_en(I); -- [16] = UDP port enable
- v_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w) := mm_reg.udp_ports(I); -- [15:0] = UDP port number
+ -- [16] = UDP port enable
+ v_reg(c_network_udp_port_w + (I - 1) * c_word_w) := mm_reg.udp_ports_en(I);
+ -- [15:0] = UDP port number
+ v_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w) := mm_reg.udp_ports(I);
end loop;
return v_reg;
end func_eth_mm_reg_demux;
@@ -245,21 +301,30 @@ package body eth_pkg is
function func_eth_mm_reg_config(mm_reg : std_logic_vector) return t_eth_mm_reg_config is
variable v_reg : t_eth_mm_reg_config;
begin
- v_reg.udp_port := mm_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w); -- [15:0] = control UDP port number
- v_reg.ip_address := mm_reg( 3 * c_word_w - 1 downto 2 * c_word_w); -- [31:0] = this node IP address
- v_reg.mac_address(47 downto 32) := mm_reg( c_halfword_w + c_word_w - 1 downto c_word_w); -- [47:32] = this node MAC address
- v_reg.mac_address(31 downto 0) := mm_reg( c_word_w - 1 downto 0); -- [31:0] = this node MAC address
+ -- [15:0] = control UDP port number
+ v_reg.udp_port := mm_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w);
+ -- [31:0] = this node IP address
+ v_reg.ip_address := mm_reg( 3 * c_word_w - 1 downto 2 * c_word_w);
+ -- [47:32] = this node MAC address
+ v_reg.mac_address(47 downto 32) := mm_reg( c_halfword_w + c_word_w - 1 downto c_word_w);
+ -- [31:0] = this node MAC address
+ v_reg.mac_address(31 downto 0) := mm_reg( c_word_w - 1 downto 0);
return v_reg;
end func_eth_mm_reg_config;
function func_eth_mm_reg_config(mm_reg : t_eth_mm_reg_config) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_config_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w) := mm_reg.udp_port; -- [15:0] = control UDP port number
- v_reg( 3 * c_word_w - 1 downto 2 * c_word_w) := mm_reg.ip_address; -- [31:0] = this node IP address
- v_reg( c_halfword_w + c_word_w - 1 downto c_word_w) := mm_reg.mac_address(47 downto 32); -- [47:32] = this node MAC address
- v_reg( c_word_w - 1 downto 0) := mm_reg.mac_address(31 downto 0); -- [31:0] = this node MAC address
+ -- rsvd
+ v_reg := (others => '0');
+ -- [15:0] = control UDP port number
+ v_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w) := mm_reg.udp_port;
+ -- [31:0] = this node IP address
+ v_reg( 3 * c_word_w - 1 downto 2 * c_word_w) := mm_reg.ip_address;
+ -- [47:32] = this node MAC address
+ v_reg( c_halfword_w + c_word_w - 1 downto c_word_w) := mm_reg.mac_address(47 downto 32);
+ -- [31:0] = this node MAC address
+ v_reg( c_word_w - 1 downto 0) := mm_reg.mac_address(31 downto 0);
return v_reg;
end func_eth_mm_reg_config;
@@ -267,23 +332,34 @@ package body eth_pkg is
function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control is
variable v_reg : t_eth_mm_reg_control;
begin
- v_reg.tx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
- v_reg.tx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16); -- [17:16]
- v_reg.tx_request := mm_reg( 2); -- [2]
- v_reg.tx_en := mm_reg( 1); -- [1]
- v_reg.rx_en := mm_reg( 0); -- [0]
+ -- [29:18]
+ v_reg.tx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16);
+ -- [17:16]
+ v_reg.tx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16);
+ -- [2]
+ v_reg.tx_request := mm_reg( 2);
+ -- [1]
+ v_reg.tx_en := mm_reg( 1);
+ -- [0]
+ v_reg.rx_en := mm_reg( 0);
return v_reg;
end func_eth_mm_reg_control;
function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_control_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.tx_nof_words; -- [29:18]
- v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.tx_empty; -- [17:16]
- v_reg( 2) := mm_reg.tx_request; -- [2]
- v_reg( 1) := mm_reg.tx_en; -- [1]
- v_reg( 0) := mm_reg.rx_en; -- [0]
+ -- rsvd
+ v_reg := (others => '0');
+ -- [29:18]
+ v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.tx_nof_words;
+ -- [17:16]
+ v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.tx_empty;
+ -- [2]
+ v_reg( 2) := mm_reg.tx_request;
+ -- [1]
+ v_reg( 1) := mm_reg.tx_en;
+ -- [0]
+ v_reg( 0) := mm_reg.rx_en;
return v_reg;
end func_eth_mm_reg_control;
@@ -291,33 +367,54 @@ package body eth_pkg is
function func_eth_mm_reg_frame(mm_reg : std_logic_vector) return t_eth_mm_reg_frame is
variable v_reg : t_eth_mm_reg_frame;
begin
- v_reg.is_dhcp := mm_reg( c_byte_w + 7); -- [15]
- v_reg.is_udp_ctrl_port := mm_reg( c_byte_w + 6); -- [14]
- v_reg.is_udp := mm_reg( c_byte_w + 5); -- [13]
- v_reg.is_icmp := mm_reg( c_byte_w + 4); -- [12]
- v_reg.ip_address_match := mm_reg( c_byte_w + 3); -- [11]
- v_reg.ip_checksum_is_ok := mm_reg( c_byte_w + 2); -- [10]
- v_reg.is_ip := mm_reg( c_byte_w + 1); -- [9]
- v_reg.is_arp := mm_reg( c_byte_w + 0); -- [8]
- v_reg.mac_address_match := mm_reg( c_byte_w - 1); -- [7]
- v_reg.eth_mac_error := mm_reg(c_eth_error_w - 1 downto 0); -- [7] not used, [5:0] = TSE MAC error
+ -- [15]
+ v_reg.is_dhcp := mm_reg( c_byte_w + 7);
+ -- [14]
+ v_reg.is_udp_ctrl_port := mm_reg( c_byte_w + 6);
+ -- [13]
+ v_reg.is_udp := mm_reg( c_byte_w + 5);
+ -- [12]
+ v_reg.is_icmp := mm_reg( c_byte_w + 4);
+ -- [11]
+ v_reg.ip_address_match := mm_reg( c_byte_w + 3);
+ -- [10]
+ v_reg.ip_checksum_is_ok := mm_reg( c_byte_w + 2);
+ -- [9]
+ v_reg.is_ip := mm_reg( c_byte_w + 1);
+ -- [8]
+ v_reg.is_arp := mm_reg( c_byte_w + 0);
+ -- [7]
+ v_reg.mac_address_match := mm_reg( c_byte_w - 1);
+ -- [7] not used, [5:0] = TSE MAC error
+ v_reg.eth_mac_error := mm_reg(c_eth_error_w - 1 downto 0);
return v_reg;
end func_eth_mm_reg_frame;
function func_eth_mm_reg_frame(mm_reg : t_eth_mm_reg_frame) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_frame_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg( c_byte_w + 7) := mm_reg.is_dhcp; -- [15]
- v_reg( c_byte_w + 6) := mm_reg.is_udp_ctrl_port; -- [14]
- v_reg( c_byte_w + 5) := mm_reg.is_udp; -- [13]
- v_reg( c_byte_w + 4) := mm_reg.is_icmp; -- [12]
- v_reg( c_byte_w + 3) := mm_reg.ip_address_match; -- [11]
- v_reg( c_byte_w + 2) := mm_reg.ip_checksum_is_ok; -- [10]
- v_reg( c_byte_w + 1) := mm_reg.is_ip; -- [9]
- v_reg( c_byte_w + 0) := mm_reg.is_arp; -- [8]
- v_reg( c_byte_w - 1) := mm_reg.mac_address_match; -- [7]
- v_reg(c_eth_error_w - 1 downto 0) := mm_reg.eth_mac_error; -- [6] not used, [5:0] = TSE MAC error
+ -- rsvd
+ v_reg := (others => '0');
+ -- [15]
+ v_reg( c_byte_w + 7) := mm_reg.is_dhcp;
+ -- [14]
+ v_reg( c_byte_w + 6) := mm_reg.is_udp_ctrl_port;
+ -- [13]
+ v_reg( c_byte_w + 5) := mm_reg.is_udp;
+ -- [12]
+ v_reg( c_byte_w + 4) := mm_reg.is_icmp;
+ -- [11]
+ v_reg( c_byte_w + 3) := mm_reg.ip_address_match;
+ -- [10]
+ v_reg( c_byte_w + 2) := mm_reg.ip_checksum_is_ok;
+ -- [9]
+ v_reg( c_byte_w + 1) := mm_reg.is_ip;
+ -- [8]
+ v_reg( c_byte_w + 0) := mm_reg.is_arp;
+ -- [7]
+ v_reg( c_byte_w - 1) := mm_reg.mac_address_match;
+ -- [6] not used, [5:0] = TSE MAC error
+ v_reg(c_eth_error_w - 1 downto 0) := mm_reg.eth_mac_error;
return v_reg;
end func_eth_mm_reg_frame;
@@ -325,23 +422,34 @@ package body eth_pkg is
function func_eth_mm_reg_status(mm_reg : std_logic_vector) return t_eth_mm_reg_status is
variable v_reg : t_eth_mm_reg_status;
begin
- v_reg.rx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
- v_reg.rx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16); -- [17:16]
- v_reg.tx_avail := mm_reg( 2); -- [2]
- v_reg.tx_done := mm_reg( 1); -- [1]
- v_reg.rx_avail := mm_reg( 0); -- [0]
+ -- [29:18]
+ v_reg.rx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16);
+ -- [17:16]
+ v_reg.rx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16);
+ -- [2]
+ v_reg.tx_avail := mm_reg( 2);
+ -- [1]
+ v_reg.tx_done := mm_reg( 1);
+ -- [0]
+ v_reg.rx_avail := mm_reg( 0);
return v_reg;
end func_eth_mm_reg_status;
function func_eth_mm_reg_status(mm_reg : t_eth_mm_reg_status) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_status_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.rx_nof_words; -- [29:18]
- v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.rx_empty; -- [17:16]
- v_reg( 2) := mm_reg.tx_avail; -- [2]
- v_reg( 1) := mm_reg.tx_done; -- [1]
- v_reg( 0) := mm_reg.rx_avail; -- [0]
+ -- rsvd
+ v_reg := (others => '0');
+ -- [29:18]
+ v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.rx_nof_words;
+ -- [17:16]
+ v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.rx_empty;
+ -- [2]
+ v_reg( 2) := mm_reg.tx_avail;
+ -- [1]
+ v_reg( 1) := mm_reg.tx_done;
+ -- [0]
+ v_reg( 0) := mm_reg.rx_avail;
return v_reg;
end func_eth_mm_reg_status;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
index 177eb750c7386763043b7282d1bfb4b3a3fc6636..ada21504435ae1849069b8859e9aad66318061d1 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
@@ -25,19 +25,28 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
package tech_tse_pkg is
- constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
+ -- = max 256 MAC registers
+ constant c_tech_tse_reg_addr_w : natural := 8;
constant c_tech_tse_byte_addr_w : natural := c_tech_tse_reg_addr_w + 2;
- constant c_tech_tse_byte_addr_pcs_offset : natural := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
- constant c_tech_tse_data_w : natural := c_word_w; -- = 32
+ -- table 4.8, 4.9 in ug_ethernet.pdf
+ constant c_tech_tse_byte_addr_pcs_offset : natural := 16#200#;
+ -- = 32
+ constant c_tech_tse_data_w : natural := c_word_w;
- constant c_tech_tse_symbol_w : natural := c_byte_w; -- = 8
- constant c_tech_tse_symbol_max : natural := 2**c_tech_tse_symbol_w - 1; -- = 255
- constant c_tech_tse_symbols_per_beat : natural := c_tech_tse_data_w / c_tech_tse_symbol_w; -- = 4
+ -- = 8
+ constant c_tech_tse_symbol_w : natural := c_byte_w;
+ -- = 255
+ constant c_tech_tse_symbol_max : natural := 2**c_tech_tse_symbol_w - 1;
+ -- = 4
+ constant c_tech_tse_symbols_per_beat : natural := c_tech_tse_data_w / c_tech_tse_symbol_w;
- constant c_tech_tse_pcs_reg_addr_w : natural := 5; -- = max 32 PCS registers
- constant c_tech_tse_pcs_halfword_addr_w : natural := c_tech_tse_pcs_reg_addr_w + 1; -- table 4.17 in ug_ethernet.pdf
+ -- = max 32 PCS registers
+ constant c_tech_tse_pcs_reg_addr_w : natural := 5;
+ -- table 4.17 in ug_ethernet.pdf
+ constant c_tech_tse_pcs_halfword_addr_w : natural := c_tech_tse_pcs_reg_addr_w + 1;
constant c_tech_tse_pcs_byte_addr_w : natural := c_tech_tse_pcs_reg_addr_w + 2;
- constant c_tech_tse_pcs_data_w : natural := c_halfword_w; -- = 16;
+ -- = 16;
+ constant c_tech_tse_pcs_data_w : natural := c_halfword_w;
constant c_tech_tse_empty_w : natural := 2;
constant c_tech_tse_tx_error_w : natural := 1;
@@ -46,11 +55,15 @@ package tech_tse_pkg is
constant c_tech_tse_err_stat_w : natural := 18;
constant c_tech_tse_frm_type_w : natural := 4;
- constant c_tech_tse_rx_ready_latency : natural := 2; -- 2 = default when FIFO is used
- constant c_tech_tse_tx_ready_latency : natural := 1; -- c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
+ -- 2 = default when FIFO is used
+ constant c_tech_tse_rx_ready_latency : natural := 2;
+ -- c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
+ constant c_tech_tse_tx_ready_latency : natural := 1;
- constant c_tech_tse_tx_fifo_depth : natural := 256; -- nof words for Tx FIFO
- constant c_tech_tse_rx_fifo_depth : natural := 256; -- nof words for Rx FIFO
+ -- nof words for Tx FIFO
+ constant c_tech_tse_tx_fifo_depth : natural := 256;
+ -- nof words for Rx FIFO
+ constant c_tech_tse_rx_fifo_depth : natural := 256;
type t_tech_tse_tx_mac is record
-- Tx MAC inputs
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
index d648f26fb1cb1a3e9c804714afad5c500ffa4798..048d776d65de66af1f7b85555885b9324efb707b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
@@ -45,25 +45,30 @@ entity avs2_eth_coe is
mms_tse_write : in std_logic;
mms_tse_read : in std_logic;
mms_tse_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_tse_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 0
- mms_tse_waitrequest : out std_logic; -- necessary because read latency is 0
+ -- read latency is 0
+ mms_tse_readdata : out std_logic_vector(c_word_w - 1 downto 0);
+ -- necessary because read latency is 0
+ mms_tse_waitrequest : out std_logic;
-- ETH registers
mms_reg_address : in std_logic_vector(c_eth_reg_addr_w - 1 downto 0);
mms_reg_write : in std_logic;
mms_reg_read : in std_logic;
mms_reg_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_reg_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 1
+ -- read latency is 1
+ mms_reg_readdata : out std_logic_vector(c_word_w - 1 downto 0);
-- ETH packet RAM
mms_ram_address : in std_logic_vector(c_eth_ram_addr_w - 1 downto 0);
mms_ram_write : in std_logic;
mms_ram_read : in std_logic;
mms_ram_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_ram_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 2
+ -- read latency is 2
+ mms_ram_readdata : out std_logic_vector(c_word_w - 1 downto 0);
-- Interrupt Sender interface
- ins_interrupt_irq : out std_logic; -- relates to the ETH registers port
+ -- relates to the ETH registers port
+ ins_interrupt_irq : out std_logic;
----------------------------------------------------------------------------
-- User side
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
index e879f1b9edecdcf0c9866d6359c01c0b6a645338..11d1cb80798696dd2c17cc8cf7ab10c9285e3daf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
@@ -57,27 +57,38 @@ package common_network_layers_pkg is
constant c_network_eth_mac_addr_w : natural := c_network_eth_mac_addr_len * c_8;
constant c_network_eth_type_len : natural := 2;
constant c_network_eth_type_w : natural := c_network_eth_type_len * c_8;
- constant c_network_eth_header_len : natural := 2 * c_network_eth_mac_addr_len + c_network_eth_type_len; -- = 14
+ -- = 14
+ constant c_network_eth_header_len : natural := 2 * c_network_eth_mac_addr_len + c_network_eth_type_len;
constant c_network_eth_payload_min : natural := 46;
constant c_network_eth_payload_max : natural := 1500;
constant c_network_eth_payload_jumbo_max : natural := 9000;
constant c_network_eth_crc_len : natural := 4;
constant c_network_eth_crc_w : natural := c_network_eth_crc_len * c_8;
- constant c_network_eth_gap_len : natural := 12; -- IPG = interpacket gap, minimum idle period between transmission of Ethernet packets
- constant c_network_eth_frame_max : natural := c_network_eth_header_len + c_network_eth_payload_max + c_network_eth_crc_len; -- = 1518
- constant c_network_eth_frame_jumbo_max : natural := c_network_eth_header_len + c_network_eth_payload_jumbo_max + c_network_eth_crc_len; -- = 9018
+ -- IPG = interpacket gap, minimum idle period between transmission of Ethernet packets
+ constant c_network_eth_gap_len : natural := 12;
+ -- = 1518
+ constant c_network_eth_frame_max : natural := c_network_eth_header_len + c_network_eth_payload_max + c_network_eth_crc_len;
+ -- = 9018
+ constant c_network_eth_frame_jumbo_max : natural := c_network_eth_header_len + c_network_eth_payload_jumbo_max + c_network_eth_crc_len;
-- default field values
- constant c_network_eth_preamble : natural := 5; -- nibble "0101"
- constant c_network_eth_frame_delimiter : natural := 13; -- nibble "1101"
+ -- nibble "0101"
+ constant c_network_eth_preamble : natural := 5;
+ -- nibble "1101"
+ constant c_network_eth_frame_delimiter : natural := 13;
-- useful field values
- constant c_network_eth_mac_slv : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := (others => 'X'); -- Ethernet MAC slv RANGE
- constant c_network_eth_bc_mac : std_logic_vector(c_network_eth_mac_slv'range) := (others => '1'); -- Broadcast destination MAC
-
- constant c_network_eth_type_slv : std_logic_vector(c_network_eth_type_w - 1 downto 0) := (others => 'X'); -- Ethernet TYPE slv RANGE
- constant c_network_eth_type_arp : natural := 16#0806#; -- ARP = Address Resolution Prorotol
- constant c_network_eth_type_ip : natural := 16#0800#; -- IPv4 = Internet Protocol, Version 4
+ -- Ethernet MAC slv RANGE
+ constant c_network_eth_mac_slv : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := (others => 'X');
+ -- Broadcast destination MAC
+ constant c_network_eth_bc_mac : std_logic_vector(c_network_eth_mac_slv'range) := (others => '1');
+
+ -- Ethernet TYPE slv RANGE
+ constant c_network_eth_type_slv : std_logic_vector(c_network_eth_type_w - 1 downto 0) := (others => 'X');
+ -- ARP = Address Resolution Prorotol
+ constant c_network_eth_type_arp : natural := 16#0806#;
+ -- IPv4 = Internet Protocol, Version 4
+ constant c_network_eth_type_ip : natural := 16#0800#;
type t_network_eth_header is record
dst_mac : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
@@ -111,8 +122,10 @@ package common_network_layers_pkg is
--
-- field widths in bits '_w' or in bytes '_len'
- constant c_network_ip_version_w : natural := 4; -- 4-bit field
- constant c_network_ip_header_length_w : natural := 4; -- 4-bit field
+ -- 4-bit field
+ constant c_network_ip_version_w : natural := 4;
+ -- 4-bit field
+ constant c_network_ip_header_length_w : natural := 4;
constant c_network_ip_version_header_len : natural := 1;
constant c_network_ip_version_header_w : natural := c_network_ip_version_header_len * c_8;
constant c_network_ip_services_len : natural := 1;
@@ -121,8 +134,10 @@ package common_network_layers_pkg is
constant c_network_ip_total_length_w : natural := c_network_ip_total_length_len * c_8;
constant c_network_ip_identification_len : natural := 2;
constant c_network_ip_identification_w : natural := c_network_ip_identification_len * c_8;
- constant c_network_ip_flags_w : natural := 3; -- 3-bit field
- constant c_network_ip_fragment_offset_w : natural := 13; -- 13-bit field
+ -- 3-bit field
+ constant c_network_ip_flags_w : natural := 3;
+ -- 13-bit field
+ constant c_network_ip_fragment_offset_w : natural := 13;
constant c_network_ip_flags_fragment_len : natural := 2;
constant c_network_ip_flags_fragment_w : natural := c_network_ip_flags_fragment_len * c_8;
constant c_network_ip_time_to_live_len : natural := 1;
@@ -142,36 +157,61 @@ package common_network_layers_pkg is
c_network_ip_addr_len;
-- = c_network_ip_header_length * c_word_sz = 20
-- default field values
- constant c_network_ip_version : natural := 4; -- 4 = IPv4,
- constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
- constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
- constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
- constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
- constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
- constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
- constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
- constant c_network_ip_header_checksum : natural := 0; -- init value
+ -- 4 = IPv4,
+ constant c_network_ip_version : natural := 4;
+ -- 5 = nof words in the header, no options field support
+ constant c_network_ip_header_length : natural := 5;
+ -- 0 = default, use default on transmit, ignore on receive, copy on reply
+ constant c_network_ip_services : natural := 0;
+ -- >= 20, nof bytes in entire datagram including header and data
+ constant c_network_ip_total_length : natural := 20;
+ -- identification number, copy on reply
+ constant c_network_ip_identification : natural := 0;
+ -- 2 = don't fragment and this is the last fragment
+ constant c_network_ip_flags : natural := 2;
+ -- 0 = first fragment
+ constant c_network_ip_fragment_offset : natural := 0;
+ -- number of hops until the packet will be discarded
+ constant c_network_ip_time_to_live : natural := 127;
+ -- init value
+ constant c_network_ip_header_checksum : natural := 0;
-- useful field values
- constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
- constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
- constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
+ -- IP protocol slv RANGE
+ constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X');
+ -- UDP = User Datagram Protocol (for board control and streaming data)
+ constant c_network_ip_protocol_udp : natural := 17;
+ -- ICMP = Internet Control Message Protocol (for ping)
+ constant c_network_ip_protocol_icmp : natural := 1;
- constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
+ -- IP address slv RANGE
+ constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X');
type t_network_ip_header is record
- version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
- header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
- services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
- total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
- identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
- flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
- fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
- time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
- protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
- header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
- src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ -- 4 bit
+ version : std_logic_vector(c_network_ip_version_w - 1 downto 0);
+ -- 4 bit
+ header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0);
+ -- 1 octet
+ services : std_logic_vector(c_network_ip_services_w - 1 downto 0);
+ -- 2 octet
+ total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0);
+ -- 2 octet
+ identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0);
+ -- 3 bit
+ flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0);
+ -- 13 bit
+ fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0);
+ -- 1 octet
+ time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0);
+ -- 1 octet
+ protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0);
+ -- 2 octet
+ header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0);
+ -- 4 octet
+ src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- 4 octet
+ dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
end record;
constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
@@ -223,27 +263,44 @@ package common_network_layers_pkg is
-- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
- constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
- constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
- constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
- constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
- constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
- constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
+ -- Hardware type, 1=ethernet
+ constant c_network_arp_htype : natural := 1;
+ -- Protocol type, do ARP for IPv4
+ constant c_network_arp_ptype : natural := c_network_eth_type_ip;
+ -- Hardware length = 6
+ constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len;
+ -- Protocol length = 4
+ constant c_network_arp_plen : natural := c_network_ip_addr_len;
+ -- Operator, 1=request
+ constant c_network_arp_oper_request : natural := 1;
+ -- Operator, 2=reply
+ constant c_network_arp_oper_reply : natural := 2;
-- useful field values
- constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
- constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
+ -- Broadcast destination MAC
+ constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac;
+ -- Broadcast target hardware address
+ constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac;
type t_network_arp_packet is record
- htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
- ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
- hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
- plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
- oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
- sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
- spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
- tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
- tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
+ -- 2 octet
+ htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0);
+ -- 2 octet
+ ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0);
+ -- 1 octet
+ hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0);
+ -- 1 octet
+ plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0);
+ -- 2 octet
+ oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0);
+ -- 6 octet, Sender Hardware Address
+ sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ -- 4 octet, Sender Protocol Address
+ spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- 6 octet, Target Hardware Address
+ tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ -- 4 octet, Target Protocol Address
+ tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
end record;
constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
@@ -283,21 +340,32 @@ package common_network_layers_pkg is
c_network_icmp_id_len + c_network_icmp_sequence_len;
-- default field values
- constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
- constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
- constant c_network_icmp_checksum : natural := 0; -- init value
+ -- 8 = echo request
+ constant c_network_icmp_msg_type_request : natural := 8;
+ -- 8 = echo reply (ping)
+ constant c_network_icmp_msg_type_reply : natural := 0;
+ -- init value
+ constant c_network_icmp_checksum : natural := 0;
-- useful field values
- constant c_network_icmp_code : natural := 0; -- default
- constant c_network_icmp_id : natural := 3; -- arbitrary value
- constant c_network_icmp_sequence : natural := 4; -- arbitrary value
+ -- default
+ constant c_network_icmp_code : natural := 0;
+ -- arbitrary value
+ constant c_network_icmp_id : natural := 3;
+ -- arbitrary value
+ constant c_network_icmp_sequence : natural := 4;
type t_network_icmp_header is record
- msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
- code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
- checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
- id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
- sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
+ -- 1 octet
+ msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0);
+ -- 1 octet
+ code : std_logic_vector(c_network_icmp_code_w - 1 downto 0);
+ -- 2 octet
+ checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0);
+ -- 2 octet
+ id : std_logic_vector(c_network_icmp_id_w - 1 downto 0);
+ -- 2 octet
+ sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0);
end record;
constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
@@ -328,23 +396,33 @@ package common_network_layers_pkg is
-- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+ -- 8
+ c_network_udp_total_length_len + c_network_udp_checksum_len;
-- default field values
- constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
- constant c_network_udp_checksum : natural := 0; -- init value
+ -- >= 8, nof bytes in entire datagram including header and data
+ constant c_network_udp_total_length : natural := 8;
+ -- init value
+ constant c_network_udp_checksum : natural := 0;
-- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
- constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
- constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
- constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
+ -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
+ constant c_network_udp_port_dhcp_in : natural := 68;
+ -- DHCP to server
+ constant c_network_udp_port_dhcp_out : natural := 67;
+ -- UDP port slv RANGE
+ constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X');
type t_network_udp_header is record
- src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
- checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
+ -- 2 octet
+ src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- 2 octet
+ dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- 2 octet
+ total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0);
+ -- 2 octet
+ checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0);
end record;
constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index 4bd7e15cc8fdafe0a37772e3eaedca527d52c4bf..33e9a782ae790b7c4c71516d23a87c8acd5a53bf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -61,8 +61,10 @@ package common_pkg is
constant c_octet_w : natural := 8;
constant c_halfword_w : natural := c_byte_w * c_halfword_sz;
constant c_word_w : natural := c_byte_w * c_word_sz;
- constant c_integer_w : natural := 32; -- unfortunately VHDL integer type is limited to 32 bit values
- constant c_natural_w : natural := c_integer_w - 1; -- unfortunately VHDL natural type is limited to 31 bit values (0 and the positive subset of the VHDL integer type0
+ -- unfortunately VHDL integer type is limited to 32 bit values
+ constant c_integer_w : natural := 32;
+ -- unfortunately VHDL natural type is limited to 31 bit values (0 and the positive subset of the VHDL integer type0
+ constant c_natural_w : natural := c_integer_w - 1;
constant c_longword_w : natural := c_byte_w * c_longword_sz;
-- logic
@@ -80,30 +82,46 @@ package common_pkg is
constant c_slv10 : std_logic_vector(255 downto 0) := c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10;
-- math
- constant c_nof_complex : natural := 2; -- Real and imaginary part of complex number
- constant c_sign_w : natural := 1; -- Sign bit, can be used to skip one of the double sign bits of a product
- constant c_sum_of_prod_w : natural := 1; -- Bit growth for sum of 2 products, can be used in case complex multiply has normalized real and imag inputs instead of normalized amplitude inputs
+ -- Real and imaginary part of complex number
+ constant c_nof_complex : natural := 2;
+ -- Sign bit, can be used to skip one of the double sign bits of a product
+ constant c_sign_w : natural := 1;
+ -- Bit growth for sum of 2 products, can be used in case complex multiply has normalized real and imag inputs instead of normalized amplitude inputs
+ constant c_sum_of_prod_w : natural := 1;
-- FF, block RAM, FIFO
- constant c_meta_delay_len : natural := 3; -- default nof flipflops (FF) in meta stability recovery delay line (e.g. for clock domain crossing)
- constant c_meta_fifo_depth : natural := 16; -- default use 16 word deep FIFO to cross clock domain, typically > 2*c_meta_delay_len or >~ 8 is enough
+ -- default nof flipflops (FF) in meta stability recovery delay line (e.g. for clock domain crossing)
+ constant c_meta_delay_len : natural := 3;
+ -- default use 16 word deep FIFO to cross clock domain, typically > 2*c_meta_delay_len or >~ 8 is enough
+ constant c_meta_fifo_depth : natural := 16;
- constant c_bram_m9k_nof_bits : natural := 1024 * 9; -- size of 1 Altera M9K block RAM in bits
- constant c_bram_m9k_max_w : natural := 36; -- maximum width of 1 Altera M9K block RAM, so the size is then 256 words of 36 bits
- constant c_bram_m9k_fifo_depth : natural := c_bram_m9k_nof_bits / c_bram_m9k_max_w; -- using a smaller FIFO depth than this leaves part of the RAM unused
+ -- size of 1 Altera M9K block RAM in bits
+ constant c_bram_m9k_nof_bits : natural := 1024 * 9;
+ -- maximum width of 1 Altera M9K block RAM, so the size is then 256 words of 36 bits
+ constant c_bram_m9k_max_w : natural := 36;
+ -- using a smaller FIFO depth than this leaves part of the RAM unused
+ constant c_bram_m9k_fifo_depth : natural := c_bram_m9k_nof_bits / c_bram_m9k_max_w;
- constant c_fifo_afull_margin : natural := 4; -- default or minimal FIFO almost full margin
+ -- default or minimal FIFO almost full margin
+ constant c_fifo_afull_margin : natural := 4;
-- DSP
- constant c_dsp_mult_w : natural := 18; -- Width of the embedded multipliers in Stratix IV
+ -- Width of the embedded multipliers in Stratix IV
+ constant c_dsp_mult_w : natural := 18;
-- TYPE DECLARATIONS --------------------------------------------------------
- type t_boolean_arr is array (integer range <>) of boolean; -- INTEGER left index starts default at -2**31
- type t_integer_arr is array (integer range <>) of integer; -- INTEGER left index starts default at -2**31
- type t_natural_arr is array (integer range <>) of natural; -- INTEGER left index starts default at -2**31
- type t_nat_boolean_arr is array (natural range <>) of boolean; -- NATURAL left index starts default at 0
- type t_nat_integer_arr is array (natural range <>) of integer; -- NATURAL left index starts default at 0
- type t_nat_natural_arr is array (natural range <>) of natural; -- NATURAL left index starts default at 0
+ -- INTEGER left index starts default at -2**31
+ type t_boolean_arr is array (integer range <>) of boolean;
+ -- INTEGER left index starts default at -2**31
+ type t_integer_arr is array (integer range <>) of integer;
+ -- INTEGER left index starts default at -2**31
+ type t_natural_arr is array (integer range <>) of natural;
+ -- NATURAL left index starts default at 0
+ type t_nat_boolean_arr is array (natural range <>) of boolean;
+ -- NATURAL left index starts default at 0
+ type t_nat_integer_arr is array (natural range <>) of integer;
+ -- NATURAL left index starts default at 0
+ type t_nat_natural_arr is array (natural range <>) of natural;
type t_sl_arr is array (integer range <>) of std_logic;
type t_slv_1_arr is array (integer range <>) of std_logic_vector(0 downto 0);
type t_slv_2_arr is array (integer range <>) of std_logic_vector(1 downto 0);
@@ -122,8 +140,10 @@ package common_pkg is
type t_slv_512_arr is array (integer range <>) of std_logic_vector(511 downto 0);
type t_slv_1024_arr is array (integer range <>) of std_logic_vector(1023 downto 0);
- constant c_boolean_arr : t_boolean_arr := (true, false); -- array all possible values that can be iterated over
- constant c_nat_boolean_arr : t_nat_boolean_arr := (true, false); -- array all possible values that can be iterated over
+ -- array all possible values that can be iterated over
+ constant c_boolean_arr : t_boolean_arr := (true, false);
+ -- array all possible values that can be iterated over
+ constant c_nat_boolean_arr : t_nat_boolean_arr := (true, false);
type t_integer_matrix is array (integer range <>, integer range <>) of integer;
type t_boolean_matrix is array (integer range <>, integer range <>) of boolean;
@@ -151,61 +171,87 @@ package common_pkg is
type t_sys_rce is record
rst : std_logic;
clk : std_logic;
- clken : std_logic; -- := '1';
+ -- := '1';
+ clken : std_logic;
end record;
type t_sys_ce is record
clk : std_logic;
- clken : std_logic; -- := '1';
+ -- := '1';
+ clken : std_logic;
end record;
-- FUNCTION DECLARATIONS ----------------------------------------------------
-- All functions assume [high downto low] input ranges
- function pow2(n : natural) return natural; -- = 2**n
- function ceil_pow2(n : integer) return natural; -- = 2**n, returns 1 for n<0
+ -- = 2**n
+ function pow2(n : natural) return natural;
+ -- = 2**n, returns 1 for n<0
+ function ceil_pow2(n : integer) return natural;
- function true_log2(n : natural) return natural; -- true_log2(n) = log2(n)
- function ceil_log2(n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ -- true_log2(n) = log2(n)
+ function true_log2(n : natural) return natural;
+ -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ function ceil_log2(n : natural) return natural;
function floor_log10(n : natural) return natural;
- function is_pow2(n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
- function true_log_pow2(n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
-
- function ratio( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
- function ratio2(n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
-
- function ceil_div( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
- function ceil_value( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
- function floor_value(n, d : natural) return natural; -- floor_value = (n/d) * d
+ -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
+ function is_pow2(n : natural) return boolean;
+ -- 2**true_log2(n), return power of 2 that is >= n
+ function true_log_pow2(n : natural) return natural;
+
+ -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
+ function ratio( n, d : natural) return natural;
+ -- return integer ratio of n/m or m/n, whichever is the largest
+ function ratio2(n, m : natural) return natural;
+
+ -- ceil_div = n/d + (n MOD d)/=0
+ function ceil_div( n, d : natural) return natural;
+ -- ceil_value = ceil_div(n, d) * d
+ function ceil_value( n, d : natural) return natural;
+ -- floor_value = (n/d) * d
+ function floor_value(n, d : natural) return natural;
function ceil_div( n : unsigned; d: natural) return unsigned;
function ceil_value( n : unsigned; d: natural) return unsigned;
function floor_value(n : unsigned; d: natural) return unsigned;
- function slv(n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
- function sl( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
+ -- standard logic to 1 element standard logic vector
+ function slv(n: in std_logic) return std_logic_vector;
+ -- 1 element standard logic vector to standard logic
+ function sl( n: in std_logic_vector) return std_logic;
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr;
function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr;
function to_integer_arr(n : t_natural_arr) return t_integer_arr;
function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr;
function to_slv_32_arr( n : t_integer_arr) return t_slv_32_arr;
function to_slv_32_arr( n : t_natural_arr) return t_slv_32_arr;
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
- function vector_and(slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
- function vector_or( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
- function vector_xor(slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
-
- function andv(slv : std_logic_vector) return std_logic; -- alias of vector_and
- function orv( slv : std_logic_vector) return std_logic; -- alias of vector_or
- function xorv(slv : std_logic_vector) return std_logic; -- alias of vector_xor
-
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
- function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
+ -- Core operation tree function for vector "AND", "OR", "XOR"
+ function vector_tree(slv : std_logic_vector; operation : string) return std_logic;
+ -- '1' when all slv bits are '1' else '0'
+ function vector_and(slv : std_logic_vector) return std_logic;
+ -- '0' when all slv bits are '0' else '1'
+ function vector_or( slv : std_logic_vector) return std_logic;
+ -- '1' when the slv has an odd number of '1' bits else '0'
+ function vector_xor(slv : std_logic_vector) return std_logic;
+ -- Returns slv when it contains one hot bit, else returns 0.
+ function vector_one_hot(slv : std_logic_vector) return std_logic_vector;
+
+ -- alias of vector_and
+ function andv(slv : std_logic_vector) return std_logic;
+ -- alias of vector_or
+ function orv( slv : std_logic_vector) return std_logic;
+ -- alias of vector_xor
+ function xorv(slv : std_logic_vector) return std_logic;
+
+ -- '1' when all matrix bits are '1' else '0'
+ function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic;
+ -- '0' when all matrix bits are '0' else '1'
+ function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic;
function smallest(n, m : integer) return integer;
function smallest(n, m, l : integer) return integer;
@@ -214,34 +260,51 @@ package common_pkg is
function largest(n, m : integer) return integer;
function largest(n : t_natural_arr) return natural;
- function func_sum( n : t_natural_arr) return natural; -- sum of all elements in array
+ -- sum of all elements in array
+ function func_sum( n : t_natural_arr) return natural;
function func_sum( n : t_nat_natural_arr) return natural;
- function func_product(n : t_natural_arr) return natural; -- product of all elements in array
+ -- product of all elements in array
+ function func_product(n : t_natural_arr) return natural;
function func_product(n : t_nat_natural_arr) return natural;
- function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
- function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
- function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
-
- function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
- function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
- function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
- function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
-
- function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
- function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
- function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
-
- function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
- function "/" (L : t_natural_arr; R : positive) return t_natural_arr; -- element wise division
- function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
+ -- element wise sum
+ function "+" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise sum
+ function "+" (L : t_natural_arr; R : integer) return t_natural_arr;
+ -- element wise sum
+ function "+" (L : integer; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise subtract
+ function "-" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise subtract, support negative result
+ function "-" (L, R: t_natural_arr) return t_integer_arr;
+ -- element wise subtract
+ function "-" (L : t_natural_arr; R : integer) return t_natural_arr;
+ -- element wise subtract
+ function "-" (L : integer; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise product
+ function "*" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise product
+ function "*" (L : t_natural_arr; R : natural) return t_natural_arr;
+ -- element wise product
+ function "*" (L : natural; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise division
+ function "/" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise division
+ function "/" (L : t_natural_arr; R : positive) return t_natural_arr;
+ -- element wise division
+ function "/" (L : natural; R : t_natural_arr) return t_natural_arr;
function is_true(a : std_logic) return boolean;
function is_true(a : std_logic) return natural;
function is_true(a : boolean) return std_logic;
function is_true(a : boolean) return natural;
- function is_true(a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
- function is_true(a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
+ -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true(a : integer) return boolean;
+ -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true(a : integer) return std_logic;
function sel_a_b(sel, a, b : boolean) return boolean;
function sel_a_b(sel, a, b : integer) return integer;
@@ -263,46 +326,79 @@ package common_pkg is
function sel_a_b(sel : boolean; a, b : severity_level) return severity_level;
-- sel_n() index sel = 0, 1, 2, ... will return a, b, c, ...
- function sel_n(sel : natural; a, b, c : boolean) return boolean; -- 3
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean; -- 4
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
-
- function sel_n(sel : natural; a, b, c : integer) return integer; -- 3
- function sel_n(sel : natural; a, b, c, d : integer) return integer; -- 4
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
-
- function sel_n(sel : natural; a, b : string) return string; -- 2
- function sel_n(sel : natural; a, b, c : string) return string; -- 3
- function sel_n(sel : natural; a, b, c, d : string) return string; -- 4
- function sel_n(sel : natural; a, b, c, d, e : string) return string; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
+ -- 3
+ function sel_n(sel : natural; a, b, c : boolean) return boolean;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : boolean) return boolean;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean;
+
+ -- 3
+ function sel_n(sel : natural; a, b, c : integer) return integer;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : integer) return integer;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : integer) return integer;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer;
+
+ -- 2
+ function sel_n(sel : natural; a, b : string) return string;
+ -- 3
+ function sel_n(sel : natural; a, b, c : string) return string;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : string) return string;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : string) return string;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : string) return string;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string;
+
+ -- useful to init a unconstrained array of size 1
+ function array_init(init : std_logic; nof : natural) return std_logic_vector;
+ -- useful to init a unconstrained array of size 1
+ function array_init(init, nof : natural) return t_natural_arr;
+ -- useful to init a unconstrained array of size 1
+ function array_init(init, nof : natural) return t_nat_natural_arr;
+ -- useful to init an array with incrementing numbers
+ function array_init(init, nof, incr : natural) return t_natural_arr;
function array_init(init, nof, incr : natural) return t_nat_natural_arr;
function array_init(init, nof, incr : integer) return t_slv_16_arr;
function array_init(init, nof, incr : integer) return t_slv_32_arr;
- function array_init(init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
- function array_init(init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
- function array_sinit(init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+ -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_init(init, nof, width : natural) return std_logic_vector;
+ -- useful to init an unconstrained std_logic_vector with incrementing content
+ function array_init(init, nof, width, incr : natural) return std_logic_vector;
+ -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_sinit(init : integer; nof, width : natural) return std_logic_vector;
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
+ -- initialize all elements in t_slv_64_matrix to value k
+ function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix;
-- Concatenate two or more STD_LOGIC_VECTORs into a single STD_LOGIC_VECTOR or extract one of them from a concatenated STD_LOGIC_VECTOR
function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
@@ -324,13 +420,15 @@ package common_pkg is
function func_slv_extract( use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
function func_slv_extract( use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function TO_UINT(vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ function TO_UINT(vec : std_logic_vector) return natural;
function TO_SINT(vec : std_logic_vector) return integer;
function TO_UVEC(dec, w : natural) return std_logic_vector;
function TO_SVEC(dec, w : integer) return std_logic_vector;
- function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
+ -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
+ function TO_SVEC_32(dec : integer) return std_logic_vector;
-- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
@@ -338,81 +436,132 @@ package common_pkg is
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
-- happens for RESIZE of UNSIGNED. Therefor this is what the RESIZE_NUM for SIGNED and the RESIZE_SVEC do
-- and better not use RESIZE for SIGNED anymore.
- function RESIZE_NUM( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
- function RESIZE_NUM( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
- function RESIZE_UINT(u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
- function RESIZE_SINT(s : integer; w : natural) return integer; -- extend sign bit or keep LS part
-
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
+ -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
+ function RESIZE_NUM( u : unsigned; w : natural) return unsigned;
+ -- extend sign bit or keep LS part
+ function RESIZE_NUM( s : signed; w : natural) return signed;
+ -- left extend with '0' into slv
+ function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector;
+ -- left extend with '0' or keep LS part
+ function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector;
+ -- extend sign bit or keep LS part
+ function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector;
+ -- left extend with '0' or keep LS part
+ function RESIZE_UINT(u : integer; w : natural) return integer;
+ -- extend sign bit or keep LS part
+ function RESIZE_SINT(s : integer; w : natural) return integer;
+
+ -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector;
+ -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector;
function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
-- Used in common_add_sub.vhd
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
-
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
-
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
-
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
+ -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
+ function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
+ function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
+ function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
+ function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+
+ -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+
+ -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
+ function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer;
+ -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
+ function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer;
+
+ -- < 0 shift left, > 0 shift right
+ function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector;
+ -- < 0 shift left, > 0 shift right
+ function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector;
function offset_binary(a : std_logic_vector) return std_logic_vector;
- function truncate( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function scale( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
- function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
- function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
- function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
-
- function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
- function s_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
- function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
- function u_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
-
- function u_to_s(u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
- function s_to_u(s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
-
- function u_wrap(u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
- function s_wrap(s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
-
- function u_clip(u : natural; max : natural) return natural; -- if s < max return s, else return n
- function s_clip(s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
- function s_clip(s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
-
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
- function hton(a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
- function ntoh(a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
-
- function flip(a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
- function flip(a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ -- remove n LSBits from vec, so result has width vec'LENGTH-n
+ function truncate( vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- remove n LSBits from vec and then resize to width w
+ function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- idem for signed values
+ function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- add n '0' LSBits to vec
+ function scale( vec : std_logic_vector; n: natural) return std_logic_vector;
+ -- add n '0' LSBits to vec and then resize to width w
+ function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- idem for signed values
+ function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- when b=TRUE then truncate to width w, else resize to width w
+ function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector;
+ -- idem for signed values
+ function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector;
+
+ -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
+ function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector;
+ -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
+ function s_round( vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- idem but round up to +infinity (s_round_up = u_round)
+ function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector;
+ -- idem but round up to +infinity (s_round_up = u_round)
+ function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- idem round up for unsigned values
+ function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector;
+ -- idem round up for unsigned values
+ function u_round( vec : std_logic_vector; n : natural) return std_logic_vector;
+
+ -- interpret w bit unsigned u as w bit signed, and remove any MSbits
+ function u_to_s(u : natural; w : natural) return integer;
+ -- interpret w bit signed s as w bit unsigned, and remove any MSbits
+ function s_to_u(s : integer; w : natural) return natural;
+
+ -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
+ function u_wrap(u : natural; w : natural) return natural;
+ -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
+ function s_wrap(s : integer; w : natural) return integer;
+
+ -- if s < max return s, else return n
+ function u_clip(u : natural; max : natural) return natural;
+ -- if s <= min return min, else if s >= max return max, else return s
+ function s_clip(s : integer; max : natural; min : integer) return integer;
+ -- if s <= -max return -max, else if s >= max return max, else return s
+ function s_clip(s : integer; max : natural ) return integer;
+
+ -- convert endianity from host to network, sz in symbols of width w
+ function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector;
+ -- convert endianity from host to network, sz in bytes
+ function hton(a : std_logic_vector; sz : natural) return std_logic_vector;
+ -- convert endianity from host to network, for all bytes in a
+ function hton(a : std_logic_vector ) return std_logic_vector;
+ -- convert endianity from network to host, sz in bytes, ntoh() = hton()
+ function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector;
+ -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
+ function ntoh(a : std_logic_vector ) return std_logic_vector;
+
+ -- bit flip a vector, map a[h:0] to [0:h]
+ function flip(a : std_logic_vector) return std_logic_vector;
+ -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ function flip(a, w : natural) return natural;
function flip(a : t_slv_32_arr) return t_slv_32_arr;
function flip(a : t_integer_arr) return t_integer_arr;
function flip(a : t_natural_arr) return t_natural_arr;
function flip(a : t_nat_natural_arr) return t_nat_natural_arr;
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
- function transpose(a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
+ -- transpose a vector, map a[i*row+j] to output index [j*col+i]
+ function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector;
+ -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose(a, row, col : natural) return natural;
function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
@@ -499,9 +648,11 @@ package body common_pkg is
-- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
- return 0; -- Get NULL array
+ -- Get NULL array
+ return 0;
elsif n = 1 then
- return 1; -- avoid NULL array
+ -- avoid NULL array
+ return 1;
else
return true_log2(n);
end if;
@@ -553,7 +704,8 @@ package body common_pkg is
function ceil_div(n : unsigned; d: natural) return unsigned is
begin
- return n / d + sel_a_b(n mod d = 0, 0, 1); -- "/" returns same width as n
+ -- "/" returns same width as n
+ return n / d + sel_a_b(n mod d = 0, 0, 1);
end;
function ceil_value(n : unsigned; d: natural) return unsigned is
@@ -561,7 +713,8 @@ package body common_pkg is
variable p : unsigned(2 * w - 1 downto 0);
begin
p := ceil_div(n, d) * d;
- return p(w - 1 downto 0); -- return same width as n
+ -- return same width as n
+ return p(w - 1 downto 0);
end;
function floor_value(n : unsigned; d: natural) return unsigned is
@@ -569,7 +722,8 @@ package body common_pkg is
variable p : unsigned(2 * w - 1 downto 0);
begin
p := (n / d) * d;
- return p(w - 1 downto 0); -- return same width as n
+ -- return same width as n
+ return p(w - 1 downto 0);
end;
function slv(n: in std_logic) return std_logic_vector is
@@ -664,7 +818,8 @@ package body common_pkg is
-- Instead use binary tree to determine result with smallest combinatorial delay that depends on log2(slv'LENGTH)
constant c_slv_w : natural := slv'length;
constant c_nof_stages : natural := ceil_log2(c_slv_w);
- constant c_w : natural := 2**c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ constant c_w : natural := 2**c_nof_stages;
type t_stage_arr is array (-1 to c_nof_stages - 1) of std_logic_vector(c_w - 1 downto 0);
variable v_stage_arr : t_stage_arr;
variable v_result : std_logic := '0';
@@ -676,7 +831,8 @@ package body common_pkg is
else
assert true report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
end if;
- v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
+ -- any unused input c_w : c_slv_w bits have void default value
+ v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv;
for J in 0 to c_nof_stages - 1 loop
for I in 0 to c_w / (2**(J + 1)) - 1 loop
if operation = "AND" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
@@ -738,7 +894,8 @@ package body common_pkg is
end;
function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic is
- variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
+ -- map to fixed range
+ variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat;
variable v_result : std_logic := '1';
begin
for I in 0 to wi - 1 loop
@@ -750,7 +907,8 @@ package body common_pkg is
end;
function matrix_or(mat : t_sl_matrix; wi, wj : natural) return std_logic is
- variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
+ -- map to fixed range
+ variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat;
variable v_result : std_logic := '0';
begin
for I in 0 to wi - 1 loop
@@ -1513,7 +1671,8 @@ package body common_pkg is
if use_f = true then v_lo := v_lo + f_w; end if;
when others => report "Unknown common_pkg func_slv_extract argument" severity FAILURE;
end case;
- return vec(v_w - 1 + v_lo downto v_lo); -- extracted slv
+ -- extracted slv
+ return vec(v_w - 1 + v_lo downto v_lo);
end func_slv_extract;
function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
@@ -1576,9 +1735,11 @@ package body common_pkg is
begin
-- extend sign bit or keep LS part
if w > s'length then
- return resize(s, w); -- extend sign bit
+ -- extend sign bit
+ return resize(s, w);
else
- return signed(resize(unsigned(s), w)); -- keep LSbits (= vec[w-1:0])
+ -- keep LSbits (= vec[w-1:0])
+ return signed(resize(unsigned(s), w));
end if;
end;
@@ -1627,10 +1788,12 @@ package body common_pkg is
begin
if dec < 0 then
v_dec := -dec;
- return std_logic_vector(unsigned(vec) - v_dec); -- uses function "-" (L : UNSIGNED, R : NATURAL), there is no function + with R : INTEGER argument
+ -- uses function "-" (L : UNSIGNED, R : NATURAL), there is no function + with R : INTEGER argument
+ return std_logic_vector(unsigned(vec) - v_dec);
else
v_dec := dec;
- return std_logic_vector(unsigned(vec) + v_dec); -- uses function "+" (L : UNSIGNED, R : NATURAL)
+ -- uses function "+" (L : UNSIGNED, R : NATURAL)
+ return std_logic_vector(unsigned(vec) + v_dec);
end if;
end;
@@ -1642,7 +1805,8 @@ package body common_pkg is
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
variable v_dec : integer;
begin
- return std_logic_vector(signed(vec) + v_dec); -- uses function "+" (L : SIGNED, R : INTEGER)
+ -- uses function "+" (L : SIGNED, R : INTEGER)
+ return std_logic_vector(signed(vec) + v_dec);
end;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector is
@@ -1703,18 +1867,22 @@ package body common_pkg is
function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
- return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift)); -- fill zeros from right
+ -- fill zeros from right
+ return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift));
else
- return std_logic_vector(SHIFT_RIGHT(unsigned(vec), shift)); -- fill zeros from left
+ -- fill zeros from left
+ return std_logic_vector(SHIFT_RIGHT(unsigned(vec), shift));
end if;
end;
function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
- return std_logic_vector(SHIFT_LEFT(signed(vec), -shift)); -- same as SHIFT_LEFT for UNSIGNED
+ -- same as SHIFT_LEFT for UNSIGNED
+ return std_logic_vector(SHIFT_LEFT(signed(vec), -shift));
else
- return std_logic_vector(SHIFT_RIGHT(signed(vec), shift)); -- extend sign
+ -- extend sign
+ return std_logic_vector(SHIFT_RIGHT(signed(vec), shift));
end if;
end;
@@ -1738,7 +1906,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ v_res(v_res'high) := not v_res(v_res'high);
return v_res;
end;
@@ -1748,7 +1917,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ -- keep MS part
+ v_res := v_vec(c_vec_w - 1 downto n);
return v_res;
end;
@@ -1758,8 +1928,10 @@ package body common_pkg is
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_trunc := truncate(vec, n); -- first keep MS part
- v_res := RESIZE_UVEC(v_trunc, w); -- then keep LS part or left extend with '0'
+ -- first keep MS part
+ v_trunc := truncate(vec, n);
+ -- then keep LS part or left extend with '0'
+ v_res := RESIZE_UVEC(v_trunc, w);
return v_res;
end;
@@ -1769,8 +1941,10 @@ package body common_pkg is
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_trunc := truncate(vec, n); -- first keep MS part
- v_res := RESIZE_SVEC(v_trunc, w); -- then keep sign bit and LS part or left extend sign bit
+ -- first keep MS part
+ v_trunc := truncate(vec, n);
+ -- then keep sign bit and LS part or left extend sign bit
+ v_res := RESIZE_SVEC(v_trunc, w);
return v_res;
end;
@@ -1779,7 +1953,8 @@ package body common_pkg is
constant c_scale_w : natural := c_vec_w + n;
variable v_res : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
begin
- v_res(c_scale_w - 1 downto n) := vec; -- scale by adding n zero bits at the right
+ -- scale by adding n zero bits at the right
+ v_res(c_scale_w - 1 downto n) := vec;
return v_res;
end;
@@ -1789,8 +1964,10 @@ package body common_pkg is
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_scale(c_scale_w - 1 downto n) := vec; -- first scale by adding n zero bits at the right
- v_res := RESIZE_UVEC(v_scale, w); -- then keep LS part or left extend with '0'
+ -- first scale by adding n zero bits at the right
+ v_scale(c_scale_w - 1 downto n) := vec;
+ -- then keep LS part or left extend with '0'
+ v_res := RESIZE_UVEC(v_scale, w);
return v_res;
end;
@@ -1800,8 +1977,10 @@ package body common_pkg is
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_scale(c_scale_w - 1 downto n) := vec; -- first scale by adding n zero bits at the right
- v_res := RESIZE_SVEC(v_scale, w); -- then keep LS part or left extend sign bit
+ -- first scale by adding n zero bits at the right
+ v_scale(c_scale_w - 1 downto n) := vec;
+ -- then keep LS part or left extend sign bit
+ v_res := RESIZE_SVEC(v_scale, w);
return v_res;
end;
@@ -1854,32 +2033,40 @@ package body common_pkg is
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
constant c_one : signed(c_in_w - 1 downto 0) := to_signed(1, c_in_w);
- constant c_half : signed(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1); -- = 2**(n-1)
- constant c_max : signed(c_in_w - 1 downto 0) := signed('0' & c_slv1(c_in_w - 2 downto 0)) - c_half; -- = 2**(c_in_w-1)-1 - c_half
- constant c_clip : signed(c_out_w - 1 downto 0) := signed('0' & c_slv1(c_out_w - 2 downto 0)); -- = 2**(c_out_w-1)-1
+ -- = 2**(n-1)
+ constant c_half : signed(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1);
+ -- = 2**(c_in_w-1)-1 - c_half
+ constant c_max : signed(c_in_w - 1 downto 0) := signed('0' & c_slv1(c_in_w - 2 downto 0)) - c_half;
+ -- = 2**(c_out_w-1)-1
+ constant c_clip : signed(c_out_w - 1 downto 0) := signed('0' & c_slv1(c_out_w - 2 downto 0));
variable v_in : signed(c_in_w - 1 downto 0);
variable v_out : signed(c_out_w - 1 downto 0);
begin
v_in := signed(vec);
if n > 0 then
if clip = true and v_in > c_max then
- v_out := c_clip; -- Round clip to maximum positive to avoid wrap to negative
+ -- Round clip to maximum positive to avoid wrap to negative
+ v_out := c_clip;
else
if vec(vec'high) = '0' then
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half + 0, n), c_out_w); -- Round up for positive
+ -- Round up for positive
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half + 0, n), c_out_w);
else
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half - 1, n), c_out_w); -- Round down for negative
+ -- Round down for negative
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half - 1, n), c_out_w);
end if;
end if;
else
- v_out := RESIZE_NUM(v_in, c_out_w); -- NOP
+ -- NOP
+ v_out := RESIZE_NUM(v_in, c_out_w);
end if;
return std_logic_vector(v_out);
end;
function s_round(vec : std_logic_vector; n : natural) return std_logic_vector is
begin
- return s_round(vec, n, false); -- no round clip
+ -- no round clip
+ return s_round(vec, n, false);
end;
-- An alternative is to always round up, also for negative numbers (i.e. s_round_up = u_round).
@@ -1890,7 +2077,8 @@ package body common_pkg is
function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector is
begin
- return u_round(vec, n, false); -- no round clip
+ -- no round clip
+ return u_round(vec, n, false);
end;
-- Unsigned numbers are round up (almost same as s_round, but without the else on negative vec)
@@ -1899,50 +2087,61 @@ package body common_pkg is
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
constant c_one : unsigned(c_in_w - 1 downto 0) := to_unsigned(1, c_in_w);
- constant c_half : unsigned(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1); -- = 2**(n-1)
- constant c_max : unsigned(c_in_w - 1 downto 0) := unsigned(c_slv1(c_in_w - 1 downto 0)) - c_half; -- = 2**c_in_w-1 - c_half
- constant c_clip : unsigned(c_out_w - 1 downto 0) := unsigned(c_slv1(c_out_w - 1 downto 0)); -- = 2**c_out_w-1
+ -- = 2**(n-1)
+ constant c_half : unsigned(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1);
+ -- = 2**c_in_w-1 - c_half
+ constant c_max : unsigned(c_in_w - 1 downto 0) := unsigned(c_slv1(c_in_w - 1 downto 0)) - c_half;
+ -- = 2**c_out_w-1
+ constant c_clip : unsigned(c_out_w - 1 downto 0) := unsigned(c_slv1(c_out_w - 1 downto 0));
variable v_in : unsigned(c_in_w - 1 downto 0);
variable v_out : unsigned(c_out_w - 1 downto 0);
begin
v_in := unsigned(vec);
if n > 0 then
if clip = true and v_in > c_max then
- v_out := c_clip; -- Round clip to +max to avoid wrap to 0
+ -- Round clip to +max to avoid wrap to 0
+ v_out := c_clip;
else
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half, n), c_out_w); -- Round up
+ -- Round up
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half, n), c_out_w);
end if;
else
- v_out := RESIZE_NUM(v_in, c_out_w); -- NOP
+ -- NOP
+ v_out := RESIZE_NUM(v_in, c_out_w);
end if;
return std_logic_vector(v_out);
end;
function u_round(vec : std_logic_vector; n : natural) return std_logic_vector is
begin
- return u_round(vec, n, false); -- no round clip
+ -- no round clip
+ return u_round(vec, n, false);
end;
function u_to_s(u : natural; w : natural) return integer is
- variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32);
begin
return TO_SINT(v_u(w - 1 downto 0));
end;
function s_to_u(s : integer; w : natural) return natural is
- variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32);
begin
return TO_UINT(v_s(w - 1 downto 0));
end;
function u_wrap(u : natural; w : natural) return natural is
- variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32);
begin
return TO_UINT(v_u(w - 1 downto 0));
end;
function s_wrap(s : integer; w : natural) return integer is
- variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32);
begin
return TO_SINT(v_s(w - 1 downto 0));
end;
@@ -1975,8 +2174,10 @@ package body common_pkg is
end;
function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector is
- variable v_a : std_logic_vector(a'length - 1 downto 0) := a; -- map a to range [h:0]
- variable v_b : std_logic_vector(a'length - 1 downto 0) := a; -- default b = a
+ -- map a to range [h:0]
+ variable v_a : std_logic_vector(a'length - 1 downto 0) := a;
+ -- default b = a
+ variable v_b : std_logic_vector(a'length - 1 downto 0) := a;
variable vL : natural;
variable vK : natural;
begin
@@ -1992,23 +2193,27 @@ package body common_pkg is
function hton(a : std_logic_vector; sz : natural) return std_logic_vector is
begin
- return hton(a, c_byte_w, sz); -- symbol width w = c_byte_w = 8
+ -- symbol width w = c_byte_w = 8
+ return hton(a, c_byte_w, sz);
end function;
function hton(a : std_logic_vector) return std_logic_vector is
constant c_sz : natural := a'length / c_byte_w;
begin
- return hton(a, c_byte_w, c_sz); -- symbol width w = c_byte_w = 8
+ -- symbol width w = c_byte_w = 8
+ return hton(a, c_byte_w, c_sz);
end function;
function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector is
begin
- return hton(a, sz); -- i.e. ntoh() = hton()
+ -- i.e. ntoh() = hton()
+ return hton(a, sz);
end function;
function ntoh(a : std_logic_vector) return std_logic_vector is
begin
- return hton(a); -- i.e. ntoh() = hton()
+ -- i.e. ntoh() = hton()
+ return hton(a);
end function;
function flip(a : std_logic_vector) return std_logic_vector is
@@ -2070,17 +2275,21 @@ package body common_pkg is
variable vIn : std_logic_vector(a'length - 1 downto 0);
variable vOut : std_logic_vector(a'length - 1 downto 0);
begin
- vIn := a; -- map input vector to h:0 range
- vOut := vIn; -- default leave any unused MSbits the same
+ -- map input vector to h:0 range
+ vIn := a;
+ -- default leave any unused MSbits the same
+ vOut := vIn;
for J in 0 to row - 1 loop
for I in 0 to col - 1 loop
- vOut(J * col + I) := vIn(I * row + J); -- transpose vector, map input index [i*row+j] to output index [j*col+i]
+ -- transpose vector, map input index [i*row+j] to output index [j*col+i]
+ vOut(J * col + I) := vIn(I * row + J);
end loop;
end loop;
return vOut;
end function;
- function transpose(a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
+ -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose(a, row, col : natural) return natural is
variable vI : natural;
variable vJ : natural;
begin
@@ -2089,16 +2298,20 @@ package body common_pkg is
return vJ * col + vI;
end;
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
+ -- Calculate input_w in multiples as close as possible to max_out_w
+ function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is
-- Examples: split_w(256, 8, 32) = 32; split_w(16, 8, 32) = 16; split_w(72, 8, 32) = 18; -- Input_w must be multiple of 2.
variable r: natural;
begin
r := input_w;
- for i in 1 to ceil_log2(input_w) loop -- Useless to divide the number beyond this
+ -- Useless to divide the number beyond this
+ for i in 1 to ceil_log2(input_w) loop
if r <= max_out_w and r >= min_out_w then
return r;
- elsif i = ceil_log2(input_w) then -- last iteration
- return 0; -- Indicates wrong values were used
+ -- last iteration
+ elsif i = ceil_log2(input_w) then
+ -- Indicates wrong values were used
+ return 0;
end if;
r := r / 2;
end loop;
@@ -2197,8 +2410,10 @@ package body common_pkg is
variable v_odd : boolean;
variable v_even : boolean;
begin
- v_odd := (I mod 2 = 1) and (J mod 2 = 1); -- for odd stage at each odd row
- v_even := (I mod 2 = 0) and (J mod 2 = 0); -- for even stage at each even row
+ -- for odd stage at each odd row
+ v_odd := (I mod 2 = 1) and (J mod 2 = 1);
+ -- for even stage at each even row
+ v_even := (I mod 2 = 0) and (J mod 2 = 0);
return v_odd or v_even;
end func_common_reorder2_is_there;
@@ -2228,7 +2443,8 @@ package body common_pkg is
-- for the active two port reorder cells use the setting at index v_K from the select setting array
v_nof_odd_stages := I / 2;
v_nof_even_stages := (I - 1) / 2;
- v_offset := (J - 1) / 2; -- suits both odd stage and even stage
+ -- suits both odd stage and even stage
+ v_offset := (J - 1) / 2;
v_K := v_nof_odd_stages * c_nof_reorder2_per_odd_stage + v_nof_even_stages * c_nof_reorder2_per_even_stage + v_offset;
end if;
return v_K;
@@ -2237,7 +2453,8 @@ package body common_pkg is
-- Get the select setting for the reorder2 cell on stage I and row J in a reorder network with N stages
function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural is
constant c_nof_select : natural := select_arr'length;
- constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
+ -- force range downto 0
+ constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr;
variable v_sel : natural;
variable v_K : integer;
begin
@@ -2252,11 +2469,13 @@ package body common_pkg is
-- Determine the inverse of a reorder network by using two reorder networks in series
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr is
constant c_nof_select : natural := select_arr'length;
- constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
+ -- force range downto 0
+ constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr;
variable v_sel : natural;
variable v_Ki : integer;
variable v_Ii : natural;
- variable v_inverse_arr : t_natural_arr(2 * c_nof_select - 1 downto 0) := (others => 0); -- default set identity for the reorder2 cells in both reorder instances
+ -- default set identity for the reorder2 cells in both reorder instances
+ variable v_inverse_arr : t_natural_arr(2 * c_nof_select - 1 downto 0) := (others => 0);
begin
-- the inverse select consists of inverse_in reorder and inverse_out reorder in series
if N mod 2 = 1 then
@@ -2276,7 +2495,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ -- stage 1 of the inverse_out reorder
+ v_Ki := c_nof_select + K;
v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index 7b6d1a2da0ec2558d87aa708358be0b79c70944d..dc48b2f8f8d20d5ee0c491104976d7126bb80f02 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -48,35 +48,59 @@ package dp_stream_pkg is
-- This grouping is useful for functions that operate on a t_dp_sosi signal.
-- * The info fields are valid at the sop or at the eop, but typically they hold their last active value to avoid unnessary
-- toggling and to ease viewing in the wave window.
- constant c_dp_stream_bsn_w : natural := 64; -- 64 is sufficient to count blocks of data for years
- constant c_dp_stream_data_w : natural := 768; -- 72 is sufficient for max word 8 * 9-bit. 576 supports half rate DDR4 bus data width. The current 768 is enough for wide single clock SLVs (e.g. headers)
- constant c_dp_stream_dsp_data_w : natural := 64; -- 64 is sufficient for DSP data, including complex power accumulates
- constant c_dp_stream_empty_w : natural := 16; -- 8 is sufficient for max 256 symbols per data word, still use 16 bit to be able to count c_dp_stream_data_w in bits
- constant c_dp_stream_channel_w : natural := 32; -- 32 is sufficient for several levels of hierarchy in mapping types of streams on to channels
- constant c_dp_stream_error_w : natural := 32; -- 32 is sufficient for several levels of hierarchy in mapping error numbers, e.g. 32 different one-hot encoded errors, bit [0] = 0 = OK
-
- constant c_dp_stream_ok : natural := 0; -- SOSI err field OK value
- constant c_dp_stream_err : natural := 1; -- SOSI err field error value /= OK
-
- constant c_dp_stream_rl : natural := 1; -- SISO default data path stream ready latency RL = 1
-
- type t_dp_siso is record -- Source In or Sink Out
- ready : std_logic; -- fine cycle based flow control using ready latency RL >= 0
- xon : std_logic; -- coarse typically block based flow control using xon/xoff
+ -- 64 is sufficient to count blocks of data for years
+ constant c_dp_stream_bsn_w : natural := 64;
+ -- 72 is sufficient for max word 8 * 9-bit. 576 supports half rate DDR4 bus data width. The current 768 is enough for wide single clock SLVs (e.g. headers)
+ constant c_dp_stream_data_w : natural := 768;
+ -- 64 is sufficient for DSP data, including complex power accumulates
+ constant c_dp_stream_dsp_data_w : natural := 64;
+ -- 8 is sufficient for max 256 symbols per data word, still use 16 bit to be able to count c_dp_stream_data_w in bits
+ constant c_dp_stream_empty_w : natural := 16;
+ -- 32 is sufficient for several levels of hierarchy in mapping types of streams on to channels
+ constant c_dp_stream_channel_w : natural := 32;
+ -- 32 is sufficient for several levels of hierarchy in mapping error numbers, e.g. 32 different one-hot encoded errors, bit [0] = 0 = OK
+ constant c_dp_stream_error_w : natural := 32;
+
+ -- SOSI err field OK value
+ constant c_dp_stream_ok : natural := 0;
+ -- SOSI err field error value /= OK
+ constant c_dp_stream_err : natural := 1;
+
+ -- SISO default data path stream ready latency RL = 1
+ constant c_dp_stream_rl : natural := 1;
+
+ -- Source In or Sink Out
+ type t_dp_siso is record
+ -- fine cycle based flow control using ready latency RL >= 0
+ ready : std_logic;
+ -- coarse typically block based flow control using xon/xoff
+ xon : std_logic;
end record;
- type t_dp_sosi is record -- Source Out or Sink In
- sync : std_logic; -- ctrl
- bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0); -- info at sop (block sequence number)
- data : std_logic_vector(c_dp_stream_data_w - 1 downto 0); -- data
- re : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0); -- data
- im : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0); -- data
- valid : std_logic; -- ctrl
- sop : std_logic; -- ctrl
- eop : std_logic; -- ctrl
- empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0); -- info at eop
- channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0); -- info at sop
- err : std_logic_vector(c_dp_stream_error_w - 1 downto 0); -- info at eop (name field 'err' to avoid the 'error' keyword)
+ -- Source Out or Sink In
+ type t_dp_sosi is record
+ -- ctrl
+ sync : std_logic;
+ -- info at sop (block sequence number)
+ bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ -- data
+ data : std_logic_vector(c_dp_stream_data_w - 1 downto 0);
+ -- data
+ re : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0);
+ -- data
+ im : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0);
+ -- ctrl
+ valid : std_logic;
+ -- ctrl
+ sop : std_logic;
+ -- ctrl
+ eop : std_logic;
+ -- info at eop
+ empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0);
+ -- info at sop
+ channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0);
+ -- info at eop (name field 'err' to avoid the 'error' keyword)
+ err : std_logic_vector(c_dp_stream_error_w - 1 downto 0);
end record;
-- Initialise signal declarations with c_dp_stream_rst/rdy to ease the interpretation of slv fields with unused bits
@@ -240,29 +264,43 @@ package dp_stream_pkg is
-- signed data in the simulation wave window it is easier to use sign extension in the record field. Therefore TO_DP_SDATA
-- and RESIZE_DP_SDATA are defined as well.
function TO_DP_BSN( n : natural) return std_logic_vector;
- function TO_DP_DATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
- function TO_DP_SDATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
- function TO_DP_UDATA( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector; -- for re and im fields, signed data
- function TO_DP_DSP_UDATA(n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
+ -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
+ function TO_DP_DATA( n : integer) return std_logic_vector;
+ -- use integer to support 32 bit range and signed
+ function TO_DP_SDATA( n : integer) return std_logic_vector;
+ -- alias of TO_DP_DATA()
+ function TO_DP_UDATA( n : integer) return std_logic_vector;
+ -- for re and im fields, signed data
+ function TO_DP_DSP_DATA(n : integer) return std_logic_vector;
+ -- for re and im fields, unsigned data (useful to carry indices)
+ function TO_DP_DSP_UDATA(n: integer) return std_logic_vector;
function TO_DP_EMPTY( n : natural) return std_logic_vector;
function TO_DP_CHANNEL( n : natural) return std_logic_vector;
function TO_DP_ERROR( n : natural) return std_logic_vector;
function RESIZE_DP_BSN( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
- function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
- function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
+ -- set unused MSBits to '0'
+ function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector;
+ -- sign extend unused MSBits
+ function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector;
+ -- set unused MSBits to 'X'
+ function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector;
+ -- sign extend unused MSBits of re and im fields
+ function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_EMPTY( vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_CHANNEL( vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_ERROR( vec : std_logic_vector) return std_logic_vector;
- function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
- function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
+ -- unsigned vec(w-1:0) + dec
+ function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
+ -- signed vec(w-1:0) + dec
+ function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
+ -- signed vec(w-1:0) + dec
+ function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
- function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+ -- replicate seq as often as fits in c_dp_stream_data_w
+ function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector;
+ -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+ function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector;
function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
@@ -332,12 +370,16 @@ package dp_stream_pkg is
-- Functions to combinatorially handle channels
-- Note that the *_select and *_remove function are equivalent to dp_demux with g_combined=TRUE
- function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
+ -- select channel nr, add the channel field
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
+ -- select channel nr, skip the channel field
+ function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
+ -- skip channel nr
+ function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
-- Functions to combinatorially handle the error field
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
+ -- force err = 0, is OK
+ function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi;
-- Functions to combinatorially handle the BSN field
function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
@@ -359,11 +401,15 @@ package dp_stream_pkg is
-- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
-- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ -- data_order_im_re = TRUE
+ function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi;
+ -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi;
function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ -- data_order_im_re = TRUE
+ function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi;
+ -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
@@ -373,8 +419,10 @@ package dp_stream_pkg is
function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
-- Concatenate the data and complex re,im fields from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
+ -- Concat SOSI_ARR data into single SOSI
+ function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi;
+ -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr;
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
-- . data_representation = "SIGNED" treat sosi.data field as signed
@@ -389,8 +437,10 @@ package dp_stream_pkg is
function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
-- Deconcatenate data and complex re,im fields from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
+ -- Deconcat SOSI data
+ function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr;
+ -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso;
end dp_stream_pkg;
@@ -431,7 +481,8 @@ package body dp_stream_pkg is
signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
- ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
+ -- SLV is used as an array: nof_streams*(0..c_ready_latency)
+ ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready;
end loop;
-- Register siso.ready in c_ready_latency registers
if rising_edge(clk) then
@@ -578,11 +629,14 @@ package body dp_stream_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0);
begin
v_data := RESIZE_UVEC(data, c_vec_w);
- v_seq := v_data(seq_w - 1 downto 0); -- low data part is the v_seq
- v_vec(seq_w - 1 downto 0) := v_seq; -- keep v_seq at low part of return value
+ -- low data part is the v_seq
+ v_seq := v_data(seq_w - 1 downto 0);
+ -- keep v_seq at low part of return value
+ v_vec(seq_w - 1 downto 0) := v_seq;
if c_nof_replications > 1 then
for I in 1 to c_nof_replications - 1 loop
- v_vec((I + 1) * seq_w - 1 downto I * seq_w) := v_data((I + 1) * seq_w - 1 downto I * seq_w) xor v_seq; -- set return bit to '1' for high part data bits that do not match low part v_seq
+ -- set return bit to '1' for high part data bits that do not match low part v_seq
+ v_vec((I + 1) * seq_w - 1 downto I * seq_w) := v_data((I + 1) * seq_w - 1 downto I * seq_w) xor v_seq;
end loop;
end if;
return v_vec(c_data_w - 1 downto 0);
@@ -612,8 +666,10 @@ package body dp_stream_pkg is
begin
assert nof_symbols_from_tail < vN report "func_dp_data_shift_first : no symbols from head" severity FAILURE;
-- use the other sosi from head_sosi
- v_sosi := head_sosi; -- I = nof_symbols_from_tail = 0
- for I in 1 to vN - 1 loop -- I > 0
+ -- I = nof_symbols_from_tail = 0
+ v_sosi := head_sosi;
+ -- I > 0
+ for I in 1 to vN - 1 loop
if nof_symbols_from_tail = I then
v_sosi.data(I * symbol_w - 1 downto 0) := tail_sosi.data(vN * symbol_w - 1 downto (vN - I) * symbol_w);
end if;
@@ -635,15 +691,18 @@ package body dp_stream_pkg is
end if;
-- use sosi data from both if 0 < nof_symbols_from_this < nof_symbols_per_data (i.e. 0 < I < vN)
- if vK < nof_symbols_per_data then -- I = vK = nof_symbols_from_this < vN
+ -- I = vK = nof_symbols_from_this < vN
+ if vK < nof_symbols_per_data then
-- Implementation using variable vK directly instead of via I in a LOOP
-- IF vK > 0 THEN
-- v_sosi.data(vN*symbol_w-1 DOWNTO vK*symbol_w) := prev_sosi.data((vN-vK)*symbol_w-1 DOWNTO 0);
-- v_sosi.data( vK*symbol_w-1 DOWNTO 0) := this_sosi.data( vN *symbol_w-1 DOWNTO (vN-vK)*symbol_w);
-- END IF;
-- Implementaion using LOOP vK rather than VARIABLE vK directly as index to help synthesis and avoid potential multiplier
- v_sosi.data := prev_sosi.data; -- I = vK = nof_symbols_from_this = 0
- for I in 1 to vN - 1 loop -- I = vK = nof_symbols_from_this > 0
+ -- I = vK = nof_symbols_from_this = 0
+ v_sosi.data := prev_sosi.data;
+ -- I = vK = nof_symbols_from_this > 0
+ for I in 1 to vN - 1 loop
if vK = I then
v_sosi.data(vN * symbol_w - 1 downto I * symbol_w) := prev_sosi.data((vN - I) * symbol_w - 1 downto 0);
v_sosi.data( I * symbol_w - 1 downto 0) := this_sosi.data( vN * symbol_w - 1 downto (vN - I) * symbol_w);
@@ -723,7 +782,8 @@ package body dp_stream_pkg is
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '1');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -738,14 +798,17 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_and(v_vec); -- return AND of the masked input fields
+ -- return AND of the masked input fields
+ return vector_and(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_and;
function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '1');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -762,9 +825,11 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_and(v_vec); -- return AND of the masked input fields
+ -- return AND of the masked input fields
+ return vector_and(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_and;
@@ -781,7 +846,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_and;
function func_dp_stream_arr_or(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '0');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -796,14 +862,17 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_or(v_vec); -- return OR of the masked input fields
+ -- return OR of the masked input fields
+ return vector_or(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_or;
function func_dp_stream_arr_or(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '0');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -820,9 +889,11 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_or(v_vec); -- return OR of the masked input fields
+ -- return OR of the masked input fields
+ return vector_or(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_or;
@@ -840,8 +911,10 @@ package body dp_stream_pkg is
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
- variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
- variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
+ -- default
+ variable v_dp : t_dp_siso_arr(dp'range) := dp;
+ -- map to ensure same range as for dp
+ variable v_slv : std_logic_vector(dp'range) := slv;
begin
for I in dp'range loop
if str = "READY" then v_dp(I).ready := v_slv(I);
@@ -853,8 +926,10 @@ package body dp_stream_pkg is
end func_dp_stream_arr_set;
function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- default
- variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
+ -- default
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
+ -- map to ensure same range as for dp
+ variable v_slv : std_logic_vector(dp'range) := slv;
begin
for I in dp'range loop
if str = "VALID" then v_dp(I).valid := v_slv(I);
@@ -1046,29 +1121,40 @@ package body dp_stream_pkg is
-- Functions to combinatorially hold the data fields and to set or reset the info and control fields in an sosi array
function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- v_dp := func_dp_stream_arr_set_info( v_dp, info); -- set sosi info
- v_dp := func_dp_stream_arr_set_control(v_dp, ctrl); -- set sosi ctrl
+ -- set sosi info
+ v_dp := func_dp_stream_arr_set_info( v_dp, info);
+ -- set sosi ctrl
+ v_dp := func_dp_stream_arr_set_control(v_dp, ctrl);
return v_dp;
end func_dp_stream_arr_combine_data_info_ctrl;
function func_dp_stream_arr_set_info(dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- set sosi info
- v_dp(I).bsn := info.bsn; -- sop
- v_dp(I).channel := info.channel; -- sop
- v_dp(I).empty := info.empty; -- eop
- v_dp(I).err := info.err; -- eop
+ -- set sosi info
+ for I in dp'range loop
+ -- sop
+ v_dp(I).bsn := info.bsn;
+ -- sop
+ v_dp(I).channel := info.channel;
+ -- eop
+ v_dp(I).empty := info.empty;
+ -- eop
+ v_dp(I).err := info.err;
end loop;
return v_dp;
end func_dp_stream_arr_set_info;
function func_dp_stream_arr_set_control(dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- set sosi control
+ -- set sosi control
+ for I in dp'range loop
v_dp(I).valid := ctrl.valid;
v_dp(I).sop := ctrl.sop;
v_dp(I).eop := ctrl.eop;
@@ -1078,9 +1164,11 @@ package body dp_stream_pkg is
end func_dp_stream_arr_set_control;
function func_dp_stream_arr_reset_control(dp : t_dp_sosi_arr) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- reset sosi control
+ -- reset sosi control
+ for I in dp'range loop
v_dp(I).valid := '0';
v_dp(I).sop := '0';
v_dp(I).eop := '0';
@@ -1090,7 +1178,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_reset_control;
function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi is
- variable v_dp : t_dp_sosi := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi := dp;
begin
-- reset sosi control
v_dp.valid := '0';
@@ -1102,7 +1191,8 @@ package body dp_stream_pkg is
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
- variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0'); -- init max v_bsn with minimum value
+ -- init max v_bsn with minimum value
+ variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0');
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1121,7 +1211,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_bsn_max;
function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
- variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1'); -- init min v_bsn with maximum value
+ -- init min v_bsn with maximum value
+ variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1');
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1142,7 +1233,8 @@ package body dp_stream_pkg is
-- Function to copy the BSN number of one valid stream to all other streams.
function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1200,10 +1292,12 @@ package body dp_stream_pkg is
end func_dp_stream_bsn_set;
function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
- variable v_rec : t_dp_sosi := data; -- Sosi data fields
+ -- Sosi data fields
+ variable v_rec : t_dp_sosi := data;
begin
-- Combine sosi data with the sosi info fields
- v_rec.sync := info.sync and data.sop; -- force sync only active at data.sop
+ -- force sync only active at data.sop
+ v_rec.sync := info.sync and data.sop;
v_rec.bsn := info.bsn;
v_rec.channel := info.channel;
v_rec.empty := info.empty;
@@ -1215,7 +1309,8 @@ package body dp_stream_pkg is
variable v_rec : t_dp_sosi_integer;
begin
v_rec.sync := slv_sosi.sync;
- v_rec.bsn := TO_UINT(slv_sosi.bsn(30 downto 0)); -- NATURAL'width = 31 bit
+ -- NATURAL'width = 31 bit
+ v_rec.bsn := TO_UINT(slv_sosi.bsn(30 downto 0));
v_rec.data := TO_SINT(slv_sosi.data(w - 1 downto 0));
v_rec.re := TO_SINT(slv_sosi.re(w - 1 downto 0));
v_rec.im := TO_SINT(slv_sosi.im(w - 1 downto 0));
@@ -1333,7 +1428,8 @@ package body dp_stream_pkg is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
- v_dp_arr(i) := func_dp_stream_complex_to_data(dp_arr(i), data_w, nof_data, data_order_im_re); -- nof_data per stream is 1
+ -- nof_data per stream is 1
+ v_dp_arr(i) := func_dp_stream_complex_to_data(dp_arr(i), data_w, nof_data, data_order_im_re);
end loop;
return v_dp_arr;
end;
@@ -1352,7 +1448,8 @@ package body dp_stream_pkg is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
- v_dp_arr(i) := func_dp_stream_data_to_complex(dp_arr(i), data_w, nof_data, data_order_im_re); -- nof_data per stream is 1
+ -- nof_data per stream is 1
+ v_dp_arr(i) := func_dp_stream_data_to_complex(dp_arr(i), data_w, nof_data, data_order_im_re);
end loop;
return v_dp_arr;
end;
@@ -1383,7 +1480,8 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
+ -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is
variable v_snk_out_arr : t_dp_siso_arr(nof_streams - 1 downto 0);
begin
for i in v_snk_out_arr'range loop
@@ -1398,7 +1496,8 @@ package body dp_stream_pkg is
constant c_compl_out_w : natural := out_w / 2;
variable v_src_out : t_dp_sosi := snk_in;
variable v_in_data : std_logic_vector(in_w - 1 downto 0);
- variable v_out_data : std_logic_vector(out_w - 1 downto 0) := (others => '0'); -- default set sosi.data to 0
+ -- default set sosi.data to 0
+ variable v_out_data : std_logic_vector(out_w - 1 downto 0) := (others => '0');
begin
v_src_out := snk_in;
v_src_out.data := (others => '0');
@@ -1406,10 +1505,12 @@ package body dp_stream_pkg is
v_src_out.im := (others => '0');
for i in 0 to nof_data - 1 loop
v_in_data := snk_in.data((i + 1) * in_w - 1 downto i * in_w);
- if data_representation = "UNSIGNED" then -- treat data as unsigned
+ -- treat data as unsigned
+ if data_representation = "UNSIGNED" then
v_out_data := RESIZE_UVEC(v_in_data, out_w);
else
- if data_representation = "SIGNED" then -- treat data as signed
+ -- treat data as signed
+ if data_representation = "SIGNED" then
v_out_data := RESIZE_SVEC(v_in_data, out_w);
else
-- treat data as complex
@@ -1467,7 +1568,8 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
+ -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is
begin
return src_out_arr(0);
end;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
index 103667575791b885ea6d707accd5dc6c04bcb535..86bd5f3ed9ef2f109669b4576b60ab58651ee0f0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
@@ -29,29 +29,39 @@ use dp_lib.dp_stream_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
- constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
- constant c_eth_empty_w : natural := c_tech_tse_empty_w; -- = ceil_log2(c_word_sz) = 2;
- constant c_eth_error_w : natural := c_tech_tse_error_w; -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
-
- constant c_eth_rx_ready_latency : natural := c_tech_tse_rx_ready_latency; -- = 2 = default when FIFO is used
- constant c_eth_tx_ready_latency : natural := c_tech_tse_tx_ready_latency; -- = 0, c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
- constant c_eth_ready_latency : natural := 1; -- = 1, fixed ETH module internal RL
+ -- = c_word_w
+ constant c_eth_data_w : natural := c_tech_tse_data_w;
+ -- = ceil_log2(c_word_sz) = 2;
+ constant c_eth_empty_w : natural := c_tech_tse_empty_w;
+ -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
+ constant c_eth_error_w : natural := c_tech_tse_error_w;
+
+ -- = 2 = default when FIFO is used
+ constant c_eth_rx_ready_latency : natural := c_tech_tse_rx_ready_latency;
+ -- = 0, c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
+ constant c_eth_tx_ready_latency : natural := c_tech_tse_tx_ready_latency;
+ -- = 1, fixed ETH module internal RL
+ constant c_eth_ready_latency : natural := 1;
-- Maximum feasible frame size
- constant c_eth_max_frame_sz : natural := 1024 * 9; -- 9 kByte fits 9020 = word align (2) + eth header (14) + maximum jumbo payload (9000) + CRC (4)
+ -- 9 kByte fits 9020 = word align (2) + eth header (14) + maximum jumbo payload (9000) + CRC (4)
+ constant c_eth_max_frame_sz : natural := 1024 * 9;
constant c_eth_max_frame_nof_words : natural := c_eth_max_frame_sz / c_word_sz;
- constant c_eth_max_frame_nof_words_w : natural := ceil_log2(c_eth_max_frame_nof_words); -- = 12 bit
+ -- = 12 bit
+ constant c_eth_max_frame_nof_words_w : natural := ceil_log2(c_eth_max_frame_nof_words);
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
-- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
- constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
+ -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
+ constant c_eth_frame_sz : natural := 1024 * 2;
-- when the module is used in an Nios II SOPC system
-- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
- constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
+ -- >= 9 bit, <= 12 bit
+ constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words);
type t_eth_data_arr is array (integer range <>) of std_logic_vector(c_eth_data_w - 1 downto 0);
@@ -79,8 +89,10 @@ package eth_pkg is
-- Definitions for eth demux udp
------------------------------------------------------------------------------
- constant c_eth_nof_udp_ports : natural := 4; -- support 2, 4, 8, ... UDP off-load ports
- constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1); -- + 1 for all other packets that go to the default port
+ -- support 2, 4, 8, ... UDP off-load ports
+ constant c_eth_nof_udp_ports : natural := 4;
+ -- + 1 for all other packets that go to the default port
+ constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1);
constant c_eth_nof_channels : natural := 2**c_eth_channel_w;
------------------------------------------------------------------------------
@@ -103,30 +115,46 @@ package eth_pkg is
-- . write/read back registers
type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
type t_eth_mm_reg_demux is record
- udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
- udp_ports : t_eth_demux_ports_arr; -- [15:0]
+ -- [16]
+ udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports);
+ -- [15:0]
+ udp_ports : t_eth_demux_ports_arr;
end record;
type t_eth_mm_reg_config is record
- udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- [15:0]
- ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- [31:0]
- mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- [15:0], [31:0]
+ -- [15:0]
+ udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- [31:0]
+ ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- [15:0], [31:0]
+ mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
end record;
type t_eth_mm_reg_control is record
- tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_request : std_logic; -- 1 bit
- tx_en : std_logic; -- 1 bit
- rx_en : std_logic; -- 1 bit
+ -- 12 bit
+ tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0);
+ -- 2 bit
+ tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0);
+ -- 1 bit
+ tx_request : std_logic;
+ -- 1 bit
+ tx_en : std_logic;
+ -- 1 bit
+ rx_en : std_logic;
end record;
- type t_eth_mm_reg_control_bi is record -- bit indices
- tx_nof_words : natural; -- [26:18]
- tx_empty : natural; -- [17:16]
- tx_request : natural; -- [2]
- tx_en : natural; -- [1]
- rx_en : natural; -- [0]
+ -- bit indices
+ type t_eth_mm_reg_control_bi is record
+ -- [26:18]
+ tx_nof_words : natural;
+ -- [17:16]
+ tx_empty : natural;
+ -- [2]
+ tx_request : natural;
+ -- [1]
+ tx_en : natural;
+ -- [0]
+ rx_en : natural;
end record;
constant c_eth_mm_reg_control_bi : t_eth_mm_reg_control_bi := (18, 16, 2, 1, 0);
@@ -146,36 +174,58 @@ package eth_pkg is
eth_mac_error : std_logic_vector(c_eth_error_w - 1 downto 0);
end record;
- type t_eth_mm_reg_frame_bi is record -- bit indices
- is_dhcp : natural; -- [15]
- is_udp_ctrl_port : natural; -- [14]
- is_udp : natural; -- [13]
- is_icmp : natural; -- [12]
- ip_address_match : natural; -- [11]
- ip_checksum_is_ok : natural; -- [10]
- is_ip : natural; -- [9]
- is_arp : natural; -- [8]
- mac_address_match : natural; -- [7]
- eth_mac_error : natural; -- [6] not used, [5:0] = TSE MAC error
+ -- bit indices
+ type t_eth_mm_reg_frame_bi is record
+ -- [15]
+ is_dhcp : natural;
+ -- [14]
+ is_udp_ctrl_port : natural;
+ -- [13]
+ is_udp : natural;
+ -- [12]
+ is_icmp : natural;
+ -- [11]
+ ip_address_match : natural;
+ -- [10]
+ ip_checksum_is_ok : natural;
+ -- [9]
+ is_ip : natural;
+ -- [8]
+ is_arp : natural;
+ -- [7]
+ mac_address_match : natural;
+ -- [6] not used, [5:0] = TSE MAC error
+ eth_mac_error : natural;
end record;
constant c_eth_mm_reg_frame_bi : t_eth_mm_reg_frame_bi := (15, 14, 13, 12, 11, 10, 9, 8, 7, 0);
constant c_eth_mm_reg_frame_rst : t_eth_mm_reg_frame := ('0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'));
type t_eth_mm_reg_status is record
- rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_avail : std_logic; -- 1 bit
- tx_done : std_logic; -- 1 bit
- rx_avail : std_logic; -- 1 bit
+ -- 12 bit
+ rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0);
+ -- 2 bit
+ rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0);
+ -- 1 bit
+ tx_avail : std_logic;
+ -- 1 bit
+ tx_done : std_logic;
+ -- 1 bit
+ rx_avail : std_logic;
end record;
- type t_eth_mm_reg_status_bi is record -- bit indices
- rx_nof_words : natural; -- [26:18]
- rx_empty : natural; -- [17:16]
- tx_avail : natural; -- [2]
- tx_done : natural; -- [1]
- rx_avail : natural; -- [0]
+ -- bit indices
+ type t_eth_mm_reg_status_bi is record
+ -- [26:18]
+ rx_nof_words : natural;
+ -- [17:16]
+ rx_empty : natural;
+ -- [2]
+ tx_avail : natural;
+ -- [1]
+ tx_done : natural;
+ -- [0]
+ rx_avail : natural;
end record;
constant c_eth_mm_reg_status_bi : t_eth_mm_reg_status_bi := (18, 16, 2, 1, 0);
@@ -202,7 +252,8 @@ package eth_pkg is
c_eth_reg_control_nof_words +
c_eth_reg_frame_nof_words +
c_eth_reg_status_nof_words;
- constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
+ -- + 1 for c_eth_continue_wi
+ constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1);
------------------------------------------------------------------------------
-- Definitions for ETH Rx packet buffer and Tx packet buffer
@@ -223,8 +274,10 @@ package body eth_pkg is
begin
-- Demux UDP MM registers
for I in 1 to c_eth_nof_udp_ports loop
- v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w); -- [16] = UDP port enable
- v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w); -- [15:0] = UDP port number
+ -- [16] = UDP port enable
+ v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w);
+ -- [15:0] = UDP port number
+ v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w);
end loop;
return v_reg;
@@ -233,10 +286,13 @@ package body eth_pkg is
function func_eth_mm_reg_demux(mm_reg : t_eth_mm_reg_demux) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_demux_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
+ -- rsvd
+ v_reg := (others => '0');
for I in 1 to c_eth_nof_udp_ports loop
- v_reg(c_network_udp_port_w + (I - 1) * c_word_w) := mm_reg.udp_ports_en(I); -- [16] = UDP port enable
- v_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w) := mm_reg.udp_ports(I); -- [15:0] = UDP port number
+ -- [16] = UDP port enable
+ v_reg(c_network_udp_port_w + (I - 1) * c_word_w) := mm_reg.udp_ports_en(I);
+ -- [15:0] = UDP port number
+ v_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w) := mm_reg.udp_ports(I);
end loop;
return v_reg;
end func_eth_mm_reg_demux;
@@ -245,21 +301,30 @@ package body eth_pkg is
function func_eth_mm_reg_config(mm_reg : std_logic_vector) return t_eth_mm_reg_config is
variable v_reg : t_eth_mm_reg_config;
begin
- v_reg.udp_port := mm_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w); -- [15:0] = control UDP port number
- v_reg.ip_address := mm_reg( 3 * c_word_w - 1 downto 2 * c_word_w); -- [31:0] = this node IP address
- v_reg.mac_address(47 downto 32) := mm_reg( c_halfword_w + c_word_w - 1 downto c_word_w); -- [47:32] = this node MAC address
- v_reg.mac_address(31 downto 0) := mm_reg( c_word_w - 1 downto 0); -- [31:0] = this node MAC address
+ -- [15:0] = control UDP port number
+ v_reg.udp_port := mm_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w);
+ -- [31:0] = this node IP address
+ v_reg.ip_address := mm_reg( 3 * c_word_w - 1 downto 2 * c_word_w);
+ -- [47:32] = this node MAC address
+ v_reg.mac_address(47 downto 32) := mm_reg( c_halfword_w + c_word_w - 1 downto c_word_w);
+ -- [31:0] = this node MAC address
+ v_reg.mac_address(31 downto 0) := mm_reg( c_word_w - 1 downto 0);
return v_reg;
end func_eth_mm_reg_config;
function func_eth_mm_reg_config(mm_reg : t_eth_mm_reg_config) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_config_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w) := mm_reg.udp_port; -- [15:0] = control UDP port number
- v_reg( 3 * c_word_w - 1 downto 2 * c_word_w) := mm_reg.ip_address; -- [31:0] = this node IP address
- v_reg( c_halfword_w + c_word_w - 1 downto c_word_w) := mm_reg.mac_address(47 downto 32); -- [47:32] = this node MAC address
- v_reg( c_word_w - 1 downto 0) := mm_reg.mac_address(31 downto 0); -- [31:0] = this node MAC address
+ -- rsvd
+ v_reg := (others => '0');
+ -- [15:0] = control UDP port number
+ v_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w) := mm_reg.udp_port;
+ -- [31:0] = this node IP address
+ v_reg( 3 * c_word_w - 1 downto 2 * c_word_w) := mm_reg.ip_address;
+ -- [47:32] = this node MAC address
+ v_reg( c_halfword_w + c_word_w - 1 downto c_word_w) := mm_reg.mac_address(47 downto 32);
+ -- [31:0] = this node MAC address
+ v_reg( c_word_w - 1 downto 0) := mm_reg.mac_address(31 downto 0);
return v_reg;
end func_eth_mm_reg_config;
@@ -267,23 +332,34 @@ package body eth_pkg is
function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control is
variable v_reg : t_eth_mm_reg_control;
begin
- v_reg.tx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
- v_reg.tx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16); -- [17:16]
- v_reg.tx_request := mm_reg( 2); -- [2]
- v_reg.tx_en := mm_reg( 1); -- [1]
- v_reg.rx_en := mm_reg( 0); -- [0]
+ -- [29:18]
+ v_reg.tx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16);
+ -- [17:16]
+ v_reg.tx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16);
+ -- [2]
+ v_reg.tx_request := mm_reg( 2);
+ -- [1]
+ v_reg.tx_en := mm_reg( 1);
+ -- [0]
+ v_reg.rx_en := mm_reg( 0);
return v_reg;
end func_eth_mm_reg_control;
function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_control_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.tx_nof_words; -- [29:18]
- v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.tx_empty; -- [17:16]
- v_reg( 2) := mm_reg.tx_request; -- [2]
- v_reg( 1) := mm_reg.tx_en; -- [1]
- v_reg( 0) := mm_reg.rx_en; -- [0]
+ -- rsvd
+ v_reg := (others => '0');
+ -- [29:18]
+ v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.tx_nof_words;
+ -- [17:16]
+ v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.tx_empty;
+ -- [2]
+ v_reg( 2) := mm_reg.tx_request;
+ -- [1]
+ v_reg( 1) := mm_reg.tx_en;
+ -- [0]
+ v_reg( 0) := mm_reg.rx_en;
return v_reg;
end func_eth_mm_reg_control;
@@ -291,33 +367,54 @@ package body eth_pkg is
function func_eth_mm_reg_frame(mm_reg : std_logic_vector) return t_eth_mm_reg_frame is
variable v_reg : t_eth_mm_reg_frame;
begin
- v_reg.is_dhcp := mm_reg( c_byte_w + 7); -- [15]
- v_reg.is_udp_ctrl_port := mm_reg( c_byte_w + 6); -- [14]
- v_reg.is_udp := mm_reg( c_byte_w + 5); -- [13]
- v_reg.is_icmp := mm_reg( c_byte_w + 4); -- [12]
- v_reg.ip_address_match := mm_reg( c_byte_w + 3); -- [11]
- v_reg.ip_checksum_is_ok := mm_reg( c_byte_w + 2); -- [10]
- v_reg.is_ip := mm_reg( c_byte_w + 1); -- [9]
- v_reg.is_arp := mm_reg( c_byte_w + 0); -- [8]
- v_reg.mac_address_match := mm_reg( c_byte_w - 1); -- [7]
- v_reg.eth_mac_error := mm_reg(c_eth_error_w - 1 downto 0); -- [7] not used, [5:0] = TSE MAC error
+ -- [15]
+ v_reg.is_dhcp := mm_reg( c_byte_w + 7);
+ -- [14]
+ v_reg.is_udp_ctrl_port := mm_reg( c_byte_w + 6);
+ -- [13]
+ v_reg.is_udp := mm_reg( c_byte_w + 5);
+ -- [12]
+ v_reg.is_icmp := mm_reg( c_byte_w + 4);
+ -- [11]
+ v_reg.ip_address_match := mm_reg( c_byte_w + 3);
+ -- [10]
+ v_reg.ip_checksum_is_ok := mm_reg( c_byte_w + 2);
+ -- [9]
+ v_reg.is_ip := mm_reg( c_byte_w + 1);
+ -- [8]
+ v_reg.is_arp := mm_reg( c_byte_w + 0);
+ -- [7]
+ v_reg.mac_address_match := mm_reg( c_byte_w - 1);
+ -- [7] not used, [5:0] = TSE MAC error
+ v_reg.eth_mac_error := mm_reg(c_eth_error_w - 1 downto 0);
return v_reg;
end func_eth_mm_reg_frame;
function func_eth_mm_reg_frame(mm_reg : t_eth_mm_reg_frame) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_frame_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg( c_byte_w + 7) := mm_reg.is_dhcp; -- [15]
- v_reg( c_byte_w + 6) := mm_reg.is_udp_ctrl_port; -- [14]
- v_reg( c_byte_w + 5) := mm_reg.is_udp; -- [13]
- v_reg( c_byte_w + 4) := mm_reg.is_icmp; -- [12]
- v_reg( c_byte_w + 3) := mm_reg.ip_address_match; -- [11]
- v_reg( c_byte_w + 2) := mm_reg.ip_checksum_is_ok; -- [10]
- v_reg( c_byte_w + 1) := mm_reg.is_ip; -- [9]
- v_reg( c_byte_w + 0) := mm_reg.is_arp; -- [8]
- v_reg( c_byte_w - 1) := mm_reg.mac_address_match; -- [7]
- v_reg(c_eth_error_w - 1 downto 0) := mm_reg.eth_mac_error; -- [6] not used, [5:0] = TSE MAC error
+ -- rsvd
+ v_reg := (others => '0');
+ -- [15]
+ v_reg( c_byte_w + 7) := mm_reg.is_dhcp;
+ -- [14]
+ v_reg( c_byte_w + 6) := mm_reg.is_udp_ctrl_port;
+ -- [13]
+ v_reg( c_byte_w + 5) := mm_reg.is_udp;
+ -- [12]
+ v_reg( c_byte_w + 4) := mm_reg.is_icmp;
+ -- [11]
+ v_reg( c_byte_w + 3) := mm_reg.ip_address_match;
+ -- [10]
+ v_reg( c_byte_w + 2) := mm_reg.ip_checksum_is_ok;
+ -- [9]
+ v_reg( c_byte_w + 1) := mm_reg.is_ip;
+ -- [8]
+ v_reg( c_byte_w + 0) := mm_reg.is_arp;
+ -- [7]
+ v_reg( c_byte_w - 1) := mm_reg.mac_address_match;
+ -- [6] not used, [5:0] = TSE MAC error
+ v_reg(c_eth_error_w - 1 downto 0) := mm_reg.eth_mac_error;
return v_reg;
end func_eth_mm_reg_frame;
@@ -325,23 +422,34 @@ package body eth_pkg is
function func_eth_mm_reg_status(mm_reg : std_logic_vector) return t_eth_mm_reg_status is
variable v_reg : t_eth_mm_reg_status;
begin
- v_reg.rx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
- v_reg.rx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16); -- [17:16]
- v_reg.tx_avail := mm_reg( 2); -- [2]
- v_reg.tx_done := mm_reg( 1); -- [1]
- v_reg.rx_avail := mm_reg( 0); -- [0]
+ -- [29:18]
+ v_reg.rx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16);
+ -- [17:16]
+ v_reg.rx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16);
+ -- [2]
+ v_reg.tx_avail := mm_reg( 2);
+ -- [1]
+ v_reg.tx_done := mm_reg( 1);
+ -- [0]
+ v_reg.rx_avail := mm_reg( 0);
return v_reg;
end func_eth_mm_reg_status;
function func_eth_mm_reg_status(mm_reg : t_eth_mm_reg_status) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_status_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.rx_nof_words; -- [29:18]
- v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.rx_empty; -- [17:16]
- v_reg( 2) := mm_reg.tx_avail; -- [2]
- v_reg( 1) := mm_reg.tx_done; -- [1]
- v_reg( 0) := mm_reg.rx_avail; -- [0]
+ -- rsvd
+ v_reg := (others => '0');
+ -- [29:18]
+ v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.rx_nof_words;
+ -- [17:16]
+ v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.rx_empty;
+ -- [2]
+ v_reg( 2) := mm_reg.tx_avail;
+ -- [1]
+ v_reg( 1) := mm_reg.tx_done;
+ -- [0]
+ v_reg( 0) := mm_reg.rx_avail;
return v_reg;
end func_eth_mm_reg_status;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
index 177eb750c7386763043b7282d1bfb4b3a3fc6636..ada21504435ae1849069b8859e9aad66318061d1 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
@@ -25,19 +25,28 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
package tech_tse_pkg is
- constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
+ -- = max 256 MAC registers
+ constant c_tech_tse_reg_addr_w : natural := 8;
constant c_tech_tse_byte_addr_w : natural := c_tech_tse_reg_addr_w + 2;
- constant c_tech_tse_byte_addr_pcs_offset : natural := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
- constant c_tech_tse_data_w : natural := c_word_w; -- = 32
+ -- table 4.8, 4.9 in ug_ethernet.pdf
+ constant c_tech_tse_byte_addr_pcs_offset : natural := 16#200#;
+ -- = 32
+ constant c_tech_tse_data_w : natural := c_word_w;
- constant c_tech_tse_symbol_w : natural := c_byte_w; -- = 8
- constant c_tech_tse_symbol_max : natural := 2**c_tech_tse_symbol_w - 1; -- = 255
- constant c_tech_tse_symbols_per_beat : natural := c_tech_tse_data_w / c_tech_tse_symbol_w; -- = 4
+ -- = 8
+ constant c_tech_tse_symbol_w : natural := c_byte_w;
+ -- = 255
+ constant c_tech_tse_symbol_max : natural := 2**c_tech_tse_symbol_w - 1;
+ -- = 4
+ constant c_tech_tse_symbols_per_beat : natural := c_tech_tse_data_w / c_tech_tse_symbol_w;
- constant c_tech_tse_pcs_reg_addr_w : natural := 5; -- = max 32 PCS registers
- constant c_tech_tse_pcs_halfword_addr_w : natural := c_tech_tse_pcs_reg_addr_w + 1; -- table 4.17 in ug_ethernet.pdf
+ -- = max 32 PCS registers
+ constant c_tech_tse_pcs_reg_addr_w : natural := 5;
+ -- table 4.17 in ug_ethernet.pdf
+ constant c_tech_tse_pcs_halfword_addr_w : natural := c_tech_tse_pcs_reg_addr_w + 1;
constant c_tech_tse_pcs_byte_addr_w : natural := c_tech_tse_pcs_reg_addr_w + 2;
- constant c_tech_tse_pcs_data_w : natural := c_halfword_w; -- = 16;
+ -- = 16;
+ constant c_tech_tse_pcs_data_w : natural := c_halfword_w;
constant c_tech_tse_empty_w : natural := 2;
constant c_tech_tse_tx_error_w : natural := 1;
@@ -46,11 +55,15 @@ package tech_tse_pkg is
constant c_tech_tse_err_stat_w : natural := 18;
constant c_tech_tse_frm_type_w : natural := 4;
- constant c_tech_tse_rx_ready_latency : natural := 2; -- 2 = default when FIFO is used
- constant c_tech_tse_tx_ready_latency : natural := 1; -- c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
+ -- 2 = default when FIFO is used
+ constant c_tech_tse_rx_ready_latency : natural := 2;
+ -- c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
+ constant c_tech_tse_tx_ready_latency : natural := 1;
- constant c_tech_tse_tx_fifo_depth : natural := 256; -- nof words for Tx FIFO
- constant c_tech_tse_rx_fifo_depth : natural := 256; -- nof words for Rx FIFO
+ -- nof words for Tx FIFO
+ constant c_tech_tse_tx_fifo_depth : natural := 256;
+ -- nof words for Rx FIFO
+ constant c_tech_tse_rx_fifo_depth : natural := 256;
type t_tech_tse_tx_mac is record
-- Tx MAC inputs
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
index 06df7d37f4b4ceeb07d517f45c42b0cfa1cac3f2..9a85eb333d9be54b8cf2161d1fc1162280487fd2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
@@ -1,84 +1,160 @@
component qsys_unb2b_minimal_avs_eth_0 is
port (
- coe_clk_export : out std_logic; -- export
- ins_interrupt_irq : out std_logic; -- irq
- coe_irq_export : in std_logic := 'X'; -- export
- csi_mm_clk : in std_logic := 'X'; -- clk
- csi_mm_reset : in std_logic := 'X'; -- reset
- mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_ram_write : in std_logic := 'X'; -- write
- mms_ram_read : in std_logic := 'X'; -- read
- mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_ram_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
- mms_reg_write : in std_logic := 'X'; -- write
- mms_reg_read : in std_logic := 'X'; -- read
- mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_reg_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_tse_write : in std_logic := 'X'; -- write
- mms_tse_read : in std_logic := 'X'; -- read
- mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_tse_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_waitrequest : out std_logic; -- waitrequest
- coe_ram_address_export : out std_logic_vector(9 downto 0); -- export
- coe_ram_read_export : out std_logic; -- export
- coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_write_export : out std_logic; -- export
- coe_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reg_address_export : out std_logic_vector(3 downto 0); -- export
- coe_reg_read_export : out std_logic; -- export
- coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reg_write_export : out std_logic; -- export
- coe_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reset_export : out std_logic; -- export
- coe_tse_address_export : out std_logic_vector(9 downto 0); -- export
- coe_tse_read_export : out std_logic; -- export
- coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_tse_waitrequest_export : in std_logic := 'X'; -- export
- coe_tse_write_export : out std_logic; -- export
- coe_tse_writedata_export : out std_logic_vector(31 downto 0) -- export
+ -- export
+ coe_clk_export : out std_logic;
+ -- irq
+ ins_interrupt_irq : out std_logic;
+ -- export
+ coe_irq_export : in std_logic := 'X';
+ -- clk
+ csi_mm_clk : in std_logic := 'X';
+ -- reset
+ csi_mm_reset : in std_logic := 'X';
+ -- address
+ mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X');
+ -- write
+ mms_ram_write : in std_logic := 'X';
+ -- read
+ mms_ram_read : in std_logic := 'X';
+ -- writedata
+ mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- readdata
+ mms_ram_readdata : out std_logic_vector(31 downto 0);
+ -- address
+ mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- write
+ mms_reg_write : in std_logic := 'X';
+ -- read
+ mms_reg_read : in std_logic := 'X';
+ -- writedata
+ mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- readdata
+ mms_reg_readdata : out std_logic_vector(31 downto 0);
+ -- address
+ mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X');
+ -- write
+ mms_tse_write : in std_logic := 'X';
+ -- read
+ mms_tse_read : in std_logic := 'X';
+ -- writedata
+ mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- readdata
+ mms_tse_readdata : out std_logic_vector(31 downto 0);
+ -- waitrequest
+ mms_tse_waitrequest : out std_logic;
+ -- export
+ coe_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ coe_ram_read_export : out std_logic;
+ -- export
+ coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_ram_write_export : out std_logic;
+ -- export
+ coe_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ coe_reg_read_export : out std_logic;
+ -- export
+ coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_reg_write_export : out std_logic;
+ -- export
+ coe_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reset_export : out std_logic;
+ -- export
+ coe_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ coe_tse_read_export : out std_logic;
+ -- export
+ coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ coe_tse_write_export : out std_logic;
+ -- export
+ coe_tse_writedata_export : out std_logic_vector(31 downto 0)
);
end component qsys_unb2b_minimal_avs_eth_0;
u0 : component qsys_unb2b_minimal_avs_eth_0
port map (
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq, -- interrupt.irq
- coe_irq_export => CONNECTED_TO_coe_irq_export, -- irq.export
- csi_mm_clk => CONNECTED_TO_csi_mm_clk, -- mm.clk
- csi_mm_reset => CONNECTED_TO_csi_mm_reset, -- mm_reset.reset
- mms_ram_address => CONNECTED_TO_mms_ram_address, -- mms_ram.address
- mms_ram_write => CONNECTED_TO_mms_ram_write, -- .write
- mms_ram_read => CONNECTED_TO_mms_ram_read, -- .read
- mms_ram_writedata => CONNECTED_TO_mms_ram_writedata, -- .writedata
- mms_ram_readdata => CONNECTED_TO_mms_ram_readdata, -- .readdata
- mms_reg_address => CONNECTED_TO_mms_reg_address, -- mms_reg.address
- mms_reg_write => CONNECTED_TO_mms_reg_write, -- .write
- mms_reg_read => CONNECTED_TO_mms_reg_read, -- .read
- mms_reg_writedata => CONNECTED_TO_mms_reg_writedata, -- .writedata
- mms_reg_readdata => CONNECTED_TO_mms_reg_readdata, -- .readdata
- mms_tse_address => CONNECTED_TO_mms_tse_address, -- mms_tse.address
- mms_tse_write => CONNECTED_TO_mms_tse_write, -- .write
- mms_tse_read => CONNECTED_TO_mms_tse_read, -- .read
- mms_tse_writedata => CONNECTED_TO_mms_tse_writedata, -- .writedata
- mms_tse_readdata => CONNECTED_TO_mms_tse_readdata, -- .readdata
- mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest, -- .waitrequest
- coe_ram_address_export => CONNECTED_TO_coe_ram_address_export, -- ram_address.export
- coe_ram_read_export => CONNECTED_TO_coe_ram_read_export, -- ram_read.export
- coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export, -- ram_readdata.export
- coe_ram_write_export => CONNECTED_TO_coe_ram_write_export, -- ram_write.export
- coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export, -- ram_writedata.export
- coe_reg_address_export => CONNECTED_TO_coe_reg_address_export, -- reg_address.export
- coe_reg_read_export => CONNECTED_TO_coe_reg_read_export, -- reg_read.export
- coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export, -- reg_readdata.export
- coe_reg_write_export => CONNECTED_TO_coe_reg_write_export, -- reg_write.export
- coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export, -- reg_writedata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- coe_tse_address_export => CONNECTED_TO_coe_tse_address_export, -- tse_address.export
- coe_tse_read_export => CONNECTED_TO_coe_tse_read_export, -- tse_read.export
- coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export, -- tse_readdata.export
- coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
- coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
- coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- interrupt.irq
+ ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq,
+ -- irq.export
+ coe_irq_export => CONNECTED_TO_coe_irq_export,
+ -- mm.clk
+ csi_mm_clk => CONNECTED_TO_csi_mm_clk,
+ -- mm_reset.reset
+ csi_mm_reset => CONNECTED_TO_csi_mm_reset,
+ -- mms_ram.address
+ mms_ram_address => CONNECTED_TO_mms_ram_address,
+ -- .write
+ mms_ram_write => CONNECTED_TO_mms_ram_write,
+ -- .read
+ mms_ram_read => CONNECTED_TO_mms_ram_read,
+ -- .writedata
+ mms_ram_writedata => CONNECTED_TO_mms_ram_writedata,
+ -- .readdata
+ mms_ram_readdata => CONNECTED_TO_mms_ram_readdata,
+ -- mms_reg.address
+ mms_reg_address => CONNECTED_TO_mms_reg_address,
+ -- .write
+ mms_reg_write => CONNECTED_TO_mms_reg_write,
+ -- .read
+ mms_reg_read => CONNECTED_TO_mms_reg_read,
+ -- .writedata
+ mms_reg_writedata => CONNECTED_TO_mms_reg_writedata,
+ -- .readdata
+ mms_reg_readdata => CONNECTED_TO_mms_reg_readdata,
+ -- mms_tse.address
+ mms_tse_address => CONNECTED_TO_mms_tse_address,
+ -- .write
+ mms_tse_write => CONNECTED_TO_mms_tse_write,
+ -- .read
+ mms_tse_read => CONNECTED_TO_mms_tse_read,
+ -- .writedata
+ mms_tse_writedata => CONNECTED_TO_mms_tse_writedata,
+ -- .readdata
+ mms_tse_readdata => CONNECTED_TO_mms_tse_readdata,
+ -- .waitrequest
+ mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest,
+ -- ram_address.export
+ coe_ram_address_export => CONNECTED_TO_coe_ram_address_export,
+ -- ram_read.export
+ coe_ram_read_export => CONNECTED_TO_coe_ram_read_export,
+ -- ram_readdata.export
+ coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export,
+ -- ram_write.export
+ coe_ram_write_export => CONNECTED_TO_coe_ram_write_export,
+ -- ram_writedata.export
+ coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export,
+ -- reg_address.export
+ coe_reg_address_export => CONNECTED_TO_coe_reg_address_export,
+ -- reg_read.export
+ coe_reg_read_export => CONNECTED_TO_coe_reg_read_export,
+ -- reg_readdata.export
+ coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export,
+ -- reg_write.export
+ coe_reg_write_export => CONNECTED_TO_coe_reg_write_export,
+ -- reg_writedata.export
+ coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- tse_address.export
+ coe_tse_address_export => CONNECTED_TO_coe_tse_address_export,
+ -- tse_read.export
+ coe_tse_read_export => CONNECTED_TO_coe_tse_read_export,
+ -- tse_readdata.export
+ coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export,
+ -- tse_waitrequest.export
+ coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export,
+ -- tse_write.export
+ coe_tse_write_export => CONNECTED_TO_coe_tse_write_export,
+ -- tse_writedata.export
+ coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
index fafd41bbfa80eae91afc0da3d18e2f4b799f6a95..7a1137fb1ee7d1624d7bb3f6d2fe54ed91502252 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
@@ -1,16 +1,24 @@
component qsys_unb2b_minimal_clk_0 is
port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
+ -- clk
+ clk_out : out std_logic;
+ -- clk
+ in_clk : in std_logic := 'X';
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- reset_n
+ reset_n_out : out std_logic
);
end component qsys_unb2b_minimal_clk_0;
u0 : component qsys_unb2b_minimal_clk_0
port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ -- clk.clk
+ clk_out => CONNECTED_TO_clk_out,
+ -- clk_in.clk
+ in_clk => CONNECTED_TO_in_clk,
+ -- clk_in_reset.reset_n
+ reset_n => CONNECTED_TO_reset_n,
+ -- clk_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
index 38fce9676fd1136ba002d70216e0ae804269cd9f..ce3af1016d3b93cea26457f43df6edd09734e79d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
@@ -1,60 +1,112 @@
component qsys_unb2b_minimal_cpu_0 is
port (
- clk : in std_logic := 'X'; -- clk
- dummy_ci_port : out std_logic; -- readra
- d_address : out std_logic_vector(19 downto 0); -- address
- d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
- d_read : out std_logic; -- read
- d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- d_waitrequest : in std_logic := 'X'; -- waitrequest
- d_write : out std_logic; -- write
- d_writedata : out std_logic_vector(31 downto 0); -- writedata
- debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
- debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
- debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
- debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
- debug_mem_slave_read : in std_logic := 'X'; -- read
- debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
- debug_mem_slave_waitrequest : out std_logic; -- waitrequest
- debug_mem_slave_write : in std_logic := 'X'; -- write
- debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- debug_reset_request : out std_logic; -- reset
- i_address : out std_logic_vector(17 downto 0); -- address
- i_read : out std_logic; -- read
- i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- i_waitrequest : in std_logic := 'X'; -- waitrequest
- irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- reset_req : in std_logic := 'X' -- reset_req
+ -- clk
+ clk : in std_logic := 'X';
+ -- readra
+ dummy_ci_port : out std_logic;
+ -- address
+ d_address : out std_logic_vector(19 downto 0);
+ -- byteenable
+ d_byteenable : out std_logic_vector(3 downto 0);
+ -- read
+ d_read : out std_logic;
+ -- readdata
+ d_readdata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- waitrequest
+ d_waitrequest : in std_logic := 'X';
+ -- write
+ d_write : out std_logic;
+ -- writedata
+ d_writedata : out std_logic_vector(31 downto 0);
+ -- debugaccess
+ debug_mem_slave_debugaccess_to_roms : out std_logic;
+ -- address
+ debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X');
+ -- byteenable
+ debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- debugaccess
+ debug_mem_slave_debugaccess : in std_logic := 'X';
+ -- read
+ debug_mem_slave_read : in std_logic := 'X';
+ -- readdata
+ debug_mem_slave_readdata : out std_logic_vector(31 downto 0);
+ -- waitrequest
+ debug_mem_slave_waitrequest : out std_logic;
+ -- write
+ debug_mem_slave_write : in std_logic := 'X';
+ -- writedata
+ debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- reset
+ debug_reset_request : out std_logic;
+ -- address
+ i_address : out std_logic_vector(17 downto 0);
+ -- read
+ i_read : out std_logic;
+ -- readdata
+ i_readdata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- waitrequest
+ i_waitrequest : in std_logic := 'X';
+ -- irq
+ irq : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- reset_req
+ reset_req : in std_logic := 'X'
);
end component qsys_unb2b_minimal_cpu_0;
u0 : component qsys_unb2b_minimal_cpu_0
port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
- d_address => CONNECTED_TO_d_address, -- data_master.address
- d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
- d_read => CONNECTED_TO_d_read, -- .read
- d_readdata => CONNECTED_TO_d_readdata, -- .readdata
- d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
- d_write => CONNECTED_TO_d_write, -- .write
- d_writedata => CONNECTED_TO_d_writedata, -- .writedata
- debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
- debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
- debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
- debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
- debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
- debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
- debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
- debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
- debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
- debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
- i_address => CONNECTED_TO_i_address, -- instruction_master.address
- i_read => CONNECTED_TO_i_read, -- .read
- i_readdata => CONNECTED_TO_i_readdata, -- .readdata
- i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- reset_req => CONNECTED_TO_reset_req -- .reset_req
+ -- clk.clk
+ clk => CONNECTED_TO_clk,
+ -- custom_instruction_master.readra
+ dummy_ci_port => CONNECTED_TO_dummy_ci_port,
+ -- data_master.address
+ d_address => CONNECTED_TO_d_address,
+ -- .byteenable
+ d_byteenable => CONNECTED_TO_d_byteenable,
+ -- .read
+ d_read => CONNECTED_TO_d_read,
+ -- .readdata
+ d_readdata => CONNECTED_TO_d_readdata,
+ -- .waitrequest
+ d_waitrequest => CONNECTED_TO_d_waitrequest,
+ -- .write
+ d_write => CONNECTED_TO_d_write,
+ -- .writedata
+ d_writedata => CONNECTED_TO_d_writedata,
+ -- .debugaccess
+ debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms,
+ -- debug_mem_slave.address
+ debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address,
+ -- .byteenable
+ debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable,
+ -- .debugaccess
+ debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess,
+ -- .read
+ debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read,
+ -- .readdata
+ debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata,
+ -- .waitrequest
+ debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest,
+ -- .write
+ debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write,
+ -- .writedata
+ debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata,
+ -- debug_reset_request.reset
+ debug_reset_request => CONNECTED_TO_debug_reset_request,
+ -- instruction_master.address
+ i_address => CONNECTED_TO_i_address,
+ -- .read
+ i_read => CONNECTED_TO_i_read,
+ -- .readdata
+ i_readdata => CONNECTED_TO_i_readdata,
+ -- .waitrequest
+ i_waitrequest => CONNECTED_TO_i_waitrequest,
+ -- irq.irq
+ irq => CONNECTED_TO_irq,
+ -- reset.reset_n
+ reset_n => CONNECTED_TO_reset_n,
+ -- .reset_req
+ reset_req => CONNECTED_TO_reset_req
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
index c76f427acbe4d282fd1db94d2af4ffdce37d9027..7907cbe1445b3078ee1487926d59879c64d018cc 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
@@ -1,100 +1,192 @@
component qsys_unb2b_minimal_jesd204 is
port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
+ -- export
+ alldev_lane_aligned : in std_logic := 'X';
+ -- export
+ csr_cf : out std_logic_vector(4 downto 0);
+ -- export
+ csr_cs : out std_logic_vector(1 downto 0);
+ -- export
+ csr_f : out std_logic_vector(7 downto 0);
+ -- export
+ csr_hd : out std_logic;
+ -- export
+ csr_k : out std_logic_vector(4 downto 0);
+ -- export
+ csr_l : out std_logic_vector(4 downto 0);
+ -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0);
+ -- export
+ csr_m : out std_logic_vector(7 downto 0);
+ -- export
+ csr_n : out std_logic_vector(4 downto 0);
+ -- export
+ csr_np : out std_logic_vector(4 downto 0);
+ -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0);
+ -- export
+ csr_s : out std_logic_vector(4 downto 0);
+ -- export
+ dev_lane_aligned : out std_logic;
+ -- export
+ dev_sync_n : out std_logic;
+ -- chipselect
+ jesd204_rx_avs_chipselect : in std_logic := 'X';
+ -- address
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X');
+ -- read
+ jesd204_rx_avs_read : in std_logic := 'X';
+ -- readdata
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0);
+ -- waitrequest
+ jesd204_rx_avs_waitrequest : out std_logic;
+ -- write
+ jesd204_rx_avs_write : in std_logic := 'X';
+ -- writedata
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- clk
+ jesd204_rx_avs_clk : in std_logic := 'X';
+ -- reset_n
+ jesd204_rx_avs_rst_n : in std_logic := 'X';
+ -- export
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_frame_error : in std_logic := 'X';
+ -- irq
+ jesd204_rx_int : out std_logic;
+ -- data
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0);
+ -- valid
+ jesd204_rx_link_valid : out std_logic;
+ -- ready
+ jesd204_rx_link_ready : in std_logic := 'X';
+ -- clk
+ pll_ref_clk : in std_logic := 'X';
+ -- rx_analogreset
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_cal_busy
+ rx_cal_busy : out std_logic_vector(0 downto 0);
+ -- rx_digitalreset
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_is_lockedtodata
+ rx_islockedtodata : out std_logic_vector(0 downto 0);
+ -- rx_serial_data
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- clk
+ rxlink_clk : in std_logic := 'X';
+ -- reset_n
+ rxlink_rst_n_reset_n : in std_logic := 'X';
+ -- export
+ rxphy_clk : out std_logic_vector(0 downto 0);
+ -- export
+ sof : out std_logic_vector(3 downto 0);
+ -- export
+ somf : out std_logic_vector(3 downto 0);
+ -- export
+ sysref : in std_logic := 'X'
);
end component qsys_unb2b_minimal_jesd204;
u0 : component qsys_unb2b_minimal_jesd204
port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
+ -- alldev_lane_aligned.export
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned,
+ -- csr_cf.export
+ csr_cf => CONNECTED_TO_csr_cf,
+ -- csr_cs.export
+ csr_cs => CONNECTED_TO_csr_cs,
+ -- csr_f.export
+ csr_f => CONNECTED_TO_csr_f,
+ -- csr_hd.export
+ csr_hd => CONNECTED_TO_csr_hd,
+ -- csr_k.export
+ csr_k => CONNECTED_TO_csr_k,
+ -- csr_l.export
+ csr_l => CONNECTED_TO_csr_l,
+ -- csr_lane_powerdown.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown,
+ -- csr_m.export
+ csr_m => CONNECTED_TO_csr_m,
+ -- csr_n.export
+ csr_n => CONNECTED_TO_csr_n,
+ -- csr_np.export
+ csr_np => CONNECTED_TO_csr_np,
+ -- csr_rx_testmode.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode,
+ -- csr_s.export
+ csr_s => CONNECTED_TO_csr_s,
+ -- dev_lane_aligned.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned,
+ -- dev_sync_n.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n,
+ -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect,
+ -- .address
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address,
+ -- .read
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read,
+ -- .readdata
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata,
+ -- .waitrequest
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest,
+ -- .write
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write,
+ -- .writedata
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata,
+ -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk,
+ -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n,
+ -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data,
+ -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid,
+ -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr,
+ -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect,
+ -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data,
+ -- jesd204_rx_frame_error.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error,
+ -- jesd204_rx_int.irq
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int,
+ -- jesd204_rx_link.data
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data,
+ -- .valid
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid,
+ -- .ready
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready,
+ -- pll_ref_clk.clk
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk,
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset => CONNECTED_TO_rx_analogreset,
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy,
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset,
+ -- rx_islockedtodata.rx_is_lockedtodata
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata,
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data => CONNECTED_TO_rx_serial_data,
+ -- rxlink_clk.clk
+ rxlink_clk => CONNECTED_TO_rxlink_clk,
+ -- rxlink_rst_n.reset_n
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n,
+ -- rxphy_clk.export
+ rxphy_clk => CONNECTED_TO_rxphy_clk,
+ -- sof.export
+ sof => CONNECTED_TO_sof,
+ -- somf.export
+ somf => CONNECTED_TO_somf,
+ -- sysref.export
+ sysref => CONNECTED_TO_sysref
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
index bc11c57e416cd6de852d448d82730d0e93d92791..49260e639cf8400d7bd28a33c4095c6a5ce39014 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
@@ -1,28 +1,48 @@
component qsys_unb2b_minimal_jtag_uart_0 is
port (
- av_chipselect : in std_logic := 'X'; -- chipselect
- av_address : in std_logic := 'X'; -- address
- av_read_n : in std_logic := 'X'; -- read_n
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_write_n : in std_logic := 'X'; -- write_n
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_waitrequest : out std_logic; -- waitrequest
- clk : in std_logic := 'X'; -- clk
- av_irq : out std_logic; -- irq
- rst_n : in std_logic := 'X' -- reset_n
+ -- chipselect
+ av_chipselect : in std_logic := 'X';
+ -- address
+ av_address : in std_logic := 'X';
+ -- read_n
+ av_read_n : in std_logic := 'X';
+ -- readdata
+ av_readdata : out std_logic_vector(31 downto 0);
+ -- write_n
+ av_write_n : in std_logic := 'X';
+ -- writedata
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- waitrequest
+ av_waitrequest : out std_logic;
+ -- clk
+ clk : in std_logic := 'X';
+ -- irq
+ av_irq : out std_logic;
+ -- reset_n
+ rst_n : in std_logic := 'X'
);
end component qsys_unb2b_minimal_jtag_uart_0;
u0 : component qsys_unb2b_minimal_jtag_uart_0
port map (
- av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
- av_address => CONNECTED_TO_av_address, -- .address
- av_read_n => CONNECTED_TO_av_read_n, -- .read_n
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_write_n => CONNECTED_TO_av_write_n, -- .write_n
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
- clk => CONNECTED_TO_clk, -- clk.clk
- av_irq => CONNECTED_TO_av_irq, -- irq.irq
- rst_n => CONNECTED_TO_rst_n -- reset.reset_n
+ -- avalon_jtag_slave.chipselect
+ av_chipselect => CONNECTED_TO_av_chipselect,
+ -- .address
+ av_address => CONNECTED_TO_av_address,
+ -- .read_n
+ av_read_n => CONNECTED_TO_av_read_n,
+ -- .readdata
+ av_readdata => CONNECTED_TO_av_readdata,
+ -- .write_n
+ av_write_n => CONNECTED_TO_av_write_n,
+ -- .writedata
+ av_writedata => CONNECTED_TO_av_writedata,
+ -- .waitrequest
+ av_waitrequest => CONNECTED_TO_av_waitrequest,
+ -- clk.clk
+ clk => CONNECTED_TO_clk,
+ -- irq.irq
+ av_irq => CONNECTED_TO_av_irq,
+ -- reset.reset_n
+ rst_n => CONNECTED_TO_rst_n
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
index f453120efc4f037dc4efbc07b42a93186450fe1d..0f577a2f63cf1f10cd5a119d56b14c7162d3e2b6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
@@ -1,28 +1,48 @@
component qsys_unb2b_minimal_onchip_memory2_0 is
port (
- clk : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- reset_req : in std_logic := 'X'; -- reset_req
- address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
- clken : in std_logic := 'X'; -- clken
- chipselect : in std_logic := 'X'; -- chipselect
- write : in std_logic := 'X'; -- write
- readdata : out std_logic_vector(31 downto 0); -- readdata
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
+ -- clk
+ clk : in std_logic := 'X';
+ -- reset
+ reset : in std_logic := 'X';
+ -- reset_req
+ reset_req : in std_logic := 'X';
+ -- address
+ address : in std_logic_vector(14 downto 0) := (others => 'X');
+ -- clken
+ clken : in std_logic := 'X';
+ -- chipselect
+ chipselect : in std_logic := 'X';
+ -- write
+ write : in std_logic := 'X';
+ -- readdata
+ readdata : out std_logic_vector(31 downto 0);
+ -- writedata
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- byteenable
+ byteenable : in std_logic_vector(3 downto 0) := (others => 'X')
);
end component qsys_unb2b_minimal_onchip_memory2_0;
u0 : component qsys_unb2b_minimal_onchip_memory2_0
port map (
- clk => CONNECTED_TO_clk, -- clk1.clk
- reset => CONNECTED_TO_reset, -- reset1.reset
- reset_req => CONNECTED_TO_reset_req, -- .reset_req
- address => CONNECTED_TO_address, -- s1.address
- clken => CONNECTED_TO_clken, -- .clken
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write => CONNECTED_TO_write, -- .write
- readdata => CONNECTED_TO_readdata, -- .readdata
- writedata => CONNECTED_TO_writedata, -- .writedata
- byteenable => CONNECTED_TO_byteenable -- .byteenable
+ -- clk1.clk
+ clk => CONNECTED_TO_clk,
+ -- reset1.reset
+ reset => CONNECTED_TO_reset,
+ -- .reset_req
+ reset_req => CONNECTED_TO_reset_req,
+ -- s1.address
+ address => CONNECTED_TO_address,
+ -- .clken
+ clken => CONNECTED_TO_clken,
+ -- .chipselect
+ chipselect => CONNECTED_TO_chipselect,
+ -- .write
+ write => CONNECTED_TO_write,
+ -- .readdata
+ readdata => CONNECTED_TO_readdata,
+ -- .writedata
+ writedata => CONNECTED_TO_writedata,
+ -- .byteenable
+ byteenable => CONNECTED_TO_byteenable
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
index 580187433d6ad3516adc8f3613297cd106f122a7..b17847229b01e7609d4b13e411ef62fd233e2ed0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_pio_pps;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
index b05a01d44469adf2ce2a5524f755a45e93ee3b55..8469f7c897471d0d4920cde1932b898c48e2184d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_pio_system_info;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
index 4639e141f52b87b436009b6f01944420186ed973..2050a6446f527e4b71f2bde2a1e901b18c675eb2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
@@ -1,24 +1,40 @@
component qsys_unb2b_minimal_pio_wdi is
port (
- clk : in std_logic := 'X'; -- clk
- out_port : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
- write_n : in std_logic := 'X'; -- write_n
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- chipselect : in std_logic := 'X'; -- chipselect
- readdata : out std_logic_vector(31 downto 0) -- readdata
+ -- clk
+ clk : in std_logic := 'X';
+ -- export
+ out_port : out std_logic;
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- address
+ address : in std_logic_vector(1 downto 0) := (others => 'X');
+ -- write_n
+ write_n : in std_logic := 'X';
+ -- writedata
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- chipselect
+ chipselect : in std_logic := 'X';
+ -- readdata
+ readdata : out std_logic_vector(31 downto 0)
);
end component qsys_unb2b_minimal_pio_wdi;
u0 : component qsys_unb2b_minimal_pio_wdi
port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- out_port => CONNECTED_TO_out_port, -- external_connection.export
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- write_n => CONNECTED_TO_write_n, -- .write_n
- writedata => CONNECTED_TO_writedata, -- .writedata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- readdata => CONNECTED_TO_readdata -- .readdata
+ -- clk.clk
+ clk => CONNECTED_TO_clk,
+ -- external_connection.export
+ out_port => CONNECTED_TO_out_port,
+ -- reset.reset_n
+ reset_n => CONNECTED_TO_reset_n,
+ -- s1.address
+ address => CONNECTED_TO_address,
+ -- .write_n
+ write_n => CONNECTED_TO_write_n,
+ -- .writedata
+ writedata => CONNECTED_TO_writedata,
+ -- .chipselect
+ chipselect => CONNECTED_TO_chipselect,
+ -- .readdata
+ readdata => CONNECTED_TO_readdata
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
index ec324643910e8ec28eea3841bf69396535f66ce8..29a64f659bdd5af5c4e45fae32a972fd3b9fd5dd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_dpmm_ctrl;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
index 902a48132b9b35e040acf2ea2bdc5803e567864e..3000423c22e59f95864c1c781ec2fa66e62fd0d8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_dpmm_data;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
index b7e771b662f1b2279fb0a2605ad86648a3821987..e49bc2a4531e7e370ff87a9e5112af9e53ee2ff9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_epcs;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
index 170f85ed587a093a331bd7da8153feb63a78358e..3c1f1809bbdaa6e3afa7af959fb69426373759fb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_fpga_temp_sens;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
index 495dae0b21c808c2f09bc98a269f98a22332116b..81c18715bcc965231b82d775a1a2423a5afb8a96 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_fpga_voltage_sens;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
index e099a81cd1f19acfb178d8108c3a40c275935b38..b9ec3f8e7c9d49e1c05a2d665f8ebcb0205c6a79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_mmdp_ctrl;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
index d25eb92a9c789a0a393083008b9dd982889f184e..c8f66632ab44c2323d7c0468e41059aa650a33dc 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_mmdp_data;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
index 837cb45819d6d993ab0e2ec2cd835b1f69bd1365..63dd733e011f3fe35b43b76fc78de59ae9954141 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_remu;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
index b97ef222ecfeac9b9cdc0609f289add83696334d..9878fc8fdf4c00e8aa50404866ef33fb77037e80 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_unb_pmbus;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
index 1871be2f741a5f58a41c9f333411b3b210fec9e6..444d691a7c1fb9cb1365e67588d5b0bc603c05c4 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_unb_sens;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
index 229a2d315e14744572cd30efdc1e44a03cb55744..13883c7092de7b4039e337b9f927be8f063d9c44 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_reg_wdi;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
index ae35f2bd1988023e11957c39257a521354f840f8..f4259cc612790dbe727994802a97a8c23dfdd834 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
@@ -4,20 +4,34 @@
g_dat_w : natural := 32
);
port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ -- export
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0);
+ -- export
+ coe_clk_export : out std_logic;
+ -- address
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X');
+ -- write
+ avs_mem_write : in std_logic := 'X';
+ -- writedata
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- read
+ avs_mem_read : in std_logic := 'X';
+ -- readdata
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- export
+ coe_read_export : out std_logic;
+ -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
+ -- export
+ coe_reset_export : out std_logic;
+ -- clk
+ csi_system_clk : in std_logic := 'X';
+ -- reset
+ csi_system_reset : in std_logic := 'X';
+ -- export
+ coe_write_export : out std_logic;
+ -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component qsys_unb2b_minimal_rom_system_info;
@@ -27,18 +41,32 @@
g_dat_w => NATURAL_VALUE_FOR_g_dat_w
)
port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ -- address.export
+ coe_address_export => CONNECTED_TO_coe_address_export,
+ -- clk.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export,
+ -- mem.address
+ avs_mem_address => CONNECTED_TO_avs_mem_address,
+ -- .write
+ avs_mem_write => CONNECTED_TO_avs_mem_write,
+ -- .writedata
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata,
+ -- .read
+ avs_mem_read => CONNECTED_TO_avs_mem_read,
+ -- .readdata
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata,
+ -- read.export
+ coe_read_export => CONNECTED_TO_coe_read_export,
+ -- readdata.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export,
+ -- reset.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export,
+ -- system.clk
+ csi_system_clk => CONNECTED_TO_csi_system_clk,
+ -- system_reset.reset
+ csi_system_reset => CONNECTED_TO_csi_system_reset,
+ -- write.export
+ coe_write_export => CONNECTED_TO_coe_write_export,
+ -- writedata.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
index ff04a90d2be254067a63715a1ab244263a405a8f..2f8c520e1f781d748592eb9785ceb3f7dae1c9e9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
@@ -1,24 +1,40 @@
component qsys_unb2b_minimal_timer_0 is
port (
- clk : in std_logic := 'X'; -- clk
- irq : out std_logic; -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
- writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
- readdata : out std_logic_vector(15 downto 0); -- readdata
- chipselect : in std_logic := 'X'; -- chipselect
- write_n : in std_logic := 'X' -- write_n
+ -- clk
+ clk : in std_logic := 'X';
+ -- irq
+ irq : out std_logic;
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- address
+ address : in std_logic_vector(2 downto 0) := (others => 'X');
+ -- writedata
+ writedata : in std_logic_vector(15 downto 0) := (others => 'X');
+ -- readdata
+ readdata : out std_logic_vector(15 downto 0);
+ -- chipselect
+ chipselect : in std_logic := 'X';
+ -- write_n
+ write_n : in std_logic := 'X'
);
end component qsys_unb2b_minimal_timer_0;
u0 : component qsys_unb2b_minimal_timer_0
port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- writedata => CONNECTED_TO_writedata, -- .writedata
- readdata => CONNECTED_TO_readdata, -- .readdata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write_n => CONNECTED_TO_write_n -- .write_n
+ -- clk.clk
+ clk => CONNECTED_TO_clk,
+ -- irq.irq
+ irq => CONNECTED_TO_irq,
+ -- reset.reset_n
+ reset_n => CONNECTED_TO_reset_n,
+ -- s1.address
+ address => CONNECTED_TO_address,
+ -- .writedata
+ writedata => CONNECTED_TO_writedata,
+ -- .readdata
+ readdata => CONNECTED_TO_readdata,
+ -- .chipselect
+ chipselect => CONNECTED_TO_chipselect,
+ -- .write_n
+ write_n => CONNECTED_TO_write_n
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
index 514ae4a7481860c8aec306184d0d937322216be4..dc0c355e2a262588038b4b5f05f031d2a05c189f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
@@ -35,21 +35,29 @@ entity unb2b_jesd_node3 is
g_design_name : string := "unb2b_jesd_node3";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e1sg;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0; -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0;
g_protect_addr_range: boolean := false
);
port (
-- GENERAL
-- CLK : IN STD_LOGIC; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
index 91849daf0fb485fa8e569cd2d38af59bb2829758..eb3fa850e14c26b3fdecdf28480de38273135cb5 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
@@ -32,7 +32,8 @@ use work.qsys_unb2b_jesd_pkg.all;
entity mmm_unb2b_jesd is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
index fd4dfd48d297596d0790d66898ca7b23f920e06f..92bd0f5daad8c1aaebae44c6b1b9a22469cb3154 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
@@ -29,188 +29,370 @@ package qsys_unb2b_jesd_pkg is
component qsys_unb2b_jesd is
port (
- altjesd_reset_seq_irq_irq : out std_logic; -- irq
- altjesd_reset_seq_pll_locked_in_reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
- altjesd_reset_seq_pll_reset_reset : out std_logic; -- reset
- altjesd_reset_seq_reset_in0_reset : in std_logic := 'X'; -- reset
- altjesd_reset_seq_rx_xcvr_ready_in_reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
- altjesd_reset_seq_tx_xcvr_ready_in_reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
- altjesd_rx_csr_cf_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_cs_export : out std_logic_vector(1 downto 0); -- export
- altjesd_rx_csr_f_export : out std_logic_vector(7 downto 0); -- export
- altjesd_rx_csr_hd_export : out std_logic; -- export
- altjesd_rx_csr_k_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_l_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_lane_powerdown_export : out std_logic_vector(0 downto 0); -- export
- altjesd_rx_csr_m_export : out std_logic_vector(7 downto 0); -- export
- altjesd_rx_csr_n_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_np_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_rx_testmode_export : out std_logic_vector(3 downto 0); -- export
- altjesd_rx_csr_s_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_dev_sync_n_export : out std_logic; -- export
- altjesd_rx_jesd204_rx_dlb_data_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_data_valid_export : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_disperr_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_errdetect_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_kchar_data_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_frame_error_export : in std_logic := 'X'; -- export
- altjesd_rx_jesd204_rx_int_irq : out std_logic; -- irq
- altjesd_rx_jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- altjesd_rx_jesd204_rx_link_valid : out std_logic; -- valid
- altjesd_rx_jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- altjesd_rx_rx_serial_data_rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- altjesd_rx_rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- altjesd_rx_rxphy_clk_export : out std_logic_vector(0 downto 0); -- export
- altjesd_rx_sof_export : out std_logic_vector(3 downto 0); -- export
- altjesd_rx_somf_export : out std_logic_vector(3 downto 0); -- export
- altjesd_rx_sysref_export : in std_logic := 'X'; -- export
- altjesd_ss_rx_corepll_locked_export : out std_logic; -- export
- altjesd_ss_rx_xcvr_reset_control_pll_powerdown_pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- altjesd_ss_rx_xcvr_reset_control_rx_ready_rx_ready : out std_logic_vector(0 downto 0); -- rx_ready
- altjesd_ss_rx_frame_reset_out_reset_reset_n : out std_logic; -- reset_n
- altjesd_ss_rx_link_reset_out_reset_reset_n : out std_logic; -- reset_n
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- device_clk_clk : in std_logic := 'X'; -- clk
- device_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
- frame_clk_clk : in std_logic := 'X'; -- clk
- frame_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
- link_clk_clk : in std_logic := 'X'; -- clk
- link_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- pll_out_frame_clk_clk : out std_logic; -- clk
- pll_out_link_clk_clk : out std_logic; -- clk
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(5 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0) -- export
+ -- irq
+ altjesd_reset_seq_irq_irq : out std_logic;
+ -- reset1_dsrt_qual
+ altjesd_reset_seq_pll_locked_in_reset1_dsrt_qual : in std_logic := 'X';
+ -- reset
+ altjesd_reset_seq_pll_reset_reset : out std_logic;
+ -- reset
+ altjesd_reset_seq_reset_in0_reset : in std_logic := 'X';
+ -- reset5_dsrt_qual
+ altjesd_reset_seq_rx_xcvr_ready_in_reset5_dsrt_qual : in std_logic := 'X';
+ -- reset2_dsrt_qual
+ altjesd_reset_seq_tx_xcvr_ready_in_reset2_dsrt_qual : in std_logic := 'X';
+ -- export
+ altjesd_rx_csr_cf_export : out std_logic_vector(4 downto 0);
+ -- export
+ altjesd_rx_csr_cs_export : out std_logic_vector(1 downto 0);
+ -- export
+ altjesd_rx_csr_f_export : out std_logic_vector(7 downto 0);
+ -- export
+ altjesd_rx_csr_hd_export : out std_logic;
+ -- export
+ altjesd_rx_csr_k_export : out std_logic_vector(4 downto 0);
+ -- export
+ altjesd_rx_csr_l_export : out std_logic_vector(4 downto 0);
+ -- export
+ altjesd_rx_csr_lane_powerdown_export : out std_logic_vector(0 downto 0);
+ -- export
+ altjesd_rx_csr_m_export : out std_logic_vector(7 downto 0);
+ -- export
+ altjesd_rx_csr_n_export : out std_logic_vector(4 downto 0);
+ -- export
+ altjesd_rx_csr_np_export : out std_logic_vector(4 downto 0);
+ -- export
+ altjesd_rx_csr_rx_testmode_export : out std_logic_vector(3 downto 0);
+ -- export
+ altjesd_rx_csr_s_export : out std_logic_vector(4 downto 0);
+ -- export
+ altjesd_rx_dev_sync_n_export : out std_logic;
+ -- export
+ altjesd_rx_jesd204_rx_dlb_data_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ altjesd_rx_jesd204_rx_dlb_data_valid_export : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- export
+ altjesd_rx_jesd204_rx_dlb_disperr_export : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ altjesd_rx_jesd204_rx_dlb_errdetect_export : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ altjesd_rx_jesd204_rx_dlb_kchar_data_export : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ altjesd_rx_jesd204_rx_frame_error_export : in std_logic := 'X';
+ -- irq
+ altjesd_rx_jesd204_rx_int_irq : out std_logic;
+ -- data
+ altjesd_rx_jesd204_rx_link_data : out std_logic_vector(31 downto 0);
+ -- valid
+ altjesd_rx_jesd204_rx_link_valid : out std_logic;
+ -- ready
+ altjesd_rx_jesd204_rx_link_ready : in std_logic := 'X';
+ -- rx_serial_data
+ altjesd_rx_rx_serial_data_rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- reset_n
+ altjesd_rx_rxlink_rst_n_reset_n : in std_logic := 'X';
+ -- export
+ altjesd_rx_rxphy_clk_export : out std_logic_vector(0 downto 0);
+ -- export
+ altjesd_rx_sof_export : out std_logic_vector(3 downto 0);
+ -- export
+ altjesd_rx_somf_export : out std_logic_vector(3 downto 0);
+ -- export
+ altjesd_rx_sysref_export : in std_logic := 'X';
+ -- export
+ altjesd_ss_rx_corepll_locked_export : out std_logic;
+ -- pll_powerdown
+ altjesd_ss_rx_xcvr_reset_control_pll_powerdown_pll_powerdown : out std_logic_vector(0 downto 0);
+ -- rx_ready
+ altjesd_ss_rx_xcvr_reset_control_rx_ready_rx_ready : out std_logic_vector(0 downto 0);
+ -- reset_n
+ altjesd_ss_rx_frame_reset_out_reset_reset_n : out std_logic;
+ -- reset_n
+ altjesd_ss_rx_link_reset_out_reset_reset_n : out std_logic;
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- clk
+ device_clk_clk : in std_logic := 'X';
+ -- reset_n
+ device_clk_reset_reset_n : in std_logic := 'X';
+ -- clk
+ frame_clk_clk : in std_logic := 'X';
+ -- reset_n
+ frame_clk_reset_reset_n : in std_logic := 'X';
+ -- clk
+ link_clk_clk : in std_logic := 'X';
+ -- reset_n
+ link_clk_reset_reset_n : in std_logic := 'X';
+ -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- clk
+ pll_out_frame_clk_clk : out std_logic;
+ -- clk
+ pll_out_link_clk_clk : out std_logic;
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic;
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(16 downto 0);
+ -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic;
+ -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic;
+ -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0)
);
end component qsys_unb2b_jesd;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
index 91de0e9f2772a37c0081c401f556e230fda90183..63ab4bfbd973e53f11fa235493eb6d04bf39136e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
@@ -35,22 +35,30 @@ entity unb2b_jesd is
g_design_name : string := "unb2b_jesd";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e1sg;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0; -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0;
g_factory_image : boolean := false;
g_protect_addr_range: boolean := false
);
port (
-- GENERAL
-- CLK : IN STD_LOGIC; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -134,12 +142,16 @@ architecture str of unb2b_jesd is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -407,8 +419,10 @@ begin
g_technology => g_technology,
g_nof_streams => 1,
g_data_w => 32,
- g_buf_nof_data => 16384, -- 8192,
- g_buf_use_sync => true, -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ -- 8192,
+ g_buf_nof_data => 16384,
+ -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ g_buf_use_sync => true,
g_use_rx_seq => false
)
port map (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
index ec0e76432a205b9af472413490552af89cc5ef35..9cb7c0e444fdb2de473b22d41f8aabafaff1925e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
@@ -54,23 +54,28 @@ use i2c_lib.i2c_commander_unb2b_pmbus_pkg.all;
entity tb_unb2b_minimal is
generic (
g_design_name : string := "unb2b_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Node 3
+ g_sim_node_nr : natural := 3
);
end tb_unb2b_minimal;
architecture tb of tb_unb2b_minimal is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb2b_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2b_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -101,33 +106,48 @@ architecture tb of tb_unb2b_minimal is
signal qsfp_led : std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
constant c_pmbus_tcvr0_address : std_logic_vector(6 downto 0) := TO_UVEC(I2C_unb2b_PMB_TCVR0_BMR461_ADR, 7);
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
-
- PMBUS_SC <= 'H'; -- pull up
- PMBUS_SD <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+
+ -- pull up
+ PMBUS_SC <= 'H';
+ -- pull up
+ PMBUS_SD <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
index a915740dc56c968cea7358d18a0c7d354f1f3e2a..0d18a1a94311acf9f583b146655395049d619787 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
@@ -32,22 +32,31 @@ entity unb2b_minimal_125m is
g_design_name : string := "unb2b_minimal_125m";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e1sg;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision id -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision id -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := true;
g_protect_addr_range: boolean := false
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
index 94c4b4e44734dbcd37a02a86632e8a6eeedde24e..3d836c792430b9265f131d5b05d7b964b8f07a57 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
@@ -32,7 +32,8 @@ use work.qsys_unb2b_minimal_pkg.all;
entity mmm_unb2b_minimal is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
index 1470cca51163e20c03fea684792e0fc3269da00f..1d286837c28645dbb61fe180b02c3ed8a24d13ea 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
@@ -29,133 +29,260 @@ package qsys_unb2b_minimal_pkg is
component qsys_unb2b_minimal is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0);
+ -- export
+ ram_scrap_clk_export : out std_logic;
+ -- export
+ ram_scrap_read_export : out std_logic;
+ -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_scrap_reset_export : out std_logic;
+ -- export
+ ram_scrap_write_export : out std_logic;
+ -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_sens_clk_export : out std_logic;
+ -- export
+ reg_unb_sens_read_export : out std_logic;
+ -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_sens_write_export : out std_logic;
+ -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- export
+ reg_unb_pmbus_reset_export : out std_logic
);
end component qsys_unb2b_minimal;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
index af68ce0e0a9d34558339dd888f16ea75c5e61838..bb5cc7cc8e9faff30e7f332d6d380198e26f8a0a 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
@@ -33,22 +33,31 @@ entity unb2b_minimal is
g_design_name : string := "unb2b_minimal";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e1sg;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision id -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision id -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := true;
g_protect_addr_range: boolean := false
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -123,12 +132,16 @@ architecture str of unb2b_minimal is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -367,7 +380,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
diff --git a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
index 08f2d036be105e43527af6fdc08992fc0229a514..e30d113c9ea6d4d1630c2c17839455cd93ba417f 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
@@ -54,23 +54,28 @@ use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
entity tb_unb2b_minimal is
generic (
g_design_name : string := "unb2b_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Node 3
+ g_sim_node_nr : natural := 3
);
end tb_unb2b_minimal;
architecture tb of tb_unb2b_minimal is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb2b_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2b_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -101,33 +106,48 @@ architecture tb of tb_unb2b_minimal is
signal qsfp_led : std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
constant c_pmbus_tcvr0_address : std_logic_vector(6 downto 0) := TO_UVEC(I2C_UNB2_PMB_TCVR0_BMR461_ADR, 7);
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
-
- PMBUS_SC <= 'H'; -- pull up
- PMBUS_SD <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
+
+ -- pull up
+ PMBUS_SC <= 'H';
+ -- pull up
+ PMBUS_SD <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
index b8d21e890e0a16f9cabfc918278fcac6875bfa86..61602fd2d55f72e22b15006362afb4cb06655fdd 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
@@ -31,20 +31,29 @@ entity unb2b_test_10GbE is
generic (
g_design_name : string := "unb2b_test_10GbE";
g_design_note : string := "10GbE: all QSFPs";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -61,9 +70,12 @@ entity unb2b_test_10GbE is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic; -- Clock 10GbE front (qsfp) and ring lines
- SB_CLK : in std_logic; -- Clock 10GbE back upper 24 lines
- BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic;
+ -- Clock 10GbE back upper 24 lines
+ SB_CLK : in std_logic;
+ -- Clock 10GbE back lower 24 lines
+ BCK_REF_CLK : in std_logic;
-- back transceivers
-- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
index 150e0d63045d3adf645914ff4000210671f53740..6cf4f1fa6ed3963080e0df1e82aa326ac2d4dc18 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
@@ -32,20 +32,29 @@ entity unb2b_test_ddr_MB_I_II is
generic (
g_design_name : string := "unb2b_test_ddr_MB_I_II";
g_design_note : string := "Test design with ddr4";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -66,8 +75,10 @@ entity unb2b_test_ddr_MB_I_II is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
- MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic;
+ -- Reference clock for MB_II
+ MB_II_REF_CLK : in std_logic;
-- SO-DIMM Memory Bank I
MB_I_IN : in t_tech_ddr4_phy_in;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index ab0300e724b7bb8f55b4b891a838ca736862dc05..7a513db698909c3e15ea3ee7a1cffebe03235ec6 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -42,7 +42,8 @@ use work.unb2b_test_pkg.all;
entity mmm_unb2b_test is
generic (
- g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
+ -- FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_technology : natural := c_tech_arria10_e1sg;
@@ -407,7 +408,8 @@ begin
proc_tech_tse_setup(g_technology, false, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth0_tse_miso, eth1g_eth0_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth0_reg_miso, sim_eth1g_eth0_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth0_reg_miso, sim_eth1g_eth0_reg_mosi);
sim_eth_mm_bus_switch <= '0';
wait;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
index 02021567e290a50a5b46eff215147816e76578ef..3a8db690235998babe682e9a49d5259b37b1c68a 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
@@ -30,358 +30,710 @@ package qsys_unb2b_test_pkg is
component qsys_unb2b_test is
port (
- avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
- avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
- avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
- avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
- avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
- avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
- avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
- avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
- avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
- avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
- avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
- avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
- avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
- avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
- avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
- avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
- avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
- avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
- avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
- avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
- clk_clk : in std_logic := '0'; -- clk.clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
- pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
- pio_pps_read_export : out std_logic; -- pio_pps_read.export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
- pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
- pio_pps_write_export : out std_logic; -- pio_pps_write.export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
- pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
- pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
- pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
- pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
- pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
- ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
- ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
- ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
- ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
- reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
- reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
- reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
- reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- reg_diag_data_buffer_10gbe_address.export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
- reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
- reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
- reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
- reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
- reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
- reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
- reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
- reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
- reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
- reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
- reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
- reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back0_address.export
- reg_eth10g_back0_clk_export : out std_logic; -- reg_eth10g_back0_clk.export
- reg_eth10g_back0_read_export : out std_logic; -- reg_eth10g_back0_read.export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back0_readdata.export
- reg_eth10g_back0_reset_export : out std_logic; -- reg_eth10g_back0_reset.export
- reg_eth10g_back0_write_export : out std_logic; -- reg_eth10g_back0_write.export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back0_writedata.export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back1_address.export
- reg_eth10g_back1_clk_export : out std_logic; -- reg_eth10g_back1_clk.export
- reg_eth10g_back1_read_export : out std_logic; -- reg_eth10g_back1_read.export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back1_readdata.export
- reg_eth10g_back1_reset_export : out std_logic; -- reg_eth10g_back1_reset.export
- reg_eth10g_back1_write_export : out std_logic; -- reg_eth10g_back1_write.export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back1_writedata.export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- reg_eth10g_qsfp_ring_address.export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- reg_eth10g_qsfp_ring_clk.export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- reg_eth10g_qsfp_ring_read.export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_qsfp_ring_readdata.export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- reg_eth10g_qsfp_ring_reset.export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- reg_eth10g_qsfp_ring_write.export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_qsfp_ring_writedata.export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- reg_fpga_temp_sens_address.export
- reg_fpga_temp_sens_clk_export : out std_logic; -- reg_fpga_temp_sens_clk.export
- reg_fpga_temp_sens_read_export : out std_logic; -- reg_fpga_temp_sens_read.export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_temp_sens_readdata.export
- reg_fpga_temp_sens_reset_export : out std_logic; -- reg_fpga_temp_sens_reset.export
- reg_fpga_temp_sens_write_export : out std_logic; -- reg_fpga_temp_sens_write.export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_temp_sens_writedata.export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- reg_fpga_voltage_sens_address.export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- reg_fpga_voltage_sens_clk.export
- reg_fpga_voltage_sens_read_export : out std_logic; -- reg_fpga_voltage_sens_read.export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_voltage_sens_readdata.export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- reg_fpga_voltage_sens_reset.export
- reg_fpga_voltage_sens_write_export : out std_logic; -- reg_fpga_voltage_sens_write.export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_voltage_sens_writedata.export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
- reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
- reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
- reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
- reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
- reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
- reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
- reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
- reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
- reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
- reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
- reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
- reg_remu_read_export : out std_logic; -- reg_remu_read.export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
- reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
- reg_remu_write_export : out std_logic; -- reg_remu_write.export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
- reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
- reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
- reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
- reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- reg_unb_pmbus_address.export
- reg_unb_pmbus_clk_export : out std_logic; -- reg_unb_pmbus_clk.export
- reg_unb_pmbus_read_export : out std_logic; -- reg_unb_pmbus_read.export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_pmbus_readdata.export
- reg_unb_pmbus_reset_export : out std_logic; -- reg_unb_pmbus_reset.export
- reg_unb_pmbus_write_export : out std_logic; -- reg_unb_pmbus_write.export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_pmbus_writedata.export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- reg_unb_sens_address.export
- reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
- reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
- reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
- reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
- reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
- reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
- reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
- reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
- reset_reset_n : in std_logic := '0'; -- reset.reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
- rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
- rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
- rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
- rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
+ -- avs_eth_0_clk.export
+ avs_eth_0_clk_export : out std_logic;
+ -- avs_eth_0_irq.export
+ avs_eth_0_irq_export : in std_logic := '0';
+ -- avs_eth_0_ram_address.export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- avs_eth_0_ram_read.export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- avs_eth_0_ram_readdata.export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- avs_eth_0_ram_write.export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- avs_eth_0_ram_writedata.export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- avs_eth_0_reg_address.export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- avs_eth_0_reg_read.export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- avs_eth_0_reg_readdata.export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- avs_eth_0_reg_write.export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- avs_eth_0_reg_writedata.export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- avs_eth_0_reset.export
+ avs_eth_0_reset_export : out std_logic;
+ -- avs_eth_0_tse_address.export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- avs_eth_0_tse_read.export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- avs_eth_0_tse_readdata.export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- avs_eth_0_tse_waitrequest.export
+ avs_eth_0_tse_waitrequest_export : in std_logic := '0';
+ -- avs_eth_0_tse_write.export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- avs_eth_0_tse_writedata.export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- avs_eth_1_clk.export
+ avs_eth_1_clk_export : out std_logic;
+ -- avs_eth_1_irq.export
+ avs_eth_1_irq_export : in std_logic := '0';
+ -- avs_eth_1_ram_address.export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0);
+ -- avs_eth_1_ram_read.export
+ avs_eth_1_ram_read_export : out std_logic;
+ -- avs_eth_1_ram_readdata.export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- avs_eth_1_ram_write.export
+ avs_eth_1_ram_write_export : out std_logic;
+ -- avs_eth_1_ram_writedata.export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- avs_eth_1_reg_address.export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0);
+ -- avs_eth_1_reg_read.export
+ avs_eth_1_reg_read_export : out std_logic;
+ -- avs_eth_1_reg_readdata.export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- avs_eth_1_reg_write.export
+ avs_eth_1_reg_write_export : out std_logic;
+ -- avs_eth_1_reg_writedata.export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- avs_eth_1_reset.export
+ avs_eth_1_reset_export : out std_logic;
+ -- avs_eth_1_tse_address.export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0);
+ -- avs_eth_1_tse_read.export
+ avs_eth_1_tse_read_export : out std_logic;
+ -- avs_eth_1_tse_readdata.export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- avs_eth_1_tse_waitrequest.export
+ avs_eth_1_tse_waitrequest_export : in std_logic := '0';
+ -- avs_eth_1_tse_write.export
+ avs_eth_1_tse_write_export : out std_logic;
+ -- avs_eth_1_tse_writedata.export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- clk.clk
+ clk_clk : in std_logic := '0';
+ -- pio_pps_address.export
+ pio_pps_address_export : out std_logic_vector(0 downto 0);
+ -- pio_pps_clk.export
+ pio_pps_clk_export : out std_logic;
+ -- pio_pps_read.export
+ pio_pps_read_export : out std_logic;
+ -- pio_pps_readdata.export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- pio_pps_reset.export
+ pio_pps_reset_export : out std_logic;
+ -- pio_pps_write.export
+ pio_pps_write_export : out std_logic;
+ -- pio_pps_writedata.export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- pio_system_info_address.export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- pio_system_info_clk.export
+ pio_system_info_clk_export : out std_logic;
+ -- pio_system_info_read.export
+ pio_system_info_read_export : out std_logic;
+ -- pio_system_info_readdata.export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- pio_system_info_reset.export
+ pio_system_info_reset_export : out std_logic;
+ -- pio_system_info_write.export
+ pio_system_info_write_export : out std_logic;
+ -- pio_system_info_writedata.export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- pio_wdi_external_connection.export
+ pio_wdi_external_connection_export : out std_logic;
+ -- ram_diag_bg_10gbe_address.export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0);
+ -- ram_diag_bg_10gbe_clk.export
+ ram_diag_bg_10gbe_clk_export : out std_logic;
+ -- ram_diag_bg_10gbe_read.export
+ ram_diag_bg_10gbe_read_export : out std_logic;
+ -- ram_diag_bg_10gbe_readdata.export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- ram_diag_bg_10gbe_reset.export
+ ram_diag_bg_10gbe_reset_export : out std_logic;
+ -- ram_diag_bg_10gbe_write.export
+ ram_diag_bg_10gbe_write_export : out std_logic;
+ -- ram_diag_bg_10gbe_writedata.export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- ram_diag_bg_1gbe_address.export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0);
+ -- ram_diag_bg_1gbe_clk.export
+ ram_diag_bg_1gbe_clk_export : out std_logic;
+ -- ram_diag_bg_1gbe_read.export
+ ram_diag_bg_1gbe_read_export : out std_logic;
+ -- ram_diag_bg_1gbe_readdata.export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- ram_diag_bg_1gbe_reset.export
+ ram_diag_bg_1gbe_reset_export : out std_logic;
+ -- ram_diag_bg_1gbe_write.export
+ ram_diag_bg_1gbe_write_export : out std_logic;
+ -- ram_diag_bg_1gbe_writedata.export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- ram_diag_data_buffer_10gbe_address.export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0);
+ -- ram_diag_data_buffer_10gbe_clk.export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic;
+ -- ram_diag_data_buffer_10gbe_read.export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic;
+ -- ram_diag_data_buffer_10gbe_readdata.export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- ram_diag_data_buffer_10gbe_reset.export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic;
+ -- ram_diag_data_buffer_10gbe_write.export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic;
+ -- ram_diag_data_buffer_10gbe_writedata.export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- ram_diag_data_buffer_1gbe_address.export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0);
+ -- ram_diag_data_buffer_1gbe_clk.export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic;
+ -- ram_diag_data_buffer_1gbe_read.export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic;
+ -- ram_diag_data_buffer_1gbe_readdata.export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- ram_diag_data_buffer_1gbe_reset.export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic;
+ -- ram_diag_data_buffer_1gbe_write.export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic;
+ -- ram_diag_data_buffer_1gbe_writedata.export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- ram_diag_data_buffer_ddr_mb_i_address.export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0);
+ -- ram_diag_data_buffer_ddr_mb_i_clk.export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_i_read.export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_i_readdata.export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- ram_diag_data_buffer_ddr_mb_i_reset.export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_i_write.export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_i_writedata.export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- ram_diag_data_buffer_ddr_mb_ii_address.export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0);
+ -- ram_diag_data_buffer_ddr_mb_ii_clk.export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_ii_read.export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- ram_diag_data_buffer_ddr_mb_ii_reset.export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_ii_write.export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic;
+ -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_bsn_monitor_10gbe_address.export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0);
+ -- reg_bsn_monitor_10gbe_clk.export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic;
+ -- reg_bsn_monitor_10gbe_read.export
+ reg_bsn_monitor_10gbe_read_export : out std_logic;
+ -- reg_bsn_monitor_10gbe_readdata.export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_bsn_monitor_10gbe_reset.export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic;
+ -- reg_bsn_monitor_10gbe_write.export
+ reg_bsn_monitor_10gbe_write_export : out std_logic;
+ -- reg_bsn_monitor_10gbe_writedata.export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_bsn_monitor_1gbe_address.export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0);
+ -- reg_bsn_monitor_1gbe_clk.export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic;
+ -- reg_bsn_monitor_1gbe_read.export
+ reg_bsn_monitor_1gbe_read_export : out std_logic;
+ -- reg_bsn_monitor_1gbe_readdata.export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_bsn_monitor_1gbe_reset.export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic;
+ -- reg_bsn_monitor_1gbe_write.export
+ reg_bsn_monitor_1gbe_write_export : out std_logic;
+ -- reg_bsn_monitor_1gbe_writedata.export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_bg_10gbe_address.export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0);
+ -- reg_diag_bg_10gbe_clk.export
+ reg_diag_bg_10gbe_clk_export : out std_logic;
+ -- reg_diag_bg_10gbe_read.export
+ reg_diag_bg_10gbe_read_export : out std_logic;
+ -- reg_diag_bg_10gbe_readdata.export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_bg_10gbe_reset.export
+ reg_diag_bg_10gbe_reset_export : out std_logic;
+ -- reg_diag_bg_10gbe_write.export
+ reg_diag_bg_10gbe_write_export : out std_logic;
+ -- reg_diag_bg_10gbe_writedata.export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_bg_1gbe_address.export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0);
+ -- reg_diag_bg_1gbe_clk.export
+ reg_diag_bg_1gbe_clk_export : out std_logic;
+ -- reg_diag_bg_1gbe_read.export
+ reg_diag_bg_1gbe_read_export : out std_logic;
+ -- reg_diag_bg_1gbe_readdata.export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_bg_1gbe_reset.export
+ reg_diag_bg_1gbe_reset_export : out std_logic;
+ -- reg_diag_bg_1gbe_write.export
+ reg_diag_bg_1gbe_write_export : out std_logic;
+ -- reg_diag_bg_1gbe_writedata.export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_data_buffer_10gbe_address.export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0);
+ -- reg_diag_data_buffer_10gbe_clk.export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic;
+ -- reg_diag_data_buffer_10gbe_read.export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic;
+ -- reg_diag_data_buffer_10gbe_readdata.export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_data_buffer_10gbe_reset.export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic;
+ -- reg_diag_data_buffer_10gbe_write.export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic;
+ -- reg_diag_data_buffer_10gbe_writedata.export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_data_buffer_1gbe_address.export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0);
+ -- reg_diag_data_buffer_1gbe_clk.export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic;
+ -- reg_diag_data_buffer_1gbe_read.export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic;
+ -- reg_diag_data_buffer_1gbe_readdata.export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_data_buffer_1gbe_reset.export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic;
+ -- reg_diag_data_buffer_1gbe_write.export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic;
+ -- reg_diag_data_buffer_1gbe_writedata.export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_data_buffer_ddr_mb_i_address.export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0);
+ -- reg_diag_data_buffer_ddr_mb_i_clk.export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_i_read.export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_i_readdata.export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_data_buffer_ddr_mb_i_reset.export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_i_write.export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_i_writedata.export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_data_buffer_ddr_mb_ii_address.export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0);
+ -- reg_diag_data_buffer_ddr_mb_ii_clk.export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_ii_read.export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_data_buffer_ddr_mb_ii_reset.export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_ii_write.export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic;
+ -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_rx_seq_10gbe_address.export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0);
+ -- reg_diag_rx_seq_10gbe_clk.export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic;
+ -- reg_diag_rx_seq_10gbe_read.export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic;
+ -- reg_diag_rx_seq_10gbe_readdata.export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_rx_seq_10gbe_reset.export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic;
+ -- reg_diag_rx_seq_10gbe_write.export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic;
+ -- reg_diag_rx_seq_10gbe_writedata.export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_rx_seq_1gbe_address.export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0);
+ -- reg_diag_rx_seq_1gbe_clk.export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic;
+ -- reg_diag_rx_seq_1gbe_read.export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic;
+ -- reg_diag_rx_seq_1gbe_readdata.export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_rx_seq_1gbe_reset.export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic;
+ -- reg_diag_rx_seq_1gbe_write.export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic;
+ -- reg_diag_rx_seq_1gbe_writedata.export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_rx_seq_ddr_mb_i_address.export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0);
+ -- reg_diag_rx_seq_ddr_mb_i_clk.export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_i_read.export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_i_readdata.export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_rx_seq_ddr_mb_i_reset.export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_i_write.export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_i_writedata.export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_rx_seq_ddr_mb_ii_address.export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0);
+ -- reg_diag_rx_seq_ddr_mb_ii_clk.export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_ii_read.export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_rx_seq_ddr_mb_ii_reset.export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_ii_write.export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic;
+ -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_tx_seq_10gbe_address.export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0);
+ -- reg_diag_tx_seq_10gbe_clk.export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic;
+ -- reg_diag_tx_seq_10gbe_read.export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic;
+ -- reg_diag_tx_seq_10gbe_readdata.export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_tx_seq_10gbe_reset.export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic;
+ -- reg_diag_tx_seq_10gbe_write.export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic;
+ -- reg_diag_tx_seq_10gbe_writedata.export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_tx_seq_1gbe_address.export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0);
+ -- reg_diag_tx_seq_1gbe_clk.export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic;
+ -- reg_diag_tx_seq_1gbe_read.export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic;
+ -- reg_diag_tx_seq_1gbe_readdata.export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_tx_seq_1gbe_reset.export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic;
+ -- reg_diag_tx_seq_1gbe_write.export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic;
+ -- reg_diag_tx_seq_1gbe_writedata.export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_tx_seq_ddr_mb_i_address.export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0);
+ -- reg_diag_tx_seq_ddr_mb_i_clk.export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_i_read.export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_i_readdata.export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_tx_seq_ddr_mb_i_reset.export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_i_write.export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_i_writedata.export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_diag_tx_seq_ddr_mb_ii_address.export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0);
+ -- reg_diag_tx_seq_ddr_mb_ii_clk.export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_ii_read.export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_diag_tx_seq_ddr_mb_ii_reset.export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_ii_write.export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic;
+ -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_dpmm_ctrl_address.export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- reg_dpmm_ctrl_clk.export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- reg_dpmm_ctrl_read.export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- reg_dpmm_ctrl_readdata.export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_dpmm_ctrl_reset.export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- reg_dpmm_ctrl_write.export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- reg_dpmm_ctrl_writedata.export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_dpmm_data_address.export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- reg_dpmm_data_clk.export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- reg_dpmm_data_read.export
+ reg_dpmm_data_read_export : out std_logic;
+ -- reg_dpmm_data_readdata.export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_dpmm_data_reset.export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- reg_dpmm_data_write.export
+ reg_dpmm_data_write_export : out std_logic;
+ -- reg_dpmm_data_writedata.export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_epcs_address.export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- reg_epcs_clk.export
+ reg_epcs_clk_export : out std_logic;
+ -- reg_epcs_read.export
+ reg_epcs_read_export : out std_logic;
+ -- reg_epcs_readdata.export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_epcs_reset.export
+ reg_epcs_reset_export : out std_logic;
+ -- reg_epcs_write.export
+ reg_epcs_write_export : out std_logic;
+ -- reg_epcs_writedata.export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_eth10g_back0_address.export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0);
+ -- reg_eth10g_back0_clk.export
+ reg_eth10g_back0_clk_export : out std_logic;
+ -- reg_eth10g_back0_read.export
+ reg_eth10g_back0_read_export : out std_logic;
+ -- reg_eth10g_back0_readdata.export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_eth10g_back0_reset.export
+ reg_eth10g_back0_reset_export : out std_logic;
+ -- reg_eth10g_back0_write.export
+ reg_eth10g_back0_write_export : out std_logic;
+ -- reg_eth10g_back0_writedata.export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_eth10g_back1_address.export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0);
+ -- reg_eth10g_back1_clk.export
+ reg_eth10g_back1_clk_export : out std_logic;
+ -- reg_eth10g_back1_read.export
+ reg_eth10g_back1_read_export : out std_logic;
+ -- reg_eth10g_back1_readdata.export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_eth10g_back1_reset.export
+ reg_eth10g_back1_reset_export : out std_logic;
+ -- reg_eth10g_back1_write.export
+ reg_eth10g_back1_write_export : out std_logic;
+ -- reg_eth10g_back1_writedata.export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_eth10g_qsfp_ring_address.export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0);
+ -- reg_eth10g_qsfp_ring_clk.export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic;
+ -- reg_eth10g_qsfp_ring_read.export
+ reg_eth10g_qsfp_ring_read_export : out std_logic;
+ -- reg_eth10g_qsfp_ring_readdata.export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_eth10g_qsfp_ring_reset.export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic;
+ -- reg_eth10g_qsfp_ring_write.export
+ reg_eth10g_qsfp_ring_write_export : out std_logic;
+ -- reg_eth10g_qsfp_ring_writedata.export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_fpga_temp_sens_address.export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- reg_fpga_temp_sens_clk.export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- reg_fpga_temp_sens_read.export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- reg_fpga_temp_sens_readdata.export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_fpga_temp_sens_reset.export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- reg_fpga_temp_sens_write.export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- reg_fpga_temp_sens_writedata.export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_fpga_voltage_sens_address.export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- reg_fpga_voltage_sens_clk.export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- reg_fpga_voltage_sens_read.export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- reg_fpga_voltage_sens_readdata.export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_fpga_voltage_sens_reset.export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- reg_fpga_voltage_sens_write.export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- reg_fpga_voltage_sens_writedata.export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_io_ddr_mb_i_address.export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0);
+ -- reg_io_ddr_mb_i_clk.export
+ reg_io_ddr_mb_i_clk_export : out std_logic;
+ -- reg_io_ddr_mb_i_read.export
+ reg_io_ddr_mb_i_read_export : out std_logic;
+ -- reg_io_ddr_mb_i_readdata.export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_io_ddr_mb_i_reset.export
+ reg_io_ddr_mb_i_reset_export : out std_logic;
+ -- reg_io_ddr_mb_i_write.export
+ reg_io_ddr_mb_i_write_export : out std_logic;
+ -- reg_io_ddr_mb_i_writedata.export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_io_ddr_mb_ii_address.export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0);
+ -- reg_io_ddr_mb_ii_clk.export
+ reg_io_ddr_mb_ii_clk_export : out std_logic;
+ -- reg_io_ddr_mb_ii_read.export
+ reg_io_ddr_mb_ii_read_export : out std_logic;
+ -- reg_io_ddr_mb_ii_readdata.export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_io_ddr_mb_ii_reset.export
+ reg_io_ddr_mb_ii_reset_export : out std_logic;
+ -- reg_io_ddr_mb_ii_write.export
+ reg_io_ddr_mb_ii_write_export : out std_logic;
+ -- reg_io_ddr_mb_ii_writedata.export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_mmdp_ctrl_address.export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- reg_mmdp_ctrl_clk.export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- reg_mmdp_ctrl_read.export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- reg_mmdp_ctrl_readdata.export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_mmdp_ctrl_reset.export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- reg_mmdp_ctrl_write.export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- reg_mmdp_ctrl_writedata.export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_mmdp_data_address.export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- reg_mmdp_data_clk.export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- reg_mmdp_data_read.export
+ reg_mmdp_data_read_export : out std_logic;
+ -- reg_mmdp_data_readdata.export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_mmdp_data_reset.export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- reg_mmdp_data_write.export
+ reg_mmdp_data_write_export : out std_logic;
+ -- reg_mmdp_data_writedata.export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_remu_address.export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- reg_remu_clk.export
+ reg_remu_clk_export : out std_logic;
+ -- reg_remu_read.export
+ reg_remu_read_export : out std_logic;
+ -- reg_remu_readdata.export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_remu_reset.export
+ reg_remu_reset_export : out std_logic;
+ -- reg_remu_write.export
+ reg_remu_write_export : out std_logic;
+ -- reg_remu_writedata.export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_tr_10gbe_back0_address.export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0);
+ -- reg_tr_10gbe_back0_clk.export
+ reg_tr_10gbe_back0_clk_export : out std_logic;
+ -- reg_tr_10gbe_back0_read.export
+ reg_tr_10gbe_back0_read_export : out std_logic;
+ -- reg_tr_10gbe_back0_readdata.export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_tr_10gbe_back0_reset.export
+ reg_tr_10gbe_back0_reset_export : out std_logic;
+ -- reg_tr_10gbe_back0_waitrequest.export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0';
+ -- reg_tr_10gbe_back0_write.export
+ reg_tr_10gbe_back0_write_export : out std_logic;
+ -- reg_tr_10gbe_back0_writedata.export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_tr_10gbe_back1_address.export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0);
+ -- reg_tr_10gbe_back1_clk.export
+ reg_tr_10gbe_back1_clk_export : out std_logic;
+ -- reg_tr_10gbe_back1_read.export
+ reg_tr_10gbe_back1_read_export : out std_logic;
+ -- reg_tr_10gbe_back1_readdata.export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_tr_10gbe_back1_reset.export
+ reg_tr_10gbe_back1_reset_export : out std_logic;
+ -- reg_tr_10gbe_back1_waitrequest.export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0';
+ -- reg_tr_10gbe_back1_write.export
+ reg_tr_10gbe_back1_write_export : out std_logic;
+ -- reg_tr_10gbe_back1_writedata.export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_tr_10gbe_qsfp_ring_address.export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0);
+ -- reg_tr_10gbe_qsfp_ring_clk.export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic;
+ -- reg_tr_10gbe_qsfp_ring_read.export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic;
+ -- reg_tr_10gbe_qsfp_ring_readdata.export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_tr_10gbe_qsfp_ring_reset.export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic;
+ -- reg_tr_10gbe_qsfp_ring_waitrequest.export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0';
+ -- reg_tr_10gbe_qsfp_ring_write.export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic;
+ -- reg_tr_10gbe_qsfp_ring_writedata.export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_unb_pmbus_address.export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0);
+ -- reg_unb_pmbus_clk.export
+ reg_unb_pmbus_clk_export : out std_logic;
+ -- reg_unb_pmbus_read.export
+ reg_unb_pmbus_read_export : out std_logic;
+ -- reg_unb_pmbus_readdata.export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_unb_pmbus_reset.export
+ reg_unb_pmbus_reset_export : out std_logic;
+ -- reg_unb_pmbus_write.export
+ reg_unb_pmbus_write_export : out std_logic;
+ -- reg_unb_pmbus_writedata.export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_unb_sens_address.export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0);
+ -- reg_unb_sens_clk.export
+ reg_unb_sens_clk_export : out std_logic;
+ -- reg_unb_sens_read.export
+ reg_unb_sens_read_export : out std_logic;
+ -- reg_unb_sens_readdata.export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_unb_sens_reset.export
+ reg_unb_sens_reset_export : out std_logic;
+ -- reg_unb_sens_write.export
+ reg_unb_sens_write_export : out std_logic;
+ -- reg_unb_sens_writedata.export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- reg_wdi_address.export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- reg_wdi_clk.export
+ reg_wdi_clk_export : out std_logic;
+ -- reg_wdi_read.export
+ reg_wdi_read_export : out std_logic;
+ -- reg_wdi_readdata.export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- reg_wdi_reset.export
+ reg_wdi_reset_export : out std_logic;
+ -- reg_wdi_write.export
+ reg_wdi_write_export : out std_logic;
+ -- reg_wdi_writedata.export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- reset.reset_n
+ reset_reset_n : in std_logic := '0';
+ -- rom_system_info_address.export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ -- rom_system_info_clk.export
+ rom_system_info_clk_export : out std_logic;
+ -- rom_system_info_read.export
+ rom_system_info_read_export : out std_logic;
+ -- rom_system_info_readdata.export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ -- rom_system_info_reset.export
+ rom_system_info_reset_export : out std_logic;
+ -- rom_system_info_write.export
+ rom_system_info_write_export : out std_logic;
+ -- rom_system_info_writedata.export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0)
);
end component qsys_unb2b_test;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
index db643432f2f69347a5544c11a16615c59ae5ed39..7b86de43ce4ac137327c7ccbd77726768dd99240 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
@@ -61,9 +61,11 @@ entity udp_stream is
ID : in std_logic_vector(c_unb2b_board_aux.id_w - 1 downto 0);
-- blockgen mm
- reg_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- BG control register (one for all streams)
+ -- BG control register (one for all streams)
+ reg_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_diag_bg_miso : out t_mem_miso;
- ram_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream)
+ -- BG buffer RAM (one per stream)
+ ram_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_diag_bg_miso : out t_mem_miso;
reg_diag_tx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_diag_tx_seq_miso : out t_mem_miso;
@@ -102,8 +104,10 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
+ -- enable (disabled by default)
+ constant c_bg_ctrl : t_diag_block_gen := ('0',
+ -- enable_sync
+ '0',
TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
@@ -178,7 +182,8 @@ begin
reg_tx_seq_miso => reg_diag_tx_seq_miso
);
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
g_technology => g_technology,
@@ -318,9 +323,11 @@ begin
generic map (
g_technology => g_technology,
g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
+ -- g_data_w, --FIXME
+ g_data_w => 32,
g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
+ -- sync by reading last address of data buffer
+ g_buf_use_sync => false,
g_use_rx_seq => true
)
port map (
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
index 5886a9aef1f2cdadbdeb47b185fea035593d6c63..3b03b63db8100e1a34b9447ebb6407d967f2fc90 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
@@ -41,24 +41,35 @@ entity unb2b_test is
g_design_name : string := "unb2b_test";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e1sg;
- g_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
- g_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
- g_sim : boolean := false; -- Overridden by TB
+ -- DDR4 has no master or slave, so no need to check number of MB
+ g_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_8g_1600m;
+ -- DDR4 has no master or slave, so no need to check number of MB
+ g_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_8g_1600m;
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_sim_model_ddr : boolean := false;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := false
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
@@ -75,13 +86,18 @@ entity unb2b_test is
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
- SB_CLK : in std_logic := '0'; -- Clock 10GbE back upper 24 lines
- BCK_REF_CLK : in std_logic := '0'; -- Clock 10GbE back lower 24 lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
+ -- Clock 10GbE back upper 24 lines
+ SB_CLK : in std_logic := '0';
+ -- Clock 10GbE back lower 24 lines
+ BCK_REF_CLK : in std_logic := '0';
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic := '0'; -- Reference clock for MB_I
- MB_II_REF_CLK : in std_logic := '0'; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic := '0';
+ -- Reference clock for MB_II
+ MB_II_REF_CLK : in std_logic := '0';
-- back transceivers
--BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0) := (OTHERS=>'0');
@@ -143,23 +159,31 @@ architecture str of unb2b_test is
constant c_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_125M;
-- Revision controlled constants
- constant c_use_1GbE : boolean := false; -- g_design_name="unb2b_test_1GbE" OR g_design_name="unb2b_test_10GbE" OR g_design_name="unb2b_test_all";
+ -- g_design_name="unb2b_test_1GbE" OR g_design_name="unb2b_test_10GbE" OR g_design_name="unb2b_test_all";
+ constant c_use_1GbE : boolean := false;
constant c_use_10GbE : boolean := g_design_name = "unb2b_test_10GbE" or g_design_name = "unb2b_test_all";
constant c_use_10GbE_qsfp : boolean := c_use_10GbE;
- constant c_use_10GbE_ring : boolean := false; -- c_use_10GbE;
- constant c_use_10GbE_back0 : boolean := false; -- c_use_10GbE;
- constant c_use_10GbE_back1 : boolean := false; -- c_use_10GbE;
+ -- c_use_10GbE;
+ constant c_use_10GbE_ring : boolean := false;
+ -- c_use_10GbE;
+ constant c_use_10GbE_back0 : boolean := false;
+ -- c_use_10GbE;
+ constant c_use_10GbE_back1 : boolean := false;
constant c_use_MB_I : boolean := g_design_name = "unb2b_test_ddr_MB_I" or g_design_name = "unb2b_test_ddr_MB_I_II" or g_design_name = "unb2b_test_all";
constant c_use_MB_II : boolean := g_design_name = "unb2b_test_ddr_MB_II" or g_design_name = "unb2b_test_ddr_MB_I_II" or g_design_name = "unb2b_test_all";
-- transceivers
constant c_nof_qsfp : natural := c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w;
- constant c_nof_ring : natural := 0; -- 8;--12;--c_unb2b_board_tr_ring.nof_bus * c_unb2b_board_tr_ring.bus_w;
- constant c_nof_back0 : natural := 0; -- c_unb2b_board_tr_back.bus_w;
- constant c_nof_back1 : natural := 0; -- c_unb2b_board_tr_back.bus_w;
+ -- 8;--12;--c_unb2b_board_tr_ring.nof_bus * c_unb2b_board_tr_ring.bus_w;
+ constant c_nof_ring : natural := 0;
+ -- c_unb2b_board_tr_back.bus_w;
+ constant c_nof_back0 : natural := 0;
+ -- c_unb2b_board_tr_back.bus_w;
+ constant c_nof_back1 : natural := 0;
-- 1GbE
- constant c_nof_streams_1GbE : natural := sel_a_b(c_use_1GbE,1,0); -- sel_a_b(c_use_1GbE,c_unb2b_board_nof_eth,0);
+ -- sel_a_b(c_use_1GbE,c_unb2b_board_nof_eth,0);
+ constant c_nof_streams_1GbE : natural := sel_a_b(c_use_1GbE,1,0);
-- 10GbE
constant c_nof_streams_qsfp : natural := sel_a_b(c_use_10GbE_qsfp,c_nof_qsfp,0);
@@ -173,15 +197,22 @@ architecture str of unb2b_test is
constant c_nof_ring_bus : natural := ceil_div(c_nof_streams_ring,c_unb2b_board_tr_ring.bus_w);
constant c_nof_back_bus : natural := ceil_div(c_nof_streams_back0,c_unb2b_board_tr_back.bus_w) + ceil_div(c_nof_streams_back1,c_unb2b_board_tr_back.bus_w);
- constant c_data_w_32 : natural := c_eth_data_w; -- 1GbE
- constant c_data_w_64 : natural := c_xgmii_data_w; -- 10GbE
+ -- 1GbE
+ constant c_data_w_32 : natural := c_eth_data_w;
+ -- 10GbE
+ constant c_data_w_64 : natural := c_xgmii_data_w;
-- ddr
- constant c_ddr_ctlr_data_w : natural := func_tech_ddr_ctlr_data_w(g_ddr_MB_I); -- = 576, assume both MB_I and MB_II use the same ctlr_data_w
- constant c_ddr_dp_data_w : natural := 144; -- DDR4 with dq_w = 72, rsl = 8 so ctrl data width = 576 and therefore the mixed width FIFO ratio is 576 /144 = 4
- constant c_ddr_dp_seq_dat_w : natural := 16; -- >= 1, test sequence data width. Choose c_ddr_dp_seq_dat_w <= c_ddr_dp_data_w. The seq data gets replicated to fill c_ddr_dp_data_w.
- constant c_ddr_dp_wr_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w); -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) to make full use of M9K which have at least 256 words
- constant c_ddr_dp_rd_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w); -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) or factors of 2 more to fit max number of read bursts
+ -- = 576, assume both MB_I and MB_II use the same ctlr_data_w
+ constant c_ddr_ctlr_data_w : natural := func_tech_ddr_ctlr_data_w(g_ddr_MB_I);
+ -- DDR4 with dq_w = 72, rsl = 8 so ctrl data width = 576 and therefore the mixed width FIFO ratio is 576 /144 = 4
+ constant c_ddr_dp_data_w : natural := 144;
+ -- >= 1, test sequence data width. Choose c_ddr_dp_seq_dat_w <= c_ddr_dp_data_w. The seq data gets replicated to fill c_ddr_dp_data_w.
+ constant c_ddr_dp_seq_dat_w : natural := 16;
+ -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) to make full use of M9K which have at least 256 words
+ constant c_ddr_dp_wr_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w);
+ -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) or factors of 2 more to fit max number of read bursts
+ constant c_ddr_dp_rd_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w);
constant c_ddr_db_buf_nof_data : natural := 1024;
constant c_ddr_mixed_width_ratio : natural := ratio2(c_ddr_ctlr_data_w, c_ddr_dp_data_w);
@@ -189,11 +220,14 @@ architecture str of unb2b_test is
constant c_bg_block_size : natural := 900;
constant c_bg_gapsize_1GbE : natural := 1000;
constant c_bg_gapsize_10GbE : natural := 100;
- constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
+ -- 200000*(900+100) = 200000000 cycles = 1 second
+ constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000);
constant c_use_jumbo_frames : boolean := false;
- constant c_def_1GbE_block_size : natural := 20; -- 0 first so we have time to set RX demux reg in dest. node
- constant c_def_10GbE_block_size : natural := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
+ -- 0 first so we have time to set RX demux reg in dest. node
+ constant c_def_1GbE_block_size : natural := 20;
+ -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
+ constant c_def_10GbE_block_size : natural := 700;
constant c_max_frame_len : natural := sel_a_b(c_use_jumbo_frames, 9018, 1518);
constant c_nof_header_bytes : natural := field_slv_len(c_hdr_field_arr) / c_byte_w;
@@ -262,22 +296,30 @@ architecture str of unb2b_test is
-- eth1g ch0
signal eth1g_eth0_mm_rst : std_logic;
- signal eth1g_eth0_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_eth0_tse_mosi : t_mem_mosi;
signal eth1g_eth0_tse_miso : t_mem_miso;
- signal eth1g_eth0_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_eth0_reg_mosi : t_mem_mosi;
signal eth1g_eth0_reg_miso : t_mem_miso;
- signal eth1g_eth0_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_eth0_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_eth0_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_eth0_ram_mosi : t_mem_mosi;
signal eth1g_eth0_ram_miso : t_mem_miso;
-- eth1g ch1
signal eth1g_eth1_mm_rst : std_logic;
- signal eth1g_eth1_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_eth1_tse_mosi : t_mem_mosi;
signal eth1g_eth1_tse_miso : t_mem_miso;
- signal eth1g_eth1_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_eth1_reg_mosi : t_mem_mosi;
signal eth1g_eth1_reg_miso : t_mem_miso;
- signal eth1g_eth1_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_eth1_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_eth1_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_eth1_ram_mosi : t_mem_mosi;
signal eth1g_eth1_ram_miso : t_mem_miso;
-- EPCS read
@@ -581,9 +623,12 @@ begin
g_hdr_field_arr => c_hdr_field_arr,
g_nof_streams_1GbE => c_unb2b_board_nof_eth,
g_nof_streams_qsfp => c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w,
- g_nof_streams_ring => 24, -- c_unb2b_board_tr_ring.nof_bus * c_unb2b_board_tr_ring.bus_w,
- g_nof_streams_back0 => 24, -- c_unb2b_board_tr_back.bus_w,
- g_nof_streams_back1 => 24 -- c_unb2b_board_tr_back.bus_w
+ -- c_unb2b_board_tr_ring.nof_bus * c_unb2b_board_tr_ring.bus_w,
+ g_nof_streams_ring => 24,
+ -- c_unb2b_board_tr_back.bus_w,
+ g_nof_streams_back0 => 24,
+ -- c_unb2b_board_tr_back.bus_w
+ g_nof_streams_back1 => 24
)
port map(
mm_rst => mm_rst,
@@ -873,7 +918,8 @@ begin
reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
);
- u_tr_10GbE_qsfp_and_ring: entity unb2b_board_10gbe_lib.unb2b_board_10gbe -- QSFP and Ring lines
+ -- QSFP and Ring lines
+ u_tr_10GbE_qsfp_and_ring: entity unb2b_board_10gbe_lib.unb2b_board_10gbe
generic map (
g_sim => g_sim,
g_sim_level => 1,
@@ -1031,7 +1077,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2b_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_unb2b_board_ext_clk_freq_200M)
)
port map (
rst => dp_rst,
@@ -1070,7 +1117,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
@@ -1103,7 +1151,8 @@ begin
-- DIAG data buffer
g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ -- nof words per data buffer
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data
)
port map (
---------------------------------------------------------------------------
@@ -1112,7 +1161,8 @@ begin
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+ -- use alternative external clock or externally connect to ctlr_clk_out
+ dp_clk => dp_clk,
---------------------------------------------------------------------------
-- IO_DDR
@@ -1125,11 +1175,14 @@ begin
ctlr_clk_out => ddr_I_clk200,
ctlr_rst_out => ddr_I_rst200,
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+ -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_clk_in => ddr_I_clk200,
+ -- connect ctlr_rst_out to ctlr_rst_in at top level
+ ctlr_rst_in => ddr_I_rst200,
-- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ -- register for DDR controller status info
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi,
reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-- Write / read FIFO status for monitoring purposes (in dp_clk domain)
@@ -1180,7 +1233,8 @@ begin
-- DIAG data buffer
g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ -- nof words per data buffer
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data
)
port map (
---------------------------------------------------------------------------
@@ -1189,7 +1243,8 @@ begin
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+ -- use alternative external clock or externally connect to ctlr_clk_out
+ dp_clk => dp_clk,
---------------------------------------------------------------------------
-- IO_DDR
@@ -1202,11 +1257,14 @@ begin
ctlr_clk_out => ddr_II_clk200,
ctlr_rst_out => ddr_II_rst200,
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+ -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_clk_in => ddr_II_clk200,
+ -- connect ctlr_rst_out to ctlr_rst_in at top level
+ ctlr_rst_in => ddr_II_rst200,
-- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ -- register for DDR controller status info
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi,
reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-- Write / read FIFO status for monitoring purposes (in dp_clk domain)
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
index 1fbcce3b6de1d7bae0adb60756efb0bb0f6b8cc3..e7cd4e7459c59a379473a647dabf52d7410201e5 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
@@ -28,15 +28,18 @@ use common_lib.common_field_pkg.all;
package unb2b_test_pkg is
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
- constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ -- Total header bits = 384 = 6 64b words
+ constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2;
+ -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
@@ -47,7 +50,8 @@ package unb2b_test_pkg is
( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
diff --git a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
index fbf404947d04d7a4da2c9edc811afae477859de1..a57d8af987a36995a3de74599c7043ef53d5a47d 100644
--- a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
@@ -62,24 +62,34 @@ end tb_unb2b_test;
architecture tb of tb_unb2b_test is
constant c_sim : boolean := true;
- constant c_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
- constant c_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
-
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- DDR4 has no master or slave, so no need to check number of MB
+ constant c_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
+ -- DDR4 has no master or slave, so no need to check number of MB
+ constant c_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
+
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb2b_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2b_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2b_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644 MHz
- constant c_sb_clk_period : time := tech_pll_clk_644_period; -- 644 MHz
- constant c_bck_ref_clk_period : time := tech_pll_clk_644_period; -- 644 MHz
- constant c_mb_I_ref_clk_period : time := 40 ns; -- 25 MHz
- constant c_mb_II_ref_clk_period : time := 40 ns; -- 25 MHz
+ -- 644 MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
+ -- 644 MHz
+ constant c_sb_clk_period : time := tech_pll_clk_644_period;
+ -- 644 MHz
+ constant c_bck_ref_clk_period : time := tech_pll_clk_644_period;
+ -- 25 MHz
+ constant c_mb_I_ref_clk_period : time := 40 ns;
+ -- 25 MHz
+ constant c_mb_II_ref_clk_period : time := 40 ns;
constant c_pps_period : natural := 1000;
-- DUT
@@ -105,8 +115,10 @@ architecture tb of tb_unb2b_test is
signal qsfp_led : std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- DDR reference clocks
- signal mb_I_ref_clk : std_logic := '1'; -- Reference clock for MB_I
- signal mb_II_ref_clk : std_logic := '1'; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ signal mb_I_ref_clk : std_logic := '1';
+ -- Reference clock for MB_II
+ signal mb_II_ref_clk : std_logic := '1';
-- DDR4 PHY interface
signal MB_I_IN : t_tech_ddr4_phy_in;
@@ -136,33 +148,51 @@ architecture tb of tb_unb2b_test is
signal si_lpbk_8 : std_logic_vector(c_unb2b_board_tr_back.bus_w - 1 downto 0);
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- sa_clk <= not sa_clk after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
- sb_clk <= not sb_clk after c_sb_clk_period / 2; -- Serial Gigabit IO sb clock (644 MHz)
- bck_ref_clk <= not bck_ref_clk after c_bck_ref_clk_period / 2; -- Serial Gigabit IO bck_ref clock (644 MHz)
- mb_I_ref_clk <= not mb_I_ref_clk after c_mb_I_ref_clk_period / 2; -- MB I reference clock (25 MHz)
- mb_II_ref_clk <= not mb_II_ref_clk after c_mb_II_ref_clk_period / 2; -- MB II reference clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ sa_clk <= not sa_clk after c_sa_clk_period / 2;
+ -- Serial Gigabit IO sb clock (644 MHz)
+ sb_clk <= not sb_clk after c_sb_clk_period / 2;
+ -- Serial Gigabit IO bck_ref clock (644 MHz)
+ bck_ref_clk <= not bck_ref_clk after c_bck_ref_clk_period / 2;
+ -- MB I reference clock (25 MHz)
+ mb_I_ref_clk <= not mb_I_ref_clk after c_mb_I_ref_clk_period / 2;
+ -- MB II reference clock (25 MHz)
+ mb_II_ref_clk <= not mb_II_ref_clk after c_mb_II_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index a23d26634c2fbf51d0e5ce4ec96d2069c24970cc..7625455dde1fd5b3c02672326e917730f42a98c0 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -43,15 +43,20 @@ entity ctrl_unb2b_board is
----------------------------------------------------------------------------
g_technology : natural := c_tech_arria10_e1sg;
g_sim : boolean := false;
- g_sim_level : natural := 1; -- 0 = use IP; 1 = use fast serdes model;
- g_sim_mm_clk_period : time := 10 ns; -- use e.g. c_mmf_mm_clk_period for MM bus file IO model, use e.g. 10 ns for MM access with TSE MAC IP
+ -- 0 = use IP; 1 = use fast serdes model;
+ g_sim_level : natural := 1;
+ -- use e.g. c_mmf_mm_clk_period for MM bus file IO model, use e.g. 10 ns for MM access with TSE MAC IP
+ g_sim_mm_clk_period : time := 10 ns;
g_design_name : string := "UNUSED";
- g_fw_version : t_unb2b_board_fw_version := (0, 0); -- firmware version x.y
+ -- firmware version x.y
+ g_fw_version : t_unb2b_board_fw_version := (0, 0);
g_stamp_date : natural := 0;
g_stamp_time : natural := 0;
- g_revision_id : string := ""; -- revision_id, commit hash (first 9 chars) or number
+ -- revision_id, commit hash (first 9 chars) or number
+ g_revision_id : string := "";
g_design_note : string := "UNUSED";
- g_base_ip : std_logic_vector(16 - 1 downto 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy
+ -- Base IP address used by unb_osy: 10.99.xx.yy
+ g_base_ip : std_logic_vector(16 - 1 downto 0) := X"0A63";
g_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_125M;
g_eth_clk_freq : natural := c_unb2b_board_eth_clk_freq_125M;
g_tse_clk_buf : boolean := false;
@@ -95,7 +100,8 @@ entity ctrl_unb2b_board is
-- STRING := "4688" = 3750+ 938 = 337.5
-- STRING := "4844" = 3750+1094 = 348.75
-- STRING := "5000" = 3750+1250 = 360
- g_dp_clk_phase : string := "0"; -- phase offset for PLL c0, typically any phase is fine, do not use 225 +-30 degrees because there the PPS edge occurs
+ -- phase offset for PLL c0, typically any phase is fine, do not use 225 +-30 degrees because there the PPS edge occurs
+ g_dp_clk_phase : string := "0";
----------------------------------------------------------------------------
-- 1GbE UDP offload
@@ -107,14 +113,18 @@ entity ctrl_unb2b_board is
-- Auxiliary Interface
----------------------------------------------------------------------------
g_fpga_temp_high : natural := 85;
- g_app_led_red : boolean := false; -- when TRUE use external LED control via app_led_red
- g_app_led_green : boolean := false; -- when TRUE use external LED control via app_led_green
+ -- when TRUE use external LED control via app_led_red
+ g_app_led_red : boolean := false;
+ -- when TRUE use external LED control via app_led_green
+ g_app_led_green : boolean := false;
g_aux : t_c_unb2b_board_aux := c_unb2b_board_aux;
g_factory_image : boolean := false;
g_protect_addr_range: boolean := false;
- g_protected_addr_lo : natural := 0; -- Byte address
- g_protected_addr_hi : natural := 41943039 -- Byte address, for UniBoard1 this is 640 sectors*256 pages*256 bytes -1 = 41943039
+ -- Byte address
+ g_protected_addr_lo : natural := 0;
+ -- Byte address, for UniBoard1 this is 640 sectors*256 pages*256 bytes -1 = 41943039
+ g_protected_addr_hi : natural := 41943039
);
port (
--
@@ -123,33 +133,49 @@ entity ctrl_unb2b_board is
-- System
cs_sim : out std_logic;
- xo_ethclk : out std_logic; -- 125 MHz ETH_CLK
- xo_rst : out std_logic; -- reset in ETH_CLK domain released after few cycles
+ -- 125 MHz ETH_CLK
+ xo_ethclk : out std_logic;
+ -- reset in ETH_CLK domain released after few cycles
+ xo_rst : out std_logic;
xo_rst_n : out std_logic;
- ext_clk200 : out std_logic; -- 200 MHz CLK
- ext_rst200 : out std_logic; -- reset in CLK clock domain released after mm_rst
-
- mm_clk : out std_logic; -- MM clock from xo_ethclk PLL
- mm_rst : out std_logic; -- reset in MM clock domain released after xo_ethclk PLL locked
-
- dp_rst : out std_logic; -- reset in DP clock domain released after mm_rst and after CLK PLL locked in case g_dp_clk_use_pll=TRUE
- dp_clk : out std_logic; -- 200 MHz DP clock from CLK system clock direct or via CLK PLL dependent on g_dp_clk_use_pll
- dp_pps : out std_logic; -- PPS in dp_clk domain
- dp_rst_in : in std_logic; -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
- dp_clk_in : in std_logic; -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
-
- mb_I_ref_rst : out std_logic; -- reset in MB_I_REF_CLK domain released after mm_rst
- mb_II_ref_rst : out std_logic; -- reset in MB_II_REF_CLK domain released after mm_rst
-
- this_chip_id : out std_logic_vector(c_unb2b_board_nof_chip_w - 1 downto 0); -- [1:0], so range 0-3 for PN
- this_bck_id : out std_logic_vector(c_unb2b_board_nof_uniboard_w - 1 downto 0); -- [5:0] used out of ID[7:2] to index UniBoard2 boards
+ -- 200 MHz CLK
+ ext_clk200 : out std_logic;
+ -- reset in CLK clock domain released after mm_rst
+ ext_rst200 : out std_logic;
+
+ -- MM clock from xo_ethclk PLL
+ mm_clk : out std_logic;
+ -- reset in MM clock domain released after xo_ethclk PLL locked
+ mm_rst : out std_logic;
+
+ -- reset in DP clock domain released after mm_rst and after CLK PLL locked in case g_dp_clk_use_pll=TRUE
+ dp_rst : out std_logic;
+ -- 200 MHz DP clock from CLK system clock direct or via CLK PLL dependent on g_dp_clk_use_pll
+ dp_clk : out std_logic;
+ -- PPS in dp_clk domain
+ dp_pps : out std_logic;
+ -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
+ dp_rst_in : in std_logic;
+ -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
+ dp_clk_in : in std_logic;
+
+ -- reset in MB_I_REF_CLK domain released after mm_rst
+ mb_I_ref_rst : out std_logic;
+ -- reset in MB_II_REF_CLK domain released after mm_rst
+ mb_II_ref_rst : out std_logic;
+
+ -- [1:0], so range 0-3 for PN
+ this_chip_id : out std_logic_vector(c_unb2b_board_nof_chip_w - 1 downto 0);
+ -- [5:0] used out of ID[7:2] to index UniBoard2 boards
+ this_bck_id : out std_logic_vector(c_unb2b_board_nof_uniboard_w - 1 downto 0);
app_led_red : in std_logic := '0';
app_led_green : in std_logic := '1';
-- PIOs
- pout_wdi : in std_logic; -- Toggled by unb_osy; can be overriden by reg_wdi.
+ -- Toggled by unb_osy; can be overriden by reg_wdi.
+ pout_wdi : in std_logic;
-- Manual WDI override
reg_wdi_mosi : in t_mem_mosi := c_mem_mosi_rst;
@@ -201,12 +227,16 @@ entity ctrl_unb2b_board is
-- eth1g control&monitoring
eth1g_mm_rst : in std_logic;
- eth1g_tse_mosi : in t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ eth1g_tse_mosi : in t_mem_mosi;
eth1g_tse_miso : out t_mem_miso;
- eth1g_reg_mosi : in t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ eth1g_reg_mosi : in t_mem_mosi;
eth1g_reg_miso : out t_mem_miso;
- eth1g_reg_interrupt : out std_logic; -- Interrupt
- eth1g_ram_mosi : in t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ eth1g_reg_interrupt : out std_logic;
+ -- ETH rx frame and tx frame memory
+ eth1g_ram_mosi : in t_mem_mosi;
eth1g_ram_miso : out t_mem_miso;
-- eth1g UDP streaming ports
@@ -223,11 +253,16 @@ entity ctrl_unb2b_board is
-- >>> Ctrl FPGA pins
--
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(g_aux.version_w - 1 downto 0);
@@ -244,20 +279,25 @@ entity ctrl_unb2b_board is
PMBUS_ALERT : in std_logic := '0';
-- DDR reference clock domains reset creation
- MB_I_REF_CLK : in std_logic := '0'; -- 25 MHz
- MB_II_REF_CLK : in std_logic := '0'; -- 25 MHz
+ -- 25 MHz
+ MB_I_REF_CLK : in std_logic := '0';
+ -- 25 MHz
+ MB_II_REF_CLK : in std_logic := '0';
-- 1GbE Control Interface
- ETH_CLK : in std_logic; -- 125 MHz
+ -- 125 MHz
+ ETH_CLK : in std_logic;
ETH_SGIN : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0) := (others => '0');
ETH_SGOUT : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0)
);
end ctrl_unb2b_board;
architecture str of ctrl_unb2b_board is
- constant c_rom_version : natural := 3; -- Only increment when something changes to the register map of rom_system_info.
+ -- Only increment when something changes to the register map of rom_system_info.
+ constant c_rom_version : natural := 3;
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
constant c_mm_clk_freq : natural := sel_a_b(g_sim = false,g_mm_clk_freq,c_unb2b_board_mm_clk_freq_10M);
constant c_ram_scrap : t_c_mem := (c_mem_ram_rd_latency, 9, 32, 2**9, 'X');
@@ -325,22 +365,27 @@ begin
INTA <= 'Z';
INTB <= 'Z';
- TESTIO <= (others => 'Z'); -- Leave unused INOUT tri-state
+ -- Leave unused INOUT tri-state
+ TESTIO <= (others => 'Z');
- ext_pps <= PPS; -- use more special name for PPS pin signal to ease searching for it in editor
+ -- use more special name for PPS pin signal to ease searching for it in editor
+ ext_pps <= PPS;
-----------------------------------------------------------------------------
-- ext_clk200 = CLK
-----------------------------------------------------------------------------
- i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
+ -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
+ i_ext_clk200 <= CLK;
u_common_areset_ext : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => i_ext_clk200,
out_rst => ext_rst200
);
@@ -349,15 +394,18 @@ begin
-- xo_ethclk = ETH_CLK
-----------------------------------------------------------------------------
- i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
+ -- use the ETH_CLK pin as xo_clk
+ i_xo_ethclk <= ETH_CLK;
u_common_areset_xo : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => i_xo_ethclk,
out_rst => i_xo_rst
);
@@ -369,22 +417,26 @@ begin
u_common_areset_mb_I : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ -- release reset some clock cycles after i_mm_rst went low
+ in_rst => i_mm_rst,
clk => MB_I_REF_CLK,
out_rst => mb_I_ref_rst
);
u_common_areset_mb_II : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ -- release reset some clock cycles after i_mm_rst went low
+ in_rst => i_mm_rst,
clk => MB_II_REF_CLK,
out_rst => mb_II_ref_rst
);
@@ -409,7 +461,8 @@ begin
port map (
arst => i_mm_rst,
clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
+ -- = c0
+ st_clk200 => dp_clk,
st_rst200 => common_areset_in_rst
);
end generate;
@@ -420,7 +473,8 @@ begin
g_delay_len => c_reset_len
)
port map (
- in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
+ -- release reset some clock cycles after i_mm_rst went low
+ in_rst => common_areset_in_rst,
clk => dp_clk_in,
out_rst => dp_rst
);
@@ -434,13 +488,18 @@ begin
clk125 when g_mm_clk_freq = c_unb2b_board_mm_clk_freq_125M else
clk100 when g_mm_clk_freq = c_unb2b_board_mm_clk_freq_100M else
clk50 when g_mm_clk_freq = c_unb2b_board_mm_clk_freq_50M else
- clk50; -- default
+ -- default
+ clk50;
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
+ -- 20 MHz, 50ns/2
+ epcs_clk <= not epcs_clk after 25 ns;
+ -- 50 MHz, 20ns/2
+ clk50 <= not clk50 after 10 ns;
+ -- 100 MHz, 10ns/2
+ clk100 <= not clk100 after 5 ns;
+ -- 125 MHz, 8ns/2
+ clk125 <= not clk125 after 4 ns;
sim_mm_clk <= not sim_mm_clk after g_sim_mm_clk_period / 2;
mm_locked <= '0', '1' after 70 ns;
end generate;
@@ -464,7 +523,8 @@ begin
u_unb2b_board_node_ctrl : entity work.unb2b_board_node_ctrl
generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us => c_mm_clk_freq / (10**6)
)
port map (
-- MM clock domain reset
@@ -473,11 +533,13 @@ begin
mm_rst => i_mm_rst,
-- WDI extend
mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ mm_wdi_out => mm_wdi,
-- Pulses
mm_pulse_us => OPEN,
mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
+ -- could be used to toggle a LED
+ mm_pulse_s => mm_pulse_s
);
-----------------------------------------------------------------------------
@@ -640,7 +702,8 @@ begin
mm_clk => i_mm_clk,
st_rst => dp_rst_in,
st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+ -- with unknown but constant phase to st_clk
+ pps_ext => ext_pps,
-- Memory-mapped clock domain
reg_mosi => reg_ppsh_mosi,
@@ -654,7 +717,8 @@ begin
-- I2C control for UniBoard sensors
------------------------------------------------------------------------------
- mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_s; -- mm_pulse_ms; ms pulse comes before the end of the I2C frame, this results in an overflow in simulation -- speed up in simulation
+ -- mm_pulse_ms; ms pulse comes before the end of the I2C frame, this results in an overflow in simulation -- speed up in simulation
+ mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_s;
u_mms_unb2b_board_sens : entity work.mms_unb2b_board_sens
generic map (
@@ -714,7 +778,8 @@ begin
mm_clk => i_mm_clk,
--mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
- mm_start => '1', -- this works
+ -- this works
+ mm_start => '1',
-- Memory-mapped clock domain
reg_temp_mosi => reg_fpga_temp_sens_mosi,
@@ -771,17 +836,22 @@ begin
u_eth : entity eth_lib.eth
generic map (
g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ -- Last two bytes set by board/FPGA ID.
+ g_init_ip_address => g_base_ip & X"0000",
g_cross_clock_domain => g_udp_offload,
g_frm_discard_en => true,
g_sim => g_sim,
- g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ g_sim_level => g_sim_level
)
port map (
-- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
+ -- use reset from QSYS
+ mm_rst => eth1g_mm_rst,
+ -- use mm_clk direct
+ mm_clk => i_mm_clk,
+ -- 125 MHz clock
+ eth_clk => i_tse_clk,
st_rst => eth1g_st_rst,
st_clk => eth1g_st_clk,
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
index 80d5432cf6ed616ad16f6149380e518f04c943fb..bec5dfea6c9dc3511a9cf2cecba990987c810f78 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
@@ -32,20 +32,26 @@ entity mms_unb2b_board_sens is
generic (
g_sim : boolean := false;
g_i2c_peripheral : natural;
- g_sens_nof_result : natural; -- Should match nof read bytes via I2C in the unb2b_board_sens_ctrl SEQUENCE list
- g_clk_freq : natural := 100 * 10**6; -- clk frequency in Hz
+ -- Should match nof read bytes via I2C in the unb2b_board_sens_ctrl SEQUENCE list
+ g_sens_nof_result : natural;
+ -- clk frequency in Hz
+ g_clk_freq : natural := 100 * 10**6;
g_temp_high : natural := 85;
g_comma_w : natural := 0
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
mm_start : in std_logic;
-- Memory-mapped clock domain
- reg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
- reg_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ reg_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ -- actual ranges defined by c_mm_reg
+ reg_miso : out t_mem_miso;
-- i2c bus
scl : inout std_logic := 'Z';
@@ -57,7 +63,8 @@ entity mms_unb2b_board_sens is
end mms_unb2b_board_sens;
architecture str of mms_unb2b_board_sens is
- constant c_temp_high_w : natural := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+ -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+ constant c_temp_high_w : natural := 7;
signal sens_err : std_logic;
signal sens_data : t_slv_8_arr(0 to g_sens_nof_result - 1);
@@ -79,7 +86,8 @@ begin
sla_out => reg_miso,
-- MM registers
- sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ sens_err => sens_err,
sens_data => sens_data,
-- Max temp threshold
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
index 690b1507ac402793d47bcb056b7b37114c1613f9..6caeffcf001a9419de53e512dc9b64a066cc76b8 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
@@ -31,13 +31,15 @@ entity mms_unb2b_board_system_info is
g_sim : boolean := false;
g_technology : natural := c_tech_arria10_e1sg;
g_design_name : string;
- g_fw_version : t_unb2b_board_fw_version := c_unb2b_board_fw_version; -- firmware version x.y
+ -- firmware version x.y
+ g_fw_version : t_unb2b_board_fw_version := c_unb2b_board_fw_version;
g_stamp_date : natural := 0;
g_stamp_time : natural := 0;
g_revision_id : string := "";
g_design_note : string := "";
g_rom_version : natural := 1;
- g_aux : t_c_unb2b_board_aux := c_unb2b_board_aux -- aux contains the hardware version
+ -- aux contains the hardware version
+ g_aux : t_c_unb2b_board_aux := c_unb2b_board_aux
);
port (
mm_rst : in std_logic;
@@ -72,12 +74,14 @@ architecture str of mms_unb2b_board_system_info is
-- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
- constant c_rom_addr_w : natural := 13; -- 2^13 = 8192 addresses * 32 bits = 32 kiB
+ -- 2^13 = 8192 addresses * 32 bits = 32 kiB
+ constant c_rom_addr_w : natural := 13;
constant c_mm_rom : t_c_mem := (latency => 1,
adr_w => c_rom_addr_w,
dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ -- = 2**adr_w
+ nof_dat => 2**c_rom_addr_w,
init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
index 8debc61a00f8796d34118b4aa36ceb74fbc6cd97..2359ca23bb7dc143ca6452a408374d524073026b 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
@@ -37,15 +37,21 @@ entity mms_unb2b_fpga_sens is
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
mm_start : in std_logic;
-- Memory-mapped clock domain
- reg_temp_mosi : in t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
- reg_temp_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
- reg_voltage_mosi : in t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
- reg_voltage_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ reg_temp_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ -- actual ranges defined by c_mm_reg
+ reg_temp_miso : out t_mem_miso;
+ -- actual ranges defined by c_mm_reg
+ reg_voltage_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ -- actual ranges defined by c_mm_reg
+ reg_voltage_miso : out t_mem_miso;
-- Temperature alarm output
temp_alarm : out std_logic
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
index f2886ef970e244fdfc973e7c87111c79e50f3c7c..6b15d7f190697bc70724466e1025ea1f35ff6e94 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
@@ -41,12 +41,17 @@ entity unb2b_board_clk125_pll is
);
port (
arst : in std_logic := '0';
- clk125 : in std_logic := '0'; -- connect to UniBoard ETH_clk pin (125 MHz)
+ -- connect to UniBoard ETH_clk pin (125 MHz)
+ clk125 : in std_logic := '0';
- c0_clk20 : out std_logic; -- PLL c0
- c1_clk50 : out std_logic; -- PLL c1
- c2_clk100 : out std_logic; -- PLL c2
- c3_clk125 : out std_logic; -- PLL c3
+ -- PLL c0
+ c0_clk20 : out std_logic;
+ -- PLL c1
+ c1_clk50 : out std_logic;
+ -- PLL c2
+ c2_clk100 : out std_logic;
+ -- PLL c3
+ c3_clk125 : out std_logic;
pll_locked : out std_logic
);
end unb2b_board_clk125_pll;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
index ac2db2f0ca43b5d3458a016c25a86eae4d501a1c..3d62521cc0e512866cda65c06debc2840c055e72 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
@@ -95,20 +95,27 @@ entity unb2b_board_clk200_pll is
g_technology : natural := c_tech_arria10_e1sg;
g_use_clkbuf : boolean := true;
g_use_fpll : boolean := false;
- g_operation_mode : string := "NORMAL"; -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
- g_clk200_phase_shift : string := "0"; -- default use 0 degrees, see clk200_pll.vhd for other phase values
- g_clk200p_phase_shift : string := "0" -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
+ g_operation_mode : string := "NORMAL";
+ -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ g_clk200_phase_shift : string := "0";
+ -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ g_clk200p_phase_shift : string := "0"
);
port (
-- It depends on g_sel which outputs are actually available
-- . common
arst : in std_logic := '0';
- clk200 : in std_logic := '0'; -- connect to UniBoard CLK pin
- st_clk200 : out std_logic; -- PLL c0 = g_clk200_phase_shift degrees phase offset to input clk200
+ -- connect to UniBoard CLK pin
+ clk200 : in std_logic := '0';
+ -- PLL c0 = g_clk200_phase_shift degrees phase offset to input clk200
+ st_clk200 : out std_logic;
st_rst200 : out std_logic;
- st_clk200p : out std_logic; -- PLL c1 = g_clk200p_phase_shift degrees phase offset to input clk200 (see clk200_pll.vhd from MegaWizard)
+ -- PLL c1 = g_clk200p_phase_shift degrees phase offset to input clk200 (see clk200_pll.vhd from MegaWizard)
+ st_clk200p : out std_logic;
st_rst200p : out std_logic;
- st_clk400 : out std_logic; -- PLL c2 = 0 degrees phase offset to input clk200
+ -- PLL c2 = 0 degrees phase offset to input clk200
+ st_clk400 : out std_logic;
st_rst400 : out std_logic
);
end unb2b_board_clk200_pll;
@@ -171,10 +178,14 @@ begin
)
port map (
areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
+ -- 200 MHz
+ inclk0 => clk200buf,
+ -- 200 MHz
+ c0 => i_st_clk200,
+ -- 200 MHz shifted 90 degrees
+ c1 => i_st_clk200p,
+ -- 400 MHz
+ c2 => i_st_clk400,
locked => st_locked
);
end generate;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
index 24625f7333a8fd823fd6eed0cf2e5198724b47e4..bdc2247e396e57633b2c6f1b3adab39083c810d4 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
@@ -39,12 +39,17 @@ entity unb2b_board_clk25_pll is
);
port (
arst : in std_logic := '0';
- clk25 : in std_logic := '0'; -- connect to UniBoard ETH_clk pin (25 MHz)
+ -- connect to UniBoard ETH_clk pin (25 MHz)
+ clk25 : in std_logic := '0';
- c0_clk20 : out std_logic; -- PLL c0
- c1_clk50 : out std_logic; -- PLL c1
- c2_clk100 : out std_logic; -- PLL c2
- c3_clk125 : out std_logic; -- PLL c3
+ -- PLL c0
+ c0_clk20 : out std_logic;
+ -- PLL c1
+ c1_clk50 : out std_logic;
+ -- PLL c2
+ c2_clk100 : out std_logic;
+ -- PLL c3
+ c3_clk125 : out std_logic;
pll_locked : out std_logic
);
end unb2b_board_clk25_pll;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
index a5877c96a459a50258e9d6de8005778240fbda51..c31e8752b120813baa899edad14aae3f8bf30940 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
@@ -33,20 +33,27 @@ use common_lib.common_pkg.all;
entity unb2b_board_clk_rst is
port (
-- Reference clock and reset to SOPC system PLL
- xo_clk : in std_logic; -- reference XO clock (e.g. 25 MHz also use by PLL in SOPC)
- xo_rst_n : out std_logic; -- NOT xo_rst (e.g. to reset the SOPC with NIOS2 uP)
+ -- reference XO clock (e.g. 25 MHz also use by PLL in SOPC)
+ xo_clk : in std_logic;
+ -- NOT xo_rst (e.g. to reset the SOPC with NIOS2 uP)
+ xo_rst_n : out std_logic;
-- System clock and locked from SOPC system PLL
- sys_clk : in std_logic; -- system clock derived from the reference XO clock (e.g. 125 MHz by a PLL from SOPC with NIOS2 uP)
- sys_locked : in std_logic; -- system clock PLL locked
- sys_rst : out std_logic -- system reset released some cycles after the system clock PLL has in locked
+ -- system clock derived from the reference XO clock (e.g. 125 MHz by a PLL from SOPC with NIOS2 uP)
+ sys_clk : in std_logic;
+ -- system clock PLL locked
+ sys_locked : in std_logic;
+ -- system reset released some cycles after the system clock PLL has in locked
+ sys_rst : out std_logic
);
end unb2b_board_clk_rst;
architecture str of unb2b_board_clk_rst is
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
-- XO clock domain
- signal xo_rst : std_logic; -- initial reset released after some XO clock cycles
+ -- initial reset released after some XO clock cycles
+ signal xo_rst : std_logic;
-- SYS clock domain
signal sys_locked_n : std_logic;
@@ -56,11 +63,13 @@ begin
u_common_areset_xo : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => xo_clk,
out_rst => xo_rst
);
@@ -70,11 +79,13 @@ begin
u_common_areset_sys : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ -- release reset after some clock cycles when the PLL has locked
+ in_rst => sys_locked_n,
clk => sys_clk,
out_rst => sys_rst
);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
index 06b87a197e1dbb9cfea0f70f306cb3308e86a314..14fa0f25e6ee66ab4e2663238fdfcdbd6ff59bdf 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
@@ -34,7 +34,8 @@ entity unb2b_board_hmc_ctrl is
port (
rst : in std_logic;
clk : in std_logic;
- start : in std_logic; -- pulse to start the I2C sequence to read out the sensors
+ -- pulse to start the I2C sequence to read out the sensors
+ start : in std_logic;
out_dat : out std_logic_vector(c_byte_w - 1 downto 0);
out_val : out std_logic;
in_dat : in std_logic_vector(c_byte_w - 1 downto 0);
@@ -53,15 +54,18 @@ architecture rtl of unb2b_board_hmc_ctrl is
-- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
-- Assume clk <= 200 MHz, so 5 ns period. Hence timeout of 4000 is enough.
- constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
+ -- wait 16 * 256 = 4096 clk periods
+ constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16);
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
+ -- RX supply
+ SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
+ -- TX supply
+ SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
index affbc014cb1d346b7737e6de055d4398127139e8..de7e65a7bd284cf2b35df0868ecf5b6db6124bde 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
@@ -32,30 +32,43 @@ use common_lib.common_pkg.all;
entity unb2b_board_node_ctrl is
generic (
- g_pulse_us : natural := 125; -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- g_pulse_ms : natural := 1000; -- nof pulse_us pulses to get ms period (fixed, use less to speed up simulation)
- g_pulse_s : natural := 1000; -- nof pulse_ms pulses to get s period (fixed, use less to speed up simulation)
- g_wdi_extend_w : natural := 14 -- extend the mm_wdi_in by toggling the mm_wdi_out for about 2**(14-1)= 8 s more
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us : natural := 125;
+ -- nof pulse_us pulses to get ms period (fixed, use less to speed up simulation)
+ g_pulse_ms : natural := 1000;
+ -- nof pulse_ms pulses to get s period (fixed, use less to speed up simulation)
+ g_pulse_s : natural := 1000;
+ -- extend the mm_wdi_in by toggling the mm_wdi_out for about 2**(14-1)= 8 s more
+ g_wdi_extend_w : natural := 14
);
port (
-- MM clock domain reset
- mm_clk : in std_logic; -- MM clock
- mm_locked : in std_logic := '1'; -- MM clock PLL locked (or use default '1')
- mm_rst : out std_logic; -- MM reset released after MM clock PLL has locked
+ -- MM clock
+ mm_clk : in std_logic;
+ -- MM clock PLL locked (or use default '1')
+ mm_locked : in std_logic := '1';
+ -- MM reset released after MM clock PLL has locked
+ mm_rst : out std_logic;
-- WDI extend
- mm_wdi_in : in std_logic; -- from software running on the NIOS2 in the SOPC design
- mm_wdi_out : out std_logic; -- to FPGA pin
+ -- from software running on the NIOS2 in the SOPC design
+ mm_wdi_in : in std_logic;
+ -- to FPGA pin
+ mm_wdi_out : out std_logic;
-- Pulses
- mm_pulse_us : out std_logic; -- pulses every us
- mm_pulse_ms : out std_logic; -- pulses every ms
- mm_pulse_s : out std_logic -- pulses every s
+ -- pulses every us
+ mm_pulse_us : out std_logic;
+ -- pulses every ms
+ mm_pulse_ms : out std_logic;
+ -- pulses every s
+ mm_pulse_s : out std_logic
);
end unb2b_board_node_ctrl;
architecture str of unb2b_board_node_ctrl is
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
signal mm_locked_n : std_logic;
signal i_mm_rst : std_logic;
@@ -68,11 +81,13 @@ begin
u_common_areset_mm : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ -- release reset after some clock cycles when the PLL has locked
+ in_rst => mm_locked_n,
clk => mm_clk,
out_rst => i_mm_rst
);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
index 50a6d2d7a593b54b932f9ed9bdfcec53db98972a..8fe6f9a04488aaecea0b725e892fe02ee580d1c6 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
@@ -45,122 +45,172 @@ package unb2b_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
-- *_dat_w : The default MM data width is c_word_w=32, otherwise it is specified in the record
type t_c_unb2b_board_peripherals_mm_reg is record
- cross_clock_domain : boolean; -- = TRUE -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ -- = TRUE -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ cross_clock_domain : boolean;
-- 1GbE
- reg_tse_adr_w : natural; -- = 10 -- = c_tse_byte_addr_w from tse_pkg.vhd
- reg_eth_adr_w : natural; -- = 4 -- = c_eth_reg_addr_w from eth_pkg.vhd
- ram_eth_adr_w : natural; -- = 10 -- = c_eth_ram_addr_w from eth_pkg.vhd
+ -- = 10 -- = c_tse_byte_addr_w from tse_pkg.vhd
+ reg_tse_adr_w : natural;
+ -- = 4 -- = c_eth_reg_addr_w from eth_pkg.vhd
+ reg_eth_adr_w : natural;
+ -- = 10 -- = c_eth_ram_addr_w from eth_pkg.vhd
+ ram_eth_adr_w : natural;
-- pi_system_info (first word of reg_unb_system_info_adr_w is backwards compatible with the original single word PIO system info)
- reg_unb_system_info_adr_w : natural; -- = 5 -- fixed, from c_mm_reg in unb_system_info_reg
- rom_unb_system_info_adr_w : natural; -- = 13 -- fixed, from c_mm_rom in mms_unb_system_info
+ -- = 5 -- fixed, from c_mm_reg in unb_system_info_reg
+ reg_unb_system_info_adr_w : natural;
+ -- = 13 -- fixed, from c_mm_rom in mms_unb_system_info
+ rom_unb_system_info_adr_w : natural;
-- pi_reg_common
- reg_common_adr_w : natural; -- = 1 -- fixed, from c_mem_reg in mms_common_reg
+ -- = 1 -- fixed, from c_mem_reg in mms_common_reg
+ reg_common_adr_w : natural;
-- pi_ppsh
- reg_ppsh_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in ppsh_reg
+ -- = 2 -- fixed, from c_mm_reg in ppsh_reg
+ reg_ppsh_adr_w : natural;
-- pi_unb_sens
- reg_unb_sens_adr_w : natural; -- = 6 -- fixed, from c_mm_reg in unb_sens_reg
+ -- = 6 -- fixed, from c_mm_reg in unb_sens_reg
+ reg_unb_sens_adr_w : natural;
-- pi_dpmm
- reg_dpmm_data_adr_w : natural; -- = 1 -- fixed, see dp_fifo_to_mm.vhd
- reg_dpmm_ctrl_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_fifo_to_mm_reg.vhd
+ -- = 1 -- fixed, see dp_fifo_to_mm.vhd
+ reg_dpmm_data_adr_w : natural;
+ -- = 1 -- fixed, from c_mm_reg in dp_fifo_to_mm_reg.vhd
+ reg_dpmm_ctrl_adr_w : natural;
-- pi_mmdp
- reg_mmdp_data_adr_w : natural; -- = 1 -- fixed, see dp_fifo_from_mm.vhd
- reg_mmdp_ctrl_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_fifo_from_mm_reg.vhd
+ -- = 1 -- fixed, see dp_fifo_from_mm.vhd
+ reg_mmdp_data_adr_w : natural;
+ -- = 1 -- fixed, from c_mm_reg in dp_fifo_from_mm_reg.vhd
+ reg_mmdp_ctrl_adr_w : natural;
-- pi_dp_ram_from_mm
- reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
+ -- = 1 -- fixed, see dp_ram_from_mm.vhd
+ reg_dp_ram_from_mm_adr_w : natural;
-- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
-- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
- reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
+ -- = 3 -- fixed, from c_mm_reg in epcs_reg
+ reg_epcs_adr_w : natural;
-- pi_remu
- reg_remu_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in remu_reg
+ -- = 3 -- fixed, from c_mm_reg in remu_reg
+ reg_remu_adr_w : natural;
-- pi_ddr
-- pi_ddr_capture (uses DP-MM read FIFO for data access)
- reg_ddr_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in ddr_reg
+ -- = 3 -- fixed, from c_mm_reg in ddr_reg
+ reg_ddr_adr_w : natural;
-- pi_io_ddr
- reg_io_ddr_adr_w : natural; -- = 16 -- fixed, from c_mm_reg in io_ddr (3) and in io_ddr_reg (8) that get multiplexed in on addresses 0..2, 8..15
+ -- = 16 -- fixed, from c_mm_reg in io_ddr (3) and in io_ddr_reg (8) that get multiplexed in on addresses 0..2, 8..15
+ reg_io_ddr_adr_w : natural;
-- pi_tr_nonbonded
- reg_tr_nonbonded_adr_w : natural; -- = 4 -- fixed, from c_mm_reg in tr_nonbonded_reg
+ -- = 4 -- fixed, from c_mm_reg in tr_nonbonded_reg
+ reg_tr_nonbonded_adr_w : natural;
-- pi_diagnostics
- reg_diagnostics_adr_w : natural; -- = 6 -- fixed, from c_mm_reg in diagnostics_reg
+ -- = 6 -- fixed, from c_mm_reg in diagnostics_reg
+ reg_diagnostics_adr_w : natural;
-- pi_dp_throttle
- reg_dp_throttle_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in dp_throttle_reg
+ -- = 2 -- fixed, from c_mm_reg in dp_throttle_reg
+ reg_dp_throttle_adr_w : natural;
-- pi_bsn_source
- reg_bsn_source_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in dp_bsn_source_reg.vhd
+ -- = 2 -- fixed, from c_mm_reg in dp_bsn_source_reg.vhd
+ reg_bsn_source_adr_w : natural;
-- pi_bsn_schedurer
- reg_bsn_scheduler_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_bsn_scheduler_reg.vhd
+ -- = 1 -- fixed, from c_mm_reg in dp_bsn_scheduler_reg.vhd
+ reg_bsn_scheduler_adr_w : natural;
-- pi_bsn_monitor
- reg_bsn_monitor_adr_w : natural; -- = 4 -- fixed, from c_mm_reg in dp_bsn_monitor_reg.vhd
+ -- = 4 -- fixed, from c_mm_reg in dp_bsn_monitor_reg.vhd
+ reg_bsn_monitor_adr_w : natural;
-- pi_aduh_quad (defaults for ADU)
- reg_adc_quad_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in aduh_quad_reg.vhd
+ -- = 3 -- fixed, from c_mm_reg in aduh_quad_reg.vhd
+ reg_adc_quad_adr_w : natural;
-- pi_aduh_i2c_commander (defaults for ADU)
- reg_i2c_commander_adr_w : natural; -- = 6 -- = c_i2c_cmdr_aduh_i2c_mm.control_adr_w, from i2c_commander_aduh_pkg, used to pass on commander_adr_w
- ram_i2c_protocol_adr_w : natural; -- = 13 -- = c_i2c_cmdr_aduh_i2c_mm.protocol_adr_w, from i2c_commander_aduh_pkg
- ram_i2c_result_adr_w : natural; -- = 12 -- = c_i2c_cmdr_aduh_i2c_mm.result_adr_w, from i2c_commander_aduh_pkg
+ -- = 6 -- = c_i2c_cmdr_aduh_i2c_mm.control_adr_w, from i2c_commander_aduh_pkg, used to pass on commander_adr_w
+ reg_i2c_commander_adr_w : natural;
+ -- = 13 -- = c_i2c_cmdr_aduh_i2c_mm.protocol_adr_w, from i2c_commander_aduh_pkg
+ ram_i2c_protocol_adr_w : natural;
+ -- = 12 -- = c_i2c_cmdr_aduh_i2c_mm.result_adr_w, from i2c_commander_aduh_pkg
+ ram_i2c_result_adr_w : natural;
-- pi_aduh_monitor (defaults for ADU or WG used in bn_capture)
- reg_aduh_mon_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in aduh_monitor_reg.vhd
- ram_aduh_mon_dat_w : natural; -- = 32 -- = c_sp_data_w, see node_bn_capture.vhd
- ram_aduh_mon_adr_w : natural; -- = 8 -- = ceil_log2(c_bn_capture.sp.monitor_buffer_nof_samples/c_wideband_factor), see node_bn_capture.vhd
+ -- = 2 -- fixed, from c_mm_reg in aduh_monitor_reg.vhd
+ reg_aduh_mon_adr_w : natural;
+ -- = 32 -- = c_sp_data_w, see node_bn_capture.vhd
+ ram_aduh_mon_dat_w : natural;
+ -- = 8 -- = ceil_log2(c_bn_capture.sp.monitor_buffer_nof_samples/c_wideband_factor), see node_bn_capture.vhd
+ ram_aduh_mon_adr_w : natural;
-- pi_diag_wg_wideband.py (defaults for WG used in bn_capture)
- reg_diag_wg_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in diag_wg_wideband_reg
- ram_diag_wg_dat_w : natural; -- = 8 -- defined here, see bn_capture_input.vhd
- ram_diag_wg_adr_w : natural; -- = 10 -- defined here, see bn_capture_input.vhd
+ -- = 2 -- fixed, from c_mm_reg in diag_wg_wideband_reg
+ reg_diag_wg_adr_w : natural;
+ -- = 8 -- defined here, see bn_capture_input.vhd
+ ram_diag_wg_dat_w : natural;
+ -- = 10 -- defined here, see bn_capture_input.vhd
+ ram_diag_wg_adr_w : natural;
-- pi_diag_data_buffer.py
- ram_diag_db_nof_buf : natural; -- = 16
- ram_diag_db_buf_size : natural; -- = 1024
- ram_diag_db_adr_w : natural; -- = 14 -- = ram_diag_db_nof_buf*ceil_log2(ram_diag_db_buf_size)
- reg_diag_db_adr_w : natural; -- = 5 -- 32 words for 16 streams max
+ -- = 16
+ ram_diag_db_nof_buf : natural;
+ -- = 1024
+ ram_diag_db_buf_size : natural;
+ -- = 14 -- = ram_diag_db_nof_buf*ceil_log2(ram_diag_db_buf_size)
+ ram_diag_db_adr_w : natural;
+ -- = 5 -- 32 words for 16 streams max
+ reg_diag_db_adr_w : natural;
-- pi_diag_block_gen (defaults when used with the BF for Apertif)
- reg_diag_bg_adr_w : natural; -- = 3
- ram_diag_bg_adr_w : natural; -- = 11 -- = ceil_log2(c_bf.nof_subbands*c_bf.nof_signal_paths/c_bf.nof_input_streams = 24*64/16 = 96) + ceil_log2(c_bf.nof_input_streams = 16)
+ -- = 3
+ reg_diag_bg_adr_w : natural;
+ -- = 11 -- = ceil_log2(c_bf.nof_subbands*c_bf.nof_signal_paths/c_bf.nof_input_streams = 24*64/16 = 96) + ceil_log2(c_bf.nof_input_streams = 16)
+ ram_diag_bg_adr_w : natural;
-- pi_diag_tx_seq.py
- reg_diag_tx_seq_w : natural; -- = 2
+ -- = 2
+ reg_diag_tx_seq_w : natural;
-- pi_diag_tx_seq.py
- reg_diag_rx_seq_w : natural; -- = 3
+ -- = 3
+ reg_diag_rx_seq_w : natural;
-- pi_bf_bf (defaults for the BF for Apertif)
- reg_bf_offsets_adr_w : natural; -- = 5 -- = ceil_log2(c_bf.nof_offsets = 6) + ceil_log2(c_bf.nof_bf_units = 4)
- ram_bf_weights_adr_w : natural; -- = 16 -- = ceil_log2(c_bf.nof_bf_units*c_bf.nof_signal_paths*c_bf.nof_weights = 4 * 64 * 256 = 65536)
- ram_st_sst_bf_adr_w : natural; -- = 11 -- = ceil_log2(c_bf.nof_bf_units*c_bf.stat_data_sz*c_bf.nof_weights = 4 * 2 * 256 = 2048)
+ -- = 5 -- = ceil_log2(c_bf.nof_offsets = 6) + ceil_log2(c_bf.nof_bf_units = 4)
+ reg_bf_offsets_adr_w : natural;
+ -- = 16 -- = ceil_log2(c_bf.nof_bf_units*c_bf.nof_signal_paths*c_bf.nof_weights = 4 * 64 * 256 = 65536)
+ ram_bf_weights_adr_w : natural;
+ -- = 11 -- = ceil_log2(c_bf.nof_bf_units*c_bf.stat_data_sz*c_bf.nof_weights = 4 * 2 * 256 = 2048)
+ ram_st_sst_bf_adr_w : natural;
-- pi_mdio
- reg_mdio_adr_w : natural; -- = 3
+ -- = 3
+ reg_mdio_adr_w : natural;
-- dp_offload
- reg_dp_offload_tx_adr_w : natural; -- = 1
+ -- = 1
+ reg_dp_offload_tx_adr_w : natural;
-- pi_unb_fpga_sensors
- reg_fpga_temp_sens_adr_w : natural; -- = 3
- reg_fpga_voltage_sens_adr_w : natural; -- = 4
+ -- = 3
+ reg_fpga_temp_sens_adr_w : natural;
+ -- = 4
+ reg_fpga_voltage_sens_adr_w : natural;
-- pi_unb_pmbus
- reg_unb_pmbus_adr_w : natural; -- = 6
+ -- = 6
+ reg_unb_pmbus_adr_w : natural;
end record;
constant c_unb2b_board_peripherals_mm_reg_default : t_c_unb2b_board_peripherals_mm_reg := (true, 10, 4, 10, 5, 13, 1, 2, 6, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1, 3, 4, 6);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
index ecc6fbb01be98b27604e6e0aa49c84cb2d09a4fc..849a8ab3360dbbd8182079f4eb3cfcff41aefa56 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
@@ -28,38 +28,58 @@ use dp_lib.dp_stream_pkg.all;
package unb2b_board_pkg is
-- UniBoard
- constant c_unb2b_board_nof_node : natural := 4; -- number of nodes on UniBoard
- constant c_unb2b_board_nof_node_w : natural := 2; -- = ceil_log2(c_unb2b_board_nof_node)
- constant c_unb2b_board_nof_chip : natural := c_unb2b_board_nof_node; -- = 4
- constant c_unb2b_board_nof_chip_w : natural := 2; -- = ceil_log2(c_unb2b_board_nof_chip)
- constant c_unb2b_board_nof_ddr : natural := 2; -- each node has 2 DDR modules
+ -- number of nodes on UniBoard
+ constant c_unb2b_board_nof_node : natural := 4;
+ -- = ceil_log2(c_unb2b_board_nof_node)
+ constant c_unb2b_board_nof_node_w : natural := 2;
+ -- = 4
+ constant c_unb2b_board_nof_chip : natural := c_unb2b_board_nof_node;
+ -- = ceil_log2(c_unb2b_board_nof_chip)
+ constant c_unb2b_board_nof_chip_w : natural := 2;
+ -- each node has 2 DDR modules
+ constant c_unb2b_board_nof_ddr : natural := 2;
-- Subrack
- constant c_unb2b_board_nof_uniboard : natural := 4; -- nof UniBoard in a subrack
- constant c_unb2b_board_nof_uniboard_w : natural := 6; -- Only 2 required for 4 boards; full width is 6.
+ -- nof UniBoard in a subrack
+ constant c_unb2b_board_nof_uniboard : natural := 4;
+ -- Only 2 required for 4 boards; full width is 6.
+ constant c_unb2b_board_nof_uniboard_w : natural := 6;
-- Clock frequencies
- constant c_unb2b_board_ext_clk_freq_200M : natural := 200 * 10**6; -- external clock, SMA clock
- constant c_unb2b_board_ext_clk_freq_256M : natural := 256 * 10**6; -- external clock, SMA clock
- constant c_unb2b_board_eth_clk_freq_25M : natural := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
- constant c_unb2b_board_eth_clk_freq_125M : natural := 125 * 10**6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
- constant c_unb2b_board_tse_clk_freq : natural := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
- constant c_unb2b_board_cal_clk_freq : natural := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
- constant c_unb2b_board_mm_clk_freq_10M : natural := 10 * 10**6; -- clock when g_sim=TRUE
- constant c_unb2b_board_mm_clk_freq_25M : natural := 25 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2b_board_mm_clk_freq_50M : natural := 50 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2b_board_mm_clk_freq_100M : natural := 100 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2b_board_mm_clk_freq_125M : natural := 125 * 10**6; -- clock derived from ETH_clk by PLL
+ -- external clock, SMA clock
+ constant c_unb2b_board_ext_clk_freq_200M : natural := 200 * 10**6;
+ -- external clock, SMA clock
+ constant c_unb2b_board_ext_clk_freq_256M : natural := 256 * 10**6;
+ -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
+ constant c_unb2b_board_eth_clk_freq_25M : natural := 25 * 10**6;
+ -- fixed 125 MHz ETH XO clock used as direct clock for TSE
+ constant c_unb2b_board_eth_clk_freq_125M : natural := 125 * 10**6;
+ -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
+ constant c_unb2b_board_tse_clk_freq : natural := 125 * 10**6;
+ -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
+ constant c_unb2b_board_cal_clk_freq : natural := 40 * 10**6;
+ -- clock when g_sim=TRUE
+ constant c_unb2b_board_mm_clk_freq_10M : natural := 10 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2b_board_mm_clk_freq_25M : natural := 25 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2b_board_mm_clk_freq_50M : natural := 50 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2b_board_mm_clk_freq_100M : natural := 100 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2b_board_mm_clk_freq_125M : natural := 125 * 10**6;
-- I2C
- constant c_unb2b_board_reg_sens_adr_w : natural := 3; -- must match ceil_log2(c_mm_nof_dat) in unb2b_board_sens_reg.vhd
+ -- must match ceil_log2(c_mm_nof_dat) in unb2b_board_sens_reg.vhd
+ constant c_unb2b_board_reg_sens_adr_w : natural := 3;
constant c_i2c_peripheral_sens : natural := 0;
constant c_i2c_peripheral_pmbus : natural := 1;
constant c_i2c_peripheral_hmc : natural := 2;
-- ETH
- constant c_unb2b_board_nof_eth : natural := 2; -- number of ETH channels per node
+ -- number of ETH channels per node
+ constant c_unb2b_board_nof_eth : natural := 2;
-- CONSTANT RECORD DECLARATIONS ---------------------------------------------
@@ -78,19 +98,27 @@ package unb2b_board_pkg is
end record;
--CONSTANT c_unb2b_board_tr_back : t_c_unb2b_board_tr := (2, 24, 3); -- per node: 2 buses with 24 channels
- constant c_unb2b_board_tr_back : t_c_unb2b_board_tr := (1, 24, 3); -- per node: 1 buses with 24 channels (testing)
+ -- per node: 1 buses with 24 channels (testing)
+ constant c_unb2b_board_tr_back : t_c_unb2b_board_tr := (1, 24, 3);
--CONSTANT c_unb2b_board_tr_back : t_c_unb2b_board_tr := (2, 12, 3); -- per node: 2 buses with 24 channels (testing)
--CONSTANT c_unb2b_board_tr_back : t_c_unb2b_board_tr := (2, 4, 3); -- per node: 2 buses with 24 channels (testing)
- constant c_unb2b_board_tr_ring : t_c_unb2b_board_tr := (2, 12, 0); -- per node: 2 buses with 12 channels
+ -- per node: 2 buses with 12 channels
+ constant c_unb2b_board_tr_ring : t_c_unb2b_board_tr := (2, 12, 0);
--CONSTANT c_unb2b_board_tr_ring : t_c_unb2b_board_tr := (2, 4, 0); -- per node: 2 buses with 12 channels (testing)
- constant c_unb2b_board_tr_qsfp : t_c_unb2b_board_tr := (6, 4, 6); -- per node: 6 buses with 4 channels
- constant c_unb2b_board_tr_jesd204b : t_c_unb2b_board_tr := (1, 12, 0); -- per node: 1 buses with 12 channels
- constant c_unb2b_board_nof_tr_jesd204b : natural := 6; -- Only 6 channels used in unb2b lab tests
- constant c_unb2b_board_start_tr_jesd204b : natural := 42; -- First transceiver used in unb2b lab tests
- constant c_unb2b_board_nof_sync_jesd204b : natural := 4; -- 4 channels used in unb2b lab tests, 1 for each RCU.
- constant c_unb2b_board_tr_qsfp_nof_leds : natural := c_unb2b_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
+ -- per node: 6 buses with 4 channels
+ constant c_unb2b_board_tr_qsfp : t_c_unb2b_board_tr := (6, 4, 6);
+ -- per node: 1 buses with 12 channels
+ constant c_unb2b_board_tr_jesd204b : t_c_unb2b_board_tr := (1, 12, 0);
+ -- Only 6 channels used in unb2b lab tests
+ constant c_unb2b_board_nof_tr_jesd204b : natural := 6;
+ -- First transceiver used in unb2b lab tests
+ constant c_unb2b_board_start_tr_jesd204b : natural := 42;
+ -- 4 channels used in unb2b lab tests, 1 for each RCU.
+ constant c_unb2b_board_nof_sync_jesd204b : natural := 4;
+ -- 2 leds per qsfp
+ constant c_unb2b_board_tr_qsfp_nof_leds : natural := c_unb2b_board_tr_qsfp.nof_bus * 2;
type t_unb2b_board_qsfp_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
type t_unb2b_board_ring_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2b_board_tr_ring.bus_w - 1 downto 0);
@@ -100,12 +128,18 @@ package unb2b_board_pkg is
-- Test IO Interface
type t_c_unb2b_board_testio is record
- tst_w : natural; -- = nof tst = 2; [tst_w-1 +tst_lo : tst_lo] = [5:4],
- led_w : natural; -- = nof led = 2; [led_w-1 +led_lo : led_lo] = [3:2],
- jmp_w : natural; -- = nof jmp = 2; [jmp_w-1 +jmp_lo : jmp_lo] = [1:0],
- tst_lo : natural; -- = 2;
- led_lo : natural; -- = 2;
- jmp_lo : natural; -- = 0;
+ -- = nof tst = 2; [tst_w-1 +tst_lo : tst_lo] = [5:4],
+ tst_w : natural;
+ -- = nof led = 2; [led_w-1 +led_lo : led_lo] = [3:2],
+ led_w : natural;
+ -- = nof jmp = 2; [jmp_w-1 +jmp_lo : jmp_lo] = [1:0],
+ jmp_w : natural;
+ -- = 2;
+ tst_lo : natural;
+ -- = 2;
+ led_lo : natural;
+ -- = 0;
+ jmp_lo : natural;
end record;
constant c_unb2b_board_testio : t_c_unb2b_board_testio := (2, 2, 2, 2, 2, 0);
@@ -113,10 +147,14 @@ package unb2b_board_pkg is
constant c_unb2b_board_testio_led_red : natural := c_unb2b_board_testio.led_lo + 1;
type t_c_unb2b_board_aux is record
- version_w : natural; -- = 2;
- id_w : natural; -- = 8; -- 6+2 bits wide = total node ID for up to 64 UniBoards in a system and 4 nodes per board
- chip_id_w : natural; -- = 2; -- board node ID for the 4 FPGA nodes on a UniBoard
- testio_w : natural; -- = 6;
+ -- = 2;
+ version_w : natural;
+ -- = 8; -- 6+2 bits wide = total node ID for up to 64 UniBoards in a system and 4 nodes per board
+ id_w : natural;
+ -- = 2; -- board node ID for the 4 FPGA nodes on a UniBoard
+ chip_id_w : natural;
+ -- = 6;
+ testio_w : natural;
testio : t_c_unb2b_board_testio;
end record;
@@ -125,8 +163,10 @@ package unb2b_board_pkg is
type t_e_unb2b_board_node is (e_any);
type t_unb2b_board_fw_version is record
- hi : natural; -- = 0..15
- lo : natural; -- = 0..15, firmware version is: hi.lo
+ -- = 0..15
+ hi : natural;
+ -- = 0..15, firmware version is: hi.lo
+ lo : natural;
end record;
constant c_unb2b_board_fw_version : t_unb2b_board_fw_version := (0, 0);
@@ -137,19 +177,27 @@ package unb2b_board_pkg is
-- . If no I2C bus arbitration or clock stretching is needed then the SCL only needs to be output.
-- . Can also be used for a PHY Management Data IO interface with serial clock MDC and serial data MDIO
type t_unb2b_board_i2c_inout is record
- scl : std_logic; -- serial clock
- sda : std_logic; -- serial data
+ -- serial clock
+ scl : std_logic;
+ -- serial data
+ sda : std_logic;
end record;
-- System info
type t_c_unb2b_board_system_info is record
- version : natural; -- UniBoard board HW version (2 bit value)
- id : natural; -- UniBoard FPGA node id (8 bit value)
+ -- UniBoard board HW version (2 bit value)
+ version : natural;
+ -- UniBoard FPGA node id (8 bit value)
+ id : natural;
-- Derived ID info:
- bck_id : natural; -- = id[7:2], ID part from back plane
- chip_id : natural; -- = id[1:0], ID part from UniBoard
- node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
- is_node2 : natural; -- 1 for Node 2, else 0.
+ -- = id[7:2], ID part from back plane
+ bck_id : natural;
+ -- = id[1:0], ID part from UniBoard
+ chip_id : natural;
+ -- = id[1:0], node ID: 0, 1, 2 or 3
+ node_id : natural;
+ -- 1 for Node 2, else 0.
+ is_node2 : natural;
end record;
function func_unb2b_board_system_info(VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
index c900196512ceae7f91f3fea9cbf0e2aba2b702cd..21d097218ad4e78fe45e7782fc94701f5bccb5c6 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
@@ -34,7 +34,8 @@ entity unb2b_board_pmbus_ctrl is
port (
rst : in std_logic;
clk : in std_logic;
- start : in std_logic; -- pulse to start the I2C sequence to read out the sensors
+ -- pulse to start the I2C sequence to read out the sensors
+ start : in std_logic;
out_dat : out std_logic_vector(c_byte_w - 1 downto 0);
out_val : out std_logic;
in_dat : in std_logic_vector(c_byte_w - 1 downto 0);
@@ -53,15 +54,18 @@ architecture rtl of unb2b_board_pmbus_ctrl is
-- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
-- Assume clk <= 200 MHz, so 5 ns period. Hence timeout of 4000 is enough.
- constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
+ -- wait 16 * 256 = 4096 clk periods
+ constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16);
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
+ -- RX supply
+ SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
+ -- TX supply
+ SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
index 08ffbbe35b61070253acda92abc2d44202345617..d13ebb29ce47b7cbbd7edc293273530a660d0a9a 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
@@ -66,10 +66,14 @@ use dp_lib.dp_stream_pkg.all;
entity unb2b_board_qsfp_leds is
generic (
- g_sim : boolean := false; -- when true speed up led toggling in simulation
- g_factory_image : boolean := false; -- distinguish factory image and user images
- g_nof_qsfp : natural := 6; -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us : natural := 200 -- nof clk cycles to get us period
+ -- when true speed up led toggling in simulation
+ g_sim : boolean := false;
+ -- distinguish factory image and user images
+ g_factory_image : boolean := false;
+ -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_nof_qsfp : natural := 6;
+ -- nof clk cycles to get us period
+ g_pulse_us : natural := 200
);
port (
rst : in std_logic;
@@ -89,8 +93,10 @@ entity unb2b_board_qsfp_leds is
end unb2b_board_qsfp_leds;
architecture str of unb2b_board_qsfp_leds is
- constant c_nof_ms : natural := sel_a_b(g_sim, 1, 100); -- force off for c_nof_ms and then on for at least c_nof_ms
- constant c_nof_lanes : natural := g_nof_qsfp * c_quad; -- number of transceiver lanes, fixed 4 per Quad-SFP cage
+ -- force off for c_nof_ms and then on for at least c_nof_ms
+ constant c_nof_ms : natural := sel_a_b(g_sim, 1, 100);
+ -- number of transceiver lanes, fixed 4 per Quad-SFP cage
+ constant c_nof_lanes : natural := g_nof_qsfp * c_quad;
signal i_pulse_ms : std_logic;
signal i_pulse_s : std_logic;
@@ -108,9 +114,12 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ -- nof clk cycles to get us period
+ g_pulse_us => g_pulse_us,
+ -- nof pulse_us pulses to get ms period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000),
+ -- nof pulse_ms pulses to get s period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000)
)
port map (
rst => rst,
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
index bdcc956341f6e19ac53b011b4d505c2928505a45..49c5fc2752f9e7ad5f6e58d2a7982253684d3d45 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
@@ -29,9 +29,11 @@ entity unb2b_board_sens is
generic (
g_sim : boolean := false;
g_i2c_peripheral : natural;
- g_clk_freq : natural := 100 * 10**6; -- clk frequency in Hz
+ -- clk frequency in Hz
+ g_clk_freq : natural := 100 * 10**6;
g_temp_high : natural := 85;
- g_sens_nof_result : natural; -- Should match nof read bytes via I2C in the unb2b_board_sens_ctrl SEQUENCE list
+ -- Should match nof read bytes via I2C in the unb2b_board_sens_ctrl SEQUENCE list
+ g_sens_nof_result : natural;
g_comma_w : natural := 0
);
port (
@@ -50,7 +52,8 @@ end entity;
architecture str of unb2b_board_sens is
-- I2C clock rate settings
- constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
+ -- define I2C clock rate
+ constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6));
--CONSTANT c_sens_comma_w : NATURAL := 13; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
-- 0 = no comma time
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
index 60b4028d32b6c4203b3485c3e4794d9ec058570d..f2675eae6233129d0f98619c7abfd6af4cc22b89 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
@@ -36,7 +36,8 @@ entity unb2b_board_sens_ctrl is
port (
rst : in std_logic;
clk : in std_logic;
- start : in std_logic; -- pulse to start the I2C sequence to read out the sensors
+ -- pulse to start the I2C sequence to read out the sensors
+ start : in std_logic;
out_dat : out std_logic_vector(c_byte_w - 1 downto 0);
out_val : out std_logic;
in_dat : in std_logic_vector(c_byte_w - 1 downto 0);
@@ -57,17 +58,23 @@ architecture rtl of unb2b_board_sens_ctrl is
constant TMP451_REM_HI : natural := 16#01#;
constant TMP451_REM_LO : natural := 16#10#;
- constant CAT24C02_ADR_00 : natural := 16#00#; -- should contain 'H'
- constant CAT24C02_ADR_01 : natural := 16#01#; -- should contain 'a'
- constant CAT24C02_ADR_02 : natural := 16#02#; -- should contain 'r'
- constant CAT24C02_ADR_03 : natural := 16#03#; -- should contain 'r'
- constant CAT24C02_ADR_04 : natural := 16#04#; -- should contain 'o'
+ -- should contain 'H'
+ constant CAT24C02_ADR_00 : natural := 16#00#;
+ -- should contain 'a'
+ constant CAT24C02_ADR_01 : natural := 16#01#;
+ -- should contain 'r'
+ constant CAT24C02_ADR_02 : natural := 16#02#;
+ -- should contain 'r'
+ constant CAT24C02_ADR_03 : natural := 16#03#;
+ -- should contain 'o'
+ constant CAT24C02_ADR_04 : natural := 16#04#;
type t_SEQUENCE is array (natural range <>) of natural;
-- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
-- Assume clk <= 200 MHz, so 5 ns period. Hence timeout of 4000 is enough.
- constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
+ -- wait 16 * 256 = 4096 clk periods
+ constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16);
constant c_SEQ : t_SEQUENCE := (
SMBUS_READ_BYTE , I2C_UNB2_SENS_EEPROM_CAT24C02_ADR, CAT24C02_ADR_00,
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
index b7b2e852c0b8c482d15b8331209b0a909f6a6721..f673b763b362d59a97559c177760b16cbcc8db64 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
@@ -72,12 +72,16 @@ entity unb2b_board_sens_reg is
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers
sens_err : in std_logic := '0';
@@ -91,12 +95,14 @@ end unb2b_board_sens_reg;
architecture rtl of unb2b_board_sens_reg is
-- Define the actual size of the MM slave register
- constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
+ -- +1 to fit user set temp_high one additional address
+ constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1;
-- +1 to fit sens_err in the last address
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_mm_nof_dat,
init_sl => '0');
@@ -139,14 +145,17 @@ begin
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
-- no need to capture sens_data, it is not critical if the sens_data happens to be read just before and after an I2C access occurred
if vA < g_sens_nof_result then
sla_out.rddata <= RESIZE_MEM_DATA(sens_data(vA)(c_byte_w - 1 downto 0));
elsif vA = g_sens_nof_result then
- sla_out.rddata(0) <= sens_err; -- only valid for node2
+ -- only valid for node2
+ sla_out.rddata(0) <= sens_err;
else
sla_out.rddata(6 downto 0) <= i_temp_high;
end if;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
index adf5baaffbd23aa5f2b97e2505c658967f120276..c03a6eae27e8e231d6843144de94d109c402cbef 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
@@ -33,8 +33,10 @@ use technology_lib.technology_pkg.all;
entity unb2b_board_system_info is
generic (
g_sim : boolean := false;
- g_fw_version : t_unb2b_board_fw_version := c_unb2b_board_fw_version; -- firmware version x.y (4b.4b)
- g_aux : t_c_unb2b_board_aux := c_unb2b_board_aux; -- aux contains the hardware version
+ -- firmware version x.y (4b.4b)
+ g_fw_version : t_unb2b_board_fw_version := c_unb2b_board_fw_version;
+ -- aux contains the hardware version
+ g_aux : t_c_unb2b_board_aux := c_unb2b_board_aux;
g_rom_version: natural := 1;
g_technology : natural := c_tech_arria10_e1sg
);
@@ -43,10 +45,14 @@ entity unb2b_board_system_info is
hw_version : in std_logic_vector(g_aux.version_w - 1 downto 0);
id : in std_logic_vector(g_aux.id_w - 1 downto 0);
info : out std_logic_vector(c_word_w - 1 downto 0);
- bck_id : out std_logic_vector(c_unb2b_board_nof_uniboard_w - 1 downto 0); -- ID[7:2]
- chip_id : out std_logic_vector(c_unb2b_board_nof_chip_w - 1 downto 0); -- ID[1:0]
- node_id : out std_logic_vector(c_unb2b_board_nof_node_w - 1 downto 0); -- ID[1:0]
- is_node2 : out std_logic -- '1' for Node 2, else '0'.
+ -- ID[7:2]
+ bck_id : out std_logic_vector(c_unb2b_board_nof_uniboard_w - 1 downto 0);
+ -- ID[1:0]
+ chip_id : out std_logic_vector(c_unb2b_board_nof_chip_w - 1 downto 0);
+ -- ID[1:0]
+ node_id : out std_logic_vector(c_unb2b_board_nof_node_w - 1 downto 0);
+ -- '1' for Node 2, else '0'.
+ is_node2 : out std_logic
);
end unb2b_board_system_info;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
index c3f5a857aa5ddf0586bf89976b5b8d5928120fdf..4e71b5b948907ab021b9bcef18a226d29e5467fc 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
@@ -72,11 +72,16 @@ entity unb2b_board_system_info_reg is
end unb2b_board_system_info_reg;
architecture rtl of unb2b_board_system_info_reg is
- constant c_nof_fixed_regs : natural := 2; -- info, use_phy
- constant c_nof_design_name_regs : natural := 13; -- design_name
- constant c_nof_stamp_regs : natural := 2; -- date, time
- constant c_nof_revision_id_regs : natural := 3; -- revision id, commit hash or id (hash: first 9 chars of the 40chars commit hash)
- constant c_nof_design_note_regs : natural := 12; -- note
+ -- info, use_phy
+ constant c_nof_fixed_regs : natural := 2;
+ -- design_name
+ constant c_nof_design_name_regs : natural := 13;
+ -- date, time
+ constant c_nof_stamp_regs : natural := 2;
+ -- revision id, commit hash or id (hash: first 9 chars of the 40chars commit hash)
+ constant c_nof_revision_id_regs : natural := 3;
+ -- note
+ constant c_nof_design_note_regs : natural := 12;
constant c_info_reg : natural := 0;
constant c_use_phy_reg : natural := 1;
@@ -85,15 +90,18 @@ architecture rtl of unb2b_board_system_info_reg is
constant c_stamp_time_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + 1;
constant c_revision_id_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
constant c_design_note_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
- constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs; -- = 2+13+2+3+12 = 32
+ -- = 2+13+2+3+12 = 32
+ constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs;
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_nof_regs,
init_sl => '0');
constant c_use_phy_w : natural := 8;
- constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
+ -- Unused but keep for compatibillity
+ constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0');
constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
constant c_revision_id : t_slv_32_arr(0 to c_nof_revision_id_regs - 1) := str_to_ascii_slv_32_arr(g_revision_id, c_nof_revision_id_regs);
@@ -111,8 +119,10 @@ begin
-- Read access: get register value
if sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
vA := TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0));
if vA = c_info_reg then
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
index 74ccf1459b4566fda04c42e9f0c7bcdac29ad01d..2a133a6b5b28d703572ed6712acfb7510d8f942f 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
@@ -37,7 +37,8 @@ entity unb2b_board_wdi_extend is
port (
rst : in std_logic;
clk : in std_logic;
- pulse_ms : in std_logic; -- pulses every 1 ms
+ -- pulses every 1 ms
+ pulse_ms : in std_logic;
wdi_in : in std_logic;
wdi_out : out std_logic
);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
index f052cbb7b21c950df7ca60ccab1ad3afb4019eac..010a0113d9dc10b74343d5f4838770d3bb10403d 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
@@ -31,12 +31,16 @@ use common_lib.common_mem_pkg.all;
entity unb2b_board_wdi_reg is
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
wdi_override : out std_logic
@@ -47,12 +51,14 @@ architecture rtl of unb2b_board_wdi_reg is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 1,
init_sl => '0');
-- For safety, WDI override requires the following word to be written:
- constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
+ -- "Boot factory"
+ constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7";
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -75,7 +81,8 @@ begin
else
wdi_override <= '0';
end if;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
index ef80a940f59a7650e4e52b4a9ea66389cf3ca932..573728b5484e5531b84be539ba959bdab3293807 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
@@ -40,7 +40,8 @@ use common_lib.tb_common_mem_pkg.all;
use work.unb2b_board_pkg.all;
architecture tb of tb_mms_unb2b_board_sens is
- constant c_sim : boolean := true; -- FALSE;
+ -- FALSE;
+ constant c_sim : boolean := true;
constant c_repeat : natural := 2;
constant c_clk_freq : natural := 100 * 10**6;
constant c_clk_period : time := (10**9 / c_clk_freq) * 1 ns;
@@ -48,19 +49,27 @@ architecture tb of tb_mms_unb2b_board_sens is
-- Model I2C sensor slaves as on the UniBoard
constant c_temp_high : natural := 85;
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard --> hot swap = 5010 mAmpere (167)
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard --> hot swap = 48000 mVolt (120)
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard --> hot swap = 5010 mAmpere (167)
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard --> hot swap = 48000 mVolt (120)
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
constant c_sens_nof_result : natural := 4 + 1;
- constant c_sens_expected : t_natural_arr(0 to c_sens_nof_result - 1) := (60, 40, 167, 120, 0); -- 4 bytes as read by c_SEQ in unb2b_board_sens_ctrl + sens_err
+ -- 4 bytes as read by c_SEQ in unb2b_board_sens_ctrl + sens_err
+ constant c_sens_expected : t_natural_arr(0 to c_sens_nof_result - 1) := (60, 40, 167, 120, 0);
signal tb_end : std_logic := '0';
signal clk : std_logic := '0';
@@ -81,15 +90,18 @@ begin
clk <= (not clk) or tb_end after c_clk_period / 2;
-- I2C bus
- scl <= 'H'; -- model I2C pull up
- sda <= 'H'; -- model I2C pull up, use '0' and '1' to verify sens_err
+ -- model I2C pull up
+ scl <= 'H';
+ -- model I2C pull up, use '0' and '1' to verify sens_err
+ sda <= 'H';
scl <= scl_stretch;
sens_clk_stretch : process (scl)
begin
if falling_edge(scl) then
- scl_stretch <= '0', 'Z' after 50 ns; -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ scl_stretch <= '0', 'Z' after 50 ns;
end if;
end process;
@@ -115,7 +127,8 @@ begin
-- read I2C result data
for I in 0 to c_sens_nof_result - 1 loop
- proc_mem_mm_bus_rd(I, clk, reg_miso, reg_mosi); -- read sens_data
+ -- read sens_data
+ proc_mem_mm_bus_rd(I, clk, reg_miso, reg_mosi);
end loop;
proc_common_wait_some_cycles(clk, 1000);
@@ -132,7 +145,8 @@ begin
-- Verify sensor data
p_verify : process
begin
- wait until rising_edge(clk); -- Added this line to avoid warning: (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+ -- Added this line to avoid warning: (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+ wait until rising_edge(clk);
proc_common_wait_until_high(clk, sens_val);
assert TO_UINT(sens_dat) = c_sens_expected(0) report "Wrong FPGA temperature value" severity ERROR;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
index df9a474f610174d3792ccb898670b46681356db3..016865bf7b6f5660f99c2cafdd4799114b64336f 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
@@ -34,7 +34,8 @@ entity tb_unb2b_board_clk125_pll is
end tb_unb2b_board_clk125_pll;
architecture tb of tb_unb2b_board_clk125_pll is
- constant c_ext_clk_period : time := 8 ns; -- 125 MHz
+ -- 125 MHz
+ constant c_ext_clk_period : time := 8 ns;
signal tb_end : std_logic := '0';
signal ext_clk : std_logic := '0';
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
index e0559528e8cc578ca11794aa41f5b15b09b1eb37..4074e356549a393a9bd63c45bb056cf5a1f42ec7 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
@@ -34,7 +34,8 @@ entity tb_unb2b_board_clk200_pll is
end tb_unb2b_board_clk200_pll;
architecture tb of tb_unb2b_board_clk200_pll is
- constant c_ext_clk_period : time := 5 ns; -- 200 MHz
+ -- 200 MHz
+ constant c_ext_clk_period : time := 5 ns;
constant c_clk_vec_w : natural := 6;
constant c_clk_div : natural := 32;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
index 02d31bf344c1f93ca78584062c1c502ce14416ea..708b372cd6086ef051e9526abff8700ab6ad0191 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
@@ -34,7 +34,8 @@ entity tb_unb2b_board_clk25_pll is
end tb_unb2b_board_clk25_pll;
architecture tb of tb_unb2b_board_clk25_pll is
- constant c_ext_clk_period : time := 40 ns; -- 25 MHz
+ -- 25 MHz
+ constant c_ext_clk_period : time := 40 ns;
signal tb_end : std_logic := '0';
signal ext_clk : std_logic := '0';
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
index 9f41504493b612ccd9a7bcfad71468dfb29e42f4..2306c0b278b29ba736eee52c5f4b88c92aaedb13 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
@@ -28,21 +28,30 @@ entity tb_unb2b_board_node_ctrl is
end tb_unb2b_board_node_ctrl;
architecture tb of tb_unb2b_board_node_ctrl is
- constant c_scale : natural := 100; -- scale to speed up simulation
+ -- scale to speed up simulation
+ constant c_scale : natural := 100;
- constant c_xo_clk_period : time := 1 us; -- 1 MHz XO, slow XO to speed up simulation
- constant c_mm_clk_period : time := c_xo_clk_period / 5; -- 5 MHz PLL output from XO reference
+ -- 1 MHz XO, slow XO to speed up simulation
+ constant c_xo_clk_period : time := 1 us;
+ -- 5 MHz PLL output from XO reference
+ constant c_mm_clk_period : time := c_xo_clk_period / 5;
constant c_mm_locked_time : time := 10 us;
- constant c_pulse_us : natural := 5; -- nof 5 MHz clk cycles to get us period
- constant c_pulse_ms : natural := 1000 / c_scale; -- nof pulse_us pulses to get ms period
- constant c_pulse_s : natural := 1000; -- nof pulse_ms pulses to get s period
+ -- nof 5 MHz clk cycles to get us period
+ constant c_pulse_us : natural := 5;
+ -- nof pulse_us pulses to get ms period
+ constant c_pulse_ms : natural := 1000 / c_scale;
+ -- nof pulse_ms pulses to get s period
+ constant c_pulse_s : natural := 1000;
- constant c_wdi_extend_w : natural := 14; -- extend wdi by about 2**(14-1)= 8 s (as defined by c_pulse_ms)
- constant c_wdi_period : time := 1000 ms; -- wdi toggle after c_wdi_period
+ -- extend wdi by about 2**(14-1)= 8 s (as defined by c_pulse_ms)
+ constant c_wdi_extend_w : natural := 14;
+ -- wdi toggle after c_wdi_period
+ constant c_wdi_period : time := 1000 ms;
-- Use c_sw_period=40000 ms to show that the c_wdi_extend_w=5 is not enough, the WD will kick in when the sw is off during reload
- constant c_sw_period : time := 40000 ms; -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
+ -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
+ constant c_sw_period : time := 40000 ms;
-- Use c_sw_period=10000 ms to show that the c_wdi_extend_w=5 is enough, the WD will not kick in when the sw is off during reload
--CONSTANT c_sw_period : TIME := 6000 ms; -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
@@ -65,10 +74,13 @@ begin
mm_clk <= not mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_locked_time;
- wdi <= not wdi after c_wdi_period / c_scale; -- wd interrupt
- sw <= not sw after c_sw_period / c_scale; -- sw active / reload
+ -- wd interrupt
+ wdi <= not wdi after c_wdi_period / c_scale;
+ -- sw active / reload
+ sw <= not sw after c_sw_period / c_scale;
- wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
+ -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
+ wdi_in <= wdi and sw;
dut : entity work.unb2b_board_node_ctrl
generic map (
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
index b7d1a8ba03c55658283f0d6f4d43cf20062e0114..11bfdc4dd5da1bcf966f42ea16c91642e0153e9d 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
@@ -140,10 +140,14 @@ begin
u_unb2b_factory_qsfp_leds : entity work.unb2b_board_qsfp_leds
generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ -- when true speed up led toggling in simulation
+ g_sim => true,
+ -- distinguish factory image and user images
+ g_factory_image => true,
+ -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_nof_qsfp => c_nof_qsfp,
+ -- nof clk cycles to get us period
+ g_pulse_us => c_nof_clk_per_us
)
port map (
rst => rst,
@@ -163,10 +167,14 @@ begin
u_unb2b_user_qsfp_leds : entity work.unb2b_board_qsfp_leds
generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ -- when true speed up led toggling in simulation
+ g_sim => true,
+ -- distinguish factory image and user images
+ g_factory_image => false,
+ -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_nof_qsfp => c_nof_qsfp,
+ -- nof clk cycles to get us period
+ g_pulse_us => c_nof_clk_per_us
)
port map (
rst => rst,
diff --git a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
index 615aa3863ad6316b754355c47b5b07308c4ef2cf..200459bcaa14b4492a07cd01cbc295915af02470 100644
--- a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
@@ -30,13 +30,18 @@ use technology_lib.technology_pkg.all;
entity unb2b_board_10gbe is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 1; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 1;
g_technology : natural := c_tech_arria10_e1sg;
g_nof_macs : natural;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
- g_tx_fifo_fill : natural := 10; -- Release tx packet only when sufficiently data is available,
- g_tx_fifo_size : natural := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
- g_rx_fifo_size : natural := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
+ -- Release tx packet only when sufficiently data is available,
+ g_tx_fifo_fill : natural := 10;
+ -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ g_tx_fifo_size : natural := 256;
+ -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ g_rx_fifo_size : natural := 256;
g_word_alignment_padding : boolean := false
);
port (
@@ -49,7 +54,8 @@ entity unb2b_board_10gbe is
reg_mac_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_mac_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi := c_mem_mosi_rst; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_eth10g_miso : out t_mem_miso;
reg_10gbase_r_24_mosi : in t_mem_mosi := c_mem_mosi_rst;
@@ -102,9 +108,12 @@ begin
port map (
-- Transceiver PLL reference clock
tr_ref_clk_644 => tr_ref_clk,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => tr_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => tr_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156,
-- MM interface
mm_rst => mm_rst,
diff --git a/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd b/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
index 40e4278b6c8442b5a18c6278b4780c03ef227fbe..423d736503bdb45351fa3538bd4a794a138e49d4 100644
--- a/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
+++ b/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
@@ -33,12 +33,16 @@ entity unb2c_led is
g_design_name : string := "unb2c_led";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e2sg;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0; -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0;
g_factory_image : boolean := true
);
port (
@@ -52,7 +56,8 @@ end unb2c_led;
architecture str of unb2c_led is
-- Firmware version x.y
constant c_fw_version : t_unb2c_board_fw_version := (2, 0);
- constant c_reset_len : natural := 40000; -- 4; -- >= c_meta_delay_len from common_pkg
+ -- 4; -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 40000;
constant c_mm_clk_freq : natural := c_unb2c_board_mm_clk_freq_50M;
-- System
@@ -95,14 +100,16 @@ begin
-- xo_ethclk = ETH_CLK
-----------------------------------------------------------------------------
- divclk <= clk200; -- ETH_CLK(1); -- use the ETH_CLK pin as xo_clk
+ -- ETH_CLK(1); -- use the ETH_CLK pin as xo_clk
+ divclk <= clk200;
leddiv <= r_TOGGLE_1HZ;
p_led : process (divclk) is
begin
if rising_edge(divclk) then
- if r_CNT_1HZ = c_CNT_1HZ - 1 then -- -1, since counter starts at 0
+ -- -1, since counter starts at 0
+ if r_CNT_1HZ = c_CNT_1HZ - 1 then
r_TOGGLE_1HZ <= not r_TOGGLE_1HZ;
r_CNT_1HZ <= 0;
else
@@ -115,7 +122,8 @@ begin
u_unb2c_board_clk200_pll : entity unb2c_board_lib.unb2c_board_clk200_pll
generic map (
- g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
+ -- FALSE, -- switch fpll or fixedpll
+ g_use_fpll => true,
g_technology => g_technology
)
port map (
@@ -124,22 +132,26 @@ begin
st_clk200 => clk200
);
- xo_ethclk <= ETH_CLK(0); -- use the ETH_CLK pin as xo_clk
+ -- use the ETH_CLK pin as xo_clk
+ xo_ethclk <= ETH_CLK(0);
u_common_areset_xo : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => xo_ethclk,
out_rst => xo_rst
);
u_unb2c_board_clk125_pll : entity unb2c_board_lib.unb2c_board_clk125_pll
generic map (
- g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
+ -- FALSE, -- switch fpll or fixedpll
+ g_use_fpll => true,
g_technology => g_technology
)
port map (
@@ -151,7 +163,8 @@ begin
u_unb2c_board_node_ctrl : entity unb2c_board_lib.unb2c_board_node_ctrl
generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us => c_mm_clk_freq / (10**6)
)
port map (
-- MM clock domain reset
@@ -163,7 +176,8 @@ begin
-- Pulses
mm_pulse_us => OPEN,
mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
+ -- could be used to toggle a LED
+ mm_pulse_s => mm_pulse_s
);
------------------------------------------------------------------------------
@@ -174,7 +188,8 @@ begin
u_extend : entity common_lib.common_pulse_extend
generic map (
- g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
+ -- (2^22) / 50e6 = 0.083886 th of 1 sec
+ g_extend_w => 22
)
port map (
rst => mm_rst,
@@ -204,7 +219,8 @@ begin
u_extend_10Hz : entity common_lib.common_pulse_extend
generic map (
- g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
+ -- (2^21) / 50e6 = 0.041943 th of 1 sec
+ g_extend_w => 21
)
port map (
rst => mm_rst,
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
index c93a01d6edde99eae874b1c13b9b5e3a6202a0e3..958d65989fd6b6b172b865d68fa6a8374bcb28ac 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
@@ -32,7 +32,8 @@ use work.qsys_unb2c_minimal_pkg.all;
entity mmm_unb2c_minimal is
generic (
- g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
+ -- FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
index 0d31242e088c49a836b4f27adaa586763bfc9338..90ed570e367b2e25a010ae14a120acb272317e58 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
@@ -29,119 +29,232 @@ package qsys_unb2c_minimal_pkg is
component qsys_unb2c_minimal is
port (
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ ram_scrap_reset_export : out std_logic;
+ -- export
+ ram_scrap_clk_export : out std_logic;
+ -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0);
+ -- export
+ ram_scrap_write_export : out std_logic;
+ -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_scrap_read_export : out std_logic;
+ -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X')
);
end component qsys_unb2c_minimal;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
index 87ec5850530b265c069f02e647273a4534d0804e..bcee35fb20ed04815b50e99e0d15caf763c53b46 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
@@ -33,22 +33,31 @@ entity unb2c_minimal is
g_design_name : string := "unb2c_minimal";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e2sg;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision id -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision id -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := true;
g_protect_addr_range: boolean := false
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -106,12 +115,16 @@ architecture str of unb2c_minimal is
-- eth1g
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- EPCS read
@@ -333,7 +346,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
diff --git a/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
index 5fc724c707fc437f308a4c839036bf3d318bfbc6..aa3bb5e4a9391745989cffc28f0aab61d27de973 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
@@ -53,23 +53,28 @@ use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
entity tb_unb2c_minimal is
generic (
g_design_name : string := "unb2c_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
+ -- UniBoard 0
+ g_sim_unb_nr : natural := 0;
+ -- Node 3
+ g_sim_node_nr : natural := 3
);
end tb_unb2c_minimal;
architecture tb of tb_unb2c_minimal is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb2c_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2c_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -95,11 +100,15 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
index b7c61245b6954414a2676567fe16525d2d3faf27..dec7d373850e19bd9885416b15782c1091aace06 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
@@ -31,20 +31,29 @@ entity unb2c_test_10GbE is
generic (
g_design_name : string := "unb2c_test_10GbE";
g_design_note : string := "10GbE: all QSFPs";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -57,9 +66,12 @@ entity unb2c_test_10GbE is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic; -- Clock 10GbE front (qsfp) and ring lines
- SB_CLK : in std_logic; -- Clock 10GbE back upper 24 lines
- BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic;
+ -- Clock 10GbE back upper 24 lines
+ SB_CLK : in std_logic;
+ -- Clock 10GbE back lower 24 lines
+ BCK_REF_CLK : in std_logic;
-- back transceivers
--BCK_RX : IN STD_LOGIC_VECTOR((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus)-1 downto 0);
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
index 55beabab75a339e670927d19901f167e8763a5b5..daa445e7fe38347717ffacbcd20c89760201d985 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
@@ -63,7 +63,8 @@ begin
pps <= not pps after 80 ns;
- eth_sgin <= eth_sgout; -- loopback eth0 and eth1
+ -- loopback eth0 and eth1
+ eth_sgin <= eth_sgout;
u_unb2c_test_1GbE_I : entity work.unb2c_test_1GbE_I
generic map (
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
index 14e29aca56f9ea10d188ec35f58018de0f5a4bc8..8307b5fff6af67255f92a1d252190b7bbe75f0c0 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
@@ -35,20 +35,29 @@ entity unb2c_test_1GbE_I is
generic (
g_design_name : string := "unb2c_test_1GbE_I";
g_design_note : string := "Uses only eth_0";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
index 0d481eb3274a34a366c02f8695af0bfb8629374b..e7e82d7a4d001a36eccd9e42c12a80c779724523 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
@@ -65,7 +65,8 @@ begin
pps <= not pps after 80 ns;
- eth_sgin <= eth_sgout; -- loopback eth0 and eth1
+ -- loopback eth0 and eth1
+ eth_sgin <= eth_sgout;
u_unb2c_test_1GbE_II : entity work.unb2c_test_1GbE_II
generic map (
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
index 850e616ac8d293cfa7d82aa9392fc18e0437cbd5..93fc41268272c26fcc926eaa9ba7dc0ce00a0e6e 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
@@ -35,20 +35,29 @@ entity unb2c_test_1GbE_II is
generic (
g_design_name : string := "unb2c_test_1GbE_II";
g_design_note : string := "Use eth_0 and eth_1";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
index b5b75bb185e1c4debb78015ca0aa15bec37c771b..cade045e850e4e593e67a0bbbc48fa3f23b372be 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
@@ -32,20 +32,29 @@ entity unb2c_test_ddr is
generic (
g_design_name : string := "unb2c_test_ddr";
g_design_note : string := "DDR: MB I and II";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -58,8 +67,10 @@ entity unb2c_test_ddr is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
- MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic;
+ -- Reference clock for MB_II
+ MB_II_REF_CLK : in std_logic;
-- SO-DIMM Memory Bank I
MB_I_IN : in t_tech_ddr4_phy_in;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
index a19523ddcae8447148730f2de4abdb640ebb17a9..cd7a2d585e6288a2fa298fe62d2c1e9d34a73b36 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
@@ -32,20 +32,29 @@ entity unb2c_test_ddr_16G is
generic (
g_design_name : string := "unb2c_test_ddr_16G";
g_design_note : string := "DDR: MB I and II";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -58,8 +67,10 @@ entity unb2c_test_ddr_16G is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
- MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic;
+ -- Reference clock for MB_II
+ MB_II_REF_CLK : in std_logic;
-- SO-DIMM Memory Bank I
MB_I_IN : in t_tech_ddr4_phy_in;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
index e85b07f9c188d7050e385628bf96c27e3700d884..127ea088dbc3f941c714de807bd15d6e2de01677 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
@@ -31,20 +31,29 @@ entity unb2c_test_heater is
generic (
g_design_name : string := "unb2c_test_heater";
g_design_note : string := "heater: none";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
index 3c61c0768039e3da09c4666f29d1e74d2652bf95..8e4368d9c4530b5d70d0d96b8ded9ae0acb2f592 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
@@ -31,20 +31,29 @@ entity unb2c_test_jesd204b is
generic (
g_design_name : string := "unb2c_test_jesd204b";
g_design_note : string := "jesd204b: none";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -57,7 +66,8 @@ entity unb2c_test_jesd204b is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- jesd204b
- BCK_REF_CLK : in std_logic; -- Clock 10GbE back. From external reference. To be used for JESD204B_REFCLK
+ -- Clock 10GbE back. From external reference. To be used for JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic;
BCK_RX : in std_logic_vector((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus) - 1 downto 0);
JESD204B_SYSREF : in std_logic;
JESD204B_SYNC : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
index 85260e0c01ed2df1c82ce1c1422f4a482294a140..3bef23c97509b9c89a8c38d6e71e83175952e7c1 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
@@ -31,20 +31,29 @@ entity unb2c_test_minimal is
generic (
g_design_name : string := "unb2c_test_minimal";
g_design_note : string := "niks";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := "" -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := ""
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index 468e48a1a4c0f2ce6ab7076a9494994d7bf54ba8..36b340c6830ef81c37a8a0b3d2cf93567554a484 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -42,7 +42,8 @@ use work.unb2c_test_pkg.all;
entity mmm_unb2c_test is
generic (
- g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
+ -- FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_technology : natural := c_tech_arria10_e1sg;
@@ -404,7 +405,8 @@ begin
proc_tech_tse_setup(c_tech_arria10_e1sg, false, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth_0_tse_miso, eth_0_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth_0_reg_miso, sim_eth_0_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth_0_reg_miso, sim_eth_0_reg_mosi);
sim_eth_mm_bus_switch <= '0';
wait;
@@ -869,7 +871,8 @@ begin
ram_diag_data_buffer_bsn_clk_export => OPEN,
ram_diag_data_buffer_bsn_reset_export => OPEN,
- ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(21 - 1 downto 0), -- 22 = ceil_log2(12 * 256k), so maximum possible data buffer size is 256 kSamples
+ -- 22 = ceil_log2(12 * 256k), so maximum possible data buffer size is 256 kSamples
+ ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(21 - 1 downto 0),
ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
index 082cb255033db9026064bf00a896cde6129207ff..947ddbe9dcd3dc165657931d0f0e876f17b34ed8 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
@@ -41,10 +41,13 @@ entity node_adc_input_and_timing_nowg is
generic (
g_technology : natural := c_tech_arria10_e2sg;
g_jesd_freq : string := "200MHz";
- g_buf_nof_data : natural := 131072; -- 8192; --1024;
+ -- 8192; --1024;
+ g_buf_nof_data : natural := 131072;
g_nof_streams : natural := 12;
- g_nof_sync_n : natural := c_unb2c_board_nof_sync_jesd204b; -- n ADCs per RCU share a sync
- g_bsn_sync_timeout : natural := 200000000; -- Default 200M, overide for short simulation
+ -- n ADCs per RCU share a sync
+ g_nof_sync_n : natural := c_unb2c_board_nof_sync_jesd204b;
+ -- Default 200M, overide for short simulation
+ g_bsn_sync_timeout : natural := 200000000;
g_sim : boolean := false
);
port (
@@ -93,13 +96,16 @@ architecture str of node_adc_input_and_timing_nowg is
init_sl => '0');
-- Frame parameters TBC
- constant c_bs_bsn_w : natural := 64; -- 51;
+ -- 51;
+ constant c_bs_bsn_w : natural := 64;
constant c_bs_block_size : natural := 1024;
- constant c_bs_nof_block_per_sync : natural := 390625; -- generate a sync every 2s for testing
+ -- generate a sync every 2s for testing
+ constant c_bs_nof_block_per_sync : natural := 390625;
constant c_data_w : natural := 16;
-- JESD signals
- signal rx_clk : std_logic; -- formerly jesd204b_frame_clk
+ -- formerly jesd204b_frame_clk
+ signal rx_clk : std_logic;
signal rx_rst : std_logic;
signal rx_sysref : std_logic;
@@ -216,7 +222,8 @@ begin
---------------------------------------------------------------------------------------
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
generic map (
- g_nof_streams => 1, -- They're all the same
+ -- They're all the same
+ g_nof_streams => 1,
g_sync_timeout => g_bsn_sync_timeout,
g_bsn_w => c_bs_bsn_w,
g_log_first_bsn => false
@@ -244,7 +251,8 @@ begin
g_nof_streams => g_nof_streams,
g_data_w => c_data_w,
g_buf_nof_data => g_buf_nof_data,
- g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ g_buf_use_sync => true
)
port map (
mm_rst => mm_rst_internal,
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
index ee430f809c65a58a0eec86b38732fef2f3d243ea..d302c105c450eadb881e3c8f6b6267ab7f51d907 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
@@ -25,442 +25,878 @@ use IEEE.std_logic_1164.all;
package qsys_unb2c_test_pkg is
component qsys_unb2c_test is
port (
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_1_reset_export : out std_logic; -- export
- avs_eth_1_clk_export : out std_logic; -- export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_tse_write_export : out std_logic; -- export
- avs_eth_1_tse_read_export : out std_logic; -- export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_1_reg_write_export : out std_logic; -- export
- avs_eth_1_reg_read_export : out std_logic; -- export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_ram_write_export : out std_logic; -- export
- avs_eth_1_ram_read_export : out std_logic; -- export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_eth_0_reset_export : out std_logic; -- export
- reg_diag_bg_eth_0_clk_export : out std_logic; -- export
- reg_diag_bg_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_bg_eth_0_write_export : out std_logic; -- export
- reg_diag_bg_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_eth_0_read_export : out std_logic; -- export
- reg_diag_bg_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_eth_1_reset_export : out std_logic; -- export
- reg_diag_bg_eth_1_clk_export : out std_logic; -- export
- reg_diag_bg_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_eth_1_write_export : out std_logic; -- export
- reg_diag_bg_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_eth_1_read_export : out std_logic; -- export
- reg_diag_bg_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back0_reset_export : out std_logic; -- export
- reg_eth10g_back0_clk_export : out std_logic; -- export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back0_write_export : out std_logic; -- export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back0_read_export : out std_logic; -- export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back1_reset_export : out std_logic; -- export
- reg_eth10g_back1_clk_export : out std_logic; -- export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back1_write_export : out std_logic; -- export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back1_read_export : out std_logic; -- export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_eth_1_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_1_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_1_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_tx_eth_1_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_1_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_1_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_eth_1_reset_export : out std_logic; -- export
- reg_hdr_dat_eth_1_clk_export : out std_logic; -- export
- reg_hdr_dat_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
- reg_hdr_dat_eth_1_write_export : out std_logic; -- export
- reg_hdr_dat_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_eth_1_read_export : out std_logic; -- export
- reg_hdr_dat_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_rx_eth_1_reset_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_clk_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
- reg_strobe_total_count_rx_eth_1_write_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_rx_eth_1_read_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_tx_eth_1_reset_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_clk_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
- reg_strobe_total_count_tx_eth_1_write_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_tx_eth_1_read_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_eth_0_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_0_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_0_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_tx_eth_0_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_0_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_0_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_eth_0_reset_export : out std_logic; -- export
- reg_hdr_dat_eth_0_clk_export : out std_logic; -- export
- reg_hdr_dat_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_eth_0_write_export : out std_logic; -- export
- reg_hdr_dat_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_eth_0_read_export : out std_logic; -- export
- reg_hdr_dat_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_rx_eth_0_reset_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_clk_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
- reg_strobe_total_count_rx_eth_0_write_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_rx_eth_0_read_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_tx_eth_0_reset_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_clk_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
- reg_strobe_total_count_tx_eth_0_write_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_tx_eth_0_read_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_reset_export : out std_logic; -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back0_write_export : out std_logic; -- export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back0_read_export : out std_logic; -- export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back1_write_export : out std_logic; -- export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back1_read_export : out std_logic; -- export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ -- export
+ avs_eth_0_reset_export : out std_logic;
+ -- export
+ avs_eth_0_clk_export : out std_logic;
+ -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_tse_write_export : out std_logic;
+ -- export
+ avs_eth_0_tse_read_export : out std_logic;
+ -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_0_reg_write_export : out std_logic;
+ -- export
+ avs_eth_0_reg_read_export : out std_logic;
+ -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_0_ram_write_export : out std_logic;
+ -- export
+ avs_eth_0_ram_read_export : out std_logic;
+ -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_0_irq_export : in std_logic := 'X';
+ -- export
+ avs_eth_1_reset_export : out std_logic;
+ -- export
+ avs_eth_1_clk_export : out std_logic;
+ -- export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_1_tse_write_export : out std_logic;
+ -- export
+ avs_eth_1_tse_read_export : out std_logic;
+ -- export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_1_tse_waitrequest_export : in std_logic := 'X';
+ -- export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ avs_eth_1_reg_write_export : out std_logic;
+ -- export
+ avs_eth_1_reg_read_export : out std_logic;
+ -- export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ avs_eth_1_ram_write_export : out std_logic;
+ -- export
+ avs_eth_1_ram_read_export : out std_logic;
+ -- export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ avs_eth_1_irq_export : in std_logic := 'X';
+ -- clk
+ clk_clk : in std_logic := 'X';
+ -- reset_n
+ reset_reset_n : in std_logic := 'X';
+ -- export
+ jesd204b_reset_export : out std_logic;
+ -- export
+ jesd204b_clk_export : out std_logic;
+ -- export
+ jesd204b_address_export : out std_logic_vector(11 downto 0);
+ -- export
+ jesd204b_write_export : out std_logic;
+ -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ jesd204b_read_export : out std_logic;
+ -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_jesd_ctrl_reset_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_clk_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ pio_jesd_ctrl_write_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_jesd_ctrl_read_export : out std_logic;
+ -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_pps_reset_export : out std_logic;
+ -- export
+ pio_pps_clk_export : out std_logic;
+ -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ pio_pps_write_export : out std_logic;
+ -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_pps_read_export : out std_logic;
+ -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_system_info_reset_export : out std_logic;
+ -- export
+ pio_system_info_clk_export : out std_logic;
+ -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ pio_system_info_write_export : out std_logic;
+ -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ pio_system_info_read_export : out std_logic;
+ -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ pio_wdi_external_connection_export : out std_logic;
+ -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic;
+ -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic;
+ -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0);
+ -- export
+ ram_diag_bg_10gbe_write_export : out std_logic;
+ -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_bg_10gbe_read_export : out std_logic;
+ -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0);
+ -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0);
+ -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0);
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0);
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_scrap_reset_export : out std_logic;
+ -- export
+ ram_scrap_clk_export : out std_logic;
+ -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0);
+ -- export
+ ram_scrap_write_export : out std_logic;
+ -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_scrap_read_export : out std_logic;
+ -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0);
+ -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_input_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0);
+ -- export
+ reg_bsn_monitor_input_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_input_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_scheduler_reset_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_clk_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_bsn_scheduler_write_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_scheduler_read_export : out std_logic;
+ -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_source_reset_export : out std_logic;
+ -- export
+ reg_bsn_source_clk_export : out std_logic;
+ -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_bsn_source_write_export : out std_logic;
+ -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_source_read_export : out std_logic;
+ -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_bg_10gbe_write_export : out std_logic;
+ -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_bg_10gbe_read_export : out std_logic;
+ -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_bg_eth_0_reset_export : out std_logic;
+ -- export
+ reg_diag_bg_eth_0_clk_export : out std_logic;
+ -- export
+ reg_diag_bg_eth_0_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_bg_eth_0_write_export : out std_logic;
+ -- export
+ reg_diag_bg_eth_0_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_bg_eth_0_read_export : out std_logic;
+ -- export
+ reg_diag_bg_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_bg_eth_1_reset_export : out std_logic;
+ -- export
+ reg_diag_bg_eth_1_clk_export : out std_logic;
+ -- export
+ reg_diag_bg_eth_1_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_bg_eth_1_write_export : out std_logic;
+ -- export
+ reg_diag_bg_eth_1_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_bg_eth_1_read_export : out std_logic;
+ -- export
+ reg_diag_bg_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0);
+ -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0);
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_ctrl_reset_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_clk_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_ctrl_write_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_ctrl_read_export : out std_logic;
+ -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_dpmm_data_reset_export : out std_logic;
+ -- export
+ reg_dpmm_data_clk_export : out std_logic;
+ -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_dpmm_data_write_export : out std_logic;
+ -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_dpmm_data_read_export : out std_logic;
+ -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_epcs_reset_export : out std_logic;
+ -- export
+ reg_epcs_clk_export : out std_logic;
+ -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_epcs_write_export : out std_logic;
+ -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_epcs_read_export : out std_logic;
+ -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_eth10g_back0_reset_export : out std_logic;
+ -- export
+ reg_eth10g_back0_clk_export : out std_logic;
+ -- export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_eth10g_back0_write_export : out std_logic;
+ -- export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_eth10g_back0_read_export : out std_logic;
+ -- export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_eth10g_back1_reset_export : out std_logic;
+ -- export
+ reg_eth10g_back1_clk_export : out std_logic;
+ -- export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0);
+ -- export
+ reg_eth10g_back1_write_export : out std_logic;
+ -- export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_eth10g_back1_read_export : out std_logic;
+ -- export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic;
+ -- export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic;
+ -- export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_eth10g_qsfp_ring_write_export : out std_logic;
+ -- export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_eth10g_qsfp_ring_read_export : out std_logic;
+ -- export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_rx_eth_1_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_eth_1_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_eth_1_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_bsn_monitor_v2_rx_eth_1_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_rx_eth_1_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_tx_eth_1_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_tx_eth_1_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_tx_eth_1_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_bsn_monitor_v2_tx_eth_1_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_tx_eth_1_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_hdr_dat_eth_1_reset_export : out std_logic;
+ -- export
+ reg_hdr_dat_eth_1_clk_export : out std_logic;
+ -- export
+ reg_hdr_dat_eth_1_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_hdr_dat_eth_1_write_export : out std_logic;
+ -- export
+ reg_hdr_dat_eth_1_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_hdr_dat_eth_1_read_export : out std_logic;
+ -- export
+ reg_hdr_dat_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_strobe_total_count_rx_eth_1_reset_export : out std_logic;
+ -- export
+ reg_strobe_total_count_rx_eth_1_clk_export : out std_logic;
+ -- export
+ reg_strobe_total_count_rx_eth_1_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_strobe_total_count_rx_eth_1_write_export : out std_logic;
+ -- export
+ reg_strobe_total_count_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_strobe_total_count_rx_eth_1_read_export : out std_logic;
+ -- export
+ reg_strobe_total_count_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_strobe_total_count_tx_eth_1_reset_export : out std_logic;
+ -- export
+ reg_strobe_total_count_tx_eth_1_clk_export : out std_logic;
+ -- export
+ reg_strobe_total_count_tx_eth_1_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_strobe_total_count_tx_eth_1_write_export : out std_logic;
+ -- export
+ reg_strobe_total_count_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_strobe_total_count_tx_eth_1_read_export : out std_logic;
+ -- export
+ reg_strobe_total_count_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_rx_eth_0_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_eth_0_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_eth_0_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_bsn_monitor_v2_rx_eth_0_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_rx_eth_0_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_bsn_monitor_v2_tx_eth_0_reset_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_tx_eth_0_clk_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_tx_eth_0_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_bsn_monitor_v2_tx_eth_0_write_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_bsn_monitor_v2_tx_eth_0_read_export : out std_logic;
+ -- export
+ reg_bsn_monitor_v2_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_hdr_dat_eth_0_reset_export : out std_logic;
+ -- export
+ reg_hdr_dat_eth_0_clk_export : out std_logic;
+ -- export
+ reg_hdr_dat_eth_0_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_hdr_dat_eth_0_write_export : out std_logic;
+ -- export
+ reg_hdr_dat_eth_0_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_hdr_dat_eth_0_read_export : out std_logic;
+ -- export
+ reg_hdr_dat_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_strobe_total_count_rx_eth_0_reset_export : out std_logic;
+ -- export
+ reg_strobe_total_count_rx_eth_0_clk_export : out std_logic;
+ -- export
+ reg_strobe_total_count_rx_eth_0_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_strobe_total_count_rx_eth_0_write_export : out std_logic;
+ -- export
+ reg_strobe_total_count_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_strobe_total_count_rx_eth_0_read_export : out std_logic;
+ -- export
+ reg_strobe_total_count_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_strobe_total_count_tx_eth_0_reset_export : out std_logic;
+ -- export
+ reg_strobe_total_count_tx_eth_0_clk_export : out std_logic;
+ -- export
+ reg_strobe_total_count_tx_eth_0_address_export : out std_logic_vector(6 downto 0);
+ -- export
+ reg_strobe_total_count_tx_eth_0_write_export : out std_logic;
+ -- export
+ reg_strobe_total_count_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_strobe_total_count_tx_eth_0_read_export : out std_logic;
+ -- export
+ reg_strobe_total_count_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_temp_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_fpga_temp_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_temp_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0);
+ -- export
+ reg_fpga_voltage_sens_write_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_fpga_voltage_sens_read_export : out std_logic;
+ -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_heater_reset_export : out std_logic;
+ -- export
+ reg_heater_clk_export : out std_logic;
+ -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0);
+ -- export
+ reg_heater_write_export : out std_logic;
+ -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_heater_read_export : out std_logic;
+ -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0);
+ -- export
+ reg_io_ddr_mb_i_write_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_io_ddr_mb_i_read_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0);
+ -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic;
+ -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_ctrl_reset_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_clk_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_ctrl_write_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_ctrl_read_export : out std_logic;
+ -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_mmdp_data_reset_export : out std_logic;
+ -- export
+ reg_mmdp_data_clk_export : out std_logic;
+ -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_mmdp_data_write_export : out std_logic;
+ -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_mmdp_data_read_export : out std_logic;
+ -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_remu_reset_export : out std_logic;
+ -- export
+ reg_remu_clk_export : out std_logic;
+ -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0);
+ -- export
+ reg_remu_write_export : out std_logic;
+ -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_remu_read_export : out std_logic;
+ -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0);
+ -- export
+ reg_tr_10gbe_back0_write_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_back0_read_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X';
+ -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0);
+ -- export
+ reg_tr_10gbe_back1_write_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_back1_read_export : out std_logic;
+ -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X';
+ -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic;
+ -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic;
+ -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0);
+ -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic;
+ -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic;
+ -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X';
+ -- export
+ reg_wdi_reset_export : out std_logic;
+ -- export
+ reg_wdi_clk_export : out std_logic;
+ -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0);
+ -- export
+ reg_wdi_write_export : out std_logic;
+ -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_wdi_read_export : out std_logic;
+ -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ rom_system_info_reset_export : out std_logic;
+ -- export
+ rom_system_info_clk_export : out std_logic;
+ -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0);
+ -- export
+ rom_system_info_write_export : out std_logic;
+ -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ rom_system_info_read_export : out std_logic;
+ -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X')
);
end component qsys_unb2c_test;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
index bb282b576aae33d6e609ccf03ed4bdd039a75566..d776ee551c434d9630ce0a146f7546d67b5d213f 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
@@ -61,9 +61,11 @@ entity udp_stream is
ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0);
-- blockgen mm
- reg_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- BG control register (one for all streams)
+ -- BG control register (one for all streams)
+ reg_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_diag_bg_miso : out t_mem_miso;
- ram_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream)
+ -- BG buffer RAM (one per stream)
+ ram_diag_bg_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_diag_bg_miso : out t_mem_miso;
reg_diag_tx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_diag_tx_seq_miso : out t_mem_miso;
@@ -102,8 +104,10 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
+ -- enable (disabled by default)
+ constant c_bg_ctrl : t_diag_block_gen := ('0',
+ -- enable_sync
+ '0',
TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
@@ -178,7 +182,8 @@ begin
reg_tx_seq_miso => reg_diag_tx_seq_miso
);
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
g_technology => g_technology,
@@ -318,9 +323,11 @@ begin
generic map (
g_technology => g_technology,
g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
+ -- g_data_w, --FIXME
+ g_data_w => 32,
g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
+ -- sync by reading last address of data buffer
+ g_buf_use_sync => false,
g_use_rx_seq => true
)
port map (
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index bed4ac8d3e09c468888fe4d8288a4d33e182a43e..8c9dba5a9ac713f7af81933a9b50e370f59ba229 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -43,23 +43,32 @@ entity unb2c_test is
g_design_name : string := "unb2c_test";
g_design_note : string := "UNUSED";
g_technology : natural := c_tech_arria10_e2sg;
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_sim_model_ddr : boolean := false;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : string := ""; -- revision ID -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- revision ID -- set by QSF
+ g_revision_id : string := "";
g_factory_image : boolean := false;
g_protect_addr_range: boolean := false
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
@@ -72,13 +81,18 @@ entity unb2c_test is
ETH_SGOUT : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
- SB_CLK : in std_logic := '0'; -- Clock 10GbE back. From on-board XTAL
- BCK_REF_CLK : in std_logic := '0'; -- Clock 10GbE back. From external reference. To be used for JESD204B_REFCLK
+ -- Clock 10GbE front (qsfp) and ring lines
+ SA_CLK : in std_logic := '0';
+ -- Clock 10GbE back. From on-board XTAL
+ SB_CLK : in std_logic := '0';
+ -- Clock 10GbE back. From external reference. To be used for JESD204B_REFCLK
+ BCK_REF_CLK : in std_logic := '0';
-- DDR reference clocks
- MB_I_REF_CLK : in std_logic := '0'; -- Reference clock for MB_I
- MB_II_REF_CLK : in std_logic := '0'; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ MB_I_REF_CLK : in std_logic := '0';
+ -- Reference clock for MB_II
+ MB_II_REF_CLK : in std_logic := '0';
-- back transceivers
BCK_RX : in std_logic_vector((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus) - 1 downto 0) := (others => '0');
@@ -132,8 +146,10 @@ architecture str of unb2c_test is
-- Revision controlled constants
constant c_revision_select : t_unb2c_test_config := func_sel_revision_rec(g_design_name);
constant c_use_loopback : boolean := c_revision_select.use_loopback;
- constant c_use_eth_0_UDP : boolean := c_revision_select.use_1GbE_I_UDP; -- Enable the UDP offload ports on 1GbE-I = eth_0, eth_0 is always enabled for control
- constant c_use_eth_1 : boolean := c_revision_select.use_1GbE_II; -- Enable the second 1GbE-II = eth_1
+ -- Enable the UDP offload ports on 1GbE-I = eth_0, eth_0 is always enabled for control
+ constant c_use_eth_0_UDP : boolean := c_revision_select.use_1GbE_I_UDP;
+ -- Enable the second 1GbE-II = eth_1
+ constant c_use_eth_1 : boolean := c_revision_select.use_1GbE_II;
constant c_use_10GbE_qsfp : boolean := c_revision_select.use_10GbE_qsfp;
constant c_use_10GbE_ring : boolean := c_revision_select.use_10GbE_ring;
constant c_use_10GbE_back0 : boolean := c_revision_select.use_10GbE_back0;
@@ -152,13 +168,20 @@ architecture str of unb2c_test is
constant c_nof_jesd204b : natural := c_unb2c_board_tr_jesd204b.nof_bus * c_unb2c_board_tr_jesd204b.bus_w;
-- 1GbE
- constant c_nof_udp_streams_eth_0 : natural := 4; -- <= c_eth_nof_udp_ports = 4, shared with M&C stream
- constant c_nof_udp_streams_eth_0_w : natural := 2; -- = true_log2(c_nof_udp_streams_eth_0), fixed reserve 2 bit extra MM address space
- constant c_nof_udp_streams_eth_1 : natural := 1; -- fixed 1 UDP stream, so no need for dp_mux
- constant c_nof_udp_streams_eth_1_w : natural := 0; -- = true_log2(c_nof_udp_streams_eth_1), fixed reserve no extra MM address space
- constant c_base_mac : std_logic_vector(32 - 1 downto 0) := c_eth_tester_eth_src_mac_47_16; -- = X"00228608"
- constant c_base_ip : std_logic_vector(16 - 1 downto 0) := c_eth_tester_ip_src_addr_31_16; -- = X"0A63"
- constant c_base_udp : std_logic_vector(8 - 1 downto 0) := c_eth_tester_udp_src_port_15_8; -- = X"E0"
+ -- <= c_eth_nof_udp_ports = 4, shared with M&C stream
+ constant c_nof_udp_streams_eth_0 : natural := 4;
+ -- = true_log2(c_nof_udp_streams_eth_0), fixed reserve 2 bit extra MM address space
+ constant c_nof_udp_streams_eth_0_w : natural := 2;
+ -- fixed 1 UDP stream, so no need for dp_mux
+ constant c_nof_udp_streams_eth_1 : natural := 1;
+ -- = true_log2(c_nof_udp_streams_eth_1), fixed reserve no extra MM address space
+ constant c_nof_udp_streams_eth_1_w : natural := 0;
+ -- = X"00228608"
+ constant c_base_mac : std_logic_vector(32 - 1 downto 0) := c_eth_tester_eth_src_mac_47_16;
+ -- = X"0A63"
+ constant c_base_ip : std_logic_vector(16 - 1 downto 0) := c_eth_tester_ip_src_addr_31_16;
+ -- = X"E0"
+ constant c_base_udp : std_logic_vector(8 - 1 downto 0) := c_eth_tester_udp_src_port_15_8;
-- 10GbE
constant c_nof_streams_qsfp : natural := sel_a_b(c_use_10GbE_qsfp,c_nof_qsfp,0);
@@ -172,15 +195,22 @@ architecture str of unb2c_test is
constant c_nof_ring_bus : natural := ceil_div(c_nof_streams_ring,c_unb2c_board_tr_ring.bus_w);
constant c_nof_back_bus : natural := ceil_div(c_nof_streams_back0,c_unb2c_board_tr_back.bus_w);
- constant c_data_w_32 : natural := c_eth_data_w; -- 1GbE
- constant c_data_w_64 : natural := c_xgmii_data_w; -- 10GbE
+ -- 1GbE
+ constant c_data_w_32 : natural := c_eth_data_w;
+ -- 10GbE
+ constant c_data_w_64 : natural := c_xgmii_data_w;
-- ddr
- constant c_ddr_ctlr_data_w : natural := func_tech_ddr_ctlr_data_w(c_ddr_MB_I); -- = 576, assume both MB_I and MB_II use the same ctlr_data_w
- constant c_ddr_dp_data_w : natural := c_ddr_ctlr_data_w / 4; -- DDR4 with dq_w = 72, rsl = 8 so ctrl data width = 576 and therefore the mixed width FIFO ratio is 576 /144 = 4
- constant c_ddr_dp_seq_dat_w : natural := 16; -- >= 1, test sequence data width. Choose c_ddr_dp_seq_dat_w <= c_ddr_dp_data_w. The seq data gets replicated to fill c_ddr_dp_data_w.
- constant c_ddr_dp_wr_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w); -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) to make full use of M9K which have at least 256 words
- constant c_ddr_dp_rd_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w); -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) or factors of 2 more to fit max number of read bursts
+ -- = 576, assume both MB_I and MB_II use the same ctlr_data_w
+ constant c_ddr_ctlr_data_w : natural := func_tech_ddr_ctlr_data_w(c_ddr_MB_I);
+ -- DDR4 with dq_w = 72, rsl = 8 so ctrl data width = 576 and therefore the mixed width FIFO ratio is 576 /144 = 4
+ constant c_ddr_dp_data_w : natural := c_ddr_ctlr_data_w / 4;
+ -- >= 1, test sequence data width. Choose c_ddr_dp_seq_dat_w <= c_ddr_dp_data_w. The seq data gets replicated to fill c_ddr_dp_data_w.
+ constant c_ddr_dp_seq_dat_w : natural := 16;
+ -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) to make full use of M9K which have at least 256 words
+ constant c_ddr_dp_wr_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w);
+ -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) or factors of 2 more to fit max number of read bursts
+ constant c_ddr_dp_rd_fifo_depth : natural := 256 * (c_ddr_ctlr_data_w / c_ddr_dp_data_w);
constant c_ddr_db_buf_nof_data : natural := 1024;
constant c_ddr_mixed_width_ratio : natural := ratio2(c_ddr_ctlr_data_w, c_ddr_dp_data_w);
@@ -188,10 +218,12 @@ architecture str of unb2c_test is
constant c_bg_block_size : natural := 900;
constant c_bg_gapsize_1GbE : natural := 1000;
constant c_bg_gapsize_10GbE : natural := 100;
- constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
+ -- 200000*(900+100) = 200000000 cycles = 1 second
+ constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000);
constant c_use_jumbo_frames : boolean := false;
- constant c_def_10GbE_block_size : natural := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
+ -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
+ constant c_def_10GbE_block_size : natural := 700;
constant c_max_frame_len : natural := sel_a_b(c_use_jumbo_frames, 9018, 1518);
constant c_nof_header_bytes : natural := field_slv_len(c_hdr_field_arr) / c_byte_w;
@@ -257,17 +289,22 @@ architecture str of unb2c_test is
-- eth1g ch0
signal eth_0_mm_rst : std_logic;
- signal eth_0_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth_0_tse_mosi : t_mem_mosi;
signal eth_0_tse_miso : t_mem_miso;
- signal eth_0_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth_0_reg_mosi : t_mem_mosi;
signal eth_0_reg_miso : t_mem_miso;
- signal eth_0_reg_interrupt : std_logic; -- Interrupt
- signal eth_0_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth_0_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth_0_ram_mosi : t_mem_mosi;
signal eth_0_ram_miso : t_mem_miso;
-- eth1g ch1 (eth_stream only has MM for TSE MAC)
signal eth_1_mm_rst : std_logic;
- signal eth_1_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth_1_tse_mosi : t_mem_mosi;
signal eth_1_tse_miso : t_mem_miso;
-- EPCS read
@@ -354,34 +391,46 @@ architecture str of unb2c_test is
-- 1GbE I eth_tester (c_nof_udp_streams_eth_0_w = 2 bit)
-- . Tx
- signal reg_diag_bg_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_diag_bg_reg_adr_w = 3 --> w = 5
+ -- c_diag_bg_reg_adr_w = 3 --> w = 5
+ signal reg_diag_bg_eth_0_copi : t_mem_copi := c_mem_copi_rst;
signal reg_diag_bg_eth_0_cipo : t_mem_cipo;
- signal reg_hdr_dat_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 7
+ -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 7
+ signal reg_hdr_dat_eth_0_copi : t_mem_copi := c_mem_copi_rst;
signal reg_hdr_dat_eth_0_cipo : t_mem_cipo;
- signal reg_bsn_monitor_v2_tx_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
+ -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
+ signal reg_bsn_monitor_v2_tx_eth_0_copi : t_mem_copi := c_mem_copi_rst;
signal reg_bsn_monitor_v2_tx_eth_0_cipo : t_mem_cipo;
- signal reg_strobe_total_count_tx_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
+ -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
+ signal reg_strobe_total_count_tx_eth_0_copi : t_mem_copi := c_mem_copi_rst;
signal reg_strobe_total_count_tx_eth_0_cipo : t_mem_cipo;
-- . Rx
- signal reg_bsn_monitor_v2_rx_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
+ -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
+ signal reg_bsn_monitor_v2_rx_eth_0_copi : t_mem_copi := c_mem_copi_rst;
signal reg_bsn_monitor_v2_rx_eth_0_cipo : t_mem_cipo;
- signal reg_strobe_total_count_rx_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
+ -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
+ signal reg_strobe_total_count_rx_eth_0_copi : t_mem_copi := c_mem_copi_rst;
signal reg_strobe_total_count_rx_eth_0_cipo : t_mem_cipo;
-- 1GbE II eth_tester (c_nof_udp_streams_eth_1_w = 0 bit)
-- . Tx
- signal reg_diag_bg_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_diag_bg_reg_adr_w = 3 --> w = 3
+ -- c_diag_bg_reg_adr_w = 3 --> w = 3
+ signal reg_diag_bg_eth_1_copi : t_mem_copi := c_mem_copi_rst;
signal reg_diag_bg_eth_1_cipo : t_mem_cipo;
- signal reg_hdr_dat_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 5
+ -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 5
+ signal reg_hdr_dat_eth_1_copi : t_mem_copi := c_mem_copi_rst;
signal reg_hdr_dat_eth_1_cipo : t_mem_cipo;
- signal reg_bsn_monitor_v2_tx_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
+ -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
+ signal reg_bsn_monitor_v2_tx_eth_1_copi : t_mem_copi := c_mem_copi_rst;
signal reg_bsn_monitor_v2_tx_eth_1_cipo : t_mem_cipo;
- signal reg_strobe_total_count_tx_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
+ -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
+ signal reg_strobe_total_count_tx_eth_1_copi : t_mem_copi := c_mem_copi_rst;
signal reg_strobe_total_count_tx_eth_1_cipo : t_mem_cipo;
-- . Rx
- signal reg_bsn_monitor_v2_rx_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
+ -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
+ signal reg_bsn_monitor_v2_rx_eth_1_copi : t_mem_copi := c_mem_copi_rst;
signal reg_bsn_monitor_v2_rx_eth_1_cipo : t_mem_cipo;
- signal reg_strobe_total_count_rx_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
+ -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
+ signal reg_strobe_total_count_rx_eth_1_copi : t_mem_copi := c_mem_copi_rst;
signal reg_strobe_total_count_rx_eth_1_cipo : t_mem_cipo;
-- 10GbE
@@ -483,7 +532,8 @@ begin
g_mm_clk_freq => c_mm_clk_freq,
g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
g_aux => c_unb2c_board_aux,
- g_base_ip => c_base_ip, -- = X"0A63" is base IP address used by unb_osy: 10.99.xx.yy
+ -- = X"0A63" is base IP address used by unb_osy: 10.99.xx.yy
+ g_base_ip => c_base_ip,
g_udp_offload => c_use_eth_0_UDP,
g_udp_offload_nof_streams => c_nof_udp_streams_eth_0,
g_factory_image => g_factory_image,
@@ -803,8 +853,10 @@ begin
u_eth_tester_I : entity eth_lib.eth_tester
generic map (
g_nof_streams => c_nof_udp_streams_eth_0,
- g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
- g_remove_crc => true -- use TRUE when using TSE link interface
+ -- BG sync interval < 11 s
+ g_bg_sync_timeout => c_eth_tester_sync_timeout,
+ -- use TRUE when using TSE link interface
+ g_remove_crc => true
)
port map (
-- Clocks and reset
@@ -860,8 +912,10 @@ begin
u_eth_tester_II : entity eth_lib.eth_tester
generic map (
g_nof_streams => c_nof_udp_streams_eth_1,
- g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
- g_remove_crc => true -- use TRUE when using TSE link interface
+ -- BG sync interval < 11 s
+ g_bg_sync_timeout => c_eth_tester_sync_timeout,
+ -- use TRUE when using TSE link interface
+ g_remove_crc => true
)
port map (
-- Clocks and reset
@@ -906,14 +960,17 @@ begin
u_eth_stream : entity eth_lib.eth_stream
generic map (
g_technology => g_technology,
- g_rx_udp_port => TO_UINT(c_eth_rx_udp_port), -- = 0x1771 = 6001
+ -- = 0x1771 = 6001
+ g_rx_udp_port => TO_UINT(c_eth_rx_udp_port),
g_jumbo_en => true,
g_sim => g_sim,
- g_sim_level => 1 -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
+ -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
+ g_sim_level => 1
)
port map (
-- Clocks and reset
- mm_rst => mm_rst, -- eth_1_mm_rst
+ -- eth_1_mm_rst
+ mm_rst => mm_rst,
mm_clk => mm_clk,
eth_clk => ETH_CLK(1),
st_rst => dp_rst,
@@ -1035,7 +1092,8 @@ begin
end generate;
gen_front_10GbE : if c_use_10GbE = true generate
- u_tr_10GbE_qsfp_and_ring: entity unb2c_board_10gbe_lib.unb2c_board_10gbe -- QSFP and Ring lines
+ -- QSFP and Ring lines
+ u_tr_10GbE_qsfp_and_ring: entity unb2c_board_10gbe_lib.unb2c_board_10gbe
generic map (
g_sim => g_sim,
g_sim_level => 1,
@@ -1116,7 +1174,8 @@ begin
u_ring_io : entity unb2c_board_lib.unb2c_board_ring_io
generic map (
- g_nof_ring_bus => 2 -- c_nof_ring_bus
+ -- c_nof_ring_bus
+ g_nof_ring_bus => 2
)
port map (
serial_tx_arr => serial_10G_tx_ring_arr,
@@ -1126,7 +1185,8 @@ begin
);
gen_10gbe_back0 : if c_use_10GbE_back0 = true generate
- u_tr_10GbE_back: entity unb2c_board_10gbe_lib.unb2c_board_10gbe -- BACK lines (upper)
+ -- BACK lines (upper)
+ u_tr_10GbE_back: entity unb2c_board_10gbe_lib.unb2c_board_10gbe
generic map (
g_sim => g_sim,
g_sim_level => 1,
@@ -1202,7 +1262,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2c_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_unb2c_board_ext_clk_freq_200M)
)
port map (
rst => dp_rst,
@@ -1241,7 +1302,8 @@ begin
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- nof clk cycles to get us period
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq)
)
port map (
rst => mm_rst,
@@ -1274,7 +1336,8 @@ begin
-- DIAG data buffer
g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ -- nof words per data buffer
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data
)
port map (
---------------------------------------------------------------------------
@@ -1283,7 +1346,8 @@ begin
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+ -- use alternative external clock or externally connect to ctlr_clk_out
+ dp_clk => dp_clk,
---------------------------------------------------------------------------
-- IO_DDR
@@ -1296,11 +1360,14 @@ begin
ctlr_clk_out => ddr_I_clk200,
ctlr_rst_out => ddr_I_rst200,
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+ -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_clk_in => ddr_I_clk200,
+ -- connect ctlr_rst_out to ctlr_rst_in at top level
+ ctlr_rst_in => ddr_I_rst200,
-- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ -- register for DDR controller status info
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi,
reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-- Write / read FIFO status for monitoring purposes (in dp_clk domain)
@@ -1351,7 +1418,8 @@ begin
-- DIAG data buffer
g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ -- nof words per data buffer
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data
)
port map (
---------------------------------------------------------------------------
@@ -1360,7 +1428,8 @@ begin
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+ -- use alternative external clock or externally connect to ctlr_clk_out
+ dp_clk => dp_clk,
---------------------------------------------------------------------------
-- IO_DDR
@@ -1373,11 +1442,14 @@ begin
ctlr_clk_out => ddr_II_clk200,
ctlr_rst_out => ddr_II_rst200,
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+ -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_clk_in => ddr_II_clk200,
+ -- connect ctlr_rst_out to ctlr_rst_in at top level
+ ctlr_rst_in => ddr_II_rst200,
-- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ -- register for DDR controller status info
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi,
reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-- Write / read FIFO status for monitoring purposes (in dp_clk domain)
@@ -1421,10 +1493,13 @@ begin
--g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
g_nof_mac4 => 750,
- g_pipeline => 72, -- max 72
- g_nof_ram => 4, -- max 4
+ -- max 72
+ g_pipeline => 72,
+ -- max 4
+ g_nof_ram => 4,
- g_nof_logic => 24 -- max 24
+ -- max 24
+ g_nof_logic => 24
)
port map (
mm_rst => mm_rst,
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
index ecd624929ce531db8a1ed03d113ce557689377f7..0ffa420e694c2b4a63d48f7c3bca32e20d9d219e 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
@@ -31,15 +31,18 @@ use tech_ddr_lib.tech_ddr_pkg.all;
package unb2c_test_pkg is
-- dp_offload_tx (carried over from unb2a_test_pkg
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
- constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ -- Total header bits = 384 = 6 64b words
+ constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2;
+ -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
@@ -50,7 +53,8 @@ package unb2c_test_pkg is
( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
@@ -62,9 +66,12 @@ package unb2c_test_pkg is
-----------------------------------------------------------------------------
type t_unb2c_test_config is record
- use_loopback : boolean; -- for pinning designs
- use_1GbE_I_UDP : boolean; -- Use the UDP offload on eth0. Eth0 is always enabled for control
- use_1GbE_II : boolean; -- Intantiate eth1 for pinning designs
+ -- for pinning designs
+ use_loopback : boolean;
+ -- Use the UDP offload on eth0. Eth0 is always enabled for control
+ use_1GbE_I_UDP : boolean;
+ -- Intantiate eth1 for pinning designs
+ use_1GbE_II : boolean;
use_10GbE_qsfp : boolean;
use_10GbE_ring : boolean;
use_10GbE_back0 : boolean;
diff --git a/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
index a34e6633db99ec9a06cab4d836db5f2030d95324..2943d9344a0e8346c247eb803b061d5d6bca6142 100644
--- a/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
@@ -61,24 +61,34 @@ end tb_unb2c_test;
architecture tb of tb_unb2c_test is
constant c_sim : boolean := true;
- constant c_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
- constant c_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
-
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Node 3
+ -- DDR4 has no master or slave, so no need to check number of MB
+ constant c_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
+ -- DDR4 has no master or slave, so no need to check number of MB
+ constant c_ddr_MB_II : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
+
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb2c_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2c_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb2c_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz XO on UniBoard
+ -- 125 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 8 ns;
constant c_clk_period : time := 5 ns;
- constant c_sa_clk_period : time := tech_pll_clk_644_period; -- 644 MHz
- constant c_sb_clk_period : time := tech_pll_clk_644_period; -- 644 MHz
- constant c_bck_ref_clk_period : time := tech_pll_clk_644_period; -- 644 MHz
- constant c_mb_I_ref_clk_period : time := 40 ns; -- 25 MHz
- constant c_mb_II_ref_clk_period : time := 40 ns; -- 25 MHz
+ -- 644 MHz
+ constant c_sa_clk_period : time := tech_pll_clk_644_period;
+ -- 644 MHz
+ constant c_sb_clk_period : time := tech_pll_clk_644_period;
+ -- 644 MHz
+ constant c_bck_ref_clk_period : time := tech_pll_clk_644_period;
+ -- 25 MHz
+ constant c_mb_I_ref_clk_period : time := 40 ns;
+ -- 25 MHz
+ constant c_mb_II_ref_clk_period : time := 40 ns;
constant c_pps_period : natural := 1000;
-- DUT
@@ -101,8 +111,10 @@ architecture tb of tb_unb2c_test is
signal qsfp_led : std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- DDR reference clocks
- signal mb_I_ref_clk : std_logic := '1'; -- Reference clock for MB_I
- signal mb_II_ref_clk : std_logic := '1'; -- Reference clock for MB_II
+ -- Reference clock for MB_I
+ signal mb_I_ref_clk : std_logic := '1';
+ -- Reference clock for MB_II
+ signal mb_II_ref_clk : std_logic := '1';
-- DDR4 PHY interface
signal MB_I_IN : t_tech_ddr4_phy_in;
@@ -134,17 +146,27 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- eth_clk(1) <= not eth_clk(1) after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
- sa_clk <= not sa_clk after c_sa_clk_period / 2; -- Serial Gigabit IO sa clock (644 MHz)
- sb_clk <= not sb_clk after c_sb_clk_period / 2; -- Serial Gigabit IO sb clock (644 MHz)
- bck_ref_clk <= not bck_ref_clk after c_bck_ref_clk_period / 2; -- Serial Gigabit IO bck_ref clock (644 MHz)
- mb_I_ref_clk <= not mb_I_ref_clk after c_mb_I_ref_clk_period / 2; -- MB I reference clock (25 MHz)
- mb_II_ref_clk <= not mb_II_ref_clk after c_mb_II_ref_clk_period / 2; -- MB II reference clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= not eth_clk(0) after c_eth_clk_period / 2;
+ -- Ethernet ref clock (125 MHz)
+ eth_clk(1) <= not eth_clk(1) after c_eth_clk_period / 2;
+ -- Serial Gigabit IO sa clock (644 MHz)
+ sa_clk <= not sa_clk after c_sa_clk_period / 2;
+ -- Serial Gigabit IO sb clock (644 MHz)
+ sb_clk <= not sb_clk after c_sb_clk_period / 2;
+ -- Serial Gigabit IO bck_ref clock (644 MHz)
+ bck_ref_clk <= not bck_ref_clk after c_bck_ref_clk_period / 2;
+ -- MB I reference clock (25 MHz)
+ mb_I_ref_clk <= not mb_I_ref_clk after c_mb_I_ref_clk_period / 2;
+ -- MB II reference clock (25 MHz)
+ mb_II_ref_clk <= not mb_II_ref_clk after c_mb_II_ref_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index 74bc5570a961ed53b0fcd6feed3601bfff152d3f..4a4bb157811fd6615947bcdae99041aa0c24971f 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -43,15 +43,20 @@ entity ctrl_unb2c_board is
----------------------------------------------------------------------------
g_technology : natural := c_tech_arria10_e2sg;
g_sim : boolean := false;
- g_sim_level : natural := 1; -- 0 = use IP; 1 = use fast serdes model;
- g_sim_mm_clk_period : time := 10 ns; -- use e.g. c_mmf_mm_clk_period for MM bus file IO model, use e.g. 10 ns for MM access with TSE MAC IP
+ -- 0 = use IP; 1 = use fast serdes model;
+ g_sim_level : natural := 1;
+ -- use e.g. c_mmf_mm_clk_period for MM bus file IO model, use e.g. 10 ns for MM access with TSE MAC IP
+ g_sim_mm_clk_period : time := 10 ns;
g_design_name : string := "UNUSED";
- g_fw_version : t_unb2c_board_fw_version := (0, 0); -- firmware version x.y
+ -- firmware version x.y
+ g_fw_version : t_unb2c_board_fw_version := (0, 0);
g_stamp_date : natural := 0;
g_stamp_time : natural := 0;
- g_revision_id : string := ""; -- revision_id, commit hash (first 9 chars) or number
+ -- revision_id, commit hash (first 9 chars) or number
+ g_revision_id : string := "";
g_design_note : string := "UNUSED";
- g_base_ip : std_logic_vector(16 - 1 downto 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy
+ -- Base IP address used by unb_osy: 10.99.xx.yy
+ g_base_ip : std_logic_vector(16 - 1 downto 0) := X"0A63";
g_mm_clk_freq : natural := c_unb2c_board_mm_clk_freq_125M;
g_eth_clk_freq : natural := c_unb2c_board_eth_clk_freq_125M;
g_tse_clk_buf : boolean := false;
@@ -95,7 +100,8 @@ entity ctrl_unb2c_board is
-- STRING := "4688" = 3750+ 938 = 337.5
-- STRING := "4844" = 3750+1094 = 348.75
-- STRING := "5000" = 3750+1250 = 360
- g_dp_clk_phase : string := "0"; -- phase offset for PLL c0, typically any phase is fine, do not use 225 +-30 degrees because there the PPS edge occurs
+ -- phase offset for PLL c0, typically any phase is fine, do not use 225 +-30 degrees because there the PPS edge occurs
+ g_dp_clk_phase : string := "0";
----------------------------------------------------------------------------
-- 1GbE UDP offload
@@ -107,14 +113,18 @@ entity ctrl_unb2c_board is
-- Auxiliary Interface
----------------------------------------------------------------------------
g_fpga_temp_high : natural := 100;
- g_app_led_red : boolean := false; -- when TRUE use external LED control via app_led_red
- g_app_led_green : boolean := false; -- when TRUE use external LED control via app_led_green
+ -- when TRUE use external LED control via app_led_red
+ g_app_led_red : boolean := false;
+ -- when TRUE use external LED control via app_led_green
+ g_app_led_green : boolean := false;
g_aux : t_c_unb2c_board_aux := c_unb2c_board_aux;
g_factory_image : boolean := false;
g_protect_addr_range: boolean := false;
- g_protected_addr_lo : natural := 0; -- Byte address
- g_protected_addr_hi : natural := 41943039 -- Byte address, for UniBoard1 this is 640 sectors*256 pages*256 bytes -1 = 41943039
+ -- Byte address
+ g_protected_addr_lo : natural := 0;
+ -- Byte address, for UniBoard1 this is 640 sectors*256 pages*256 bytes -1 = 41943039
+ g_protected_addr_hi : natural := 41943039
);
port (
--
@@ -123,33 +133,49 @@ entity ctrl_unb2c_board is
-- System
cs_sim : out std_logic;
- xo_ethclk : out std_logic; -- 125 MHz ETH_CLK
- xo_rst : out std_logic; -- reset in ETH_CLK domain released after few cycles
+ -- 125 MHz ETH_CLK
+ xo_ethclk : out std_logic;
+ -- reset in ETH_CLK domain released after few cycles
+ xo_rst : out std_logic;
xo_rst_n : out std_logic;
- ext_clk200 : out std_logic; -- 200 MHz CLK
- ext_rst200 : out std_logic; -- reset in CLK clock domain released after mm_rst
-
- mm_clk : out std_logic; -- MM clock from xo_ethclk PLL
- mm_rst : out std_logic; -- reset in MM clock domain released after xo_ethclk PLL locked
-
- dp_rst : out std_logic; -- reset in DP clock domain released after mm_rst and after CLK PLL locked in case g_dp_clk_use_pll=TRUE
- dp_clk : out std_logic; -- 200 MHz DP clock from CLK system clock direct or via CLK PLL dependent on g_dp_clk_use_pll
- dp_pps : out std_logic; -- PPS in dp_clk domain
- dp_rst_in : in std_logic; -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
- dp_clk_in : in std_logic; -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
-
- mb_I_ref_rst : out std_logic; -- reset in MB_I_REF_CLK domain released after mm_rst
- mb_II_ref_rst : out std_logic; -- reset in MB_II_REF_CLK domain released after mm_rst
-
- this_chip_id : out std_logic_vector(c_unb2c_board_nof_chip_w - 1 downto 0); -- [1:0], so range 0-3 for PN
- this_bck_id : out std_logic_vector(c_unb2c_board_nof_uniboard_w - 1 downto 0); -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
+ -- 200 MHz CLK
+ ext_clk200 : out std_logic;
+ -- reset in CLK clock domain released after mm_rst
+ ext_rst200 : out std_logic;
+
+ -- MM clock from xo_ethclk PLL
+ mm_clk : out std_logic;
+ -- reset in MM clock domain released after xo_ethclk PLL locked
+ mm_rst : out std_logic;
+
+ -- reset in DP clock domain released after mm_rst and after CLK PLL locked in case g_dp_clk_use_pll=TRUE
+ dp_rst : out std_logic;
+ -- 200 MHz DP clock from CLK system clock direct or via CLK PLL dependent on g_dp_clk_use_pll
+ dp_clk : out std_logic;
+ -- PPS in dp_clk domain
+ dp_pps : out std_logic;
+ -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
+ dp_rst_in : in std_logic;
+ -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
+ dp_clk_in : in std_logic;
+
+ -- reset in MB_I_REF_CLK domain released after mm_rst
+ mb_I_ref_rst : out std_logic;
+ -- reset in MB_II_REF_CLK domain released after mm_rst
+ mb_II_ref_rst : out std_logic;
+
+ -- [1:0], so range 0-3 for PN
+ this_chip_id : out std_logic_vector(c_unb2c_board_nof_chip_w - 1 downto 0);
+ -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
+ this_bck_id : out std_logic_vector(c_unb2c_board_nof_uniboard_w - 1 downto 0);
app_led_red : in std_logic := '0';
app_led_green : in std_logic := '1';
-- PIOs
- pout_wdi : in std_logic; -- Toggled by unb_osy; can be overriden by reg_wdi.
+ -- Toggled by unb_osy; can be overriden by reg_wdi.
+ pout_wdi : in std_logic;
-- Manual WDI override
reg_wdi_mosi : in t_mem_mosi := c_mem_mosi_rst;
@@ -194,12 +220,16 @@ entity ctrl_unb2c_board is
-- eth1g control&monitoring
eth1g_mm_rst : in std_logic;
- eth1g_tse_mosi : in t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ eth1g_tse_mosi : in t_mem_mosi;
eth1g_tse_miso : out t_mem_miso;
- eth1g_reg_mosi : in t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ eth1g_reg_mosi : in t_mem_mosi;
eth1g_reg_miso : out t_mem_miso;
- eth1g_reg_interrupt : out std_logic; -- Interrupt
- eth1g_ram_mosi : in t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ eth1g_reg_interrupt : out std_logic;
+ -- ETH rx frame and tx frame memory
+ eth1g_ram_mosi : in t_mem_mosi;
eth1g_ram_miso : out t_mem_miso;
-- eth1g UDP streaming ports
@@ -216,11 +246,16 @@ entity ctrl_unb2c_board is
-- >>> Ctrl FPGA pins
--
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(g_aux.version_w - 1 downto 0);
@@ -228,20 +263,27 @@ entity ctrl_unb2c_board is
TESTIO : inout std_logic_vector(g_aux.testio_w - 1 downto 0);
-- DDR reference clock domains reset creation
- MB_I_REF_CLK : in std_logic := '0'; -- 25 MHz
- MB_II_REF_CLK : in std_logic := '0'; -- 25 MHz
+ -- 25 MHz
+ MB_I_REF_CLK : in std_logic := '0';
+ -- 25 MHz
+ MB_II_REF_CLK : in std_logic := '0';
-- 1GbE Control Interface
- ETH_CLK : in std_logic; -- 125 MHz
- ETH_SGIN : in std_logic; -- _VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0) := (OTHERS=>'0');
- ETH_SGOUT : out std_logic -- _VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0)
+ -- 125 MHz
+ ETH_CLK : in std_logic;
+ -- _VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0) := (OTHERS=>'0');
+ ETH_SGIN : in std_logic;
+ -- _VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0)
+ ETH_SGOUT : out std_logic
);
end ctrl_unb2c_board;
architecture str of ctrl_unb2c_board is
- constant c_rom_version : natural := 3; -- Only increment when something changes to the register map of rom_system_info.
+ -- Only increment when something changes to the register map of rom_system_info.
+ constant c_rom_version : natural := 3;
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
constant c_mm_clk_freq : natural := sel_a_b(g_sim = false,g_mm_clk_freq,c_unb2c_board_mm_clk_freq_10M);
constant c_ram_scrap : t_c_mem := (c_mem_ram_rd_latency, 9, 32, 2**9, 'X');
@@ -308,22 +350,27 @@ begin
INTA <= 'Z';
INTB <= 'Z';
- TESTIO <= (others => 'Z'); -- Leave unused INOUT tri-state
+ -- Leave unused INOUT tri-state
+ TESTIO <= (others => 'Z');
- ext_pps <= PPS; -- use more special name for PPS pin signal to ease searching for it in editor
+ -- use more special name for PPS pin signal to ease searching for it in editor
+ ext_pps <= PPS;
-----------------------------------------------------------------------------
-- ext_clk200 = CLK
-----------------------------------------------------------------------------
- i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
+ -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
+ i_ext_clk200 <= CLK;
u_common_areset_ext : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => i_ext_clk200,
out_rst => ext_rst200
);
@@ -332,15 +379,18 @@ begin
-- xo_ethclk = ETH_CLK
-----------------------------------------------------------------------------
- i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
+ -- use the ETH_CLK pin as xo_clk
+ i_xo_ethclk <= ETH_CLK;
u_common_areset_xo : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => i_xo_ethclk,
out_rst => i_xo_rst
);
@@ -352,22 +402,26 @@ begin
u_common_areset_mb_I : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ -- release reset some clock cycles after i_mm_rst went low
+ in_rst => i_mm_rst,
clk => MB_I_REF_CLK,
out_rst => mb_I_ref_rst
);
u_common_areset_mb_II : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ -- release reset some clock cycles after i_mm_rst went low
+ in_rst => i_mm_rst,
clk => MB_II_REF_CLK,
out_rst => mb_II_ref_rst
);
@@ -392,7 +446,8 @@ begin
port map (
arst => i_mm_rst,
clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
+ -- = c0
+ st_clk200 => dp_clk,
st_rst200 => common_areset_in_rst
);
end generate;
@@ -403,7 +458,8 @@ begin
g_delay_len => c_reset_len
)
port map (
- in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
+ -- release reset some clock cycles after i_mm_rst went low
+ in_rst => common_areset_in_rst,
clk => dp_clk_in,
out_rst => dp_rst
);
@@ -418,13 +474,18 @@ begin
clk125 when g_mm_clk_freq = c_unb2c_board_mm_clk_freq_125M else
clk100 when g_mm_clk_freq = c_unb2c_board_mm_clk_freq_100M else
clk50 when g_mm_clk_freq = c_unb2c_board_mm_clk_freq_50M else
- clk50; -- default
+ -- default
+ clk50;
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
+ -- 20 MHz, 50ns/2
+ epcs_clk <= not epcs_clk after 25 ns;
+ -- 50 MHz, 20ns/2
+ clk50 <= not clk50 after 10 ns;
+ -- 100 MHz, 10ns/2
+ clk100 <= not clk100 after 5 ns;
+ -- 125 MHz, 8ns/2
+ clk125 <= not clk125 after 4 ns;
sim_mm_clk <= not sim_mm_clk after g_sim_mm_clk_period / 2;
mm_locked <= '0', '1' after 70 ns;
end generate;
@@ -448,7 +509,8 @@ begin
u_unb2c_board_node_ctrl : entity work.unb2c_board_node_ctrl
generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us => c_mm_clk_freq / (10**6)
)
port map (
-- MM clock domain reset
@@ -457,11 +519,13 @@ begin
mm_rst => i_mm_rst,
-- WDI extend
mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ mm_wdi_out => mm_wdi,
-- Pulses
mm_pulse_us => OPEN,
mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
+ -- could be used to toggle a LED
+ mm_pulse_s => mm_pulse_s
);
-----------------------------------------------------------------------------
@@ -624,7 +688,8 @@ begin
mm_clk => i_mm_clk,
st_rst => dp_rst_in,
st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+ -- with unknown but constant phase to st_clk
+ pps_ext => ext_pps,
-- Memory-mapped clock domain
reg_mosi => reg_ppsh_mosi,
@@ -702,17 +767,22 @@ begin
u_eth : entity eth_lib.eth
generic map (
g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ -- Last two bytes set by board/FPGA ID.
+ g_init_ip_address => g_base_ip & X"0000",
g_cross_clock_domain => g_udp_offload,
g_frm_discard_en => true,
g_sim => g_sim,
- g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ g_sim_level => g_sim_level
)
port map (
-- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
+ -- use reset from QSYS
+ mm_rst => eth1g_mm_rst,
+ -- use mm_clk direct
+ mm_clk => i_mm_clk,
+ -- 125 MHz clock
+ eth_clk => i_tse_clk,
st_rst => eth1g_st_rst,
st_clk => eth1g_st_clk,
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
index 699c38a4d2262156a5cc1fa378aeb487034d732f..b438b8b6205edef96ce9f0c39a9d7abf435b18a0 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
@@ -31,13 +31,15 @@ entity mms_unb2c_board_system_info is
g_sim : boolean := false;
g_technology : natural := c_tech_arria10_e2sg;
g_design_name : string;
- g_fw_version : t_unb2c_board_fw_version := c_unb2c_board_fw_version; -- firmware version x.y
+ -- firmware version x.y
+ g_fw_version : t_unb2c_board_fw_version := c_unb2c_board_fw_version;
g_stamp_date : natural := 0;
g_stamp_time : natural := 0;
g_revision_id : string := "";
g_design_note : string := "";
g_rom_version : natural := 2;
- g_aux : t_c_unb2c_board_aux := c_unb2c_board_aux -- aux contains the hardware version
+ -- aux contains the hardware version
+ g_aux : t_c_unb2c_board_aux := c_unb2c_board_aux
);
port (
mm_rst : in std_logic;
@@ -65,19 +67,22 @@ architecture str of mms_unb2c_board_system_info is
-- Provide different prefixes (absolute and relative) for the same path. ModelSim understands $UNB, Quartus does not.
-- Required because the work paths of ModelSim and Quartus are different.
constant c_quartus_path_prefix : string := "";
- constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/"; -- TODO: change path
+ -- TODO: change path
+ constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/";
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
-- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
-- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
- constant c_rom_addr_w : natural := 13; -- 2^13 = 8192 addresses * 32 bits = 32 kiB
+ -- 2^13 = 8192 addresses * 32 bits = 32 kiB
+ constant c_rom_addr_w : natural := 13;
constant c_mm_rom : t_c_mem := (latency => 1,
adr_w => c_rom_addr_w,
dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ -- = 2**adr_w
+ nof_dat => 2**c_rom_addr_w,
init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
index 6b19f5aad1f07bc80ddbdc66a4e10bde2219af4e..3042ec8c92204135111968014d3a79d2103291a5 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
@@ -37,15 +37,21 @@ entity mms_unb2c_fpga_sens is
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
mm_start : in std_logic;
-- Memory-mapped clock domain
- reg_temp_mosi : in t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
- reg_temp_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
- reg_voltage_mosi : in t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
- reg_voltage_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ reg_temp_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ -- actual ranges defined by c_mm_reg
+ reg_temp_miso : out t_mem_miso;
+ -- actual ranges defined by c_mm_reg
+ reg_voltage_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ -- actual ranges defined by c_mm_reg
+ reg_voltage_miso : out t_mem_miso;
-- Temperature alarm output
temp_alarm : out std_logic
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
index 1c0b8a5d378373cd491677a316c707a5d54e7020..1867c6d7e923fb78f6296f9ad54c9d88f8f280ee 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
@@ -41,12 +41,17 @@ entity unb2c_board_clk125_pll is
);
port (
arst : in std_logic := '0';
- clk125 : in std_logic := '0'; -- connect to UniBoard ETH_clk pin (125 MHz)
+ -- connect to UniBoard ETH_clk pin (125 MHz)
+ clk125 : in std_logic := '0';
- c0_clk20 : out std_logic; -- PLL c0
- c1_clk50 : out std_logic; -- PLL c1
- c2_clk100 : out std_logic; -- PLL c2
- c3_clk125 : out std_logic; -- PLL c3
+ -- PLL c0
+ c0_clk20 : out std_logic;
+ -- PLL c1
+ c1_clk50 : out std_logic;
+ -- PLL c2
+ c2_clk100 : out std_logic;
+ -- PLL c3
+ c3_clk125 : out std_logic;
pll_locked : out std_logic
);
end unb2c_board_clk125_pll;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
index ac16a08d1527d9590123f78b04e3bf8fe1ec08b4..a2e6655ed00fd15fc3443f904ae07e9164781654 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
@@ -95,20 +95,27 @@ entity unb2c_board_clk200_pll is
g_technology : natural := c_tech_arria10_e2sg;
g_use_clkbuf : boolean := true;
g_use_fpll : boolean := false;
- g_operation_mode : string := "NORMAL"; -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
- g_clk200_phase_shift : string := "0"; -- default use 0 degrees, see clk200_pll.vhd for other phase values
- g_clk200p_phase_shift : string := "0" -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
+ g_operation_mode : string := "NORMAL";
+ -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ g_clk200_phase_shift : string := "0";
+ -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ g_clk200p_phase_shift : string := "0"
);
port (
-- It depends on g_sel which outputs are actually available
-- . common
arst : in std_logic := '0';
- clk200 : in std_logic := '0'; -- connect to UniBoard CLK pin
- st_clk200 : out std_logic; -- PLL c0 = g_clk200_phase_shift degrees phase offset to input clk200
+ -- connect to UniBoard CLK pin
+ clk200 : in std_logic := '0';
+ -- PLL c0 = g_clk200_phase_shift degrees phase offset to input clk200
+ st_clk200 : out std_logic;
st_rst200 : out std_logic;
- st_clk200p : out std_logic; -- PLL c1 = g_clk200p_phase_shift degrees phase offset to input clk200 (see clk200_pll.vhd from MegaWizard)
+ -- PLL c1 = g_clk200p_phase_shift degrees phase offset to input clk200 (see clk200_pll.vhd from MegaWizard)
+ st_clk200p : out std_logic;
st_rst200p : out std_logic;
- st_clk400 : out std_logic; -- PLL c2 = 0 degrees phase offset to input clk200
+ -- PLL c2 = 0 degrees phase offset to input clk200
+ st_clk400 : out std_logic;
st_rst400 : out std_logic
);
end unb2c_board_clk200_pll;
@@ -171,10 +178,14 @@ begin
)
port map (
areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
+ -- 200 MHz
+ inclk0 => clk200buf,
+ -- 200 MHz
+ c0 => i_st_clk200,
+ -- 200 MHz shifted 90 degrees
+ c1 => i_st_clk200p,
+ -- 400 MHz
+ c2 => i_st_clk400,
locked => st_locked
);
end generate;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
index 71a8f3000c65aa0a7d3ed3c3ef3cee696d09c8b6..8f4bf7bfe048b64262f0403759672c04cd7e86a9 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
@@ -39,12 +39,17 @@ entity unb2c_board_clk25_pll is
);
port (
arst : in std_logic := '0';
- clk25 : in std_logic := '0'; -- connect to UniBoard ETH_clk pin (25 MHz)
+ -- connect to UniBoard ETH_clk pin (25 MHz)
+ clk25 : in std_logic := '0';
- c0_clk20 : out std_logic; -- PLL c0
- c1_clk50 : out std_logic; -- PLL c1
- c2_clk100 : out std_logic; -- PLL c2
- c3_clk125 : out std_logic; -- PLL c3
+ -- PLL c0
+ c0_clk20 : out std_logic;
+ -- PLL c1
+ c1_clk50 : out std_logic;
+ -- PLL c2
+ c2_clk100 : out std_logic;
+ -- PLL c3
+ c3_clk125 : out std_logic;
pll_locked : out std_logic
);
end unb2c_board_clk25_pll;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
index 25dd597531db0184a247147f3cf4ae108149fc54..6a9754aabc373cffcb154e442d6f561e4bc7f56d 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
@@ -33,20 +33,27 @@ use common_lib.common_pkg.all;
entity unb2c_board_clk_rst is
port (
-- Reference clock and reset to SOPC system PLL
- xo_clk : in std_logic; -- reference XO clock (e.g. 25 MHz also use by PLL in SOPC)
- xo_rst_n : out std_logic; -- NOT xo_rst (e.g. to reset the SOPC with NIOS2 uP)
+ -- reference XO clock (e.g. 25 MHz also use by PLL in SOPC)
+ xo_clk : in std_logic;
+ -- NOT xo_rst (e.g. to reset the SOPC with NIOS2 uP)
+ xo_rst_n : out std_logic;
-- System clock and locked from SOPC system PLL
- sys_clk : in std_logic; -- system clock derived from the reference XO clock (e.g. 125 MHz by a PLL from SOPC with NIOS2 uP)
- sys_locked : in std_logic; -- system clock PLL locked
- sys_rst : out std_logic -- system reset released some cycles after the system clock PLL has in locked
+ -- system clock derived from the reference XO clock (e.g. 125 MHz by a PLL from SOPC with NIOS2 uP)
+ sys_clk : in std_logic;
+ -- system clock PLL locked
+ sys_locked : in std_logic;
+ -- system reset released some cycles after the system clock PLL has in locked
+ sys_rst : out std_logic
);
end unb2c_board_clk_rst;
architecture str of unb2c_board_clk_rst is
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
-- XO clock domain
- signal xo_rst : std_logic; -- initial reset released after some XO clock cycles
+ -- initial reset released after some XO clock cycles
+ signal xo_rst : std_logic;
-- SYS clock domain
signal sys_locked_n : std_logic;
@@ -56,11 +63,13 @@ begin
u_common_areset_xo : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => xo_clk,
out_rst => xo_rst
);
@@ -70,11 +79,13 @@ begin
u_common_areset_sys : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ -- release reset after some clock cycles when the PLL has locked
+ in_rst => sys_locked_n,
clk => sys_clk,
out_rst => sys_rst
);
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
index cd18bbc40cec125f81658a0fd47e06cef83951e1..08a2f4149d10706d48894bd4f686d3a9f9e9ba63 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
@@ -32,30 +32,43 @@ use common_lib.common_pkg.all;
entity unb2c_board_node_ctrl is
generic (
- g_pulse_us : natural := 125; -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- g_pulse_ms : natural := 1000; -- nof pulse_us pulses to get ms period (fixed, use less to speed up simulation)
- g_pulse_s : natural := 1000; -- nof pulse_ms pulses to get s period (fixed, use less to speed up simulation)
- g_wdi_extend_w : natural := 14 -- extend the mm_wdi_in by toggling the mm_wdi_out for about 2**(14-1)= 8 s more
+ -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_us : natural := 125;
+ -- nof pulse_us pulses to get ms period (fixed, use less to speed up simulation)
+ g_pulse_ms : natural := 1000;
+ -- nof pulse_ms pulses to get s period (fixed, use less to speed up simulation)
+ g_pulse_s : natural := 1000;
+ -- extend the mm_wdi_in by toggling the mm_wdi_out for about 2**(14-1)= 8 s more
+ g_wdi_extend_w : natural := 14
);
port (
-- MM clock domain reset
- mm_clk : in std_logic; -- MM clock
- mm_locked : in std_logic := '1'; -- MM clock PLL locked (or use default '1')
- mm_rst : out std_logic; -- MM reset released after MM clock PLL has locked
+ -- MM clock
+ mm_clk : in std_logic;
+ -- MM clock PLL locked (or use default '1')
+ mm_locked : in std_logic := '1';
+ -- MM reset released after MM clock PLL has locked
+ mm_rst : out std_logic;
-- WDI extend
- mm_wdi_in : in std_logic; -- from software running on the NIOS2 in the SOPC design
- mm_wdi_out : out std_logic; -- to FPGA pin
+ -- from software running on the NIOS2 in the SOPC design
+ mm_wdi_in : in std_logic;
+ -- to FPGA pin
+ mm_wdi_out : out std_logic;
-- Pulses
- mm_pulse_us : out std_logic; -- pulses every us
- mm_pulse_ms : out std_logic; -- pulses every ms
- mm_pulse_s : out std_logic -- pulses every s
+ -- pulses every us
+ mm_pulse_us : out std_logic;
+ -- pulses every ms
+ mm_pulse_ms : out std_logic;
+ -- pulses every s
+ mm_pulse_s : out std_logic
);
end unb2c_board_node_ctrl;
architecture str of unb2c_board_node_ctrl is
- constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
+ -- >= c_meta_delay_len from common_pkg
+ constant c_reset_len : natural := 4;
signal mm_locked_n : std_logic;
signal i_mm_rst : std_logic;
@@ -68,11 +81,13 @@ begin
u_common_areset_mm : entity common_lib.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ -- release reset after some clock cycles when the PLL has locked
+ in_rst => mm_locked_n,
clk => mm_clk,
out_rst => i_mm_rst
);
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
index 09f3d31eb03c9dea2187fe903fad302efc866c1b..5a396dce4a58ebccf68e09295eab84a1d37e7681 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
@@ -45,122 +45,172 @@ package unb2c_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
-- *_dat_w : The default MM data width is c_word_w=32, otherwise it is specified in the record
type t_c_unb2c_board_peripherals_mm_reg is record
- cross_clock_domain : boolean; -- = TRUE -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ -- = TRUE -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ cross_clock_domain : boolean;
-- 1GbE
- reg_tse_adr_w : natural; -- = 10 -- = c_tse_byte_addr_w from tse_pkg.vhd
- reg_eth_adr_w : natural; -- = 4 -- = c_eth_reg_addr_w from eth_pkg.vhd
- ram_eth_adr_w : natural; -- = 10 -- = c_eth_ram_addr_w from eth_pkg.vhd
+ -- = 10 -- = c_tse_byte_addr_w from tse_pkg.vhd
+ reg_tse_adr_w : natural;
+ -- = 4 -- = c_eth_reg_addr_w from eth_pkg.vhd
+ reg_eth_adr_w : natural;
+ -- = 10 -- = c_eth_ram_addr_w from eth_pkg.vhd
+ ram_eth_adr_w : natural;
-- pi_system_info (first word of reg_unb_system_info_adr_w is backwards compatible with the original single word PIO system info)
- reg_unb_system_info_adr_w : natural; -- = 5 -- fixed, from c_mm_reg in unb_system_info_reg
- rom_unb_system_info_adr_w : natural; -- = 13 -- fixed, from c_mm_rom in mms_unb_system_info
+ -- = 5 -- fixed, from c_mm_reg in unb_system_info_reg
+ reg_unb_system_info_adr_w : natural;
+ -- = 13 -- fixed, from c_mm_rom in mms_unb_system_info
+ rom_unb_system_info_adr_w : natural;
-- pi_reg_common
- reg_common_adr_w : natural; -- = 1 -- fixed, from c_mem_reg in mms_common_reg
+ -- = 1 -- fixed, from c_mem_reg in mms_common_reg
+ reg_common_adr_w : natural;
-- pi_ppsh
- reg_ppsh_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in ppsh_reg
+ -- = 2 -- fixed, from c_mm_reg in ppsh_reg
+ reg_ppsh_adr_w : natural;
-- pi_unb_sens
- reg_unb_sens_adr_w : natural; -- = 6 -- fixed, from c_mm_reg in unb_sens_reg
+ -- = 6 -- fixed, from c_mm_reg in unb_sens_reg
+ reg_unb_sens_adr_w : natural;
-- pi_dpmm
- reg_dpmm_data_adr_w : natural; -- = 1 -- fixed, see dp_fifo_to_mm.vhd
- reg_dpmm_ctrl_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_fifo_to_mm_reg.vhd
+ -- = 1 -- fixed, see dp_fifo_to_mm.vhd
+ reg_dpmm_data_adr_w : natural;
+ -- = 1 -- fixed, from c_mm_reg in dp_fifo_to_mm_reg.vhd
+ reg_dpmm_ctrl_adr_w : natural;
-- pi_mmdp
- reg_mmdp_data_adr_w : natural; -- = 1 -- fixed, see dp_fifo_from_mm.vhd
- reg_mmdp_ctrl_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_fifo_from_mm_reg.vhd
+ -- = 1 -- fixed, see dp_fifo_from_mm.vhd
+ reg_mmdp_data_adr_w : natural;
+ -- = 1 -- fixed, from c_mm_reg in dp_fifo_from_mm_reg.vhd
+ reg_mmdp_ctrl_adr_w : natural;
-- pi_dp_ram_from_mm
- reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
+ -- = 1 -- fixed, see dp_ram_from_mm.vhd
+ reg_dp_ram_from_mm_adr_w : natural;
-- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
-- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
- reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
+ -- = 3 -- fixed, from c_mm_reg in epcs_reg
+ reg_epcs_adr_w : natural;
-- pi_remu
- reg_remu_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in remu_reg
+ -- = 3 -- fixed, from c_mm_reg in remu_reg
+ reg_remu_adr_w : natural;
-- pi_ddr
-- pi_ddr_capture (uses DP-MM read FIFO for data access)
- reg_ddr_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in ddr_reg
+ -- = 3 -- fixed, from c_mm_reg in ddr_reg
+ reg_ddr_adr_w : natural;
-- pi_io_ddr
- reg_io_ddr_adr_w : natural; -- = 16 -- fixed, from c_mm_reg in io_ddr (3) and in io_ddr_reg (8) that get multiplexed in on addresses 0..2, 8..15
+ -- = 16 -- fixed, from c_mm_reg in io_ddr (3) and in io_ddr_reg (8) that get multiplexed in on addresses 0..2, 8..15
+ reg_io_ddr_adr_w : natural;
-- pi_tr_nonbonded
- reg_tr_nonbonded_adr_w : natural; -- = 4 -- fixed, from c_mm_reg in tr_nonbonded_reg
+ -- = 4 -- fixed, from c_mm_reg in tr_nonbonded_reg
+ reg_tr_nonbonded_adr_w : natural;
-- pi_diagnostics
- reg_diagnostics_adr_w : natural; -- = 6 -- fixed, from c_mm_reg in diagnostics_reg
+ -- = 6 -- fixed, from c_mm_reg in diagnostics_reg
+ reg_diagnostics_adr_w : natural;
-- pi_dp_throttle
- reg_dp_throttle_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in dp_throttle_reg
+ -- = 2 -- fixed, from c_mm_reg in dp_throttle_reg
+ reg_dp_throttle_adr_w : natural;
-- pi_bsn_source
- reg_bsn_source_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in dp_bsn_source_reg.vhd
+ -- = 2 -- fixed, from c_mm_reg in dp_bsn_source_reg.vhd
+ reg_bsn_source_adr_w : natural;
-- pi_bsn_schedurer
- reg_bsn_scheduler_adr_w : natural; -- = 1 -- fixed, from c_mm_reg in dp_bsn_scheduler_reg.vhd
+ -- = 1 -- fixed, from c_mm_reg in dp_bsn_scheduler_reg.vhd
+ reg_bsn_scheduler_adr_w : natural;
-- pi_bsn_monitor
- reg_bsn_monitor_adr_w : natural; -- = 4 -- fixed, from c_mm_reg in dp_bsn_monitor_reg.vhd
+ -- = 4 -- fixed, from c_mm_reg in dp_bsn_monitor_reg.vhd
+ reg_bsn_monitor_adr_w : natural;
-- pi_aduh_quad (defaults for ADU)
- reg_adc_quad_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in aduh_quad_reg.vhd
+ -- = 3 -- fixed, from c_mm_reg in aduh_quad_reg.vhd
+ reg_adc_quad_adr_w : natural;
-- pi_aduh_i2c_commander (defaults for ADU)
- reg_i2c_commander_adr_w : natural; -- = 6 -- = c_i2c_cmdr_aduh_i2c_mm.control_adr_w, from i2c_commander_aduh_pkg, used to pass on commander_adr_w
- ram_i2c_protocol_adr_w : natural; -- = 13 -- = c_i2c_cmdr_aduh_i2c_mm.protocol_adr_w, from i2c_commander_aduh_pkg
- ram_i2c_result_adr_w : natural; -- = 12 -- = c_i2c_cmdr_aduh_i2c_mm.result_adr_w, from i2c_commander_aduh_pkg
+ -- = 6 -- = c_i2c_cmdr_aduh_i2c_mm.control_adr_w, from i2c_commander_aduh_pkg, used to pass on commander_adr_w
+ reg_i2c_commander_adr_w : natural;
+ -- = 13 -- = c_i2c_cmdr_aduh_i2c_mm.protocol_adr_w, from i2c_commander_aduh_pkg
+ ram_i2c_protocol_adr_w : natural;
+ -- = 12 -- = c_i2c_cmdr_aduh_i2c_mm.result_adr_w, from i2c_commander_aduh_pkg
+ ram_i2c_result_adr_w : natural;
-- pi_aduh_monitor (defaults for ADU or WG used in bn_capture)
- reg_aduh_mon_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in aduh_monitor_reg.vhd
- ram_aduh_mon_dat_w : natural; -- = 32 -- = c_sp_data_w, see node_bn_capture.vhd
- ram_aduh_mon_adr_w : natural; -- = 8 -- = ceil_log2(c_bn_capture.sp.monitor_buffer_nof_samples/c_wideband_factor), see node_bn_capture.vhd
+ -- = 2 -- fixed, from c_mm_reg in aduh_monitor_reg.vhd
+ reg_aduh_mon_adr_w : natural;
+ -- = 32 -- = c_sp_data_w, see node_bn_capture.vhd
+ ram_aduh_mon_dat_w : natural;
+ -- = 8 -- = ceil_log2(c_bn_capture.sp.monitor_buffer_nof_samples/c_wideband_factor), see node_bn_capture.vhd
+ ram_aduh_mon_adr_w : natural;
-- pi_diag_wg_wideband.py (defaults for WG used in bn_capture)
- reg_diag_wg_adr_w : natural; -- = 2 -- fixed, from c_mm_reg in diag_wg_wideband_reg
- ram_diag_wg_dat_w : natural; -- = 8 -- defined here, see bn_capture_input.vhd
- ram_diag_wg_adr_w : natural; -- = 10 -- defined here, see bn_capture_input.vhd
+ -- = 2 -- fixed, from c_mm_reg in diag_wg_wideband_reg
+ reg_diag_wg_adr_w : natural;
+ -- = 8 -- defined here, see bn_capture_input.vhd
+ ram_diag_wg_dat_w : natural;
+ -- = 10 -- defined here, see bn_capture_input.vhd
+ ram_diag_wg_adr_w : natural;
-- pi_diag_data_buffer.py
- ram_diag_db_nof_buf : natural; -- = 16
- ram_diag_db_buf_size : natural; -- = 1024
- ram_diag_db_adr_w : natural; -- = 14 -- = ram_diag_db_nof_buf*ceil_log2(ram_diag_db_buf_size)
- reg_diag_db_adr_w : natural; -- = 5 -- 32 words for 16 streams max
+ -- = 16
+ ram_diag_db_nof_buf : natural;
+ -- = 1024
+ ram_diag_db_buf_size : natural;
+ -- = 14 -- = ram_diag_db_nof_buf*ceil_log2(ram_diag_db_buf_size)
+ ram_diag_db_adr_w : natural;
+ -- = 5 -- 32 words for 16 streams max
+ reg_diag_db_adr_w : natural;
-- pi_diag_block_gen (defaults when used with the BF for Apertif)
- reg_diag_bg_adr_w : natural; -- = 3
- ram_diag_bg_adr_w : natural; -- = 11 -- = ceil_log2(c_bf.nof_subbands*c_bf.nof_signal_paths/c_bf.nof_input_streams = 24*64/16 = 96) + ceil_log2(c_bf.nof_input_streams = 16)
+ -- = 3
+ reg_diag_bg_adr_w : natural;
+ -- = 11 -- = ceil_log2(c_bf.nof_subbands*c_bf.nof_signal_paths/c_bf.nof_input_streams = 24*64/16 = 96) + ceil_log2(c_bf.nof_input_streams = 16)
+ ram_diag_bg_adr_w : natural;
-- pi_diag_tx_seq.py
- reg_diag_tx_seq_w : natural; -- = 2
+ -- = 2
+ reg_diag_tx_seq_w : natural;
-- pi_diag_tx_seq.py
- reg_diag_rx_seq_w : natural; -- = 3
+ -- = 3
+ reg_diag_rx_seq_w : natural;
-- pi_bf_bf (defaults for the BF for Apertif)
- reg_bf_offsets_adr_w : natural; -- = 5 -- = ceil_log2(c_bf.nof_offsets = 6) + ceil_log2(c_bf.nof_bf_units = 4)
- ram_bf_weights_adr_w : natural; -- = 16 -- = ceil_log2(c_bf.nof_bf_units*c_bf.nof_signal_paths*c_bf.nof_weights = 4 * 64 * 256 = 65536)
- ram_st_sst_bf_adr_w : natural; -- = 11 -- = ceil_log2(c_bf.nof_bf_units*c_bf.stat_data_sz*c_bf.nof_weights = 4 * 2 * 256 = 2048)
+ -- = 5 -- = ceil_log2(c_bf.nof_offsets = 6) + ceil_log2(c_bf.nof_bf_units = 4)
+ reg_bf_offsets_adr_w : natural;
+ -- = 16 -- = ceil_log2(c_bf.nof_bf_units*c_bf.nof_signal_paths*c_bf.nof_weights = 4 * 64 * 256 = 65536)
+ ram_bf_weights_adr_w : natural;
+ -- = 11 -- = ceil_log2(c_bf.nof_bf_units*c_bf.stat_data_sz*c_bf.nof_weights = 4 * 2 * 256 = 2048)
+ ram_st_sst_bf_adr_w : natural;
-- pi_mdio
- reg_mdio_adr_w : natural; -- = 3
+ -- = 3
+ reg_mdio_adr_w : natural;
-- dp_offload
- reg_dp_offload_tx_adr_w : natural; -- = 1
+ -- = 1
+ reg_dp_offload_tx_adr_w : natural;
-- pi_unb_fpga_sensors
- reg_fpga_temp_sens_adr_w : natural; -- = 3
- reg_fpga_voltage_sens_adr_w : natural; -- = 4
+ -- = 3
+ reg_fpga_temp_sens_adr_w : natural;
+ -- = 4
+ reg_fpga_voltage_sens_adr_w : natural;
-- pi_unb_pmbus
- reg_unb_pmbus_adr_w : natural; -- = 6
+ -- = 6
+ reg_unb_pmbus_adr_w : natural;
end record;
constant c_unb2c_board_peripherals_mm_reg_default : t_c_unb2c_board_peripherals_mm_reg := (true, 10, 4, 10, 5, 13, 1, 2, 6, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1, 3, 4, 6);
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
index 58d12477543d49583818dbc0ecda26a5527523f9..edde25f462721b06248fcf222d14aae7793c5844 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
@@ -28,31 +28,50 @@ use dp_lib.dp_stream_pkg.all;
package unb2c_board_pkg is
-- UniBoard
- constant c_unb2c_board_nof_node : natural := 4; -- number of nodes on UniBoard
- constant c_unb2c_board_nof_node_w : natural := 2; -- = ceil_log2(c_unb2c_board_nof_node)
- constant c_unb2c_board_nof_chip : natural := c_unb2c_board_nof_node; -- = 4
- constant c_unb2c_board_nof_chip_w : natural := 2; -- = ceil_log2(c_unb2c_board_nof_chip)
- constant c_unb2c_board_nof_ddr : natural := 2; -- each node has 2 DDR modules
+ -- number of nodes on UniBoard
+ constant c_unb2c_board_nof_node : natural := 4;
+ -- = ceil_log2(c_unb2c_board_nof_node)
+ constant c_unb2c_board_nof_node_w : natural := 2;
+ -- = 4
+ constant c_unb2c_board_nof_chip : natural := c_unb2c_board_nof_node;
+ -- = ceil_log2(c_unb2c_board_nof_chip)
+ constant c_unb2c_board_nof_chip_w : natural := 2;
+ -- each node has 2 DDR modules
+ constant c_unb2c_board_nof_ddr : natural := 2;
-- Subrack : TODO: Isn't this application specific?
- constant c_unb2c_board_nof_uniboard : natural := 4; -- nof UniBoard in a subrack
- constant c_unb2c_board_nof_uniboard_w : natural := 6; -- Only 2 required for 4 boards; full width is 6.
+ -- nof UniBoard in a subrack
+ constant c_unb2c_board_nof_uniboard : natural := 4;
+ -- Only 2 required for 4 boards; full width is 6.
+ constant c_unb2c_board_nof_uniboard_w : natural := 6;
-- Clock frequencies
- constant c_unb2c_board_ext_clk_freq_200M : natural := 200 * 10**6; -- external clock, SMA clock
- constant c_unb2c_board_ext_clk_freq_256M : natural := 256 * 10**6; -- external clock, SMA clock
- constant c_unb2c_board_eth_clk_freq_25M : natural := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
- constant c_unb2c_board_eth_clk_freq_125M : natural := 125 * 10**6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
- constant c_unb2c_board_tse_clk_freq : natural := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
- constant c_unb2c_board_cal_clk_freq : natural := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
- constant c_unb2c_board_mm_clk_freq_10M : natural := 10 * 10**6; -- clock when g_sim=TRUE
- constant c_unb2c_board_mm_clk_freq_25M : natural := 25 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2c_board_mm_clk_freq_50M : natural := 50 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2c_board_mm_clk_freq_100M : natural := 100 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2c_board_mm_clk_freq_125M : natural := 125 * 10**6; -- clock derived from ETH_clk by PLL
+ -- external clock, SMA clock
+ constant c_unb2c_board_ext_clk_freq_200M : natural := 200 * 10**6;
+ -- external clock, SMA clock
+ constant c_unb2c_board_ext_clk_freq_256M : natural := 256 * 10**6;
+ -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
+ constant c_unb2c_board_eth_clk_freq_25M : natural := 25 * 10**6;
+ -- fixed 125 MHz ETH XO clock used as direct clock for TSE
+ constant c_unb2c_board_eth_clk_freq_125M : natural := 125 * 10**6;
+ -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
+ constant c_unb2c_board_tse_clk_freq : natural := 125 * 10**6;
+ -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
+ constant c_unb2c_board_cal_clk_freq : natural := 40 * 10**6;
+ -- clock when g_sim=TRUE
+ constant c_unb2c_board_mm_clk_freq_10M : natural := 10 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2c_board_mm_clk_freq_25M : natural := 25 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2c_board_mm_clk_freq_50M : natural := 50 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2c_board_mm_clk_freq_100M : natural := 100 * 10**6;
+ -- clock derived from ETH_clk by PLL
+ constant c_unb2c_board_mm_clk_freq_125M : natural := 125 * 10**6;
-- ETH
- constant c_unb2c_board_nof_eth : natural := 2; -- number of ETH channels per node
+ -- number of ETH channels per node
+ constant c_unb2c_board_nof_eth : natural := 2;
-- CONSTANT RECORD DECLARATIONS ---------------------------------------------
@@ -70,14 +89,22 @@ package unb2c_board_pkg is
i2c_w : natural;
end record;
- constant c_unb2c_board_tr_back : t_c_unb2c_board_tr := (1, 24, 0); -- per node: 2 buses with 24 channels
- constant c_unb2c_board_tr_ring : t_c_unb2c_board_tr := (2, 12, 0); -- per node: 2 buses with 12 channels
- constant c_unb2c_board_tr_qsfp : t_c_unb2c_board_tr := (6, 4, 0); -- per node: 6 buses with 4 channels
- constant c_unb2c_board_tr_jesd204b : t_c_unb2c_board_tr := (1, 12, 0); -- per node: 1 buses with 12 channels
- constant c_unb2c_board_nof_tr_jesd204b : natural := 12; -- 12 channels used in unb2c lab tests
- constant c_unb2c_board_start_tr_jesd204b : natural := 0; -- First BCK transceiver used for jesd in unb2c lab tests
- constant c_unb2c_board_nof_sync_jesd204b : natural := 4; -- 4 channels used in unb2c lab tests, 1 for each RCU.
- constant c_unb2c_board_tr_qsfp_nof_leds : natural := c_unb2c_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
+ -- per node: 2 buses with 24 channels
+ constant c_unb2c_board_tr_back : t_c_unb2c_board_tr := (1, 24, 0);
+ -- per node: 2 buses with 12 channels
+ constant c_unb2c_board_tr_ring : t_c_unb2c_board_tr := (2, 12, 0);
+ -- per node: 6 buses with 4 channels
+ constant c_unb2c_board_tr_qsfp : t_c_unb2c_board_tr := (6, 4, 0);
+ -- per node: 1 buses with 12 channels
+ constant c_unb2c_board_tr_jesd204b : t_c_unb2c_board_tr := (1, 12, 0);
+ -- 12 channels used in unb2c lab tests
+ constant c_unb2c_board_nof_tr_jesd204b : natural := 12;
+ -- First BCK transceiver used for jesd in unb2c lab tests
+ constant c_unb2c_board_start_tr_jesd204b : natural := 0;
+ -- 4 channels used in unb2c lab tests, 1 for each RCU.
+ constant c_unb2c_board_nof_sync_jesd204b : natural := 4;
+ -- 2 leds per qsfp
+ constant c_unb2c_board_tr_qsfp_nof_leds : natural := c_unb2c_board_tr_qsfp.nof_bus * 2;
type t_unb2c_board_qsfp_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
type t_unb2c_board_ring_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0);
@@ -87,12 +114,18 @@ package unb2c_board_pkg is
-- Test IO Interface
type t_c_unb2c_board_testio is record
- tst_w : natural; -- = nof tst = 2; [tst_w-1 +tst_lo : tst_lo] = [5:4],
- led_w : natural; -- = nof led = 2; [led_w-1 +led_lo : led_lo] = [3:2],
- jmp_w : natural; -- = nof jmp = 2; [jmp_w-1 +jmp_lo : jmp_lo] = [1:0],
- tst_lo : natural; -- = 2;
- led_lo : natural; -- = 2;
- jmp_lo : natural; -- = 0;
+ -- = nof tst = 2; [tst_w-1 +tst_lo : tst_lo] = [5:4],
+ tst_w : natural;
+ -- = nof led = 2; [led_w-1 +led_lo : led_lo] = [3:2],
+ led_w : natural;
+ -- = nof jmp = 2; [jmp_w-1 +jmp_lo : jmp_lo] = [1:0],
+ jmp_w : natural;
+ -- = 2;
+ tst_lo : natural;
+ -- = 2;
+ led_lo : natural;
+ -- = 0;
+ jmp_lo : natural;
end record;
constant c_unb2c_board_testio : t_c_unb2c_board_testio := (2, 2, 2, 2, 2, 0);
@@ -100,10 +133,14 @@ package unb2c_board_pkg is
constant c_unb2c_board_testio_led_red : natural := c_unb2c_board_testio.led_lo + 1;
type t_c_unb2c_board_aux is record
- version_w : natural; -- = 2;
- id_w : natural; -- = 8; -- 6+2 bits wide = total node ID for up to 64 UniBoards in a system and 4 nodes per board
- chip_id_w : natural; -- = 2; -- board node ID for the 4 FPGA nodes on a UniBoard
- testio_w : natural; -- = 6;
+ -- = 2;
+ version_w : natural;
+ -- = 8; -- 6+2 bits wide = total node ID for up to 64 UniBoards in a system and 4 nodes per board
+ id_w : natural;
+ -- = 2; -- board node ID for the 4 FPGA nodes on a UniBoard
+ chip_id_w : natural;
+ -- = 6;
+ testio_w : natural;
testio : t_c_unb2c_board_testio;
end record;
@@ -112,8 +149,10 @@ package unb2c_board_pkg is
type t_e_unb2_board_node is (e_any);
type t_unb2c_board_fw_version is record
- hi : natural; -- = 0..15
- lo : natural; -- = 0..15, firmware version is: hi.lo
+ -- = 0..15
+ hi : natural;
+ -- = 0..15, firmware version is: hi.lo
+ lo : natural;
end record;
constant c_unb2c_board_fw_version : t_unb2c_board_fw_version := (0, 0);
@@ -122,13 +161,19 @@ package unb2c_board_pkg is
-- System info
type t_c_unb2c_board_system_info is record
- version : natural; -- UniBoard board HW version (2 bit value)
- id : natural; -- UniBoard FPGA node id (8 bit value)
+ -- UniBoard board HW version (2 bit value)
+ version : natural;
+ -- UniBoard FPGA node id (8 bit value)
+ id : natural;
-- Derived ID info:
- bck_id : natural; -- = id[7:2], ID part from back plane
- chip_id : natural; -- = id[1:0], ID part from UniBoard
- node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
- is_node2 : natural; -- 1 for Node 2, else 0.
+ -- = id[7:2], ID part from back plane
+ bck_id : natural;
+ -- = id[1:0], ID part from UniBoard
+ chip_id : natural;
+ -- = id[1:0], node ID: 0, 1, 2 or 3
+ node_id : natural;
+ -- 1 for Node 2, else 0.
+ is_node2 : natural;
end record;
function func_unb2c_board_system_info(VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
index 47ba71e8f14fc9c3f4fd57fb24ecdaa1de4724f1..eb5b3607ecfcbe2506472d7b767b557ac9d290f1 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
@@ -66,10 +66,14 @@ use dp_lib.dp_stream_pkg.all;
entity unb2c_board_qsfp_leds is
generic (
- g_sim : boolean := false; -- when true speed up led toggling in simulation
- g_factory_image : boolean := false; -- distinguish factory image and user images
- g_nof_qsfp : natural := 6; -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us : natural := 200 -- nof clk cycles to get us period
+ -- when true speed up led toggling in simulation
+ g_sim : boolean := false;
+ -- distinguish factory image and user images
+ g_factory_image : boolean := false;
+ -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_nof_qsfp : natural := 6;
+ -- nof clk cycles to get us period
+ g_pulse_us : natural := 200
);
port (
rst : in std_logic;
@@ -89,8 +93,10 @@ entity unb2c_board_qsfp_leds is
end unb2c_board_qsfp_leds;
architecture str of unb2c_board_qsfp_leds is
- constant c_nof_ms : natural := sel_a_b(g_sim, 1, 100); -- force off for c_nof_ms and then on for at least c_nof_ms
- constant c_nof_lanes : natural := g_nof_qsfp * c_quad; -- number of transceiver lanes, fixed 4 per Quad-SFP cage
+ -- force off for c_nof_ms and then on for at least c_nof_ms
+ constant c_nof_ms : natural := sel_a_b(g_sim, 1, 100);
+ -- number of transceiver lanes, fixed 4 per Quad-SFP cage
+ constant c_nof_lanes : natural := g_nof_qsfp * c_quad;
signal i_pulse_ms : std_logic;
signal i_pulse_s : std_logic;
@@ -108,9 +114,12 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ -- nof clk cycles to get us period
+ g_pulse_us => g_pulse_us,
+ -- nof pulse_us pulses to get ms period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000),
+ -- nof pulse_ms pulses to get s period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000)
)
port map (
rst => rst,
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
index ca28bdf4878eba02b20b0cc25d2ed634eb722b75..79e95fa3c172c83bc989d0020b249099459e3576 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
@@ -33,8 +33,10 @@ use technology_lib.technology_pkg.all;
entity unb2c_board_system_info is
generic (
g_sim : boolean := false;
- g_fw_version : t_unb2c_board_fw_version := c_unb2c_board_fw_version; -- firmware version x.y (4b.4b)
- g_aux : t_c_unb2c_board_aux := c_unb2c_board_aux; -- aux contains the hardware version
+ -- firmware version x.y (4b.4b)
+ g_fw_version : t_unb2c_board_fw_version := c_unb2c_board_fw_version;
+ -- aux contains the hardware version
+ g_aux : t_c_unb2c_board_aux := c_unb2c_board_aux;
g_rom_version: natural := 2;
g_technology : natural := c_tech_arria10_e2sg
);
@@ -43,10 +45,14 @@ entity unb2c_board_system_info is
hw_version : in std_logic_vector(g_aux.version_w - 1 downto 0);
id : in std_logic_vector(g_aux.id_w - 1 downto 0);
info : out std_logic_vector(c_word_w - 1 downto 0);
- bck_id : out std_logic_vector(c_unb2c_board_nof_uniboard_w - 1 downto 0); -- ID[7:2]
- chip_id : out std_logic_vector(c_unb2c_board_nof_chip_w - 1 downto 0); -- ID[1:0]
- node_id : out std_logic_vector(c_unb2c_board_nof_node_w - 1 downto 0); -- ID[1:0]
- is_node2 : out std_logic -- '1' for Node 2, else '0'.
+ -- ID[7:2]
+ bck_id : out std_logic_vector(c_unb2c_board_nof_uniboard_w - 1 downto 0);
+ -- ID[1:0]
+ chip_id : out std_logic_vector(c_unb2c_board_nof_chip_w - 1 downto 0);
+ -- ID[1:0]
+ node_id : out std_logic_vector(c_unb2c_board_nof_node_w - 1 downto 0);
+ -- '1' for Node 2, else '0'.
+ is_node2 : out std_logic
);
end unb2c_board_system_info;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
index 355bf6c3afeb7a535f5da8a5ad23e2886cc4da62..fb8fa38b162c36c0fb844b096b7968c8d5bed7bc 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
@@ -72,11 +72,16 @@ entity unb2c_board_system_info_reg is
end unb2c_board_system_info_reg;
architecture rtl of unb2c_board_system_info_reg is
- constant c_nof_fixed_regs : natural := 2; -- info, use_phy
- constant c_nof_design_name_regs : natural := 13; -- design_name
- constant c_nof_stamp_regs : natural := 2; -- date, time
- constant c_nof_revision_id_regs : natural := 3; -- revision id, commit hash or id (hash: first 9 chars of the 40chars commit hash)
- constant c_nof_design_note_regs : natural := 12; -- note
+ -- info, use_phy
+ constant c_nof_fixed_regs : natural := 2;
+ -- design_name
+ constant c_nof_design_name_regs : natural := 13;
+ -- date, time
+ constant c_nof_stamp_regs : natural := 2;
+ -- revision id, commit hash or id (hash: first 9 chars of the 40chars commit hash)
+ constant c_nof_revision_id_regs : natural := 3;
+ -- note
+ constant c_nof_design_note_regs : natural := 12;
constant c_info_reg : natural := 0;
constant c_use_phy_reg : natural := 1;
@@ -85,15 +90,18 @@ architecture rtl of unb2c_board_system_info_reg is
constant c_stamp_time_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + 1;
constant c_revision_id_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
constant c_design_note_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
- constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs; -- = 2+13+2+3+12 = 32
+ -- = 2+13+2+3+12 = 32
+ constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs;
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_nof_regs,
init_sl => '0');
constant c_use_phy_w : natural := 8;
- constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
+ -- Unused but keep for compatibillity
+ constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0');
constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
constant c_revision_id : t_slv_32_arr(0 to c_nof_revision_id_regs - 1) := str_to_ascii_slv_32_arr(g_revision_id, c_nof_revision_id_regs);
@@ -111,8 +119,10 @@ begin
-- Read access: get register value
if sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
vA := TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0));
if vA = c_info_reg then
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
index 4c53cdcc41f7c1f197a447530a4d6890ae6d0d48..1e719d829ae2ba455a0acc3a031d61ceeccb142e 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
@@ -37,7 +37,8 @@ entity unb2c_board_wdi_extend is
port (
rst : in std_logic;
clk : in std_logic;
- pulse_ms : in std_logic; -- pulses every 1 ms
+ -- pulses every 1 ms
+ pulse_ms : in std_logic;
wdi_in : in std_logic;
wdi_out : out std_logic
);
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
index 6c9a33e3833702e9aeffa2a846dd915129136e1f..a09dc1b3a87289c41d13d3cff71f77e4bec38e18 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
@@ -31,12 +31,16 @@ use common_lib.common_mem_pkg.all;
entity unb2c_board_wdi_reg is
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
wdi_override : out std_logic
@@ -47,12 +51,14 @@ architecture rtl of unb2c_board_wdi_reg is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 1,
init_sl => '0');
-- For safety, WDI override requires the following word to be written:
- constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
+ -- "Boot factory"
+ constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7";
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -75,7 +81,8 @@ begin
else
wdi_override <= '0';
end if;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
index 320d5febe60192f37cbbf7a5b57e4e152c719d76..98ec81570f7d427e120448e328e89360277ae413 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
@@ -34,7 +34,8 @@ entity tb_unb2c_board_clk125_pll is
end tb_unb2c_board_clk125_pll;
architecture tb of tb_unb2c_board_clk125_pll is
- constant c_ext_clk_period : time := 8 ns; -- 125 MHz
+ -- 125 MHz
+ constant c_ext_clk_period : time := 8 ns;
signal tb_end : std_logic := '0';
signal ext_clk : std_logic := '0';
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
index 4a035d2eb5a0a25872bae21f0151d62c0582edde..3347f47298421adf1a0dcadb4e3be6f6affa23b0 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
@@ -34,7 +34,8 @@ entity tb_unb2c_board_clk200_pll is
end tb_unb2c_board_clk200_pll;
architecture tb of tb_unb2c_board_clk200_pll is
- constant c_ext_clk_period : time := 5 ns; -- 200 MHz
+ -- 200 MHz
+ constant c_ext_clk_period : time := 5 ns;
constant c_clk_vec_w : natural := 6;
constant c_clk_div : natural := 32;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
index 9923168e21be66ac5518393923c47ae5457e6d05..70d851e9257d6c51bb4cc83c8aade9df18b6655a 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
@@ -34,7 +34,8 @@ entity tb_unb2c_board_clk25_pll is
end tb_unb2c_board_clk25_pll;
architecture tb of tb_unb2c_board_clk25_pll is
- constant c_ext_clk_period : time := 40 ns; -- 25 MHz
+ -- 25 MHz
+ constant c_ext_clk_period : time := 40 ns;
signal tb_end : std_logic := '0';
signal ext_clk : std_logic := '0';
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
index a7a90847160de275f83afcbb6bb16352204cba95..4bae7e7a0b3f9bdf1bb2ffe60b5df02e8abdcefd 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
@@ -28,21 +28,30 @@ entity tb_unb2c_board_node_ctrl is
end tb_unb2c_board_node_ctrl;
architecture tb of tb_unb2c_board_node_ctrl is
- constant c_scale : natural := 100; -- scale to speed up simulation
+ -- scale to speed up simulation
+ constant c_scale : natural := 100;
- constant c_xo_clk_period : time := 1 us; -- 1 MHz XO, slow XO to speed up simulation
- constant c_mm_clk_period : time := c_xo_clk_period / 5; -- 5 MHz PLL output from XO reference
+ -- 1 MHz XO, slow XO to speed up simulation
+ constant c_xo_clk_period : time := 1 us;
+ -- 5 MHz PLL output from XO reference
+ constant c_mm_clk_period : time := c_xo_clk_period / 5;
constant c_mm_locked_time : time := 10 us;
- constant c_pulse_us : natural := 5; -- nof 5 MHz clk cycles to get us period
- constant c_pulse_ms : natural := 1000 / c_scale; -- nof pulse_us pulses to get ms period
- constant c_pulse_s : natural := 1000; -- nof pulse_ms pulses to get s period
+ -- nof 5 MHz clk cycles to get us period
+ constant c_pulse_us : natural := 5;
+ -- nof pulse_us pulses to get ms period
+ constant c_pulse_ms : natural := 1000 / c_scale;
+ -- nof pulse_ms pulses to get s period
+ constant c_pulse_s : natural := 1000;
- constant c_wdi_extend_w : natural := 14; -- extend wdi by about 2**(14-1)= 8 s (as defined by c_pulse_ms)
- constant c_wdi_period : time := 1000 ms; -- wdi toggle after c_wdi_period
+ -- extend wdi by about 2**(14-1)= 8 s (as defined by c_pulse_ms)
+ constant c_wdi_extend_w : natural := 14;
+ -- wdi toggle after c_wdi_period
+ constant c_wdi_period : time := 1000 ms;
-- Use c_sw_period=40000 ms to show that the c_wdi_extend_w=5 is not enough, the WD will kick in when the sw is off during reload
- constant c_sw_period : time := 40000 ms; -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
+ -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
+ constant c_sw_period : time := 40000 ms;
-- Use c_sw_period=10000 ms to show that the c_wdi_extend_w=5 is enough, the WD will not kick in when the sw is off during reload
--CONSTANT c_sw_period : TIME := 6000 ms; -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
@@ -65,10 +74,13 @@ begin
mm_clk <= not mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_locked_time;
- wdi <= not wdi after c_wdi_period / c_scale; -- wd interrupt
- sw <= not sw after c_sw_period / c_scale; -- sw active / reload
+ -- wd interrupt
+ wdi <= not wdi after c_wdi_period / c_scale;
+ -- sw active / reload
+ sw <= not sw after c_sw_period / c_scale;
- wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
+ -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
+ wdi_in <= wdi and sw;
dut : entity work.unb2c_board_node_ctrl
generic map (
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
index 9ee6059b7f62c1dc5c3ae93cc12772da27049228..a1231253d12870a2c835135e8ac053217431155e 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
@@ -140,10 +140,14 @@ begin
u_unb2c_factory_qsfp_leds : entity work.unb2c_board_qsfp_leds
generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ -- when true speed up led toggling in simulation
+ g_sim => true,
+ -- distinguish factory image and user images
+ g_factory_image => true,
+ -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_nof_qsfp => c_nof_qsfp,
+ -- nof clk cycles to get us period
+ g_pulse_us => c_nof_clk_per_us
)
port map (
rst => rst,
@@ -163,10 +167,14 @@ begin
u_unb2c_user_qsfp_leds : entity work.unb2c_board_qsfp_leds
generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ -- when true speed up led toggling in simulation
+ g_sim => true,
+ -- distinguish factory image and user images
+ g_factory_image => false,
+ -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_nof_qsfp => c_nof_qsfp,
+ -- nof clk cycles to get us period
+ g_pulse_us => c_nof_clk_per_us
)
port map (
rst => rst,
diff --git a/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd b/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
index 92199c7404a1380dffa28b1478c66a69c87469fc..fd86aafcb5bc81b8716e36b65083275b9a2aa5bf 100644
--- a/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
@@ -30,14 +30,19 @@ use technology_lib.technology_pkg.all;
entity unb2c_board_10gbe is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 1; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 1;
g_technology : natural := c_tech_arria10_e2sg;
g_nof_macs : natural;
g_use_loopback : boolean := false;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
- g_tx_fifo_fill : natural := 10; -- Release tx packet only when sufficiently data is available,
- g_tx_fifo_size : natural := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
- g_rx_fifo_size : natural := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
+ -- Release tx packet only when sufficiently data is available,
+ g_tx_fifo_fill : natural := 10;
+ -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ g_tx_fifo_size : natural := 256;
+ -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ g_rx_fifo_size : natural := 256;
g_word_alignment_padding : boolean := false
);
port (
@@ -50,7 +55,8 @@ entity unb2c_board_10gbe is
reg_mac_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_mac_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi := c_mem_mosi_rst; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_eth10g_miso : out t_mem_miso;
reg_10gbase_r_24_mosi : in t_mem_mosi := c_mem_mosi_rst;
@@ -104,9 +110,12 @@ begin
port map (
-- Transceiver PLL reference clock
tr_ref_clk_644 => tr_ref_clk,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => tr_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => tr_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156,
-- MM interface
mm_rst => mm_rst,
diff --git a/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
index e95d9eaf75c95c18f69917a472c173b12a9cfdf2..d90ee7bf4ccc8d486766c68618bc11ad9ed4ba8b 100644
--- a/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
@@ -42,14 +42,18 @@ use work.axi4_lite_pkg.all;
entity axi4_lite_mm_bridge is
generic (
- g_active_low_rst : boolean := false -- When True, in_rst is interpreted as active-low.
+ -- When True, in_rst is interpreted as active-low.
+ g_active_low_rst : boolean := false
);
port (
in_clk : in std_logic := '0';
- in_rst : in std_logic := is_true(g_active_low_rst); -- Default state is "not in reset".
+ -- Default state is "not in reset".
+ in_rst : in std_logic := is_true(g_active_low_rst);
- aresetn : out std_logic := '1'; -- AXI4 active-low reset
- mm_rst : out std_logic := '0'; -- MM active-high reset
+ -- AXI4 active-low reset
+ aresetn : out std_logic := '1';
+ -- MM active-high reset
+ mm_rst : out std_logic := '0';
-- Translate AXI4 lite to MM
axi4_in_copi : in t_axi4_lite_copi := c_axi4_lite_copi_rst;
diff --git a/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
index 6f94af5302e237eaadbc1ee564b4dd6f46f381c3..05c1687c17b8a262f14dfe78edf4f7096c6c7a12 100644
--- a/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
@@ -44,39 +44,60 @@ package axi4_lite_pkg is
constant c_axi4_lite_prot_w : natural := 3;
constant c_axi4_lite_resp_w : natural := 2;
- type t_axi4_lite_copi is record -- Controller Out Peripheral In
+ -- Controller Out Peripheral In
+ type t_axi4_lite_copi is record
-- write address channel
- awaddr : std_logic_vector(c_axi4_lite_address_w - 1 downto 0); -- write address
- awprot : std_logic_vector(c_axi4_lite_prot_w - 1 downto 0); -- access permission for write
- awvalid : std_logic; -- write address valid
+ -- write address
+ awaddr : std_logic_vector(c_axi4_lite_address_w - 1 downto 0);
+ -- access permission for write
+ awprot : std_logic_vector(c_axi4_lite_prot_w - 1 downto 0);
+ -- write address valid
+ awvalid : std_logic;
-- write data channel
- wdata : std_logic_vector(c_axi4_lite_data_w - 1 downto 0); -- write data
- wstrb : std_logic_vector((c_axi4_lite_data_w / c_byte_w) - 1 downto 0); -- write strobes
- wvalid : std_logic; -- write valid
+ -- write data
+ wdata : std_logic_vector(c_axi4_lite_data_w - 1 downto 0);
+ -- write strobes
+ wstrb : std_logic_vector((c_axi4_lite_data_w / c_byte_w) - 1 downto 0);
+ -- write valid
+ wvalid : std_logic;
-- write response channel
- bready : std_logic; -- response ready
+ -- response ready
+ bready : std_logic;
-- read address channel
- araddr : std_logic_vector(c_axi4_lite_address_w - 1 downto 0); -- read address
- arprot : std_logic_vector(c_axi4_lite_prot_w - 1 downto 0); -- access permission for read
- arvalid : std_logic; -- read address valid
+ -- read address
+ araddr : std_logic_vector(c_axi4_lite_address_w - 1 downto 0);
+ -- access permission for read
+ arprot : std_logic_vector(c_axi4_lite_prot_w - 1 downto 0);
+ -- read address valid
+ arvalid : std_logic;
-- read data channel
- rready : std_logic; -- read ready
+ -- read ready
+ rready : std_logic;
end record;
- type t_axi4_lite_cipo is record -- Controller In Peripheral Out
+ -- Controller In Peripheral Out
+ type t_axi4_lite_cipo is record
-- write_address channel
- awready : std_logic; -- write address ready
+ -- write address ready
+ awready : std_logic;
-- write data channel
- wready : std_logic; -- write ready
+ -- write ready
+ wready : std_logic;
-- write response channel
- bresp : std_logic_vector(c_axi4_lite_resp_w - 1 downto 0); -- write response
- bvalid : std_logic; -- write response valid
+ -- write response
+ bresp : std_logic_vector(c_axi4_lite_resp_w - 1 downto 0);
+ -- write response valid
+ bvalid : std_logic;
-- read address channel
- arready : std_logic; -- read address ready
+ -- read address ready
+ arready : std_logic;
-- read data channel
- rdata : std_logic_vector(c_axi4_lite_data_w - 1 downto 0); -- read data
- rresp : std_logic_vector(c_axi4_lite_resp_w - 1 downto 0); -- read response
- rvalid : std_logic; -- read valid
+ -- read data
+ rdata : std_logic_vector(c_axi4_lite_data_w - 1 downto 0);
+ -- read response
+ rresp : std_logic_vector(c_axi4_lite_resp_w - 1 downto 0);
+ -- read valid
+ rvalid : std_logic;
end record;
constant c_axi4_lite_copi_rst : t_axi4_lite_copi := ((others => '0'), (others => '0'), '0', (others => '0'), (others => '0'), '0', '0', (others => '0'), (others => '0'), '0', '0');
@@ -86,10 +107,14 @@ package axi4_lite_pkg is
type t_axi4_lite_cipo_arr is array (integer range <>) of t_axi4_lite_cipo;
type t_axi4_lite_copi_arr is array (integer range <>) of t_axi4_lite_copi;
- constant c_axi4_lite_resp_okay : std_logic_vector(c_axi4_lite_resp_w - 1 downto 0) := "00"; -- normal access success
- constant c_axi4_lite_resp_exokay : std_logic_vector(c_axi4_lite_resp_w - 1 downto 0) := "01"; -- exclusive access okay
- constant c_axi4_lite_resp_slverr : std_logic_vector(c_axi4_lite_resp_w - 1 downto 0) := "10"; -- peripheral error
- constant c_axi4_lite_resp_decerr : std_logic_vector(c_axi4_lite_resp_w - 1 downto 0) := "11"; -- decode error
+ -- normal access success
+ constant c_axi4_lite_resp_okay : std_logic_vector(c_axi4_lite_resp_w - 1 downto 0) := "00";
+ -- exclusive access okay
+ constant c_axi4_lite_resp_exokay : std_logic_vector(c_axi4_lite_resp_w - 1 downto 0) := "01";
+ -- peripheral error
+ constant c_axi4_lite_resp_slverr : std_logic_vector(c_axi4_lite_resp_w - 1 downto 0) := "10";
+ -- decode error
+ constant c_axi4_lite_resp_decerr : std_logic_vector(c_axi4_lite_resp_w - 1 downto 0) := "11";
-- Functions to convert axi4-lite to MM.
function func_axi4_lite_to_mm_copi(axi4_copi : t_axi4_lite_copi) return t_mem_copi;
@@ -106,9 +131,11 @@ package body axi4_lite_pkg is
variable v_mm_copi : t_mem_copi := c_mem_copi_rst;
begin
if axi4_copi.awvalid = '1' then
- v_mm_copi.address := "00" & axi4_copi.awaddr(c_axi4_lite_address_w - 1 downto 2); -- convert byte addressed to word addressed.
+ -- convert byte addressed to word addressed.
+ v_mm_copi.address := "00" & axi4_copi.awaddr(c_axi4_lite_address_w - 1 downto 2);
else
- v_mm_copi.address := "00" & axi4_copi.araddr(c_axi4_lite_address_w - 1 downto 2); -- convert byte addressed to word addressed.
+ -- convert byte addressed to word addressed.
+ v_mm_copi.address := "00" & axi4_copi.araddr(c_axi4_lite_address_w - 1 downto 2);
end if;
v_mm_copi.wrdata(c_axi4_lite_data_w - 1 downto 0) := axi4_copi.wdata;
@@ -129,17 +156,22 @@ package body axi4_lite_pkg is
function func_axi4_lite_from_mm_copi(mm_copi : t_mem_copi) return t_axi4_lite_copi is
variable v_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
begin
- v_axi4_copi.awaddr := mm_copi.address(c_axi4_lite_address_w - 3 downto 0) & "00"; -- convert word addressed to byte addressed.
+ -- convert word addressed to byte addressed.
+ v_axi4_copi.awaddr := mm_copi.address(c_axi4_lite_address_w - 3 downto 0) & "00";
v_axi4_copi.awprot := (others => '0');
v_axi4_copi.awvalid := mm_copi.wr;
v_axi4_copi.wdata := mm_copi.wrdata(c_axi4_lite_data_w - 1 downto 0);
- v_axi4_copi.wstrb := (others => '1'); -- Either ignored or all bytes selected.
+ -- Either ignored or all bytes selected.
+ v_axi4_copi.wstrb := (others => '1');
v_axi4_copi.wvalid := mm_copi.wr;
- v_axi4_copi.bready := '1'; -- Unsupported by MM, assuming always ready.
- v_axi4_copi.araddr := mm_copi.address(c_axi4_lite_address_w - 3 downto 0) & "00"; -- convert word addressed to byte addressed.
+ -- Unsupported by MM, assuming always ready.
+ v_axi4_copi.bready := '1';
+ -- convert word addressed to byte addressed.
+ v_axi4_copi.araddr := mm_copi.address(c_axi4_lite_address_w - 3 downto 0) & "00";
v_axi4_copi.arprot := (others => '0');
v_axi4_copi.arvalid := mm_copi.rd;
- v_axi4_copi.rready := '1'; -- Unsupported by MM, assuming always ready.
+ -- Unsupported by MM, assuming always ready.
+ v_axi4_copi.rready := '1';
return v_axi4_copi;
end;
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
index 35b1086347c509af47361b9e044acf0ed57cf023..cfd6aa842113c2fec390f315b369a681e1c4d262 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
@@ -55,18 +55,24 @@ use work.axi4_stream_pkg.all;
entity axi4_stream_dp_bridge is
generic (
- g_nof_bytes : natural := 64; -- Max = 64 bytes
- g_use_empty : boolean := false; -- When True the dp empty field is derived from axi4 tkeep.
+ -- Max = 64 bytes
+ g_nof_bytes : natural := 64;
+ -- When True the dp empty field is derived from axi4 tkeep.
+ g_use_empty : boolean := false;
g_axi4_rl : natural := 0;
g_dp_rl : natural := 1;
- g_active_low_rst : boolean := false -- When True, in_rst is interpreted as active-low.
+ -- When True, in_rst is interpreted as active-low.
+ g_active_low_rst : boolean := false
);
port (
in_clk : in std_logic := '0';
- in_rst : in std_logic := is_true(g_active_low_rst); -- Default state is "not in reset".
+ -- Default state is "not in reset".
+ in_rst : in std_logic := is_true(g_active_low_rst);
- aresetn : out std_logic := '1'; -- AXI4 active-low reset
- dp_rst : out std_logic := '0'; -- DP active-high reset
+ -- AXI4 active-low reset
+ aresetn : out std_logic := '1';
+ -- DP active-high reset
+ dp_rst : out std_logic := '0';
axi4_in_sosi : in t_axi4_sosi := c_axi4_sosi_rst;
axi4_in_siso : out t_axi4_siso := c_axi4_siso_rst;
@@ -83,7 +89,8 @@ entity axi4_stream_dp_bridge is
end axi4_stream_dp_bridge;
architecture str of axi4_stream_dp_bridge is
- signal i_rst : std_logic := '0'; -- Internal active high reset.
+ -- Internal active high reset.
+ signal i_rst : std_logic := '0';
signal axi4_from_dp_sosi : t_dp_sosi;
signal axi4_from_dp_siso : t_dp_siso;
@@ -137,10 +144,12 @@ begin
variable v : t_reg := c_reg_init;
begin
v := q_reg;
- v.dp_from_axi4_sosi := func_axi4_stream_to_dp_sosi(axi4_in_sosi); -- Does not have sop or empty yet.
+ -- Does not have sop or empty yet.
+ v.dp_from_axi4_sosi := func_axi4_stream_to_dp_sosi(axi4_in_sosi);
-- Generate sop on first valid after eop.
- if axi4_in_sosi.tvalid = '1' and g_axi4_rl = 1 then -- axi4 ready latency = 1
+ -- axi4 ready latency = 1
+ if axi4_in_sosi.tvalid = '1' and g_axi4_rl = 1 then
if axi4_in_sosi.tlast = '1' then
v.r_eop := '1';
elsif q_reg.r_eop = '1' then
@@ -150,7 +159,8 @@ begin
v.dp_from_axi4_sosi.sop := '0';
end if;
- elsif axi4_in_sosi.tvalid = '1' and g_axi4_rl = 0 then -- axi4 ready latency = 0
+ -- axi4 ready latency = 0
+ elsif axi4_in_sosi.tvalid = '1' and g_axi4_rl = 0 then
if axi4_in_sosi.tlast = '1' and dp_from_axi4_siso.ready = '1' then
v.r_eop := '1';
elsif q_reg.r_eop = '1' and dp_from_axi4_siso.ready = '1' then
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
index 713f1ed150006f96a432c5605bc1b224c6c52d85..54e7fe4ed84c3746000c6c8c639be8829714838c 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
@@ -53,26 +53,43 @@ use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
package axi4_stream_pkg is
- constant c_axi4_stream_data_w : natural := 512; -- Data width, upto 512bit for Xilinx IP
- constant c_axi4_stream_user_w : natural := 70; -- User data, upto 70bit for Xilinx IP
- constant c_axi4_stream_tid_w : natural := 4; -- Thread ID, upto 4bit for Xilinx IP
- constant c_axi4_stream_dest_w : natural := 32; -- Routing data, upto 32bit for Xilinx IP
- constant c_axi4_stream_keep_w : natural := c_axi4_stream_data_w / 8; -- 1 bit for each byte in data.
- constant c_axi4_stream_strb_w : natural := c_axi4_stream_data_w / 8; -- 1 bit for each byte in daya.
-
- type t_axi4_siso is record -- Source In and Sink Out
- tready : std_logic; -- Ready to accept data from destination
+ -- Data width, upto 512bit for Xilinx IP
+ constant c_axi4_stream_data_w : natural := 512;
+ -- User data, upto 70bit for Xilinx IP
+ constant c_axi4_stream_user_w : natural := 70;
+ -- Thread ID, upto 4bit for Xilinx IP
+ constant c_axi4_stream_tid_w : natural := 4;
+ -- Routing data, upto 32bit for Xilinx IP
+ constant c_axi4_stream_dest_w : natural := 32;
+ -- 1 bit for each byte in data.
+ constant c_axi4_stream_keep_w : natural := c_axi4_stream_data_w / 8;
+ -- 1 bit for each byte in daya.
+ constant c_axi4_stream_strb_w : natural := c_axi4_stream_data_w / 8;
+
+ -- Source In and Sink Out
+ type t_axi4_siso is record
+ -- Ready to accept data from destination
+ tready : std_logic;
end record;
- type t_axi4_sosi is record -- Source Out and Sink In
- tvalid : std_logic; -- Data valid
- tdata : std_logic_vector(c_axi4_stream_data_w - 1 downto 0); -- Data bus
- tstrb : std_logic_vector(c_axi4_stream_strb_w - 1 downto 0); -- Byte valids, indicates if data is position (0) or data (1). Generally not used
- tkeep : std_logic_vector(c_axi4_stream_keep_w - 1 downto 0); -- Indicate valid data bytes (1) or null bytes (0).
- tlast : std_logic; -- Last transaction in a burst
- tid : std_logic_vector(c_axi4_stream_tid_w - 1 downto 0); -- Transaction ID
- tdest : std_logic_vector(c_axi4_stream_dest_w - 1 downto 0); -- Destination rounting information
- tuser : std_logic_vector(c_axi4_stream_user_w - 1 downto 0); -- Tranaction user fields
+ -- Source Out and Sink In
+ type t_axi4_sosi is record
+ -- Data valid
+ tvalid : std_logic;
+ -- Data bus
+ tdata : std_logic_vector(c_axi4_stream_data_w - 1 downto 0);
+ -- Byte valids, indicates if data is position (0) or data (1). Generally not used
+ tstrb : std_logic_vector(c_axi4_stream_strb_w - 1 downto 0);
+ -- Indicate valid data bytes (1) or null bytes (0).
+ tkeep : std_logic_vector(c_axi4_stream_keep_w - 1 downto 0);
+ -- Last transaction in a burst
+ tlast : std_logic;
+ -- Transaction ID
+ tid : std_logic_vector(c_axi4_stream_tid_w - 1 downto 0);
+ -- Destination rounting information
+ tdest : std_logic_vector(c_axi4_stream_dest_w - 1 downto 0);
+ -- Tranaction user fields
+ tuser : std_logic_vector(c_axi4_stream_user_w - 1 downto 0);
end record;
-- Initialise signal declarations with c_axi4_stream_rst/rdy to ease the interpretation of slv fields with unused bits
@@ -226,7 +243,8 @@ package body axi4_stream_pkg is
signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
- ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).tready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
+ -- SLV is used as an array: nof_streams*(0..c_ready_latency)
+ ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).tready;
end loop;
-- Register siso.ready in c_ready_latency registers
if rising_edge(clk) then
@@ -256,8 +274,10 @@ package body axi4_stream_pkg is
begin
assert nof_symbols_from_tail < vN report "func_axi4_data_shift_first : no symbols from head" severity FAILURE;
-- use the other sosi from head_sosi
- v_sosi := head_sosi; -- I = nof_symbols_from_tail = 0
- for I in 1 to vN - 1 loop -- I > 0
+ -- I = nof_symbols_from_tail = 0
+ v_sosi := head_sosi;
+ -- I > 0
+ for I in 1 to vN - 1 loop
if nof_symbols_from_tail = I then
v_sosi.tdata(I * symbol_w - 1 downto 0) := tail_sosi.tdata(vN * symbol_w - 1 downto (vN - I) * symbol_w);
end if;
@@ -279,15 +299,18 @@ package body axi4_stream_pkg is
end if;
-- use sosi data from both if 0 < nof_symbols_from_this < nof_symbols_per_data (i.e. 0 < I < vN)
- if vK < nof_symbols_per_data then -- I = vK = nof_symbols_from_this < vN
+ -- I = vK = nof_symbols_from_this < vN
+ if vK < nof_symbols_per_data then
-- Implementation using variable vK directly instead of via I in a LOOP
-- IF vK > 0 THEN
-- v_sosi.data(vN*symbol_w-1 DOWNTO vK*symbol_w) := prev_sosi.data((vN-vK)*symbol_w-1 DOWNTO 0);
-- v_sosi.data( vK*symbol_w-1 DOWNTO 0) := this_sosi.data( vN *symbol_w-1 DOWNTO (vN-vK)*symbol_w);
-- END IF;
-- Implementaion using LOOP vK rather than VARIABLE vK directly as index to help synthesis and avoid potential multiplier
- v_sosi.tdata := prev_sosi.tdata; -- I = vK = nof_symbols_from_this = 0
- for I in 1 to vN - 1 loop -- I = vK = nof_symbols_from_this > 0
+ -- I = vK = nof_symbols_from_this = 0
+ v_sosi.tdata := prev_sosi.tdata;
+ -- I = vK = nof_symbols_from_this > 0
+ for I in 1 to vN - 1 loop
if vK = I then
v_sosi.tdata(vN * symbol_w - 1 downto I * symbol_w) := prev_sosi.tdata((vN - I) * symbol_w - 1 downto 0);
v_sosi.tdata( I * symbol_w - 1 downto 0) := this_sosi.tdata( vN * symbol_w - 1 downto (vN - I) * symbol_w);
@@ -367,7 +390,8 @@ package body axi4_stream_pkg is
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_axi4_*_arr (for all elements or only for the mask[]='1' elements)
function func_axi4_stream_arr_and(axi4 : t_axi4_siso_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(axi4'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(axi4'range) := (others => '1');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -381,14 +405,17 @@ package body axi4_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_and(v_vec); -- return AND of the masked input fields
+ -- return AND of the masked input fields
+ return vector_and(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_axi4_stream_arr_and;
function func_axi4_stream_arr_and(axi4 : t_axi4_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(axi4'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(axi4'range) := (others => '1');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -402,9 +429,11 @@ package body axi4_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_and(v_vec); -- return AND of the masked input fields
+ -- return AND of the masked input fields
+ return vector_and(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_axi4_stream_arr_and;
@@ -421,7 +450,8 @@ package body axi4_stream_pkg is
end func_axi4_stream_arr_and;
function func_axi4_stream_arr_or(axi4 : t_axi4_siso_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(axi4'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(axi4'range) := (others => '0');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -435,14 +465,17 @@ package body axi4_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_or(v_vec); -- return OR of the masked input fields
+ -- return OR of the masked input fields
+ return vector_or(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_axi4_stream_arr_or;
function func_axi4_stream_arr_or(axi4 : t_axi4_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(axi4'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(axi4'range) := (others => '0');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -456,9 +489,11 @@ package body axi4_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_or(v_vec); -- return OR of the masked input fields
+ -- return OR of the masked input fields
+ return vector_or(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_axi4_stream_arr_or;
@@ -476,8 +511,10 @@ package body axi4_stream_pkg is
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
function func_axi4_stream_arr_set(axi4 : t_axi4_siso_arr; slv : std_logic_vector; str : string) return t_axi4_siso_arr is
- variable v_axi4 : t_axi4_siso_arr(axi4'range) := axi4; -- default
- variable v_slv : std_logic_vector(axi4'range) := slv; -- map to ensure same range as for axi4
+ -- default
+ variable v_axi4 : t_axi4_siso_arr(axi4'range) := axi4;
+ -- map to ensure same range as for axi4
+ variable v_slv : std_logic_vector(axi4'range) := slv;
begin
for I in axi4'range loop
if str = "READY" then v_axi4(I).tready := v_slv(I);
@@ -488,8 +525,10 @@ package body axi4_stream_pkg is
end func_axi4_stream_arr_set;
function func_axi4_stream_arr_set(axi4 : t_axi4_sosi_arr; slv : std_logic_vector; str : string) return t_axi4_sosi_arr is
- variable v_axi4 : t_axi4_sosi_arr(axi4'range) := axi4; -- default
- variable v_slv : std_logic_vector(axi4'range) := slv; -- map to ensure same range as for axi4
+ -- default
+ variable v_axi4 : t_axi4_sosi_arr(axi4'range) := axi4;
+ -- map to ensure same range as for axi4
+ variable v_slv : std_logic_vector(axi4'range) := slv;
begin
for I in axi4'range loop
if str = "VALID" then v_axi4(I).tvalid := v_slv(I);
@@ -674,9 +713,11 @@ package body axi4_stream_pkg is
-- Functions to combinatorially hold the data fields and to set or reset the control fields in an sosi array
function func_axi4_stream_arr_set_control(axi4 : t_axi4_sosi_arr; ctrl : t_axi4_sosi) return t_axi4_sosi_arr is
- variable v_axi4 : t_axi4_sosi_arr(axi4'range) := axi4; -- hold sosi data
+ -- hold sosi data
+ variable v_axi4 : t_axi4_sosi_arr(axi4'range) := axi4;
begin
- for I in axi4'range loop -- set sosi control
+ -- set sosi control
+ for I in axi4'range loop
v_axi4(I).tvalid := ctrl.tvalid;
v_axi4(I).tuser := ctrl.tuser;
v_axi4(I).tdest := ctrl.tdest;
@@ -685,9 +726,11 @@ package body axi4_stream_pkg is
end func_axi4_stream_arr_set_control;
function func_axi4_stream_arr_reset_control(axi4 : t_axi4_sosi_arr) return t_axi4_sosi_arr is
- variable v_axi4 : t_axi4_sosi_arr(axi4'range) := axi4; -- hold sosi data
+ -- hold sosi data
+ variable v_axi4 : t_axi4_sosi_arr(axi4'range) := axi4;
begin
- for I in axi4'range loop -- reset sosi control
+ -- reset sosi control
+ for I in axi4'range loop
v_axi4(I).tvalid := '0';
end loop;
return v_axi4;
@@ -701,8 +744,10 @@ package body axi4_stream_pkg is
variable v_keep : std_logic_vector(c_axi4_stream_keep_w - 1 downto 0) := (others => '1');
begin
v_empty_int := TO_UINT(dp_sosi.empty(c_max_empty_w - 1 downto 0));
- if dp_sosi.eop = '1' then -- empty is only valid on eop
- v_keep(v_empty_int - 1 downto 0) := (others => '0'); -- Keep is one hot encoded.
+ -- empty is only valid on eop
+ if dp_sosi.eop = '1' then
+ -- Keep is one hot encoded.
+ v_keep(v_empty_int - 1 downto 0) := (others => '0');
else
v_keep := (others => '1');
end if;
@@ -732,7 +777,8 @@ package body axi4_stream_pkg is
begin
v_dp_sosi.data(c_axi4_stream_data_w - 1 downto 0) := axi4_sosi.tdata;
v_dp_sosi.valid := axi4_sosi.tvalid;
- v_dp_sosi.sop := '0'; -- Should be generated (first valid after eop).
+ -- Should be generated (first valid after eop).
+ v_dp_sosi.sop := '0';
v_dp_sosi.eop := axi4_sosi.tlast;
-- Cannot always derive from tkeep as it can have any bytes (not just the last bytes)
diff --git a/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
index d4cc4a03ccb806bb9eec3cd9fd20759ea80e4d95..d9bdc0b49c8e355d844d1a4fe44db087edd706ca 100644
--- a/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
@@ -66,7 +66,8 @@ architecture tb of tb_axi4_lite_mm_bridge is
dat_w => 8,
nof_dat => 32,
init_sl => '0');
- constant c_offset : natural := 57; -- Some value to offset the counter data written to ram.
+ -- Some value to offset the counter data written to ram.
+ constant c_offset : natural := 57;
signal mm_rst : std_logic;
signal mm_clk : std_logic := '0';
diff --git a/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
index ca7be826cff4b337bf5af9b2cbf58ae17568e978..d72c45eb77d8532043b8f8828bc5256fced82bd5 100644
--- a/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
@@ -42,16 +42,21 @@ end tb_axi4_stream_dp_bridge;
architecture tb of tb_axi4_stream_dp_bridge is
-- TX ready latency to DUT chain
- constant c_tx_void : natural := sel_a_b(g_dp_rl, 1, 0); -- used to avoid empty range VHDL warnings when g_dp_rl=0
+ -- used to avoid empty range VHDL warnings when g_dp_rl=0
+ constant c_tx_void : natural := sel_a_b(g_dp_rl, 1, 0);
constant c_tx_offset_sop : natural := 0;
- constant c_tx_period_sop : natural := 7; -- sop in data valid cycle 0, 7, 14, ...
- constant c_tx_offset_eop : natural := 6; -- eop in data valid cycle 6, 13, 20, ...
+ -- sop in data valid cycle 0, 7, 14, ...
+ constant c_tx_period_sop : natural := 7;
+ -- eop in data valid cycle 6, 13, 20, ...
+ constant c_tx_offset_eop : natural := 6;
constant c_tx_period_eop : natural := c_tx_period_sop;
- constant c_tx_offset_sync : natural := 3; -- sync in data valid cycle 3, 20, 37, ...
+ -- sync in data valid cycle 3, 20, 37, ...
+ constant c_tx_offset_sync : natural := 3;
constant c_tx_period_sync : natural := 17;
- constant c_verify_en_wait : natural := 10; -- wait some cycles before asserting verify enable
+ -- wait some cycles before asserting verify enable
+ constant c_verify_en_wait : natural := 10;
constant c_empty_offset : natural := 1;
constant c_channel_offset : natural := 2;
@@ -140,7 +145,8 @@ begin
proc_dp_verify_valid(g_dp_rl, clk, verify_en, out_ready, prev_out_ready, out_val);
proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", clk, verify_en, out_data, out_val, out_sop);
proc_dp_verify_ctrl(c_tx_offset_eop, c_tx_period_eop, "eop", clk, verify_en, out_data, out_val, out_eop);
- proc_dp_verify_sop_and_eop(g_dp_rl, false, clk, out_ready, out_val, out_sop, out_eop, hold_out_sop); -- Verify that sop and eop come in pairs, no check on valid between eop and sop
+ -- Verify that sop and eop come in pairs, no check on valid between eop and sop
+ proc_dp_verify_sop_and_eop(g_dp_rl, false, clk, out_ready, out_val, out_sop, out_eop, hold_out_sop);
exp_empty <= RESIZE_UVEC(INCR_UVEC(out_data, c_empty_offset)(c_max_empty_w - 1 downto 0), c_dp_empty_w) when out_eop = '1' else (others => '0');
exp_channel <= RESIZE_UVEC(INCR_UVEC(out_data, c_channel_offset)(c_max_channel_w - 1 downto 0), c_dp_channel_w);
@@ -154,8 +160,10 @@ begin
-- DUT
------------------------------------------------------------------------------
-- map sl, slv to record
- in_ready <= dut_siso.ready; -- SISO
- dut_sosi.data(c_dp_data_w - 1 downto 0) <= in_data; -- SOSI
+ -- SISO
+ in_ready <= dut_siso.ready;
+ -- SOSI
+ dut_sosi.data(c_dp_data_w - 1 downto 0) <= in_data;
dut_sosi.empty <= in_empty;
dut_sosi.channel <= in_channel;
dut_sosi.sync <= in_sync;
@@ -186,8 +194,10 @@ begin
);
-- map record to sl, slv
- dut_out_siso.ready <= out_ready; -- SISO
- out_data <= dut_out_sosi.data(c_dp_data_w - 1 downto 0); -- SOSI
+ -- SISO
+ dut_out_siso.ready <= out_ready;
+ -- SOSI
+ out_data <= dut_out_sosi.data(c_dp_data_w - 1 downto 0);
out_empty(c_dp_empty_w - 1 downto 0) <= dut_out_sosi.empty;
out_channel(c_dp_channel_w - 1 downto 0) <= dut_out_sosi.channel;
out_sync <= dut_out_sosi.sync;
diff --git a/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
index 28f6ea68f5fde2c46683b3d4ba106953bf33f54e..86e030a8fbc5d2129a58728d3b3577925e457c96 100644
--- a/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
@@ -31,7 +31,8 @@ entity tb_tb_axi4_stream_dp_bridge is
end tb_tb_axi4_stream_dp_bridge;
architecture tb of tb_tb_axi4_stream_dp_bridge is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 2
-- > run -all --> OK
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd b/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
index 1f9b9ac8d31a13d1c3507010069245c86a3f0cb6..8b57c2db41bcc860ac77cb7fb37e3ede4cb5a15f 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
@@ -73,5 +73,6 @@ begin
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
- ins_interrupt_irq <= coe_irq_export; -- can not use coe_interrupt_export as name, because *_interrupt_* is already the MM side name
+ -- can not use coe_interrupt_export as name, because *_interrupt_* is already the MM side name
+ ins_interrupt_irq <= coe_irq_export;
end wrap;
diff --git a/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
index bdf118db203240608da8269776a38fd9b01df640..faec557084a37fb81d811310152da1fe6d192b1a 100644
--- a/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
@@ -35,7 +35,8 @@ use IEEE.std_logic_1164.all;
use work.common_mem_pkg.all;
entity avs_common_ram_crw_crw is
- generic ( -- t_c_mem := (c_mem_ram_rd_latency, 10, 9, 2**10, 'X'); -- 1 M9K
+ -- t_c_mem := (c_mem_ram_rd_latency, 10, 9, 2**10, 'X'); -- 1 M9K
+ generic (
g_latency : natural := c_mem_ram_rd_latency;
g_adr_w : natural := 10;
g_dat_w : natural := 9;
diff --git a/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd b/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
index dda794990475e9aefaf176f3c733ca25536ea4f0..0556cfa04d0ebec794b4324b1af9cdff27fba2ef 100644
--- a/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
@@ -37,11 +37,14 @@ use work.common_mem_pkg.all;
entity avs_common_reg_r_w is
generic (
- g_latency : natural := 1; -- read latency
+ -- read latency
+ g_latency : natural := 1;
g_adr_w : natural := 5;
g_dat_w : natural := 32;
- g_nof_dat : natural := 32; -- optional, nof dat words <= 2**adr_w
- g_init_sl : std_logic := '0'; -- optional, init all dat words to std_logic '0', '1' or 'X'
+ -- optional, nof dat words <= 2**adr_w
+ g_nof_dat : natural := 32;
+ -- optional, init all dat words to std_logic '0', '1' or 'X'
+ g_init_sl : std_logic := '0';
g_init_reg : std_logic_vector(c_mem_reg_init_w - 1 downto 0) := (others => '0')
);
port (
diff --git a/libraries/base/common/src/vhdl/common_acapture.vhd b/libraries/base/common/src/vhdl/common_acapture.vhd
index cd7ccca147cefb9c3a43031cac01e9f006b9feb4..60d2e676943e1d52ffb7f05ff0e4c3d5574321fd 100644
--- a/libraries/base/common/src/vhdl/common_acapture.vhd
+++ b/libraries/base/common/src/vhdl/common_acapture.vhd
@@ -44,14 +44,17 @@ use common_lib.common_pkg.all;
entity common_acapture is
generic (
g_rst_level : std_logic := '0';
- g_in_delay_len : positive := 1; -- = 1, typically fixed
- g_out_delay_len : positive := 1 -- >= 1, e.g. use c_meta_delay_len
+ -- = 1, typically fixed
+ g_in_delay_len : positive := 1;
+ -- >= 1, e.g. use c_meta_delay_len
+ g_out_delay_len : positive := 1
);
port (
in_rst : in std_logic := '0';
in_clk : in std_logic;
in_dat : in std_logic;
- in_cap : out std_logic; -- typically leave OPEN, available only for monitoring with common_acapture_slv
+ -- typically leave OPEN, available only for monitoring with common_acapture_slv
+ in_cap : out std_logic;
out_clk : in std_logic;
out_cap : out std_logic
);
diff --git a/libraries/base/common/src/vhdl/common_acapture_slv.vhd b/libraries/base/common/src/vhdl/common_acapture_slv.vhd
index 04aa1970550e15f5ae0aececbf10ef805c9ac595..9056798aceb27892dba991f8d7d5cb57ba40fbf2 100644
--- a/libraries/base/common/src/vhdl/common_acapture_slv.vhd
+++ b/libraries/base/common/src/vhdl/common_acapture_slv.vhd
@@ -33,8 +33,10 @@ use common_lib.common_pkg.all;
entity common_acapture_slv is
generic (
g_rst_level : std_logic := '0';
- g_in_delay_len : positive := 1; -- = 1, typically fixed
- g_out_delay_len : positive := 1 -- >= 1, e.g. use c_meta_delay_len
+ -- = 1, typically fixed
+ g_in_delay_len : positive := 1;
+ -- >= 1, e.g. use c_meta_delay_len
+ g_out_delay_len : positive := 1
);
port (
in_rst : in std_logic := '0';
diff --git a/libraries/base/common/src/vhdl/common_accumulate.vhd b/libraries/base/common/src/vhdl/common_accumulate.vhd
index f891ae560a8572449a100e2decf05c2ba05d161f..c8bf363dbed86084094ecd2bf6eb0a94fb27d8a9 100644
--- a/libraries/base/common/src/vhdl/common_accumulate.vhd
+++ b/libraries/base/common/src/vhdl/common_accumulate.vhd
@@ -32,7 +32,8 @@ use work.common_pkg.all;
entity common_accumulate is
generic (
- g_representation : string := "SIGNED" -- or "UNSIGNED"
+ -- or "UNSIGNED"
+ g_representation : string := "SIGNED"
);
port (
rst : in std_logic := '0';
diff --git a/libraries/base/common/src/vhdl/common_add_sub.vhd b/libraries/base/common/src/vhdl/common_add_sub.vhd
index 62efa07c4d9682dbd8c1b8c7721ab17225a65af4..74f886ce3f26ec1dc7333f1fc7ffc497c6dcc712 100644
--- a/libraries/base/common/src/vhdl/common_add_sub.vhd
+++ b/libraries/base/common/src/vhdl/common_add_sub.vhd
@@ -25,17 +25,23 @@ use work.common_pkg.all;
entity common_add_sub is
generic (
- g_direction : string := "ADD"; -- or "SUB", or "BOTH" and use sel_add
- g_representation : string := "SIGNED"; -- or "UNSIGNED", important if g_out_dat_w > g_in_dat_w, not relevant if g_out_dat_w = g_in_dat_w
- g_pipeline_input : natural := 0; -- 0 or 1
- g_pipeline_output : natural := 1; -- >= 0
+ -- or "SUB", or "BOTH" and use sel_add
+ g_direction : string := "ADD";
+ -- or "UNSIGNED", important if g_out_dat_w > g_in_dat_w, not relevant if g_out_dat_w = g_in_dat_w
+ g_representation : string := "SIGNED";
+ -- 0 or 1
+ g_pipeline_input : natural := 0;
+ -- >= 0
+ g_pipeline_output : natural := 1;
g_in_dat_w : natural := 8;
- g_out_dat_w : natural := 9 -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ g_out_dat_w : natural := 9
);
port (
clk : in std_logic;
clken : in std_logic := '1';
- sel_add : in std_logic := '1'; -- only used for g_direction "BOTH"
+ -- only used for g_direction "BOTH"
+ sel_add : in std_logic := '1';
in_a : in std_logic_vector(g_in_dat_w - 1 downto 0);
in_b : in std_logic_vector(g_in_dat_w - 1 downto 0);
result : out std_logic_vector(g_out_dat_w - 1 downto 0)
@@ -55,12 +61,14 @@ architecture str of common_add_sub is
begin
in_add <= '1' when g_direction = "ADD" or (g_direction = "BOTH" and sel_add = '1') else '0';
- no_input_reg : if g_pipeline_input = 0 generate -- wired input
+ -- wired input
+ no_input_reg : if g_pipeline_input = 0 generate
in_a_p <= in_a;
in_b_p <= in_b;
sel_add_p <= in_add;
end generate;
- gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ -- register input
+ gen_input_reg : if g_pipeline_input > 0 generate
p_reg : process(clk)
begin
if rising_edge(clk) then
@@ -81,10 +89,12 @@ begin
result_p <= ADD_UVEC(in_a_p, in_b_p, c_res_w) when sel_add_p = '1' else SUB_UVEC(in_a_p, in_b_p, c_res_w);
end generate;
- u_output_pipe : entity work.common_pipeline -- pipeline output
+ -- pipeline output
+ u_output_pipe : entity work.common_pipeline
generic map (
g_representation => g_representation,
- g_pipeline => g_pipeline_output, -- 0 for wires, >0 for register stages
+ -- 0 for wires, >0 for register stages
+ g_pipeline => g_pipeline_output,
g_in_dat_w => result'LENGTH,
g_out_dat_w => result'length
)
diff --git a/libraries/base/common/src/vhdl/common_add_symbol.vhd b/libraries/base/common/src/vhdl/common_add_symbol.vhd
index 5472ab24a520321e4d79867d46b065d7c24ab83b..9eb5b6eadd10dfebee76d9ce2630cee3a5844878 100644
--- a/libraries/base/common/src/vhdl/common_add_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_add_symbol.vhd
@@ -51,9 +51,12 @@ entity common_add_symbol is
in_eop : in std_logic := 'X';
out_data : out std_logic_vector(g_nof_symbols * g_symbol_w - 1 downto 0);
- out_val : out std_logic; -- pipelined in_val
- out_sop : out std_logic; -- pipelined in_sop
- out_eop : out std_logic -- pipelined in_eop
+ -- pipelined in_val
+ out_val : out std_logic;
+ -- pipelined in_sop
+ out_sop : out std_logic;
+ -- pipelined in_eop
+ out_eop : out std_logic
);
end common_add_symbol;
diff --git a/libraries/base/common/src/vhdl/common_adder_staged.vhd b/libraries/base/common/src/vhdl/common_adder_staged.vhd
index fe3c110aa9c35162249b14efd8e3566f6c0e5ab4..6b89795f9a2e3cb7cb3bd3359b9005d6e436fb09 100644
--- a/libraries/base/common/src/vhdl/common_adder_staged.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_staged.vhd
@@ -41,9 +41,12 @@ use common_lib.common_pkg.all;
entity common_adder_staged is
generic (
g_dat_w : natural;
- g_adder_w : natural; -- g_adder_w internal adder width
- g_pipeline_input : natural; -- 0 no input registers, else register input
- g_pipeline_output : natural -- pipeline for the adder, must be >= ceil(g_dat_w / g_adder_w) to allow g_adder_w < g_dat_w
+ -- g_adder_w internal adder width
+ g_adder_w : natural;
+ -- 0 no input registers, else register input
+ g_pipeline_input : natural;
+ -- pipeline for the adder, must be >= ceil(g_dat_w / g_adder_w) to allow g_adder_w < g_dat_w
+ g_pipeline_output : natural
);
port (
clk : in std_logic;
@@ -61,8 +64,10 @@ architecture str of common_adder_staged is
constant c_nof_adder : natural := g_dat_w / g_adder_w + sel_a_b(g_dat_w mod g_adder_w = 0, 0, 1);
- type t_inp_matrix is array (integer range <>, integer range <>) of std_logic_vector(g_adder_w - 1 downto 0); -- (STAGE, SECTION)
- type t_sum_matrix is array (integer range <>, integer range <>) of std_logic_vector(g_adder_w downto 0); -- (STAGE, SECTION), width +1 for carry bit
+ -- (STAGE, SECTION)
+ type t_inp_matrix is array (integer range <>, integer range <>) of std_logic_vector(g_adder_w - 1 downto 0);
+ -- (STAGE, SECTION), width +1 for carry bit
+ type t_sum_matrix is array (integer range <>, integer range <>) of std_logic_vector(g_adder_w downto 0);
-- Input signals
signal reg_dat_a : std_logic_vector(g_dat_w - 1 downto 0) := (others => '0');
@@ -74,7 +79,8 @@ architecture str of common_adder_staged is
-- Internal sub adders
signal m_a : t_inp_matrix(0 to c_nof_adder - 1, 0 to c_nof_adder - 1);
signal m_b : t_inp_matrix(0 to c_nof_adder - 1, 0 to c_nof_adder - 1);
- signal m_sum : t_sum_matrix(0 to c_nof_adder - 1, -1 to c_nof_adder - 1); -- section index -1 for first zero carry input
+ -- section index -1 for first zero carry input
+ signal m_sum : t_sum_matrix(0 to c_nof_adder - 1, -1 to c_nof_adder - 1);
signal vec_add : std_logic_vector(c_nof_adder * g_adder_w - 1 downto 0);
@@ -168,7 +174,8 @@ begin
u_stage_add_input : entity common_lib.common_add_sub
generic map (
g_direction => "ADD",
- g_representation => "UNSIGNED", -- must treat the sections as unsigned
+ -- must treat the sections as unsigned
+ g_representation => "UNSIGNED",
g_pipeline_input => 0,
g_pipeline_output => 1,
g_in_dat_w => g_adder_w,
@@ -183,14 +190,17 @@ begin
);
gen_stage : for STAGE in 1 to c_nof_adder - 1 generate
- m_a(STAGE, SECTION) <= m_sum(STAGE-1, SECTION )(g_adder_w - 1 downto 0); -- sum from preceding stage
- m_b(STAGE, SECTION) <= RESIZE_UVEC(m_sum(STAGE-1, SECTION - 1)(g_adder_w), g_adder_w); -- carry from less significant section in preceding stage
+ -- sum from preceding stage
+ m_a(STAGE, SECTION) <= m_sum(STAGE-1, SECTION )(g_adder_w - 1 downto 0);
+ -- carry from less significant section in preceding stage
+ m_b(STAGE, SECTION) <= RESIZE_UVEC(m_sum(STAGE-1, SECTION - 1)(g_adder_w), g_adder_w);
-- Adder stages to add and propagate the carry for each section
u_add_carry : entity common_lib.common_add_sub
generic map (
g_direction => "ADD",
- g_representation => "UNSIGNED", -- must treat the sections as unsigned
+ -- must treat the sections as unsigned
+ g_representation => "UNSIGNED",
g_pipeline_input => 0,
g_pipeline_output => 1,
g_in_dat_w => g_adder_w,
@@ -200,7 +210,8 @@ begin
clk => clk,
clken => clken,
in_a => m_a(STAGE, SECTION),
- in_b => m_b(STAGE, SECTION), -- + carry 0 or 1 from the less significant adder section
+ -- + carry 0 or 1 from the less significant adder section
+ in_b => m_b(STAGE, SECTION),
result => m_sum(STAGE, SECTION)
);
end generate;
@@ -221,7 +232,8 @@ begin
port map (
clk => clk,
clken => clken,
- in_dat => vec_add(g_dat_w - 1 downto 0), -- resize length of multiple g_adder_w back to g_dat_w width
+ -- resize length of multiple g_adder_w back to g_dat_w width
+ in_dat => vec_add(g_dat_w - 1 downto 0),
out_dat => out_dat
);
end generate;
diff --git a/libraries/base/common/src/vhdl/common_adder_tree.vhd b/libraries/base/common/src/vhdl/common_adder_tree.vhd
index 7d95c7b027a51d4b8950a204350a2dfc3463bd16..ac4ccc9e2b53187c403e4b49a804e4f8825cb8a0 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree.vhd
@@ -39,10 +39,13 @@ use IEEE.std_logic_1164.all;
entity common_adder_tree is
generic (
g_representation : string := "SIGNED";
- g_pipeline : natural := 1; -- amount of pipelining per stage
- g_nof_inputs : natural := 4; -- >= 1, nof stages = ceil_log2(g_nof_inputs)
+ -- amount of pipelining per stage
+ g_pipeline : natural := 1;
+ -- >= 1, nof stages = ceil_log2(g_nof_inputs)
+ g_nof_inputs : natural := 4;
g_dat_w : natural := (12 + 16) + 2;
- g_sum_w : natural := (12 + 16) + 4 -- g_dat_w + ceil_log2(g_nof_inputs)
+ -- g_dat_w + ceil_log2(g_nof_inputs)
+ g_sum_w : natural := (12 + 16) + 4
);
port (
clk : in std_logic;
diff --git a/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd b/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
index ece19109a02fba5b375d21bd4325a91e3215ac31..c92d927032e380ef6c1d4faff5826090f2d9547c 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
@@ -28,8 +28,10 @@ architecture recursive of common_adder_tree is
constant c_pipeline_in : natural := 0;
constant c_pipeline_out : natural := g_pipeline;
- constant c_nof_h1 : natural := g_nof_inputs / 2; -- lower half
- constant c_nof_h2 : natural := g_nof_inputs - g_nof_inputs / 2; -- upper half
+ -- lower half
+ constant c_nof_h1 : natural := g_nof_inputs / 2;
+ -- upper half
+ constant c_nof_h2 : natural := g_nof_inputs - g_nof_inputs / 2;
-- The h1 branch needs an extra dummy stage when c_nof_h1 is a power of 2 AND c_nof_h2=c_nof_h1+1
function func_stage_h1(h1, h2 : natural) return boolean is
@@ -45,7 +47,8 @@ architecture recursive of common_adder_tree is
constant c_stage_h1 : boolean := func_stage_h1(c_nof_h1, c_nof_h2);
- constant c_sum_w : natural := g_dat_w + ceil_log2(g_nof_inputs); -- internally work with worst case bit growth
+ -- internally work with worst case bit growth
+ constant c_sum_w : natural := g_dat_w + ceil_log2(g_nof_inputs);
constant c_sum_h_w : natural := c_sum_w - 1;
constant c_sum_h1_w : natural := sel_a_b(c_stage_h1, c_sum_h_w - 1, c_sum_h_w);
constant c_sum_h2_w : natural := c_sum_h_w;
diff --git a/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd b/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
index 579de011dc92e04ab491bea1fa48c23370b155f9..cf82a00bdbcc29e50ae0dbb82288e3cbc0dd5404 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
@@ -38,11 +38,15 @@ architecture str of common_adder_tree is
-- growth at every stage, because synthesis will optimize unused MSbits away
-- when g_sum_w < c_sum_w.
- constant c_w : natural := g_dat_w; -- input data width
- constant c_sum_w : natural := g_dat_w + ceil_log2(g_nof_inputs); -- adder tree sum width
+ -- input data width
+ constant c_w : natural := g_dat_w;
+ -- adder tree sum width
+ constant c_sum_w : natural := g_dat_w + ceil_log2(g_nof_inputs);
- constant c_N : natural := g_nof_inputs; -- nof inputs to the adder tree
- constant c_nof_stages : natural := ceil_log2(c_N); -- nof stages in the adder tree
+ -- nof inputs to the adder tree
+ constant c_N : natural := g_nof_inputs;
+ -- nof stages in the adder tree
+ constant c_nof_stages : natural := ceil_log2(c_N);
-- Allocate c_sum_w for each field and allocate c_N fields for the input
-- stage and use this array for all stages. Hence the stage vectors
@@ -130,7 +134,8 @@ begin
-- Map final sum to larger output vector using sign extension or to smaller width output vector preserving the LS part
sum <= RESIZE_SVEC(adds(c_nof_stages - 1)(c_sum_w - 1 downto 0), g_sum_w) when g_representation = "SIGNED" else
RESIZE_UVEC(adds(c_nof_stages - 1)(c_sum_w - 1 downto 0), g_sum_w);
- end generate; -- gen_tree
+ -- gen_tree
+ end generate;
no_tree : if g_nof_inputs = 1 generate
-- For g_nof_inputs = 1 gen_tree yields wires sum <= in_dat, therefore
@@ -150,6 +155,7 @@ begin
in_dat => in_dat,
out_dat => sum
);
- end generate; -- no_tree
+ -- no_tree
+ end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_areset.vhd b/libraries/base/common/src/vhdl/common_areset.vhd
index 13c3a2454c660456b76f0b0f3bfc1d6da2f559bb..8246149ea496420327970dc1e278c1b81d1171fe 100644
--- a/libraries/base/common/src/vhdl/common_areset.vhd
+++ b/libraries/base/common/src/vhdl/common_areset.vhd
@@ -37,8 +37,10 @@ use work.common_pkg.all;
entity common_areset is
generic (
- g_in_rst_level : std_logic := '1'; -- = in_rst level
- g_rst_level : std_logic := '1'; -- = out_rst level (keep original generic
+ -- = in_rst level
+ g_in_rst_level : std_logic := '1';
+ -- = out_rst level (keep original generic
+ g_rst_level : std_logic := '1';
-- name for backward compatibility)
g_delay_len : natural := c_meta_delay_len
);
diff --git a/libraries/base/common/src/vhdl/common_async.vhd b/libraries/base/common/src/vhdl/common_async.vhd
index e4a037445b3ae691e19928183db6d9b16ceb4ab2..bcdf5383a4ae236fb2d3d7c299c1307e1860e92d 100644
--- a/libraries/base/common/src/vhdl/common_async.vhd
+++ b/libraries/base/common/src/vhdl/common_async.vhd
@@ -31,7 +31,8 @@ entity common_async is
generic (
g_rising_edge : boolean := true;
g_rst_level : std_logic := '0';
- g_delay_len : positive := c_meta_delay_len -- use common_pipeline if g_delay_len=0 for wires only is also needed
+ -- use common_pipeline if g_delay_len=0 for wires only is also needed
+ g_delay_len : positive := c_meta_delay_len
);
port (
rst : in std_logic := '0';
diff --git a/libraries/base/common/src/vhdl/common_async_slv.vhd b/libraries/base/common/src/vhdl/common_async_slv.vhd
index 1ff3d1454aa4e77e1fa5d8d5ecb3baf01b0638a1..22ba2deaedbd85e956b0cb91751e86da250388b8 100644
--- a/libraries/base/common/src/vhdl/common_async_slv.vhd
+++ b/libraries/base/common/src/vhdl/common_async_slv.vhd
@@ -31,7 +31,8 @@ use work.common_pkg.all;
entity common_async_slv is
generic (
g_rst_level : std_logic := '0';
- g_delay_len : positive := c_meta_delay_len -- use common_pipeline if g_delay_len=0 for wires only is also needed
+ -- use common_pipeline if g_delay_len=0 for wires only is also needed
+ g_delay_len : positive := c_meta_delay_len
);
port (
rst : in std_logic := '0';
diff --git a/libraries/base/common/src/vhdl/common_bit_delay.vhd b/libraries/base/common/src/vhdl/common_bit_delay.vhd
index 2f3dc51f730b5771ed3e96042eddf0bd2008d950..4c5ff6c62633710da344ac253448270c9435d961 100644
--- a/libraries/base/common/src/vhdl/common_bit_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_bit_delay.vhd
@@ -38,12 +38,15 @@ use IEEE.std_logic_1164.all;
entity common_bit_delay is
generic (
- g_depth : natural := 16 -- Quartus infers fifo for 4 to 4096 g_depth, 8 Bits.
+ -- Quartus infers fifo for 4 to 4096 g_depth, 8 Bits.
+ g_depth : natural := 16
);
port (
clk : in std_logic;
- rst : in std_logic := '0'; -- asynchronous reset for initial start
- in_clr : in std_logic := '0'; -- synchronous reset for control of dynamic restart(s)
+ -- asynchronous reset for initial start
+ rst : in std_logic := '0';
+ -- synchronous reset for control of dynamic restart(s)
+ in_clr : in std_logic := '0';
in_bit : in std_logic;
in_val : in std_logic := '1';
out_bit : out std_logic
diff --git a/libraries/base/common/src/vhdl/common_clip.vhd b/libraries/base/common/src/vhdl/common_clip.vhd
index 3f83c3d3a8f2e3619b68628d4eb50e844afd8fb4..3f3d749213260a08e65b93406f8f13f1392d37f5 100644
--- a/libraries/base/common/src/vhdl/common_clip.vhd
+++ b/libraries/base/common/src/vhdl/common_clip.vhd
@@ -38,7 +38,8 @@ use common_lib.common_pkg.all;
entity common_clip is
generic (
- g_representation : string := "SIGNED"; -- SIGNED or UNSIGNED clipping
+ -- SIGNED or UNSIGNED clipping
+ g_representation : string := "SIGNED";
g_pipeline : natural := 1;
g_full_scale : unsigned
);
diff --git a/libraries/base/common/src/vhdl/common_clock_active_detector.vhd b/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
index 246e57815e02004d836e322758e8a0a0fa722060..d48c98f96ecba5145bdb99dc24fd3d23aa506880 100644
--- a/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
+++ b/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
@@ -29,8 +29,10 @@ use work.common_pkg.all;
entity common_clock_active_detector is
generic (
- g_in_period_w : natural := 8; -- created 2**g_in_period_w period source signal in in_clk domain
- g_dp_detect_period : natural := 128; -- expected period for source signal in dp_clk domain given 2**g_in_period_w in in_clk domain
+ -- created 2**g_in_period_w period source signal in in_clk domain
+ g_in_period_w : natural := 8;
+ -- expected period for source signal in dp_clk domain given 2**g_in_period_w in in_clk domain
+ g_dp_detect_period : natural := 128;
g_dp_detect_margin : natural := 1
);
port (
@@ -50,7 +52,8 @@ architecture str of common_clock_active_detector is
constant c_dp_detect_period_w : natural := ceil_log2(g_dp_detect_period);
constant c_dp_detect_max : natural := g_dp_detect_period + g_dp_detect_margin;
constant c_dp_detect_min : natural := g_dp_detect_period - g_dp_detect_margin;
- constant c_dp_clk_cnt_w : natural := c_dp_detect_period_w + 1; -- +1 to be wide enough to fit somewhat more than maximum nof clock cycles per interval
+ -- +1 to be wide enough to fit somewhat more than maximum nof clock cycles per interval
+ constant c_dp_clk_cnt_w : natural := c_dp_detect_period_w + 1;
constant c_dp_clk_cnt_max : natural := 2**c_dp_clk_cnt_w - 1;
signal dbg_g_in_period_w : natural := g_in_period_w;
diff --git a/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd b/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
index b44ac564c54ada7d1b705da5abfb70621982ca9f..f6f9d0ad1fa5cca6178d1dbbad6a57ca2c22bbc5 100644
--- a/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
+++ b/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
@@ -102,10 +102,12 @@ entity common_clock_phase_detector is
g_phase_rst_level : std_logic := '0';
g_meta_delay_len : positive := c_meta_delay_len;
g_offset_delay_len : integer := 0;
- g_clk_factor : positive := 1 -- = N
+ -- = N
+ g_clk_factor : positive := 1
);
port (
- in_clk : in std_logic; -- used as data input for clk domain
+ -- used as data input for clk domain
+ in_clk : in std_logic;
rst : in std_logic := '0';
clk : in std_logic;
phase : out std_logic;
@@ -115,11 +117,15 @@ end common_clock_phase_detector;
architecture str of common_clock_phase_detector is
constant c_period_len : natural := 2 * g_clk_factor;
- constant c_delay_len : natural := ceil_div(g_meta_delay_len, c_period_len) * c_period_len + 1 + g_offset_delay_len; -- detect clock phase relation independent of g_meta_delay_len
+ -- detect clock phase relation independent of g_meta_delay_len
+ constant c_delay_len : natural := ceil_div(g_meta_delay_len, c_period_len) * c_period_len + 1 + g_offset_delay_len;
- signal dbg_g_meta_delay_len : natural := g_meta_delay_len; -- to view it in the wave window
- signal dbg_c_period_len : natural := c_period_len; -- to view it in the wave window
- signal dbg_c_delay_len : natural := c_delay_len; -- to view it in the wave window
+ -- to view it in the wave window
+ signal dbg_g_meta_delay_len : natural := g_meta_delay_len;
+ -- to view it in the wave window
+ signal dbg_c_period_len : natural := c_period_len;
+ -- to view it in the wave window
+ signal dbg_c_delay_len : natural := c_delay_len;
signal in_phs_cap : std_logic;
signal in_phs : std_logic;
@@ -147,11 +153,14 @@ begin
end generate;
gen_fr_reg : if g_rising_edge = false generate
- in_phs <= g_phase_rst_level when rst = '1' else in_phs_cap when rising_edge(clk); -- get from f to r
+ -- get from f to r
+ in_phs <= g_phase_rst_level when rst = '1' else in_phs_cap when rising_edge(clk);
end generate;
- in_phs_dly(0) <= in_phs when rising_edge(clk); -- when N=1 or M>1
- in_phs_dly(g_clk_factor - 1 downto 1) <= in_phs_dly(g_clk_factor - 2 downto 0) when rising_edge(clk); -- when N>1
+ -- when N=1 or M>1
+ in_phs_dly(0) <= in_phs when rising_edge(clk);
+ -- when N>1
+ in_phs_dly(g_clk_factor - 1 downto 1) <= in_phs_dly(g_clk_factor - 2 downto 0) when rising_edge(clk);
phase_det <= '0' when rst = '1' else nxt_phase_det when rising_edge(clk);
diff --git a/libraries/base/common/src/vhdl/common_complex_add_sub.vhd b/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
index 51192d7b4cfa2b8384e059dc685887e0e1ea59d6..f096ddf6e743788fe18ba92a32e013f7b97219bf 100644
--- a/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
+++ b/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
@@ -24,12 +24,17 @@ use IEEE.std_logic_1164.all;
entity common_complex_add_sub is
generic (
- g_direction : string := "ADD"; -- or "SUB"
- g_representation : string := "SIGNED"; -- or "UNSIGNED"
- g_pipeline_input : natural := 0; -- 0 or 1
- g_pipeline_output : natural := 1; -- >= 0
+ -- or "SUB"
+ g_direction : string := "ADD";
+ -- or "UNSIGNED"
+ g_representation : string := "SIGNED";
+ -- 0 or 1
+ g_pipeline_input : natural := 0;
+ -- >= 0
+ g_pipeline_output : natural := 1;
g_in_dat_w : natural := 8;
- g_out_dat_w : natural := 9 -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ g_out_dat_w : natural := 9
);
port (
clk : in std_logic;
diff --git a/libraries/base/common/src/vhdl/common_complex_round.vhd b/libraries/base/common/src/vhdl/common_complex_round.vhd
index b365d78a728e29d04f4c6392d1368faa057cd1d2..93c5d160de418f1164d4210f1463ef75baf133c6 100644
--- a/libraries/base/common/src/vhdl/common_complex_round.vhd
+++ b/libraries/base/common/src/vhdl/common_complex_round.vhd
@@ -24,11 +24,16 @@ use IEEE.std_logic_1164.all;
entity common_complex_round is
generic (
- g_representation : string := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
- g_round : boolean := true; -- when TRUE round the input, else truncate the input
- g_round_clip : boolean := false; -- when TRUE clip rounded input >= +max to avoid wrapping to output -min (signed) or 0 (unsigned)
- g_pipeline_input : natural := 0; -- >= 0
- g_pipeline_output : natural := 1; -- >= 0, use g_pipeline_input=0 and g_pipeline_output=0 for combinatorial output
+ -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
+ g_representation : string := "SIGNED";
+ -- when TRUE round the input, else truncate the input
+ g_round : boolean := true;
+ -- when TRUE clip rounded input >= +max to avoid wrapping to output -min (signed) or 0 (unsigned)
+ g_round_clip : boolean := false;
+ -- >= 0
+ g_pipeline_input : natural := 0;
+ -- >= 0, use g_pipeline_input=0 and g_pipeline_output=0 for combinatorial output
+ g_pipeline_output : natural := 1;
g_in_dat_w : natural := 36;
g_out_dat_w : natural := 18
);
diff --git a/libraries/base/common/src/vhdl/common_components_pkg.vhd b/libraries/base/common/src/vhdl/common_components_pkg.vhd
index ba5e04a595382f2f4586cf619f49c9088b596572..398091807cbf3727f550cf0f336fdc9569e7c896 100644
--- a/libraries/base/common/src/vhdl/common_components_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_components_pkg.vhd
@@ -31,8 +31,10 @@ use work.common_mem_pkg.all;
package common_components_pkg is
component common_pipeline is
generic (
- g_representation : string := "SIGNED"; -- or "UNSIGNED"
- g_pipeline : natural := 1; -- 0 for wires, > 0 for registers,
+ -- or "UNSIGNED"
+ g_representation : string := "SIGNED";
+ -- 0 for wires, > 0 for registers,
+ g_pipeline : natural := 1;
g_reset_value : integer := 0;
g_in_dat_w : natural := 8;
g_out_dat_w : natural := 9
@@ -50,8 +52,10 @@ package common_components_pkg is
component common_pipeline_sl is
generic (
- g_pipeline : natural := 1; -- 0 for wires, > 0 for registers,
- g_reset_value : natural := 0; -- 0 or 1, bit reset value,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline : natural := 1;
+ -- 0 or 1, bit reset value,
+ g_reset_value : natural := 0;
g_out_invert : boolean := false
);
port (
diff --git a/libraries/base/common/src/vhdl/common_counter.vhd b/libraries/base/common/src/vhdl/common_counter.vhd
index e5a449527e4e92286d1a16288bdd937d53aacd50..466416c9361240fc3bfc211cc582c468ed977f49 100644
--- a/libraries/base/common/src/vhdl/common_counter.vhd
+++ b/libraries/base/common/src/vhdl/common_counter.vhd
@@ -38,31 +38,42 @@ use work.common_pkg.all;
entity common_counter is
generic (
- g_latency : natural := 1; -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ g_latency : natural := 1;
g_init : integer := 0;
g_width : natural := 32;
- g_max : natural := 0; -- default 0 to disable the g_max setting.
- g_step_size : integer := 1; -- counting in steps of g_step_size, can be + or -
- g_clip : boolean := false -- when True, counter will clip at g_max, if g_max = 0 and g_step_size > 0, the counter clips at 2**g_width -1.
+ -- default 0 to disable the g_max setting.
+ g_max : natural := 0;
+ -- counting in steps of g_step_size, can be + or -
+ g_step_size : integer := 1;
+ -- when True, counter will clip at g_max, if g_max = 0 and g_step_size > 0, the counter clips at 2**g_width -1.
+ g_clip : boolean := false
);
port (
- rst : in std_logic := '0'; -- either use asynchronous rst or synchronous cnt_clr
+ -- either use asynchronous rst or synchronous cnt_clr
+ rst : in std_logic := '0';
clk : in std_logic;
clken : in std_logic := '1';
- cnt_clr : in std_logic := '0'; -- synchronous cnt_clr is only interpreted when clken is active
- cnt_ld : in std_logic := '0'; -- cnt_ld loads the output count with the input load value, independent of cnt_en
+ -- synchronous cnt_clr is only interpreted when clken is active
+ cnt_clr : in std_logic := '0';
+ -- cnt_ld loads the output count with the input load value, independent of cnt_en
+ cnt_ld : in std_logic := '0';
cnt_en : in std_logic := '1';
cnt_max : in std_logic_vector(g_width - 1 downto 0) := sel_a_b( g_step_size > 0 and g_max = 0, array_init('1', g_width),
- sel_a_b( ceil_log2(g_max + 1) > g_width, array_init('1', g_width), TO_UVEC(g_max, g_width) )); -- see remarks
+ -- see remarks
+ sel_a_b( ceil_log2(g_max + 1) > g_width, array_init('1', g_width), TO_UVEC(g_max, g_width) ));
load : in std_logic_vector(g_width - 1 downto 0) := TO_SVEC(g_init, g_width);
count : out std_logic_vector(g_width - 1 downto 0)
);
end common_counter;
architecture rtl of common_counter is
- signal reg_count : std_logic_vector(count'range) := TO_SVEC(g_init, g_width); -- in case rst is not used
- signal nxt_count : std_logic_vector(count'range) := TO_SVEC(g_init, g_width); -- to avoid Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE, when using unsigned()
- signal comb_count : std_logic_vector(count'range) := TO_SVEC(g_init, g_width); -- to avoid Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE, when using unsigned()
+ -- in case rst is not used
+ signal reg_count : std_logic_vector(count'range) := TO_SVEC(g_init, g_width);
+ -- to avoid Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE, when using unsigned()
+ signal nxt_count : std_logic_vector(count'range) := TO_SVEC(g_init, g_width);
+ -- to avoid Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE, when using unsigned()
+ signal comb_count : std_logic_vector(count'range) := TO_SVEC(g_init, g_width);
begin
comb_count <= nxt_count;
diff --git a/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd b/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
index a89e287f0db450947d3f56c963cfedf0de9b350d..e49a704333da3ffd0ed9275507af6834d6bbeea6 100644
--- a/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
@@ -66,18 +66,22 @@ entity common_create_strobes_from_valid is
out_val : out std_logic;
out_sop : out std_logic;
out_eop : out std_logic;
- out_sync : out std_logic; -- DP style: sync at sop
- out_sync1 : out std_logic -- LOFAR1 style: sync before sop
+ -- DP style: sync at sop
+ out_sync : out std_logic;
+ -- LOFAR1 style: sync before sop
+ out_sync1 : out std_logic
);
end common_create_strobes_from_valid;
architecture rtl of common_create_strobes_from_valid is
- type t_state is record -- function state registers
+ -- function state registers
+ type t_state is record
val_cnt : natural range 0 to g_nof_clk_per_sync - 1;
blk_cnt : natural range 0 to g_nof_clk_per_block - 1;
end record;
- type t_outputs is record -- copy of entity outputs
+ -- copy of entity outputs
+ type t_outputs is record
out_val : std_logic;
out_sop : std_logic;
out_eop : std_logic;
@@ -87,11 +91,15 @@ architecture rtl of common_create_strobes_from_valid is
constant c_state_rst : t_state := (val_cnt => 0, blk_cnt => 0);
constant c_outputs_rst : t_outputs := ('0', '0', '0', '0');
- signal q : t_state := c_state_rst; -- stored state with latency one
- signal d : t_state := c_state_rst; -- zero latency state
+ -- stored state with latency one
+ signal q : t_state := c_state_rst;
+ -- zero latency state
+ signal d : t_state := c_state_rst;
- signal o : t_outputs := c_outputs_rst; -- zero latency outputs
- signal p : t_outputs := c_outputs_rst; -- pipelined outputs
+ -- zero latency outputs
+ signal o : t_outputs := c_outputs_rst;
+ -- pipelined outputs
+ signal p : t_outputs := c_outputs_rst;
begin
-- p_state
q <= d when rising_edge(clk);
diff --git a/libraries/base/common/src/vhdl/common_ddreg.vhd b/libraries/base/common/src/vhdl/common_ddreg.vhd
index 74638cc7e16c677257c6e2b8b9d7b9690be4212e..2baf9138e52c7d5e057f4752e80863ac05118549 100644
--- a/libraries/base/common/src/vhdl/common_ddreg.vhd
+++ b/libraries/base/common/src/vhdl/common_ddreg.vhd
@@ -137,7 +137,8 @@ entity common_ddreg_f is
in_dat : in std_logic;
rst : in std_logic := '0';
out_clk : in std_logic;
- out_dat_f : out std_logic -- clocked at falling edge of out_clk
+ -- clocked at falling edge of out_clk
+ out_dat_f : out std_logic
);
end common_ddreg_f;
@@ -184,16 +185,20 @@ entity common_ddreg_fr is
port (
rst : in std_logic := '0';
clk : in std_logic;
- in_dat_f : in std_logic; -- clocked at falling edge of clk
- out_dat_r : out std_logic -- clocked at rising edge of clk
+ -- clocked at falling edge of clk
+ in_dat_f : in std_logic;
+ -- clocked at rising edge of clk
+ out_dat_r : out std_logic
);
end common_ddreg_fr;
architecture str of common_ddreg_fr is
signal in_dat_d : std_logic;
begin
- in_dat_d <= in_dat_f when falling_edge(clk); -- input at falling edge
- out_dat_r <= in_dat_d when rising_edge(clk); -- Output at rising edge
+ -- input at falling edge
+ in_dat_d <= in_dat_f when falling_edge(clk);
+ -- Output at rising edge
+ out_dat_r <= in_dat_d when rising_edge(clk);
end str;
--------------------------------------------------------------------------------
@@ -251,7 +256,8 @@ begin
in_dat => in_dat,
rst => rst,
out_clk => out_clk,
- out_dat_f => out_dat_f -- clocked at falling edge of out_clk
+ -- clocked at falling edge of out_clk
+ out_dat_f => out_dat_f
);
u_ddreg_lo : entity work.common_ddreg_fr
@@ -259,6 +265,7 @@ begin
rst => rst,
clk => out_clk,
in_dat_f => out_dat_f,
- out_dat_r => out_dat_lo -- clocked at rising edge of out_clk
+ -- clocked at rising edge of out_clk
+ out_dat_r => out_dat_lo
);
end str;
diff --git a/libraries/base/common/src/vhdl/common_debounce.vhd b/libraries/base/common/src/vhdl/common_debounce.vhd
index fa2d76a017ad2a9af1f4caed0cf0cf83ca0ab8d4..14f3e8f68115cd19288b0c46d73015996a2d89d5 100644
--- a/libraries/base/common/src/vhdl/common_debounce.vhd
+++ b/libraries/base/common/src/vhdl/common_debounce.vhd
@@ -31,11 +31,14 @@ use work.common_pkg.all;
entity common_debounce is
generic (
- g_type : string := "BOTH"; -- "BOTH" = debounce g_latency clk cycles for both bgoing high when d_in='1' and for going low when d_in='0'
+ -- "BOTH" = debounce g_latency clk cycles for both bgoing high when d_in='1' and for going low when d_in='0'
+ g_type : string := "BOTH";
-- "HIGH" = debounce g_latency clk cycles for going high when d_in='1', go low immediately when d_in='0'
-- "LOW" = debounce g_latency clk cycles for going low when d_in='0', go high immediately when d_in='1'
- g_delay_len : natural := c_meta_delay_len; -- = 3, combat meta stability
- g_latency : natural := 8; -- >= 1, combat debounces over nof clk cycles
+ -- = 3, combat meta stability
+ g_delay_len : natural := c_meta_delay_len;
+ -- >= 1, combat debounces over nof clk cycles
+ g_latency : natural := 8;
g_init_level : std_logic := '1'
);
port (
@@ -50,7 +53,8 @@ end common_debounce;
architecture rtl of common_debounce is
constant c_latency_w : natural := ceil_log2(g_latency + 1);
- signal cnt : std_logic_vector(c_latency_w - 1 downto 0); -- use cnt = g_latency to stop the counter
+ -- use cnt = g_latency to stop the counter
+ signal cnt : std_logic_vector(c_latency_w - 1 downto 0);
signal cnt_clr : std_logic;
signal cnt_en : std_logic;
signal stable_d : std_logic;
diff --git a/libraries/base/common/src/vhdl/common_delay.vhd b/libraries/base/common/src/vhdl/common_delay.vhd
index 0e72b7574362dbdef1c24d911acd3d84a04258ce..5d2d8ae16d6b4a92936b0d652339927a06183177 100644
--- a/libraries/base/common/src/vhdl/common_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_delay.vhd
@@ -29,7 +29,8 @@ use IEEE.std_logic_1164.all;
entity common_delay is
generic (
- g_dat_w : natural := 8; -- need g_dat_w to be able to use (others=>'') assignments for two dimensional unconstraint vector arrays
+ -- need g_dat_w to be able to use (others=>'') assignments for two dimensional unconstraint vector arrays
+ g_dat_w : natural := 8;
g_depth : natural := 16
);
port (
diff --git a/libraries/base/common/src/vhdl/common_demultiplexer.vhd b/libraries/base/common/src/vhdl/common_demultiplexer.vhd
index 52f37b9cd5be508a913914ed8705e79346678cc1..48b24403bd1001cbbadbabeabc3cf54f88c330fe 100644
--- a/libraries/base/common/src/vhdl/common_demultiplexer.vhd
+++ b/libraries/base/common/src/vhdl/common_demultiplexer.vhd
@@ -38,7 +38,8 @@ entity common_demultiplexer is
);
port (
rst : in std_logic := '0';
- clk : in std_logic := '0'; -- for g_pipeline_* = 0 no rst and clk are needed, because then the demultiplexer works combinatorialy
+ -- for g_pipeline_* = 0 no rst and clk are needed, because then the demultiplexer works combinatorialy
+ clk : in std_logic := '0';
in_dat : in std_logic_vector(g_dat_w - 1 downto 0);
in_val : in std_logic;
@@ -77,9 +78,11 @@ begin
begin
sel_val <= (others => '0');
for I in g_nof_out - 1 downto 0 loop
- sel_dat((I + 1) * g_dat_w - 1 downto I * g_dat_w) <= in_dat_reg; -- replicate in_dat to all outputs, this requires less logic than default forcing invalid outputs to 0
+ -- replicate in_dat to all outputs, this requires less logic than default forcing invalid outputs to 0
+ sel_dat((I + 1) * g_dat_w - 1 downto I * g_dat_w) <= in_dat_reg;
if TO_UINT(out_sel_reg) = I then
- sel_val(I) <= in_val_reg; -- let out_sel determine which output is valid
+ -- let out_sel determine which output is valid
+ sel_val(I) <= in_val_reg;
end if;
end loop;
end process;
diff --git a/libraries/base/common/src/vhdl/common_duty_cycle.vhd b/libraries/base/common/src/vhdl/common_duty_cycle.vhd
index 8c09e6292f07279763381f58bd8325d475a8520f..33530ed3964682890d2abf0851ef1a3fc6e88493 100644
--- a/libraries/base/common/src/vhdl/common_duty_cycle.vhd
+++ b/libraries/base/common/src/vhdl/common_duty_cycle.vhd
@@ -40,11 +40,16 @@ use WORK.common_pkg.all;
entity common_duty_cycle is
generic (
- g_rst_lvl : std_logic := '0'; -- dc_out level on reset
- g_dis_lvl : std_logic := '0'; -- dc_out level when disabled
- g_act_lvl : std_logic := '1'; -- Level that's DC controlled
- g_per_cnt : positive; -- Nof clk cycles per period. Note: if the dc_per_cnt input is used, this generic sets the maximum period.
- g_act_cnt : natural -- Nof clk cycles/period active level
+ -- dc_out level on reset
+ g_rst_lvl : std_logic := '0';
+ -- dc_out level when disabled
+ g_dis_lvl : std_logic := '0';
+ -- Level that's DC controlled
+ g_act_lvl : std_logic := '1';
+ -- Nof clk cycles per period. Note: if the dc_per_cnt input is used, this generic sets the maximum period.
+ g_per_cnt : positive;
+ -- Nof clk cycles/period active level
+ g_act_cnt : natural
);
port (
rst : in std_logic;
diff --git a/libraries/base/common/src/vhdl/common_evt.vhd b/libraries/base/common/src/vhdl/common_evt.vhd
index c4ad6d2bfd1d34bebf41b8a3b41fc5ccfa381303..66431dd6754dc743c12d3a8c79ae8ded05efc104 100644
--- a/libraries/base/common/src/vhdl/common_evt.vhd
+++ b/libraries/base/common/src/vhdl/common_evt.vhd
@@ -25,9 +25,12 @@ use work.common_pkg.all;
entity common_evt is
generic (
- g_evt_type : string := "RISING"; -- type can be: "RISING", "FALLING", or "BOTH"
- g_out_invert : boolean := false; -- if TRUE then invert the output to have active low output, else default use active high output
- g_out_reg : boolean := false -- if TRUE then the output is registered, else it is not
+ -- type can be: "RISING", "FALLING", or "BOTH"
+ g_evt_type : string := "RISING";
+ -- if TRUE then invert the output to have active low output, else default use active high output
+ g_out_invert : boolean := false;
+ -- if TRUE then the output is registered, else it is not
+ g_out_reg : boolean := false
);
port (
rst : in std_logic := '0';
diff --git a/libraries/base/common/src/vhdl/common_fanout.vhd b/libraries/base/common/src/vhdl/common_fanout.vhd
index 77143e1487c43d7c0147c90824b0c54df06afb42..12f0f2a80f8fb037eba3f8e2f9b8514db4bd4c4f 100644
--- a/libraries/base/common/src/vhdl/common_fanout.vhd
+++ b/libraries/base/common/src/vhdl/common_fanout.vhd
@@ -33,8 +33,10 @@ use work.common_pkg.all;
entity common_fanout is
generic (
- g_nof_output : natural := 1; -- >= 1
- g_pipeline_arr : t_natural_arr; -- range: g_nof_output-1 DOWNTO 0, value: 0 for wires, >0 for register stages
+ -- >= 1
+ g_nof_output : natural := 1;
+ -- range: g_nof_output-1 DOWNTO 0, value: 0 for wires, >0 for register stages
+ g_pipeline_arr : t_natural_arr;
g_dat_w : natural := 8
);
port (
diff --git a/libraries/base/common/src/vhdl/common_fanout_tree.vhd b/libraries/base/common/src/vhdl/common_fanout_tree.vhd
index d0dcc9ba25c5e0b9d486220db465275b95f96fe4..c47d88646161f590a2f9a3639dbab8361942a79f 100644
--- a/libraries/base/common/src/vhdl/common_fanout_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_fanout_tree.vhd
@@ -79,11 +79,16 @@ use work.common_pkg.all;
entity common_fanout_tree is
generic (
- g_nof_stages : positive := 1; -- >= 1
- g_nof_output_per_cell : positive := 1; -- >= 1
- g_nof_output : positive := 1; -- >= 1 and <= g_nof_output_per_cell**g_nof_stages
- g_cell_pipeline_factor_arr : t_natural_arr; -- range: g_nof_stages-1 DOWNTO 0, stage g_nof_stages-1 is output stage. Value: stage factor to multiply with g_cell_pipeline_arr
- g_cell_pipeline_arr : t_natural_arr; -- range: g_nof_output_per_cell-1 DOWNTO 0. Value: 0 for wires, >0 for register stages
+ -- >= 1
+ g_nof_stages : positive := 1;
+ -- >= 1
+ g_nof_output_per_cell : positive := 1;
+ -- >= 1 and <= g_nof_output_per_cell**g_nof_stages
+ g_nof_output : positive := 1;
+ -- range: g_nof_stages-1 DOWNTO 0, stage g_nof_stages-1 is output stage. Value: stage factor to multiply with g_cell_pipeline_arr
+ g_cell_pipeline_factor_arr : t_natural_arr;
+ -- range: g_nof_output_per_cell-1 DOWNTO 0. Value: 0 for wires, >0 for register stages
+ g_cell_pipeline_arr : t_natural_arr;
g_dat_w : natural := 8
);
port (
@@ -102,8 +107,10 @@ architecture str of common_fanout_tree is
constant c_nof_output : natural := g_nof_output_per_cell**g_nof_stages;
-- Define t_natural_arr range
- constant c_cell_pipeline_factor_arr : t_natural_arr(g_nof_stages - 1 downto 0) := g_cell_pipeline_factor_arr; -- value: stage factor to multiply with g_cell_pipeline_arr
- constant c_cell_pipeline_arr : t_natural_arr(g_nof_output_per_cell - 1 downto 0) := g_cell_pipeline_arr; -- value: 0 for wires, >0 for register stages
+ -- value: stage factor to multiply with g_cell_pipeline_arr
+ constant c_cell_pipeline_factor_arr : t_natural_arr(g_nof_stages - 1 downto 0) := g_cell_pipeline_factor_arr;
+ -- value: 0 for wires, >0 for register stages
+ constant c_cell_pipeline_arr : t_natural_arr(g_nof_output_per_cell - 1 downto 0) := g_cell_pipeline_arr;
type t_stage_dat_vec_arr is array (integer range <>) of std_logic_vector(c_nof_output * g_dat_w - 1 downto 0);
type t_stage_sl_vec_arr is array (integer range <>) of std_logic_vector(c_nof_output - 1 downto 0);
@@ -144,7 +151,8 @@ begin
out_en_vec <= stage_en_vec_arr( g_nof_stages - 1)(g_nof_output - 1 downto 0);
out_val_vec <= stage_val_vec_arr(g_nof_stages - 1)(g_nof_output - 1 downto 0);
out_dat_vec <= stage_dat_vec_arr(g_nof_stages - 1)(g_nof_output * g_dat_w - 1 downto 0);
- end generate; -- gen_tree
+ -- gen_tree
+ end generate;
no_tree : if g_nof_output = 1 generate
u_reg : entity work.common_fanout
@@ -163,6 +171,7 @@ begin
out_val_vec => out_val_vec,
out_dat_vec => out_dat_vec
);
- end generate; -- no_tree
+ -- no_tree
+ end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_field_pkg.vhd b/libraries/base/common/src/vhdl/common_field_pkg.vhd
index 7f3d90b4ee7ab330bff244ff5f96f986c9824c87..c5c559b552de03a913dfb9a745e365cb0557f59d 100644
--- a/libraries/base/common/src/vhdl/common_field_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_field_pkg.vhd
@@ -57,7 +57,8 @@ package common_field_pkg is
function field_default(slv_in: std_logic_vector) return std_logic_vector;
function field_default(nat_in: natural) return std_logic_vector;
- function field_map_defaults(field_arr : t_common_field_arr) return std_logic_vector; -- returns slv_out
+ -- returns slv_out
+ function field_map_defaults(field_arr : t_common_field_arr) return std_logic_vector;
function field_mode (field_arr : t_common_field_arr; name: string ) return string;
function field_size (field_arr : t_common_field_arr; name: string ) return natural;
@@ -69,9 +70,12 @@ package common_field_pkg is
function field_slv_in_len (field_arr : t_common_field_arr ) return natural;
function field_slv_out_len (field_arr : t_common_field_arr ) return natural;
function field_nof_words (field_arr : t_common_field_arr; word_w : natural ) return natural;
- function field_map_in (field_arr : t_common_field_arr; slv : std_logic_vector; word_w : natural ; mode : string) return std_logic_vector; -- returns word_arr
- function field_map_out (field_arr : t_common_field_arr; word_arr : std_logic_vector; word_w : natural ) return std_logic_vector; -- returns slv_out
- function field_map (field_arr : t_common_field_arr; word_arr_in: std_logic_vector; word_arr_out: std_logic_vector; word_w : natural) return std_logic_vector; -- returns word_arr
+ -- returns word_arr
+ function field_map_in (field_arr : t_common_field_arr; slv : std_logic_vector; word_w : natural ; mode : string) return std_logic_vector;
+ -- returns slv_out
+ function field_map_out (field_arr : t_common_field_arr; word_arr : std_logic_vector; word_w : natural ) return std_logic_vector;
+ -- returns word_arr
+ function field_map (field_arr : t_common_field_arr; word_arr_in: std_logic_vector; word_arr_out: std_logic_vector; word_w : natural) return std_logic_vector;
function field_ovr_arr(field_arr : t_common_field_arr; ovr_init: std_logic_vector) return t_common_field_arr;
@@ -140,14 +144,16 @@ package body common_field_pkg is
begin
if field_exists(field_arr, name) then
for i in 0 to field_arr'high loop
- if field_arr(i).mode = field_mode(field_arr, name) then -- increment index only for the "RO" = IN or the "RW" = OUT
+ -- increment index only for the "RO" = IN or the "RW" = OUT
+ if field_arr(i).mode = field_mode(field_arr, name) then
v_acc_hi := v_acc_hi + field_arr(i).size;
if field_arr(i).name = field_name_pad(name) then
return v_acc_hi - 1;
end if;
end if;
end loop;
- else -- field does not exist; return -1 which results in null array
+ -- field does not exist; return -1 which results in null array
+ else
return - 1;
end if;
end field_hi;
@@ -170,7 +176,8 @@ package body common_field_pkg is
begin
if field_exists(field_arr, name) then
for i in 0 to field_arr'high loop
- if field_arr(i).mode = field_mode(field_arr, name) then -- increment index only for the "RO" = IN or the "RW" = OUT
+ -- increment index only for the "RO" = IN or the "RW" = OUT
+ if field_arr(i).mode = field_mode(field_arr, name) then
v_acc_hi := v_acc_hi + field_arr(i).size;
if field_arr(i).name = field_name_pad(name) then
return v_acc_hi - field_arr(i).size;
@@ -250,7 +257,8 @@ package body common_field_pkg is
begin
for f in 0 to field_arr'high loop
-- Only extract the fields that are inputs
- if field_arr(f).mode = mode then -- if mode="RO" then slv = slv_in, else if mode="RW" then slv = slv_out
+ -- if mode="RO" then slv = slv_in, else if mode="RW" then slv = slv_out
+ if field_arr(f).mode = mode then
-- Extract the field
v_word_arr( v_word_cnt * word_w + field_arr(f).size-1 downto v_word_cnt * word_w) := slv( field_hi(field_arr, field_arr(f).name) downto field_lo(field_arr, field_arr(f).name) );
end if;
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc.vhd b/libraries/base/common/src/vhdl/common_fifo_dc.vhd
index 08ad5365defe15e0e22c3acc25a08d01082688be..733a7472071cb05504939118c2069bfccb825139 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc.vhd
@@ -29,10 +29,13 @@ use technology_lib.technology_select_pkg.all;
entity common_fifo_dc is
generic (
g_technology : natural := c_tech_select_default;
- g_note_is_ful : boolean := true; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_fail_rd_emp : boolean := false; -- when TRUE report FAILURE when read from an empty FIFO
+ -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_note_is_ful : boolean := true;
+ -- when TRUE report FAILURE when read from an empty FIFO
+ g_fail_rd_emp : boolean := false;
g_dat_w : natural := 36;
- g_nof_words : natural := 256 -- 36 * 256 = 1 M9K
+ -- 36 * 256 = 1 M9K
+ g_nof_words : natural := 256
);
port (
rst : in std_logic;
@@ -52,7 +55,8 @@ entity common_fifo_dc is
end common_fifo_dc;
architecture str of common_fifo_dc is
- constant c_nof_words : natural := 2**ceil_log2(g_nof_words); -- ensure size is power of 2 for dual clock FIFO
+ -- ensure size is power of 2 for dual clock FIFO
+ constant c_nof_words : natural := 2**ceil_log2(g_nof_words);
signal wr_rst : std_logic;
signal wr_init : std_logic;
@@ -92,16 +96,20 @@ begin
port map (
in_rst => wr_rst,
clk => wr_clk,
- out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
+ -- assume init has finished g_delay_len cycles after release of wr_rst
+ out_rst => wr_init
);
wr_init_out <= wr_init;
-- The FIFO under read and over write protection are kept enabled in the MegaWizard
- wr_en <= wr_req and not wr_init; -- check on NOT ful is not necessary when overflow_checking="ON" (Altera) or according to fifo_generator_ug175.pdf (Xilinx)
- rd_en <= rd_req; -- check on NOT emp is not necessary when underflow_checking="ON" (Altera)
+ -- check on NOT ful is not necessary when overflow_checking="ON" (Altera) or according to fifo_generator_ug175.pdf (Xilinx)
+ wr_en <= wr_req and not wr_init;
+ -- check on NOT emp is not necessary when underflow_checking="ON" (Altera)
+ rd_en <= rd_req;
- nxt_rd_val <= rd_req and not emp; -- check on NOT emp is necessary for rd_val
+ -- check on NOT emp is necessary for rd_val
+ nxt_rd_val <= rd_req and not emp;
wr_ful <= ful when wr_init = '0' else '0';
@@ -121,7 +129,8 @@ begin
g_nof_words => c_nof_words
)
port map (
- aclr => wr_rst, -- MegaWizard fifo_dc seems to use aclr synchronous with wr_clk
+ -- MegaWizard fifo_dc seems to use aclr synchronous with wr_clk
+ aclr => wr_rst,
data => wr_dat,
rdclk => rd_clk,
rdreq => rd_en,
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd b/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
index f94b9e105487bac831a533128a1ecf0bfb35e6b0..0ce185587f155f4b13dac3f89bc3c47a5cc94e4e 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
@@ -79,15 +79,19 @@ use common_lib.common_pkg.all;
entity common_fifo_dc_lock_control is
generic (
- g_hold_wr_clk_rst : natural := 2; -- >= 1, nof cycles to hold the wr_clk_rst
- g_hold_dc_fifo_rst : natural := 7; -- >= 1, nof cycles to hold the dc_fifo_rst, sufficiently long for wr_clk to have restarted after wr_clk_rst release
+ -- >= 1, nof cycles to hold the wr_clk_rst
+ g_hold_wr_clk_rst : natural := 2;
+ -- >= 1, nof cycles to hold the dc_fifo_rst, sufficiently long for wr_clk to have restarted after wr_clk_rst release
+ g_hold_dc_fifo_rst : natural := 7;
g_rd_fill_level : natural := 8;
g_rd_fill_margin : natural := 1
);
port (
-- FIFO rd_clk domain
- rd_rst : in std_logic; -- connect to FIFO rd_rst
- rd_clk : in std_logic; -- connect to FIFO rd_clk
+ -- connect to FIFO rd_rst
+ rd_rst : in std_logic;
+ -- connect to FIFO rd_clk
+ rd_clk : in std_logic;
rd_usedw : in std_logic_vector;
rd_req : out std_logic;
wr_clk_rst : out std_logic;
@@ -102,11 +106,14 @@ entity common_fifo_dc_lock_control is
end common_fifo_dc_lock_control;
architecture rtl of common_fifo_dc_lock_control is
- constant c_fifo_latency : natural := 10; -- large enough to ensure that the FIFO filling has started, but small enough such that the FIFO is not filled yet
+ -- large enough to ensure that the FIFO filling has started, but small enough such that the FIFO is not filled yet
+ constant c_fifo_latency : natural := 10;
constant c_fill_level_max : natural := 2**rd_usedw'length - 1;
- constant c_cnt_arr : t_natural_arr := (g_hold_wr_clk_rst, g_hold_dc_fifo_rst, c_fifo_latency); -- array to hold all timeouts
- constant c_cnt_max : natural := largest(c_cnt_arr); -- largest of all timeouts
+ -- array to hold all timeouts
+ constant c_cnt_arr : t_natural_arr := (g_hold_wr_clk_rst, g_hold_dc_fifo_rst, c_fifo_latency);
+ -- largest of all timeouts
+ constant c_cnt_max : natural := largest(c_cnt_arr);
constant c_cnt_w : natural := ceil_log2(c_cnt_max + 1);
type t_state is (s_detect_wr_clk, s_restart_wr_clk, s_reset_fifo, s_init_fifo, s_fill_fifo, s_fill_level, s_dc_locked, s_dc_lost);
@@ -172,7 +179,8 @@ begin
when s_restart_wr_clk =>
cnt_en <= '1';
if unsigned(cnt) < g_hold_wr_clk_rst then
- nxt_wr_clk_rst <= '1'; -- reset and restart the external write clock divider by asserting wr_clk_rst for g_hold_wr_clk_rst cycles of the rd_clk
+ -- reset and restart the external write clock divider by asserting wr_clk_rst for g_hold_wr_clk_rst cycles of the rd_clk
+ nxt_wr_clk_rst <= '1';
else
cnt_clr <= '1';
nxt_state <= s_reset_fifo;
@@ -180,7 +188,8 @@ begin
when s_reset_fifo =>
cnt_en <= '1';
if unsigned(cnt) < g_hold_dc_fifo_rst then
- nxt_dc_fifo_rst <= '1'; -- reset the input FIFO until the wr_clk has been able to restart for sure
+ -- reset the input FIFO until the wr_clk has been able to restart for sure
+ nxt_dc_fifo_rst <= '1';
else
cnt_clr <= '1';
nxt_state <= s_init_fifo;
@@ -218,8 +227,10 @@ begin
-- the FIFO fill level changed (too much) so the lock is lost
nxt_state <= s_dc_lost;
end if;
- when others => -- s_dc_lost
- nxt_dc_fifo_rst <= '1'; -- reset the input FIFO to reset rd_usedw
+ -- s_dc_lost
+ when others =>
+ -- reset the input FIFO to reset rd_usedw
+ nxt_dc_fifo_rst <= '1';
nxt_state <= s_detect_wr_clk;
end case;
end process;
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd b/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
index 32aaf05a36d63454b735525c1fa03e4e4248b8b4..2dd1133163b253c009f41892033260c9f3afa2e6 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
@@ -48,10 +48,14 @@ use technology_lib.technology_select_pkg.all;
entity common_fifo_dc_mixed_widths is
generic (
g_technology : natural := c_tech_select_default;
- g_note_is_ful : boolean := true; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_fail_rd_emp : boolean := false; -- when TRUE report FAILURE when read from an empty FIFO
- g_nof_words : natural := c_bram_m9k_fifo_depth; -- FIFO size in nof wr_dat words
- g_wr_dat_w : natural := 36; -- 36 * 256 = 1 M9K
+ -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_note_is_ful : boolean := true;
+ -- when TRUE report FAILURE when read from an empty FIFO
+ g_fail_rd_emp : boolean := false;
+ -- FIFO size in nof wr_dat words
+ g_nof_words : natural := c_bram_m9k_fifo_depth;
+ -- 36 * 256 = 1 M9K
+ g_wr_dat_w : natural := 36;
g_rd_dat_w : natural := 9
);
port (
@@ -71,7 +75,8 @@ entity common_fifo_dc_mixed_widths is
end common_fifo_dc_mixed_widths;
architecture str of common_fifo_dc_mixed_widths is
- constant c_nof_words : natural := 2**ceil_log2(g_nof_words); -- ensure size is power of 2 for dual clock FIFO
+ -- ensure size is power of 2 for dual clock FIFO
+ constant c_nof_words : natural := 2**ceil_log2(g_nof_words);
signal wr_rst : std_logic;
signal wr_init : std_logic;
@@ -111,14 +116,18 @@ begin
port map (
in_rst => wr_rst,
clk => wr_clk,
- out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
+ -- assume init has finished g_delay_len cycles after release of wr_rst
+ out_rst => wr_init
);
-- The FIFO under read and over write protection are kept enabled in the MegaWizard
- wr_en <= wr_req and not wr_init; -- check on NOT ful is not necessary according to fifo_generator_ug175.pdf
- rd_en <= rd_req; -- check on NOT emp is not necessary
+ -- check on NOT ful is not necessary according to fifo_generator_ug175.pdf
+ wr_en <= wr_req and not wr_init;
+ -- check on NOT emp is not necessary
+ rd_en <= rd_req;
- nxt_rd_val <= rd_req and not emp; -- check on NOT emp is necessary for rd_val
+ -- check on NOT emp is necessary for rd_val
+ nxt_rd_val <= rd_req and not emp;
wr_ful <= ful;
rd_emp <= emp;
@@ -138,7 +147,8 @@ begin
g_rddat_w => g_rd_dat_w
)
port map (
- aclr => wr_rst, -- MegaWizard fifo_dc_mixed_widths seems to use aclr synchronous with wr_clk
+ -- MegaWizard fifo_dc_mixed_widths seems to use aclr synchronous with wr_clk
+ aclr => wr_rst,
data => wr_dat,
rdclk => rd_clk,
rdreq => rd_en,
diff --git a/libraries/base/common/src/vhdl/common_fifo_sc.vhd b/libraries/base/common/src/vhdl/common_fifo_sc.vhd
index 302f5c2225f88fc1a3bcc4abdbcfc0fd4951156d..ff2be6a4ce335afde4058629a25cfe6d81641c24 100644
--- a/libraries/base/common/src/vhdl/common_fifo_sc.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_sc.vhd
@@ -29,16 +29,23 @@ use technology_lib.technology_select_pkg.all;
entity common_fifo_sc is
generic (
g_technology : natural := c_tech_select_default;
- g_note_is_ful : boolean := true; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_fail_rd_emp : boolean := false; -- when TRUE report FAILURE when read from an empty FIFO
- g_use_lut : boolean := false; -- when TRUE then force using LUTs via Altera eab="OFF",
+ -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_note_is_ful : boolean := true;
+ -- when TRUE report FAILURE when read from an empty FIFO
+ g_fail_rd_emp : boolean := false;
+ -- when TRUE then force using LUTs via Altera eab="OFF",
+ g_use_lut : boolean := false;
-- else use default eab="ON" and ram_block_type="AUTO", default ram_block_type="AUTO" is sufficient, because
-- there seems no need to force using RAM and there are two types of Stratix IV RAM (M9K and M144K)
- g_reset : boolean := false; -- when TRUE release FIFO reset some cycles after rst release, else use rst directly
- g_init : boolean := false; -- when TRUE force wr_req inactive for some cycles after FIFO reset release, else use wr_req as is
- g_dat_w : natural := 36; -- 36 * 256 = 1 M9K
+ -- when TRUE release FIFO reset some cycles after rst release, else use rst directly
+ g_reset : boolean := false;
+ -- when TRUE force wr_req inactive for some cycles after FIFO reset release, else use wr_req as is
+ g_init : boolean := false;
+ -- 36 * 256 = 1 M9K
+ g_dat_w : natural := 36;
g_nof_words : natural := c_bram_m9k_fifo_depth;
- g_af_margin : natural := 0 -- FIFO almost full margin for wr_aful flagging
+ -- FIFO almost full margin for wr_aful flagging
+ g_af_margin : natural := 0
);
port (
rst : in std_logic;
@@ -46,7 +53,8 @@ entity common_fifo_sc is
wr_dat : in std_logic_vector(g_dat_w - 1 downto 0);
wr_req : in std_logic;
wr_ful : out std_logic;
- wr_aful : out std_logic; -- registered FIFO almost full flag
+ -- registered FIFO almost full flag
+ wr_aful : out std_logic;
rd_dat : out std_logic_vector(g_dat_w - 1 downto 0);
rd_req : in std_logic;
rd_emp : out std_logic;
@@ -56,10 +64,13 @@ entity common_fifo_sc is
end common_fifo_sc;
architecture str of common_fifo_sc is
- constant c_use_eab : string := sel_a_b(g_use_lut, "OFF", "ON"); -- when g_use_lut=TRUE then force using LUTs via Altera eab="OFF", else default to ram_block_type = "AUTO"
+ -- when g_use_lut=TRUE then force using LUTs via Altera eab="OFF", else default to ram_block_type = "AUTO"
+ constant c_use_eab : string := sel_a_b(g_use_lut, "OFF", "ON");
- constant c_fifo_af_latency : natural := 1; -- pipeline register wr_aful
- constant c_fifo_af_margin : natural := g_af_margin + c_fifo_af_latency; -- FIFO almost full level
+ -- pipeline register wr_aful
+ constant c_fifo_af_latency : natural := 1;
+ -- FIFO almost full level
+ constant c_fifo_af_margin : natural := g_af_margin + c_fifo_af_latency;
signal fifo_rst : std_logic;
signal fifo_init : std_logic;
@@ -120,21 +131,25 @@ begin
end process;
nxt_fifo_wr_dat <= wr_dat;
- nxt_fifo_wr_en <= wr_req and not fifo_init; -- check on NOT full is not necessary according to fifo_generator_ug175.pdf
+ -- check on NOT full is not necessary according to fifo_generator_ug175.pdf
+ nxt_fifo_wr_en <= wr_req and not fifo_init;
end generate;
no_init : if g_init = false generate
fifo_wr_dat <= wr_dat;
- fifo_wr_en <= wr_req; -- check on NOT full is not necessary according to fifo_generator_ug175.pdf
+ -- check on NOT full is not necessary according to fifo_generator_ug175.pdf
+ fifo_wr_en <= wr_req;
end generate;
wr_ful <= fifo_full;
rd_emp <= fifo_empty;
usedw <= fifo_usedw;
- fifo_rd_en <= rd_req; -- check on NOT empty is not necessary according to fifo_generator_ds317.pdf, so skip it to easy synthesis timing
+ -- check on NOT empty is not necessary according to fifo_generator_ds317.pdf, so skip it to easy synthesis timing
+ fifo_rd_en <= rd_req;
- nxt_rd_val <= fifo_rd_en and not fifo_empty; -- check on NOT empty is necessary for rd_val
+ -- check on NOT empty is necessary for rd_val
+ nxt_rd_val <= fifo_rd_en and not fifo_empty;
nxt_wr_aful <= '0' when TO_UINT(fifo_usedw) < g_nof_words - c_fifo_af_margin else '1';
diff --git a/libraries/base/common/src/vhdl/common_init.vhd b/libraries/base/common/src/vhdl/common_init.vhd
index 0dbfdf1c99393accdae15efcd5f7650ee4307150..74462c63d42c6ecade260a0620095cb09aa79c4a 100644
--- a/libraries/base/common/src/vhdl/common_init.vhd
+++ b/libraries/base/common/src/vhdl/common_init.vhd
@@ -41,7 +41,8 @@ use IEEE.std_logic_1164.all;
entity common_init is
generic (
- g_latency_w : natural := 4 -- >= 1
+ -- >= 1
+ g_latency_w : natural := 4
);
port (
rst : in std_logic;
@@ -52,7 +53,8 @@ entity common_init is
end;
architecture rtl of common_init is
- signal cnt : std_logic_vector(g_latency_w downto 0); -- use cnt(g_latency_w) to stop the counter
+ -- use cnt(g_latency_w) to stop the counter
+ signal cnt : std_logic_vector(g_latency_w downto 0);
signal cnt_en : std_logic;
signal prev_cnt_en : std_logic;
diff --git a/libraries/base/common/src/vhdl/common_inout.vhd b/libraries/base/common/src/vhdl/common_inout.vhd
index ba4efdbf26440dd4fc149816a28fd4c1247db5e9..1f5f793b1559b0b7a3e142adbe5ea53a930afc36 100644
--- a/libraries/base/common/src/vhdl/common_inout.vhd
+++ b/libraries/base/common/src/vhdl/common_inout.vhd
@@ -28,8 +28,10 @@ entity common_inout is
port (
dat_inout : inout std_logic;
dat_in_from_line : out std_logic;
- dat_out_to_line : in std_logic := '0'; -- default drive INOUT low when output enabled
- dat_out_en : in std_logic := '0' -- output enable, default use INOUT as tristate input
+ -- default drive INOUT low when output enabled
+ dat_out_to_line : in std_logic := '0';
+ -- output enable, default use INOUT as tristate input
+ dat_out_en : in std_logic := '0'
);
end common_inout;
@@ -37,5 +39,6 @@ architecture rtl of common_inout is
begin
dat_inout <= 'Z' when dat_out_en = '0' else dat_out_to_line;
- dat_in_from_line <= not (not dat_inout); -- do via NOT(NOT) for simulation to force 'H' -> '1' and 'L' --> '0'
+ -- do via NOT(NOT) for simulation to force 'H' -> '1' and 'L' --> '0'
+ dat_in_from_line <= not (not dat_inout);
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd b/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
index 42890418c20ba63f325edd89b045fcd291aed20f..0234804c81c5415298cfb9a7508f1a67572361c4 100644
--- a/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
@@ -48,11 +48,14 @@ package common_interface_layers_pkg is
constant c_xgmii_d_start : std_logic_vector(c_xgmii_data_w - 1 downto 0) := x"00000000000000FB";
constant c_xgmii_d_term : std_logic_vector(c_xgmii_data_w - 1 downto 0) := x"07070707FD000000";
- constant c_xgmii_c_init : std_logic_vector(c_xgmii_nof_lanes - 1 downto 0) := x"11"; -- During (re)initialization
+ -- During (re)initialization
+ constant c_xgmii_c_init : std_logic_vector(c_xgmii_nof_lanes - 1 downto 0) := x"11";
constant c_xgmii_c_idle : std_logic_vector(c_xgmii_nof_lanes - 1 downto 0) := x"FF";
constant c_xgmii_c_data : std_logic_vector(c_xgmii_nof_lanes - 1 downto 0) := x"00";
- constant c_xgmii_c_start : std_logic_vector(c_xgmii_nof_lanes - 1 downto 0) := x"01"; -- b'00000001' as byte 0 contains START word FB
- constant c_xgmii_c_term : std_logic_vector(c_xgmii_nof_lanes - 1 downto 0) := x"F8"; -- b'11111000' as byte 3 contains TERMINATE word FD, bytes 7..4 are IDLE.
+ -- b'00000001' as byte 0 contains START word FB
+ constant c_xgmii_c_start : std_logic_vector(c_xgmii_nof_lanes - 1 downto 0) := x"01";
+ -- b'11111000' as byte 3 contains TERMINATE word FD, bytes 7..4 are IDLE.
+ constant c_xgmii_c_term : std_logic_vector(c_xgmii_nof_lanes - 1 downto 0) := x"F8";
function func_xgmii_dc( data : in std_logic_vector(c_xgmii_data_w - 1 downto 0); ctrl : in std_logic_vector(c_xgmii_nof_lanes - 1 downto 0)) return std_logic_vector;
function func_xgmii_d( data_ctrl: in std_logic_vector(c_xgmii_w - 1 downto 0)) return std_logic_vector;
diff --git a/libraries/base/common/src/vhdl/common_interleave.vhd b/libraries/base/common/src/vhdl/common_interleave.vhd
index 11645c0f290e5b3c585ee51f7c6fb72b080e4210..507e3f326682df3c5cd8d6dd7c3ce641c92e949d 100644
--- a/libraries/base/common/src/vhdl/common_interleave.vhd
+++ b/libraries/base/common/src/vhdl/common_interleave.vhd
@@ -37,7 +37,8 @@ use work.common_pkg.all;
entity common_interleave is
generic (
- g_nof_in : natural; -- >= 2
+ -- >= 2
+ g_nof_in : natural;
g_dat_w : natural;
g_block_size : natural
);
diff --git a/libraries/base/common/src/vhdl/common_interval_monitor.vhd b/libraries/base/common/src/vhdl/common_interval_monitor.vhd
index 0056a8bce9da6f6ed79166ed515bd0f4f0373d4e..ceac4b4c400a2c45917b71a725cc9b798e6ef1b8 100644
--- a/libraries/base/common/src/vhdl/common_interval_monitor.vhd
+++ b/libraries/base/common/src/vhdl/common_interval_monitor.vhd
@@ -32,7 +32,8 @@ use common_lib.common_pkg.all;
entity common_interval_monitor is
generic (
- g_interval_cnt_w : natural := 20 -- wide enough to fit somewhat more than maximum nof valid clock cycles per interval
+ -- wide enough to fit somewhat more than maximum nof valid clock cycles per interval
+ g_interval_cnt_w : natural := 20
);
port (
rst : in std_logic;
diff --git a/libraries/base/common/src/vhdl/common_iobuf_in.vhd b/libraries/base/common/src/vhdl/common_iobuf_in.vhd
index 688910ed0dab3a8199c82df12ea5d574be9c0eff..c54279070d64cc09972402761f62f36aa11b6e70 100644
--- a/libraries/base/common/src/vhdl/common_iobuf_in.vhd
+++ b/libraries/base/common/src/vhdl/common_iobuf_in.vhd
@@ -29,7 +29,8 @@ entity common_iobuf_in is
generic(
g_device_family : string := "Stratix IV";
g_width : natural := 8;
- g_delay_arr : t_natural_arr := array_init(0, 8) -- nof must match g_width
+ -- nof must match g_width
+ g_delay_arr : t_natural_arr := array_init(0, 8)
);
port (
config_rst : in std_logic;
diff --git a/libraries/base/common/src/vhdl/common_led_controller.vhd b/libraries/base/common/src/vhdl/common_led_controller.vhd
index b0d2adbb0ec2383dad7d4deeb1e30d69849942ba..4a16434ea376531f44cdbc1739e814f7e29c5073 100644
--- a/libraries/base/common/src/vhdl/common_led_controller.vhd
+++ b/libraries/base/common/src/vhdl/common_led_controller.vhd
@@ -37,16 +37,20 @@ use common_lib.common_pkg.all;
entity common_led_controller is
generic (
- g_nof_ms : natural := 100 -- force LED off for g_nof_ms and then on for at least g_nof_ms
+ -- force LED off for g_nof_ms and then on for at least g_nof_ms
+ g_nof_ms : natural := 100
);
port (
rst : in std_logic;
clk : in std_logic;
- pulse_ms : in std_logic := '0'; -- pulses every ms, used to time the ctrl_evt effect on the led
+ -- pulses every ms, used to time the ctrl_evt effect on the led
+ pulse_ms : in std_logic := '0';
-- led control
ctrl_on : in std_logic := '0';
- ctrl_evt : in std_logic := '0'; -- when ctrl_on='1' then the led output is on and pulses off for g_nof_ms when a ctrl_evt='1' event pulse occurs
- ctrl_input : in std_logic := '0'; -- when ctrl_on='0' then use ctrl_input to control the led output
+ -- when ctrl_on='1' then the led output is on and pulses off for g_nof_ms when a ctrl_evt='1' event pulse occurs
+ ctrl_evt : in std_logic := '0';
+ -- when ctrl_on='0' then use ctrl_input to control the led output
+ ctrl_input : in std_logic := '0';
-- led output
led : out std_logic
);
@@ -111,7 +115,8 @@ begin
nxt_state <= s_on;
end if;
end if;
- when others => -- s_on
+ -- s_on
+ when others =>
if pulse_ms_reg = '1' then
nxt_cnt <= cnt + 1;
if cnt = g_nof_ms then
diff --git a/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd b/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
index 3f11c037e9a5958791241439b19654ea710b8fff..8ffc6d433e6c08d63312401b90c052ff162a4986 100644
--- a/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
@@ -36,7 +36,8 @@ use work.common_pkg.all;
package common_lfsr_sequences_pkg is
constant c_common_lfsr_max_nof_feedbacks : natural := 6;
- constant c_common_lfsr_first : natural := 1; -- also support n = 1 and 2 in addition to n >= 3
+ -- also support n = 1 and 2 in addition to n >= 3
+ constant c_common_lfsr_first : natural := 1;
type t_FEEDBACKS is array (c_common_lfsr_max_nof_feedbacks - 1 downto 0) of natural;
type t_SEQUENCES is array (natural range <>) of t_FEEDBACKS;
@@ -51,78 +52,150 @@ package common_lfsr_sequences_pkg is
-- (0,0,0,0, 2, 1) yields repeat <0, 1, 2>
-- XNOR feedbacks from outputs for n = 3 .. 72 from Xilinx xapp052.pdf (that lists feedbacks for in total 168 sequences)
- constant c_common_lfsr_sequences : t_SEQUENCES := ((0,0,0,0,0, 1), -- 1 : <0, 1>
- (0,0,0,0, 0, 2), -- 2 : <0, 1, 3, 2>
- (0,0,0,0, 3, 2), -- 3
- (0,0,0,0, 4, 3), -- 4
- (0,0,0,0, 5, 3), -- 5
- (0,0,0,0, 6, 5), -- 6
- (0,0,0,0, 7, 6), -- 7
- (0,0, 8, 6, 5, 4), -- 8
- (0,0,0,0, 9, 5), -- 9
- (0,0,0,0, 10, 7), -- 10
- (0,0,0,0, 11, 9), -- 11
- (0,0, 12, 6, 4, 1), -- 12
- (0,0, 13, 4, 3, 1), -- 13
- (0,0, 14, 5, 3, 1), -- 14
- (0,0,0,0, 15,14 ), -- 15
- (0,0, 16,15,13, 4), -- 16
- (0,0,0,0, 17,14 ), -- 17
- (0,0,0,0, 18,11 ), -- 18
- (0,0, 19, 6, 2, 1), -- 19
- (0,0,0,0, 20,17 ), -- 20
- (0,0,0,0, 21,19 ), -- 21
- (0,0,0,0, 22,21 ), -- 22
- (0,0,0,0, 23,18 ), -- 23
- (0,0, 24,23,22,17), -- 24
- (0,0,0,0, 25,22 ), -- 25
- (0,0, 26, 6, 2, 1), -- 26
- (0,0, 27, 5, 2, 1), -- 27
- (0,0,0,0, 28,25 ), -- 28
- (0,0,0,0, 29,27 ), -- 29
- (0,0, 30, 6, 4, 1), -- 30
- (0,0,0,0, 31,28 ), -- 31
- (0,0, 32,22, 2, 1), -- 32
- (0,0,0,0, 33,20 ), -- 33
- (0,0, 34,27, 2, 1), -- 34
- (0,0,0,0, 35,33 ), -- 35
- (0,0,0,0, 36,25 ), -- 36
- ( 37, 5, 4, 3, 2, 1), -- 37
- (0,0, 38, 6, 5, 1), -- 38
- (0,0,0,0, 39,35 ), -- 39
- (0,0, 40,38,21,19), -- 40
- (0,0,0,0, 41,38 ), -- 41
- (0,0, 42,41,20,19), -- 42
- (0,0, 43,42,38,37), -- 43
- (0,0, 44,43,18,17), -- 44
- (0,0, 45,44,42,41), -- 45
- (0,0, 46,45,26,25), -- 46
- (0,0,0,0, 47,42 ), -- 47
- (0,0, 48,47,21,20), -- 48
- (0,0,0,0, 49,40 ), -- 49
- (0,0, 50,49,24,23), -- 50
- (0,0, 51,50,36,35), -- 51
- (0,0,0,0, 52,49 ), -- 52
- (0,0, 53,52,38,37), -- 53
- (0,0, 54,53,18,17), -- 54
- (0,0,0,0, 55,31 ), -- 55
- (0,0, 56,55,35,34), -- 56
- (0,0,0,0, 57,50 ), -- 57
- (0,0,0,0, 58,39 ), -- 58
- (0,0, 59,58,38,37), -- 59
- (0,0,0,0, 60,59 ), -- 60
- (0,0, 61,60,46,45), -- 61
- (0,0, 62,61, 6, 5), -- 62
- (0,0,0,0, 63,62 ), -- 63
- (0,0, 64,63,61,60), -- 64
- (0,0,0,0, 65,47 ), -- 65
- (0,0, 66,65,57,56), -- 66
- (0,0, 67,66,58,57), -- 67
- (0,0,0,0, 68,59 ), -- 68
- (0,0, 69,67,42,40), -- 69
- (0,0, 70,69,55,54), -- 70
- (0,0,0,0, 71,65 ), -- 71
- (0,0, 72,66,25,19)); -- 72
+ -- 1 : <0, 1>
+ constant c_common_lfsr_sequences : t_SEQUENCES := ((0,0,0,0,0, 1),
+ -- 2 : <0, 1, 3, 2>
+ (0,0,0,0, 0, 2),
+ -- 3
+ (0,0,0,0, 3, 2),
+ -- 4
+ (0,0,0,0, 4, 3),
+ -- 5
+ (0,0,0,0, 5, 3),
+ -- 6
+ (0,0,0,0, 6, 5),
+ -- 7
+ (0,0,0,0, 7, 6),
+ -- 8
+ (0,0, 8, 6, 5, 4),
+ -- 9
+ (0,0,0,0, 9, 5),
+ -- 10
+ (0,0,0,0, 10, 7),
+ -- 11
+ (0,0,0,0, 11, 9),
+ -- 12
+ (0,0, 12, 6, 4, 1),
+ -- 13
+ (0,0, 13, 4, 3, 1),
+ -- 14
+ (0,0, 14, 5, 3, 1),
+ -- 15
+ (0,0,0,0, 15,14 ),
+ -- 16
+ (0,0, 16,15,13, 4),
+ -- 17
+ (0,0,0,0, 17,14 ),
+ -- 18
+ (0,0,0,0, 18,11 ),
+ -- 19
+ (0,0, 19, 6, 2, 1),
+ -- 20
+ (0,0,0,0, 20,17 ),
+ -- 21
+ (0,0,0,0, 21,19 ),
+ -- 22
+ (0,0,0,0, 22,21 ),
+ -- 23
+ (0,0,0,0, 23,18 ),
+ -- 24
+ (0,0, 24,23,22,17),
+ -- 25
+ (0,0,0,0, 25,22 ),
+ -- 26
+ (0,0, 26, 6, 2, 1),
+ -- 27
+ (0,0, 27, 5, 2, 1),
+ -- 28
+ (0,0,0,0, 28,25 ),
+ -- 29
+ (0,0,0,0, 29,27 ),
+ -- 30
+ (0,0, 30, 6, 4, 1),
+ -- 31
+ (0,0,0,0, 31,28 ),
+ -- 32
+ (0,0, 32,22, 2, 1),
+ -- 33
+ (0,0,0,0, 33,20 ),
+ -- 34
+ (0,0, 34,27, 2, 1),
+ -- 35
+ (0,0,0,0, 35,33 ),
+ -- 36
+ (0,0,0,0, 36,25 ),
+ -- 37
+ ( 37, 5, 4, 3, 2, 1),
+ -- 38
+ (0,0, 38, 6, 5, 1),
+ -- 39
+ (0,0,0,0, 39,35 ),
+ -- 40
+ (0,0, 40,38,21,19),
+ -- 41
+ (0,0,0,0, 41,38 ),
+ -- 42
+ (0,0, 42,41,20,19),
+ -- 43
+ (0,0, 43,42,38,37),
+ -- 44
+ (0,0, 44,43,18,17),
+ -- 45
+ (0,0, 45,44,42,41),
+ -- 46
+ (0,0, 46,45,26,25),
+ -- 47
+ (0,0,0,0, 47,42 ),
+ -- 48
+ (0,0, 48,47,21,20),
+ -- 49
+ (0,0,0,0, 49,40 ),
+ -- 50
+ (0,0, 50,49,24,23),
+ -- 51
+ (0,0, 51,50,36,35),
+ -- 52
+ (0,0,0,0, 52,49 ),
+ -- 53
+ (0,0, 53,52,38,37),
+ -- 54
+ (0,0, 54,53,18,17),
+ -- 55
+ (0,0,0,0, 55,31 ),
+ -- 56
+ (0,0, 56,55,35,34),
+ -- 57
+ (0,0,0,0, 57,50 ),
+ -- 58
+ (0,0,0,0, 58,39 ),
+ -- 59
+ (0,0, 59,58,38,37),
+ -- 60
+ (0,0,0,0, 60,59 ),
+ -- 61
+ (0,0, 61,60,46,45),
+ -- 62
+ (0,0, 62,61, 6, 5),
+ -- 63
+ (0,0,0,0, 63,62 ),
+ -- 64
+ (0,0, 64,63,61,60),
+ -- 65
+ (0,0,0,0, 65,47 ),
+ -- 66
+ (0,0, 66,65,57,56),
+ -- 67
+ (0,0, 67,66,58,57),
+ -- 68
+ (0,0,0,0, 68,59 ),
+ -- 69
+ (0,0, 69,67,42,40),
+ -- 70
+ (0,0, 70,69,55,54),
+ -- 71
+ (0,0,0,0, 71,65 ),
+ -- 72
+ (0,0, 72,66,25,19));
-- Procedure for calculating the next PSRG and COUNTER sequence value
procedure common_lfsr_nxt_seq(constant c_lfsr_nr : in natural;
@@ -156,10 +229,12 @@ package body common_lfsr_sequences_pkg is
begin
nxt_prsg <= prsg;
nxt_cntr <= cntr;
- if in_en = '0' then -- init reference value
+ -- init reference value
+ if in_en = '0' then
nxt_prsg <= in_dat;
nxt_cntr <= in_dat;
- elsif in_req = '1' then -- next reference value
+ -- next reference value
+ elsif in_req = '1' then
-- PRSG shift
nxt_prsg <= prsg(prsg'high - 1 downto 0) & '0';
-- PRSG feedback
diff --git a/libraries/base/common/src/vhdl/common_math_pkg.vhd b/libraries/base/common/src/vhdl/common_math_pkg.vhd
index 2dfec614b7bf5b0c4097f7f3de7a92e5be8ff8a0..78c0c498133f3ee3e2b628dfded0f11c2f33ee41 100644
--- a/libraries/base/common/src/vhdl/common_math_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_math_pkg.vhd
@@ -76,7 +76,8 @@ package common_math_pkg is
-- A complex FFT of N points has N bins or channels: ch = -N/2:0:N/2-1.
-- To create an FFT input phasor with frequency in the middle of a channel use FREQ = ch.
function common_math_create_look_up_table_phasor(N, W : positive; AMPL, FREQ, PHI : real) return t_nat_integer_arr;
- function common_math_create_look_up_table_phasor(N, W : positive; AMPL, FREQ, PHI : real) return t_slv_32_arr; -- range 0 TO N-1
+ -- range 0 TO N-1
+ function common_math_create_look_up_table_phasor(N, W : positive; AMPL, FREQ, PHI : real) return t_slv_32_arr;
function common_math_create_random_arr(N, W : positive; seed : natural) return t_integer_arr;
end common_math_pkg;
@@ -164,7 +165,8 @@ package body common_math_pkg is
constant c_sin_arr : t_nat_integer_arr := common_math_create_look_up_table_sin(N, AMPL, FREQ, PHI);
constant c_exp_arr : t_nat_integer_arr := common_math_concat_look_up_table(c_sin_arr, c_cos_arr, W);
begin
- return c_exp_arr; -- Concatenated W bit sin imag part & W bit cos real part
+ -- Concatenated W bit sin imag part & W bit cos real part
+ return c_exp_arr;
end;
function common_math_create_look_up_table_phasor(N, W : positive; AMPL, FREQ, PHI : real) return t_slv_32_arr is
diff --git a/libraries/base/common/src/vhdl/common_mem_demux.vhd b/libraries/base/common/src/vhdl/common_mem_demux.vhd
index 26692341887b313712ead728d2c962313facef82..8f9f880fb661b649ac3717a148b995bd495fcb05 100644
--- a/libraries/base/common/src/vhdl/common_mem_demux.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_demux.vhd
@@ -56,12 +56,15 @@ use common_lib.common_mem_pkg.all;
entity common_mem_demux is
generic (
- g_nof_mosi : positive := 256; -- Number of memory interfaces in the array.
- g_mult_addr_w : positive := 8; -- Address width of each memory-interface element in the muliplexed array.
+ -- Number of memory interfaces in the array.
+ g_nof_mosi : positive := 256;
+ -- Address width of each memory-interface element in the muliplexed array.
+ g_mult_addr_w : positive := 8;
g_rd_latency : natural := 0
);
port (
- clk : in std_logic := '0'; -- only used when g_rd_latency > 0
+ -- only used when g_rd_latency > 0
+ clk : in std_logic := '0';
mosi_arr : in t_mem_mosi_arr(g_nof_mosi - 1 downto 0);
miso_arr : out t_mem_miso_arr(g_nof_mosi - 1 downto 0);
mosi : out t_mem_mosi;
@@ -74,8 +77,10 @@ architecture rtl of common_mem_demux is
constant c_total_addr_w : natural := c_index_w + g_mult_addr_w;
signal index_arr : t_natural_arr(0 to g_rd_latency);
- signal index_rw : natural; -- read or write access
- signal index_rd : natural; -- read response
+ -- read or write access
+ signal index_rw : natural;
+ -- read response
+ signal index_rd : natural;
begin
gen_single : if g_nof_mosi = 1 generate
mosi <= mosi_arr(0);
diff --git a/libraries/base/common/src/vhdl/common_mem_mux.vhd b/libraries/base/common/src/vhdl/common_mem_mux.vhd
index 17b494471e212fc87aba6ec98cc93e3f892d930f..3e0f792e90c3728d2c88dde8a5df730a683cd0f2 100644
--- a/libraries/base/common/src/vhdl/common_mem_mux.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_mux.vhd
@@ -64,12 +64,15 @@ use common_lib.common_mem_pkg.all;
entity common_mem_mux is
generic (
g_broadcast : boolean := false;
- g_nof_mosi : positive := 256; -- Number of memory interfaces in the array.
- g_mult_addr_w : positive := 8; -- Address width of each memory-interface element in the muliplexed array.
+ -- Number of memory interfaces in the array.
+ g_nof_mosi : positive := 256;
+ -- Address width of each memory-interface element in the muliplexed array.
+ g_mult_addr_w : positive := 8;
g_rd_latency : natural := 0
);
port (
- clk : in std_logic := '0'; -- only used when g_rd_latency > 0
+ -- only used when g_rd_latency > 0
+ clk : in std_logic := '0';
mosi : in t_mem_mosi;
miso : out t_mem_miso;
mosi_arr : out t_mem_mosi_arr(g_nof_mosi - 1 downto 0);
@@ -82,8 +85,10 @@ architecture rtl of common_mem_mux is
constant c_total_addr_w : natural := c_index_w + g_mult_addr_w;
signal index_arr : t_natural_arr(0 to g_rd_latency);
- signal index_rw : natural; -- read or write access
- signal index_rd : natural; -- read response
+ -- read or write access
+ signal index_rw : natural;
+ -- read response
+ signal index_rd : natural;
begin
gen_single : if g_broadcast = false and g_nof_mosi = 1 generate
mosi_arr(0) <= mosi;
@@ -132,8 +137,10 @@ begin
end generate;
gen_broadcast : if g_broadcast = true generate
- mosi_arr <= (others => mosi); -- broadcast write to all [g_nof_mosi-1:0] MM ports
- miso <= miso_arr(0); -- broadcast read only from MM port [0]
+ -- broadcast write to all [g_nof_mosi-1:0] MM ports
+ mosi_arr <= (others => mosi);
+ -- broadcast read only from MM port [0]
+ miso <= miso_arr(0);
end generate;
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_mem_pkg.vhd b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
index 9f035bdfd442ab3c23d9086666076bdfbb92b927..9f1e82b10c9c491405c24795a4b5a2cb93d1662a 100644
--- a/libraries/base/common/src/vhdl/common_mem_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
@@ -54,20 +54,27 @@ use work.common_pkg.all;
package common_mem_pkg is
-- Choose smallest maximum slv lengths that fit all use cases, because unconstrained record fields slv is not allowed
- constant c_mem_address_w : natural := 32; -- address range (suits 32-bit processor)
- constant c_mem_data_w : natural := 72; -- data width (suit up to 8 bytes, that can also be 9 bit bytes)
+ -- address range (suits 32-bit processor)
+ constant c_mem_address_w : natural := 32;
+ -- data width (suit up to 8 bytes, that can also be 9 bit bytes)
+ constant c_mem_data_w : natural := 72;
constant c_mem_address_sz : natural := c_mem_address_w / c_byte_w;
constant c_mem_data_sz : natural := c_mem_data_w / c_byte_w;
- type t_mem_miso is record -- Master In Slave Out. For backward compatibility only. Use t_mem_copi for new designs.
- rddata : std_logic_vector(c_mem_data_w - 1 downto 0); -- data width (suits 1, 2 or 4 bytes)
+ -- Master In Slave Out. For backward compatibility only. Use t_mem_copi for new designs.
+ type t_mem_miso is record
+ -- data width (suits 1, 2 or 4 bytes)
+ rddata : std_logic_vector(c_mem_data_w - 1 downto 0);
rdval : std_logic;
waitrequest : std_logic;
end record;
- type t_mem_mosi is record -- Master Out Slave In. For backward compatibility only. Use t_mem_cipo for new designs.
- address : std_logic_vector(c_mem_address_w - 1 downto 0); -- address range (suits 32-bit processor)
- wrdata : std_logic_vector(c_mem_data_w - 1 downto 0); -- data width (suits 1, 2 or 4 bytes)
+ -- Master Out Slave In. For backward compatibility only. Use t_mem_cipo for new designs.
+ type t_mem_mosi is record
+ -- address range (suits 32-bit processor)
+ address : std_logic_vector(c_mem_address_w - 1 downto 0);
+ -- data width (suits 1, 2 or 4 bytes)
+ wrdata : std_logic_vector(c_mem_data_w - 1 downto 0);
wr : std_logic;
rd : std_logic;
end record;
@@ -80,8 +87,10 @@ package common_mem_pkg is
type t_mem_mosi_arr is array (integer range <>) of t_mem_mosi;
-- MOSI/MISO subtypes
- subtype t_mem_copi is t_mem_mosi; -- Controller Out Peripheral In
- subtype t_mem_cipo is t_mem_miso; -- Peripheral In Controller Out
+ -- Controller Out Peripheral In
+ subtype t_mem_copi is t_mem_mosi;
+ -- Peripheral In Controller Out
+ subtype t_mem_cipo is t_mem_miso;
constant c_mem_cipo_rst : t_mem_cipo := c_mem_miso_rst;
constant c_mem_copi_rst : t_mem_copi := c_mem_mosi_rst;
@@ -90,24 +99,35 @@ package common_mem_pkg is
subtype t_mem_copi_arr is t_mem_mosi_arr;
-- Reset only the control fields of the MM record
- function RESET_MEM_MOSI_CTRL(mosi : t_mem_mosi) return t_mem_mosi; -- deprecated, use RESET_MEM_COPI_CTRL() instead
+ -- deprecated, use RESET_MEM_COPI_CTRL() instead
+ function RESET_MEM_MOSI_CTRL(mosi : t_mem_mosi) return t_mem_mosi;
function RESET_MEM_COPI_CTRL(copi : t_mem_copi) return t_mem_copi;
function RESET_MEM_COPI_CTRL(copi_arr : t_mem_copi_arr) return t_mem_copi_arr;
- function RESET_MEM_MISO_CTRL(miso : t_mem_miso) return t_mem_miso; -- deprecated, use RESET_MEM_CIPO_CTRL() instead
+ -- deprecated, use RESET_MEM_CIPO_CTRL() instead
+ function RESET_MEM_MISO_CTRL(miso : t_mem_miso) return t_mem_miso;
function RESET_MEM_CIPO_CTRL(cipo : t_mem_cipo) return t_mem_cipo;
function RESET_MEM_CIPO_CTRL(cipo_arr : t_mem_cipo_arr) return t_mem_cipo_arr;
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width
- function TO_MEM_ADDRESS(n : integer) return std_logic_vector; -- unsigned, use integer to support 32 bit range
- function TO_MEM_DATA( n : integer) return std_logic_vector; -- unsigned, alias of TO_MEM_DATA()
- function TO_MEM_UDATA( n : integer) return std_logic_vector; -- unsigned, use integer to support 32 bit range
- function TO_MEM_SDATA( n : integer) return std_logic_vector; -- sign extended
- function RESIZE_MEM_ADDRESS(vec : std_logic_vector) return std_logic_vector; -- unsigned
- function RESIZE_MEM_DATA( vec : std_logic_vector) return std_logic_vector; -- unsigned, alias of RESIZE_MEM_UDATA
- function RESIZE_MEM_UDATA( vec : std_logic_vector) return std_logic_vector; -- unsigned
- function RESIZE_MEM_SDATA( vec : std_logic_vector) return std_logic_vector; -- sign extended
- function RESIZE_MEM_XDATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
+ -- unsigned, use integer to support 32 bit range
+ function TO_MEM_ADDRESS(n : integer) return std_logic_vector;
+ -- unsigned, alias of TO_MEM_DATA()
+ function TO_MEM_DATA( n : integer) return std_logic_vector;
+ -- unsigned, use integer to support 32 bit range
+ function TO_MEM_UDATA( n : integer) return std_logic_vector;
+ -- sign extended
+ function TO_MEM_SDATA( n : integer) return std_logic_vector;
+ -- unsigned
+ function RESIZE_MEM_ADDRESS(vec : std_logic_vector) return std_logic_vector;
+ -- unsigned, alias of RESIZE_MEM_UDATA
+ function RESIZE_MEM_DATA( vec : std_logic_vector) return std_logic_vector;
+ -- unsigned
+ function RESIZE_MEM_UDATA( vec : std_logic_vector) return std_logic_vector;
+ -- sign extended
+ function RESIZE_MEM_SDATA( vec : std_logic_vector) return std_logic_vector;
+ -- set unused MSBits to 'X'
+ function RESIZE_MEM_XDATA( vec : std_logic_vector) return std_logic_vector;
------------------------------------------------------------------------------
-- Procedures to access MM bus
@@ -141,8 +161,10 @@ package common_mem_pkg is
type t_mem_ctlr_miso is record
rddata : std_logic_vector(c_mem_ctlr_data_w - 1 downto 0);
rdval : std_logic;
- waitrequest_n : std_logic; -- comparable to DP siso.ready
- done : std_logic; -- comparable to DP siso.xon, not part of Avalon bus, can eg. act as init done or init ok or ready for next block, useful for DDR controller
+ -- comparable to DP siso.ready
+ waitrequest_n : std_logic;
+ -- comparable to DP siso.xon, not part of Avalon bus, can eg. act as init done or init ok or ready for next block, useful for DDR controller
+ done : std_logic;
cal_ok : std_logic;
cal_fail : std_logic;
end record;
@@ -154,7 +176,8 @@ package common_mem_pkg is
rd : std_logic;
burstbegin : std_logic;
burstsize : std_logic_vector(c_mem_ctlr_burstsize_w - 1 downto 0);
- flush : std_logic; -- not part of Avalon bus, but useful for DDR driver
+ -- not part of Avalon bus, but useful for DDR driver
+ flush : std_logic;
end record;
constant c_mem_ctlr_miso_rst : t_mem_ctlr_miso := ((others => '0'), '0', '0', '0', '0', '0');
@@ -165,33 +188,45 @@ package common_mem_pkg is
type t_mem_ctlr_mosi_arr is array (integer range <>) of t_mem_ctlr_mosi;
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_ctlr_miso or t_mem_ctlr_mosi field width
- function TO_MEM_CTLR_ADDRESS( n : integer) return std_logic_vector; -- unsigned, use integer to support 32 bit range
- function TO_MEM_CTLR_DATA( n : integer) return std_logic_vector; -- unsigned
- function TO_MEM_CTLR_BURSTSIZE(n : integer) return std_logic_vector; -- unsigned
-
- function RESIZE_MEM_CTLR_ADDRESS( vec : std_logic_vector) return std_logic_vector; -- unsigned
- function RESIZE_MEM_CTLR_DATA( vec : std_logic_vector) return std_logic_vector; -- unsigned
- function RESIZE_MEM_CTLR_BURSTSIZE(vec : std_logic_vector) return std_logic_vector; -- unsigned
+ -- unsigned, use integer to support 32 bit range
+ function TO_MEM_CTLR_ADDRESS( n : integer) return std_logic_vector;
+ -- unsigned
+ function TO_MEM_CTLR_DATA( n : integer) return std_logic_vector;
+ -- unsigned
+ function TO_MEM_CTLR_BURSTSIZE(n : integer) return std_logic_vector;
+
+ -- unsigned
+ function RESIZE_MEM_CTLR_ADDRESS( vec : std_logic_vector) return std_logic_vector;
+ -- unsigned
+ function RESIZE_MEM_CTLR_DATA( vec : std_logic_vector) return std_logic_vector;
+ -- unsigned
+ function RESIZE_MEM_CTLR_BURSTSIZE(vec : std_logic_vector) return std_logic_vector;
------------------------------------------------------------------------------
-- RAM block memory and MM register defintions
------------------------------------------------------------------------------
type t_c_mem is record
- latency : natural; -- read latency
+ -- read latency
+ latency : natural;
adr_w : natural;
dat_w : natural;
- nof_dat : natural; -- optional, nof dat words <= 2**adr_w
- init_sl : std_logic; -- optional, init all dat words to std_logic '0', '1' or 'X'
+ -- optional, nof dat words <= 2**adr_w
+ nof_dat : natural;
+ -- optional, init all dat words to std_logic '0', '1' or 'X'
+ init_sl : std_logic;
--init_file : STRING; -- "UNUSED", unconstrained length can not be in record
end record;
- constant c_mem_ram_rd_latency : natural := 2; -- note common_ram_crw_crw(stratix4) now also supports read latency 1
- constant c_mem_ram : t_c_mem := (c_mem_ram_rd_latency, 10, 9, 2**10, 'X'); -- 1 M9K
+ -- note common_ram_crw_crw(stratix4) now also supports read latency 1
+ constant c_mem_ram_rd_latency : natural := 2;
+ -- 1 M9K
+ constant c_mem_ram : t_c_mem := (c_mem_ram_rd_latency, 10, 9, 2**10, 'X');
constant c_mem_reg_rd_latency : natural := 1;
constant c_mem_reg : t_c_mem := (c_mem_reg_rd_latency, 1, 32, 1, 'X');
- constant c_mem_reg_init_w : natural := 1 * 256 * 32; -- >= largest expected value of dat_w*nof_dat (256 * 32 bit = 1k byte)
+ -- >= largest expected value of dat_w*nof_dat (256 * 32 bit = 1k byte)
+ constant c_mem_reg_init_w : natural := 1 * 256 * 32;
------------------------------------------------------------------------------
-- Functions to swap endianess
diff --git a/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd b/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
index 904b55d3dfea5b58117775a3e898fc8e8f8bc44d..6e133b3c2c556e425c3eda3ffe4e0da218efc6bc 100644
--- a/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
@@ -57,32 +57,44 @@ package common_network_layers_pkg is
-- field widths in bits '_w' or in bytes '_len', '_min', '_max', '_sz'
constant c_network_eth_preamble_len : natural := 8;
- constant c_network_eth_word_align_len : natural := 2; -- to align 14 octets eth header at 32b word
+ -- to align 14 octets eth header at 32b word
+ constant c_network_eth_word_align_len : natural := 2;
constant c_network_eth_mac_addr_len : natural := 6;
constant c_network_eth_mac_addr_w : natural := c_network_eth_mac_addr_len * c_8;
constant c_network_eth_type_len : natural := 2;
constant c_network_eth_type_w : natural := c_network_eth_type_len * c_8;
- constant c_network_eth_header_len : natural := 2 * c_network_eth_mac_addr_len + c_network_eth_type_len; -- = 14
+ -- = 14
+ constant c_network_eth_header_len : natural := 2 * c_network_eth_mac_addr_len + c_network_eth_type_len;
constant c_network_eth_payload_min : natural := 46;
constant c_network_eth_payload_max : natural := 1500;
constant c_network_eth_payload_jumbo_max : natural := 9000;
constant c_network_eth_crc_len : natural := 4;
constant c_network_eth_crc_w : natural := c_network_eth_crc_len * c_8;
- constant c_network_eth_gap_len : natural := 12; -- IPG = interpacket gap, minimum idle period between transmission of Ethernet packets
- constant c_network_eth_frame_max : natural := c_network_eth_header_len + c_network_eth_payload_max + c_network_eth_crc_len; -- = 1518
- constant c_network_eth_frame_jumbo_max : natural := c_network_eth_header_len + c_network_eth_payload_jumbo_max + c_network_eth_crc_len; -- = 9018
+ -- IPG = interpacket gap, minimum idle period between transmission of Ethernet packets
+ constant c_network_eth_gap_len : natural := 12;
+ -- = 1518
+ constant c_network_eth_frame_max : natural := c_network_eth_header_len + c_network_eth_payload_max + c_network_eth_crc_len;
+ -- = 9018
+ constant c_network_eth_frame_jumbo_max : natural := c_network_eth_header_len + c_network_eth_payload_jumbo_max + c_network_eth_crc_len;
-- default field values
- constant c_network_eth_preamble : natural := 5; -- nibble "0101"
- constant c_network_eth_frame_delimiter : natural := 13; -- nibble "1101"
+ -- nibble "0101"
+ constant c_network_eth_preamble : natural := 5;
+ -- nibble "1101"
+ constant c_network_eth_frame_delimiter : natural := 13;
-- useful field values
- constant c_network_eth_mac_slv : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := (others => 'X'); -- Ethernet MAC slv RANGE
- constant c_network_eth_bc_mac : std_logic_vector(c_network_eth_mac_slv'range) := (others => '1'); -- Broadcast destination MAC
-
- constant c_network_eth_type_slv : std_logic_vector(c_network_eth_type_w - 1 downto 0) := (others => 'X'); -- Ethernet TYPE slv RANGE
- constant c_network_eth_type_arp : natural := 16#0806#; -- ARP = Address Resolution Prorotol
- constant c_network_eth_type_ip : natural := 16#0800#; -- IPv4 = Internet Protocol, Version 4
+ -- Ethernet MAC slv RANGE
+ constant c_network_eth_mac_slv : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := (others => 'X');
+ -- Broadcast destination MAC
+ constant c_network_eth_bc_mac : std_logic_vector(c_network_eth_mac_slv'range) := (others => '1');
+
+ -- Ethernet TYPE slv RANGE
+ constant c_network_eth_type_slv : std_logic_vector(c_network_eth_type_w - 1 downto 0) := (others => 'X');
+ -- ARP = Address Resolution Prorotol
+ constant c_network_eth_type_arp : natural := 16#0806#;
+ -- IPv4 = Internet Protocol, Version 4
+ constant c_network_eth_type_ip : natural := 16#0800#;
type t_network_eth_header is record
dst_mac : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
@@ -116,8 +128,10 @@ package common_network_layers_pkg is
--
-- field widths in bits '_w' or in bytes '_len'
- constant c_network_ip_version_w : natural := 4; -- 4-bit field
- constant c_network_ip_header_length_w : natural := 4; -- 4-bit field
+ -- 4-bit field
+ constant c_network_ip_version_w : natural := 4;
+ -- 4-bit field
+ constant c_network_ip_header_length_w : natural := 4;
constant c_network_ip_version_header_len : natural := 1;
constant c_network_ip_version_header_w : natural := c_network_ip_version_header_len * c_8;
constant c_network_ip_services_len : natural := 1;
@@ -126,8 +140,10 @@ package common_network_layers_pkg is
constant c_network_ip_total_length_w : natural := c_network_ip_total_length_len * c_8;
constant c_network_ip_identification_len : natural := 2;
constant c_network_ip_identification_w : natural := c_network_ip_identification_len * c_8;
- constant c_network_ip_flags_w : natural := 3; -- 3-bit field
- constant c_network_ip_fragment_offset_w : natural := 13; -- 13-bit field
+ -- 3-bit field
+ constant c_network_ip_flags_w : natural := 3;
+ -- 13-bit field
+ constant c_network_ip_fragment_offset_w : natural := 13;
constant c_network_ip_flags_fragment_len : natural := 2;
constant c_network_ip_flags_fragment_w : natural := c_network_ip_flags_fragment_len * c_8;
constant c_network_ip_time_to_live_len : natural := 1;
@@ -147,36 +163,61 @@ package common_network_layers_pkg is
c_network_ip_addr_len;
-- = c_network_ip_header_length * c_word_sz = 20
-- default field values
- constant c_network_ip_version : natural := 4; -- 4 = IPv4,
- constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
- constant c_network_ip_services : natural := 0; -- 0 = default, use default on transmit, ignore on receive, copy on reply
- constant c_network_ip_total_length : natural := 20; -- >= 20, nof bytes in entire datagram including header and data
- constant c_network_ip_identification : natural := 0; -- identification number, copy on reply
- constant c_network_ip_flags : natural := 2; -- 2 = don't fragment and this is the last fragment
- constant c_network_ip_fragment_offset : natural := 0; -- 0 = first fragment
- constant c_network_ip_time_to_live : natural := 127; -- number of hops until the packet will be discarded
- constant c_network_ip_header_checksum : natural := 0; -- init value
+ -- 4 = IPv4,
+ constant c_network_ip_version : natural := 4;
+ -- 5 = nof words in the header, no options field support
+ constant c_network_ip_header_length : natural := 5;
+ -- 0 = default, use default on transmit, ignore on receive, copy on reply
+ constant c_network_ip_services : natural := 0;
+ -- >= 20, nof bytes in entire datagram including header and data
+ constant c_network_ip_total_length : natural := 20;
+ -- identification number, copy on reply
+ constant c_network_ip_identification : natural := 0;
+ -- 2 = don't fragment and this is the last fragment
+ constant c_network_ip_flags : natural := 2;
+ -- 0 = first fragment
+ constant c_network_ip_fragment_offset : natural := 0;
+ -- number of hops until the packet will be discarded
+ constant c_network_ip_time_to_live : natural := 127;
+ -- init value
+ constant c_network_ip_header_checksum : natural := 0;
-- useful field values
- constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X'); -- IP protocol slv RANGE
- constant c_network_ip_protocol_udp : natural := 17; -- UDP = User Datagram Protocol (for board control and streaming data)
- constant c_network_ip_protocol_icmp : natural := 1; -- ICMP = Internet Control Message Protocol (for ping)
+ -- IP protocol slv RANGE
+ constant c_network_ip_protocol_slv : std_logic_vector(c_network_ip_protocol_w - 1 downto 0) := (others => 'X');
+ -- UDP = User Datagram Protocol (for board control and streaming data)
+ constant c_network_ip_protocol_udp : natural := 17;
+ -- ICMP = Internet Control Message Protocol (for ping)
+ constant c_network_ip_protocol_icmp : natural := 1;
- constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X'); -- IP address slv RANGE
+ -- IP address slv RANGE
+ constant c_network_ip_addr_slv : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := (others => 'X');
type t_network_ip_header is record
- version : std_logic_vector(c_network_ip_version_w - 1 downto 0); -- 4 bit
- header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0); -- 4 bit
- services : std_logic_vector(c_network_ip_services_w - 1 downto 0); -- 1 octet
- total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0); -- 2 octet
- identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0); -- 2 octet
- flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0); -- 3 bit
- fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0); -- 13 bit
- time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0); -- 1 octet
- protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0); -- 1 octet
- header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0); -- 2 octet
- src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
- dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
+ -- 4 bit
+ version : std_logic_vector(c_network_ip_version_w - 1 downto 0);
+ -- 4 bit
+ header_length : std_logic_vector(c_network_ip_header_length_w - 1 downto 0);
+ -- 1 octet
+ services : std_logic_vector(c_network_ip_services_w - 1 downto 0);
+ -- 2 octet
+ total_length : std_logic_vector(c_network_ip_total_length_w - 1 downto 0);
+ -- 2 octet
+ identification : std_logic_vector(c_network_ip_identification_w - 1 downto 0);
+ -- 3 bit
+ flags : std_logic_vector(c_network_ip_flags_w - 1 downto 0);
+ -- 13 bit
+ fragment_offset : std_logic_vector(c_network_ip_fragment_offset_w - 1 downto 0);
+ -- 1 octet
+ time_to_live : std_logic_vector(c_network_ip_time_to_live_w - 1 downto 0);
+ -- 1 octet
+ protocol : std_logic_vector(c_network_ip_protocol_w - 1 downto 0);
+ -- 2 octet
+ header_checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0);
+ -- 4 octet
+ src_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- 4 octet
+ dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
end record;
constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
@@ -228,27 +269,44 @@ package common_network_layers_pkg is
-- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
- constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
- constant c_network_arp_ptype : natural := c_network_eth_type_ip; -- Protocol type, do ARP for IPv4
- constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len; -- Hardware length = 6
- constant c_network_arp_plen : natural := c_network_ip_addr_len; -- Protocol length = 4
- constant c_network_arp_oper_request : natural := 1; -- Operator, 1=request
- constant c_network_arp_oper_reply : natural := 2; -- Operator, 2=reply
+ -- Hardware type, 1=ethernet
+ constant c_network_arp_htype : natural := 1;
+ -- Protocol type, do ARP for IPv4
+ constant c_network_arp_ptype : natural := c_network_eth_type_ip;
+ -- Hardware length = 6
+ constant c_network_arp_hlen : natural := c_network_eth_mac_addr_len;
+ -- Protocol length = 4
+ constant c_network_arp_plen : natural := c_network_ip_addr_len;
+ -- Operator, 1=request
+ constant c_network_arp_oper_request : natural := 1;
+ -- Operator, 2=reply
+ constant c_network_arp_oper_reply : natural := 2;
-- useful field values
- constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast destination MAC
- constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac; -- Broadcast target hardware address
+ -- Broadcast destination MAC
+ constant c_network_arp_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac;
+ -- Broadcast target hardware address
+ constant c_network_arp_tha : std_logic_vector(c_network_eth_mac_slv'range) := c_network_eth_bc_mac;
type t_network_arp_packet is record
- htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0); -- 2 octet
- ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0); -- 2 octet
- hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0); -- 1 octet
- plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0); -- 1 octet
- oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0); -- 2 octet
- sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Sender Hardware Address
- spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Sender Protocol Address
- tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- 6 octet, Target Hardware Address
- tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
+ -- 2 octet
+ htype : std_logic_vector(c_network_arp_htype_w - 1 downto 0);
+ -- 2 octet
+ ptype : std_logic_vector(c_network_arp_ptype_w - 1 downto 0);
+ -- 1 octet
+ hlen : std_logic_vector(c_network_arp_hlen_w - 1 downto 0);
+ -- 1 octet
+ plen : std_logic_vector(c_network_arp_plen_w - 1 downto 0);
+ -- 2 octet
+ oper : std_logic_vector(c_network_arp_oper_w - 1 downto 0);
+ -- 6 octet, Sender Hardware Address
+ sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ -- 4 octet, Sender Protocol Address
+ spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- 6 octet, Target Hardware Address
+ tha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ -- 4 octet, Target Protocol Address
+ tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
end record;
constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
@@ -288,21 +346,32 @@ package common_network_layers_pkg is
c_network_icmp_id_len + c_network_icmp_sequence_len;
-- default field values
- constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
- constant c_network_icmp_msg_type_reply : natural := 0; -- 8 = echo reply (ping)
- constant c_network_icmp_checksum : natural := 0; -- init value
+ -- 8 = echo request
+ constant c_network_icmp_msg_type_request : natural := 8;
+ -- 8 = echo reply (ping)
+ constant c_network_icmp_msg_type_reply : natural := 0;
+ -- init value
+ constant c_network_icmp_checksum : natural := 0;
-- useful field values
- constant c_network_icmp_code : natural := 0; -- default
- constant c_network_icmp_id : natural := 3; -- arbitrary value
- constant c_network_icmp_sequence : natural := 4; -- arbitrary value
+ -- default
+ constant c_network_icmp_code : natural := 0;
+ -- arbitrary value
+ constant c_network_icmp_id : natural := 3;
+ -- arbitrary value
+ constant c_network_icmp_sequence : natural := 4;
type t_network_icmp_header is record
- msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0); -- 1 octet
- code : std_logic_vector(c_network_icmp_code_w - 1 downto 0); -- 1 octet
- checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0); -- 2 octet
- id : std_logic_vector(c_network_icmp_id_w - 1 downto 0); -- 2 octet
- sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
+ -- 1 octet
+ msg_type : std_logic_vector(c_network_icmp_msg_type_w - 1 downto 0);
+ -- 1 octet
+ code : std_logic_vector(c_network_icmp_code_w - 1 downto 0);
+ -- 2 octet
+ checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0);
+ -- 2 octet
+ id : std_logic_vector(c_network_icmp_id_w - 1 downto 0);
+ -- 2 octet
+ sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0);
end record;
constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
@@ -333,23 +402,33 @@ package common_network_layers_pkg is
-- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+ -- 8
+ c_network_udp_total_length_len + c_network_udp_checksum_len;
-- default field values
- constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
- constant c_network_udp_checksum : natural := 0; -- init value
+ -- >= 8, nof bytes in entire datagram including header and data
+ constant c_network_udp_total_length : natural := 8;
+ -- init value
+ constant c_network_udp_checksum : natural := 0;
-- useful field values -- Note that ARP header = ARP packet, because ARP has no payload
- constant c_network_udp_port_dhcp_in : natural := 68; -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
- constant c_network_udp_port_dhcp_out : natural := 67; -- DHCP to server
- constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X'); -- UDP port slv RANGE
+ -- DHCP to client = Dynamic Host Configuration Protocol (for IP address assignment)
+ constant c_network_udp_port_dhcp_in : natural := 68;
+ -- DHCP to server
+ constant c_network_udp_port_dhcp_out : natural := 67;
+ -- UDP port slv RANGE
+ constant c_network_udp_port_slv : std_logic_vector(c_network_udp_port_w - 1 downto 0) := (others => 'X');
type t_network_udp_header is record
- src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- 2 octet
- total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0); -- 2 octet
- checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
+ -- 2 octet
+ src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- 2 octet
+ dst_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- 2 octet
+ total_length : std_logic_vector(c_network_udp_total_length_w - 1 downto 0);
+ -- 2 octet
+ checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0);
end record;
constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
@@ -362,8 +441,10 @@ end common_network_layers_pkg;
package body common_network_layers_pkg is
function func_network_ip_header_checksum(field_arr : t_common_field_arr; hdr_fields_slv : std_logic_vector) return std_logic_vector is
-- function to calculate the ip header checksum based on a header field array.
- constant c_cin_w : natural := 4; -- bit width of carry
- constant c_nof_halfword : natural := (c_network_ip_header_len / c_halfword_sz) - 1; -- -1 as we exclude the checksum field itself for calculation.
+ -- bit width of carry
+ constant c_cin_w : natural := 4;
+ -- -1 as we exclude the checksum field itself for calculation.
+ constant c_nof_halfword : natural := (c_network_ip_header_len / c_halfword_sz) - 1;
variable sum : unsigned(c_network_ip_header_checksum_w + c_cin_w - 1 downto 0) := (others => '0');
variable crc : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0);
diff --git a/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd b/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
index 32587a2affb491938595856dac431fd419cf9822..03459c46caeab6c55dd784acb3c10b43d3beb2d3 100644
--- a/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
@@ -57,9 +57,12 @@ use work.common_network_layers_pkg.all;
package common_network_total_header_pkg is
-- Define total network header that fits all relevant packets in common_network_layers_pkg, because they have the same total header length
- constant c_network_total_header_arp_len : natural := c_network_eth_header_len + c_network_arp_data_len; -- = 14 + 28 = 42
- constant c_network_total_header_icmp_len : natural := c_network_eth_header_len + c_network_ip_header_len + c_network_icmp_header_len; -- = 14 + 20 + 8 = 42
- constant c_network_total_header_udp_len : natural := c_network_eth_header_len + c_network_ip_header_len + c_network_udp_header_len; -- = 14 + 20 + 8 = 42
+ -- = 14 + 28 = 42
+ constant c_network_total_header_arp_len : natural := c_network_eth_header_len + c_network_arp_data_len;
+ -- = 14 + 20 + 8 = 42
+ constant c_network_total_header_icmp_len : natural := c_network_eth_header_len + c_network_ip_header_len + c_network_icmp_header_len;
+ -- = 14 + 20 + 8 = 42
+ constant c_network_total_header_udp_len : natural := c_network_eth_header_len + c_network_ip_header_len + c_network_udp_header_len;
constant c_network_total_header_len : natural := 42;
@@ -85,28 +88,36 @@ package common_network_total_header_pkg is
-- Map total network header in words array
-----------------------------------------------------------------------------
- constant c_network_total_header_32b_align_len : natural := 2; -- to align eth, ip and udp payload to 32 bit boundaries
+ -- to align eth, ip and udp payload to 32 bit boundaries
+ constant c_network_total_header_32b_align_len : natural := 2;
constant c_network_total_header_32b_align_w : natural := c_network_total_header_32b_align_len * c_8;
- constant c_network_total_header_64b_align_len : natural := 6; -- to align eth, ip and udp payload to 32 bit boundaries and
- constant c_network_total_header_64b_align_w : natural := c_network_total_header_64b_align_len * c_8; -- udp payload to 64 bit boundaries
+ -- to align eth, ip and udp payload to 32 bit boundaries and
+ constant c_network_total_header_64b_align_len : natural := 6;
+ -- udp payload to 64 bit boundaries
+ constant c_network_total_header_64b_align_w : natural := c_network_total_header_64b_align_len * c_8;
- constant c_network_total_header_32b_nof_words : natural := (c_network_total_header_32b_align_len + c_network_total_header_len) / 4; -- = 44 / c_word_sz = 11
- constant c_network_total_header_64b_nof_words : natural := (c_network_total_header_64b_align_len + c_network_total_header_len) / 8; -- = 48 / c_longword_sz = 6
+ -- = 44 / c_word_sz = 11
+ constant c_network_total_header_32b_nof_words : natural := (c_network_total_header_32b_align_len + c_network_total_header_len) / 4;
+ -- = 48 / c_longword_sz = 6
+ constant c_network_total_header_64b_nof_words : natural := (c_network_total_header_64b_align_len + c_network_total_header_len) / 8;
type t_network_total_header_32b_arr is array(0 to c_network_total_header_32b_nof_words - 1) of std_logic_vector(c_32 - 1 downto 0);
type t_network_total_header_64b_arr is array(0 to c_network_total_header_64b_nof_words - 1) of std_logic_vector(c_64 - 1 downto 0);
-- Word indices in the total header array to know when the field in the mapped record is valid
-- . 32b
- constant c_network_total_header_32b_eth_lo_wi : natural := 0; -- first word index
+ -- first word index
+ constant c_network_total_header_32b_eth_lo_wi : natural := 0;
constant c_network_total_header_32b_eth_dst_mac_wi : natural := 1;
constant c_network_total_header_32b_eth_src_mac_wi : natural := 3;
constant c_network_total_header_32b_eth_type_wi : natural := 3;
- constant c_network_total_header_32b_eth_hi_wi : natural := 3; -- last word index
+ -- last word index
+ constant c_network_total_header_32b_eth_hi_wi : natural := 3;
constant c_network_total_header_32b_eth_nof_words : natural := c_network_total_header_32b_eth_hi_wi - c_network_total_header_32b_eth_lo_wi + 1;
- constant c_network_total_header_32b_ip_lo_wi : natural := 4; -- first word index
+ -- first word index
+ constant c_network_total_header_32b_ip_lo_wi : natural := 4;
constant c_network_total_header_32b_ip_version_wi : natural := 4;
constant c_network_total_header_32b_ip_header_length_wi : natural := 4;
constant c_network_total_header_32b_ip_services_wi : natural := 4;
@@ -119,10 +130,12 @@ package common_network_total_header_pkg is
constant c_network_total_header_32b_ip_header_checksum_wi : natural := 6;
constant c_network_total_header_32b_ip_src_ip_addr_wi : natural := 7;
constant c_network_total_header_32b_ip_dst_ip_addr_wi : natural := 8;
- constant c_network_total_header_32b_ip_hi_wi : natural := 8; -- last word index
+ -- last word index
+ constant c_network_total_header_32b_ip_hi_wi : natural := 8;
constant c_network_total_header_32b_ip_nof_words : natural := c_network_total_header_32b_ip_hi_wi - c_network_total_header_32b_ip_lo_wi + 1;
- constant c_network_total_header_32b_arp_lo_wi : natural := 4; -- first word index
+ -- first word index
+ constant c_network_total_header_32b_arp_lo_wi : natural := 4;
constant c_network_total_header_32b_arp_htype_wi : natural := 4;
constant c_network_total_header_32b_arp_ptype_wi : natural := 4;
constant c_network_total_header_32b_arp_hlen_wi : natural := 5;
@@ -132,35 +145,43 @@ package common_network_total_header_pkg is
constant c_network_total_header_32b_arp_spa_wi : natural := 8;
constant c_network_total_header_32b_arp_tha_wi : natural := 9;
constant c_network_total_header_32b_arp_tpa_wi : natural := 10;
- constant c_network_total_header_32b_arp_hi_wi : natural := 10; -- last word index
+ -- last word index
+ constant c_network_total_header_32b_arp_hi_wi : natural := 10;
constant c_network_total_header_32b_arp_nof_words : natural := c_network_total_header_32b_arp_hi_wi - c_network_total_header_32b_arp_lo_wi + 1;
- constant c_network_total_header_32b_icmp_lo_wi : natural := 9; -- first word index
+ -- first word index
+ constant c_network_total_header_32b_icmp_lo_wi : natural := 9;
constant c_network_total_header_32b_icmp_msg_type_wi : natural := 9;
constant c_network_total_header_32b_icmp_code_wi : natural := 9;
constant c_network_total_header_32b_icmp_checksum_wi : natural := 9;
constant c_network_total_header_32b_icmp_id_wi : natural := 10;
constant c_network_total_header_32b_icmp_sequence_wi : natural := 10;
- constant c_network_total_header_32b_icmp_hi_wi : natural := 10; -- last word index
+ -- last word index
+ constant c_network_total_header_32b_icmp_hi_wi : natural := 10;
constant c_network_total_header_32b_icmp_nof_words : natural := c_network_total_header_32b_icmp_hi_wi - c_network_total_header_32b_icmp_lo_wi + 1;
- constant c_network_total_header_32b_udp_lo_wi : natural := 9; -- first word index
+ -- first word index
+ constant c_network_total_header_32b_udp_lo_wi : natural := 9;
constant c_network_total_header_32b_udp_src_port_wi : natural := 9;
constant c_network_total_header_32b_udp_dst_port_wi : natural := 9;
constant c_network_total_header_32b_udp_total_length_wi : natural := 10;
constant c_network_total_header_32b_udp_checksum_wi : natural := 10;
- constant c_network_total_header_32b_udp_hi_wi : natural := 10; -- last word index
+ -- last word index
+ constant c_network_total_header_32b_udp_hi_wi : natural := 10;
constant c_network_total_header_32b_udp_nof_words : natural := c_network_total_header_32b_udp_hi_wi - c_network_total_header_32b_udp_lo_wi + 1;
-- . 64b
- constant c_network_total_header_64b_eth_lo_wi : natural := 0; -- first word index
+ -- first word index
+ constant c_network_total_header_64b_eth_lo_wi : natural := 0;
constant c_network_total_header_64b_eth_dst_mac_wi : natural := 1;
constant c_network_total_header_64b_eth_src_mac_wi : natural := 2;
constant c_network_total_header_64b_eth_type_wi : natural := 2;
- constant c_network_total_header_64b_eth_hi_wi : natural := 2; -- last word index
+ -- last word index
+ constant c_network_total_header_64b_eth_hi_wi : natural := 2;
constant c_network_total_header_64b_eth_nof_words : natural := c_network_total_header_64b_eth_hi_wi - c_network_total_header_64b_eth_lo_wi + 1;
- constant c_network_total_header_64b_ip_lo_wi : natural := 2; -- first word index
+ -- first word index
+ constant c_network_total_header_64b_ip_lo_wi : natural := 2;
constant c_network_total_header_64b_ip_version_wi : natural := 2;
constant c_network_total_header_64b_ip_header_length_wi : natural := 2;
constant c_network_total_header_64b_ip_services_wi : natural := 2;
@@ -173,10 +194,12 @@ package common_network_total_header_pkg is
constant c_network_total_header_64b_ip_header_checksum_wi : natural := 3;
constant c_network_total_header_64b_ip_src_ip_addr_wi : natural := 4;
constant c_network_total_header_64b_ip_dst_ip_addr_wi : natural := 4;
- constant c_network_total_header_64b_ip_hi_wi : natural := 4; -- last word index
+ -- last word index
+ constant c_network_total_header_64b_ip_hi_wi : natural := 4;
constant c_network_total_header_64b_ip_nof_words : natural := c_network_total_header_64b_ip_hi_wi - c_network_total_header_64b_ip_lo_wi + 1;
- constant c_network_total_header_64b_arp_lo_wi : natural := 2; -- first word index
+ -- first word index
+ constant c_network_total_header_64b_arp_lo_wi : natural := 2;
constant c_network_total_header_64b_arp_htype_wi : natural := 2;
constant c_network_total_header_64b_arp_ptype_wi : natural := 2;
constant c_network_total_header_64b_arp_hlen_wi : natural := 3;
@@ -186,24 +209,29 @@ package common_network_total_header_pkg is
constant c_network_total_header_64b_arp_spa_wi : natural := 4;
constant c_network_total_header_64b_arp_tha_wi : natural := 5;
constant c_network_total_header_64b_arp_tpa_wi : natural := 5;
- constant c_network_total_header_64b_arp_hi_wi : natural := 5; -- last word index
+ -- last word index
+ constant c_network_total_header_64b_arp_hi_wi : natural := 5;
constant c_network_total_header_64b_arp_nof_words : natural := c_network_total_header_64b_arp_hi_wi - c_network_total_header_64b_arp_lo_wi + 1;
- constant c_network_total_header_64b_icmp_lo_wi : natural := 5; -- first word index
+ -- first word index
+ constant c_network_total_header_64b_icmp_lo_wi : natural := 5;
constant c_network_total_header_64b_icmp_msg_type_wi : natural := 5;
constant c_network_total_header_64b_icmp_code_wi : natural := 5;
constant c_network_total_header_64b_icmp_checksum_wi : natural := 5;
constant c_network_total_header_64b_icmp_id_wi : natural := 5;
constant c_network_total_header_64b_icmp_sequence_wi : natural := 5;
- constant c_network_total_header_64b_icmp_hi_wi : natural := 5; -- last word index
+ -- last word index
+ constant c_network_total_header_64b_icmp_hi_wi : natural := 5;
constant c_network_total_header_64b_icmp_nof_words : natural := c_network_total_header_64b_icmp_hi_wi - c_network_total_header_64b_icmp_lo_wi + 1;
- constant c_network_total_header_64b_udp_lo_wi : natural := 5; -- first word index
+ -- first word index
+ constant c_network_total_header_64b_udp_lo_wi : natural := 5;
constant c_network_total_header_64b_udp_src_port_wi : natural := 5;
constant c_network_total_header_64b_udp_dst_port_wi : natural := 5;
constant c_network_total_header_64b_udp_total_length_wi : natural := 5;
constant c_network_total_header_64b_udp_checksum_wi : natural := 5;
- constant c_network_total_header_64b_udp_hi_wi : natural := 5; -- last word index
+ -- last word index
+ constant c_network_total_header_64b_udp_hi_wi : natural := 5;
constant c_network_total_header_64b_udp_nof_words : natural := c_network_total_header_64b_udp_hi_wi - c_network_total_header_64b_udp_lo_wi + 1;
-----------------------------------------------------------------------------
@@ -235,12 +263,16 @@ package common_network_total_header_pkg is
function func_network_total_header_no_align_extract_udp( hdr_arr : t_network_total_header_64b_arr) return t_network_udp_header;
-- Construct the total header array from the individual header records
- function func_network_total_header_construct_eth( eth : t_network_eth_header) return t_network_total_header_32b_arr; -- sets unused words to zero
- function func_network_total_header_construct_eth( eth : t_network_eth_header) return t_network_total_header_64b_arr; -- sets unused words to zero
+ -- sets unused words to zero
+ function func_network_total_header_construct_eth( eth : t_network_eth_header) return t_network_total_header_32b_arr;
+ -- sets unused words to zero
+ function func_network_total_header_construct_eth( eth : t_network_eth_header) return t_network_total_header_64b_arr;
function func_network_total_header_construct_arp( eth : t_network_eth_header; arp : t_network_arp_packet) return t_network_total_header_32b_arr;
function func_network_total_header_construct_arp( eth : t_network_eth_header; arp : t_network_arp_packet) return t_network_total_header_64b_arr;
- function func_network_total_header_construct_ip( eth : t_network_eth_header; ip : t_network_ip_header) return t_network_total_header_32b_arr; -- sets unused words to zero
- function func_network_total_header_construct_ip( eth : t_network_eth_header; ip : t_network_ip_header) return t_network_total_header_64b_arr; -- sets unused words to zero
+ -- sets unused words to zero
+ function func_network_total_header_construct_ip( eth : t_network_eth_header; ip : t_network_ip_header) return t_network_total_header_32b_arr;
+ -- sets unused words to zero
+ function func_network_total_header_construct_ip( eth : t_network_eth_header; ip : t_network_ip_header) return t_network_total_header_64b_arr;
function func_network_total_header_construct_icmp(eth : t_network_eth_header; ip : t_network_ip_header; icmp : t_network_icmp_header) return t_network_total_header_32b_arr;
function func_network_total_header_construct_icmp(eth : t_network_eth_header; ip : t_network_ip_header; icmp : t_network_icmp_header) return t_network_total_header_64b_arr;
function func_network_total_header_construct_udp( eth : t_network_eth_header; ip : t_network_ip_header; udp : t_network_udp_header) return t_network_total_header_32b_arr;
@@ -566,7 +598,8 @@ package body common_network_total_header_pkg is
function func_network_total_header_construct_eth( eth : t_network_eth_header) return t_network_total_header_32b_arr is
variable v_total : t_network_total_header_32b_arr := (others => (others => '0'));
begin
- v_total(0)(31 downto 16) := (others => '0'); -- force word align to zero
+ -- force word align to zero
+ v_total(0)(31 downto 16) := (others => '0');
v_total(0)(15 downto 0) := eth.dst_mac(47 downto 32);
v_total(1) := eth.dst_mac(31 downto 0);
v_total(2) := eth.src_mac(47 downto 16);
@@ -578,7 +611,8 @@ package body common_network_total_header_pkg is
function func_network_total_header_construct_eth( eth : t_network_eth_header) return t_network_total_header_64b_arr is
variable v_total : t_network_total_header_64b_arr := (others => (others => '0'));
begin
- v_total(0)(63 downto 16) := (others => '0'); -- force word align to zero
+ -- force word align to zero
+ v_total(0)(63 downto 16) := (others => '0');
v_total(0)(15 downto 0) := eth.dst_mac(47 downto 32);
v_total(1)(63 downto 32) := eth.dst_mac(31 downto 0);
v_total(1)(31 downto 0) := eth.src_mac(47 downto 16);
diff --git a/libraries/base/common/src/vhdl/common_operation.vhd b/libraries/base/common/src/vhdl/common_operation.vhd
index d807bdcd3ff29a5a83b4e57ebeeb343a42b91753..303c0de6a92663298c405c1972b9e36f77aa5e70 100644
--- a/libraries/base/common/src/vhdl/common_operation.vhd
+++ b/libraries/base/common/src/vhdl/common_operation.vhd
@@ -26,10 +26,14 @@ use work.common_pkg.all;
entity common_operation is
generic (
- g_operation : string := "MAX"; -- supported operations "MAX", "MIN"
- g_representation : string := "SIGNED"; -- or "UNSIGNED"
- g_pipeline_input : natural := 0; -- 0 or 1
- g_pipeline_output : natural := 1; -- >= 0
+ -- supported operations "MAX", "MIN"
+ g_operation : string := "MAX";
+ -- or "UNSIGNED"
+ g_representation : string := "SIGNED";
+ -- 0 or 1
+ g_pipeline_input : natural := 0;
+ -- >= 0
+ g_pipeline_output : natural := 1;
g_dat_w : natural := 8
);
port (
@@ -59,7 +63,8 @@ architecture rtl of common_operation is
if operation = "MAX" then return c_umin; end if;
end if;
assert true report "Operation not supported" severity FAILURE;
- return c_umin; -- void return statement to avoid compiler warning on missing return
+ -- void return statement to avoid compiler warning on missing return
+ return c_umin;
end;
function func_operation(operation, representation : string; a, b : std_logic_vector) return std_logic_vector is
@@ -72,7 +77,8 @@ architecture rtl of common_operation is
if operation = "MAX" then if unsigned(a) > unsigned(b) then return a; else return b; end if; end if;
end if;
assert true report "Operation not supported" severity FAILURE;
- return a; -- void return statement to avoid compiler warning on missing return
+ -- void return statement to avoid compiler warning on missing return
+ return a;
end;
signal nxt_a : std_logic_vector(g_dat_w - 1 downto 0);
@@ -84,11 +90,13 @@ begin
nxt_a <= in_a when in_en_a = '1' else func_default(g_operation, g_representation, g_dat_w);
nxt_b <= in_b when in_en_b = '1' else func_default(g_operation, g_representation, g_dat_w);
- no_input_reg : if g_pipeline_input = 0 generate -- wired input
+ -- wired input
+ no_input_reg : if g_pipeline_input = 0 generate
a <= nxt_a;
b <= nxt_b;
end generate;
- gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ -- register input
+ gen_input_reg : if g_pipeline_input > 0 generate
p_reg : process(clk)
begin
if rising_edge(clk) then
@@ -102,10 +110,12 @@ begin
nxt_result <= func_operation(g_operation, g_representation, a, b);
- u_output_pipe : entity work.common_pipeline -- pipeline output
+ -- pipeline output
+ u_output_pipe : entity work.common_pipeline
generic map (
g_representation => g_representation,
- g_pipeline => g_pipeline_output, -- 0 for wires, >0 for register stages
+ -- 0 for wires, >0 for register stages
+ g_pipeline => g_pipeline_output,
g_in_dat_w => g_dat_w,
g_out_dat_w => g_dat_w
)
diff --git a/libraries/base/common/src/vhdl/common_operation_tree.vhd b/libraries/base/common/src/vhdl/common_operation_tree.vhd
index 0ad7a72e6a505ae3d16858522dab7aae34254de7..596bb36f75ea99ad6a414ef060af3af6b27579a7 100644
--- a/libraries/base/common/src/vhdl/common_operation_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_operation_tree.vhd
@@ -42,11 +42,15 @@ use work.common_pkg.all;
entity common_operation_tree is
generic (
- g_operation : string := "MAX"; -- supported operations "MAX", "MIN"
+ -- supported operations "MAX", "MIN"
+ g_operation : string := "MAX";
g_representation : string := "SIGNED";
- g_pipeline : natural := 0; -- amount of output pipelining per stage
- g_pipeline_mod : positive := 1; -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
- g_nof_inputs : natural := 4; -- >= 1, nof stages = ceil_log2(g_nof_inputs)
+ -- amount of output pipelining per stage
+ g_pipeline : natural := 0;
+ -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
+ g_pipeline_mod : positive := 1;
+ -- >= 1, nof stages = ceil_log2(g_nof_inputs)
+ g_nof_inputs : natural := 4;
g_dat_w : natural := 8
);
port (
@@ -63,10 +67,13 @@ architecture str of common_operation_tree is
constant c_pipeline_in : natural := 0;
constant c_pipeline_out : natural := g_pipeline;
- constant c_w : natural := g_dat_w; -- input data width
+ -- input data width
+ constant c_w : natural := g_dat_w;
- constant c_N : natural := g_nof_inputs; -- nof inputs to the adder tree
- constant c_nof_stages : natural := ceil_log2(c_N); -- nof stages in the adder tree
+ -- nof inputs to the adder tree
+ constant c_N : natural := g_nof_inputs;
+ -- nof stages in the adder tree
+ constant c_nof_stages : natural := ceil_log2(c_N);
type t_stage_arr is array (integer range <>) of std_logic_vector(c_N * g_dat_w - 1 downto 0);
type t_stage_en_arr is array (integer range <>) of std_logic_vector(c_N - 1 downto 0);
@@ -77,7 +84,8 @@ begin
gen_tree : if g_nof_inputs > 1 generate
-- Input wires
stage_arr(-1) <= in_data_vec;
- stage_en_arr(-1) <= in_en_vec; -- the first stage enables depend on in_en_vec, the other stages are determined in the stages
+ -- the first stage enables depend on in_en_vec, the other stages are determined in the stages
+ stage_en_arr(-1) <= in_en_vec;
-- Adder tree
gen_stage : for j in 0 to c_nof_stages - 1 generate
@@ -129,7 +137,8 @@ begin
end generate;
result <= stage_arr(c_nof_stages - 1)(c_w - 1 downto 0);
- end generate; -- gen_tree
+ -- gen_tree
+ end generate;
no_tree : if g_nof_inputs = 1 generate
u_reg : entity work.common_pipeline
@@ -145,6 +154,7 @@ begin
in_dat => in_data_vec,
out_dat => result
);
- end generate; -- no_tree
+ -- no_tree
+ end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
index 4bc889b7fe958710a094a72551dec6fe230a54ea..b060919e32bf28fe2747a1e3c165c5c439e1fdfa 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
@@ -47,7 +47,8 @@ entity common_paged_ram_crw_crw is
g_technology : natural := c_tech_select_default;
g_str : string := "use_adr";
g_data_w : natural;
- g_nof_pages : natural := 2; -- >= 2
+ -- >= 2
+ g_nof_pages : natural := 2;
g_page_sz : natural;
g_start_page_a : natural := 0;
g_start_page_b : natural := 0;
@@ -95,7 +96,8 @@ architecture rtl of common_paged_ram_crw_crw is
-- g_str = "use_adr" :
constant c_mem_nof_pages_w : natural := true_log2(g_nof_pages);
constant c_mem_addr_w : natural := c_mem_nof_pages_w + c_page_addr_w;
- constant c_mem_nof_words : natural := g_nof_pages * 2**c_page_addr_w; -- <= 2**c_mem_addr_w
+ -- <= 2**c_mem_addr_w
+ constant c_mem_nof_words : natural := g_nof_pages * 2**c_page_addr_w;
constant c_mem_ram : t_c_mem := (latency => g_rd_latency,
adr_w => c_mem_addr_w,
@@ -269,7 +271,8 @@ begin
rd_val_a <= page_rd_val_a(page_sel_a_dly(g_rd_latency - 1));
rd_val_b <= page_rd_val_b(page_sel_b_dly(g_rd_latency - 1));
end process;
- end generate; -- gen_mux
+ -- gen_mux
+ end generate;
gen_adr : if g_str = "use_adr" generate
u_mem : entity work.common_ram_crw_crw
@@ -302,7 +305,8 @@ begin
mem_adr_a <= TO_UVEC(page_sel_a, c_mem_nof_pages_w) & adr_a;
mem_adr_b <= TO_UVEC(page_sel_b, c_mem_nof_pages_w) & adr_b;
- end generate; -- gen_adr
+ -- gen_adr
+ end generate;
gen_ofs : if g_str = "use_ofs" generate
u_buf : entity work.common_ram_crw_crw
@@ -335,6 +339,7 @@ begin
buf_adr_a <= INCR_UVEC(RESIZE_UVEC(adr_a, c_buf_addr_w), page_ofs_a);
buf_adr_b <= INCR_UVEC(RESIZE_UVEC(adr_b, c_buf_addr_w), page_ofs_b);
- end generate; -- gen_ofs
+ -- gen_ofs
+ end generate;
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd b/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
index 254a426c535fa4f92dbcb191a1fb9a21c1e7ecb5..284e572a1847bbb9ccac05c7668a90c508e3e467 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
@@ -37,7 +37,8 @@ entity common_paged_ram_r_w is
g_technology : natural := c_tech_select_default;
g_str : string := "use_adr";
g_data_w : natural;
- g_nof_pages : natural := 2; -- >= 2
+ -- >= 2
+ g_nof_pages : natural := 2;
g_page_sz : natural;
g_wr_start_page : natural := 0;
g_rd_start_page : natural := 0;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
index 22dc9992af4ac0225fe7caa13e1f6f108312a1b3..93a1ee72765958913f79244a1b8cc99fda2b4b34 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
@@ -37,7 +37,8 @@ entity common_paged_ram_rw_rw is
g_technology : natural := c_tech_select_default;
g_str : string := "use_adr";
g_data_w : natural;
- g_nof_pages : natural := 2; -- >= 2
+ -- >= 2
+ g_nof_pages : natural := 2;
g_page_sz : natural;
g_start_page_a : natural := 0;
g_start_page_b : natural := 0;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd b/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
index 4c253131235954b6e58b1a55d0afa6eb6a4f19ec..677f361e6ad28dca76787c4a82a555a3b42479a2 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
@@ -33,11 +33,14 @@ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_w_rr is
generic (
g_technology : natural := c_tech_select_default;
- g_pipeline_in : natural := 0; -- >= 0
- g_pipeline_out : natural := 0; -- >= 0
+ -- >= 0
+ g_pipeline_in : natural := 0;
+ -- >= 0
+ g_pipeline_out : natural := 0;
g_data_w : natural;
g_page_sz : natural;
- g_ram_rd_latency : natural := 1 -- >= 1
+ -- >= 1
+ g_ram_rd_latency : natural := 1
);
port (
rst : in std_logic;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd b/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
index 8a0e60be2e9fc87e21176f90504d5e47ff4fd7d8..0398ac13e98fb79f5726c43ddb6edf8b311462d5 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
@@ -35,11 +35,14 @@ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_ww_rr is
generic (
g_technology : natural := c_tech_select_default;
- g_pipeline_in : natural := 0; -- >= 0
- g_pipeline_out : natural := 0; -- >= 0
+ -- >= 0
+ g_pipeline_in : natural := 0;
+ -- >= 0
+ g_pipeline_out : natural := 0;
g_data_w : natural;
g_page_sz : natural;
- g_ram_rd_latency : natural := 1 -- >= 1
+ -- >= 1
+ g_ram_rd_latency : natural := 1
);
port (
rst : in std_logic;
@@ -71,8 +74,10 @@ architecture rtl of common_paged_ram_ww_rr is
constant c_sel_latency : natural := g_pipeline_in + g_ram_rd_latency;
constant c_rd_latency : natural := g_pipeline_in + g_ram_rd_latency + g_pipeline_out;
- constant c_nof_ports : natural := 2; -- Fixed dual port, port a and port b
- constant c_nof_pages : natural := 2; -- Fixed dual page, page 0 and page 1
+ -- Fixed dual port, port a and port b
+ constant c_nof_ports : natural := 2;
+ -- Fixed dual page, page 0 and page 1
+ constant c_nof_pages : natural := 2;
constant c_addr_w : natural := ceil_log2(g_page_sz);
diff --git a/libraries/base/common/src/vhdl/common_paged_reg.vhd b/libraries/base/common/src/vhdl/common_paged_reg.vhd
index 1e02358fc6f748f42a4df1a020cf466479a27893..e0a3489ca38a88effca485c0c8fd0d7cbc1fd757 100644
--- a/libraries/base/common/src/vhdl/common_paged_reg.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_reg.vhd
@@ -33,7 +33,8 @@ use work.common_pkg.all;
entity common_paged_reg is
generic (
g_data_w : natural := 8;
- g_nof_pages : natural := 2 -- >= 0
+ -- >= 0
+ g_nof_pages : natural := 2
);
port (
rst : in std_logic := '0';
diff --git a/libraries/base/common/src/vhdl/common_pipeline.vhd b/libraries/base/common/src/vhdl/common_pipeline.vhd
index 27d000cd2b1f9cf65557a442b6bd99b5524a5484..3fc25b772d1174bddb0f4f13165b2b1b213b26bb 100644
--- a/libraries/base/common/src/vhdl/common_pipeline.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline.vhd
@@ -25,8 +25,10 @@ use work.common_pkg.all;
entity common_pipeline is
generic (
- g_representation : string := "SIGNED"; -- or "UNSIGNED"
- g_pipeline : natural := 1; -- 0 for wires, > 0 for registers,
+ -- or "UNSIGNED"
+ g_representation : string := "SIGNED";
+ -- 0 for wires, > 0 for registers,
+ g_pipeline : natural := 1;
g_reset_value : integer := 0;
g_in_dat_w : natural := 8;
g_out_dat_w : natural := 9
diff --git a/libraries/base/common/src/vhdl/common_pipeline_integer.vhd b/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
index 5965cde936445198449e97e2e441b7ffb0b657e3..05673db9ab563bf577bc2edd844cc739e781a9e0 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
@@ -25,8 +25,10 @@ use work.common_pkg.all;
entity common_pipeline_integer is
generic (
- g_representation : string := "SIGNED"; -- or "UNSIGNED"
- g_pipeline : natural := 1; -- 0 for wires, > 0 for registers,
+ -- or "UNSIGNED"
+ g_representation : string := "SIGNED";
+ -- 0 for wires, > 0 for registers,
+ g_pipeline : natural := 1;
g_reset_value : integer := 0;
g_dat_w : natural := 8
);
diff --git a/libraries/base/common/src/vhdl/common_pipeline_natural.vhd b/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
index 971946f8d493a5ab394837cabc938ac36ed547f9..f71f0edc27bb2f629831f7bda5b36850dea65d1c 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
@@ -25,7 +25,8 @@ use work.common_pkg.all;
entity common_pipeline_natural is
generic (
- g_pipeline : natural := 1; -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline : natural := 1;
g_reset_value : integer := 0;
g_dat_w : natural := 8
);
diff --git a/libraries/base/common/src/vhdl/common_pipeline_sl.vhd b/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
index 0d592b72419de476307bb184b4820be12f7ae97a..a521b247ffb05f2da7d4a03c62a8de5f7c49273f 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
@@ -26,8 +26,10 @@ use work.common_pkg.all;
entity common_pipeline_sl is
generic (
- g_pipeline : natural := 1; -- 0 for wires, > 0 for registers,
- g_reset_value : natural := 0; -- 0 or 1, bit reset value,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline : natural := 1;
+ -- 0 or 1, bit reset value,
+ g_reset_value : natural := 0;
g_out_invert : boolean := false
);
port (
diff --git a/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd b/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
index 8d883bbf79825eb22ceaac144aab055bc737e26a..849510c07c88c351fbd1b92080648b62a58f05ad 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
@@ -33,7 +33,8 @@ use work.common_pkg.all;
entity common_pipeline_symbol is
generic (
- g_pipeline_arr : t_natural_arr; -- range g_nof_symbols-1 DOWNTO 0
+ -- range g_nof_symbols-1 DOWNTO 0
+ g_pipeline_arr : t_natural_arr;
g_nof_symbols : natural := 4;
g_symbol_w : natural := 16
);
@@ -47,9 +48,12 @@ entity common_pipeline_symbol is
in_eop : in std_logic := '0';
out_data : out std_logic_vector(g_nof_symbols * g_symbol_w - 1 downto 0);
- out_val_arr : out std_logic_vector(g_nof_symbols - 1 downto 0); -- pipelined in_val
- out_sop_arr : out std_logic_vector(g_nof_symbols - 1 downto 0); -- pipelined in_sop
- out_eop_arr : out std_logic_vector(g_nof_symbols - 1 downto 0) -- pipelined in_eop
+ -- pipelined in_val
+ out_val_arr : out std_logic_vector(g_nof_symbols - 1 downto 0);
+ -- pipelined in_sop
+ out_sop_arr : out std_logic_vector(g_nof_symbols - 1 downto 0);
+ -- pipelined in_eop
+ out_eop_arr : out std_logic_vector(g_nof_symbols - 1 downto 0)
);
end common_pipeline_symbol;
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index e1c2f98ffbcb2ba3cbf1ce2ba0ceff36e2e5250c..1f224becbde604d45c06a2ef54e69fee88a266ee 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -50,7 +50,8 @@ package common_pkg is
constant c_64 : natural := 64;
constant c_128 : natural := 128;
constant c_256 : natural := 256;
- constant c_natural_high : natural := 2147483647; -- = 2**31 - 1 = NATURAL'HIGH;
+ -- = 2**31 - 1 = NATURAL'HIGH;
+ constant c_natural_high : natural := 2147483647;
-- widths and sizes
constant c_halfword_sz : natural := 2;
@@ -61,8 +62,10 @@ package common_pkg is
constant c_octet_w : natural := 8;
constant c_halfword_w : natural := c_byte_w * c_halfword_sz;
constant c_word_w : natural := c_byte_w * c_word_sz;
- constant c_integer_w : natural := 32; -- unfortunately VHDL integer type is limited to 32 bit values
- constant c_natural_w : natural := c_integer_w - 1; -- unfortunately VHDL natural type is limited to 31 bit values (0 and the positive subset of the VHDL integer type0
+ -- unfortunately VHDL integer type is limited to 32 bit values
+ constant c_integer_w : natural := 32;
+ -- unfortunately VHDL natural type is limited to 31 bit values (0 and the positive subset of the VHDL integer type0
+ constant c_natural_w : natural := c_integer_w - 1;
constant c_longword_w : natural := c_byte_w * c_longword_sz;
-- logic
@@ -80,35 +83,56 @@ package common_pkg is
constant c_slv10 : std_logic_vector(255 downto 0) := c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10 & c_word_10;
-- math
- constant c_nof_complex : natural := 2; -- Real and imaginary part of complex number
- constant c_sign_w : natural := 1; -- Sign bit, can be used to skip one of the double sign bits of a product
- constant c_sum_of_prod_w : natural := 1; -- Bit growth for sum of 2 products, can be used in case complex multiply has normalized real and imag inputs instead of normalized amplitude inputs
- constant c_eps : real := 1.0e-20; -- add small epsilon value to avoid 1/0 and log(0), 1e-20 < 1/2**64
+ -- Real and imaginary part of complex number
+ constant c_nof_complex : natural := 2;
+ -- Sign bit, can be used to skip one of the double sign bits of a product
+ constant c_sign_w : natural := 1;
+ -- Bit growth for sum of 2 products, can be used in case complex multiply has normalized real and imag inputs instead of normalized amplitude inputs
+ constant c_sum_of_prod_w : natural := 1;
+ -- add small epsilon value to avoid 1/0 and log(0), 1e-20 < 1/2**64
+ constant c_eps : real := 1.0e-20;
-- FF, block RAM, FIFO
- constant c_meta_delay_len : natural := 3; -- default nof flipflops (FF) in meta stability recovery delay line (e.g. for clock domain crossing)
- constant c_meta_fifo_depth : natural := 16; -- default use 16 word deep FIFO to cross clock domain, typically > 2*c_meta_delay_len or >~ 8 is enough
+ -- default nof flipflops (FF) in meta stability recovery delay line (e.g. for clock domain crossing)
+ constant c_meta_delay_len : natural := 3;
+ -- default use 16 word deep FIFO to cross clock domain, typically > 2*c_meta_delay_len or >~ 8 is enough
+ constant c_meta_fifo_depth : natural := 16;
- constant c_bram_m9k_nof_bits : natural := 1024 * 9; -- size of 1 Altera M9K block RAM in bits
- constant c_bram_m9k_max_w : natural := 36; -- maximum width of 1 Altera M9K block RAM, so the size is then 256 words of 36 bits
- constant c_bram_m9k_fifo_depth : natural := c_bram_m9k_nof_bits / c_bram_m9k_max_w; -- using a smaller FIFO depth than this leaves part of the RAM unused
+ -- size of 1 Altera M9K block RAM in bits
+ constant c_bram_m9k_nof_bits : natural := 1024 * 9;
+ -- maximum width of 1 Altera M9K block RAM, so the size is then 256 words of 36 bits
+ constant c_bram_m9k_max_w : natural := 36;
+ -- using a smaller FIFO depth than this leaves part of the RAM unused
+ constant c_bram_m9k_fifo_depth : natural := c_bram_m9k_nof_bits / c_bram_m9k_max_w;
- constant c_fifo_afull_margin : natural := 4; -- default or minimal FIFO almost full margin
+ -- default or minimal FIFO almost full margin
+ constant c_fifo_afull_margin : natural := 4;
-- DSP
- constant c_dsp_mult_w : natural := 18; -- Width of the embedded multipliers in Stratix IV (and Arria 10 for 2 multipliers per DSP block)
- constant c_dsp_mult_18_w : natural := 18; -- Width of the embedded multipliers in Stratix IV (and Arria 10 for 2 multipliers per DSP block)
- constant c_dsp_mult_27_w : natural := 27; -- Width of the embedded multipliers in Arria 10
+ -- Width of the embedded multipliers in Stratix IV (and Arria 10 for 2 multipliers per DSP block)
+ constant c_dsp_mult_w : natural := 18;
+ -- Width of the embedded multipliers in Stratix IV (and Arria 10 for 2 multipliers per DSP block)
+ constant c_dsp_mult_18_w : natural := 18;
+ -- Width of the embedded multipliers in Arria 10
+ constant c_dsp_mult_27_w : natural := 27;
-- TYPE DECLARATIONS --------------------------------------------------------
- type t_boolean_arr is array (integer range <>) of boolean; -- INTEGER left index starts default at -2**31
- type t_integer_arr is array (integer range <>) of integer; -- INTEGER left index starts default at -2**31
- type t_natural_arr is array (integer range <>) of natural; -- INTEGER left index starts default at -2**31
- type t_real_arr is array (integer range <>) of real; -- INTEGER left index starts default at -2**31
- type t_nat_boolean_arr is array (natural range <>) of boolean; -- NATURAL left index starts default at 0
- type t_nat_integer_arr is array (natural range <>) of integer; -- NATURAL left index starts default at 0
- type t_nat_natural_arr is array (natural range <>) of natural; -- NATURAL left index starts default at 0
- type t_nat_real_arr is array (natural range <>) of real; -- NATURAL left index starts default at 0
+ -- INTEGER left index starts default at -2**31
+ type t_boolean_arr is array (integer range <>) of boolean;
+ -- INTEGER left index starts default at -2**31
+ type t_integer_arr is array (integer range <>) of integer;
+ -- INTEGER left index starts default at -2**31
+ type t_natural_arr is array (integer range <>) of natural;
+ -- INTEGER left index starts default at -2**31
+ type t_real_arr is array (integer range <>) of real;
+ -- NATURAL left index starts default at 0
+ type t_nat_boolean_arr is array (natural range <>) of boolean;
+ -- NATURAL left index starts default at 0
+ type t_nat_integer_arr is array (natural range <>) of integer;
+ -- NATURAL left index starts default at 0
+ type t_nat_natural_arr is array (natural range <>) of natural;
+ -- NATURAL left index starts default at 0
+ type t_nat_real_arr is array (natural range <>) of real;
type t_sl_arr is array (integer range <>) of std_logic;
type t_slv_1_arr is array (integer range <>) of std_logic_vector(0 downto 0);
type t_slv_2_arr is array (integer range <>) of std_logic_vector(1 downto 0);
@@ -127,8 +151,10 @@ package common_pkg is
type t_slv_512_arr is array (integer range <>) of std_logic_vector(511 downto 0);
type t_slv_1024_arr is array (integer range <>) of std_logic_vector(1023 downto 0);
- constant c_boolean_arr : t_boolean_arr := (true, false); -- array the two possible boolean values that can be iterated over
- constant c_nat_boolean_arr : t_nat_boolean_arr := (true, false); -- array the two possible boolean values that can be iterated over
+ -- array the two possible boolean values that can be iterated over
+ constant c_boolean_arr : t_boolean_arr := (true, false);
+ -- array the two possible boolean values that can be iterated over
+ constant c_nat_boolean_arr : t_nat_boolean_arr := (true, false);
type t_integer_matrix is array (integer range <>, integer range <>) of integer;
type t_boolean_matrix is array (integer range <>, integer range <>) of boolean;
@@ -167,86 +193,125 @@ package common_pkg is
type t_sys_rce is record
rst : std_logic;
clk : std_logic;
- clken : std_logic; -- := '1';
+ -- := '1';
+ clken : std_logic;
end record;
type t_sys_ce is record
clk : std_logic;
- clken : std_logic; -- := '1';
+ -- := '1';
+ clken : std_logic;
end record;
-- FUNCTION DECLARATIONS ----------------------------------------------------
-- All functions assume [high downto low] input ranges
- function pow2(n : natural) return natural; -- = 2**n
- function ceil_pow2(n : integer) return natural; -- = 2**n, returns 1 for n<0
+ -- = 2**n
+ function pow2(n : natural) return natural;
+ -- = 2**n, returns 1 for n<0
+ function ceil_pow2(n : integer) return natural;
- function true_log2(n : natural) return natural; -- true_log2(n) = log2(n)
- function ceil_log2(n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ -- true_log2(n) = log2(n)
+ function true_log2(n : natural) return natural;
+ -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ function ceil_log2(n : natural) return natural;
function floor_log10(n : natural) return natural;
- function is_pow2(n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
- function true_log_pow2(n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
+ -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
+ function is_pow2(n : natural) return boolean;
+ -- 2**true_log2(n), return power of 2 that is >= n
+ function true_log_pow2(n : natural) return natural;
- function ratio( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
- function ratio2(n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
+ -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
+ function ratio( n, d : natural) return natural;
+ -- return integer ratio of n/m or m/n, whichever is the largest
+ function ratio2(n, m : natural) return natural;
-- use almost_equal(a/b, 1.0, max_ratio) to verify that a and b differ less than max_ratio/100 percent
-- use almost_zero(a/b, max_ratio) to verify that a is less than max_ratio/100 percent of b, so almost zero
- function almost_equal(a, b, delta : real) return boolean; -- return TRUE when abs(a - b) < abs(delta), else return FALSE
+ -- return TRUE when abs(a - b) < abs(delta), else return FALSE
+ function almost_equal(a, b, delta : real) return boolean;
function almost_equal(a, b, delta : integer) return boolean;
- function almost_zero(a, delta : real) return boolean; -- return TRUE when abs(a) < abs(delta), else return FALSE
+ -- return TRUE when abs(a) < abs(delta), else return FALSE
+ function almost_zero(a, delta : real) return boolean;
function almost_zero(a, delta : integer) return boolean;
- function ceil_div( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
- function ceil_value( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
- function floor_value(n, d : natural) return natural; -- floor_value = (n/d) * d
+ -- ceil_div = n/d + (n MOD d)/=0
+ function ceil_div( n, d : natural) return natural;
+ -- ceil_value = ceil_div(n, d) * d
+ function ceil_value( n, d : natural) return natural;
+ -- floor_value = (n/d) * d
+ function floor_value(n, d : natural) return natural;
function ceil_div( n : unsigned; d: natural) return unsigned;
function ceil_value( n : unsigned; d: natural) return unsigned;
function floor_value(n : unsigned; d: natural) return unsigned;
- function gcd(a, b : natural) return natural; -- greatest common divider
-
- function slv(n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
- function sl( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
-
- function to_sl( n: in boolean) return std_logic; -- if TRUE then return '1' else '0'
- function to_bool(n: in std_logic) return boolean; -- if '1' or 'H' then return TRUE else FALSE
- function to_bool(n: in integer) return boolean; -- if 0 then return FALSE else TRUE
-
- function not_int(n: in integer) return integer; -- if 0 then return 1 else 0
-
- function pack_complex(re, im : integer; w : natural) return integer; -- pack order: im & re
- function unpack_complex_re(data : integer; w : natural) return integer; -- pack order: im & re
- function unpack_complex_re(data : std_logic_vector; w : natural) return integer; -- pack order: im & re
- function unpack_complex_im(data : integer; w : natural) return integer; -- pack order: im & re
- function unpack_complex_im(data : std_logic_vector; w : natural) return integer; -- pack order: im & re
-
- function atan2(Y, X: real) return real; -- = ARCTAN(Y, X) but returns 0 when Y = X = 0, without reporting Error: ARCTAN(0.0, 0.0) is undetermined
-
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ -- greatest common divider
+ function gcd(a, b : natural) return natural;
+
+ -- standard logic to 1 element standard logic vector
+ function slv(n: in std_logic) return std_logic_vector;
+ -- 1 element standard logic vector to standard logic
+ function sl( n: in std_logic_vector) return std_logic;
+
+ -- if TRUE then return '1' else '0'
+ function to_sl( n: in boolean) return std_logic;
+ -- if '1' or 'H' then return TRUE else FALSE
+ function to_bool(n: in std_logic) return boolean;
+ -- if 0 then return FALSE else TRUE
+ function to_bool(n: in integer) return boolean;
+
+ -- if 0 then return 1 else 0
+ function not_int(n: in integer) return integer;
+
+ -- pack order: im & re
+ function pack_complex(re, im : integer; w : natural) return integer;
+ -- pack order: im & re
+ function unpack_complex_re(data : integer; w : natural) return integer;
+ -- pack order: im & re
+ function unpack_complex_re(data : std_logic_vector; w : natural) return integer;
+ -- pack order: im & re
+ function unpack_complex_im(data : integer; w : natural) return integer;
+ -- pack order: im & re
+ function unpack_complex_im(data : std_logic_vector; w : natural) return integer;
+
+ -- = ARCTAN(Y, X) but returns 0 when Y = X = 0, without reporting Error: ARCTAN(0.0, 0.0) is undetermined
+ function atan2(Y, X: real) return real;
+
+ -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr;
function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr;
function to_integer_arr(n : t_natural_arr) return t_integer_arr;
function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr;
function to_slv_32_arr( n : t_integer_arr) return t_slv_32_arr;
function to_slv_32_arr( n : t_natural_arr) return t_slv_32_arr;
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
- function vector_and(slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
- function vector_or( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
- function vector_xor(slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
-
- function andv(slv : std_logic_vector) return std_logic; -- alias of vector_and
- function orv( slv : std_logic_vector) return std_logic; -- alias of vector_or
- function xorv(slv : std_logic_vector) return std_logic; -- alias of vector_xor
+ -- Core operation tree function for vector "AND", "OR", "XOR"
+ function vector_tree(slv : std_logic_vector; operation : string) return std_logic;
+ -- '1' when all slv bits are '1' else '0'
+ function vector_and(slv : std_logic_vector) return std_logic;
+ -- '0' when all slv bits are '0' else '1'
+ function vector_or( slv : std_logic_vector) return std_logic;
+ -- '1' when the slv has an odd number of '1' bits else '0'
+ function vector_xor(slv : std_logic_vector) return std_logic;
+ -- Returns slv when it contains one hot bit, else returns 0.
+ function vector_one_hot(slv : std_logic_vector) return std_logic_vector;
+
+ -- alias of vector_and
+ function andv(slv : std_logic_vector) return std_logic;
+ -- alias of vector_or
+ function orv( slv : std_logic_vector) return std_logic;
+ -- alias of vector_xor
+ function xorv(slv : std_logic_vector) return std_logic;
function array_and(arr : t_nat_boolean_arr) return boolean;
function array_or( arr : t_nat_boolean_arr) return boolean;
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
- function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
+ -- '1' when all matrix bits are '1' else '0'
+ function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic;
+ -- '0' when all matrix bits are '0' else '1'
+ function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic;
function smallest(n, m : integer) return integer;
function smallest(n, m : real) return real;
@@ -259,34 +324,51 @@ package common_pkg is
function largest(n : t_natural_arr) return natural;
function largest(n : t_nat_natural_arr) return natural;
- function func_sum( n : t_natural_arr) return natural; -- sum of all elements in array
+ -- sum of all elements in array
+ function func_sum( n : t_natural_arr) return natural;
function func_sum( n : t_nat_natural_arr) return natural;
- function func_product(n : t_natural_arr) return natural; -- product of all elements in array
+ -- product of all elements in array
+ function func_product(n : t_natural_arr) return natural;
function func_product(n : t_nat_natural_arr) return natural;
- function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
- function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
- function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
-
- function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
- function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
- function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
- function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
-
- function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
- function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
- function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
-
- function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
- function "/" (L : t_natural_arr; R : positive) return t_natural_arr; -- element wise division
- function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
+ -- element wise sum
+ function "+" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise sum
+ function "+" (L : t_natural_arr; R : integer) return t_natural_arr;
+ -- element wise sum
+ function "+" (L : integer; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise subtract
+ function "-" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise subtract, support negative result
+ function "-" (L, R: t_natural_arr) return t_integer_arr;
+ -- element wise subtract
+ function "-" (L : t_natural_arr; R : integer) return t_natural_arr;
+ -- element wise subtract
+ function "-" (L : integer; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise product
+ function "*" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise product
+ function "*" (L : t_natural_arr; R : natural) return t_natural_arr;
+ -- element wise product
+ function "*" (L : natural; R : t_natural_arr) return t_natural_arr;
+
+ -- element wise division
+ function "/" (L, R: t_natural_arr) return t_natural_arr;
+ -- element wise division
+ function "/" (L : t_natural_arr; R : positive) return t_natural_arr;
+ -- element wise division
+ function "/" (L : natural; R : t_natural_arr) return t_natural_arr;
function is_true(a : std_logic) return boolean;
function is_true(a : std_logic) return natural;
function is_true(a : boolean) return std_logic;
function is_true(a : boolean) return natural;
- function is_true(a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
- function is_true(a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
+ -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true(a : integer) return boolean;
+ -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true(a : integer) return std_logic;
function sel_a_b(sel, a, b : boolean) return boolean;
function sel_a_b(sel, a, b : integer) return integer;
@@ -308,47 +390,81 @@ package common_pkg is
function sel_a_b(sel : boolean; a, b : severity_level) return severity_level;
-- sel_n() index sel = 0, 1, 2, ... will return a, b, c, ...
- function sel_n(sel : natural; a, b, c : boolean) return boolean; -- 3
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean; -- 4
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
-
- function sel_n(sel : natural; a, b, c : integer) return integer; -- 3
- function sel_n(sel : natural; a, b, c, d : integer) return integer; -- 4
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
-
- function sel_n(sel : natural; a, b : string) return string; -- 2
- function sel_n(sel : natural; a, b, c : string) return string; -- 3
- function sel_n(sel : natural; a, b, c, d : string) return string; -- 4
- function sel_n(sel : natural; a, b, c, d, e : string) return string; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
- function array_init(init : boolean; nof : natural) return t_nat_boolean_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
+ -- 3
+ function sel_n(sel : natural; a, b, c : boolean) return boolean;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : boolean) return boolean;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean;
+
+ -- 3
+ function sel_n(sel : natural; a, b, c : integer) return integer;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : integer) return integer;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : integer) return integer;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer;
+
+ -- 2
+ function sel_n(sel : natural; a, b : string) return string;
+ -- 3
+ function sel_n(sel : natural; a, b, c : string) return string;
+ -- 4
+ function sel_n(sel : natural; a, b, c, d : string) return string;
+ -- 5
+ function sel_n(sel : natural; a, b, c, d, e : string) return string;
+ -- 6
+ function sel_n(sel : natural; a, b, c, d, e, f : string) return string;
+ -- 7
+ function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string;
+ -- 8
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string;
+ -- 9
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string;
+ -- 10
+ function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string;
+
+ -- useful to init a unconstrained array of size 1
+ function array_init(init : std_logic; nof : natural) return std_logic_vector;
+ -- useful to init a unconstrained array of size 1
+ function array_init(init : boolean; nof : natural) return t_nat_boolean_arr;
+ -- useful to init a unconstrained array of size 1
+ function array_init(init, nof : natural) return t_natural_arr;
+ -- useful to init a unconstrained array of size 1
+ function array_init(init, nof : natural) return t_nat_natural_arr;
+ -- useful to init an array with incrementing numbers
+ function array_init(init, nof, incr : natural) return t_natural_arr;
function array_init(init, nof, incr : natural) return t_nat_natural_arr;
function array_init(init, nof, incr : integer) return t_slv_16_arr;
function array_init(init, nof, incr : integer) return t_slv_32_arr;
- function array_init(init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
- function array_init(init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
- function array_sinit(init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+ -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_init(init, nof, width : natural) return std_logic_vector;
+ -- useful to init an unconstrained std_logic_vector with incrementing content
+ function array_init(init, nof, width, incr : natural) return std_logic_vector;
+ -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_sinit(init : integer; nof, width : natural) return std_logic_vector;
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
+ -- initialize all elements in t_slv_64_matrix to value k
+ function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix;
-- Concatenate two or more STD_LOGIC_VECTORs into a single STD_LOGIC_VECTOR or extract one of them from a concatenated STD_LOGIC_VECTOR
-- . Note that using func_slv_concat() without the BOOLEAN use_* is equivalent to using the
@@ -395,23 +511,33 @@ package common_pkg is
-- . https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Definition+of+fixed+point+numbers
-- . https://support.astron.nl/confluence/display/L2M/L4+SDPFW+Decision%3A+Number+representation%2C+resizing+and+rounding
- function TO_UINT(vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ function TO_UINT(vec : std_logic_vector) return natural;
function TO_SINT(vec : std_logic_vector) return integer;
function TO_UVEC(dec, w : natural) return std_logic_vector;
function TO_SVEC(dec, w : integer) return std_logic_vector;
- function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
-
- function TO_UINT(udec : real; w, resolution_w : integer) return natural; -- REAL >= 0 to NATURAL fixed point number
- function TO_SINT(sdec : real; w, resolution_w : integer) return integer; -- REAL to INTEGER fixed point number
- function TO_UVEC(udec : real; w, resolution_w : integer) return std_logic_vector; -- REAL >= 0 to unsigned SLV fixed point number
- function TO_SVEC(sdec : real; w, resolution_w : integer) return std_logic_vector; -- REAL to signed SLV fixed point number
-
- function TO_UREAL(uvec : std_logic_vector) return real; -- convert unsigned slv of any length to REAL, fixed point number with resolution = 1
- function TO_SREAL(svec : std_logic_vector) return real; -- convert signed slv of any length to REAL, fixed point number with resolution = 1
- function TO_UREAL(uvec : std_logic_vector; resolution_w : integer) return real; -- convert unsigned fixed point slv of any length, and with resolution of 2**resolution_w, to REAL
- function TO_SREAL(svec : std_logic_vector; resolution_w : integer) return real; -- convert signed fixed point slv of any length, and with resolution of 2**resolution_w, to REAL
+ -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
+ function TO_SVEC_32(dec : integer) return std_logic_vector;
+
+ -- REAL >= 0 to NATURAL fixed point number
+ function TO_UINT(udec : real; w, resolution_w : integer) return natural;
+ -- REAL to INTEGER fixed point number
+ function TO_SINT(sdec : real; w, resolution_w : integer) return integer;
+ -- REAL >= 0 to unsigned SLV fixed point number
+ function TO_UVEC(udec : real; w, resolution_w : integer) return std_logic_vector;
+ -- REAL to signed SLV fixed point number
+ function TO_SVEC(sdec : real; w, resolution_w : integer) return std_logic_vector;
+
+ -- convert unsigned slv of any length to REAL, fixed point number with resolution = 1
+ function TO_UREAL(uvec : std_logic_vector) return real;
+ -- convert signed slv of any length to REAL, fixed point number with resolution = 1
+ function TO_SREAL(svec : std_logic_vector) return real;
+ -- convert unsigned fixed point slv of any length, and with resolution of 2**resolution_w, to REAL
+ function TO_UREAL(uvec : std_logic_vector; resolution_w : integer) return real;
+ -- convert signed fixed point slv of any length, and with resolution of 2**resolution_w, to REAL
+ function TO_SREAL(svec : std_logic_vector; resolution_w : integer) return real;
-- RESIZE_NUM() original description:
-- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
@@ -445,108 +571,176 @@ package common_pkg is
-- RESIZE() does (keeping the MSbit and the w-1 LSbits). The wrapping of RESIZE_NUM() preserves the
-- capability of recovering from intermediate overflow in a summator, which can be beneficial for e.g.
-- a beamformer.
- function RESIZE_NUM( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
- function RESIZE_NUM( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
- function RESIZE_UINT(u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
- function RESIZE_SINT(s : integer; w : natural) return integer; -- extend sign bit or keep LS part
-
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
-
- function NEGATE_SVEC(vec : std_logic_vector) return std_logic_vector; -- assume negated ranges fits within -+max
- function NEGATE_SVEC(vec : std_logic_vector; w : integer) return std_logic_vector; -- avoid overflow by forcing -min to +max. Use w <= vec'LENGTH
+ -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
+ function RESIZE_NUM( u : unsigned; w : natural) return unsigned;
+ -- extend sign bit or keep LS part
+ function RESIZE_NUM( s : signed; w : natural) return signed;
+ -- left extend with '0' into slv
+ function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector;
+ -- left extend with '0' or keep LS part
+ function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector;
+ -- extend sign bit or keep LS part
+ function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector;
+ -- left extend with '0' or keep LS part
+ function RESIZE_UINT(u : integer; w : natural) return integer;
+ -- extend sign bit or keep LS part
+ function RESIZE_SINT(s : integer; w : natural) return integer;
+
+ -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector;
+ -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector;
+
+ -- assume negated ranges fits within -+max
+ function NEGATE_SVEC(vec : std_logic_vector) return std_logic_vector;
+ -- avoid overflow by forcing -min to +max. Use w <= vec'LENGTH
+ function NEGATE_SVEC(vec : std_logic_vector; w : integer) return std_logic_vector;
function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
-- Used in common_add_sub.vhd
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
-
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
-
- function MULT_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec * r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH + r_vec'LENGTH
- function MULT_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec * r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH + r_vec'LENGTH
-
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
+ -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
+ function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
+ function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
+ function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
+ function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector;
+
+ -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+
+ -- l_vec * r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH + r_vec'LENGTH
+ function MULT_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+ -- l_vec * r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH + r_vec'LENGTH
+ function MULT_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector;
+
+ -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
+ function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer;
+ -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
+ function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer;
-- Convert between polar and rectangular coordinates
function COMPLEX_RADIUS(re, im : real) return real;
function COMPLEX_RADIUS(re, im : integer) return real;
- function COMPLEX_PHASE( re, im : real; radians : boolean) return real; -- phase in radians or degrees
- function COMPLEX_PHASE( re, im : integer; radians : boolean) return real; -- phase in radians or degrees
- function COMPLEX_PHASE( re, im : real) return real; -- phase in degrees
- function COMPLEX_PHASE( re, im : integer) return real; -- phase in degrees
-
- function COMPLEX_RE(ampl, phase : real; radians : boolean) return real; -- phase in radians or degrees
- function COMPLEX_RE(ampl, phase : integer; radians : boolean) return real; -- phase in radians or degrees
- function COMPLEX_RE(ampl, phase : real) return real; -- phase in degrees
- function COMPLEX_RE(ampl, phase : integer) return real; -- phase in degrees
-
- function COMPLEX_IM(ampl, phase : real; radians : boolean) return real; -- phase in radians or degrees
- function COMPLEX_IM(ampl, phase : integer; radians : boolean) return real; -- phase in radians or degrees
- function COMPLEX_IM(ampl, phase : real) return real; -- phase in degrees
- function COMPLEX_IM(ampl, phase : integer) return real; -- phase in degrees
-
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
-
- function ROTATE_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 rotate left, > 0 rotate right
+ -- phase in radians or degrees
+ function COMPLEX_PHASE( re, im : real; radians : boolean) return real;
+ -- phase in radians or degrees
+ function COMPLEX_PHASE( re, im : integer; radians : boolean) return real;
+ -- phase in degrees
+ function COMPLEX_PHASE( re, im : real) return real;
+ -- phase in degrees
+ function COMPLEX_PHASE( re, im : integer) return real;
+
+ -- phase in radians or degrees
+ function COMPLEX_RE(ampl, phase : real; radians : boolean) return real;
+ -- phase in radians or degrees
+ function COMPLEX_RE(ampl, phase : integer; radians : boolean) return real;
+ -- phase in degrees
+ function COMPLEX_RE(ampl, phase : real) return real;
+ -- phase in degrees
+ function COMPLEX_RE(ampl, phase : integer) return real;
+
+ -- phase in radians or degrees
+ function COMPLEX_IM(ampl, phase : real; radians : boolean) return real;
+ -- phase in radians or degrees
+ function COMPLEX_IM(ampl, phase : integer; radians : boolean) return real;
+ -- phase in degrees
+ function COMPLEX_IM(ampl, phase : real) return real;
+ -- phase in degrees
+ function COMPLEX_IM(ampl, phase : integer) return real;
+
+ -- < 0 shift left, > 0 shift right
+ function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector;
+ -- < 0 shift left, > 0 shift right
+ function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector;
+
+ -- < 0 rotate left, > 0 rotate right
+ function ROTATE_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector;
function offset_binary(a : std_logic_vector) return std_logic_vector;
- function truncate( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function scale( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
- function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
- function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
- function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
-
- function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
- function s_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
- function s_round( vec : std_logic_vector; n : natural; clip, even : boolean) return std_logic_vector; -- idem but round half to even for signed
- function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
- function u_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
- function u_round( vec : std_logic_vector; n : natural; clip, even : boolean) return std_logic_vector; -- idem but round half to even for unsigned
-
- function u_to_s(u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
- function s_to_u(s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
-
- function u_wrap(u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
- function s_wrap(s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
-
- function u_clip(u : natural; max : natural) return natural; -- if s < max return s, else return n
- function s_clip(s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
- function s_clip(s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
-
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
- function hton(a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
- function ntoh(a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
-
- function flip(a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
- function flip(a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ -- remove n LSBits from vec, so result has width vec'LENGTH-n
+ function truncate( vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- remove n LSBits from vec and then resize to width w
+ function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- idem for signed values
+ function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- add n '0' LSBits to vec
+ function scale( vec : std_logic_vector; n: natural) return std_logic_vector;
+ -- add n '0' LSBits to vec and then resize to width w
+ function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- idem for signed values
+ function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector;
+ -- when b=TRUE then truncate to width w, else resize to width w
+ function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector;
+ -- idem for signed values
+ function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector;
+
+ -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
+ function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector;
+ -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
+ function s_round( vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- idem but round half to even for signed
+ function s_round( vec : std_logic_vector; n : natural; clip, even : boolean) return std_logic_vector;
+ -- idem round up for unsigned values
+ function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector;
+ -- idem round up for unsigned values
+ function u_round( vec : std_logic_vector; n : natural) return std_logic_vector;
+ -- idem but round half to even for unsigned
+ function u_round( vec : std_logic_vector; n : natural; clip, even : boolean) return std_logic_vector;
+
+ -- interpret w bit unsigned u as w bit signed, and remove any MSbits
+ function u_to_s(u : natural; w : natural) return integer;
+ -- interpret w bit signed s as w bit unsigned, and remove any MSbits
+ function s_to_u(s : integer; w : natural) return natural;
+
+ -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
+ function u_wrap(u : natural; w : natural) return natural;
+ -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
+ function s_wrap(s : integer; w : natural) return integer;
+
+ -- if s < max return s, else return n
+ function u_clip(u : natural; max : natural) return natural;
+ -- if s <= min return min, else if s >= max return max, else return s
+ function s_clip(s : integer; max : natural; min : integer) return integer;
+ -- if s <= -max return -max, else if s >= max return max, else return s
+ function s_clip(s : integer; max : natural ) return integer;
+
+ -- convert endianity from host to network, sz in symbols of width w
+ function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector;
+ -- convert endianity from host to network, sz in bytes
+ function hton(a : std_logic_vector; sz : natural) return std_logic_vector;
+ -- convert endianity from host to network, for all bytes in a
+ function hton(a : std_logic_vector ) return std_logic_vector;
+ -- convert endianity from network to host, sz in bytes, ntoh() = hton()
+ function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector;
+ -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
+ function ntoh(a : std_logic_vector ) return std_logic_vector;
+
+ -- bit flip a vector, map a[h:0] to [0:h]
+ function flip(a : std_logic_vector) return std_logic_vector;
+ -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ function flip(a, w : natural) return natural;
function flip(a : t_slv_32_arr) return t_slv_32_arr;
function flip(a : t_integer_arr) return t_integer_arr;
function flip(a : t_natural_arr) return t_natural_arr;
function flip(a : t_nat_natural_arr) return t_nat_natural_arr;
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
- function transpose(a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
+ -- transpose a vector, map a[i*row+j] to output index [j*col+i]
+ function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector;
+ -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose(a, row, col : natural) return natural;
function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
@@ -633,9 +827,11 @@ package body common_pkg is
-- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
- return 0; -- Get NULL array
+ -- Get NULL array
+ return 0;
elsif n = 1 then
- return 1; -- avoid NULL array
+ -- avoid NULL array
+ return 1;
else
return true_log2(n);
end if;
@@ -715,7 +911,8 @@ package body common_pkg is
function ceil_div(n : unsigned; d: natural) return unsigned is
begin
- return n / d + sel_a_b(n mod d = 0, 0, 1); -- "/" returns same width as n
+ -- "/" returns same width as n
+ return n / d + sel_a_b(n mod d = 0, 0, 1);
end;
function ceil_value(n : unsigned; d: natural) return unsigned is
@@ -723,7 +920,8 @@ package body common_pkg is
variable p : unsigned(2 * w - 1 downto 0);
begin
p := ceil_div(n, d) * d;
- return p(w - 1 downto 0); -- return same width as n
+ -- return same width as n
+ return p(w - 1 downto 0);
end;
function floor_value(n : unsigned; d: natural) return unsigned is
@@ -731,10 +929,12 @@ package body common_pkg is
variable p : unsigned(2 * w - 1 downto 0);
begin
p := (n / d) * d;
- return p(w - 1 downto 0); -- return same width as n
+ -- return same width as n
+ return p(w - 1 downto 0);
end;
- function gcd(a, b : natural) return natural is -- greatest common divider
+ -- greatest common divider
+ function gcd(a, b : natural) return natural is
begin
if b = 0 then
return a;
@@ -786,9 +986,11 @@ package body common_pkg is
variable v_complex_slv : std_logic_vector(c_complex_w - 1 downto 0) := TO_SVEC(im, w) & TO_SVEC(re, w);
begin
assert c_complex_w <= c_word_w report "common_pkg: Complex value to large to pack into 32 bit integer" severity FAILURE;
- if c_complex_w < c_word_w then -- fits in 31 bit unsigned NATURAL
+ -- fits in 31 bit unsigned NATURAL
+ if c_complex_w < c_word_w then
return TO_UINT(v_complex_slv);
- else -- need to use 32 bit signed INTEGER
+ -- need to use 32 bit signed INTEGER
+ else
return TO_SINT(v_complex_slv);
end if;
end;
@@ -796,27 +998,31 @@ package body common_pkg is
function unpack_complex_re(data : std_logic_vector; w : natural) return integer is
begin
assert w <= c_word_w report "common_pkg: Complex value to large to unpack into 32 bit integer parts" severity FAILURE;
- return TO_SINT(data(w - 1 downto 0)); -- Re in LS part
+ -- Re in LS part
+ return TO_SINT(data(w - 1 downto 0));
end;
function unpack_complex_re(data : integer; w : natural) return integer is
constant c_complex_w : natural := 2 * w;
variable v_complex_slv : std_logic_vector(c_complex_w - 1 downto 0) := TO_SVEC(data, c_complex_w);
begin
- return TO_SINT(v_complex_slv(w - 1 downto 0)); -- Re in LS part
+ -- Re in LS part
+ return TO_SINT(v_complex_slv(w - 1 downto 0));
end;
function unpack_complex_im(data : std_logic_vector; w : natural) return integer is
begin
assert w <= c_word_w report "common_pkg: Complex value to large to unpack into 32 bit integer parts" severity FAILURE;
- return TO_SINT(data(2 * w - 1 downto w)); -- Im in MS part
+ -- Im in MS part
+ return TO_SINT(data(2 * w - 1 downto w));
end;
function unpack_complex_im(data : integer; w : natural) return integer is
constant c_complex_w : natural := 2 * w;
variable v_complex_slv : std_logic_vector(c_complex_w - 1 downto 0) := TO_SVEC(data, c_complex_w);
begin
- return TO_SINT(v_complex_slv(c_complex_w - 1 downto w)); -- Im in MS part
+ -- Im in MS part
+ return TO_SINT(v_complex_slv(c_complex_w - 1 downto w));
end;
function atan2(Y, X: real) return real is
@@ -906,7 +1112,8 @@ package body common_pkg is
-- Instead use binary tree to determine result with smallest combinatorial delay that depends on log2(slv'LENGTH)
constant c_slv_w : natural := slv'length;
constant c_nof_stages : natural := ceil_log2(c_slv_w);
- constant c_w : natural := 2**c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ constant c_w : natural := 2**c_nof_stages;
type t_stage_arr is array (-1 to c_nof_stages - 1) of std_logic_vector(c_w - 1 downto 0);
variable v_stage_arr : t_stage_arr;
variable v_result : std_logic := '0';
@@ -918,7 +1125,8 @@ package body common_pkg is
else
assert true report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
end if;
- v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
+ -- any unused input c_w : c_slv_w bits have void default value
+ v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv;
for J in 0 to c_nof_stages - 1 loop
for I in 0 to c_w / (2**(J + 1)) - 1 loop
if operation = "AND" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
@@ -982,19 +1190,24 @@ package body common_pkg is
function array_and(arr : t_nat_boolean_arr) return boolean is
variable v_slv : std_logic_vector(arr'range);
begin
- for I in arr'range loop v_slv(I) := sel_a_b(arr(I), '1', '0'); end loop; -- wire map boolean arr to slv
- return sel_a_b(vector_and(v_slv) = '1', true, false); -- use vector_tree to determine result
+ -- wire map boolean arr to slv
+ for I in arr'range loop v_slv(I) := sel_a_b(arr(I), '1', '0'); end loop;
+ -- use vector_tree to determine result
+ return sel_a_b(vector_and(v_slv) = '1', true, false);
end;
function array_or(arr : t_nat_boolean_arr) return boolean is
variable v_slv : std_logic_vector(arr'range);
begin
- for I in arr'range loop v_slv(I) := sel_a_b(arr(I), '1', '0'); end loop; -- wire map boolean arr to slv
- return sel_a_b(vector_or(v_slv) = '1', true, false); -- use vector_tree to determine result
+ -- wire map boolean arr to slv
+ for I in arr'range loop v_slv(I) := sel_a_b(arr(I), '1', '0'); end loop;
+ -- use vector_tree to determine result
+ return sel_a_b(vector_or(v_slv) = '1', true, false);
end;
function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic is
- variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
+ -- map to fixed range
+ variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat;
variable v_result : std_logic := '1';
begin
for I in 0 to wi - 1 loop
@@ -1006,7 +1219,8 @@ package body common_pkg is
end;
function matrix_or(mat : t_sl_matrix; wi, wj : natural) return std_logic is
- variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
+ -- map to fixed range
+ variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat;
variable v_result : std_logic := '0';
begin
for I in 0 to wi - 1 loop
@@ -1874,7 +2088,8 @@ package body common_pkg is
if use_g = true then v_lo := v_lo + g_w; end if;
when others => report "Unknown common_pkg func_slv_extract argument" severity FAILURE;
end case;
- return vec(v_w - 1 + v_lo downto v_lo); -- extracted slv
+ -- extracted slv
+ return vec(v_w - 1 + v_lo downto v_lo);
end func_slv_extract;
function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
@@ -1969,10 +2184,12 @@ package body common_pkg is
function TO_UINT(udec : real; w, resolution_w : integer) return natural is
constant c_resolution : real := 1.0 / 2.0**REAL(resolution_w);
- constant c_ureal : real := ROUND(udec / c_resolution); -- rounds away from zero
+ -- rounds away from zero
+ constant c_ureal : real := ROUND(udec / c_resolution);
begin
if udec >= 0.0 then
- return TO_SINT(udec, w + 1, resolution_w); -- w + 1, because unsigned has no sign bit
+ -- w + 1, because unsigned has no sign bit
+ return TO_SINT(udec, w + 1, resolution_w);
else
report "Negative real clipped to integer 0 : " & real'image(c_ureal) & " -- > 0" severity WARNING;
return 0;
@@ -1983,7 +2200,8 @@ package body common_pkg is
constant c_max : real := 2.0**REAL(w - 1) - 1.0;
constant c_min : real := -2.0**REAL(w - 1);
constant c_resolution : real := 1.0 / 2.0**REAL(resolution_w);
- constant c_sreal : real := ROUND(sdec / c_resolution); -- rounds away from zero
+ -- rounds away from zero
+ constant c_sreal : real := ROUND(sdec / c_resolution);
constant c_sint : integer := integer(c_sreal);
begin
if c_sreal >= c_min then
@@ -1991,11 +2209,13 @@ package body common_pkg is
return c_sint;
else
report "REAL clipped to integer max : " & real'image(c_sreal) & " -- > " & integer'image(integer(c_max)) severity WARNING;
- return integer(c_max); -- clip to max
+ -- clip to max
+ return integer(c_max);
end if;
else
report "REAL clipped to integer min : " & real'image(c_sreal) & " -- > " & integer'image(integer(c_min)) severity WARNING;
- return integer(c_min); -- clip to min
+ -- clip to min
+ return integer(c_min);
end if;
end;
@@ -2004,7 +2224,8 @@ package body common_pkg is
constant c_uvec_max : std_logic_vector(w - 1 downto 0) := (others => '1');
constant c_max : real := 2.0**REAL(w) - 1.0;
constant c_resolution : real := 1.0 / 2.0**REAL(resolution_w);
- variable v_ureal : real := ROUND(udec / c_resolution); -- rounds away from zero
+ -- rounds away from zero
+ variable v_ureal : real := ROUND(udec / c_resolution);
-- Convert to uvec
variable v_floor : real := 0.0;
variable v_uvec : std_logic_vector(w - 1 downto 0) := (others => '0');
@@ -2051,7 +2272,8 @@ package body common_pkg is
constant c_max : real := 2.0**REAL(w - 1) - 1.0;
constant c_min : real := -2.0**REAL(w - 1);
constant c_resolution : real := 1.0 / 2.0**REAL(resolution_w);
- constant c_sreal : real := ROUND(sdec / c_resolution); -- rounds away from zero
+ -- rounds away from zero
+ constant c_sreal : real := ROUND(sdec / c_resolution);
-- Convert to positive using TO_UVEC, so if sdec is negative, then
-- negate sdec to have positive c_udec.
constant c_pos : boolean := sdec >= 0.0;
@@ -2066,11 +2288,13 @@ package body common_pkg is
return c_svec(w - 1 downto 0);
else
report "REAL clipped to SVEC max : " & real'image(c_sreal) & " -- > " & real'image(c_max) severity WARNING;
- return c_svec_max; -- clip to max
+ -- clip to max
+ return c_svec_max;
end if;
else
report "REAL clipped to SVEC min : " & real'image(c_sreal) & " -- > " & real'image(c_min) severity WARNING;
- return c_svec_min; -- clip to min
+ -- clip to min
+ return c_svec_min;
end if;
end;
@@ -2127,14 +2351,16 @@ package body common_pkg is
function RESIZE_NUM(u : unsigned; w : natural) return unsigned is
begin
-- left extend with '0' or remove MSbits and keep LS part (= u[w-1:0])
- return resize(u, w); -- same as RESIZE for UNSIGNED
+ -- same as RESIZE for UNSIGNED
+ return resize(u, w);
end;
function RESIZE_NUM(s : signed; w : natural) return signed is
begin
-- extend sign bit or keep LS part
if w > s'length then
- return resize(s, w); -- extend sign bit
+ -- extend sign bit
+ return resize(s, w);
else
-- RESIZE() wraps between -, 0 for negative and 0, + for positive, so it keeps the sign and w-1 LSbits
-- RESIZE_NUM() removes MSbits, so it wraps from + to - and from - to +, and it keeps the w LSbits
@@ -2190,7 +2416,8 @@ package body common_pkg is
begin
-- use NUMERIC_STD to avoid range limitation of 32b INTEGER
-- default approach
- return std_logic_vector(-signed(vec)); -- negate by multiplying by -1
+ -- negate by multiplying by -1
+ return std_logic_vector(-signed(vec));
-- alternative equivalent approach
-- RETURN INCR_UVEC(NOT vec, 1); -- negate by using two complement negate
end;
@@ -2200,15 +2427,19 @@ package body common_pkg is
constant c_max : integer := 2**(w - 1) - 1;
constant c_min : integer := -2**(w - 1);
constant c_vec_w : natural := vec'length;
- variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec; -- independent of vec'RANGE
+ -- independent of vec'RANGE
+ variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_val : std_logic_vector(w - 1 downto 0);
begin
- v_val := v_vec(w - 1 downto 0); -- operate on width w and resize to c_vec_w for return
+ -- operate on width w and resize to c_vec_w for return
+ v_val := v_vec(w - 1 downto 0);
-- use NUMERIC_STD to avoid range limitation of 32b INTEGER
if signed(v_val) = c_min then
- return std_logic_vector(to_signed(c_max, c_vec_w)); -- most negative becomes most positive
+ -- most negative becomes most positive
+ return std_logic_vector(to_signed(c_max, c_vec_w));
else
- return std_logic_vector(RESIZE_NUM(-signed(v_val), c_vec_w)); -- negate by multiplying by -1
+ -- negate by multiplying by -1
+ return std_logic_vector(RESIZE_NUM(-signed(v_val), c_vec_w));
end if;
end;
@@ -2217,10 +2448,12 @@ package body common_pkg is
begin
if dec < 0 then
v_dec := -dec;
- return std_logic_vector(unsigned(vec) - v_dec); -- uses function "-" (L : UNSIGNED, R : NATURAL), there is no function + with R : INTEGER argument
+ -- uses function "-" (L : UNSIGNED, R : NATURAL), there is no function + with R : INTEGER argument
+ return std_logic_vector(unsigned(vec) - v_dec);
else
v_dec := dec;
- return std_logic_vector(unsigned(vec) + v_dec); -- uses function "+" (L : UNSIGNED, R : NATURAL)
+ -- uses function "+" (L : UNSIGNED, R : NATURAL)
+ return std_logic_vector(unsigned(vec) + v_dec);
end if;
end;
@@ -2231,7 +2464,8 @@ package body common_pkg is
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
begin
- return std_logic_vector(signed(vec) + dec); -- uses function "+" (L : SIGNED, R : INTEGER)
+ -- uses function "+" (L : SIGNED, R : INTEGER)
+ return std_logic_vector(signed(vec) + dec);
end;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector is
@@ -2393,28 +2627,34 @@ package body common_pkg is
function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
- return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift)); -- fill zeros from right
+ -- fill zeros from right
+ return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift));
else
- return std_logic_vector(SHIFT_RIGHT(unsigned(vec), shift)); -- fill zeros from left
+ -- fill zeros from left
+ return std_logic_vector(SHIFT_RIGHT(unsigned(vec), shift));
end if;
end;
function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
- return std_logic_vector(SHIFT_LEFT(signed(vec), -shift)); -- same as SHIFT_LEFT for UNSIGNED
+ -- same as SHIFT_LEFT for UNSIGNED
+ return std_logic_vector(SHIFT_LEFT(signed(vec), -shift));
else
- return std_logic_vector(SHIFT_RIGHT(signed(vec), shift)); -- extend sign
+ -- extend sign
+ return std_logic_vector(SHIFT_RIGHT(signed(vec), shift));
end if;
end;
function ROTATE_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
- return std_logic_vector(ROTATE_LEFT(unsigned(vec), -shift)); -- /<-- vec <--\
+ -- /<-- vec <--\
+ return std_logic_vector(ROTATE_LEFT(unsigned(vec), -shift));
-- \---------->/
else
- return std_logic_vector(ROTATE_RIGHT(unsigned(vec), shift)); -- /--> vec -->\
+ -- /--> vec -->\
+ return std_logic_vector(ROTATE_RIGHT(unsigned(vec), shift));
-- \<----------/
end if;
end;
@@ -2439,7 +2679,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ v_res(v_res'high) := not v_res(v_res'high);
return v_res;
end;
@@ -2449,7 +2690,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ -- keep MS part
+ v_res := v_vec(c_vec_w - 1 downto n);
return v_res;
end;
@@ -2459,8 +2701,10 @@ package body common_pkg is
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_trunc := truncate(vec, n); -- first keep MS part
- v_res := RESIZE_UVEC(v_trunc, w); -- then keep LS part or left extend with '0'
+ -- first keep MS part
+ v_trunc := truncate(vec, n);
+ -- then keep LS part or left extend with '0'
+ v_res := RESIZE_UVEC(v_trunc, w);
return v_res;
end;
@@ -2470,8 +2714,10 @@ package body common_pkg is
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_trunc := truncate(vec, n); -- first keep MS part
- v_res := RESIZE_SVEC(v_trunc, w); -- then keep sign bit and LS part or left extend sign bit
+ -- first keep MS part
+ v_trunc := truncate(vec, n);
+ -- then keep sign bit and LS part or left extend sign bit
+ v_res := RESIZE_SVEC(v_trunc, w);
return v_res;
end;
@@ -2480,7 +2726,8 @@ package body common_pkg is
constant c_scale_w : natural := c_vec_w + n;
variable v_res : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
begin
- v_res(c_scale_w - 1 downto n) := vec; -- scale by adding n zero bits at the right
+ -- scale by adding n zero bits at the right
+ v_res(c_scale_w - 1 downto n) := vec;
return v_res;
end;
@@ -2490,8 +2737,10 @@ package body common_pkg is
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_scale(c_scale_w - 1 downto n) := vec; -- first scale by adding n zero bits at the right
- v_res := RESIZE_UVEC(v_scale, w); -- then keep LS part or left extend with '0'
+ -- first scale by adding n zero bits at the right
+ v_scale(c_scale_w - 1 downto n) := vec;
+ -- then keep LS part or left extend with '0'
+ v_res := RESIZE_UVEC(v_scale, w);
return v_res;
end;
@@ -2501,8 +2750,10 @@ package body common_pkg is
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
variable v_res : std_logic_vector(w - 1 downto 0);
begin
- v_scale(c_scale_w - 1 downto n) := vec; -- first scale by adding n zero bits at the right
- v_res := RESIZE_SVEC(v_scale, w); -- then keep LS part or left extend sign bit
+ -- first scale by adding n zero bits at the right
+ v_scale(c_scale_w - 1 downto n) := vec;
+ -- then keep LS part or left extend sign bit
+ v_res := RESIZE_SVEC(v_scale, w);
return v_res;
end;
@@ -2609,50 +2860,63 @@ package body common_pkg is
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
constant c_one : signed(c_in_w - 1 downto 0) := to_signed(1, c_in_w);
- constant c_half : signed(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1); -- = 2**(n-1)
- constant c_max : signed(c_in_w - 1 downto 0) := signed('0' & c_slv1(c_in_w - 2 downto 0)) - c_half; -- = 2**(c_in_w-1)-1 - c_half
+ -- = 2**(n-1)
+ constant c_half : signed(c_in_w - 1 downto 0) := SHIFT_LEFT(c_one, n - 1);
+ -- = 2**(c_in_w-1)-1 - c_half
+ constant c_max : signed(c_in_w - 1 downto 0) := signed('0' & c_slv1(c_in_w - 2 downto 0)) - c_half;
-- When c_out_w = 1, then c_clip = 0, because a 1 bit signed value is -1 or 0
- constant c_clip : signed(c_out_w - 1 downto 0) := signed('0' & c_slv1(c_out_w - 2 downto 0)); -- = 2**(c_out_w-1)-1
+ -- = 2**(c_out_w-1)-1
+ constant c_clip : signed(c_out_w - 1 downto 0) := signed('0' & c_slv1(c_out_w - 2 downto 0));
variable v_in : signed(c_in_w - 1 downto 0);
- constant u_half : unsigned(n - 1 downto 0) := unsigned(std_logic_vector(c_half(n - 1 downto 0))); -- convert to UNSIGNED to compare with u_fraction
+ -- convert to UNSIGNED to compare with u_fraction
+ constant u_half : unsigned(n - 1 downto 0) := unsigned(std_logic_vector(c_half(n - 1 downto 0)));
variable u_fraction : unsigned(n - 1 downto 0);
variable v_out : signed(c_out_w - 1 downto 0);
begin
v_in := signed(vec);
if n > 0 then
if clip = true and v_in > c_max then
- v_out := c_clip; -- Round clip to maximum positive to avoid wrap to negative
+ -- Round clip to maximum positive to avoid wrap to negative
+ v_out := c_clip;
else
if even = false then
-- Round half away
if vec(vec'high) = '0' then
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half + 0, n), c_out_w); -- Round half up for positive
+ -- Round half up for positive
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half + 0, n), c_out_w);
else
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half - 1, n), c_out_w); -- Round half down for negative
+ -- Round half down for negative
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half - 1, n), c_out_w);
end if;
else
-- Round half to even
- v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half, n), c_out_w); -- Round to nearest using floor(vec + 0.5)
+ -- Round to nearest using floor(vec + 0.5)
+ v_out := RESIZE_NUM(SHIFT_RIGHT(v_in + c_half, n), c_out_w);
u_fraction := unsigned(vec(n - 1 downto 0));
- if u_fraction = u_half and v_out(0) = '1' then -- Round half to even, so when odd subtract 1
- v_out := v_out - 1; -- to make v_out even
+ -- Round half to even, so when odd subtract 1
+ if u_fraction = u_half and v_out(0) = '1' then
+ -- to make v_out even
+ v_out := v_out - 1;
end if;
end if;
end if;
else
- v_out := RESIZE_NUM(v_in, c_out_w); -- NOP
+ -- NOP
+ v_out := RESIZE_NUM(v_in, c_out_w);
end if;
return std_logic_vector(v_out);
end;
function s_round(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
begin
- return s_round(vec, n, clip, false); -- no round half to even
+ -- no round half to even
+ return s_round(vec, n, clip, false);
end;
function s_round(vec : std_logic_vector; n : natural) return std_logic_vector is
begin
- return s_round(vec, n, false); -- no round clip
+ -- no round clip
+ return s_round(vec, n, false);
end;
-- for unsigned round half away and round half up are equivalent
@@ -2670,34 +2934,40 @@ package body common_pkg is
function u_round(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
begin
- return u_round(vec, n, clip, false); -- no round half to even
+ -- no round half to even
+ return u_round(vec, n, clip, false);
end;
function u_round(vec : std_logic_vector; n : natural) return std_logic_vector is
begin
- return u_round(vec, n, false); -- no round clip
+ -- no round clip
+ return u_round(vec, n, false);
end;
function u_to_s(u : natural; w : natural) return integer is
- variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32);
begin
return TO_SINT(v_u(w - 1 downto 0));
end;
function s_to_u(s : integer; w : natural) return natural is
- variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32);
begin
return TO_UINT(v_s(w - 1 downto 0));
end;
function u_wrap(u : natural; w : natural) return natural is
- variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32);
begin
return TO_UINT(v_u(w - 1 downto 0));
end;
function s_wrap(s : integer; w : natural) return integer is
- variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
+ variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32);
begin
return TO_SINT(v_s(w - 1 downto 0));
end;
@@ -2730,8 +3000,10 @@ package body common_pkg is
end;
function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector is
- variable v_a : std_logic_vector(a'length - 1 downto 0) := a; -- map a to range [h:0]
- variable v_b : std_logic_vector(a'length - 1 downto 0) := a; -- default b = a
+ -- map a to range [h:0]
+ variable v_a : std_logic_vector(a'length - 1 downto 0) := a;
+ -- default b = a
+ variable v_b : std_logic_vector(a'length - 1 downto 0) := a;
variable vL : natural;
variable vK : natural;
begin
@@ -2747,23 +3019,27 @@ package body common_pkg is
function hton(a : std_logic_vector; sz : natural) return std_logic_vector is
begin
- return hton(a, c_byte_w, sz); -- symbol width w = c_byte_w = 8
+ -- symbol width w = c_byte_w = 8
+ return hton(a, c_byte_w, sz);
end function;
function hton(a : std_logic_vector) return std_logic_vector is
constant c_sz : natural := a'length / c_byte_w;
begin
- return hton(a, c_byte_w, c_sz); -- symbol width w = c_byte_w = 8
+ -- symbol width w = c_byte_w = 8
+ return hton(a, c_byte_w, c_sz);
end function;
function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector is
begin
- return hton(a, sz); -- i.e. ntoh() = hton()
+ -- i.e. ntoh() = hton()
+ return hton(a, sz);
end function;
function ntoh(a : std_logic_vector) return std_logic_vector is
begin
- return hton(a); -- i.e. ntoh() = hton()
+ -- i.e. ntoh() = hton()
+ return hton(a);
end function;
function flip(a : std_logic_vector) return std_logic_vector is
@@ -2825,17 +3101,21 @@ package body common_pkg is
variable vIn : std_logic_vector(a'length - 1 downto 0);
variable vOut : std_logic_vector(a'length - 1 downto 0);
begin
- vIn := a; -- map input vector to h:0 range
- vOut := vIn; -- default leave any unused MSbits the same
+ -- map input vector to h:0 range
+ vIn := a;
+ -- default leave any unused MSbits the same
+ vOut := vIn;
for J in 0 to row - 1 loop
for I in 0 to col - 1 loop
- vOut(J * col + I) := vIn(I * row + J); -- transpose vector, map input index [i*row+j] to output index [j*col+i]
+ -- transpose vector, map input index [i*row+j] to output index [j*col+i]
+ vOut(J * col + I) := vIn(I * row + J);
end loop;
end loop;
return vOut;
end function;
- function transpose(a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
+ -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose(a, row, col : natural) return natural is
variable vI : natural;
variable vJ : natural;
begin
@@ -2844,16 +3124,20 @@ package body common_pkg is
return vJ * col + vI;
end;
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
+ -- Calculate input_w in multiples as close as possible to max_out_w
+ function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is
-- Examples: split_w(256, 8, 32) = 32; split_w(16, 8, 32) = 16; split_w(72, 8, 32) = 18; -- Input_w must be multiple of 2.
variable r: natural;
begin
r := input_w;
- for i in 1 to ceil_log2(input_w) loop -- Useless to divide the number beyond this
+ -- Useless to divide the number beyond this
+ for i in 1 to ceil_log2(input_w) loop
if r <= max_out_w and r >= min_out_w then
return r;
- elsif i = ceil_log2(input_w) then -- last iteration
- return 0; -- Indicates wrong values were used
+ -- last iteration
+ elsif i = ceil_log2(input_w) then
+ -- Indicates wrong values were used
+ return 0;
end if;
r := r / 2;
end loop;
@@ -2952,8 +3236,10 @@ package body common_pkg is
variable v_odd : boolean;
variable v_even : boolean;
begin
- v_odd := (I mod 2 = 1) and (J mod 2 = 1); -- for odd stage at each odd row
- v_even := (I mod 2 = 0) and (J mod 2 = 0); -- for even stage at each even row
+ -- for odd stage at each odd row
+ v_odd := (I mod 2 = 1) and (J mod 2 = 1);
+ -- for even stage at each even row
+ v_even := (I mod 2 = 0) and (J mod 2 = 0);
return v_odd or v_even;
end func_common_reorder2_is_there;
@@ -2983,7 +3269,8 @@ package body common_pkg is
-- for the active two port reorder cells use the setting at index v_K from the select setting array
v_nof_odd_stages := I / 2;
v_nof_even_stages := (I - 1) / 2;
- v_offset := (J - 1) / 2; -- suits both odd stage and even stage
+ -- suits both odd stage and even stage
+ v_offset := (J - 1) / 2;
v_K := v_nof_odd_stages * c_nof_reorder2_per_odd_stage + v_nof_even_stages * c_nof_reorder2_per_even_stage + v_offset;
end if;
return v_K;
@@ -2992,7 +3279,8 @@ package body common_pkg is
-- Get the select setting for the reorder2 cell on stage I and row J in a reorder network with N stages
function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural is
constant c_nof_select : natural := select_arr'length;
- constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
+ -- force range downto 0
+ constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr;
variable v_sel : natural;
variable v_K : integer;
begin
@@ -3007,11 +3295,13 @@ package body common_pkg is
-- Determine the inverse of a reorder network by using two reorder networks in series
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr is
constant c_nof_select : natural := select_arr'length;
- constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
+ -- force range downto 0
+ constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr;
variable v_sel : natural;
variable v_Ki : integer;
variable v_Ii : natural;
- variable v_inverse_arr : t_natural_arr(2 * c_nof_select - 1 downto 0) := (others => 0); -- default set identity for the reorder2 cells in both reorder instances
+ -- default set identity for the reorder2 cells in both reorder instances
+ variable v_inverse_arr : t_natural_arr(2 * c_nof_select - 1 downto 0) := (others => 0);
begin
-- the inverse select consists of inverse_in reorder and inverse_out reorder in series
if N mod 2 = 1 then
@@ -3031,7 +3321,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ -- stage 1 of the inverse_out reorder
+ v_Ki := c_nof_select + K;
v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
diff --git a/libraries/base/common/src/vhdl/common_pulse_delay.vhd b/libraries/base/common/src/vhdl/common_pulse_delay.vhd
index 66ffa0296b87fcc73b80afe230f814cc1e23d0f7..d56a39c8f9111a7255654c0548511ae44b3b5439 100644
--- a/libraries/base/common/src/vhdl/common_pulse_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_delay.vhd
@@ -31,8 +31,10 @@ use work.common_pkg.all;
entity common_pulse_delay is
generic (
- g_pulse_delay_max : natural; -- Maximum delay value desired by user; determines internal counter width.
- g_register_out : boolean -- TRUE adds output register, adding 1 cycle of delay to the pulse_delay setting.
+ -- Maximum delay value desired by user; determines internal counter width.
+ g_pulse_delay_max : natural;
+ -- TRUE adds output register, adding 1 cycle of delay to the pulse_delay setting.
+ g_register_out : boolean
);
port (
clk : in std_logic;
@@ -85,7 +87,8 @@ begin
port map (
clk => clk,
rst => rst,
- cnt_ld => pulse_in, -- Clear (load "1") the counter on every pulse_in
+ -- Clear (load "1") the counter on every pulse_in
+ cnt_ld => pulse_in,
cnt_en => common_counter_cnt_en,
load => TO_UVEC(1, c_pulse_delay_max_width),
count => common_counter_count
@@ -97,8 +100,10 @@ begin
-- Store the control setting
nxt_pulse_delay_reg <= pulse_delay when pulse_in = '1' else pulse_delay_reg;
- nxt_pulse_out <= pulse_in when pulse_delay = TO_UVEC(0, c_pulse_delay_max_width) else -- 0 cycles delay (pulse_delay_reg not valid yet; using pulse_delay)
- '1' when common_counter_count = pulse_delay_reg else '0'; -- >=1 cycles delay (so pulse_delay_reg will contain registered pulse_delay)
+ -- 0 cycles delay (pulse_delay_reg not valid yet; using pulse_delay)
+ nxt_pulse_out <= pulse_in when pulse_delay = TO_UVEC(0, c_pulse_delay_max_width) else
+ -- >=1 cycles delay (so pulse_delay_reg will contain registered pulse_delay)
+ '1' when common_counter_count = pulse_delay_reg else '0';
-------------------------------------------------------------------------------
-- Optional output register
diff --git a/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd b/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
index f4e02fa89d7abea93b3391c150b08aa2e35abee7..bce57426f2ad5cc96dabd9ef075e9758130ba260 100644
--- a/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
@@ -33,8 +33,10 @@ use common_lib.common_mem_pkg.all;
entity common_pulse_delay_reg is
generic (
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and pulse_clk are the same, else use TRUE to cross the clock domain
- g_pulse_delay_max : natural := 0 -- Maximum number of clk cycles that pulse can be delayed
+ -- use FALSE when mm_clk and pulse_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
+ -- Maximum number of clk cycles that pulse can be delayed
+ g_pulse_delay_max : natural := 0
);
port (
pulse_clk : in std_logic;
@@ -85,18 +87,22 @@ begin
when 0 =>
-- Write pulse_delay
mm_pulse_delay <= sla_in.wrdata(ceil_log2(g_pulse_delay_max) - 1 downto 0);
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
when 0 =>
-- Read back pulse_delay
sla_out.rddata(ceil_log2(g_pulse_delay_max) - 1 downto 0) <= mm_pulse_delay;
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
end if;
end if;
@@ -118,9 +124,11 @@ begin
-- be on the save side) and only use a crossing component for the word
-- signals if it is necessary (to avoid using more logic than necessary).
------------------------------------------------------------------------------
- no_common_reg_cross_domain : if g_cross_clock_domain = false generate -- so mm_clk = pulse_clk
+ -- so mm_clk = pulse_clk
+ no_common_reg_cross_domain : if g_cross_clock_domain = false generate
pulse_delay <= mm_pulse_delay;
- end generate; -- common_reg_cross_domain
+ -- common_reg_cross_domain
+ end generate;
gen_common_reg_cross_domain : if g_cross_clock_domain = true generate
u_common_reg_cross_domain : entity work.common_reg_cross_domain
@@ -134,6 +142,7 @@ begin
out_dat => pulse_delay,
out_new => open
);
- end generate; -- gen_common_reg_cross_domain
+ -- gen_common_reg_cross_domain
+ end generate;
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_pulse_extend.vhd b/libraries/base/common/src/vhdl/common_pulse_extend.vhd
index 23b38e1ebf0c4f404cd18e126280c803865b4914..900c34d15fce5349c65e9cd5fb18e6e89333d071 100644
--- a/libraries/base/common/src/vhdl/common_pulse_extend.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_extend.vhd
@@ -36,7 +36,8 @@ entity common_pulse_extend is
g_p_in_level : std_logic := '1';
g_ep_out_level : std_logic := '1';
g_extend_w : natural := 1;
- g_nof_cycles : natural := 1 -- 1 = use maximum determined by g_extend_w
+ -- 1 = use maximum determined by g_extend_w
+ g_nof_cycles : natural := 1
);
port (
rst : in std_logic := '0';
diff --git a/libraries/base/common/src/vhdl/common_pulser.vhd b/libraries/base/common/src/vhdl/common_pulser.vhd
index 5100346bb59a6726d1cc421478d65f3a9a367455..2edf7bf63d749d66a510d52aa80a16e3e7752b38 100644
--- a/libraries/base/common/src/vhdl/common_pulser.vhd
+++ b/libraries/base/common/src/vhdl/common_pulser.vhd
@@ -37,16 +37,20 @@ use common_lib.common_pkg.all;
-- . g_pulse_phase=g_pulse_period-N : first pulse after N cycles
entity common_pulser is
generic (
- g_pulse_period : natural := 25000; -- nof clk cycles to get pulse period
+ -- nof clk cycles to get pulse period
+ g_pulse_period : natural := 25000;
g_pulse_phase : natural := 0
);
port (
rst : in std_logic;
clk : in std_logic;
- clken : in std_logic := '1'; -- support running on clken freq
+ -- support running on clken freq
+ clken : in std_logic := '1';
pulse_period : in std_logic_vector(ceil_log2(g_pulse_period + 1) - 1 downto 0) := TO_UVEC(g_pulse_period, ceil_log2(g_pulse_period + 1));
- pulse_en : in std_logic := '1'; -- enable the pulse interval timer
- pulse_clr : in std_logic := '0'; -- restart the pulse interval timer
+ -- enable the pulse interval timer
+ pulse_en : in std_logic := '1';
+ -- restart the pulse interval timer
+ pulse_clr : in std_logic := '0';
pulse_out : out std_logic
);
end common_pulser;
diff --git a/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd b/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
index 0afbe95fb9133a89cdcb03bb99ac462450ea5fda..3b75f60f41b515ade1cf8371a0036d1a8c77727e 100644
--- a/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
+++ b/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
@@ -28,31 +28,43 @@ use common_lib.common_pkg.all;
entity common_pulser_us_ms_s is
generic (
- g_pulse_us : natural := 125; -- nof clk cycles to get us period
- g_pulse_ms : natural := 1000; -- nof pulse_us pulses to get ms period
- g_pulse_s : natural := 1000 -- nof pulse_ms pulses to get s period
+ -- nof clk cycles to get us period
+ g_pulse_us : natural := 125;
+ -- nof pulse_us pulses to get ms period
+ g_pulse_ms : natural := 1000;
+ -- nof pulse_ms pulses to get s period
+ g_pulse_s : natural := 1000
);
port (
rst : in std_logic;
clk : in std_logic;
sync : in std_logic := '0';
- pulse_us : out std_logic; -- pulses after every g_pulse_us clock cycles
- pulse_ms : out std_logic; -- pulses after every g_pulse_us*g_pulse_ms clock cycles
- pulse_s : out std_logic -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
+ -- pulses after every g_pulse_us clock cycles
+ pulse_us : out std_logic;
+ -- pulses after every g_pulse_us*g_pulse_ms clock cycles
+ pulse_ms : out std_logic;
+ -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
+ pulse_s : out std_logic
);
end common_pulser_us_ms_s;
architecture str of common_pulser_us_ms_s is
- signal pulse_us_pp : std_logic; -- register to align with pulse_ms
- signal pulse_us_p : std_logic; -- register to align with pulse_s
- signal pulse_us_reg : std_logic; -- output register
+ -- register to align with pulse_ms
+ signal pulse_us_pp : std_logic;
+ -- register to align with pulse_s
+ signal pulse_us_p : std_logic;
+ -- output register
+ signal pulse_us_reg : std_logic;
signal i_pulse_us : std_logic;
- signal pulse_ms_p : std_logic; -- register to align with pulse_s
- signal pulse_ms_reg : std_logic; -- output register
+ -- register to align with pulse_s
+ signal pulse_ms_p : std_logic;
+ -- output register
+ signal pulse_ms_reg : std_logic;
signal i_pulse_ms : std_logic;
- signal pulse_s_reg : std_logic; -- output register
+ -- output register
+ signal pulse_s_reg : std_logic;
signal i_pulse_s : std_logic;
begin
-- register output pulses to ease timing closure
diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
index b2a595644f4227a84650c31fb80f51690131f4b9..637425c180bec4e47939f9af8881e8b45d31a63d 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
@@ -27,8 +27,10 @@ use technology_lib.technology_select_pkg.all;
entity common_ram_cr_cw_ratio is
generic (
g_technology : natural := c_tech_select_default;
- g_ram_wr : t_c_mem := c_mem_ram; -- settings for port a
- g_ram_rd : t_c_mem := c_mem_ram; -- data width and address range for port b
+ -- settings for port a
+ g_ram_wr : t_c_mem := c_mem_ram;
+ -- data width and address range for port b
+ g_ram_rd : t_c_mem := c_mem_ram;
g_init_file : string := "UNUSED"
);
port (
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
index acdfa0d2196449f5df82793998de66d4e9972299..dda12abe8aa668c219c55e61358d7e256cd55e42 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
@@ -55,8 +55,10 @@ entity common_ram_crw_crw is
end common_ram_crw_crw;
architecture str of common_ram_crw_crw is
- constant c_rd_latency : natural := sel_a_b(g_ram.latency < 2, g_ram.latency, 2); -- handle read latency 1 or 2 in RAM
- constant c_pipeline : natural := sel_a_b(g_ram.latency > c_rd_latency, g_ram.latency - c_rd_latency, 0); -- handle rest of read latency > 2 in pipeline
+ -- handle read latency 1 or 2 in RAM
+ constant c_rd_latency : natural := sel_a_b(g_ram.latency < 2, g_ram.latency, 2);
+ -- handle rest of read latency > 2 in pipeline
+ constant c_pipeline : natural := sel_a_b(g_ram.latency > c_rd_latency, g_ram.latency - c_rd_latency, 0);
-- Intermediate signal for extra pipelining
signal ram_rd_dat_a : std_logic_vector(rd_dat_a'range);
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
index c9930f48926ce557ab8fe1ff32714b7b1c50df1a..e9b5c898a374239ab6dc0a05be26715fd87b64b1 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
@@ -28,8 +28,10 @@ use technology_lib.technology_select_pkg.all;
entity common_ram_crw_crw_ratio is
generic (
g_technology : natural := c_tech_select_default;
- g_ram_a : t_c_mem := c_mem_ram; -- settings for port a
- g_ram_b : t_c_mem := c_mem_ram; -- data width and address range for port b
+ -- settings for port a
+ g_ram_a : t_c_mem := c_mem_ram;
+ -- data width and address range for port b
+ g_ram_b : t_c_mem := c_mem_ram;
g_init_file : string := "UNUSED"
);
port (
@@ -55,10 +57,13 @@ entity common_ram_crw_crw_ratio is
end common_ram_crw_crw_ratio;
architecture str of common_ram_crw_crw_ratio is
- constant c_ram : t_c_mem := g_ram_a; -- use shared parameters from port a parameter
+ -- use shared parameters from port a parameter
+ constant c_ram : t_c_mem := g_ram_a;
- constant c_rd_latency : natural := sel_a_b(c_ram.latency < 2, c_ram.latency, 2); -- handle read latency 1 or 2 in RAM
- constant c_pipeline : natural := sel_a_b(c_ram.latency > c_rd_latency, c_ram.latency - c_rd_latency, 0); -- handle rest of read latency > 2 in pipeline
+ -- handle read latency 1 or 2 in RAM
+ constant c_rd_latency : natural := sel_a_b(c_ram.latency < 2, c_ram.latency, 2);
+ -- handle rest of read latency > 2 in pipeline
+ constant c_pipeline : natural := sel_a_b(c_ram.latency > c_rd_latency, c_ram.latency - c_rd_latency, 0);
-- Intermediate signal for extra pipelining
signal ram_rd_dat_a : std_logic_vector(rd_dat_a'range);
diff --git a/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd b/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
index 84e56f935c2a68e0df66662259b81b45ba48ab43..3e0af8e5d86a0dd69cf00b9acbd0cd1b8f91eab6 100644
--- a/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
@@ -40,19 +40,23 @@ use work.common_mem_pkg.all;
entity common_reg_cross_domain is
generic (
g_input_buf : boolean := true;
- g_in_new_latency : natural := 0; -- >= 0
+ -- >= 0
+ g_in_new_latency : natural := 0;
g_out_dat_init : std_logic_vector(c_mem_reg_init_w - 1 downto 0) := (others => '0')
);
port (
in_rst : in std_logic;
in_clk : in std_logic;
- in_new : in std_logic := '1'; -- when '1' then new in_dat is available after g_in_new_latency
+ -- when '1' then new in_dat is available after g_in_new_latency
+ in_new : in std_logic := '1';
in_dat : in std_logic_vector;
- in_done : out std_logic; -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done : out std_logic;
out_rst : in std_logic;
out_clk : in std_logic;
out_dat : out std_logic_vector;
- out_new : out std_logic -- when '1' then the out_dat was updated with in_dat due to in_new
+ -- when '1' then the out_dat was updated with in_dat due to in_new
+ out_new : out std_logic
);
end common_reg_cross_domain;
@@ -85,7 +89,8 @@ architecture rtl of common_reg_cross_domain is
-- out_clk domain
------------------------------------------------------------------------------
signal out_en : std_logic;
- signal i_out_dat : std_logic_vector(c_dat'range) := c_dat; -- register init without physical reset
+ -- register init without physical reset
+ signal i_out_dat : std_logic_vector(c_dat'range) := c_dat;
signal nxt_out_dat : std_logic_vector(c_dat'range);
begin
out_dat <= i_out_dat;
@@ -127,7 +132,8 @@ begin
-- capture the new register data
no_in_buf : if g_input_buf = false generate
- in_buf <= in_dat; -- assumes that in_dat remains unchanged during the crossing of in_new to out_en
+ -- assumes that in_dat remains unchanged during the crossing of in_new to out_en
+ in_buf <= in_dat;
end generate;
gen_in_buf : if g_input_buf = true generate
@@ -150,9 +156,11 @@ begin
cross_req <= '1';
nxt_state <= s_busy;
elsif unsigned(reg_new) = 0 and prev_state = s_busy then
- nxt_in_done <= '1'; -- no pending in_new at input or in shift register and just left s_busy, so signal in_done
+ -- no pending in_new at input or in shift register and just left s_busy, so signal in_done
+ nxt_in_done <= '1';
end if;
- when others => -- s_busy
+ -- s_busy
+ when others =>
if reg_new(g_in_new_latency) = '1' then
nxt_in_new_hold <= '1';
end if;
diff --git a/libraries/base/common/src/vhdl/common_reg_r_w.vhd b/libraries/base/common/src/vhdl/common_reg_r_w.vhd
index f58ac2c3b00cdd510b8e66cf4c204ea9fe6261fd..1b032b49c0640857a984b3b892126dd5aadb5f0e 100644
--- a/libraries/base/common/src/vhdl/common_reg_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_r_w.vhd
@@ -82,7 +82,8 @@ end common_reg_r_w;
architecture rtl of common_reg_r_w is
constant c_rd_latency : natural := 1;
constant c_pipeline : natural := g_reg.latency - c_rd_latency;
- constant c_pipe_dat_w : natural := 1 + g_reg.dat_w; -- pipeline rd_val & rd_dat together
+ -- pipeline rd_val & rd_dat together
+ constant c_pipe_dat_w : natural := 1 + g_reg.dat_w;
type t_reg_arr is array (integer range <>) of std_logic_vector(g_reg.dat_w - 1 downto 0);
@@ -153,7 +154,8 @@ begin
p_control : process (rd_en, int_rd_dat, rd_adr, in_reg, i_out_reg, wr_adr, wr_en, wr_dat)
begin
- nxt_rd_val <= rd_en; -- rd_val depends only on rd_en, so for an out of range address the old rd_dat is output
+ -- rd_val depends only on rd_en, so for an out of range address the old rd_dat is output
+ nxt_rd_val <= rd_en;
nxt_reg_rd_arr <= (others => '0');
nxt_rd_dat <= int_rd_dat;
diff --git a/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd b/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
index 63e5a8a45f785fbcf29bfdfeb5bd1d10de4eb889..56af1f96fac208caeabb499cc39c61ca1a511b51 100644
--- a/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
@@ -58,23 +58,32 @@ use work.common_mem_pkg.all;
entity common_reg_r_w_dc is
generic (
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_in_new_latency : natural := 0; -- >= 0
- g_readback : boolean := false; -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
+ -- >= 0
+ g_in_new_latency : natural := 0;
+ -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+ g_readback : boolean := false;
--g_readback : BOOLEAN := TRUE; -- can use TRUE for write and readback register
g_reg : t_c_mem := c_mem_reg;
g_init_reg : std_logic_vector(c_mem_reg_init_w - 1 downto 0) := (others => '0')
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by g_reg
- sla_out : out t_mem_miso; -- actual ranges defined by g_reg
+ -- actual ranges defined by g_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by g_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
reg_wr_arr : out std_logic_vector( g_reg.nof_dat - 1 downto 0);
@@ -82,7 +91,8 @@ entity common_reg_r_w_dc is
in_new : in std_logic := '1';
in_reg : in std_logic_vector(g_reg.dat_w * g_reg.nof_dat - 1 downto 0);
out_reg : out std_logic_vector(g_reg.dat_w * g_reg.nof_dat - 1 downto 0);
- out_new : out std_logic -- Pulses '1' when new data has been written.
+ -- Pulses '1' when new data has been written.
+ out_new : out std_logic
);
end common_reg_r_w_dc;
@@ -153,7 +163,8 @@ begin
reg_wr_arr <= vector_wr_arr;
reg_rd_arr <= vector_rd_arr;
out_new <= vector_wr_arr(0);
- end generate; -- no_cross
+ -- no_cross
+ end generate;
gen_cross : if g_cross_clock_domain = true generate
gen_rdback : if g_readback = true generate
@@ -236,5 +247,6 @@ begin
);
end generate;
- end generate; -- gen_cross
+ -- gen_cross
+ end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_reinterleave.vhd b/libraries/base/common/src/vhdl/common_reinterleave.vhd
index af7766e68e562ad2f6d8ce40eeb6e64249340bce..2617aed70da03aadb90828488a2c966b670eff00 100644
--- a/libraries/base/common/src/vhdl/common_reinterleave.vhd
+++ b/libraries/base/common/src/vhdl/common_reinterleave.vhd
@@ -226,7 +226,8 @@ begin
clk => clk,
in_dat => inter_in_concat_dat_arr(i),
- in_val => inter_in_concat_val_arr(i)(0), -- All input streams are valid at the same time.
+ -- All input streams are valid at the same time.
+ in_val => inter_in_concat_val_arr(i)(0),
out_dat => inter_out_dat_arr(i),
out_val => inter_out_val(i)
diff --git a/libraries/base/common/src/vhdl/common_reorder_symbol.vhd b/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
index a3bcf0c3c6197039c53a3c0b602214b64311ac37..2c1aa779c692dc2647c4d694faacbbdd550b1246 100644
--- a/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
@@ -91,9 +91,12 @@ entity common_reorder_symbol is
g_nof_input : natural := 4;
g_nof_output : natural := 4;
g_symbol_w : natural := 16;
- g_select_w : natural := 2; -- fixed 2 bit per X select
- g_nof_select : natural := 6; -- size must match c_N*(c_N-1)/2
- g_pipeline_arr : t_natural_arr := array_init(0, 5) -- range must fit [0:c_N]
+ -- fixed 2 bit per X select
+ g_select_w : natural := 2;
+ -- size must match c_N*(c_N-1)/2
+ g_nof_select : natural := 6;
+ -- range must fit [0:c_N]
+ g_pipeline_arr : t_natural_arr := array_init(0, 5)
);
port (
rst : in std_logic;
@@ -108,24 +111,34 @@ entity common_reorder_symbol is
in_select : in std_logic_vector(g_nof_select * g_select_w - 1 downto 0);
out_data : out std_logic_vector(g_nof_output * g_symbol_w - 1 downto 0);
- out_val : out std_logic; -- pipelined in_val
- out_sop : out std_logic; -- pipelined in_sop
- out_eop : out std_logic; -- pipelined in_eop
- out_sync : out std_logic -- pipelined in_sync
+ -- pipelined in_val
+ out_val : out std_logic;
+ -- pipelined in_sop
+ out_sop : out std_logic;
+ -- pipelined in_eop
+ out_eop : out std_logic;
+ -- pipelined in_sync
+ out_sync : out std_logic
);
end common_reorder_symbol;
architecture rtl of common_reorder_symbol is
- constant c_N : natural := largest(g_nof_input, g_nof_output); -- nof stages of the reorder network
+ -- nof stages of the reorder network
+ constant c_N : natural := largest(g_nof_input, g_nof_output);
- constant c_pipeline_arr : t_natural_arr(0 to c_N) := g_pipeline_arr; -- force range [0:c_N]
+ -- force range [0:c_N]
+ constant c_pipeline_arr : t_natural_arr(0 to c_N) := g_pipeline_arr;
constant c_total_pipeline : natural := func_sum(c_pipeline_arr);
- constant c_nof_reorder2_total : natural := c_N * (c_N - 1) / 2; -- = g_nof_select
+ -- = g_nof_select
+ constant c_nof_reorder2_total : natural := c_N * (c_N - 1) / 2;
- type t_symbol_arr is array (integer range <>) of std_logic_vector(g_symbol_w - 1 downto 0); -- one stage
- type t_symbol_2arr is array (integer range <>) of t_symbol_arr(c_N downto - 1); -- all stages
- type t_select_2arr is array (integer range <>) of t_natural_arr(g_nof_select - 1 downto 0); -- all stages
+ -- one stage
+ type t_symbol_arr is array (integer range <>) of std_logic_vector(g_symbol_w - 1 downto 0);
+ -- all stages
+ type t_symbol_2arr is array (integer range <>) of t_symbol_arr(c_N downto - 1);
+ -- all stages
+ type t_select_2arr is array (integer range <>) of t_natural_arr(g_nof_select - 1 downto 0);
-- Perform the basic two port reorder cell function, see description section for explanation
function func_reorder2(data : t_symbol_arr(1 downto 0); sel : natural) return t_symbol_arr is
diff --git a/libraries/base/common/src/vhdl/common_requantize.vhd b/libraries/base/common/src/vhdl/common_requantize.vhd
index e60f590d7815b90b0e1557ba8c46ce476d4bf25a..cf64b25e10f4cc4d8fd4c023f3c5826bdf161c74 100644
--- a/libraries/base/common/src/vhdl/common_requantize.vhd
+++ b/libraries/base/common/src/vhdl/common_requantize.vhd
@@ -53,28 +53,43 @@ use work.common_pkg.all;
entity common_requantize is
generic (
- g_representation : string := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
- g_lsb_w : integer := 4; -- when > 0, number of LSbits to remove from in_dat
+ -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
+ g_representation : string := "SIGNED";
+ -- when > 0, number of LSbits to remove from in_dat
+ g_lsb_w : integer := 4;
-- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
-- when 0 then no effect
- g_lsb_round : boolean := true; -- when TRUE round else truncate the input LSbits
- g_lsb_round_clip : boolean := false; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
- g_lsb_round_even : boolean := true; -- when TRUE round half to even, else round half away from zero
- g_msb_clip : boolean := true; -- when TRUE CLIP else WRAP the input MSbits
- g_msb_clip_symmetric : boolean := false; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
+ -- when TRUE round else truncate the input LSbits
+ g_lsb_round : boolean := true;
+ -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
+ g_lsb_round_clip : boolean := false;
+ -- when TRUE round half to even, else round half away from zero
+ g_lsb_round_even : boolean := true;
+ -- when TRUE CLIP else WRAP the input MSbits
+ g_msb_clip : boolean := true;
+ -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
+ g_msb_clip_symmetric : boolean := false;
-- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
- g_gain_w : natural := 0; -- do not use, must be 0, use negative g_lsb_w instead
- g_pipeline_remove_lsb : natural := 0; -- >= 0
- g_pipeline_remove_msb : natural := 0; -- >= 0, use g_pipeline_remove_lsb=0 and g_pipeline_remove_msb=0 for combinatorial output
- g_in_dat_w : natural := 36; -- input data width
- g_out_dat_w : natural := 18 -- output data width
+ -- do not use, must be 0, use negative g_lsb_w instead
+ g_gain_w : natural := 0;
+ -- >= 0
+ g_pipeline_remove_lsb : natural := 0;
+ -- >= 0, use g_pipeline_remove_lsb=0 and g_pipeline_remove_msb=0 for combinatorial output
+ g_pipeline_remove_msb : natural := 0;
+ -- input data width
+ g_in_dat_w : natural := 36;
+ -- output data width
+ g_out_dat_w : natural := 18
);
port (
clk : in std_logic;
clken : in std_logic := '1';
- in_dat : in std_logic_vector; -- unconstrained slv to also support widths other than g_in_dat_w by only using [g_in_dat_w-1:0] from the in_dat slv
- out_dat : out std_logic_vector; -- unconstrained slv to also support widths other then g_out_dat_w by resizing the result [g_out_dat_w-1:0] to the out_dat slv
- out_ovr : out std_logic -- out_ovr is '1' when the removal of MSbits causes clipping or wrapping
+ -- unconstrained slv to also support widths other than g_in_dat_w by only using [g_in_dat_w-1:0] from the in_dat slv
+ in_dat : in std_logic_vector;
+ -- unconstrained slv to also support widths other then g_out_dat_w by resizing the result [g_out_dat_w-1:0] to the out_dat slv
+ out_dat : out std_logic_vector;
+ -- out_ovr is '1' when the removal of MSbits causes clipping or wrapping
+ out_ovr : out std_logic
);
end;
@@ -85,10 +100,13 @@ architecture str of common_requantize is
constant c_rem_dat_w : natural := g_in_dat_w - c_lsb_w;
- signal rem_dat : std_logic_vector(c_rem_dat_w - 1 downto 0); -- remaining in_dat after removing the c_lsb_w number of LSBits
- signal res_dat : std_logic_vector(g_out_dat_w - 1 downto 0); -- resulting out_dat after removing the g_msb_w number of MSBits
+ -- remaining in_dat after removing the c_lsb_w number of LSBits
+ signal rem_dat : std_logic_vector(c_rem_dat_w - 1 downto 0);
+ -- resulting out_dat after removing the g_msb_w number of MSBits
+ signal res_dat : std_logic_vector(g_out_dat_w - 1 downto 0);
- signal gain_dat : std_logic_vector(g_out_dat_w + c_gain_w - 1 downto 0) := (others => '0'); -- fill extra LSBits with '0' instead of extending MSbits
+ -- fill extra LSBits with '0' instead of extending MSbits
+ signal gain_dat : std_logic_vector(g_out_dat_w + c_gain_w - 1 downto 0) := (others => '0');
begin
assert g_gain_w = 0 report "common_requantize: must use g_gain_w = 0, because gain is now supported via negative g_lsb_w." severity FAILURE;
diff --git a/libraries/base/common/src/vhdl/common_resize.vhd b/libraries/base/common/src/vhdl/common_resize.vhd
index 04ae5e8e6d7e24e1b028e370d9eb5384af5e3686..dae11e04bf3b09248006cbc0f3a936accf76859e 100644
--- a/libraries/base/common/src/vhdl/common_resize.vhd
+++ b/libraries/base/common/src/vhdl/common_resize.vhd
@@ -26,12 +26,17 @@ use work.common_pkg.all;
entity common_resize is
generic (
- g_representation : string := "SIGNED"; -- SIGNED or UNSIGNED resizing
- g_clip : boolean := false; -- when TRUE clip input if it is outside the output range, else wrap
- g_clip_symmetric : boolean := false; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
+ -- SIGNED or UNSIGNED resizing
+ g_representation : string := "SIGNED";
+ -- when TRUE clip input if it is outside the output range, else wrap
+ g_clip : boolean := false;
+ -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
+ g_clip_symmetric : boolean := false;
-- for wrapping when g_clip=FALSE the g_clip_symmetric is ignored, so signed wrapping is done asymmetric
- g_pipeline_input : natural := 0; -- >= 0
- g_pipeline_output : natural := 1; -- >= 0
+ -- >= 0
+ g_pipeline_input : natural := 0;
+ -- >= 0
+ g_pipeline_output : natural := 1;
g_in_dat_w : integer := 36;
g_out_dat_w : integer := 18
);
@@ -49,10 +54,14 @@ architecture rtl of common_resize is
constant c_clip : boolean := g_clip and (g_out_dat_w < g_in_dat_w);
-- Use SIGNED, UNSIGNED to avoid NATURAL (32 bit range) overflow error
- constant c_umax : unsigned(out_dat'range) := unsigned( c_slv1(g_out_dat_w - 1 downto 0)); -- = 2** g_out_dat_w -1
- constant c_smax : signed(out_dat'range) := signed('0' & c_slv1(g_out_dat_w - 2 downto 0)); -- = 2**(g_out_dat_w-1)-1
- constant c_smin_most : signed(out_dat'range) := signed('1' & c_slv0(g_out_dat_w - 2 downto 0)); -- = -2**(c_in_dat_w-1)
- constant c_smin_symm : signed(out_dat'range) := -c_smax; -- = -2**(c_in_dat_w-1)+1
+ -- = 2** g_out_dat_w -1
+ constant c_umax : unsigned(out_dat'range) := unsigned( c_slv1(g_out_dat_w - 1 downto 0));
+ -- = 2**(g_out_dat_w-1)-1
+ constant c_smax : signed(out_dat'range) := signed('0' & c_slv1(g_out_dat_w - 2 downto 0));
+ -- = -2**(c_in_dat_w-1)
+ constant c_smin_most : signed(out_dat'range) := signed('1' & c_slv0(g_out_dat_w - 2 downto 0));
+ -- = -2**(c_in_dat_w-1)+1
+ constant c_smin_symm : signed(out_dat'range) := -c_smax;
constant c_smin : signed(out_dat'range) := sel_a_b(g_clip_symmetric, c_smin_symm, c_smin_most);
signal reg_dat : std_logic_vector(in_dat'range);
@@ -64,7 +73,8 @@ architecture rtl of common_resize is
signal res_vec : std_logic_vector(g_out_dat_w downto 0);
signal out_vec : std_logic_vector(g_out_dat_w downto 0);
begin
- u_input_pipe : entity work.common_pipeline -- pipeline input
+ -- pipeline input
+ u_input_pipe : entity work.common_pipeline
generic map (
g_representation => "SIGNED",
g_pipeline => g_pipeline_input,
@@ -114,7 +124,8 @@ begin
res_vec <= res_ovr & res_dat;
- u_output_pipe : entity work.common_pipeline -- pipeline output
+ -- pipeline output
+ u_output_pipe : entity work.common_pipeline
generic map (
g_representation => "SIGNED",
g_pipeline => g_pipeline_output,
diff --git a/libraries/base/common/src/vhdl/common_reverse_n_data.vhd b/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
index 783c41fe81b80a148ad6234c1c93734d06a68e4a..6ae1d3e9cc40b67f612b449e499810abdbc67afd 100644
--- a/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
+++ b/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
@@ -51,9 +51,11 @@ use work.common_pkg.all;
entity common_reverse_n_data is
generic (
-- Pipeline: 0 for combinatorial, > 0 for registers
- g_pipeline_demux_in : natural := 1; -- serial to parallel demux
+ -- serial to parallel demux
+ g_pipeline_demux_in : natural := 1;
g_pipeline_demux_out : natural := 0;
- g_pipeline_mux_in : natural := 0; -- parallel to serial mux
+ -- parallel to serial mux
+ g_pipeline_mux_in : natural := 0;
g_pipeline_mux_out : natural := 1;
g_reverse_len : natural := 2;
g_data_w : natural := 16
@@ -241,6 +243,7 @@ begin
in_val => reverse_val,
out_dat => out_data,
- out_val => out_val -- = in_val delayed by c_pipeline_total
+ -- = in_val delayed by c_pipeline_total
+ out_val => out_val
);
end str;
diff --git a/libraries/base/common/src/vhdl/common_rl_decrease.vhd b/libraries/base/common/src/vhdl/common_rl_decrease.vhd
index 41fa78b5592b069f56ad68357d26dd59ed469649..09021323120f10888b445d142492be6ed5e9b343 100644
--- a/libraries/base/common/src/vhdl/common_rl_decrease.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_decrease.vhd
@@ -33,7 +33,8 @@ use IEEE.std_logic_1164.all;
entity common_rl_decrease is
generic (
- g_adapt : boolean := true; -- default when TRUE then decrease sink RL 1 to source RL 0, else then implement wires
+ -- default when TRUE then decrease sink RL 1 to source RL 0, else then implement wires
+ g_adapt : boolean := true;
g_dat_w : natural := 18
);
port (
@@ -52,7 +53,8 @@ end common_rl_decrease;
architecture rtl of common_rl_decrease is
-- Internally use streaming record for the SOSI, for the SISO.ready directly use src_in_ready
- type t_sosi is record -- Source Out or Sink In
+ -- Source Out or Sink In
+ type t_sosi is record
data : std_logic_vector(g_dat_w - 1 downto 0);
valid : std_logic;
end record;
@@ -117,7 +119,8 @@ begin
nxt_buf <= buf;
if src_in_ready = '1' then
nxt_buf(0) <= buf(1);
- nxt_buf(1).valid <= '0'; -- not strictly necessary, but robust
+ -- not strictly necessary, but robust
+ nxt_buf(1).valid <= '0';
end if;
-- Put input data at the first available location dependent on src_in_ready, no need to explicitly check snk_in_val
diff --git a/libraries/base/common/src/vhdl/common_rl_increase.vhd b/libraries/base/common/src/vhdl/common_rl_increase.vhd
index 43f002b9f52d79aa5edfe7446f93a04c2d66ad3c..4e6c8050d646f20e5435c264c952be9779c0a95c 100644
--- a/libraries/base/common/src/vhdl/common_rl_increase.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_increase.vhd
@@ -38,19 +38,23 @@ use IEEE.std_logic_1164.all;
entity common_rl_increase is
generic (
- g_adapt : boolean := true; -- default when TRUE then increase sink RL 0 to source RL 1, else then implement wires
- g_hold_dat_en : boolean := true; -- default when TRUE hold the src_out_dat until the next active src_out_val, else just pass on snk_in_dat as wires
+ -- default when TRUE then increase sink RL 0 to source RL 1, else then implement wires
+ g_adapt : boolean := true;
+ -- default when TRUE hold the src_out_dat until the next active src_out_val, else just pass on snk_in_dat as wires
+ g_hold_dat_en : boolean := true;
g_dat_w : natural := 18
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sink
- snk_out_ready : out std_logic; -- sink RL = 0
+ -- sink RL = 0
+ snk_out_ready : out std_logic;
snk_in_dat : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X');
snk_in_val : in std_logic := 'X';
-- Source
- src_in_ready : in std_logic; -- source RL = 1
+ -- source RL = 1
+ src_in_ready : in std_logic;
src_out_dat : out std_logic_vector(g_dat_w - 1 downto 0);
src_out_val : out std_logic
);
@@ -82,7 +86,8 @@ begin
end process;
-- SISO
- snk_out_ready <= ready_reg; -- Adjust ready latency
+ -- Adjust ready latency
+ snk_out_ready <= ready_reg;
-- SOSI
hold_val <= snk_in_val and ready_reg;
diff --git a/libraries/base/common/src/vhdl/common_rl_register.vhd b/libraries/base/common/src/vhdl/common_rl_register.vhd
index 1a4f287ddc18dc343c2966e1a6b7f638901cf2cb..4ddfc3a8d5943e5cb4600b8de77cd2b4266d2ee0 100644
--- a/libraries/base/common/src/vhdl/common_rl_register.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_register.vhd
@@ -39,8 +39,10 @@ use IEEE.std_logic_1164.all;
entity common_rl_register is
generic (
- g_adapt : boolean := true; -- default when TRUE then register RL 1 --> 0 --> 1, else then implement wires
- g_hold_dat_en : boolean := true; -- default when TRUE hold the src_out_dat until the next active src_out_val, else just pass on snk_in_dat as wires
+ -- default when TRUE then register RL 1 --> 0 --> 1, else then implement wires
+ g_adapt : boolean := true;
+ -- default when TRUE hold the src_out_dat until the next active src_out_val, else just pass on snk_in_dat as wires
+ g_hold_dat_en : boolean := true;
g_dat_w : natural := 18
);
port (
@@ -90,11 +92,13 @@ begin
rst => rst,
clk => clk,
-- Sink
- snk_out_ready => reg_ready, -- sink RL = 0
+ -- sink RL = 0
+ snk_out_ready => reg_ready,
snk_in_dat => reg_dat,
snk_in_val => reg_val,
-- Source
- src_in_ready => src_in_ready, -- source RL = 1
+ -- source RL = 1
+ src_in_ready => src_in_ready,
src_out_dat => src_out_dat,
src_out_val => src_out_val
);
diff --git a/libraries/base/common/src/vhdl/common_round.vhd b/libraries/base/common/src/vhdl/common_round.vhd
index 6f7aae19d2d8a1ef6b16dcab4e354766cf3e076c..bdd02416034dd7087a387c704a6d964c6433a3e1 100644
--- a/libraries/base/common/src/vhdl/common_round.vhd
+++ b/libraries/base/common/src/vhdl/common_round.vhd
@@ -38,12 +38,18 @@ entity common_round is
-- When g_round = FALSE then truncate (= remove) the LSbits and then g_round_clip and g_round_even are dont care.
--
generic (
- g_representation : string := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
- g_round : boolean := true; -- when TRUE round the input, else truncate the input
- g_round_clip : boolean := false; -- when TRUE clip rounded input >= +max to avoid wrapping to output -min (signed) or 0 (unsigned)
- g_round_even : boolean := false; -- when TRUE round to even, else round away from zero
- g_pipeline_input : natural := 0; -- >= 0
- g_pipeline_output : natural := 1; -- >= 0, use g_pipeline_input=0 and g_pipeline_output=0 for combinatorial output
+ -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
+ g_representation : string := "SIGNED";
+ -- when TRUE round the input, else truncate the input
+ g_round : boolean := true;
+ -- when TRUE clip rounded input >= +max to avoid wrapping to output -min (signed) or 0 (unsigned)
+ g_round_clip : boolean := false;
+ -- when TRUE round to even, else round away from zero
+ g_round_even : boolean := false;
+ -- >= 0
+ g_pipeline_input : natural := 0;
+ -- >= 0, use g_pipeline_input=0 and g_pipeline_output=0 for combinatorial output
+ g_pipeline_output : natural := 1;
g_in_dat_w : natural := 36;
g_out_dat_w : natural := 18
);
diff --git a/libraries/base/common/src/vhdl/common_select_m_symbols.vhd b/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
index 9c5981c47a625208abe8bff59d3d2a1b8e7c6185..fbab91d492193a66755bc969881ea72fc672440e 100644
--- a/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
+++ b/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
@@ -44,9 +44,12 @@ entity common_select_m_symbols is
g_nof_input : natural := 4;
g_nof_output : natural := 4;
g_symbol_w : natural := 16;
- g_pipeline_in : natural := 0; -- pipeline in_data
- g_pipeline_in_m : natural := 0; -- pipeline in_data for M-fold fan out
- g_pipeline_out : natural := 1 -- pipeline out_data
+ -- pipeline in_data
+ g_pipeline_in : natural := 0;
+ -- pipeline in_data for M-fold fan out
+ g_pipeline_in_m : natural := 0;
+ -- pipeline out_data
+ g_pipeline_out : natural := 1
);
port (
rst : in std_logic;
@@ -61,10 +64,14 @@ entity common_select_m_symbols is
in_select : in std_logic_vector(g_nof_output * ceil_log2(g_nof_input) - 1 downto 0);
out_data : out std_logic_vector(g_nof_output * g_symbol_w - 1 downto 0);
- out_val : out std_logic; -- pipelined in_val
- out_sop : out std_logic; -- pipelined in_sop
- out_eop : out std_logic; -- pipelined in_eop
- out_sync : out std_logic -- pipelined in_sync
+ -- pipelined in_val
+ out_val : out std_logic;
+ -- pipelined in_sop
+ out_sop : out std_logic;
+ -- pipelined in_eop
+ out_eop : out std_logic;
+ -- pipelined in_sync
+ out_sync : out std_logic
);
end common_select_m_symbols;
@@ -129,10 +136,14 @@ begin
out_sel => OPEN,
out_symbol => out_data_arr(I),
- out_val => out_val_arr(I), -- pipelined in_val
- out_sop => out_sop_arr(I), -- pipelined in_sop
- out_eop => out_eop_arr(I), -- pipelined in_eop
- out_sync => out_sync_arr(I) -- pipelined in_sync
+ -- pipelined in_val
+ out_val => out_val_arr(I),
+ -- pipelined in_sop
+ out_sop => out_sop_arr(I),
+ -- pipelined in_eop
+ out_eop => out_eop_arr(I),
+ -- pipelined in_sync
+ out_sync => out_sync_arr(I)
);
out_data((I + 1) * g_symbol_w - 1 downto I * g_symbol_w) <= out_data_arr(I);
diff --git a/libraries/base/common/src/vhdl/common_select_symbol.vhd b/libraries/base/common/src/vhdl/common_select_symbol.vhd
index 117fb8c133e1a1f783e09ff7e4e48e2764fc0146..c16b2547f6b8a36442df4606a720db3be461fbbb 100644
--- a/libraries/base/common/src/vhdl/common_select_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_select_symbol.vhd
@@ -52,13 +52,18 @@ entity common_select_symbol is
in_sync : in std_logic := '0';
in_sel : in std_logic_vector(g_sel_w - 1 downto 0);
- out_sel : out std_logic_vector(g_sel_w - 1 downto 0); -- pipelined in_sel, use range to allow leaving it OPEN
+ -- pipelined in_sel, use range to allow leaving it OPEN
+ out_sel : out std_logic_vector(g_sel_w - 1 downto 0);
out_symbol : out std_logic_vector(g_symbol_w - 1 downto 0);
- out_val : out std_logic; -- pipelined in_val
- out_sop : out std_logic; -- pipelined in_sop
- out_eop : out std_logic; -- pipelined in_eop
- out_sync : out std_logic -- pipelined in_sync
+ -- pipelined in_val
+ out_val : out std_logic;
+ -- pipelined in_sop
+ out_sop : out std_logic;
+ -- pipelined in_eop
+ out_eop : out std_logic;
+ -- pipelined in_sync
+ out_sync : out std_logic
);
end common_select_symbol;
diff --git a/libraries/base/common/src/vhdl/common_shiftram.vhd b/libraries/base/common/src/vhdl/common_shiftram.vhd
index 382a87a482c9a6c1d4976ea96cbbb0fa2357cdf5..1dcdcb494a52d8b7c9f9d73e15e9d12e0553ce53 100644
--- a/libraries/base/common/src/vhdl/common_shiftram.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftram.vhd
@@ -60,10 +60,13 @@ entity common_shiftram is
generic (
g_technology : natural := c_tech_select_default;
g_data_w : natural;
- g_nof_words : natural; -- Depth of RAM. Must be a power of two.
+ -- Depth of RAM. Must be a power of two.
+ g_nof_words : natural;
g_output_invalid_during_shift_incr : boolean := false;
- g_fixed_shift : boolean := false -- If data_in_shift is constant, set to TRUE
- ); -- for better timing results
+ -- If data_in_shift is constant, set to TRUE
+ g_fixed_shift : boolean := false
+ -- for better timing results
+ );
port (
rst : in std_logic;
clk : in std_logic;
diff --git a/libraries/base/common/src/vhdl/common_shiftreg.vhd b/libraries/base/common/src/vhdl/common_shiftreg.vhd
index e18a57174abfb7bb2165f3de14ee4fab9b2e8780..198245e0197528dda955ac8b8af13db0753693ad 100644
--- a/libraries/base/common/src/vhdl/common_shiftreg.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftreg.vhd
@@ -42,9 +42,12 @@ use work.common_pkg.all;
entity common_shiftreg is
generic (
- g_pipeline : natural := 0; -- pipeline output
- g_flush_en : boolean := false; -- use true to flush shift register when in_eop is active else only shift at active in_val
- g_nof_dat : positive := 4; -- nof data in the shift register, including in_dat, so >= 1
+ -- pipeline output
+ g_pipeline : natural := 0;
+ -- use true to flush shift register when in_eop is active else only shift at active in_val
+ g_flush_en : boolean := false;
+ -- nof data in the shift register, including in_dat, so >= 1
+ g_nof_dat : positive := 4;
g_dat_w : natural := 16
);
port (
@@ -61,12 +64,17 @@ entity common_shiftreg is
out_val_vec : out std_logic_vector(g_nof_dat - 1 downto 0);
out_sop_vec : out std_logic_vector(g_nof_dat - 1 downto 0);
out_eop_vec : out std_logic_vector(g_nof_dat - 1 downto 0);
- out_cnt : out std_logic_vector(sel_a_b(g_nof_dat = 1,1,ceil_log2(g_nof_dat)) - 1 downto 0); -- avoid ISE synthesis failure on NULL range for g_nof_dat=1
+ -- avoid ISE synthesis failure on NULL range for g_nof_dat=1
+ out_cnt : out std_logic_vector(sel_a_b(g_nof_dat = 1,1,ceil_log2(g_nof_dat)) - 1 downto 0);
- out_dat : out std_logic_vector(g_dat_w - 1 downto 0); -- = out_data_vec(0)
- out_val : out std_logic; -- = out_val_vec(0)
- out_sop : out std_logic; -- = out_sop_vec(0)
- out_eop : out std_logic -- = out_eop_vec(0)
+ -- = out_data_vec(0)
+ out_dat : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- = out_val_vec(0)
+ out_val : out std_logic;
+ -- = out_sop_vec(0)
+ out_sop : out std_logic;
+ -- = out_eop_vec(0)
+ out_eop : out std_logic
);
end common_shiftreg;
@@ -167,7 +175,8 @@ begin
end process;
gen_data_vec : for I in g_nof_dat - 1 downto 0 generate
- data_vec((I + 1) * g_dat_w - 1 downto I * g_dat_w) <= data_arr(I); -- map arr to output vector
+ -- map arr to output vector
+ data_vec((I + 1) * g_dat_w - 1 downto I * g_dat_w) <= data_arr(I);
val_vec(I) <= val_arr(I) and shift_en;
sop_vec(I) <= sop_arr(I) and shift_en;
eop_vec(I) <= eop_arr(I) and shift_en;
diff --git a/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd b/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
index e5a3137af0c6d1c0e6042f3dca9df27e67ddeefd..d95d932896494ee9cde5b53acecb37c5659a7a65 100644
--- a/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
@@ -35,9 +35,12 @@ use work.common_pkg.all;
entity common_shiftreg_symbol is
generic (
- g_shiftline_arr : t_natural_arr; -- range g_nof_symbols-1 DOWNTO 0
- g_pipeline : natural := 0; -- pipeline output
- g_flush_en : boolean := false; -- use true to flush shift register when full else only shift at active in_val
+ -- range g_nof_symbols-1 DOWNTO 0
+ g_shiftline_arr : t_natural_arr;
+ -- pipeline output
+ g_pipeline : natural := 0;
+ -- use true to flush shift register when full else only shift at active in_val
+ g_flush_en : boolean := false;
g_nof_symbols : natural := 4;
g_symbol_w : natural := 16
);
@@ -50,10 +53,14 @@ entity common_shiftreg_symbol is
in_sop : in std_logic := '0';
in_eop : in std_logic := '0';
- out_data : out std_logic_vector(g_nof_symbols * g_symbol_w - 1 downto 0); -- shifted in_data
- out_val_arr : out std_logic_vector(g_nof_symbols - 1 downto 0); -- shifted in_val
- out_sop_arr : out std_logic_vector(g_nof_symbols - 1 downto 0); -- shifted in_sop
- out_eop_arr : out std_logic_vector(g_nof_symbols - 1 downto 0) -- shifted in_eop
+ -- shifted in_data
+ out_data : out std_logic_vector(g_nof_symbols * g_symbol_w - 1 downto 0);
+ -- shifted in_val
+ out_val_arr : out std_logic_vector(g_nof_symbols - 1 downto 0);
+ -- shifted in_sop
+ out_sop_arr : out std_logic_vector(g_nof_symbols - 1 downto 0);
+ -- shifted in_eop
+ out_eop_arr : out std_logic_vector(g_nof_symbols - 1 downto 0)
);
end common_shiftreg_symbol;
diff --git a/libraries/base/common/src/vhdl/common_stable_delayed.vhd b/libraries/base/common/src/vhdl/common_stable_delayed.vhd
index e9d5ae319709f9be85beb7a352cb700302200cbf..b99d9a1a74fdedb05320f1aedae0a89d62acf873 100644
--- a/libraries/base/common/src/vhdl/common_stable_delayed.vhd
+++ b/libraries/base/common/src/vhdl/common_stable_delayed.vhd
@@ -43,7 +43,8 @@ entity common_stable_delayed is
generic (
g_active_level : std_logic := '1';
g_delayed_w : natural := 8;
- g_delayed_lo : natural := 7 -- choose <= g_delayed_hi = g_delayed_w-1
+ -- choose <= g_delayed_hi = g_delayed_w-1
+ g_delayed_lo : natural := 7
);
port (
rst : in std_logic;
diff --git a/libraries/base/common/src/vhdl/common_str_pkg.vhd b/libraries/base/common/src/vhdl/common_str_pkg.vhd
index e309a4d10a00d1432c3c166ae1b0bc0174f251c9..164d7545861ea7668344e4ead90ee77824a31baf 100644
--- a/libraries/base/common/src/vhdl/common_str_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_str_pkg.vhd
@@ -104,7 +104,8 @@ package body common_str_pkg is
end;
function bool_to_str(bool : boolean) return string is
- constant c_max_len_bool : natural := 5; -- "TRUE", "FALSE"
+ -- "TRUE", "FALSE"
+ constant c_max_len_bool : natural := 5;
variable v_line: LINE;
variable v_str: string(1 to c_max_len_bool) := (others => ' ');
begin
@@ -183,7 +184,8 @@ package body common_str_pkg is
function hex_to_slv(str: string) return std_logic_vector is
constant c_length : natural := str'length;
- variable v_str : string(1 to str'length) := str; -- Keep local copy of str to prevent range mismatch
+ -- Keep local copy of str to prevent range mismatch
+ variable v_str : string(1 to str'length) := str;
variable v_result : std_logic_vector(c_length * 4 - 1 downto 0);
begin
for i in c_length downto 1 loop
@@ -301,8 +303,10 @@ package body common_str_pkg is
-- Initialize all elements to (OTHERS=>'0') so any unused bytes become a NULL character
variable r: t_slv_32_arr(0 to ceil_div(s'right * c_byte_w, c_word_w) - 1) := (others => (others => '0'));
begin
- for word in r'range loop -- 0, 1
- for byte in 0 to c_bytes_per_word - 1 loop -- 0,1,2,3
+ -- 0, 1
+ for word in r'range loop
+ -- 0,1,2,3
+ for byte in 0 to c_bytes_per_word - 1 loop
if byte + c_bytes_per_word * word <= c_slv_8'right then
r(word)(byte * c_byte_w + c_byte_w - 1 downto byte * c_byte_w) := c_slv_8(byte + c_bytes_per_word * word);
end if;
diff --git a/libraries/base/common/src/vhdl/common_switch.vhd b/libraries/base/common/src/vhdl/common_switch.vhd
index ae38d1382f21e2ae23aba02ed97605269fef8c1b..d30985c6661d448b515d8043614d20aaa409b415 100644
--- a/libraries/base/common/src/vhdl/common_switch.vhd
+++ b/libraries/base/common/src/vhdl/common_switch.vhd
@@ -34,17 +34,23 @@ use ieee.std_logic_1164.all;
entity common_switch is
generic (
- g_rst_level : std_logic := '0'; -- Defines the output level at reset.
- g_priority_lo : boolean := true; -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
- g_or_high : boolean := false; -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
- g_and_low : boolean := false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ -- Defines the output level at reset.
+ g_rst_level : std_logic := '0';
+ -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
+ g_priority_lo : boolean := true;
+ -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
+ g_or_high : boolean := false;
+ -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ g_and_low : boolean := false
);
port (
rst : in std_logic;
clk : in std_logic;
clken : in std_logic := '1';
- switch_high : in std_logic; -- A pulse on switch_high makes the out_level go high
- switch_low : in std_logic; -- A pulse on switch_low makes the out_level go low
+ -- A pulse on switch_high makes the out_level go high
+ switch_high : in std_logic;
+ -- A pulse on switch_low makes the out_level go low
+ switch_low : in std_logic;
out_level : out std_logic
);
end;
diff --git a/libraries/base/common/src/vhdl/common_toggle.vhd b/libraries/base/common/src/vhdl/common_toggle.vhd
index 79d9a4a67ddc74f473f6e32c5175c0d3a6f05218..d6781375045d0a6ceefdb144355dbce964828254 100644
--- a/libraries/base/common/src/vhdl/common_toggle.vhd
+++ b/libraries/base/common/src/vhdl/common_toggle.vhd
@@ -24,8 +24,10 @@ use IEEE.std_logic_1164.all;
entity common_toggle is
generic (
- g_evt_type : string := "RISING"; -- type can be toggle at "RISING", "FALLING", or "BOTH" edges of in_dat when in_val='1'
- g_rst_level : std_logic := '0' -- Defines the output level at reset.
+ -- type can be toggle at "RISING", "FALLING", or "BOTH" edges of in_dat when in_val='1'
+ g_evt_type : string := "RISING";
+ -- Defines the output level at reset.
+ g_rst_level : std_logic := '0'
);
port (
rst : in std_logic;
diff --git a/libraries/base/common/src/vhdl/common_toggle_align.vhd b/libraries/base/common/src/vhdl/common_toggle_align.vhd
index 6739bf67d4c9fb7a678f09ad4605353dd19c1daa..fc105f1952a232ca98d81bf780f0261b397b947f 100644
--- a/libraries/base/common/src/vhdl/common_toggle_align.vhd
+++ b/libraries/base/common/src/vhdl/common_toggle_align.vhd
@@ -37,9 +37,12 @@ use IEEE.std_logic_1164.all;
entity common_toggle_align is
generic (
- g_pipeline : natural := 1; -- 0 for combinatorial to have out_toggle in phase with in_toggle, > 0 for pipelined out_toggle
- g_reset_value : natural := 0; -- 0 or 1, bit reset value for out_toggle
- g_nof_clk_per_period : natural := 4 -- must be even and >= 2
+ -- 0 for combinatorial to have out_toggle in phase with in_toggle, > 0 for pipelined out_toggle
+ g_pipeline : natural := 1;
+ -- 0 or 1, bit reset value for out_toggle
+ g_reset_value : natural := 0;
+ -- must be even and >= 2
+ g_nof_clk_per_period : natural := 4
);
port (
rst : in std_logic := '0';
@@ -64,7 +67,8 @@ begin
begin
if rst = '1' then
cnt <= 0;
- prev_in_toggle <= '1'; -- use '1' to avoid any initial in_toggle_revt (this is not critical though)
+ -- use '1' to avoid any initial in_toggle_revt (this is not critical though)
+ prev_in_toggle <= '1';
elsif rising_edge(clk) then
cnt <= nxt_cnt;
prev_in_toggle <= in_toggle;
diff --git a/libraries/base/common/src/vhdl/common_transpose.vhd b/libraries/base/common/src/vhdl/common_transpose.vhd
index 0408bdf4864644e09e5870dee67dca9bfa2b7820..f938597ba21c9e6697d27ad73277c9119a9a8e8d 100644
--- a/libraries/base/common/src/vhdl/common_transpose.vhd
+++ b/libraries/base/common/src/vhdl/common_transpose.vhd
@@ -41,9 +41,11 @@ entity common_transpose is
g_pipeline_hold : natural := 0;
g_pipeline_select : natural := 1;
g_nof_data : natural := 4;
- g_data_w : natural := 16; -- must be multiple of g_nof_data
+ -- must be multiple of g_nof_data
+ g_data_w : natural := 16;
g_addr_w : natural := 9;
- g_addr_offset : natural := 0 -- default use fixed offset, in_offset * g_nof_data must fit in g_addr_w address range
+ -- default use fixed offset, in_offset * g_nof_data must fit in g_addr_w address range
+ g_addr_offset : natural := 0
);
port (
rst : in std_logic;
diff --git a/libraries/base/common/src/vhdl/common_transpose_symbol.vhd b/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
index bd6fc252d0e666f29c1a638464bf5ea0fa850c8c..048231ee7a2448bfb13192afca7f257f00df6440 100644
--- a/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
@@ -48,7 +48,8 @@ entity common_transpose_symbol is
generic (
g_pipeline : natural := 0;
g_nof_data : natural := 4;
- g_data_w : natural := 16 -- must be multiple of g_nof_data
+ -- must be multiple of g_nof_data
+ g_data_w : natural := 16
);
port (
rst : in std_logic;
@@ -60,9 +61,12 @@ entity common_transpose_symbol is
in_eop : in std_logic := '0';
out_data : out std_logic_vector(g_nof_data * g_data_w - 1 downto 0);
- out_val : out std_logic; -- pipelined in_val
- out_sop : out std_logic; -- pipelined in_sop
- out_eop : out std_logic -- pipelined in_eop
+ -- pipelined in_val
+ out_val : out std_logic;
+ -- pipelined in_sop
+ out_sop : out std_logic;
+ -- pipelined in_eop
+ out_eop : out std_logic
);
end common_transpose_symbol;
diff --git a/libraries/base/common/src/vhdl/common_variable_delay.vhd b/libraries/base/common/src/vhdl/common_variable_delay.vhd
index 10ddd4a1eb095fa4ea55cbca134a0ee91d16e85f..ca9b7a95bbe7a4628a7bc0aed276d73c54ae8f66 100644
--- a/libraries/base/common/src/vhdl/common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_variable_delay.vhd
@@ -74,9 +74,11 @@ begin
-- Accept new in_pulse when idle, ignore new in_pulse when busy
if in_pulse = '1' then
if delay = 0 then
- nxt_out_pulse <= '1'; -- out_pulse immediately
+ -- out_pulse immediately
+ nxt_out_pulse <= '1';
else
- nxt_cnt_en <= '1'; -- apply out_pulse after delay
+ -- apply out_pulse after delay
+ nxt_cnt_en <= '1';
end if;
end if;
end if;
diff --git a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
index 4327b27652223a0cb41674eee9732cb927ee961c..7301308911c335a253323f2a6c9c08941dc3ed47 100644
--- a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
+++ b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
@@ -39,16 +39,20 @@ entity common_wideband_data_scope is
generic (
g_sim : boolean := false;
g_use_sclk : boolean := true;
- g_wideband_factor : natural := 4; -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian : boolean := true; -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w : natural := 8 -- Actual width of the data samples
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor : natural := 4;
+ -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian : boolean := true;
+ -- Actual width of the data samples
+ g_dat_w : natural := 8
);
port (
-- Digital processing clk
DCLK : in std_logic := '0';
-- Sampling clk, for simulation only
- SCLK : in std_logic := '0'; -- SCLK rate = g_wideband_factor * DCLK rate
+ -- SCLK rate = g_wideband_factor * DCLK rate
+ SCLK : in std_logic := '0';
-- Streaming input data
in_data : in std_logic_vector(g_wideband_factor * g_dat_w - 1 downto 0);
@@ -62,13 +66,15 @@ entity common_wideband_data_scope is
end common_wideband_data_scope;
architecture beh of common_wideband_data_scope is
- signal SCLKi : std_logic; -- sampling clk, for simulation only
+ -- sampling clk, for simulation only
+ signal SCLKi : std_logic;
signal scope_cnt : natural;
signal scope_dat : std_logic_vector(g_dat_w - 1 downto 0);
begin
sim_only : if g_sim = true generate
use_sclk : if g_use_sclk = true generate
- SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
+ -- no worry about the delta cycle delay from SCLK to SCLKi
+ SCLKi <= SCLK;
end generate;
gen_sclk : if g_use_sclk = false generate
diff --git a/libraries/base/common/src/vhdl/common_zip.vhd b/libraries/base/common/src/vhdl/common_zip.vhd
index 2bb1bd6abda1cba1f7929db7668139cb7b6f749d..60eeed99f26b07b4aee23efe0516a4b6349cbe76 100644
--- a/libraries/base/common/src/vhdl/common_zip.vhd
+++ b/libraries/base/common/src/vhdl/common_zip.vhd
@@ -30,7 +30,8 @@ use work.common_pkg.all;
entity common_zip is
generic (
- g_nof_streams : natural := 2; -- Number of input streams to be zipped
+ -- Number of input streams to be zipped
+ g_nof_streams : natural := 2;
g_dat_w : natural := 8
);
port (
@@ -47,10 +48,14 @@ architecture rtl of common_zip is
type t_dat_arr is array (natural range <>) of std_logic_vector(out_dat'range);
type reg_type is record
- in_dat_arr : t_dat_arr(g_nof_streams - 1 downto 1); -- Input register
- index : integer range 1 to g_nof_streams; -- Index
- out_dat : std_logic_vector(g_dat_w - 1 downto 0); -- Registered output value
- out_val : std_logic; -- Registered data valid signal
+ -- Input register
+ in_dat_arr : t_dat_arr(g_nof_streams - 1 downto 1);
+ -- Index
+ index : integer range 1 to g_nof_streams;
+ -- Registered output value
+ out_dat : std_logic_vector(g_dat_w - 1 downto 0);
+ -- Registered data valid signal
+ out_val : std_logic;
end record;
signal r, rin : reg_type;
@@ -59,20 +64,25 @@ begin
variable v : reg_type;
begin
v := r;
- v.out_val := '0'; -- Default the output valid signal is low.
+ -- Default the output valid signal is low.
+ v.out_val := '0';
- if(in_val = '1') then -- Wait for incoming data
+ -- Wait for incoming data
+ if(in_val = '1') then
v.index := 1;
v.out_val := '1';
- v.out_dat := in_dat_arr(0)(g_dat_w - 1 downto 0); -- Output the first stream already
+ -- Output the first stream already
+ v.out_dat := in_dat_arr(0)(g_dat_w - 1 downto 0);
for I in 1 to g_nof_streams - 1 loop
- v.in_dat_arr(I) := in_dat_arr(I)(g_dat_w - 1 downto 0); -- Store input data in register
+ -- Store input data in register
+ v.in_dat_arr(I) := in_dat_arr(I)(g_dat_w - 1 downto 0);
end loop;
end if;
if(r.index < g_nof_streams) then
v.out_val := '1';
- v.out_dat := r.in_dat_arr(r.index); -- Output the next input stream
+ -- Output the next input stream
+ v.out_dat := r.in_dat_arr(r.index);
v.index := r.index + 1;
end if;
diff --git a/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd b/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
index ea0228354d9411895fb7453fa07eb334c6e49ac8..e800699016cba9fcedf62b3ae5fe88d303e8f613 100644
--- a/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
@@ -33,7 +33,8 @@ use technology_lib.technology_select_pkg.all;
entity mms_common_pulse_delay is
generic (
- g_pulse_delay_max : natural := 0; -- Maximum number of clk cycles that pulse can be delayed
+ -- Maximum number of clk cycles that pulse can be delayed
+ g_pulse_delay_max : natural := 0;
g_register_out : boolean
);
port (
diff --git a/libraries/base/common/src/vhdl/mms_common_reg.vhd b/libraries/base/common/src/vhdl/mms_common_reg.vhd
index 56fb4f3865a2cbee12747a9ffa69878e1bf7856b..90fbda23826ae447d03ee970b4f23e80b7241b53 100644
--- a/libraries/base/common/src/vhdl/mms_common_reg.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_reg.vhd
@@ -35,14 +35,19 @@ entity mms_common_reg is
-- dat_w : NATURAL;
-- nof_dat : NATURAL; -- optional, nof dat words <= 2**adr_w
-- init_sl : STD_LOGIC; -- optional, init all dat words to std_logic '0', '1' or 'X'
- g_mm_reg : t_c_mem := c_mem_reg -- = (1, 1, 32, 1, 'X')
+ -- = (1, 1, 32, 1, 'X')
+ g_mm_reg : t_c_mem := c_mem_reg
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- MM bus access in memory-mapped clock domain
reg_mosi : in t_mem_mosi;
diff --git a/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd b/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
index c1bf30f4e766887b13fc92adceb1eca0088d0ebe..08ceb817b1ecd271839da058f6030119c205c6e6 100644
--- a/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
@@ -29,21 +29,28 @@ use common_lib.common_mem_pkg.all;
entity mms_common_stable_monitor is
generic (
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
g_nof_input : natural := 8
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
st_in_arr : in std_logic_vector(g_nof_input - 1 downto 0);
-- Memory-mapped clock domain
- reg_mosi : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- reg_miso : out t_mem_miso -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ reg_mosi : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ reg_miso : out t_mem_miso
);
end mms_common_stable_monitor;
@@ -55,7 +62,8 @@ architecture str of mms_common_stable_monitor is
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => c_adr_w,
- dat_w => c_dat_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_dat_w,
nof_dat => c_nof_dat,
init_sl => '0');
diff --git a/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd b/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
index 57d388d15f500b1d3cc92f08eec27ff3e0db3556..a97e912fde9a9e5f6e317f25b60dfdfc0c69ca08 100644
--- a/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
@@ -56,7 +56,8 @@ architecture str of mms_common_variable_delay is
signal enable : std_logic := '0';
begin
- trigger_en <= sl(enable_reg); -- also provide enable as OUT
+ -- also provide enable as OUT
+ trigger_en <= sl(enable_reg);
enable <= sl(enable_reg);
-- device under test
diff --git a/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd b/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
index b415d4357756ff863f60880ad9b48e35103bd05a..88812151e9fe22c25386dbe77c747367d1061283 100644
--- a/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
@@ -26,12 +26,17 @@ use work.common_pkg.all;
entity tb_common_add_sub is
generic (
- g_direction : string := "SUB"; -- "SUB", "ADD" or "BOTH"
- g_sel_add : std_logic := '1'; -- '0' = sub, '1' = add, only valid for g_direction = "BOTH"
- g_pipeline_in : natural := 0; -- input pipelining 0 or 1
- g_pipeline_out : natural := 2; -- output pipelining >= 0
+ -- "SUB", "ADD" or "BOTH"
+ g_direction : string := "SUB";
+ -- '0' = sub, '1' = add, only valid for g_direction = "BOTH"
+ g_sel_add : std_logic := '1';
+ -- input pipelining 0 or 1
+ g_pipeline_in : natural := 0;
+ -- output pipelining >= 0
+ g_pipeline_out : natural := 2;
g_in_dat_w : natural := 5;
- g_out_dat_w : natural := 5 -- g_in_dat_w or g_in_dat_w+1
+ -- g_in_dat_w or g_in_dat_w+1
+ g_out_dat_w : natural := 5
);
end tb_common_add_sub;
@@ -60,8 +65,10 @@ architecture tb of tb_common_add_sub is
signal clk : std_logic := '0';
signal in_a : std_logic_vector(g_in_dat_w - 1 downto 0);
signal in_b : std_logic_vector(g_in_dat_w - 1 downto 0);
- signal out_result : std_logic_vector(g_out_dat_w - 1 downto 0); -- combinatorial result
- signal result_expected : std_logic_vector(g_out_dat_w - 1 downto 0); -- pipelined results
+ -- combinatorial result
+ signal out_result : std_logic_vector(g_out_dat_w - 1 downto 0);
+ -- pipelined results
+ signal result_expected : std_logic_vector(g_out_dat_w - 1 downto 0);
signal result_rtl : std_logic_vector(g_out_dat_w - 1 downto 0);
begin
clk <= not clk or tb_end after clk_period / 2;
diff --git a/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
index 1686b6f4e3b5512fe8e5fa259922b31b52fd688d..36dd7dd94bcbfc3d96846b87651081f6a41b374b 100644
--- a/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
@@ -39,10 +39,13 @@ use work.tb_common_pkg.all;
entity tb_common_adder_tree is
generic (
g_representation : string := "SIGNED";
- g_pipeline : natural := 1; -- amount of pipelining per stage
- g_nof_inputs : natural := 31; -- >= 1
+ -- amount of pipelining per stage
+ g_pipeline : natural := 1;
+ -- >= 1
+ g_nof_inputs : natural := 31;
g_symbol_w : natural := 8;
- g_sum_w : natural := 8 -- worst case bit growth requires g_symbol_w + ceil_log2(g_nof_inputs);
+ -- worst case bit growth requires g_symbol_w + ceil_log2(g_nof_inputs);
+ g_sum_w : natural := 8
);
end tb_common_adder_tree;
@@ -90,14 +93,17 @@ architecture tb of tb_common_adder_tree is
signal clk : std_logic := '1';
signal tb_end : std_logic := '0';
- signal result_comb : std_logic_vector(g_sum_w - 1 downto 0); -- expected combinatorial sum
+ -- expected combinatorial sum
+ signal result_comb : std_logic_vector(g_sum_w - 1 downto 0);
signal in_data_vec : std_logic_vector(c_data_vec_w - 1 downto 0) := (others => '0');
signal in_data_vec_p : std_logic_vector(c_data_vec_w - 1 downto 0);
signal in_data_arr_p : t_symbol_arr(0 to g_nof_inputs - 1);
- signal result_expected : std_logic_vector(g_sum_w - 1 downto 0); -- expected pipelined sum
- signal result_dut : std_logic_vector(g_sum_w - 1 downto 0); -- DUT sum
+ -- expected pipelined sum
+ signal result_expected : std_logic_vector(g_sum_w - 1 downto 0);
+ -- DUT sum
+ signal result_dut : std_logic_vector(g_sum_w - 1 downto 0);
begin
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 3;
@@ -166,7 +172,8 @@ begin
-- Using work.common_adder_tree(recursive) will only invoke the recursive architecture once, because the next recursive level will default to using the last compiled architecture
-- Therefore only instatiatiate the DUT once in this tb and use compile order to influence which architecture is used.
- dut : entity work.common_adder_tree -- uses last compile architecture
+ -- uses last compile architecture
+ dut : entity work.common_adder_tree
generic map (
g_representation => g_representation,
g_pipeline => g_pipeline,
diff --git a/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd b/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
index 27265014b5ad9e222bcebc9c4ddc8cb5d4f3ff86..35eaf77dbbda259abbb1893b4a15c52486c472f0 100644
--- a/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
@@ -35,7 +35,8 @@ use work.tb_common_pkg.all;
entity tb_common_clock_phase_detector is
generic (
--g_clk_factor : REAL := 0.5 -- = clk rate / in_clk rate, must be integer or 1/integer
- g_clk_factor : real := 2.0 -- = clk rate / in_clk rate, must be integer or 1/integer
+ -- = clk rate / in_clk rate, must be integer or 1/integer
+ g_clk_factor : real := 2.0
);
end tb_common_clock_phase_detector;
@@ -45,7 +46,8 @@ architecture tb of tb_common_clock_phase_detector is
constant c_in_clk_period : time := c_clk_factor_num * 5 ns;
- constant in_clk_drift : time := 6 ps; -- must be 0 or even, use drift to model different clock phases
+ -- must be 0 or even, use drift to model different clock phases
+ constant in_clk_drift : time := 6 ps;
constant in_clk_period : time := c_in_clk_period + in_clk_drift;
constant clk_period : time := c_clk_factor_den * c_in_clk_period / c_clk_factor_num;
@@ -93,7 +95,8 @@ begin
g_clk_factor => c_clk_factor_num
)
port map (
- in_clk => in_clk, -- used as data input for clk domain
+ -- used as data input for clk domain
+ in_clk => in_clk,
rst => rst,
clk => clk,
phase => phase_r,
@@ -107,7 +110,8 @@ begin
g_clk_factor => c_clk_factor_num
)
port map (
- in_clk => in_clk, -- used as data input for clk domain
+ -- used as data input for clk domain
+ in_clk => in_clk,
rst => rst,
clk => clk,
phase => phase_f,
diff --git a/libraries/base/common/tb/vhdl/tb_common_counter.vhd b/libraries/base/common/tb/vhdl/tb_common_counter.vhd
index ff4e5fd21d1e654375919064c2f6f76452eb05a3..42de369af5dd0c1617d29b2ac2b8702b411af067 100644
--- a/libraries/base/common/tb/vhdl/tb_common_counter.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_counter.vhd
@@ -36,8 +36,10 @@ architecture tb of tb_common_counter is
signal rst : std_logic;
signal clk : std_logic := '0';
- signal cnt_clr : std_logic := '0'; -- synchronous cnt_clr is only interpreted when clken is active
- signal cnt_ld : std_logic := '0'; -- cnt_ld loads the output count with the input load value, independent of cnt_en
+ -- synchronous cnt_clr is only interpreted when clken is active
+ signal cnt_clr : std_logic := '0';
+ -- cnt_ld loads the output count with the input load value, independent of cnt_en
+ signal cnt_ld : std_logic := '0';
signal cnt_en : std_logic := '1';
signal load : std_logic_vector(c_cnt_w - 1 downto 0) := TO_UVEC(c_cnt_init, c_cnt_w);
signal count : std_logic_vector(c_cnt_w - 1 downto 0);
diff --git a/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd b/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
index c42ebccaeef4d30440159588d01a6d5368aab779..01873883f0e1f4ca5f6349788a0fb590e56b27dd 100644
--- a/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
@@ -68,7 +68,8 @@ begin
for J in 0 to c_nof_block_per_sync_max - 1 loop
for K in 0 to g_nof_clk_per_block - 1 loop
if g_in_val_gaps and K = 0 then
- in_val <= '0'; -- insert a one cycle gap
+ -- insert a one cycle gap
+ in_val <= '0';
proc_common_wait_some_cycles(clk, 1);
end if;
in_val <= '1';
diff --git a/libraries/base/common/tb/vhdl/tb_common_debounce.vhd b/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
index bbd52cac8588a2a541d69c918273605e757c32f8..c7becf14dcf8be855d307f5ab3d6dd44d2c641da 100644
--- a/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
@@ -47,9 +47,12 @@ end tb_common_debounce;
architecture tb of tb_common_debounce is
constant clk_period : time := 10 ns;
- constant c_rst_level_both : std_logic := '0'; -- choose any reset level, because both levels are equivalent
- constant c_rst_level_high : std_logic := '0'; -- choose '0' = not '1' for q_high reset level
- constant c_rst_level_low : std_logic := '1'; -- choose '1' = not '0' for q_low reset level
+ -- choose any reset level, because both levels are equivalent
+ constant c_rst_level_both : std_logic := '0';
+ -- choose '0' = not '1' for q_high reset level
+ constant c_rst_level_high : std_logic := '0';
+ -- choose '1' = not '0' for q_low reset level
+ constant c_rst_level_low : std_logic := '1';
--CONSTANT d_in_level : STD_LOGIC := '1';
constant d_in_level : std_logic := '0';
diff --git a/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
index d5b732914c646908c5fe68787948e8d0aeaca8e5..a9b731724de3c084a73fb191e7a6a667649bcaae 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
@@ -39,11 +39,16 @@ entity tb_common_fanout_tree is
g_random_in_en : boolean := false;
g_random_in_val : boolean := false;
-- DUT settings
- g_nof_stages : positive := 2; -- >= 1
- g_nof_output_per_cell : positive := 2; -- >= 1
- g_nof_output : positive := 3; -- >= 1 and <= g_nof_output_per_cell**g_nof_stages
- g_cell_pipeline_factor_arr : t_natural_arr := (1, 2); -- range: g_nof_stages-1 DOWNTO 0, stage g_nof_stages-1 is output stage. Value: stage factor to multiply with g_cell_pipeline_arr
- g_cell_pipeline_arr : t_natural_arr := (1, 0) -- range: g_nof_output_per_cell-1 DOWNTO 0. Value: 0 for wires, >0 for register stages
+ -- >= 1
+ g_nof_stages : positive := 2;
+ -- >= 1
+ g_nof_output_per_cell : positive := 2;
+ -- >= 1 and <= g_nof_output_per_cell**g_nof_stages
+ g_nof_output : positive := 3;
+ -- range: g_nof_stages-1 DOWNTO 0, stage g_nof_stages-1 is output stage. Value: stage factor to multiply with g_cell_pipeline_arr
+ g_cell_pipeline_factor_arr : t_natural_arr := (1, 2);
+ -- range: g_nof_output_per_cell-1 DOWNTO 0. Value: 0 for wires, >0 for register stages
+ g_cell_pipeline_arr : t_natural_arr := (1, 0)
);
end tb_common_fanout_tree;
@@ -66,8 +71,10 @@ architecture tb of tb_common_fanout_tree is
signal clk : std_logic := '1';
signal ready : std_logic := '1';
signal verify_en : std_logic := '0';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal in_en : std_logic := '1';
signal cnt_en : std_logic := '1';
diff --git a/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd b/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
index 59082dfeef4c8bc1dd5781dee5c4cb58863e24e6..4c040a4e498f90ddee7d8f834aad6f0f9c6875b7 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
@@ -33,8 +33,10 @@ use work.tb_common_pkg.all;
entity tb_common_fifo_dc_mixed_widths is
generic (
- g_wr_clk_freq : positive := 1; -- normalized write clock frequency
- g_rd_clk_freq : positive := 1; -- normalized read clock frequency
+ -- normalized write clock frequency
+ g_wr_clk_freq : positive := 1;
+ -- normalized read clock frequency
+ g_rd_clk_freq : positive := 1;
g_wr_dat_w : natural := 8;
g_rd_dat_w : natural := 16
--g_rd_dat_w : NATURAL := 4
diff --git a/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd b/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
index ca6a2b06dc61fe3b6d1cbd86332354e23a0b5115..705fd02042acde763baee12eb415b349a4421c86 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
@@ -28,7 +28,8 @@ use work.tb_common_pkg.all;
entity tb_common_fifo_rd is
generic (
- g_random_control : boolean := true -- use TRUE for random rd_req control
+ -- use TRUE for random rd_req control
+ g_random_control : boolean := true
);
end tb_common_fifo_rd;
@@ -37,8 +38,10 @@ end tb_common_fifo_rd;
architecture tb of tb_common_fifo_rd is
constant clk_period : time := 10 ns;
constant c_dat_w : natural := 16;
- constant c_fifo_rl : natural := 1; -- FIFO has RL = 1
- constant c_read_rl : natural := 0; -- show ahead FIFO has RL = 0
+ -- FIFO has RL = 1
+ constant c_fifo_rl : natural := 1;
+ -- show ahead FIFO has RL = 0
+ constant c_read_rl : natural := 0;
signal rst : std_logic;
signal clk : std_logic := '0';
diff --git a/libraries/base/common/tb/vhdl/tb_common_init.vhd b/libraries/base/common/tb/vhdl/tb_common_init.vhd
index 04488cf09601e7ff617f3ebb9eb48547810a22a5..1fc73be66092a8d31f8ced600318b3ed03511401 100644
--- a/libraries/base/common/tb/vhdl/tb_common_init.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_init.vhd
@@ -42,11 +42,13 @@ begin
u_reset : entity work.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => clk,
out_rst => rst
);
diff --git a/libraries/base/common/tb/vhdl/tb_common_int2float.vhd b/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
index 507ce94cc18fa3fec3f1ba96fe11e5b77d49d721..a6393c9a3dddc1263b87dd91cef8ef824ca078f2 100644
--- a/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
@@ -20,7 +20,8 @@ architecture tb of tb_common_int2float is
signal exp : integer := c_exp;
signal in_dat : std_logic_vector(c_in_dat_w - 1 downto 0) := (others => '0');
signal in_dat1 : std_logic_vector(c_in_dat_w - 1 downto 0) := (others => '0');
- signal in_dat2 : std_logic_vector(c_in_dat_w - 1 downto 0) := (others => '0'); -- delay by c_pipeline to compare with out_dat
+ -- delay by c_pipeline to compare with out_dat
+ signal in_dat2 : std_logic_vector(c_in_dat_w - 1 downto 0) := (others => '0');
signal out_dat : std_logic_vector(c_out_dat_w - 1 downto 0) := (others => '0');
signal out_dat_exp : std_logic;
signal out_dat_man : std_logic_vector(c_out_dat_w - 2 downto 0);
diff --git a/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd b/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
index 48aad92238cd56c41c2075e933483188d60eb988..c6c108cc5e63aa38640d8d7581bbd1fe3e0b43e3 100644
--- a/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
@@ -38,7 +38,8 @@ architecture tb of tb_common_iobuf_in is
constant c_width : natural := 8;
constant c_delay_init : natural := 0;
constant c_delay_incr : natural := 1;
- constant c_delay_arr : t_natural_arr(0 to c_width - 1) := array_init(c_delay_init, c_width, c_delay_incr); -- 0, 1, 2, 3, ...
+ -- 0, 1, 2, 3, ...
+ constant c_delay_arr : t_natural_arr(0 to c_width - 1) := array_init(c_delay_init, c_width, c_delay_incr);
signal rst : std_logic;
signal clk : std_logic := '0';
diff --git a/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd b/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
index 3934f37a7c894d0f54dd11c524adf3e3442c4466..69d4c1f40fa0ca651624bc9c5fc06269d42511b1 100644
--- a/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
@@ -40,7 +40,8 @@ end tb_common_led_controller;
architecture tb of tb_common_led_controller is
constant c_pulse_us : natural := 10;
- constant c_1000 : natural := 10; -- use eg 10 instead of 1000 to speed up simulation
+ -- use eg 10 instead of 1000 to speed up simulation
+ constant c_1000 : natural := 10;
constant c_led_nof_ms : natural := 3;
constant c_on_nof_ms : natural := 50;
constant c_off_nof_ms : natural := 100;
@@ -102,14 +103,18 @@ begin
u_common_pulser_us_ms_s : entity work.common_pulser_us_ms_s
generic map (
- g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
- g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
+ -- nof clk cycles to get us period
+ g_pulse_us => c_pulse_us,
+ -- nof pulse_us pulses to get ms period
+ g_pulse_ms => c_1000,
+ -- nof pulse_ms pulses to get s period
+ g_pulse_s => c_1000
)
port map (
rst => rst,
clk => clk,
- pulse_ms => pulse_ms -- pulses after every g_pulse_us*g_pulse_ms clock cycles
+ -- pulses after every g_pulse_us*g_pulse_ms clock cycles
+ pulse_ms => pulse_ms
);
u_common_toggle_ms : entity work.common_toggle
diff --git a/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd b/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
index 76794c62a8d87f21ef51923b4c998ac31900e934..53aeb91f28d8c016008db82e10ae6e18d49f41cf 100644
--- a/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
@@ -29,8 +29,10 @@ use work.tb_common_mem_pkg.all;
entity tb_common_mem_mux is
generic (
- g_nof_mosi : positive := 16; -- Number of memory interfaces in the array.
- g_mult_addr_w : positive := 4 -- Address width of each memory-interface element in the array.
+ -- Number of memory interfaces in the array.
+ g_nof_mosi : positive := 16;
+ -- Address width of each memory-interface element in the array.
+ g_mult_addr_w : positive := 4
);
end tb_common_mem_mux;
diff --git a/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
index 94e5f10bbfb7a530bd28415974f67c6a6872c6fe..4ddfdb6985082d2d7d81bfdbf8aba357008f0fc9 100644
--- a/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
@@ -35,35 +35,48 @@ package tb_common_mem_pkg is
-- as signal).
-- Write data to the MM bus
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural; -- [31:0]
- constant wr_data : in integer; -- [31:0]
+ -- [31:0]
+ procedure proc_mem_mm_bus_wr(constant wr_addr : in natural;
+ -- [31:0]
+ constant wr_data : in integer;
signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
+ -- used for waitrequest
+ signal mm_miso : in t_mem_miso;
signal mm_mosi : out t_mem_mosi);
- procedure proc_mem_mm_bus_wr(constant wr_addr : in integer; -- [31:0]
- signal wr_data : in std_logic_vector; -- [31:0]
+ -- [31:0]
+ procedure proc_mem_mm_bus_wr(constant wr_addr : in integer;
+ -- [31:0]
+ signal wr_data : in std_logic_vector;
signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
+ -- used for waitrequest
+ signal mm_miso : in t_mem_miso;
signal mm_mosi : out t_mem_mosi);
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural; -- [31:0]
- constant wr_data : in integer; -- [31:0]
+ -- [31:0]
+ procedure proc_mem_mm_bus_wr(constant wr_addr : in natural;
+ -- [31:0]
+ constant wr_data : in integer;
signal mm_clk : in std_logic;
signal mm_mosi : out t_mem_mosi);
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural; -- [31:0]
- constant wr_data : in std_logic_vector; -- [31:0]
+ -- [31:0]
+ procedure proc_mem_mm_bus_wr(constant wr_addr : in natural;
+ -- [31:0]
+ constant wr_data : in std_logic_vector;
signal mm_clk : in std_logic;
signal mm_mosi : out t_mem_mosi);
-- Read data request to the MM bus
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural; -- [31:0]
+ -- [31:0]
+ procedure proc_mem_mm_bus_rd(constant rd_addr : in natural;
signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
+ -- used for waitrequest
+ signal mm_miso : in t_mem_miso;
signal mm_mosi : out t_mem_mosi);
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural; -- [31:0]
+ -- [31:0]
+ procedure proc_mem_mm_bus_rd(constant rd_addr : in natural;
signal mm_clk : in std_logic;
signal mm_mosi : out t_mem_mosi);
@@ -204,7 +217,8 @@ package body tb_common_mem_pkg is
constant data_arr : in t_slv_32_arr;
signal mm_clk : in std_logic;
signal mm_mosi : out t_mem_mosi) is
- constant c_data_arr : t_slv_32_arr(data_arr'length - 1 downto 0) := data_arr; -- map to fixed range [h:0]
+ -- map to fixed range [h:0]
+ constant c_data_arr : t_slv_32_arr(data_arr'length - 1 downto 0) := data_arr;
begin
for I in 0 to nof_data - 1 loop
proc_mem_mm_bus_wr(offset + I, c_data_arr(I), mm_clk, mm_mosi);
@@ -230,7 +244,8 @@ package body tb_common_mem_pkg is
begin
for I in 0 to nof_data - 1 loop
proc_mem_mm_bus_rd(offset + I, mm_clk, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, mm_clk); -- assume read latency is 1
+ -- assume read latency is 1
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
data_arr(I) <= mm_miso.rddata(31 downto 0);
end loop;
-- wait one mm_clk cycle more to have last rddata captured in signal data_arr (otherwise this proc would need to use variable data_arr)
diff --git a/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd b/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
index f07dd4db303e5d24c65f76b4c677f1a9cc2c8085..a3e59f16ef73af2f610a36ea0e2a34d43eaf96af 100644
--- a/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
@@ -68,7 +68,8 @@ architecture tb of tb_common_multiplexer is
signal clk : std_logic := '1';
signal ready : std_logic := '1';
signal verify_en : std_logic := '0';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
signal cnt_en : std_logic := '1';
-- DUT input
@@ -109,7 +110,8 @@ begin
-- . selection
in_sel <= INCR_UVEC(in_sel, 1) when rising_edge(clk) and TO_UINT(in_sel) < g_nof_streams - 1 else
- TO_UVEC(0, c_sel_w) when rising_edge(clk); -- periodic selection over all demultiplexer output and multiplexer input streams
+ -- periodic selection over all demultiplexer output and multiplexer input streams
+ TO_UVEC(0, c_sel_w) when rising_edge(clk);
-- . verification
p_verify_en : process
@@ -185,7 +187,10 @@ begin
-- Verification
------------------------------------------------------------------------------
- proc_common_verify_data(c_rl, clk, verify_en, ready, out_val, out_dat, prev_out_dat); -- verify out_dat assuming incrementing data
- proc_common_verify_latency("data", c_pipeline_total, clk, verify_en, in_dat, pipe_dat_vec, out_dat); -- verify out_dat using delayed input
- proc_common_verify_latency("valid", c_pipeline_total, clk, verify_en, in_val, pipe_val_vec, out_val); -- verify out_val using delayed input
+ -- verify out_dat assuming incrementing data
+ proc_common_verify_data(c_rl, clk, verify_en, ready, out_val, out_dat, prev_out_dat);
+ -- verify out_dat using delayed input
+ proc_common_verify_latency("data", c_pipeline_total, clk, verify_en, in_dat, pipe_dat_vec, out_dat);
+ -- verify out_val using delayed input
+ proc_common_verify_latency("valid", c_pipeline_total, clk, verify_en, in_val, pipe_val_vec, out_val);
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
index 255bb24dd4a17b7baa968cc131b13373a62edccf..34743ced33f2b1e77f32fa7d2df12fc7adcd9dc1 100644
--- a/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
@@ -37,11 +37,15 @@ use work.tb_common_pkg.all;
entity tb_common_operation_tree is
generic (
- g_operation : string := "MAX"; -- supported operations "MAX", "MIN"
+ -- supported operations "MAX", "MIN"
+ g_operation : string := "MAX";
g_representation : string := "UNSIGNED";
- g_pipeline : natural := 1; -- amount of pipelining per stage
- g_pipeline_mod : natural := 1; -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
- g_nof_inputs : natural := 5 -- >= 1
+ -- amount of pipelining per stage
+ g_pipeline : natural := 1;
+ -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
+ g_pipeline_mod : natural := 1;
+ -- >= 1
+ g_nof_inputs : natural := 5
);
end tb_common_operation_tree;
@@ -110,7 +114,8 @@ architecture tb of tb_common_operation_tree is
signal rst : std_logic;
signal clk : std_logic := '1';
- signal expected_comb : std_logic_vector(c_dat_w - 1 downto 0); -- expected combinatorial result
+ -- expected combinatorial result
+ signal expected_comb : std_logic_vector(c_dat_w - 1 downto 0);
signal in_val : std_logic;
signal in_en_vec : std_logic_vector(g_nof_inputs - 1 downto 0) := (others => '1');
@@ -118,8 +123,10 @@ architecture tb of tb_common_operation_tree is
signal in_data_vec_p : std_logic_vector(c_data_vec_w - 1 downto 0);
signal in_data_arr_p : t_data_arr(0 to g_nof_inputs - 1);
- signal result : std_logic_vector(c_dat_w - 1 downto 0); -- dut result
- signal expected : std_logic_vector(c_dat_w - 1 downto 0); -- expected pipelined result
+ -- dut result
+ signal result : std_logic_vector(c_dat_w - 1 downto 0);
+ -- expected pipelined result
+ signal expected : std_logic_vector(c_dat_w - 1 downto 0);
signal expected_val : std_logic;
begin
clk <= not clk or tb_end after clk_period / 2;
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
index ae4a886e08c4f51afa526f2c194d00ee358f71be..8cd256324758dfb349d873087f206f822daec328 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
@@ -44,11 +44,13 @@ architecture tb of tb_common_paged_ram_crw_crw is
constant clk_period : time := 10 ns;
constant c_data_w : natural := 8;
- constant c_nof_pages : natural := 2; -- >= 2
+ -- >= 2
+ constant c_nof_pages : natural := 2;
constant c_page_sz : natural := 8;
constant c_start_page_a : natural := 0;
constant c_start_page_b : natural := 1;
- constant c_gap_sz : natural := 0; -- >= 0
+ -- >= 0
+ constant c_gap_sz : natural := 0;
constant c_rl : natural := 1;
signal rst : std_logic;
@@ -113,7 +115,8 @@ begin
proc_common_wait_some_cycles(clk, 1);
next_page <= '0';
wr_en_a <= '0';
- proc_common_wait_some_cycles(clk, c_gap_sz); -- optinal gap between the pages
+ -- optinal gap between the pages
+ proc_common_wait_some_cycles(clk, c_gap_sz);
end loop;
wr_en_a <= '0';
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
index 5b632a2f4c0e81444eba462f60002dd8d5d24a98..a3f04782d10f295fb9ab1814d2c9a8053cad3b4a 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
@@ -40,9 +40,12 @@ use work.tb_common_pkg.all;
entity tb_common_paged_ram_ww_rr is
generic (
- g_pipeline_in : natural := 0; -- >= 0
- g_pipeline_out : natural := 1; -- >= 0
- g_page_sz : natural := 10 -- >= 1
+ -- >= 0
+ g_pipeline_in : natural := 0;
+ -- >= 0
+ g_pipeline_out : natural := 1;
+ -- >= 1
+ g_page_sz : natural := 10
);
end tb_common_paged_ram_ww_rr;
@@ -53,11 +56,13 @@ architecture tb of tb_common_paged_ram_ww_rr is
constant c_ram_rd_latency : natural := 1;
constant c_rd_latency : natural := g_pipeline_in + c_ram_rd_latency + g_pipeline_out;
- constant c_offset_a : natural := 2 mod g_page_sz; -- use c_offset_a and c_offset_b to have a read and b read from independent address
+ -- use c_offset_a and c_offset_b to have a read and b read from independent address
+ constant c_offset_a : natural := 2 mod g_page_sz;
constant c_offset_b : natural := 5 mod g_page_sz;
constant c_data_w : natural := 8;
- constant c_gap_sz : natural := 0; -- >= 0
+ -- >= 0
+ constant c_gap_sz : natural := 0;
constant c_addr_w : natural := ceil_log2(g_page_sz);
constant c_rl : natural := 1;
@@ -126,21 +131,26 @@ begin
in_adr <= TO_UVEC((TO_UINT(in_adr) + 1) mod g_page_sz, c_addr_w) when rising_edge(clk) and in_en = '1';
-- Double write use in_en for halve of the g_page_sz time
- wr_en_a <= in_en when in_mod_adr mod 2 = 0 else '0'; -- use port a to write the even addresses
+ -- use port a to write the even addresses
+ wr_en_a <= in_en when in_mod_adr mod 2 = 0 else '0';
wr_dat_a <= in_dat;
wr_adr_a <= in_adr;
- wr_en_b <= '0' when in_mod_adr = g_page_sz - 1 and g_page_sz mod 2 = 1 else -- do not write at last address in case of odd g_page_sz
- in_en when in_mod_adr mod 2 = 0 else '0'; -- use port b to write the odd addresses
+ -- do not write at last address in case of odd g_page_sz
+ wr_en_b <= '0' when in_mod_adr = g_page_sz - 1 and g_page_sz mod 2 = 1 else
+ -- use port b to write the odd addresses
+ in_en when in_mod_adr mod 2 = 0 else '0';
wr_dat_b <= INCR_UVEC(in_dat, 1);
wr_adr_b <= TO_UVEC((TO_UINT(in_adr) + 1) mod g_page_sz, c_addr_w);
-- Double read use in_en
rd_en_a <= in_en;
- rd_adr_a <= TO_UVEC((TO_UINT(in_adr) + c_offset_a) mod g_page_sz, c_addr_w); -- b read from other address than a
+ -- b read from other address than a
+ rd_adr_a <= TO_UVEC((TO_UINT(in_adr) + c_offset_a) mod g_page_sz, c_addr_w);
rd_en_b <= in_en;
- rd_adr_b <= TO_UVEC((TO_UINT(in_adr) + c_offset_b) mod g_page_sz, c_addr_w); -- b read from other address than a
+ -- b read from other address than a
+ rd_adr_b <= TO_UVEC((TO_UINT(in_adr) + c_offset_b) mod g_page_sz, c_addr_w);
p_stimuli : process
begin
@@ -157,7 +167,8 @@ begin
proc_common_wait_some_cycles(clk, 1);
next_page <= '0';
in_en <= '0';
- proc_common_wait_some_cycles(clk, c_gap_sz); -- optional gap between the pages
+ -- optional gap between the pages
+ proc_common_wait_some_cycles(clk, c_gap_sz);
end loop;
in_en <= '0';
@@ -171,7 +182,8 @@ begin
verify_en <= '0';
proc_common_wait_until_high(clk, next_page);
proc_common_wait_some_cycles(clk, c_rd_latency);
- proc_common_wait_some_cycles(clk, 1); -- use first read value as initial reference value
+ -- use first read value as initial reference value
+ proc_common_wait_some_cycles(clk, 1);
verify_en <= '1';
wait;
end process;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
index de11904870898ab5668afb9fe86fa7601b1e149f..3d945fc63f7591cadb41e2f02a3a7cd619bc0371 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
@@ -32,8 +32,10 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-use std.textio.all; -- for boolean, integer file IO
-use IEEE.std_logic_textio.all; -- for std_logic, std_logic_vector file IO
+-- for boolean, integer file IO
+use std.textio.all;
+-- for std_logic, std_logic_vector file IO
+use IEEE.std_logic_textio.all;
use work.common_pkg.all;
package tb_common_pkg is
@@ -130,7 +132,8 @@ package tb_common_pkg is
procedure proc_common_stop_simulation(signal tb_end : in std_logic);
procedure proc_common_stop_simulation(constant g_tb_end : in boolean;
- constant g_latency : in natural; -- latency between tb_done and tb_)end
+ -- latency between tb_done and tb_)end
+ constant g_latency : in natural;
signal clk : in std_logic;
signal tb_done : in std_logic;
signal tb_end : out std_logic);
@@ -143,7 +146,8 @@ package tb_common_pkg is
-- Handle stream ready signal, only support ready latency c_rl = 0 or 1.
procedure proc_common_ready_latency(constant c_rl : in natural;
signal clk : in std_logic;
- signal enable : in std_logic; -- when '1' then active output when ready
+ -- when '1' then active output when ready
+ signal enable : in std_logic;
signal ready : in std_logic;
signal out_valid : out std_logic);
@@ -163,16 +167,22 @@ package tb_common_pkg is
constant c_st_clk_period : in time);
-- Generate a single active, inactive pulse
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
+ -- pulse active for nof clk
+ procedure proc_common_gen_pulse(constant c_active : in natural;
+ -- pulse period for nof clk
+ constant c_period : in natural;
+ -- pulse level when active
+ constant c_level : in std_logic;
signal clk : in std_logic;
signal pulse : out std_logic);
-- Pulse forever after rst was released
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
+ -- pulse active for nof clk
+ procedure proc_common_gen_pulse(constant c_active : in natural;
+ -- pulse period for nof clk
+ constant c_period : in natural;
+ -- pulse level when active
+ constant c_level : in std_logic;
signal rst : in std_logic;
signal clk : in std_logic;
signal pulse : out std_logic);
@@ -182,39 +192,52 @@ package tb_common_pkg is
signal pulse : out std_logic);
-- Generate a periodic pulse with arbitrary duty cycle
- procedure proc_common_gen_duty_pulse(constant c_delay : in natural; -- delay pulse for nof_clk after enable
- constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
+ -- delay pulse for nof_clk after enable
+ procedure proc_common_gen_duty_pulse(constant c_delay : in natural;
+ -- pulse active for nof clk
+ constant c_active : in natural;
+ -- pulse period for nof clk
+ constant c_period : in natural;
+ -- pulse level when active
+ constant c_level : in std_logic;
signal rst : in std_logic;
signal clk : in std_logic;
- signal enable : in std_logic; -- once enabled, the pulse remains enabled
+ -- once enabled, the pulse remains enabled
+ signal enable : in std_logic;
signal pulse : out std_logic);
- procedure proc_common_gen_duty_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
+ -- pulse active for nof clk
+ procedure proc_common_gen_duty_pulse(constant c_active : in natural;
+ -- pulse period for nof clk
+ constant c_period : in natural;
+ -- pulse level when active
+ constant c_level : in std_logic;
signal rst : in std_logic;
signal clk : in std_logic;
- signal enable : in std_logic; -- once enabled, the pulse remains enabled
+ -- once enabled, the pulse remains enabled
+ signal enable : in std_logic;
signal pulse : out std_logic);
-- Generate counter data with valid and arbitrary increment or fixed increment=1
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
+ -- 0, 1 are supported by proc_common_ready_latency()
+ procedure proc_common_gen_data(constant c_rl : in natural;
constant c_init : in integer;
constant c_incr : in integer;
signal rst : in std_logic;
signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ -- when '0' then no valid output even when ready='1'
+ signal enable : in std_logic;
signal ready : in std_logic;
signal out_data : out std_logic_vector;
signal out_valid : out std_logic);
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
+ -- 0, 1 are supported by proc_common_ready_latency()
+ procedure proc_common_gen_data(constant c_rl : in natural;
constant c_init : in integer;
signal rst : in std_logic;
signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ -- when '0' then no valid output even when ready='1'
+ signal enable : in std_logic;
signal ready : in std_logic;
signal out_data : out std_logic_vector;
signal out_valid : out std_logic);
@@ -260,21 +283,25 @@ package tb_common_pkg is
signal out_valid : in std_logic);
-- Verify the DUT input to output latency for SL ctrl signals
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "valid", "sop", "eop"
+ -- e.g. "valid", "sop", "eop"
+ procedure proc_common_verify_latency(constant c_str : in string;
constant c_latency : in natural;
signal clk : in std_logic;
signal verify_en : in std_logic;
signal in_ctrl : in std_logic;
- signal pipe_ctrl_vec : inout std_logic_vector; -- range [0:c_latency]
+ -- range [0:c_latency]
+ signal pipe_ctrl_vec : inout std_logic_vector;
signal out_ctrl : in std_logic);
-- Verify the DUT input to output latency for SLV data signals
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "data"
+ -- e.g. "data"
+ procedure proc_common_verify_latency(constant c_str : in string;
constant c_latency : in natural;
signal clk : in std_logic;
signal verify_en : in std_logic;
signal in_data : in std_logic_vector;
- signal pipe_data_vec : inout std_logic_vector; -- range [0:(1 + c_latency)*c_data_w-1]
+ -- range [0:(1 + c_latency)*c_data_w-1]
+ signal pipe_data_vec : inout std_logic_vector;
signal out_data : in std_logic_vector);
-- Verify the expected value, e.g. to check that a test has ran at all
@@ -696,9 +723,12 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Generate a single active, inactive pulse
------------------------------------------------------------------------------
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
+ -- pulse active for nof clk
+ procedure proc_common_gen_pulse(constant c_active : in natural;
+ -- pulse period for nof clk
+ constant c_period : in natural;
+ -- pulse level when active
+ constant c_level : in std_logic;
signal clk : in std_logic;
signal pulse : out std_logic) is
variable v_cnt : natural range 0 to c_period := 0;
@@ -715,9 +745,12 @@ package body tb_common_pkg is
end proc_common_gen_pulse;
-- Pulse forever after rst was released
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
+ -- pulse active for nof clk
+ procedure proc_common_gen_pulse(constant c_active : in natural;
+ -- pulse period for nof clk
+ constant c_period : in natural;
+ -- pulse level when active
+ constant c_level : in std_logic;
signal rst : in std_logic;
signal clk : in std_logic;
signal pulse : out std_logic) is
@@ -742,10 +775,14 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Generate a periodic pulse with arbitrary duty cycle
------------------------------------------------------------------------------
- procedure proc_common_gen_duty_pulse(constant c_delay : in natural; -- delay pulse for nof_clk after enable
- constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
+ -- delay pulse for nof_clk after enable
+ procedure proc_common_gen_duty_pulse(constant c_delay : in natural;
+ -- pulse active for nof clk
+ constant c_active : in natural;
+ -- pulse period for nof clk
+ constant c_period : in natural;
+ -- pulse level when active
+ constant c_level : in std_logic;
signal rst : in std_logic;
signal clk : in std_logic;
signal enable : in std_logic;
@@ -754,8 +791,10 @@ package body tb_common_pkg is
begin
pulse <= not c_level;
if rst = '0' then
- proc_common_wait_until_high(clk, enable); -- if enabled then continue immediately else wait here
- proc_common_wait_some_cycles(clk, c_delay); -- apply initial c_delay. Once enabled, the pulse remains enabled
+ -- if enabled then continue immediately else wait here
+ proc_common_wait_until_high(clk, enable);
+ -- apply initial c_delay. Once enabled, the pulse remains enabled
+ proc_common_wait_some_cycles(clk, c_delay);
while true loop
wait until rising_edge(clk);
if v_cnt < c_active then
@@ -772,9 +811,12 @@ package body tb_common_pkg is
end if;
end proc_common_gen_duty_pulse;
- procedure proc_common_gen_duty_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
+ -- pulse active for nof clk
+ procedure proc_common_gen_duty_pulse(constant c_active : in natural;
+ -- pulse period for nof clk
+ constant c_period : in natural;
+ -- pulse level when active
+ constant c_level : in std_logic;
signal rst : in std_logic;
signal clk : in std_logic;
signal enable : in std_logic;
@@ -788,12 +830,14 @@ package body tb_common_pkg is
-- . Output counter data dependent on enable and ready
------------------------------------------------------------------------------
-- arbitrary c_incr
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
+ -- 0, 1 are supported by proc_common_ready_latency()
+ procedure proc_common_gen_data(constant c_rl : in natural;
constant c_init : in integer;
constant c_incr : in integer;
signal rst : in std_logic;
signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ -- when '0' then no valid output even when ready='1'
+ signal enable : in std_logic;
signal ready : in std_logic;
signal out_data : out std_logic_vector;
signal out_valid : out std_logic) is
@@ -813,11 +857,13 @@ package body tb_common_pkg is
end proc_common_gen_data;
-- c_incr = 1
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
+ -- 0, 1 are supported by proc_common_ready_latency()
+ procedure proc_common_gen_data(constant c_rl : in natural;
constant c_init : in integer;
signal rst : in std_logic;
signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ -- when '0' then no valid output even when ready='1'
+ signal enable : in std_logic;
signal ready : in std_logic;
signal out_data : out std_logic_vector;
signal out_valid : out std_logic) is
@@ -899,7 +945,8 @@ package body tb_common_pkg is
-- for ready_latency = 0 out_valid only indicates new data when it is confirmed by ready
if c_rl = 1 or (c_rl = 0 and ready = '1') then
prev_out_data <= out_data;
- v_exp_data := INCR_UVEC(prev_out_data, 1); -- increment first then compare to also support increment wrap around
+ -- increment first then compare to also support increment wrap around
+ v_exp_data := INCR_UVEC(prev_out_data, 1);
if verify_en = '1' and unsigned(out_data) /= unsigned(v_exp_data) then
report "COMMON : Wrong out_data count" severity ERROR;
end if;
@@ -938,16 +985,19 @@ package body tb_common_pkg is
-- PROCEDURE: Verify the DUT input to output latency
------------------------------------------------------------------------------
-- for SL ctrl
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "valid", "sop", "eop"
+ -- e.g. "valid", "sop", "eop"
+ procedure proc_common_verify_latency(constant c_str : in string;
constant c_latency : in natural;
signal clk : in std_logic;
signal verify_en : in std_logic;
signal in_ctrl : in std_logic;
- signal pipe_ctrl_vec : inout std_logic_vector; -- range [0:c_latency]
+ -- range [0:c_latency]
+ signal pipe_ctrl_vec : inout std_logic_vector;
signal out_ctrl : in std_logic) is
begin
if rising_edge(clk) then
- pipe_ctrl_vec <= in_ctrl & pipe_ctrl_vec(0 to c_latency - 1); -- note: pipe_ctrl_vec(c_latency) is a dummy place holder to avoid [0:-1] range
+ -- note: pipe_ctrl_vec(c_latency) is a dummy place holder to avoid [0:-1] range
+ pipe_ctrl_vec <= in_ctrl & pipe_ctrl_vec(0 to c_latency - 1);
if verify_en = '1' then
if c_latency = 0 then
if in_ctrl /= out_ctrl then
@@ -963,18 +1013,22 @@ package body tb_common_pkg is
end proc_common_verify_latency;
-- for SLV data
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "data"
+ -- e.g. "data"
+ procedure proc_common_verify_latency(constant c_str : in string;
constant c_latency : in natural;
signal clk : in std_logic;
signal verify_en : in std_logic;
signal in_data : in std_logic_vector;
- signal pipe_data_vec : inout std_logic_vector; -- range [0:(1 + c_latency)*c_data_w-1]
+ -- range [0:(1 + c_latency)*c_data_w-1]
+ signal pipe_data_vec : inout std_logic_vector;
signal out_data : in std_logic_vector) is
constant c_data_w : natural := in_data'length;
- constant c_data_vec_w : natural := pipe_data_vec'length; -- = (1 + c_latency) * c_data_w
+ -- = (1 + c_latency) * c_data_w
+ constant c_data_vec_w : natural := pipe_data_vec'length;
begin
if rising_edge(clk) then
- pipe_data_vec <= in_data & pipe_data_vec(0 to c_data_vec_w - c_data_w - 1); -- note: pipe_data_vec(c_latency) is a dummy place holder to avoid [0:-1] range
+ -- note: pipe_data_vec(c_latency) is a dummy place holder to avoid [0:-1] range
+ pipe_data_vec <= in_data & pipe_data_vec(0 to c_data_vec_w - c_data_w - 1);
if verify_en = '1' then
if c_latency = 0 then
if unsigned(in_data) /= unsigned(out_data) then
@@ -1002,10 +1056,12 @@ package body tb_common_pkg is
if rising_edge(clk) then
if en = '1' then
if mode = 0 and unsigned(res) /= unsigned(exp) then
- report "COMMON : Wrong result value" severity ERROR; -- == (equal)
+ -- == (equal)
+ report "COMMON : Wrong result value" severity ERROR;
end if;
if mode = 1 and unsigned(res) < unsigned(exp) then
- report "COMMON : Wrong result value too small" severity ERROR; -- >= (at least)
+ -- >= (at least)
+ report "COMMON : Wrong result value too small" severity ERROR;
end if;
end if;
end if;
@@ -1159,7 +1215,8 @@ package body tb_common_pkg is
-- of the results string
for I in res_string'range loop
read(v_line, v_char, is_string);
- if not is_string then -- found end of line
+ -- found end of line
+ if not is_string then
exit;
end if;
res_string(I) := v_char;
@@ -1207,7 +1264,8 @@ package body tb_common_pkg is
for J in 0 to nof_row - 1 loop
proc_common_readline_file(v_file_status, v_in_file, v_row_arr, nof_col);
for I in 0 to nof_col - 1 loop
- return_array(J * nof_col + I) <= v_row_arr(I); -- use loop to be independent of t_integer_arr downto or to range
+ -- use loop to be independent of t_integer_arr downto or to range
+ return_array(J * nof_col + I) <= v_row_arr(I);
end loop;
if ENDFILE(v_in_file) then
if J /= nof_row - 1 then
@@ -1245,11 +1303,13 @@ package body tb_common_pkg is
-- Read the header.
while not v_end_header loop
proc_common_readline_file(v_file_status, v_in_file, v_string);
- if(func_find_string_in_string(v_string, "WIDTH=")) then -- check for "WIDTH="
+ -- check for "WIDTH="
+ if(func_find_string_in_string(v_string, "WIDTH=")) then
v_up_bound := func_find_char_in_string(v_string, ';');
v_low_bound := func_find_char_in_string(v_string, '=');
v_mem_width := func_decstring_to_integer(v_string(v_low_bound + 1 to v_up_bound - 1));
- elsif(func_find_string_in_string(v_string, "DEPTH=")) then -- check for "DEPTH="
+ -- check for "DEPTH="
+ elsif(func_find_string_in_string(v_string, "DEPTH=")) then
v_up_bound := func_find_char_in_string(v_string, ';');
v_low_bound := func_find_char_in_string(v_string, '=');
v_mem_depth := func_decstring_to_integer(v_string(v_low_bound + 1 to v_up_bound - 1));
@@ -1259,9 +1319,12 @@ package body tb_common_pkg is
end loop;
-- Read the data
for I in 0 to v_mem_depth - 1 loop
- proc_common_readline_file(v_file_status, v_in_file, v_string); -- Read the next line from the file.
- v_low_bound := func_find_char_in_string(v_string, ':'); -- Find the left position of the string that contains the data field
- v_up_bound := func_find_char_in_string(v_string, ';'); -- Find the right position of the string that contains the data field
+ -- Read the next line from the file.
+ proc_common_readline_file(v_file_status, v_in_file, v_string);
+ -- Find the left position of the string that contains the data field
+ v_low_bound := func_find_char_in_string(v_string, ':');
+ -- Find the right position of the string that contains the data field
+ v_up_bound := func_find_char_in_string(v_string, ';');
return_array(I) <= func_hexstring_to_integer(v_string(v_low_bound + 1 to v_up_bound - 1));
end loop;
-- Close the file
@@ -1283,8 +1346,10 @@ package body tb_common_pkg is
-- From mti_numeric_std.vhd follows:
-- . SIGNED * --> output width = 2 * input width
-- . SIGNED + --> output width = largest(input width)
- constant c_in_w : natural := in_ar'length; -- all input have same width
- constant c_res_w : natural := 2 * c_in_w + 1; -- *2 for multiply, +1 for sum of two products
+ -- all input have same width
+ constant c_in_w : natural := in_ar'length;
+ -- *2 for multiply, +1 for sum of two products
+ constant c_res_w : natural := 2 * c_in_w + 1;
variable v_ar : signed(c_in_w - 1 downto 0);
variable v_ai : signed(c_in_w - 1 downto 0);
variable v_br : signed(c_in_w - 1 downto 0);
@@ -1320,9 +1385,11 @@ package body tb_common_pkg is
-- c) detect MSbits = "01" to clip max positive to get _b011111 = +63
-- Option a) seems to map best on the FPGA hardware multiplier IP.
if str = "RE" then
- return std_logic_vector(RESIZE_NUM(v_result_re, g_out_dat_w)); -- conform option a)
+ -- conform option a)
+ return std_logic_vector(RESIZE_NUM(v_result_re, g_out_dat_w));
else
- return std_logic_vector(RESIZE_NUM(v_result_im, g_out_dat_w)); -- conform option a)
+ -- conform option a)
+ return std_logic_vector(RESIZE_NUM(v_result_im, g_out_dat_w));
end if;
end;
@@ -1330,7 +1397,8 @@ package body tb_common_pkg is
-- FUNCTION: Converts the decimal value represented in a string to an integer value.
------------------------------------------------------------------------------
function func_decstring_to_integer(in_string: string) return integer is
- constant c_nof_digits : natural := in_string'length; -- Define the length of the string
+ -- Define the length of the string
+ constant c_nof_digits : natural := in_string'length;
variable v_char : character;
variable v_weight : integer := 1;
variable v_return_int : integer := 0;
@@ -1351,8 +1419,10 @@ package body tb_common_pkg is
when '9' => v_return_int := v_return_int + 9 * v_weight;
when others => null;
end case;
- if (v_char /= ' ') then -- Only increment the weight when the character is NOT a spacebar.
- v_weight := v_weight * 10; -- Addapt the weight for the next decimal digit.
+ -- Only increment the weight when the character is NOT a spacebar.
+ if (v_char /= ' ') then
+ -- Addapt the weight for the next decimal digit.
+ v_weight := v_weight * 10;
end if;
end loop;
return(v_return_int);
@@ -1362,7 +1432,8 @@ package body tb_common_pkg is
-- FUNCTION: Converts the hexadecimal value represented in a string to an integer value.
------------------------------------------------------------------------------
function func_hexstring_to_integer(in_string: string) return integer is
- constant c_nof_digits : natural := in_string'length; -- Define the length of the string
+ -- Define the length of the string
+ constant c_nof_digits : natural := in_string'length;
variable v_char : character;
variable v_weight : integer := 1;
variable v_return_int : integer := 0;
@@ -1389,8 +1460,10 @@ package body tb_common_pkg is
when 'F' | 'f' => v_return_int := v_return_int + 15 * v_weight;
when others => null;
end case;
- if (v_char /= ' ') then -- Only increment the weight when the character is NOT a spacebar.
- v_weight := v_weight * 16; -- Addapt the weight for the next hexadecimal digit.
+ -- Only increment the weight when the character is NOT a spacebar.
+ if (v_char /= ' ') then
+ -- Addapt the weight for the next hexadecimal digit.
+ v_weight := v_weight * 16;
end if;
end loop;
return(v_return_int);
@@ -1416,8 +1489,10 @@ package body tb_common_pkg is
-- The result is returned as a BOOLEAN.
------------------------------------------------------------------------------
function func_find_string_in_string(in_string: string; find_string: string) return boolean is
- constant c_in_length : natural := in_string'length; -- Define the length of the string to search in
- constant c_find_length : natural := find_string'length; -- Define the length of the string to be find
+ -- Define the length of the string to search in
+ constant c_in_length : natural := in_string'length;
+ -- Define the length of the string to be find
+ constant c_find_length : natural := find_string'length;
variable v_found_it : boolean := false;
begin
for I in 1 to c_in_length - c_find_length loop
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
index 5a9bddeddedb9ae751ca72a87ba36627f5e2c3b8..bda9e0c3f68f69f83eea93b3e81b44f5459efb4d 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
@@ -63,9 +63,12 @@ architecture tb of tb_common_pulse_delay is
-- Verification
----------------------------------------------------------------------------
constant c_nof_pulses : natural := pow2(ceil_log2(c_pulse_delay_max)) - 1;
- constant c_init_cycles : natural := 12; -- Number of clock cycles for init (startup after reset)
- constant c_total_delay_cycles : natural := (c_nof_pulses * (c_nof_pulses + 1)) / 2; -- sum of functional delays 1..c_nof_pulses
- constant c_total_reg_delay_cycles : natural := c_nof_pulses; -- 1 extra delay cycles is introduced for every pulse due to register
+ -- Number of clock cycles for init (startup after reset)
+ constant c_init_cycles : natural := 12;
+ -- sum of functional delays 1..c_nof_pulses
+ constant c_total_delay_cycles : natural := (c_nof_pulses * (c_nof_pulses + 1)) / 2;
+ -- 1 extra delay cycles is introduced for every pulse due to register
+ constant c_total_reg_delay_cycles : natural := c_nof_pulses;
constant c_total_cycles : natural := c_init_cycles + c_total_delay_cycles + c_total_reg_delay_cycles;
signal tb_end : std_logic := '0';
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulser.vhd b/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
index 4dec90a01d91961ed20959663c2c3cf99dde740f..47667efe4f0d7f64cb27fdd233cc4fbae35fd7d6 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
@@ -67,11 +67,13 @@ begin
u_reset : entity work.common_areset
generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
+ -- power up default will be inferred in FPGA
+ g_rst_level => '1',
g_delay_len => c_reset_len
)
port map (
- in_rst => '0', -- release reset after some clock cycles
+ -- release reset after some clock cycles
+ in_rst => '0',
clk => clk,
out_rst => rst
);
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd b/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
index 7f99b1261041ed636b8ed5cf4dce8255d9cec6f7..f509cbb3a87c69479982f14a1c16d739799b2892 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
@@ -39,7 +39,8 @@ end tb_common_pulser_us_ms_s;
architecture tb of tb_common_pulser_us_ms_s is
constant c_pulse_us : natural := 10;
- constant c_1000 : natural := 10; -- use eg 10 instead of 1000 to speed up simulation
+ -- use eg 10 instead of 1000 to speed up simulation
+ constant c_1000 : natural := 10;
constant clk_period : time := 1000 ns / c_pulse_us;
@@ -90,16 +91,22 @@ begin
u_common_pulser_us_ms_s : entity work.common_pulser_us_ms_s
generic map (
- g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
- g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
+ -- nof clk cycles to get us period
+ g_pulse_us => c_pulse_us,
+ -- nof pulse_us pulses to get ms period
+ g_pulse_ms => c_1000,
+ -- nof pulse_ms pulses to get s period
+ g_pulse_s => c_1000
)
port map (
rst => rst,
clk => clk,
sync => sync,
- pulse_us => pulse_us, -- pulses after every g_pulse_us clock cycles
- pulse_ms => pulse_ms, -- pulses after every g_pulse_us*g_pulse_ms clock cycles
- pulse_s => pulse_s -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
+ -- pulses after every g_pulse_us clock cycles
+ pulse_us => pulse_us,
+ -- pulses after every g_pulse_us*g_pulse_ms clock cycles
+ pulse_ms => pulse_ms,
+ -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
+ pulse_s => pulse_s
);
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd b/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
index 5cdd3da0d1cc1fbe34409b08b9119736c56381ab..56ccd683552494052af49dabd394fff0a32c97d6 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
@@ -34,7 +34,8 @@ architecture tb of tb_common_reg_cross_domain is
constant c_interval : natural := 19;
--CONSTANT c_interval : NATURAL := 20;
- constant c_in_new_latency : natural := 2; -- use <2 and =2 to verify s_pulse_latency
+ -- use <2 and =2 to verify s_pulse_latency
+ constant c_in_new_latency : natural := 2;
constant c_dat_w : natural := 8;
-- The state name tells what kind of test is done
@@ -121,12 +122,14 @@ begin
port map (
in_rst => in_rst,
in_clk => in_clk,
- in_new => in_new, -- when '1' then new in_dat is available after g_in_new_latency
+ -- when '1' then new in_dat is available after g_in_new_latency
+ in_new => in_new,
in_dat => in_dat,
in_done => in_done,
out_rst => out_rst,
out_clk => out_clk,
out_dat => out_dat,
- out_new => out_new -- when '1' then the out_dat was updated with in_dat due to in_new
+ -- when '1' then the out_dat was updated with in_dat due to in_new
+ out_new => out_new
);
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd b/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
index 842665e03eaef6b8cf5ee40cc701ac970ca4d0ff..b266eeb76bf82c52c7efd169ed732298b6eef121 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
@@ -33,13 +33,17 @@ use work.tb_common_pkg.all;
entity tb_common_reinterleave is
generic (
- g_dat_w : natural := 16; -- Data width including concatenated stream ID byte (if used)
- g_nof_in : natural := 2; -- Max 6 if stream ID is used
+ -- Data width including concatenated stream ID byte (if used)
+ g_dat_w : natural := 16;
+ -- Max 6 if stream ID is used
+ g_nof_in : natural := 2;
g_deint_block_size : natural := 2;
g_nof_out : natural := 2;
g_inter_block_size : natural := 2;
- g_concat_id : boolean := true; -- Concatenate a 1 byte stream ID 0xA..F @ MSB so user can follow streams in wave window
- g_cnt_sync : boolean := true -- When TRUE all generated streams start at 0, else they're offset by 16 counter values.
+ -- Concatenate a 1 byte stream ID 0xA..F @ MSB so user can follow streams in wave window
+ g_concat_id : boolean := true;
+ -- When TRUE all generated streams start at 0, else they're offset by 16 counter values.
+ g_cnt_sync : boolean := true
);
end;
@@ -59,11 +63,13 @@ architecture rtl of tb_common_reinterleave is
-----------------------------------------------------------------------------
-- Override g_dat_w if user want to concatenate stream IDs
-----------------------------------------------------------------------------
- constant c_id_w : natural := c_nibble_w; -- HEX 0xA..0xF
+ -- HEX 0xA..0xF
+ constant c_id_w : natural := c_nibble_w;
constant c_cnt_dat_w : natural := sel_a_b(g_concat_id, g_dat_w - c_id_w, g_dat_w);
- constant c_nof_id : natural := 6; -- HEX 0xA..0xF
+ -- HEX 0xA..0xF
+ constant c_nof_id : natural := 6;
constant c_id_arr : t_slv_4_arr(c_nof_id - 1 downto 0) := (x"F", x"E", x"D", x"C", x"B", x"A");
signal cnt_ena : std_logic;
@@ -155,7 +161,8 @@ begin
clk => clk,
in_dat => dut_in_dat,
- in_val => dut_in_val_arr(0), -- All input streams should be synchronous in terms of timing
+ -- All input streams should be synchronous in terms of timing
+ in_val => dut_in_val_arr(0),
out_dat => dut_out_dat,
out_val => dut_out_val
@@ -173,7 +180,8 @@ begin
-----------------------------------------------------------------------------
u_rev_reinterleave : entity work.common_reinterleave
generic map (
- g_nof_in => g_nof_out, -- Note the reversed generics
+ -- Note the reversed generics
+ g_nof_in => g_nof_out,
g_deint_block_size => g_inter_block_size,
g_nof_out => g_nof_in,
g_inter_block_size => g_deint_block_size,
diff --git a/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd b/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
index a2e3cb2e3b6db3b0c8b783dabb56c78052c1d16e..686276affaf161e062bdd91a34edef1983627e1d 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
@@ -53,8 +53,10 @@ entity tb_common_reorder_symbol is
g_nof_input : natural := 5;
g_nof_output : natural := 5;
g_symbol_w : natural := 8;
- g_select_arr : t_natural_arr := (3,3,3,3,3, 3,3,3,3,3); -- array_init(3, 6) -- range must fit [c_N*(c_N-1)/2-1:0]
- g_pipeline_arr : t_natural_arr := (0,0,0,0,0,0) -- array_init(0, 5) -- range must fit [0:c_N]
+ -- array_init(3, 6) -- range must fit [c_N*(c_N-1)/2-1:0]
+ g_select_arr : t_natural_arr := (3,3,3,3,3, 3,3,3,3,3);
+ -- array_init(0, 5) -- range must fit [0:c_N]
+ g_pipeline_arr : t_natural_arr := (0,0,0,0,0,0)
);
end tb_common_reorder_symbol;
@@ -70,10 +72,12 @@ architecture tb of tb_common_reorder_symbol is
constant c_N : natural := largest(g_nof_input, g_nof_output);
constant c_dut_pipeline : natural := func_sum(g_pipeline_arr);
- constant c_total_pipeline : natural := c_dut_pipeline * 3; -- factor for DUT, inverse DUT in and out
+ -- factor for DUT, inverse DUT in and out
+ constant c_total_pipeline : natural := c_dut_pipeline * 3;
constant c_nof_select : natural := c_N * (c_N - 1) / 2;
- constant c_select_w : natural := 2; -- fixed 2 bit per X select
+ -- fixed 2 bit per X select
+ constant c_select_w : natural := 2;
-- Stimuli
signal tb_end : std_logic := '0';
@@ -81,7 +85,8 @@ architecture tb of tb_common_reorder_symbol is
signal clk : std_logic := '1';
-- DUT input
- signal in_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := g_select_arr; -- force range [c_N*(c_N-1)/2-1:0]
+ -- force range [c_N*(c_N-1)/2-1:0]
+ signal in_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := g_select_arr;
signal in_select_vec : std_logic_vector(c_nof_select * c_select_w - 1 downto 0);
signal in_data_vec : std_logic_vector(g_nof_input * g_symbol_w - 1 downto 0);
signal in_dat : std_logic_vector( g_symbol_w - 1 downto 0) := (others => '0');
@@ -98,7 +103,8 @@ architecture tb of tb_common_reorder_symbol is
signal reorder_sync : std_logic;
-- inverse output
- signal inverse_select_arr : t_natural_arr(2 * c_nof_select - 1 downto 0) := (others => 0); -- default reorder2 select is 0 for pass on
+ -- default reorder2 select is 0 for pass on
+ signal inverse_select_arr : t_natural_arr(2 * c_nof_select - 1 downto 0) := (others => 0);
signal inverse_select_vec : std_logic_vector(2 * c_nof_select * c_select_w - 1 downto 0) := (others => '0');
signal inverse_data_vec : std_logic_vector(g_nof_output * g_symbol_w - 1 downto 0);
signal inverse_val : std_logic;
diff --git a/libraries/base/common/tb/vhdl/tb_common_rl.vhd b/libraries/base/common/tb/vhdl/tb_common_rl.vhd
index 2eb0d6329b4ee81480ef6c1b11b5a7ffaa7711c3..c1b194ce924c0907385ffc445315c4dbd7fe4cec 100644
--- a/libraries/base/common/tb/vhdl/tb_common_rl.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_rl.vhd
@@ -46,12 +46,17 @@ use work.tb_common_pkg.all;
entity tb_common_rl is
generic (
- g_nof_blocks : natural := 1000; -- nof blocks to simulate
- g_random_enable : boolean := true; -- use TRUE for random input enable flow control
- g_random_ready : boolean := true; -- use TRUE for random output ready flow control
+ -- nof blocks to simulate
+ g_nof_blocks : natural := 1000;
+ -- use TRUE for random input enable flow control
+ g_random_enable : boolean := true;
+ -- use TRUE for random output ready flow control
+ g_random_ready : boolean := true;
g_fifo_size : natural := 1024;
- g_rl_decrease_en : boolean := true; -- use TRUE to make the FIFO with RL = 1 behave as a show ahead fifo with RL = 0
- g_rl_increase_en : boolean := false; -- use TRUE to go back to RL = 1
+ -- use TRUE to make the FIFO with RL = 1 behave as a show ahead fifo with RL = 0
+ g_rl_decrease_en : boolean := true;
+ -- use TRUE to go back to RL = 1
+ g_rl_increase_en : boolean := false;
g_rl_increase_hold_dat_en : boolean := true
);
end tb_common_rl;
@@ -64,13 +69,18 @@ architecture tb of tb_common_rl is
constant c_dat_w : natural := 16;
constant c_random_w : natural := 61;
- constant c_gen_rl : natural := 1; -- input generator has fixed RL = 1
- constant c_fifo_rl : natural := 1; -- FIFO has RL = 1 fixed
+ -- input generator has fixed RL = 1
+ constant c_gen_rl : natural := 1;
+ -- FIFO has RL = 1 fixed
+ constant c_fifo_rl : natural := 1;
- constant c_rl_decrease_rl : natural := sel_a_b(g_rl_decrease_en, 0, 1); -- show ahead FIFO has RL = 0
+ -- show ahead FIFO has RL = 0
+ constant c_rl_decrease_rl : natural := sel_a_b(g_rl_decrease_en, 0, 1);
- constant c_rl_increase_en : boolean := c_rl_decrease_rl = 1 and g_rl_increase_en; -- only accept increase RL to 1 if current RL is 0
- constant c_rl_increase_rl : natural := sel_a_b(c_rl_increase_en, 1, c_rl_decrease_rl); -- determine output RL
+ -- only accept increase RL to 1 if current RL is 0
+ constant c_rl_increase_en : boolean := c_rl_decrease_rl = 1 and g_rl_increase_en;
+ -- determine output RL
+ constant c_rl_increase_rl : natural := sel_a_b(c_rl_increase_en, 1, c_rl_decrease_rl);
constant c_fifo_af_margin : natural := c_fifo_rl + c_rl_increase_rl;
@@ -152,7 +162,8 @@ begin
u_fifo_sc : entity work.common_fifo_sc
generic map (
- g_note_is_ful => true, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_note_is_ful => true,
g_dat_w => c_dat_w,
g_nof_words => g_fifo_size,
g_af_margin => c_fifo_af_margin
@@ -163,7 +174,8 @@ begin
wr_dat => fifo_in_dat,
wr_req => fifo_in_val,
wr_ful => fifo_ful,
- wr_aful => fifo_almost_full, -- get FIFO almost full to be used to force rl_increase_in_ready
+ -- get FIFO almost full to be used to force rl_increase_in_ready
+ wr_aful => fifo_almost_full,
rd_dat => fifo_out_dat,
rd_req => fifo_in_ready,
rd_emp => fifo_emp,
diff --git a/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd b/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
index f6a168912820278e61ea99cf63f3ae8d3dc15bde..4cf9d956628978c244d6a05838675665cd0ef0cb 100644
--- a/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
@@ -38,9 +38,12 @@ use work.tb_common_pkg.all;
entity tb_common_rl_register is
generic (
- g_nof_blocks : natural := 1000; -- nof blocks to simulate
- g_random_enable : boolean := true; -- use TRUE for random input enable flow control
- g_random_ready : boolean := true; -- use TRUE for random output ready flow control
+ -- nof blocks to simulate
+ g_nof_blocks : natural := 1000;
+ -- use TRUE for random input enable flow control
+ g_random_enable : boolean := true;
+ -- use TRUE for random output ready flow control
+ g_random_ready : boolean := true;
g_fifo_size : natural := 64;
g_rl_register_en : boolean := true;
g_rl_register_hold_dat_en : boolean := true
@@ -55,9 +58,12 @@ architecture tb of tb_common_rl_register is
constant c_dat_w : natural := 16;
constant c_random_w : natural := 61;
- constant c_gen_rl : natural := 1; -- input generator has fixed RL = 1
- constant c_fifo_rl : natural := 1; -- FIFO has RL = 1 fixed
- constant c_rl_register_rl : natural := 1; -- common_rl_register has RL = 1 fixed
+ -- input generator has fixed RL = 1
+ constant c_gen_rl : natural := 1;
+ -- FIFO has RL = 1 fixed
+ constant c_fifo_rl : natural := 1;
+ -- common_rl_register has RL = 1 fixed
+ constant c_rl_register_rl : natural := 1;
constant c_fifo_af_margin : natural := c_fifo_rl + sel_a_b(g_rl_register_en, 1, 0);
@@ -131,7 +137,8 @@ begin
u_fifo_sc : entity work.common_fifo_sc
generic map (
- g_note_is_ful => true, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_note_is_ful => true,
g_dat_w => c_dat_w,
g_nof_words => g_fifo_size,
g_af_margin => c_fifo_af_margin
@@ -142,7 +149,8 @@ begin
wr_dat => fifo_in_dat,
wr_req => fifo_in_val,
wr_ful => fifo_ful,
- wr_aful => fifo_almost_full, -- get FIFO almost full to be used to force rl_register_in_ready
+ -- get FIFO almost full to be used to force rl_register_in_ready
+ wr_aful => fifo_almost_full,
rd_dat => fifo_out_dat,
rd_req => fifo_in_ready,
rd_emp => fifo_emp,
diff --git a/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd b/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
index 5fc43a60f2effd7296ebfdefaa345d0a7e5ac0e3..8d0cabbe6b615f1c446ef78fb0703ed3c1491065 100644
--- a/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
@@ -40,9 +40,12 @@ entity tb_common_select_m_symbols is
g_nof_input : natural := 4;
g_nof_output : natural := 4;
g_symbol_w : natural := 16;
- g_pipeline_in : natural := 0; -- pipeline in_data
- g_pipeline_in_m : natural := 0; -- pipeline in_data for M-fold fan out
- g_pipeline_out : natural := 1; -- pipeline out_data
+ -- pipeline in_data
+ g_pipeline_in : natural := 0;
+ -- pipeline in_data for M-fold fan out
+ g_pipeline_in_m : natural := 0;
+ -- pipeline out_data
+ g_pipeline_out : natural := 1;
g_select_arr : t_natural_arr := (2,3,0,1)
);
end tb_common_select_m_symbols;
@@ -59,7 +62,8 @@ architecture tb of tb_common_select_m_symbols is
constant c_N : natural := largest(g_nof_input, g_nof_output);
constant c_dut_pipeline : natural := g_pipeline_in + g_pipeline_in_m + g_pipeline_out;
- constant c_total_pipeline : natural := c_dut_pipeline * 2; -- factor for DUT, inverse DUT
+ -- factor for DUT, inverse DUT
+ constant c_total_pipeline : natural := c_dut_pipeline * 2;
constant c_select_w : natural := ceil_log2(g_nof_input);
diff --git a/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd b/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
index 14f400a91f88f8431654ee96caa00765690b2398..c3ffffc699e0f04feee91fa82e0b53c7e3eb4daa 100644
--- a/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
@@ -46,7 +46,8 @@ architecture tb of tb_common_shiftram is
constant clk_period : time := 10 ns;
constant c_shift_w : natural := ceil_log2(g_nof_words);
- constant c_data_io_delay : natural := 3; -- data_in takes 3 cycles to emerge as data_out
+ -- data_in takes 3 cycles to emerge as data_out
+ constant c_data_io_delay : natural := 3;
signal rst : std_logic;
signal clk : std_logic := '1';
diff --git a/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd b/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
index 306d94849f22786bb7666f0ca151d0a51fe9b173..f719e0b173a531a3c1c9ae8666dddce928ce2b69 100644
--- a/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
@@ -34,8 +34,10 @@ use common_lib.tb_common_pkg.all;
entity tb_common_shiftreg is
generic (
g_pipeline : natural := 0;
- g_flush_en : boolean := true; -- use true to flush shift register when full else only shift at active in_val
- g_nof_dat : natural := 3; -- nof dat in the shift register, including in_dat
+ -- use true to flush shift register when full else only shift at active in_val
+ g_flush_en : boolean := true;
+ -- nof dat in the shift register, including in_dat
+ g_nof_dat : natural := 3;
g_dat_w : natural := 8
);
end tb_common_shiftreg;
diff --git a/libraries/base/common/tb/vhdl/tb_common_switch.vhd b/libraries/base/common/tb/vhdl/tb_common_switch.vhd
index 457290cb5c787750f4466b1c972a8bd425fbcab8..908073852ac7f8d571985c70ede2d1641a5a820d 100644
--- a/libraries/base/common/tb/vhdl/tb_common_switch.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_switch.vhd
@@ -199,7 +199,8 @@ begin
in_hi <= '0';
in_lo <= '0';
proc_common_wait_some_cycles(clk, 5);
- in_lo <= '1'; -- ensure low output if it was still high
+ -- ensure low output if it was still high
+ in_lo <= '1';
proc_common_wait_some_cycles(clk, 1);
in_lo <= '0';
proc_common_wait_some_cycles(clk, 10);
@@ -223,7 +224,8 @@ begin
gen_dut : for I in 0 to c_nof_dut - 1 generate
u_switch : entity work.common_switch
generic map (
- g_rst_level => '0', -- output level at reset.
+ -- output level at reset.
+ g_rst_level => '0',
--g_rst_level => '1',
g_priority_lo => c_generics_matrix(I,0),
g_or_high => c_generics_matrix(I,1),
diff --git a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
index 30de6415c851352612305aeb5f88fc3e38221e26..01455178d6a21a72bbd2fa376872eb5311cef387 100644
--- a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
@@ -64,8 +64,10 @@ architecture tb of tb_common_to_sreal is
signal a_real : real := 0.0;
signal a_sint : integer := 0;
signal a_uint : natural := 0;
- signal a_slv : std_logic_vector(c_width - 1 downto 0) := (others => '0'); -- signed slv
- signal a_ulv : std_logic_vector(c_width - 1 downto 0) := (others => '0'); -- unsigned slv
+ -- signed slv
+ signal a_slv : std_logic_vector(c_width - 1 downto 0) := (others => '0');
+ -- unsigned slv
+ signal a_ulv : std_logic_vector(c_width - 1 downto 0) := (others => '0');
signal dbg_resolution_w : integer := 0;
signal dbg_resolution : real := 0.0;
diff --git a/libraries/base/common/tb/vhdl/tb_common_transpose.vhd b/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
index 922093695f4ad3b5ecea723503355b9ca98df9f0..1f37d33e77030b7aff9474f7e1e7a82d94343f28 100644
--- a/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
@@ -41,7 +41,8 @@ entity tb_common_transpose is
g_nof_data : natural := 3;
g_data_w : natural := 12;
g_addr_w : natural := 9;
- g_addr_offset : natural := 10 -- default use fixed offset, in_offset * g_nof_data must fit in g_addr_w address range
+ -- default use fixed offset, in_offset * g_nof_data must fit in g_addr_w address range
+ g_addr_offset : natural := 10
);
end tb_common_transpose;
@@ -87,7 +88,8 @@ architecture tb of tb_common_transpose is
signal in_eop : std_logic;
-- DUT output
- signal trans_offset : std_logic_vector(g_addr_w - 1 downto 0) := TO_SVEC(-g_addr_offset, g_addr_w); -- use -g_addr_offset as inverse operation
+ -- use -g_addr_offset as inverse operation
+ signal trans_offset : std_logic_vector(g_addr_w - 1 downto 0) := TO_SVEC(-g_addr_offset, g_addr_w);
signal trans_addr : std_logic_vector(g_addr_w - 1 downto 0);
signal trans_data : std_logic_vector(g_data_w - 1 downto 0);
signal trans_val : std_logic;
diff --git a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
index e83313ab6c22d2cff4fc02624756da9f8a84821d..8e3add971010cbe9d83066a5032fe32f80a6763f 100644
--- a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
@@ -37,8 +37,10 @@ end tb_common_variable_delay;
architecture tb of tb_common_variable_delay is
constant c_clk_period : time := 10 ns;
- constant c_trigger_interval : natural := 40; -- in clk's
- constant c_trigger_latency : natural := 1; -- in clk's
+ -- in clk's
+ constant c_trigger_interval : natural := 40;
+ -- in clk's
+ constant c_trigger_latency : natural := 1;
-- Use a delay > c_trigger_interval to check wiht exp_triggers_cnt that new
-- triggers are ignored when a delay is already busy
diff --git a/libraries/base/common/tb/vhdl/tb_common_zip.vhd b/libraries/base/common/tb/vhdl/tb_common_zip.vhd
index 5dd2390947c3888e8d984f4ca02987e3f5e12370..8baa35e45cdf21bf17e34c8b0a0201dc553b6276 100644
--- a/libraries/base/common/tb/vhdl/tb_common_zip.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_zip.vhd
@@ -37,20 +37,23 @@ use work.tb_common_pkg.all;
entity tb_common_zip is
generic (
- g_nof_streams : natural := 3; -- Number of input streams to be zipped
+ -- Number of input streams to be zipped
+ g_nof_streams : natural := 3;
g_dat_w : natural := 8
);
end tb_common_zip;
architecture tb of tb_common_zip is
constant clk_period : time := 10 ns;
- constant c_rl : natural := 1; -- Read Latency = 1
+ -- Read Latency = 1
+ constant c_rl : natural := 1;
signal rst : std_logic;
signal clk : std_logic := '0';
signal tb_end : std_logic := '0';
- signal ready : std_logic := '1'; -- Ready is always '1'
+ -- Ready is always '1'
+ signal ready : std_logic := '1';
signal in_dat_arr : t_slv_64_arr(g_nof_streams - 1 downto 0);
signal in_val : std_logic := '1';
signal out_dat : std_logic_vector(g_dat_w - 1 downto 0);
diff --git a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
index 93022fd6a2b4ad09ec80851a04d49f1816a61e74..05d38b7289ab12a1fcc8b2f45fd2bc2519b4310f 100644
--- a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
@@ -42,7 +42,8 @@ end tb_mms_common_variable_delay;
architecture tb of tb_mms_common_variable_delay is
constant c_clk_period : time := 10 ns;
- constant c_trigger_interval : natural := 40; -- in clk's
+ -- in clk's
+ constant c_trigger_interval : natural := 40;
constant c_mm_addr_enable : natural := 0;
constant c_cross_clock_domain_latency : natural := 40;
diff --git a/libraries/base/common/tb/vhdl/tb_requantize.vhd b/libraries/base/common/tb/vhdl/tb_requantize.vhd
index 68fd97cdd1457e0e60a444f7718ecbf7cccf736f..5c2c4ccfad5a4e974ee5120693ad57828b9da88f 100644
--- a/libraries/base/common/tb/vhdl/tb_requantize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_requantize.vhd
@@ -54,9 +54,12 @@ architecture tb of tb_requantize is
constant c_in_dat_w : natural := 6;
constant c_out_dat_w : natural := 3;
constant c_lsb_w : natural := 2;
- constant c_lsb_round_clip : boolean := true; -- FALSE;
- constant c_lsb_round_even : boolean := false; -- golden reference data is for round half away from zero
- constant c_msb_clip_symmetric : boolean := true; -- FALSE;
+ -- FALSE;
+ constant c_lsb_round_clip : boolean := true;
+ -- golden reference data is for round half away from zero
+ constant c_lsb_round_even : boolean := false;
+ -- FALSE;
+ constant c_msb_clip_symmetric : boolean := true;
-- Stimuli
signal in_val : std_logic;
@@ -67,22 +70,30 @@ architecture tb of tb_requantize is
signal reg_dat : std_logic_vector(c_in_dat_w - 1 downto 0);
-- DUT output
- signal out_s_r_c_dat : std_logic_vector(c_out_dat_w - 1 downto 0); -- src = signed round and clip
+ -- src = signed round and clip
+ signal out_s_r_c_dat : std_logic_vector(c_out_dat_w - 1 downto 0);
signal out_s_r_c_ovr : std_logic;
- signal out_s_r_w_dat : std_logic_vector(c_out_dat_w - 1 downto 0); -- srw = signed round and wrap
+ -- srw = signed round and wrap
+ signal out_s_r_w_dat : std_logic_vector(c_out_dat_w - 1 downto 0);
signal out_s_r_w_ovr : std_logic;
- signal out_s_t_c_dat : std_logic_vector(c_out_dat_w - 1 downto 0); -- stc = signed truncate and clip
+ -- stc = signed truncate and clip
+ signal out_s_t_c_dat : std_logic_vector(c_out_dat_w - 1 downto 0);
signal out_s_t_c_ovr : std_logic;
- signal out_s_t_w_dat : std_logic_vector(c_out_dat_w - 1 downto 0); -- stw = signed truncate and wrap
+ -- stw = signed truncate and wrap
+ signal out_s_t_w_dat : std_logic_vector(c_out_dat_w - 1 downto 0);
signal out_s_t_w_ovr : std_logic;
- signal out_u_r_c_dat : std_logic_vector(c_out_dat_w - 1 downto 0); -- urc = unsigned round and clip
+ -- urc = unsigned round and clip
+ signal out_u_r_c_dat : std_logic_vector(c_out_dat_w - 1 downto 0);
signal out_u_r_c_ovr : std_logic;
- signal out_u_r_w_dat : std_logic_vector(c_out_dat_w - 1 downto 0); -- urw = unsigned round and wrap
+ -- urw = unsigned round and wrap
+ signal out_u_r_w_dat : std_logic_vector(c_out_dat_w - 1 downto 0);
signal out_u_r_w_ovr : std_logic;
- signal out_u_t_c_dat : std_logic_vector(c_out_dat_w - 1 downto 0); -- utc = unsigned truncate and clip
+ -- utc = unsigned truncate and clip
+ signal out_u_t_c_dat : std_logic_vector(c_out_dat_w - 1 downto 0);
signal out_u_t_c_ovr : std_logic;
- signal out_u_t_w_dat : std_logic_vector(c_out_dat_w - 1 downto 0); -- utw = unsigned truncate and wrap
+ -- utw = unsigned truncate and wrap
+ signal out_u_t_w_dat : std_logic_vector(c_out_dat_w - 1 downto 0);
signal out_u_t_w_ovr : std_logic;
-- Verification by means of writing output files that can be compared with stored golden reference files
diff --git a/libraries/base/common/tb/vhdl/tb_resize.vhd b/libraries/base/common/tb/vhdl/tb_resize.vhd
index 01c561206458156c024ae06aeb2b78d6676ef6ae..7fdfb6d9122d6f22479496356df493611d3edbf3 100644
--- a/libraries/base/common/tb/vhdl/tb_resize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_resize.vhd
@@ -64,19 +64,29 @@ architecture tb of tb_resize is
-- Signed output data, view as radix decimal in Wave window
signal reg_sdat : std_logic_vector(g_in_dat_w - 1 downto 0);
- signal lowrange_sdat : std_logic_vector(g_out_dat_w - 1 downto 0); -- keep LSbits or sign extend
- signal resize_num_sdat : std_logic_vector(g_out_dat_w - 1 downto 0); -- using RESIZE_NUM() from common_pkg.vhd
- signal resize_sdat : std_logic_vector(g_out_dat_w - 1 downto 0); -- using RESIZE() from IEEE.NUMERIC_STD
- signal out_sdat : std_logic_vector(g_out_dat_w - 1 downto 0); -- using common_resize.vhd
- signal out_sovr : std_logic; -- overflow for out_sdat
+ -- keep LSbits or sign extend
+ signal lowrange_sdat : std_logic_vector(g_out_dat_w - 1 downto 0);
+ -- using RESIZE_NUM() from common_pkg.vhd
+ signal resize_num_sdat : std_logic_vector(g_out_dat_w - 1 downto 0);
+ -- using RESIZE() from IEEE.NUMERIC_STD
+ signal resize_sdat : std_logic_vector(g_out_dat_w - 1 downto 0);
+ -- using common_resize.vhd
+ signal out_sdat : std_logic_vector(g_out_dat_w - 1 downto 0);
+ -- overflow for out_sdat
+ signal out_sovr : std_logic;
-- Unsigned output data, view as radix unsigned in Wave window
signal reg_udat : std_logic_vector(g_in_dat_w - 1 downto 0);
- signal lowrange_udat : std_logic_vector(g_out_dat_w - 1 downto 0); -- keep LSbits
- signal resize_num_udat : std_logic_vector(g_out_dat_w - 1 downto 0); -- using RESIZE_NUM() from common_pkg.vhd
- signal resize_udat : std_logic_vector(g_out_dat_w - 1 downto 0); -- using RESIZE() from IEEE.NUMERIC_STD
- signal out_udat : std_logic_vector(g_out_dat_w - 1 downto 0); -- using common_resize.vhd
- signal out_uovr : std_logic; -- overflow for out_udat
+ -- keep LSbits
+ signal lowrange_udat : std_logic_vector(g_out_dat_w - 1 downto 0);
+ -- using RESIZE_NUM() from common_pkg.vhd
+ signal resize_num_udat : std_logic_vector(g_out_dat_w - 1 downto 0);
+ -- using RESIZE() from IEEE.NUMERIC_STD
+ signal resize_udat : std_logic_vector(g_out_dat_w - 1 downto 0);
+ -- using common_resize.vhd
+ signal out_udat : std_logic_vector(g_out_dat_w - 1 downto 0);
+ -- overflow for out_udat
+ signal out_uovr : std_logic;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
@@ -98,9 +108,11 @@ begin
tb_end <= '0';
wait until in_val = '1';
wait until rising_edge(clk);
- v_dat := in_dat; -- keep first in_dat
+ -- keep first in_dat
+ v_dat := in_dat;
wait until rising_edge(clk);
- wait until v_dat = in_dat; -- wait until all incrementing in_dat values have been applied at least once
+ -- wait until all incrementing in_dat values have been applied at least once
+ wait until v_dat = in_dat;
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
@@ -130,8 +142,10 @@ begin
begin
if rising_edge(clk) then
-- Extend MSbits for "SIGNED" and "UNSIGNED"
- lowrange_sdat <= (others => in_dat(g_in_dat_w - 1)); -- Extend MSbit for "SIGNED"
- lowrange_udat <= (others => '0'); -- Extend '0' for "UNSIGNED"
+ -- Extend MSbit for "SIGNED"
+ lowrange_sdat <= (others => in_dat(g_in_dat_w - 1));
+ -- Extend '0' for "UNSIGNED"
+ lowrange_udat <= (others => '0');
lowrange_sdat(g_in_dat_w - 1 downto 0) <= in_dat;
lowrange_udat(g_in_dat_w - 1 downto 0) <= in_dat;
end if;
diff --git a/libraries/base/common/tb/vhdl/tb_round.vhd b/libraries/base/common/tb/vhdl/tb_round.vhd
index 59813adae6bea5dcd004310721f07947af8b203b..8b46e517c4971c32c11078a7e621c84b9356073a 100644
--- a/libraries/base/common/tb/vhdl/tb_round.vhd
+++ b/libraries/base/common/tb/vhdl/tb_round.vhd
@@ -42,8 +42,10 @@ use work.common_pkg.all;
entity tb_round is
generic (
- g_in_dat_w : natural := 4; -- w = g_in_dat_w, in [2]
- g_out_dat_w : natural := 1 -- r = g_in_dat_w - g_out_dat_w, in [2]
+ -- w = g_in_dat_w, in [2]
+ g_in_dat_w : natural := 4;
+ -- r = g_in_dat_w - g_out_dat_w, in [2]
+ g_out_dat_w : natural := 1
);
end tb_round;
@@ -149,7 +151,8 @@ architecture tb of tb_round is
signal fs_signed_round_half_even : std_logic_vector(g_out_dat_w - 1 downto 0);
signal fs_signed_round_half_even_clip : std_logic_vector(g_out_dat_w - 1 downto 0);
- signal S_w4 : natural; -- lookup index for signed
+ -- lookup index for signed
+ signal S_w4 : natural;
signal exp_w4_r1_signed_truncate : integer;
signal exp_w4_r1_signed_round_half_away : integer;
signal exp_w4_r1_signed_round_half_away_clip : integer;
@@ -168,7 +171,8 @@ architecture tb of tb_round is
signal exp_w4_r3_signed_round_half_even : integer;
signal exp_w4_r3_signed_round_half_even_clip : integer;
- signal S_w5 : natural; -- lookup index for signed
+ -- lookup index for signed
+ signal S_w5 : natural;
signal exp_w5_r2_signed_truncate : integer;
signal exp_w5_r2_signed_round_half_away : integer;
signal exp_w5_r2_signed_round_half_away_clip : integer;
@@ -198,7 +202,8 @@ architecture tb of tb_round is
signal fs_unsigned_round_half_even : std_logic_vector(g_out_dat_w - 1 downto 0);
signal fs_unsigned_round_half_even_clip : std_logic_vector(g_out_dat_w - 1 downto 0);
- signal U_w4 : natural; -- lookup index for unsigned
+ -- lookup index for unsigned
+ signal U_w4 : natural;
signal exp_w4_r1_unsigned_truncate : integer;
signal exp_w4_r1_unsigned_round_half_up : integer;
signal exp_w4_r1_unsigned_round_half_up_clip : integer;
@@ -217,7 +222,8 @@ architecture tb of tb_round is
signal exp_w4_r3_unsigned_round_half_even : integer;
signal exp_w4_r3_unsigned_round_half_even_clip : integer;
- signal U_w5 : natural; -- lookup index for unsigned
+ -- lookup index for unsigned
+ signal U_w5 : natural;
signal exp_w5_r2_unsigned_truncate : integer;
signal exp_w5_r2_unsigned_round_half_up : integer;
signal exp_w5_r2_unsigned_round_half_up_clip : integer;
@@ -458,7 +464,8 @@ begin
-- Expected rounded values
-- . w = 4
- S_w4 <= (TO_UINT(in_dat) + 8) mod 16; -- 2**4 = 16
+ -- 2**4 = 16
+ S_w4 <= (TO_UINT(in_dat) + 8) mod 16;
U_w4 <= TO_UINT(in_dat) mod 16;
-- . w = 4, r = 1
@@ -501,7 +508,8 @@ begin
exp_w4_r3_unsigned_round_half_even_clip <= c_exp_w4_r3_unsigned_round_half_even_clip(U_w4);
-- . w = 5
- S_w5 <= (TO_UINT(in_dat) + 16) mod 32; -- 2**5 = 32
+ -- 2**5 = 32
+ S_w5 <= (TO_UINT(in_dat) + 16) mod 32;
U_w5 <= TO_UINT(in_dat) mod 32;
-- . w = 5, r = 2
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
index 7d7001e00c70289cbc19599507292e353d3f4b06..cf8a0c017449e268d44d4dcc8f456663b81b1b50 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
@@ -26,7 +26,8 @@ entity tb_tb_common_add_sub is
end tb_tb_common_add_sub;
architecture tb of tb_tb_common_add_sub is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_direction : STRING := "SUB"; -- "SUB" or "ADD"
-- g_sel_add : STD_LOGIC :='1'; -- '0' = sub, '1' = add, only valid for g_direction = "BOTH"
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd
index ac64038aab845870f1cbe72e10dc762f5daca025..7c77050310c8d751e424f8acbd30ef152cc929ef 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd
@@ -27,7 +27,8 @@ entity tb_tb_common_adder_tree is
end tb_tb_common_adder_tree;
architecture tb of tb_tb_common_adder_tree is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Usage:
-- > as 4
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
index b24e0b6dacd38a4c5b06961d049e09b0724b9084..4af7fee42a887e73a90ca854801e125da4ee8e81 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
@@ -30,7 +30,8 @@ entity tb_tb_common_create_strobes_from_valid is
end tb_tb_common_create_strobes_from_valid;
architecture tb of tb_tb_common_create_strobes_from_valid is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_pipeline : BOOLEAN := FALSE;
-- g_in_val_gaps : BOOLEAN := FALSE;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
index d76e0e916dab65fdcc25e62784fa8e02406fb119..5acf6657f5d8aea09513d44b4763f17c43924a1a 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
@@ -27,7 +27,8 @@ entity tb_tb_common_fanout_tree is
end tb_tb_common_fanout_tree;
architecture tb of tb_tb_common_fanout_tree is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Usage:
-- > as 3
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
index 64bfdbd9cc9226ae3d796e42feeb727418b6cce0..0805946186debb49a2c2ea99c3feb537a7c6af69 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
@@ -27,7 +27,8 @@ entity tb_tb_common_multiplexer is
end tb_tb_common_multiplexer;
architecture tb of tb_tb_common_multiplexer is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Usage:
-- > as 3
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
index 238655a6c46242c876c819de5a50976a430f2ac6..2981eb29861c034952ec5ffffd94b3b05442afc4 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
@@ -26,7 +26,8 @@ entity tb_tb_common_operation_tree is
end tb_tb_common_operation_tree;
architecture tb of tb_tb_common_operation_tree is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Usage:
-- > as 2
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
index 4a6aa138cac61b38b8c5527351ec791461b52570..756cf94b0c71a5921ff1a07b49a894fd1baa8bc1 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
@@ -27,7 +27,8 @@ entity tb_tb_common_paged_ram_ww_rr is
end tb_tb_common_paged_ram_ww_rr;
architecture tb of tb_tb_common_paged_ram_ww_rr is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Usage:
-- > as 3
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
index 309b4f2b8c154f874014d7e79b7fc408992e882b..0010039f3d0fa7ba9ccb63d1dab17686cae069e4 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
@@ -26,7 +26,8 @@ entity tb_tb_common_reorder_symbol is
end tb_tb_common_reorder_symbol;
architecture tb of tb_tb_common_reorder_symbol is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Usage:
-- > as 3
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
index 297df49506fa275b644a311a1da67b66528c504a..e78eec8ae80da33d268b4595a8efbc8c82131009 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
@@ -29,7 +29,8 @@ end tb_tb_common_rl;
architecture tb of tb_tb_common_rl is
constant c_nof_blocks : natural := 1000;
constant c_fifo_size : natural := 64;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Usage:
-- > as 2
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
index 77863f33c08dc86ddb65e1d38873fe6cf8682686..e56c8a26d048ffa57bcafb230c09331d2fe1c44a 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
@@ -29,7 +29,8 @@ end tb_tb_common_rl_register;
architecture tb of tb_tb_common_rl_register is
constant c_nof_blocks : natural := 1000;
constant c_fifo_size : natural := 64;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Usage:
-- > as 2
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
index 3fd334e1a175212ea76ce8c0417c682c6b59fa60..70fd269cff0c6e399be5e6209e076cef0f87da77 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
@@ -31,7 +31,8 @@ entity tb_tb_common_transpose is
end tb_tb_common_transpose;
architecture tb of tb_tb_common_transpose is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_pipeline_shiftreg : NATURAL := 0;
-- | g_pipeline_transpose : NATURAL := 0;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_resize.vhd b/libraries/base/common/tb/vhdl/tb_tb_resize.vhd
index af84a20edf01fb0227a6bd82122d160c92b6d46d..acc78d266fb4bba4432fef268cf116656f789811 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_resize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_resize.vhd
@@ -26,7 +26,8 @@ entity tb_tb_resize is
end tb_tb_resize;
architecture tb of tb_tb_resize is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- Supported for RESIZE_NUM() and common_resize.vhd
-- g_in_dat_w : NATURAL := 5;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_round.vhd b/libraries/base/common/tb/vhdl/tb_tb_round.vhd
index d6d452e9d10be67b639e327e39fc408373150121..b9d3dece127806677bf590184cc03c36d630f8bc 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_round.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_round.vhd
@@ -26,7 +26,8 @@ entity tb_tb_round is
end tb_tb_round;
architecture tb of tb_tb_round is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- Supported for RESIZE_NUM() and common_round.vhd
-- g_in_dat_w : NATURAL := 5;
@@ -34,9 +35,14 @@ begin
u_extend : entity work.tb_round generic map (5, 6);
u_wires : entity work.tb_round generic map (5, 5);
- u_round_w4_r1 : entity work.tb_round generic map (4, 3); -- -r = 4 - 3 = 1
- u_round_w4_r2 : entity work.tb_round generic map (4, 2); -- -r = 4 - 2 = 2
- u_round_w4_r3 : entity work.tb_round generic map (4, 1); -- -r = 4 - 1 = 3
- u_round_w5_r2 : entity work.tb_round generic map (5, 3); -- -r = 5 - 3 = 2
- u_round_w5_r3 : entity work.tb_round generic map (5, 2); -- -r = 5 - 2 = 3
+ -- -r = 4 - 3 = 1
+ u_round_w4_r1 : entity work.tb_round generic map (4, 3);
+ -- -r = 4 - 2 = 2
+ u_round_w4_r2 : entity work.tb_round generic map (4, 2);
+ -- -r = 4 - 1 = 3
+ u_round_w4_r3 : entity work.tb_round generic map (4, 1);
+ -- -r = 5 - 3 = 2
+ u_round_w5_r2 : entity work.tb_round generic map (5, 3);
+ -- -r = 5 - 2 = 3
+ u_round_w5_r3 : entity work.tb_round generic map (5, 2);
end tb;
diff --git a/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd b/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
index 7ecc20e1be586ac59a46ce8c50b1090c84109256..05be691ef7a3eb740c7a5a134f45177bfda64686 100644
--- a/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
@@ -51,12 +51,17 @@ entity common_complex_mult is
g_variant : string := "IP";
g_in_a_w : positive;
g_in_b_w : positive;
- g_out_p_w : positive; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
+ -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
+ g_out_p_w : positive;
g_conjugate_b : boolean := false;
- g_pipeline_input : natural := 1; -- 0 or 1
- g_pipeline_product : natural := 0; -- 0 or 1
- g_pipeline_adder : natural := 1; -- 0 or 1
- g_pipeline_output : natural := 1 -- >= 0
+ -- 0 or 1
+ g_pipeline_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_product : natural := 0;
+ -- 0 or 1
+ g_pipeline_adder : natural := 1;
+ -- >= 0
+ g_pipeline_output : natural := 1
);
port (
rst : in std_logic := '0';
@@ -132,7 +137,8 @@ begin
-- Extra output pipelining
------------------------------------------------------------------------------
- u_output_re_pipe : entity common_lib.common_pipeline -- pipeline output
+ -- pipeline output
+ u_output_re_pipe : entity common_lib.common_pipeline
generic map (
g_representation => "SIGNED",
g_pipeline => c_pipeline_output,
@@ -146,7 +152,8 @@ begin
out_dat => out_pr
);
- u_output_im_pipe : entity common_lib.common_pipeline -- pipeline output
+ -- pipeline output
+ u_output_im_pipe : entity common_lib.common_pipeline
generic map (
g_representation => "SIGNED",
g_pipeline => c_pipeline_output,
diff --git a/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd b/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
index 1d2064de811449511e1c7f5d9785b3a976d13b07..4b792ba0c2f8be0b741f87296773af96547cae59 100644
--- a/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
@@ -32,10 +32,14 @@ entity common_complex_mult_add is
g_in_b_w : positive := 16;
g_ch_w : positive := 38;
g_out_p_w : positive := 38;
- g_pipeline_input : natural := 1; -- 0 or 1
- g_pipeline_product : natural := 0; -- 0 or 1
- g_pipeline_adder : natural := 1; -- 0 or 1
- g_pipeline_output : natural := 1 -- >= 0
+ -- 0 or 1
+ g_pipeline_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_product : natural := 0;
+ -- 0 or 1
+ g_pipeline_adder : natural := 1;
+ -- >= 0
+ g_pipeline_output : natural := 1
);
port (
rst : in std_logic := '0';
@@ -59,8 +63,10 @@ end common_complex_mult_add;
architecture str of common_complex_mult_add is
constant c_conjugate : boolean := false;
constant c_direction : string := "ADD";
- constant c_pipeline_in : natural := 0; -- input pipelining 0 or 1
- constant c_pipeline_out : natural := 1; -- output pipelining >= 0
+ -- input pipelining 0 or 1
+ constant c_pipeline_in : natural := 0;
+ -- output pipelining >= 0
+ constant c_pipeline_out : natural := 1;
constant c_sel_add : std_logic := '1';
constant c_prod_w : natural := g_in_a_w + g_in_b_w;
@@ -71,7 +77,8 @@ architecture str of common_complex_mult_add is
signal add_ini : std_logic_vector(g_out_p_w - 1 downto 0);
begin
-- u_complex_mult : entity work.common_complex_mult(stratix4) -- requires sum of g_pipeline >= 3
- u_complex_mult : entity work.common_complex_mult -- suits sum of g_pipeline >= 0
+ -- suits sum of g_pipeline >= 0
+ u_complex_mult : entity work.common_complex_mult
generic map (
g_technology => g_technology,
g_variant => "RTL",
@@ -96,7 +103,8 @@ begin
out_pi => out_pi
);
- add_inr <= RESIZE_SVEC(out_pr, g_out_p_w); -- Connect the output of the multiplier to the adders input
+ -- Connect the output of the multiplier to the adders input
+ add_inr <= RESIZE_SVEC(out_pr, g_out_p_w);
add_ini <= RESIZE_SVEC(out_pi, g_out_p_w);
u_adder_real : entity common_lib.common_add_sub
@@ -153,7 +161,8 @@ architecture rtl of common_complex_mult_add is
begin
process (clk, rst, clken)
begin
- if(rst = '1') then -- asynchronous reset
+ -- asynchronous reset
+ if(rst = '1') then
ar_reg <= (others => '0');
ai_reg <= (others => '0');
br_reg <= (others => '0');
@@ -165,7 +174,8 @@ begin
sumr <= (others => '0');
sumi <= (others => '0');
- elsif(rising_edge(clk) and clken = '1') then -- rising clock edge
+ -- rising clock edge
+ elsif(rising_edge(clk) and clken = '1') then
ar_reg <= signed(in_ar);
ai_reg <= signed(in_ai);
br_reg <= signed(in_br);
@@ -173,11 +183,15 @@ begin
chr_reg <= signed(in_chr);
chi_reg <= signed(in_chi);
- pr <= RESIZE_NUM((ar_reg * br_reg), c_prod_w) - RESIZE_NUM((ai_reg * bi_reg), c_prod_w); -- Calculate the real part
- pi <= RESIZE_NUM((ar_reg * bi_reg), c_prod_w) + RESIZE_NUM((ai_reg * br_reg), c_prod_w); -- Calculate the imaginary part
+ -- Calculate the real part
+ pr <= RESIZE_NUM((ar_reg * br_reg), c_prod_w) - RESIZE_NUM((ai_reg * bi_reg), c_prod_w);
+ -- Calculate the imaginary part
+ pi <= RESIZE_NUM((ar_reg * bi_reg), c_prod_w) + RESIZE_NUM((ai_reg * br_reg), c_prod_w);
- sumr <= RESIZE_NUM(pr, g_out_p_w) + RESIZE_NUM(signed(in_chr), g_out_p_w); -- Add the chain_in real part to the real product
- sumi <= RESIZE_NUM(pi, g_out_p_w) + RESIZE_NUM(signed(in_chi), g_out_p_w); -- Add the chain_in imaginary part to the imaginary product
+ -- Add the chain_in real part to the real product
+ sumr <= RESIZE_NUM(pr, g_out_p_w) + RESIZE_NUM(signed(in_chr), g_out_p_w);
+ -- Add the chain_in imaginary part to the imaginary product
+ sumi <= RESIZE_NUM(pi, g_out_p_w) + RESIZE_NUM(signed(in_chi), g_out_p_w);
end if;
end process;
diff --git a/libraries/base/common_mult/src/vhdl/common_mult.vhd b/libraries/base/common_mult/src/vhdl/common_mult.vhd
index e533209b2a9c53ec2a53e523cca4009ddc4b843f..787f717ba97b4d918375b4b30867f6609fc7fd4f 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult.vhd
@@ -45,12 +45,18 @@ entity common_mult is
g_variant : string := "IP";
g_in_a_w : positive := 18;
g_in_b_w : positive := 18;
- g_out_p_w : positive := 36; -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
- g_nof_mult : positive := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
- g_pipeline_input : natural := 1; -- 0 or 1
- g_pipeline_product : natural := 1; -- 0 or 1
- g_pipeline_output : natural := 1; -- >= 0
- g_representation : string := "SIGNED" -- or "UNSIGNED"
+ -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
+ g_out_p_w : positive := 36;
+ -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+ g_nof_mult : positive := 1;
+ -- 0 or 1
+ g_pipeline_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_product : natural := 1;
+ -- >= 0
+ g_pipeline_output : natural := 1;
+ -- or "UNSIGNED"
+ g_representation : string := "SIGNED"
);
port (
rst : in std_logic := '0';
@@ -58,7 +64,8 @@ entity common_mult is
clken : in std_logic := '1';
in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
- in_val : in std_logic := '1'; -- only propagate valid, not used internally
+ -- only propagate valid, not used internally
+ in_val : in std_logic := '1';
out_p : out std_logic_vector(g_nof_mult * g_out_p_w - 1 downto 0);
out_val : out std_logic
);
@@ -70,7 +77,8 @@ architecture str of common_mult is
-- Extra output pipelining using common_pipeline is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
- signal result : std_logic_vector(out_p'range); -- stage dependent on g_pipeline_output being 0 or 1
+ -- stage dependent on g_pipeline_output being 0 or 1
+ signal result : std_logic_vector(out_p'range);
begin
u_mult : entity tech_mult_lib.tech_mult
generic map(
@@ -111,7 +119,8 @@ begin
-- Extra output pipelining
------------------------------------------------------------------------------
- u_output_pipe : entity common_lib.common_pipeline -- pipeline output
+ -- pipeline output
+ u_output_pipe : entity common_lib.common_pipeline
generic map (
g_representation => g_representation,
g_pipeline => c_pipeline_output,
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
index 397a229a0b61e78e80b832e2d0e7a31606fcc191..c206d1e4efe68694d4060aba8e31905bbd160dcb 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
@@ -45,14 +45,22 @@ entity common_mult_add2 is
g_variant : string := "RTL";
g_in_a_w : positive;
g_in_b_w : positive;
- g_res_w : positive; -- g_in_a_w + g_in_b_w + log2(4)
- g_force_dsp : boolean := true; -- when TRUE resize input width to >= 18
- g_add_sub : string := "ADD"; -- or "SUB" only available with rtl architecture
- g_nof_mult : integer := 4; -- fixed
- g_pipeline_input : natural := 1; -- 0 or 1
- g_pipeline_product : natural := 0; -- 0 or 1
- g_pipeline_adder : natural := 1; -- 0 or 1, first sum
- g_pipeline_output : natural := 1 -- >= 0, second sum and optional rounding
+ -- g_in_a_w + g_in_b_w + log2(4)
+ g_res_w : positive;
+ -- when TRUE resize input width to >= 18
+ g_force_dsp : boolean := true;
+ -- or "SUB" only available with rtl architecture
+ g_add_sub : string := "ADD";
+ -- fixed
+ g_nof_mult : integer := 4;
+ -- 0 or 1
+ g_pipeline_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_product : natural := 0;
+ -- 0 or 1, first sum
+ g_pipeline_adder : natural := 1;
+ -- >= 0, second sum and optional rounding
+ g_pipeline_output : natural := 1
);
port (
rst : in std_logic := '0';
@@ -97,7 +105,8 @@ begin
-- Extra output pipelining
------------------------------------------------------------------------------
- u_output_pipe : entity common_lib.common_pipeline -- pipeline output
+ -- pipeline output
+ u_output_pipe : entity common_lib.common_pipeline
generic map (
g_representation => "SIGNED",
g_pipeline => c_pipeline_output,
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
index 088c8ccc9de1ba7caac16f910f081742e8edb794..c79a72fdd93c9defa0b55e3c024ad8af67fca2d6 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
@@ -48,16 +48,26 @@ entity common_mult_add4 is
g_variant : string := "RTL";
g_in_a_w : positive;
g_in_b_w : positive;
- g_res_w : positive; -- g_in_a_w + g_in_b_w + log2(4)
- g_force_dsp : boolean := true; -- when TRUE resize input width to >= 18
- g_add_sub0 : string := "ADD"; -- or "SUB"
- g_add_sub1 : string := "ADD"; -- or "SUB"
- g_add_sub : string := "ADD"; -- or "SUB" only available with rtl architecture
- g_nof_mult : integer := 4; -- fixed
- g_pipeline_input : natural := 1; -- 0 or 1
- g_pipeline_product : natural := 0; -- 0 or 1
- g_pipeline_adder : natural := 1; -- 0 or 1, first sum
- g_pipeline_output : natural := 1 -- >= 0, second sum and optional rounding
+ -- g_in_a_w + g_in_b_w + log2(4)
+ g_res_w : positive;
+ -- when TRUE resize input width to >= 18
+ g_force_dsp : boolean := true;
+ -- or "SUB"
+ g_add_sub0 : string := "ADD";
+ -- or "SUB"
+ g_add_sub1 : string := "ADD";
+ -- or "SUB" only available with rtl architecture
+ g_add_sub : string := "ADD";
+ -- fixed
+ g_nof_mult : integer := 4;
+ -- 0 or 1
+ g_pipeline_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_product : natural := 0;
+ -- 0 or 1, first sum
+ g_pipeline_adder : natural := 1;
+ -- >= 0, second sum and optional rounding
+ g_pipeline_output : natural := 1
);
port (
rst : in std_logic := '0';
@@ -104,7 +114,8 @@ begin
-- Extra output pipelining
------------------------------------------------------------------------------
- u_output_pipe : entity common_lib.common_pipeline -- pipeline output
+ -- pipeline output
+ u_output_pipe : entity common_lib.common_pipeline
generic map (
g_representation => "SIGNED",
g_pipeline => c_pipeline_output,
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
index bd0dec1fcb3901fe47473d489bf296e7f83c68a7..b2a20cffee94b648fcc7fb4a5808382e5c05fbfc 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
@@ -37,9 +37,11 @@ use common_lib.tb_common_pkg.all;
entity tb_common_complex_mult is
generic (
- g_variant : string := "IP"; -- "RTL" or "IP"
+ -- "RTL" or "IP"
+ g_variant : string := "IP";
g_in_dat_w : natural := 18;
- g_conjugate_b : boolean := true; -- When FALSE p = a * b, else p = a * conj(b)
+ -- When FALSE p = a * b, else p = a * conj(b)
+ g_conjugate_b : boolean := true;
g_pipeline_input : natural := 1;
g_pipeline_product : natural := 0;
g_pipeline_adder : natural := 1;
@@ -65,7 +67,8 @@ architecture tb of tb_common_complex_mult is
signal rst : std_logic;
signal clk : std_logic := '0';
- signal random : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(14 downto 0) := (others => '0');
-- Input
signal in_ar : std_logic_vector(g_in_dat_w - 1 downto 0);
@@ -73,7 +76,8 @@ architecture tb of tb_common_complex_mult is
signal in_br : std_logic_vector(g_in_dat_w - 1 downto 0);
signal in_bi : std_logic_vector(g_in_dat_w - 1 downto 0);
- signal in_val : std_logic; -- in_val is only passed on to out_val, not used by multiplier itself
+ -- in_val is only passed on to out_val, not used by multiplier itself
+ signal in_val : std_logic;
-- Results
-- . expected valid and DUT valid, only depends on in_val and c_pipeline
@@ -81,9 +85,11 @@ architecture tb of tb_common_complex_mult is
signal result_val_dut : std_logic;
-- . product result
- signal ref_result_re : std_logic_vector(c_out_dat_w - 1 downto 0); -- combinatorial result
+ -- combinatorial result
+ signal ref_result_re : std_logic_vector(c_out_dat_w - 1 downto 0);
signal ref_result_im : std_logic_vector(c_out_dat_w - 1 downto 0);
- signal result_re_expected : std_logic_vector(c_out_dat_w - 1 downto 0); -- pipelined results
+ -- pipelined results
+ signal result_re_expected : std_logic_vector(c_out_dat_w - 1 downto 0);
signal result_re_dut : std_logic_vector(c_out_dat_w - 1 downto 0);
signal result_im_expected : std_logic_vector(c_out_dat_w - 1 downto 0);
signal result_im_dut : std_logic_vector(c_out_dat_w - 1 downto 0);
@@ -114,7 +120,8 @@ begin
proc_common_wait_some_cycles(clk, 10);
-- Some more special combinations with max and min
- in_ar <= TO_SVEC( c_max, g_in_dat_w); -- p*p - p*p + j ( p*p + p*p) = 0 + j 2pp or p*p + p*p + j (-p*p + p*p) = 2pp + j 0
+ -- p*p - p*p + j ( p*p + p*p) = 0 + j 2pp or p*p + p*p + j (-p*p + p*p) = 2pp + j 0
+ in_ar <= TO_SVEC( c_max, g_in_dat_w);
in_ai <= TO_SVEC( c_max, g_in_dat_w);
in_br <= TO_SVEC( c_max, g_in_dat_w);
in_bi <= TO_SVEC( c_max, g_in_dat_w);
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
index 811b71ec89ccee4aec11d0f464f4c09d4cc58ed4..5484df235757fbde98c8c422d865677f88d7f30e 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
@@ -36,7 +36,8 @@ use common_lib.tb_common_pkg.all;
entity tb_common_mult is
generic (
g_in_dat_w : natural := 7;
- g_out_dat_w : natural := 11; -- = 2*g_in_dat_w, or smaller to truncate MSbits, or larger to extend MSbits
+ -- = 2*g_in_dat_w, or smaller to truncate MSbits, or larger to extend MSbits
+ g_out_dat_w : natural := 11;
g_nof_mult : natural := 2;
g_pipeline_input : natural := 1;
g_pipeline_product : natural := 1;
@@ -47,7 +48,8 @@ end tb_common_mult;
architecture tb of tb_common_mult is
constant clk_period : time := 10 ns;
constant c_pipeline : natural := g_pipeline_input + g_pipeline_product + g_pipeline_output;
- constant c_nof_mult : natural := 2; -- fixed
+ -- fixed
+ constant c_nof_mult : natural := 2;
constant c_max_p : integer := 2**(g_in_dat_w - 1) - 1;
constant c_min : integer := -c_max_p;
@@ -56,7 +58,8 @@ architecture tb of tb_common_mult is
constant c_technology : natural := c_tech_select_default;
function func_sresult(in_a, in_b : std_logic_vector) return std_logic_vector is
- constant c_res_w : natural := 2 * g_in_dat_w; -- use sufficiently large result width
+ -- use sufficiently large result width
+ constant c_res_w : natural := 2 * g_in_dat_w;
variable v_a : std_logic_vector(g_in_dat_w - 1 downto 0);
variable v_b : std_logic_vector(g_in_dat_w - 1 downto 0);
variable v_result : signed(c_res_w - 1 downto 0);
@@ -65,11 +68,13 @@ architecture tb of tb_common_mult is
v_a := RESIZE_SVEC(in_a, g_in_dat_w);
v_b := RESIZE_SVEC(in_b, g_in_dat_w);
v_result := RESIZE_NUM(signed(v_a) * signed(v_b), c_res_w);
- return RESIZE_SVEC(std_logic_vector(v_result), g_out_dat_w); -- Truncate MSbits or sign extend MSBits
+ -- Truncate MSbits or sign extend MSBits
+ return RESIZE_SVEC(std_logic_vector(v_result), g_out_dat_w);
end;
function func_uresult(in_a, in_b : std_logic_vector) return std_logic_vector is
- constant c_res_w : natural := 2 * g_in_dat_w; -- use sufficiently large result width
+ -- use sufficiently large result width
+ constant c_res_w : natural := 2 * g_in_dat_w;
variable v_a : std_logic_vector(g_in_dat_w - 1 downto 0);
variable v_b : std_logic_vector(g_in_dat_w - 1 downto 0);
variable v_result : unsigned(c_res_w - 1 downto 0);
@@ -78,7 +83,8 @@ architecture tb of tb_common_mult is
v_a := RESIZE_UVEC(in_a, g_in_dat_w);
v_b := RESIZE_UVEC(in_b, g_in_dat_w);
v_result := RESIZE_NUM(unsigned(v_a) * unsigned(v_b), c_res_w);
- return RESIZE_UVEC(std_logic_vector(v_result), g_out_dat_w); -- Truncate MSbits or zero extend MSBits
+ -- Truncate MSbits or zero extend MSBits
+ return RESIZE_UVEC(std_logic_vector(v_result), g_out_dat_w);
end;
signal rst : std_logic;
@@ -92,18 +98,22 @@ architecture tb of tb_common_mult is
signal in_b_p : std_logic_vector(g_in_dat_w - 1 downto 0);
-- Product signals
- signal sresult_expected : std_logic_vector(g_out_dat_w - 1 downto 0); -- pipelined expected result
+ -- pipelined expected result
+ signal sresult_expected : std_logic_vector(g_out_dat_w - 1 downto 0);
signal sresult_rtl : std_logic_vector(g_out_dat_w - 1 downto 0);
signal sresult_ip : std_logic_vector(g_out_dat_w - 1 downto 0);
- signal uresult_expected : std_logic_vector(g_out_dat_w - 1 downto 0); -- pipelined expected result
+ -- pipelined expected result
+ signal uresult_expected : std_logic_vector(g_out_dat_w - 1 downto 0);
signal uresult_rtl : std_logic_vector(g_out_dat_w - 1 downto 0);
signal uresult_ip : std_logic_vector(g_out_dat_w - 1 downto 0);
-- auxiliary signals
signal in_a_arr : std_logic_vector(g_nof_mult * g_in_dat_w - 1 downto 0);
signal in_b_arr : std_logic_vector(g_nof_mult * g_in_dat_w - 1 downto 0);
- signal out_sresult : std_logic_vector(g_out_dat_w - 1 downto 0); -- combinatorial expected result
- signal out_uresult : std_logic_vector(g_out_dat_w - 1 downto 0); -- combinatorial expected result
+ -- combinatorial expected result
+ signal out_sresult : std_logic_vector(g_out_dat_w - 1 downto 0);
+ -- combinatorial expected result
+ signal out_uresult : std_logic_vector(g_out_dat_w - 1 downto 0);
signal sresult_arr_expected : std_logic_vector(g_nof_mult * g_out_dat_w - 1 downto 0);
signal uresult_arr_expected : std_logic_vector(g_nof_mult * g_out_dat_w - 1 downto 0);
signal sresult_arr_rtl : std_logic_vector(g_nof_mult * g_out_dat_w - 1 downto 0);
@@ -127,19 +137,24 @@ begin
in_a <= TO_SVEC(2, g_in_dat_w);
in_b <= TO_SVEC(3, g_in_dat_w);
wait until rising_edge(clk);
- in_a <= TO_SVEC(c_max_p, g_in_dat_w); -- p*p = pp
+ -- p*p = pp
+ in_a <= TO_SVEC(c_max_p, g_in_dat_w);
in_b <= TO_SVEC(c_max_p, g_in_dat_w);
wait until rising_edge(clk);
- in_a <= TO_SVEC(c_max_n, g_in_dat_w); -- -p*-p = pp
+ -- -p*-p = pp
+ in_a <= TO_SVEC(c_max_n, g_in_dat_w);
in_b <= TO_SVEC(c_max_n, g_in_dat_w);
wait until rising_edge(clk);
- in_a <= TO_SVEC(c_max_p, g_in_dat_w); -- p*-p = = -pp
+ -- p*-p = = -pp
+ in_a <= TO_SVEC(c_max_p, g_in_dat_w);
in_b <= TO_SVEC(c_max_n, g_in_dat_w);
wait until rising_edge(clk);
- in_a <= TO_SVEC(c_max_p, g_in_dat_w); -- p*(-p-1) = -pp - p
+ -- p*(-p-1) = -pp - p
+ in_a <= TO_SVEC(c_max_p, g_in_dat_w);
in_b <= TO_SVEC(c_min, g_in_dat_w);
wait until rising_edge(clk);
- in_a <= TO_SVEC(c_max_n, g_in_dat_w); -- -p*(-p-1) = pp + p
+ -- -p*(-p-1) = pp + p
+ in_a <= TO_SVEC(c_max_n, g_in_dat_w);
in_b <= TO_SVEC(c_min, g_in_dat_w);
wait until rising_edge(clk);
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
index b2e150e364f970ccc4aa55aaf78c046ef66dbde4..57d79211816f4545a9125bb8af2aac9528f39099 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
@@ -37,9 +37,12 @@ entity tb_common_mult_add2 is
g_technology : natural := c_tech_select_default;
g_variant : string := "RTL";
g_in_dat_w : natural := 5;
- g_out_dat_w : natural := 11; -- 2*g_in_dat_w+1
- g_force_dsp : boolean := true; -- when TRUE resize input width to >= 18 for 'stratix4'
- g_add_sub : string := "ADD"; -- or "SUB"
+ -- 2*g_in_dat_w+1
+ g_out_dat_w : natural := 11;
+ -- when TRUE resize input width to >= 18 for 'stratix4'
+ g_force_dsp : boolean := true;
+ -- or "SUB"
+ g_add_sub : string := "ADD";
g_pipeline_input : natural := 1;
g_pipeline_product : natural := 0;
g_pipeline_adder : natural := 1;
@@ -50,7 +53,8 @@ end tb_common_mult_add2;
architecture tb of tb_common_mult_add2 is
constant clk_period : time := 10 ns;
constant c_pipeline : natural := g_pipeline_input + g_pipeline_product + g_pipeline_adder + g_pipeline_output;
- constant c_nof_mult : natural := 2; -- fixed
+ -- fixed
+ constant c_nof_mult : natural := 2;
constant c_max_p : integer := 2**(g_in_dat_w - 1) - 1;
constant c_min : integer := -c_max_p;
@@ -61,7 +65,8 @@ architecture tb of tb_common_mult_add2 is
-- . SIGNED * --> output width = 2 * input width
-- . SIGNED + --> output width = largest(input width)
constant c_in_w : natural := g_in_dat_w;
- constant c_res_w : natural := 2 * g_in_dat_w + ceil_log2(c_nof_mult); -- use sufficiently large result width
+ -- use sufficiently large result width
+ constant c_res_w : natural := 2 * g_in_dat_w + ceil_log2(c_nof_mult);
variable v_a0 : signed(c_in_w - 1 downto 0);
variable v_b0 : signed(c_in_w - 1 downto 0);
variable v_a1 : signed(c_in_w - 1 downto 0);
@@ -91,8 +96,10 @@ architecture tb of tb_common_mult_add2 is
signal in_a : std_logic_vector(c_nof_mult * g_in_dat_w - 1 downto 0);
signal in_b : std_logic_vector(c_nof_mult * g_in_dat_w - 1 downto 0);
- signal out_result : std_logic_vector(g_out_dat_w - 1 downto 0); -- combinatorial result
- signal result_expected : std_logic_vector(g_out_dat_w - 1 downto 0); -- pipelined results
+ -- combinatorial result
+ signal out_result : std_logic_vector(g_out_dat_w - 1 downto 0);
+ -- pipelined results
+ signal result_expected : std_logic_vector(g_out_dat_w - 1 downto 0);
signal result_rtl : std_logic_vector(g_out_dat_w - 1 downto 0);
begin
clk <= not clk or tb_end after clk_period / 2;
@@ -120,27 +127,32 @@ begin
in_a1 <= TO_SVEC(4, g_in_dat_w);
in_b1 <= TO_SVEC(5, g_in_dat_w);
wait until rising_edge(clk);
- in_a0 <= TO_SVEC(c_max_p, g_in_dat_w); -- p*p + p*p = 2pp
+ -- p*p + p*p = 2pp
+ in_a0 <= TO_SVEC(c_max_p, g_in_dat_w);
in_b0 <= TO_SVEC(c_max_p, g_in_dat_w);
in_a1 <= TO_SVEC(c_max_p, g_in_dat_w);
in_b1 <= TO_SVEC(c_max_p, g_in_dat_w);
wait until rising_edge(clk);
- in_a0 <= TO_SVEC(c_max_n, g_in_dat_w); -- -p*-p + -p*-p = -2pp
+ -- -p*-p + -p*-p = -2pp
+ in_a0 <= TO_SVEC(c_max_n, g_in_dat_w);
in_b0 <= TO_SVEC(c_max_n, g_in_dat_w);
in_a1 <= TO_SVEC(c_max_n, g_in_dat_w);
in_b1 <= TO_SVEC(c_max_n, g_in_dat_w);
wait until rising_edge(clk);
- in_a0 <= TO_SVEC(c_max_p, g_in_dat_w); -- p*-p + p*-p = = -2pp
+ -- p*-p + p*-p = = -2pp
+ in_a0 <= TO_SVEC(c_max_p, g_in_dat_w);
in_b0 <= TO_SVEC(c_max_n, g_in_dat_w);
in_a1 <= TO_SVEC(c_max_p, g_in_dat_w);
in_b1 <= TO_SVEC(c_max_n, g_in_dat_w);
wait until rising_edge(clk);
- in_a0 <= TO_SVEC(c_max_p, g_in_dat_w); -- p*(-p-1)_ + p*(-p-1) = -(2pp + 2p)
+ -- p*(-p-1)_ + p*(-p-1) = -(2pp + 2p)
+ in_a0 <= TO_SVEC(c_max_p, g_in_dat_w);
in_b0 <= TO_SVEC(c_min, g_in_dat_w);
in_a1 <= TO_SVEC(c_max_p, g_in_dat_w);
in_b1 <= TO_SVEC(c_min, g_in_dat_w);
wait until rising_edge(clk);
- in_a0 <= TO_SVEC(c_max_n, g_in_dat_w); -- -p*(-p-1)_ + -p*(-p-1) = 2pp + 2p
+ -- -p*(-p-1)_ + -p*(-p-1) = 2pp + 2p
+ in_a0 <= TO_SVEC(c_max_n, g_in_dat_w);
in_b0 <= TO_SVEC(c_min, g_in_dat_w);
in_a1 <= TO_SVEC(c_max_n, g_in_dat_w);
in_b1 <= TO_SVEC(c_min, g_in_dat_w);
@@ -194,8 +206,10 @@ begin
generic map (
g_in_a_w => g_in_dat_w,
g_in_b_w => g_in_dat_w,
- g_res_w => g_out_dat_w, -- g_in_a_w + g_in_b_w + log2(2)
- g_force_dsp => g_force_dsp, -- not applicable for 'rtl'
+ -- g_in_a_w + g_in_b_w + log2(2)
+ g_res_w => g_out_dat_w,
+ -- not applicable for 'rtl'
+ g_force_dsp => g_force_dsp,
g_add_sub => g_add_sub,
g_nof_mult => 2,
g_pipeline_input => g_pipeline_input,
diff --git a/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
index a8b7dfd246c23d01cad3ff677bd4397cfa55d4c2..27975ec061956b32067005ffc07cdc2774ad1e1b 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
@@ -34,7 +34,8 @@ entity tb_tb_common_complex_mult is
end tb_tb_common_complex_mult;
architecture tb of tb_tb_common_complex_mult is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_variant : STRING := "IP";
-- g_in_dat_w : NATURAL := 4;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
index d08b84661010615219ddb40fb60a75f2f8d6e2ce..392e2df807f2304f43afd3223270e287fdea74c0 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
@@ -30,7 +30,8 @@ entity tb_tb_common_mult is
end tb_tb_common_mult;
architecture tb of tb_tb_common_mult is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_in_dat_w : NATURAL := 7;
-- g_out_dat_w : NATURAL := 11; -- = 2*g_in_dat_w, or smaller to truncate MSbits, or larger to extend MSbits
@@ -40,10 +41,14 @@ begin
-- g_pipeline_output : NATURAL := 1
-- Vary g_out_dat_w
- u_mult_7_12_nof_2_pipe_1_1_1 : entity work.tb_common_mult generic map (7, 12, 2, 1, 1, 1); -- truncate extra bit
- u_mult_7_13_nof_2_pipe_1_1_1 : entity work.tb_common_mult generic map (7, 13, 2, 1, 1, 1); -- truncate double sign bit
- u_mult_7_14_nof_2_pipe_1_1_1 : entity work.tb_common_mult generic map (7, 14, 2, 1, 1, 1); -- preserve full product range
- u_mult_7_15_nof_2_pipe_1_1_1 : entity work.tb_common_mult generic map (7, 15, 2, 1, 1, 1); -- extend product
+ -- truncate extra bit
+ u_mult_7_12_nof_2_pipe_1_1_1 : entity work.tb_common_mult generic map (7, 12, 2, 1, 1, 1);
+ -- truncate double sign bit
+ u_mult_7_13_nof_2_pipe_1_1_1 : entity work.tb_common_mult generic map (7, 13, 2, 1, 1, 1);
+ -- preserve full product range
+ u_mult_7_14_nof_2_pipe_1_1_1 : entity work.tb_common_mult generic map (7, 14, 2, 1, 1, 1);
+ -- extend product
+ u_mult_7_15_nof_2_pipe_1_1_1 : entity work.tb_common_mult generic map (7, 15, 2, 1, 1, 1);
-- Vary g_nof_mult
u_mult_7_11_nof_1_pipe_1_1_1 : entity work.tb_common_mult generic map (7, 11, 1, 1, 1, 1);
diff --git a/libraries/base/diag/src/vhdl/diag_block_gen.vhd b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
index 7163a9b310a821795ca5beac075d067d72bf765b..a10a00af11c0d0e0eaef41ca080d28a168525fb9 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
@@ -81,7 +81,8 @@ use dp_lib.dp_stream_pkg.all;
entity diag_block_gen is
generic (
- g_blk_sync : boolean := false; -- when true use active sync during entire block, else use single clock cycle sync pulse
+ -- when true use active sync during entire block, else use single clock cycle sync pulse
+ g_blk_sync : boolean := false;
g_buf_dat_w : natural := 32;
g_buf_addr_w : natural := 7
);
@@ -93,7 +94,8 @@ entity diag_block_gen is
buf_rddat : in std_logic_vector(g_buf_dat_w - 1 downto 0);
buf_rdval : in std_logic;
ctrl : in t_diag_block_gen;
- ctrl_hold : out t_diag_block_gen; -- hold current active ctrl
+ -- hold current active ctrl
+ ctrl_hold : out t_diag_block_gen;
en_sync : in std_logic := '1';
out_siso : in t_dp_siso := c_dp_siso_rdy;
out_sosi : out t_dp_sosi
@@ -104,24 +106,32 @@ architecture rtl of diag_block_gen is
type state_type is (s_idle, s_block, s_gap);
type reg_type is record
- ctrl_hold : t_diag_block_gen; -- capture ctrl
- blk_en : std_logic; -- enable at block level
- blk_xon : std_logic; -- siso.xon at block level, the BG continues but the sosi control depend on xon (the BG does not support siso.ready)
- blk_sync : std_logic; -- block sync alternative of the pulse sync
- pls_sync : std_logic; -- pulse sync
+ -- capture ctrl
+ ctrl_hold : t_diag_block_gen;
+ -- enable at block level
+ blk_en : std_logic;
+ -- siso.xon at block level, the BG continues but the sosi control depend on xon (the BG does not support siso.ready)
+ blk_xon : std_logic;
+ -- block sync alternative of the pulse sync
+ blk_sync : std_logic;
+ -- pulse sync
+ pls_sync : std_logic;
valid : std_logic;
sop : std_logic;
eop : std_logic;
rd_ena : std_logic;
samples_cnt : natural range 0 to 2**c_diag_bg_gapsize_w - 1;
blocks_cnt : natural range 0 to 2**c_diag_bg_blocks_per_sync_w - 1;
- bsn_cnt : std_logic_vector(c_diag_bg_bsn_init_w - 1 downto 0); -- = c_dp_stream_bsn_w
+ -- = c_dp_stream_bsn_w
+ bsn_cnt : std_logic_vector(c_diag_bg_bsn_init_w - 1 downto 0);
mem_cnt : natural range 0 to 2**g_buf_addr_w - 1;
- state : state_type; -- The state machine.
+ -- The state machine.
+ state : state_type;
end record;
signal r, rin : reg_type;
- signal out_sosi_i : t_dp_sosi := c_dp_sosi_rst; -- Signal used to assign reset values to output
+ -- Signal used to assign reset values to output
+ signal out_sosi_i : t_dp_sosi := c_dp_sosi_rst;
signal xon_reg : std_logic := '0';
begin
-- xon is not clk cycle timing critical, so can use register xon to ease timing closure
@@ -141,7 +151,8 @@ begin
v_mem_low_adrs := TO_UINT(r.ctrl_hold.mem_low_adrs);
v_mem_high_adrs := TO_UINT(r.ctrl_hold.mem_high_adrs);
- v := r; -- default hold all r fields
+ -- default hold all r fields
+ v := r;
v.pls_sync := '0';
v.valid := '0';
v.sop := '0';
@@ -176,9 +187,12 @@ begin
v.samples_cnt := 0;
v.blocks_cnt := 0;
v.mem_cnt := v_mem_low_adrs;
- if r.blk_en = '1' then -- Wait until enabled
- if xon_reg = '1' then -- Wait until XON is 1
- v.ctrl_hold := ctrl; -- hold new control settings while BG is enabled
+ -- Wait until enabled
+ if r.blk_en = '1' then
+ -- Wait until XON is 1
+ if xon_reg = '1' then
+ -- hold new control settings while BG is enabled
+ v.ctrl_hold := ctrl;
v.bsn_cnt := ctrl.bsn_init;
v.rd_ena := '1';
v.state := s_block;
@@ -188,9 +202,11 @@ begin
when s_block =>
if out_siso.ready = '1' then
- v.rd_ena := '1'; -- read next data
+ -- read next data
+ v.rd_ena := '1';
if r.samples_cnt = 0 and r.blocks_cnt = 0 then
- v.pls_sync := '1'; -- Always start with a pulse sync
+ -- Always start with a pulse sync
+ v.pls_sync := '1';
v.blk_sync := '1';
v.sop := '1';
v.samples_cnt := v.samples_cnt + 1;
@@ -213,7 +229,8 @@ begin
else
v.samples_cnt := r.samples_cnt + 1;
end if;
- v.valid := '1'; -- output pending data
+ -- output pending data
+ v.valid := '1';
if r.mem_cnt >= v_mem_high_adrs then
v.mem_cnt := v_mem_low_adrs;
@@ -222,11 +239,14 @@ begin
end if;
if v.eop = '1' and r.blk_en = '0' then
- v.state := s_idle; -- accept disable after eop, not during block
+ -- accept disable after eop, not during block
+ v.state := s_idle;
end if;
- end if; -- out_siso.ready='1'
+ -- out_siso.ready='1'
+ end if;
if r.eop = '1' then
- v.blk_xon := xon_reg; -- accept XOFF after eop, not during block
+ -- accept XOFF after eop, not during block
+ v.blk_xon := xon_reg;
end if;
when s_gap =>
@@ -286,9 +306,12 @@ begin
out_sosi_i.sync <= r.pls_sync and r.blk_xon when g_blk_sync = false else r.blk_sync and r.blk_xon;
out_sosi_i.valid <= r.valid and r.blk_xon;
out_sosi_i.bsn <= r.bsn_cnt;
- out_sosi_i.re <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w / 2 - 1 downto 0)); -- treat as signed
- out_sosi_i.im <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w - 1 downto g_buf_dat_w / 2)); -- treat as signed
- out_sosi_i.data <= RESIZE_DP_DATA( buf_rddat(g_buf_dat_w - 1 downto 0)); -- treat as unsigned
+ -- treat as signed
+ out_sosi_i.re <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w / 2 - 1 downto 0));
+ -- treat as signed
+ out_sosi_i.im <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w - 1 downto g_buf_dat_w / 2));
+ -- treat as unsigned
+ out_sosi_i.data <= RESIZE_DP_DATA( buf_rddat(g_buf_dat_w - 1 downto 0));
out_sosi <= out_sosi_i;
buf_addr <= TO_UVEC(r.mem_cnt, g_buf_addr_w);
diff --git a/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd b/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
index 018ca44aef18e5794d40feaa22ddabc49ca2b3a5..4bd6ba522e90d0e1fd1a74a59e30c2bcd01b20b5 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
@@ -28,15 +28,18 @@ use work.diag_pkg.all;
entity diag_block_gen_reg is
generic (
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
g_diag_block_gen_rst : t_diag_block_gen := c_diag_block_gen_rst
);
port (
- mm_rst : in std_logic; -- Clocks and reset
+ -- Clocks and reset
+ mm_rst : in std_logic;
mm_clk : in std_logic;
dp_rst : in std_logic := '0';
dp_clk : in std_logic;
- mm_mosi : in t_mem_mosi; -- Memory Mapped Slave in mm_clk domain
+ -- Memory Mapped Slave in mm_clk domain
+ mm_mosi : in t_mem_mosi;
mm_miso : out t_mem_miso := c_mem_miso_rst;
bg_ctrl : out t_diag_block_gen := g_diag_block_gen_rst
);
@@ -83,11 +86,13 @@ begin
mm_bg_ctrl.bsn_init(31 downto 0) <= mm_mosi.wrdata(31 downto 0);
when 7 =>
mm_bg_ctrl.bsn_init(63 downto 32) <= mm_mosi.wrdata(31 downto 0);
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif mm_mosi.rd = '1' then
- mm_miso <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
+ -- set unused rddata bits to '0' when read
+ mm_miso <= c_mem_miso_rst;
mm_miso.rdval <= '1';
case TO_UINT(mm_mosi.address(c_adrs_width - 1 downto 0)) is
-- Read Block Sync
@@ -108,7 +113,8 @@ begin
mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(31 downto 0);
when 7 =>
mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(63 downto 32);
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
end if;
end if;
@@ -133,7 +139,8 @@ begin
no_cross : if g_cross_clock_domain = false generate
dp_bg_ctrl <= mm_bg_ctrl;
- end generate; -- no_cross
+ -- no_cross
+ end generate;
gen_crossing : if g_cross_clock_domain = true generate
-- Assume diag BG enable gets written last, so when diag BG enable is transfered properly to the dp_clk domain, then
@@ -155,7 +162,8 @@ begin
dp_bg_ctrl.mem_low_adrs <= mm_bg_ctrl.mem_low_adrs;
dp_bg_ctrl.mem_high_adrs <= mm_bg_ctrl.mem_high_adrs;
dp_bg_ctrl.bsn_init <= mm_bg_ctrl.bsn_init;
- end generate; -- gen_crossing
+ -- gen_crossing
+ end generate;
bg_ctrl <= dp_bg_ctrl;
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
index f0211b988e02efcb26a0db4e683659a837eb458c..8214037be1563ff0260d00642813713589a3eced 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
@@ -56,14 +56,16 @@ entity diag_data_buffer is
g_technology : natural := c_tech_select_default;
g_data_w : natural := 32;
g_nof_data : natural := 1024;
- g_use_in_sync : boolean := false -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ g_use_in_sync : boolean := false
);
port (
-- Memory-mapped clock domain
mm_rst : in std_logic;
mm_clk : in std_logic;
- ram_mm_mosi : in t_mem_mosi; -- read and overwrite access to the data buffer
+ -- read and overwrite access to the data buffer
+ ram_mm_mosi : in t_mem_mosi;
ram_mm_miso : out t_mem_miso;
reg_mm_mosi : in t_mem_mosi := c_mem_mosi_rst;
@@ -80,7 +82,8 @@ entity diag_data_buffer is
end diag_data_buffer;
architecture rtl of diag_data_buffer is
- constant c_mm_factor : natural := ceil_div(g_data_w, c_word_w); -- must be a power of 2 multiple
+ -- must be a power of 2 multiple
+ constant c_mm_factor : natural := ceil_div(g_data_w, c_word_w);
constant c_nof_data_mm : natural := g_nof_data * c_mm_factor;
constant g_data_mm_w : natural := g_data_w / c_mm_factor;
@@ -99,11 +102,14 @@ architecture rtl of diag_data_buffer is
constant c_reg : t_c_mem := (latency => 1,
adr_w => c_diag_db_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_diag_db_reg_nof_dat, -- 1: word_cnt; 0:sync_cnt
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
+ -- 1: word_cnt; 0:sync_cnt
+ nof_dat => c_diag_db_reg_nof_dat,
init_sl => '0');
- signal i_ram_mm_miso : t_mem_miso := c_mem_miso_rst; -- used to avoid vsim-8684 error "No drivers exist" for the unused fields
+ -- used to avoid vsim-8684 error "No drivers exist" for the unused fields
+ signal i_ram_mm_miso : t_mem_miso := c_mem_miso_rst;
signal rd_last : std_logic;
signal wr_sync : std_logic;
@@ -122,7 +128,8 @@ architecture rtl of diag_data_buffer is
signal reg_slv : std_logic_vector(c_reg.nof_dat * c_word_w - 1 downto 0);
signal sync_cnt_clr : std_logic := '0';
- signal sync_cnt : std_logic_vector(c_word_w - 1 downto 0); -- Nof times buffer has been written
+ -- Nof times buffer has been written
+ signal sync_cnt : std_logic_vector(c_word_w - 1 downto 0);
signal word_cnt : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
begin
assert c_mm_factor = 2**true_log2(c_mm_factor) report "Only support mixed width data that uses a power of 2 multiple." severity FAILURE;
@@ -148,7 +155,8 @@ begin
end generate;
use_in_sync : if g_use_in_sync = true generate
- sync_cnt_clr <= rd_last; -- clear sync_cnt register on read of last data
+ -- clear sync_cnt register on read of last data
+ sync_cnt_clr <= rd_last;
wr_sync <= in_sync;
end generate;
@@ -180,7 +188,8 @@ begin
nxt_wr_addr <= (others => '0');
elsif wr_en = '1' then
if unsigned(wr_addr) = g_nof_data - 1 then
- nxt_wr_done <= '1'; -- keep wr_addr, do not allow wr_addr increment >= g_nof_data to avoid RAM address out-of-bound warning in Modelsim in case c_buf.nof_dat < 2**c_buf.adr_w
+ -- keep wr_addr, do not allow wr_addr increment >= g_nof_data to avoid RAM address out-of-bound warning in Modelsim in case c_buf.nof_dat < 2**c_buf.adr_w
+ nxt_wr_done <= '1';
else
nxt_wr_addr <= INCR_UVEC(wr_addr, 1);
end if;
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
index 278e607ea21c93de95a9e902c8e8020b5a4aa49a..13947347c55655517e21c496891517bcd136eb65 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
@@ -77,14 +77,16 @@ entity diag_data_buffer_dev is
g_technology : natural := c_tech_select_default;
g_data_w : natural := 32;
g_nof_data : natural := 1024;
- g_use_in_sync : boolean := false -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ g_use_in_sync : boolean := false
);
port (
-- Memory-mapped clock domain
mm_rst : in std_logic;
mm_clk : in std_logic;
- ram_mm_mosi : in t_mem_mosi; -- read and overwrite access to the data buffer
+ -- read and overwrite access to the data buffer
+ ram_mm_mosi : in t_mem_mosi;
ram_mm_miso : out t_mem_miso;
reg_mm_mosi : in t_mem_mosi := c_mem_mosi_rst;
@@ -104,7 +106,8 @@ end diag_data_buffer_dev;
architecture rtl of diag_data_buffer_dev is
constant c_version : natural := 1;
- constant c_mm_factor : natural := ceil_div(g_data_w, c_word_w); -- must be a power of 2 multiple
+ -- must be a power of 2 multiple
+ constant c_mm_factor : natural := ceil_div(g_data_w, c_word_w);
constant c_nof_data_mm : natural := g_nof_data * c_mm_factor;
constant g_data_mm_w : natural := g_data_w / c_mm_factor;
@@ -122,11 +125,14 @@ architecture rtl of diag_data_buffer_dev is
constant c_reg : t_c_mem := (latency => 1,
adr_w => c_diag_db_dev_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_diag_db_dev_reg_nof_dat, -- 3: reg_sync_delay 2: valid_cnt 1: word_cnt; 0:sync_cnt
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
+ -- 3: reg_sync_delay 2: valid_cnt 1: word_cnt; 0:sync_cnt
+ nof_dat => c_diag_db_dev_reg_nof_dat,
init_sl => '0');
- signal i_ram_mm_miso : t_mem_miso := c_mem_miso_rst; -- used to avoid vsim-8684 error "No drivers exist" for the unused fields
+ -- used to avoid vsim-8684 error "No drivers exist" for the unused fields
+ signal i_ram_mm_miso : t_mem_miso := c_mem_miso_rst;
signal rd_last : std_logic;
signal rd_last_st : std_logic;
@@ -149,7 +155,8 @@ architecture rtl of diag_data_buffer_dev is
signal arm_enable : std_logic := '0';
signal sync_cnt_clr : std_logic := '0';
- signal sync_cnt : std_logic_vector(c_word_w - 1 downto 0); -- Nof times buffer has been written
+ -- Nof times buffer has been written
+ signal sync_cnt : std_logic_vector(c_word_w - 1 downto 0);
signal word_cnt : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
signal valid_cnt : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
signal reg_sync_delay : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
@@ -158,7 +165,8 @@ architecture rtl of diag_data_buffer_dev is
type reg_type is record
wr_sync : std_logic;
- state : state_type; -- The state machine.
+ -- The state machine.
+ state : state_type;
end record;
signal r, rin : reg_type;
@@ -276,7 +284,8 @@ begin
nxt_wr_addr <= (others => '0');
elsif wr_en = '1' then
if unsigned(wr_addr) = g_nof_data - 1 then
- nxt_wr_done <= '1'; -- keep wr_addr, do not allow wr_addr increment >= g_nof_data to avoid RAM address out-of-bound warning in Modelsim in case c_buf.nof_dat < 2**c_buf.adr_w
+ -- keep wr_addr, do not allow wr_addr increment >= g_nof_data to avoid RAM address out-of-bound warning in Modelsim in case c_buf.nof_dat < 2**c_buf.adr_w
+ nxt_wr_done <= '1';
else
nxt_wr_addr <= INCR_UVEC(wr_addr, 1);
end if;
diff --git a/libraries/base/diag/src/vhdl/diag_frm_generator.vhd b/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
index cccb660269ccd0b07ac18b1f035d3a4168cc7ede..d0edd1636d988c47806966a6c68789210f31e2ee 100644
--- a/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
+++ b/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
@@ -38,14 +38,20 @@ use common_lib.common_pkg.all;
entity diag_frm_generator is
generic (
- g_sel : std_logic := '1'; -- '0' = PRSG, '1' = COUNTER
- g_frame_len : natural := 2; -- >= 2, test frame length in nof dat words
- g_sof_period : natural := 1; -- >= 1, nof cycles between sop that start a frame, typically >> g_frame_len
+ -- '0' = PRSG, '1' = COUNTER
+ g_sel : std_logic := '1';
+ -- >= 2, test frame length in nof dat words
+ g_frame_len : natural := 2;
+ -- >= 1, nof cycles between sop that start a frame, typically >> g_frame_len
+ g_sof_period : natural := 1;
-- to generate frames with idle in between
g_frame_cnt_w : natural := 32;
- g_dat_w : natural := 16; -- >= 1, test data width
- g_symbol_w : natural := 16; -- >= 1, and nof_symbols_per_dat = g_dat_w/g_symbol_w, must be an integer
- g_empty : natural := 0 -- >= 0 and < nof symbols per dat,
+ -- >= 1, test data width
+ g_dat_w : natural := 16;
+ -- >= 1, and nof_symbols_per_dat = g_dat_w/g_symbol_w, must be an integer
+ g_symbol_w : natural := 16;
+ -- >= 0 and < nof symbols per dat,
+ g_empty : natural := 0
);
port (
rst : in std_logic;
@@ -54,29 +60,39 @@ entity diag_frm_generator is
-- Static control input (connect via MM or leave open to use default)
diag_en : in std_logic;
- diag_sel : in std_logic := g_sel; -- '0' = PRSG sequence data, '1' = COUNTER sequence data
- diag_dc : in std_logic := '0'; -- '0' = output diag_sel sequence data, '1' = output constant diag_init data
+ -- '0' = PRSG sequence data, '1' = COUNTER sequence data
+ diag_sel : in std_logic := g_sel;
+ -- '0' = output diag_sel sequence data, '1' = output constant diag_init data
+ diag_dc : in std_logic := '0';
diag_frame_len : in std_logic_vector(ceil_log2(g_frame_len) - 1 downto 0) := TO_UVEC(g_frame_len, ceil_log2(g_frame_len));
diag_frame_empty : in std_logic_vector(ceil_log2(g_dat_w / g_symbol_w) - 1 downto 0) := TO_UVEC(g_empty, ceil_log2(g_dat_w / g_symbol_w));
diag_sof_period : in std_logic_vector(ceil_log2(g_sof_period) - 1 downto 0) := TO_UVEC(g_sof_period, ceil_log2(g_sof_period));
diag_frame_cnt : out std_logic_vector(g_frame_cnt_w - 1 downto 0);
-- ST output
- out_ready : in std_logic := '1'; -- '1' = request ST test data output, '0' = halt ST test data output
- out_dat : out std_logic_vector(g_dat_w - 1 downto 0); -- test sequence data
- out_val : out std_logic; -- '1' when out_data is valid
- out_sop : out std_logic; -- '1' for first valid frame data
- out_eop : out std_logic; -- '1' for last valid frame data
- out_empty : out std_logic_vector(ceil_log2(g_dat_w / g_symbol_w) - 1 downto 0) -- nof empty symbols in last out_dat word marked by out_eop
+ -- '1' = request ST test data output, '0' = halt ST test data output
+ out_ready : in std_logic := '1';
+ -- test sequence data
+ out_dat : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- '1' when out_data is valid
+ out_val : out std_logic;
+ -- '1' for first valid frame data
+ out_sop : out std_logic;
+ -- '1' for last valid frame data
+ out_eop : out std_logic;
+ -- nof empty symbols in last out_dat word marked by out_eop
+ out_empty : out std_logic_vector(ceil_log2(g_dat_w / g_symbol_w) - 1 downto 0)
);
end diag_frm_generator;
architecture str of diag_frm_generator is
- constant c_init : natural := 0; -- first data word of first frame that is generated after diag_en = '1'
+ -- first data word of first frame that is generated after diag_en = '1'
+ constant c_init : natural := 0;
constant c_frame_len_w : natural := ceil_log2(g_frame_len);
signal diag_en_revt : std_logic;
- signal diag_init : std_logic_vector(g_dat_w - 1 downto 0) := TO_UVEC(c_init, g_dat_w); -- init data for out_dat when diag_sop = '1'
+ -- init data for out_dat when diag_sop = '1'
+ signal diag_init : std_logic_vector(g_dat_w - 1 downto 0) := TO_UVEC(c_init, g_dat_w);
signal nxt_diag_init : std_logic_vector(diag_init'range);
signal diag_sop : std_logic;
signal diag_ready : std_logic;
diff --git a/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd b/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
index 1993a7509844865d3d8727e06c807a64d203b910..7eea3be01e3997da2a9c407a85e56bcb7f108681 100644
--- a/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
+++ b/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
@@ -56,8 +56,10 @@ entity diag_frm_monitor is
diag_error_cnt : out std_logic_vector(g_frame_cnt_w - 1 downto 0);
-- ST input
- in_eop : in std_logic; -- '1' for last valid frame data
- in_error : in std_logic -- '1' when received frame contained an error, '0' when OK
+ -- '1' for last valid frame data
+ in_eop : in std_logic;
+ -- '1' when received frame contained an error, '0' when OK
+ in_error : in std_logic
);
end diag_frm_monitor;
diff --git a/libraries/base/diag/src/vhdl/diag_pkg.vhd b/libraries/base/diag/src/vhdl/diag_pkg.vhd
index 8f88945551725e4a93ed9d88fd2714e027a73f0e..cb16ee75ce98ceef96a3daf37b0aba8a76d3de13 100644
--- a/libraries/base/diag/src/vhdl/diag_pkg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_pkg.vhd
@@ -29,25 +29,41 @@ package diag_pkg is
-- PHY interface tests (e.g. for ethernet, transceivers, lvds, memory)
-----------------------------------------------------------------------------
- constant c_diag_test_mode_no_tst : natural := 0; -- no test, the PHY interface runs in normal user mode
- constant c_diag_test_mode_loop_local : natural := 1; -- loop back via PHY chip
- constant c_diag_test_mode_loop_remote : natural := 2; -- loop back via loopback cable or plug in the connector
- constant c_diag_test_mode_tx : natural := 4; -- transmit only
- constant c_diag_test_mode_rx : natural := 5; -- receive only
- constant c_diag_test_mode_tx_rx : natural := 6; -- transmit and receive
-
- constant c_diag_test_data_lfsr : natural := 0; -- use pseudo random data
- constant c_diag_test_data_incr : natural := 1; -- use incrementing counter data
-
- constant c_diag_test_duration_quick : natural := 0; -- end Rx test after 1 data frame or word, end Tx test after correspondingly sufficient data frames or words transmitted, or all memory lines
- constant c_diag_test_duration_normal : natural := 1; -- idem for e.g. 100 data frames or words, or full memory
- constant c_diag_test_duration_extra : natural := 2; -- idem for e.g. 100000 data frames or words
-
- constant c_diag_test_result_ok : natural := 0; -- test went OK
- constant c_diag_test_result_none : natural := 1; -- test did not run, default
- constant c_diag_test_result_timeout : natural := 2; -- test started but no valid data was received
- constant c_diag_test_result_error : natural := 3; -- test received valid data, but the value was wrong for one or more
- constant c_diag_test_result_illegal : natural := 4; -- exception, condition that can not occur in the logic
+ -- no test, the PHY interface runs in normal user mode
+ constant c_diag_test_mode_no_tst : natural := 0;
+ -- loop back via PHY chip
+ constant c_diag_test_mode_loop_local : natural := 1;
+ -- loop back via loopback cable or plug in the connector
+ constant c_diag_test_mode_loop_remote : natural := 2;
+ -- transmit only
+ constant c_diag_test_mode_tx : natural := 4;
+ -- receive only
+ constant c_diag_test_mode_rx : natural := 5;
+ -- transmit and receive
+ constant c_diag_test_mode_tx_rx : natural := 6;
+
+ -- use pseudo random data
+ constant c_diag_test_data_lfsr : natural := 0;
+ -- use incrementing counter data
+ constant c_diag_test_data_incr : natural := 1;
+
+ -- end Rx test after 1 data frame or word, end Tx test after correspondingly sufficient data frames or words transmitted, or all memory lines
+ constant c_diag_test_duration_quick : natural := 0;
+ -- idem for e.g. 100 data frames or words, or full memory
+ constant c_diag_test_duration_normal : natural := 1;
+ -- idem for e.g. 100000 data frames or words
+ constant c_diag_test_duration_extra : natural := 2;
+
+ -- test went OK
+ constant c_diag_test_result_ok : natural := 0;
+ -- test did not run, default
+ constant c_diag_test_result_none : natural := 1;
+ -- test started but no valid data was received
+ constant c_diag_test_result_timeout : natural := 2;
+ -- test received valid data, but the value was wrong for one or more
+ constant c_diag_test_result_error : natural := 3;
+ -- exception, condition that can not occur in the logic
+ constant c_diag_test_result_illegal : natural := 4;
-----------------------------------------------------------------------------
-- Waveform Generator
@@ -55,10 +71,14 @@ package diag_pkg is
-- control register
constant c_diag_wg_mode_w : natural := 8;
- constant c_diag_wg_nofsamples_w : natural := 16; -- >~ minimum data path block size
- constant c_diag_wg_phase_w : natural := 16; -- = c_diag_wg_nofsamples_w
- constant c_diag_wg_freq_w : natural := 31; -- >> c_diag_wg_nofsamples_w, determines the minimum frequency = Fs / 2**c_diag_wg_freq_w
- constant c_diag_wg_ampl_w : natural := 17; -- Typically fit DSP multiply 18x18 element so use <= 17, to fit unsigned in 18 bit signed,
+ -- >~ minimum data path block size
+ constant c_diag_wg_nofsamples_w : natural := 16;
+ -- = c_diag_wg_nofsamples_w
+ constant c_diag_wg_phase_w : natural := 16;
+ -- >> c_diag_wg_nofsamples_w, determines the minimum frequency = Fs / 2**c_diag_wg_freq_w
+ constant c_diag_wg_freq_w : natural := 31;
+ -- Typically fit DSP multiply 18x18 element so use <= 17, to fit unsigned in 18 bit signed,
+ constant c_diag_wg_ampl_w : natural := 17;
-- = waveform data width-1 (sign bit) to be able to make a 1 LSBit amplitude sinus
constant c_diag_wg_mode_off : natural := 0;
@@ -68,25 +88,35 @@ package diag_pkg is
type t_diag_wg is record
mode : std_logic_vector(c_diag_wg_mode_w - 1 downto 0);
- nof_samples : std_logic_vector(c_diag_wg_nofsamples_w - 1 downto 0); -- unsigned value
- phase : std_logic_vector(c_diag_wg_phase_w - 1 downto 0); -- unsigned value
- freq : std_logic_vector(c_diag_wg_freq_w - 1 downto 0); -- unsigned value
- ampl : std_logic_vector(c_diag_wg_ampl_w - 1 downto 0); -- unsigned value, range [0:2**c_diag_wg_ampl_w> normalized to range [0 c_diag_wg_gain>
+ -- unsigned value
+ nof_samples : std_logic_vector(c_diag_wg_nofsamples_w - 1 downto 0);
+ -- unsigned value
+ phase : std_logic_vector(c_diag_wg_phase_w - 1 downto 0);
+ -- unsigned value
+ freq : std_logic_vector(c_diag_wg_freq_w - 1 downto 0);
+ -- unsigned value, range [0:2**c_diag_wg_ampl_w> normalized to range [0 c_diag_wg_gain>
+ ampl : std_logic_vector(c_diag_wg_ampl_w - 1 downto 0);
end record;
- constant c_diag_wg_ampl_norm : real := 1.0; -- Use this default amplitude norm = 1.0 when WG data width = WG waveform buffer data width,
+ -- Use this default amplitude norm = 1.0 when WG data width = WG waveform buffer data width,
+ constant c_diag_wg_ampl_norm : real := 1.0;
-- else use extra amplitude unit scaling by (WG data max)/(WG data max + 1)
- constant c_diag_wg_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
+ -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
+ constant c_diag_wg_gain_w : natural := 1;
-- . use gain 2**0 = 1 to have fulle scale without clipping
-- . use gain 2**g_calc_gain_w > 1 to cause clipping
-- For c_diag_wg_gain_w = 1 there is clipping from [1 2> For normalized values >= 2**c_diag_wg_gain_w = 2
-- the behaviour becomes more or less undefined. Due to wrapping it appears that normalized values [2 3>
-- result in a sinus again. Therefore use normalized range [0 2**c_diag_wg_gain_w>.
- constant c_diag_wg_ampl_unit : real := 2**REAL(c_diag_wg_ampl_w - c_diag_wg_gain_w) * c_diag_wg_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
- constant c_diag_wg_freq_unit : real := 2**REAL(c_diag_wg_freq_w); -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
- constant c_diag_wg_phase_unit : real := 2**REAL(c_diag_wg_phase_w) / 360.0; -- ^= 1 degree
-
- constant c_diag_wg_latency : natural := 10; -- WG starts 10 cycles after trigger
+ -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
+ constant c_diag_wg_ampl_unit : real := 2**REAL(c_diag_wg_ampl_w - c_diag_wg_gain_w) * c_diag_wg_ampl_norm;
+ -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
+ constant c_diag_wg_freq_unit : real := 2**REAL(c_diag_wg_freq_w);
+ -- ^= 1 degree
+ constant c_diag_wg_phase_unit : real := 2**REAL(c_diag_wg_phase_w) / 360.0;
+
+ -- WG starts 10 cycles after trigger
+ constant c_diag_wg_latency : natural := 10;
constant c_diag_wg_rst : t_diag_wg := (TO_UVEC(c_diag_wg_mode_off, c_diag_wg_mode_w),
TO_UVEC( 1024, c_diag_wg_nofsamples_w),
TO_UVEC( 0, c_diag_wg_phase_w),
@@ -110,7 +140,8 @@ package diag_pkg is
constant c_diag_bg_samples_per_packet_w : natural := 24;
constant c_diag_bg_blocks_per_sync_w : natural := 24;
constant c_diag_bg_gapsize_w : natural := 31;
- constant c_diag_bg_gapsize_max : natural := c_natural_high; -- = 2147483647 = 2**31 - 1 = NATURAL'HIGH
+ -- = 2147483647 = 2**31 - 1 = NATURAL'HIGH
+ constant c_diag_bg_gapsize_max : natural := c_natural_high;
constant c_diag_bg_mem_adrs_w : natural := 24;
constant c_diag_bg_mem_low_adrs_w : natural := c_diag_bg_mem_adrs_w;
constant c_diag_bg_mem_high_adrs_w : natural := c_diag_bg_mem_adrs_w;
@@ -118,8 +149,10 @@ package diag_pkg is
constant c_diag_bg_bsn_init_w : natural := 64;
type t_diag_block_gen is record
- enable : std_logic; -- block enable
- enable_sync : std_logic; -- block enable on sync pulse
+ -- block enable
+ enable : std_logic;
+ -- block enable on sync pulse
+ enable_sync : std_logic;
samples_per_packet : std_logic_vector(c_diag_bg_samples_per_packet_w - 1 downto 0);
blocks_per_sync : std_logic_vector(c_diag_bg_blocks_per_sync_w - 1 downto 0);
gapsize : std_logic_vector(c_diag_bg_gapsize_w - 1 downto 0);
@@ -154,7 +187,8 @@ package diag_pkg is
TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
TO_UVEC( 7, c_diag_bg_gapsize_w),
TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( 15, c_diag_bg_mem_high_adrs_w), -- fits any BG buffer that has address width >= 4
+ -- fits any BG buffer that has address width >= 4
+ TO_UVEC( 15, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
type t_diag_block_gen_arr is array (integer range <>) of t_diag_block_gen;
@@ -176,7 +210,8 @@ package diag_pkg is
type t_diag_data_type_enum is (
e_data,
- e_complex, -- im & re
+ -- im & re
+ e_complex,
e_real,
e_imag
);
@@ -184,7 +219,8 @@ package diag_pkg is
-----------------------------------------------------------------------------
-- Data buffer dev
-----------------------------------------------------------------------------
- constant c_diag_db_dev_reg_nof_dat : natural := 8; -- Create headroom of 4 registers.
+ -- Create headroom of 4 registers.
+ constant c_diag_db_dev_reg_nof_dat : natural := 8;
constant c_diag_db_dev_reg_adr_w : natural := ceil_log2(c_diag_db_dev_reg_nof_dat);
-----------------------------------------------------------------------------
diff --git a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
index 4bf373e254343579497acde7c1872eda9cc6fd26..01f247e4f6d41d07e5f0f979f2d43bb8c2f9bc00 100644
--- a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
@@ -98,10 +98,12 @@ use work.diag_pkg.all;
entity diag_rx_seq is
generic (
- g_input_reg : boolean := false; -- Use unregistered input to save logic, use registered input to ease achieving timing constrains.
+ -- Use unregistered input to save logic, use registered input to ease achieving timing constrains.
+ g_input_reg : boolean := false;
g_use_steps : boolean := false;
g_nof_steps : natural := c_diag_seq_rx_reg_nof_steps;
- g_sel : std_logic := '1'; -- '0' = PRSG, '1' = COUNTER
+ -- '0' = PRSG, '1' = COUNTER
+ g_sel : std_logic := '1';
g_cnt_incr : integer := 1;
g_cnt_w : natural := c_word_w;
g_dat_w : natural := 12;
@@ -113,19 +115,26 @@ entity diag_rx_seq is
clken : in std_logic := '1';
-- Static control input (connect via MM or leave open to use default)
- diag_en : in std_logic; -- '0' = init and disable, '1' = enable
+ -- '0' = init and disable, '1' = enable
+ diag_en : in std_logic;
diag_sel : in std_logic := g_sel;
diag_steps_arr : t_integer_arr(g_nof_steps - 1 downto 0) := (others => 1);
- diag_res : out std_logic_vector(g_diag_res_w - 1 downto 0); -- diag_res valid indication bits & aggregate diff of in_dat during diag_en
+ -- diag_res valid indication bits & aggregate diff of in_dat during diag_en
+ diag_res : out std_logic_vector(g_diag_res_w - 1 downto 0);
diag_res_val : out std_logic;
- diag_sample : out std_logic_vector(g_dat_w - 1 downto 0); -- monitor last valid in_dat
- diag_sample_diff : out std_logic_vector(g_dat_w - 1 downto 0); -- monitor difference between last valid in_dat and previous valid in_dat
+ -- monitor last valid in_dat
+ diag_sample : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- monitor difference between last valid in_dat and previous valid in_dat
+ diag_sample_diff : out std_logic_vector(g_dat_w - 1 downto 0);
diag_sample_val : out std_logic;
-- ST input
- in_cnt : out std_logic_vector(g_cnt_w - 1 downto 0); -- count valid input test sequence data
- in_dat : in std_logic_vector(g_dat_w - 1 downto 0); -- input test sequence data
- in_val : in std_logic -- gaps are allowed, however diag_res requires at least 2 valid in_dat to report a valid result
+ -- count valid input test sequence data
+ in_cnt : out std_logic_vector(g_cnt_w - 1 downto 0);
+ -- input test sequence data
+ in_dat : in std_logic_vector(g_dat_w - 1 downto 0);
+ -- gaps are allowed, however diag_res requires at least 2 valid in_dat to report a valid result
+ in_val : in std_logic
);
end diag_rx_seq;
@@ -140,10 +149,14 @@ architecture rtl of diag_rx_seq is
signal in_val_reg : std_logic;
signal in_dat_reg : std_logic_vector(in_dat'range);
- signal in_dat_dly1 : std_logic_vector(in_dat'range); -- latency common_lfsr_nxt_seq
- signal in_dat_dly2 : std_logic_vector(in_dat'range); -- latency ref_dat
- signal in_val_dly1 : std_logic; -- latency common_lfsr_nxt_seq
- signal in_val_dly2 : std_logic; -- latency ref_dat
+ -- latency common_lfsr_nxt_seq
+ signal in_dat_dly1 : std_logic_vector(in_dat'range);
+ -- latency ref_dat
+ signal in_dat_dly2 : std_logic_vector(in_dat'range);
+ -- latency common_lfsr_nxt_seq
+ signal in_val_dly1 : std_logic;
+ -- latency ref_dat
+ signal in_val_dly2 : std_logic;
signal prsg : std_logic_vector(in_dat'range);
signal nxt_prsg : std_logic_vector(in_dat'range);
@@ -210,7 +223,8 @@ begin
end generate;
-- Use initialisation to set initial diag_res to invalid
- diag_res <= diag_res_int; -- use initialisation of internal signal diag_res_int rather than initialisation of entity output diag_res
+ -- use initialisation of internal signal diag_res_int rather than initialisation of entity output diag_res
+ diag_res <= diag_res_int;
-- -- Use rst to set initial diag_res to invalid
-- p_rst_clk : PROCESS (rst, clk)
@@ -274,10 +288,12 @@ begin
rst => rst,
switch_high => in_val_reg,
switch_low => diag_dis,
- out_level => in_val_1 -- first in_val has been detected, but this one was used as seed for common_lfsr_nxt_seq
+ -- first in_val has been detected, but this one was used as seed for common_lfsr_nxt_seq
+ out_level => in_val_1
);
- in_val_act <= in_val_1 and in_val_reg; -- Signal the second valid in_dat after diag_en='1'
+ -- Signal the second valid in_dat after diag_en='1'
+ in_val_act <= in_val_1 and in_val_reg;
u_in_val_2 : entity common_lib.common_switch
port map(
@@ -285,7 +301,8 @@ begin
rst => rst,
switch_high => in_val_act,
switch_low => diag_dis,
- out_level => in_val_2 -- second in_val has been detected, representing a true next sequence value
+ -- second in_val has been detected, representing a true next sequence value
+ out_level => in_val_2
);
-- Use in_val_2_act instead of in_val_2 to have stable start in case diag_dis takes just a pulse and in_val is continue high
@@ -299,15 +316,24 @@ begin
no_steps : if g_use_steps = false generate
-- Determine next reference dat based on current input dat
- common_lfsr_nxt_seq(c_lfsr_nr, -- IN
- g_cnt_incr, -- IN
- ref_en, -- IN
- in_val_reg, -- IN, use in_val_reg to allow gaps in the input data valid stream
- in_dat_reg, -- IN, used only to init nxt_prsg and nxt_cntr when ref_en='0'
- prsg, -- IN
- cntr, -- IN
- nxt_prsg, -- OUT
- nxt_cntr); -- OUT
+ -- IN
+ common_lfsr_nxt_seq(c_lfsr_nr,
+ -- IN
+ g_cnt_incr,
+ -- IN
+ ref_en,
+ -- IN, use in_val_reg to allow gaps in the input data valid stream
+ in_val_reg,
+ -- IN, used only to init nxt_prsg and nxt_cntr when ref_en='0'
+ in_dat_reg,
+ -- IN
+ prsg,
+ -- IN
+ cntr,
+ -- OUT
+ nxt_prsg,
+ -- OUT
+ nxt_cntr);
nxt_ref_dat <= prsg when diag_sel = '0' else cntr;
@@ -393,7 +419,8 @@ begin
out_level => diff_hold
);
- diff_res <= (others => diff_hold); -- convert diff_hold to diff_res slv format as used for g_use_steps=FALSE
+ -- convert diff_hold to diff_res slv format as used for g_use_steps=FALSE
+ diff_res <= (others => diff_hold);
end generate;
------------------------------------------------------------------------------
@@ -408,8 +435,10 @@ begin
nxt_diag_res <= c_diag_res_invalid;
if diag_res_en = '1' then
-- The test runs AND there have been valid input samples to verify
- nxt_diag_res <= (others => '0'); -- MSBits of valid diag_res are 0
- nxt_diag_res(diff_res'range) <= diff_res; -- diff_res of dat[]
+ -- MSBits of valid diag_res are 0
+ nxt_diag_res <= (others => '0');
+ -- diff_res of dat[]
+ nxt_diag_res(diff_res'range) <= diff_res;
end if;
end process;
@@ -418,14 +447,16 @@ begin
------------------------------------------------------------------------------
u_common_counter : entity common_lib.common_counter
generic map (
- g_latency => 1, -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ g_latency => 1,
g_width => g_cnt_w
)
port map (
rst => rst,
clk => clk,
clken => clken,
- cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
+ -- synchronous cnt_clr is only interpreted when clken is active
+ cnt_clr => diag_dis,
cnt_en => in_val,
count => in_cnt
);
diff --git a/libraries/base/diag/src/vhdl/diag_tx_frm.vhd b/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
index 0f392a8179f1357c5ecf7e6848dbb7b576332d25..ba21c3ce8cc5263c2758e91c28307cd4953bc90a 100644
--- a/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
+++ b/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
@@ -45,10 +45,14 @@ use common_lib.common_lfsr_sequences_pkg.all;
entity diag_tx_frm is
generic (
- g_sel : std_logic := '1'; -- '0' = PRSG, '1' = COUNTER
- g_init : natural := 0; -- default test sequence init value
- g_frame_len : natural := 2; -- >= 2, test frame length
- g_dat_w : natural := 16 -- >= 1, test data width
+ -- '0' = PRSG, '1' = COUNTER
+ g_sel : std_logic := '1';
+ -- default test sequence init value
+ g_init : natural := 0;
+ -- >= 2, test frame length
+ g_frame_len : natural := 2;
+ -- >= 1, test data width
+ g_dat_w : natural := 16
);
port (
rst : in std_logic;
@@ -56,21 +60,31 @@ entity diag_tx_frm is
clken : in std_logic := '1';
-- Static control input (connect via MM or leave open to use default)
- diag_sel : in std_logic := g_sel; -- '0' = PRSG sequence data, '1' = COUNTER sequence data
- diag_dc : in std_logic := '0'; -- '0' = output diag_sel sequence data, '1' = output constant diag_init data
+ -- '0' = PRSG sequence data, '1' = COUNTER sequence data
+ diag_sel : in std_logic := g_sel;
+ -- '0' = output diag_sel sequence data, '1' = output constant diag_init data
+ diag_dc : in std_logic := '0';
diag_frame_len : in std_logic_vector(ceil_log2(g_frame_len) - 1 downto 0) := TO_UVEC(g_frame_len, ceil_log2(g_frame_len));
-- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
- diag_ready : out std_logic; -- '1' when the generator can accept a new diag_sop
- diag_init : in std_logic_vector(g_dat_w - 1 downto 0) := TO_UVEC(g_init, g_dat_w); -- init data for out_dat when diag_sop = '1'
- diag_sop : in std_logic := '1'; -- '1' start a frame generation
+ -- '1' when the generator can accept a new diag_sop
+ diag_ready : out std_logic;
+ -- init data for out_dat when diag_sop = '1'
+ diag_init : in std_logic_vector(g_dat_w - 1 downto 0) := TO_UVEC(g_init, g_dat_w);
+ -- '1' start a frame generation
+ diag_sop : in std_logic := '1';
-- ST output
- out_ready : in std_logic := '1'; -- '1' = request ST test data output, '0' = halt ST test data output
- out_dat : out std_logic_vector(g_dat_w - 1 downto 0); -- test sequence data
- out_val : out std_logic; -- '1' when out_data is valid
- out_sop : out std_logic; -- '1' for first valid frame data
- out_eop : out std_logic -- '1' for last valid frame data
+ -- '1' = request ST test data output, '0' = halt ST test data output
+ out_ready : in std_logic := '1';
+ -- test sequence data
+ out_dat : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- '1' when out_data is valid
+ out_val : out std_logic;
+ -- '1' for first valid frame data
+ out_sop : out std_logic;
+ -- '1' for last valid frame data
+ out_eop : out std_logic
);
end diag_tx_frm;
diff --git a/libraries/base/diag/src/vhdl/diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
index 6b00fcfb0d0b1643d8b08c7fc35da4f3376c0045..9b0fb59ec7948d673abdc4ff563ef4240bb36688 100644
--- a/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
@@ -42,28 +42,41 @@ use common_lib.common_lfsr_sequences_pkg.all;
entity diag_tx_seq is
generic (
- g_latency : natural := 1; -- default 1 for registered out_cnt/dat/val output, use 0 for immediate combinatorial out_cnt/dat/val output
- g_sel : std_logic := '1'; -- '0' = PRSG, '1' = COUNTER
- g_init : natural := 0; -- init value for out_dat when diag_en = '0'
+ -- default 1 for registered out_cnt/dat/val output, use 0 for immediate combinatorial out_cnt/dat/val output
+ g_latency : natural := 1;
+ -- '0' = PRSG, '1' = COUNTER
+ g_sel : std_logic := '1';
+ -- init value for out_dat when diag_en = '0'
+ g_init : natural := 0;
g_cnt_incr : integer := 1;
g_cnt_w : natural := c_word_w;
- g_dat_w : natural -- >= 1, test data width
+ -- >= 1, test data width
+ g_dat_w : natural
);
port (
rst : in std_logic;
clk : in std_logic;
clken : in std_logic := '1';
-- Static control input (connect via MM or leave open to use default)
- diag_en : in std_logic; -- '0' = init and disable output sequence, '1' = enable output sequence
- diag_sel : in std_logic := g_sel; -- '0' = PRSG sequence data, '1' = COUNTER sequence data
- diag_dc : in std_logic := '0'; -- '0' = output diag_sel sequence data, '1' = output constant diag_init data
- diag_init : in std_logic_vector(g_dat_w - 1 downto 0) := TO_UVEC(g_init, g_dat_w); -- init value for out_dat when diag_en = '0'
- diag_mod : in std_logic_vector(g_dat_w - 1 downto 0) := TO_UVEC(0, g_dat_w); -- default 0 to wrap modulo 2*g_dat_w
+ -- '0' = init and disable output sequence, '1' = enable output sequence
+ diag_en : in std_logic;
+ -- '0' = PRSG sequence data, '1' = COUNTER sequence data
+ diag_sel : in std_logic := g_sel;
+ -- '0' = output diag_sel sequence data, '1' = output constant diag_init data
+ diag_dc : in std_logic := '0';
+ -- init value for out_dat when diag_en = '0'
+ diag_init : in std_logic_vector(g_dat_w - 1 downto 0) := TO_UVEC(g_init, g_dat_w);
+ -- default 0 to wrap modulo 2*g_dat_w
+ diag_mod : in std_logic_vector(g_dat_w - 1 downto 0) := TO_UVEC(0, g_dat_w);
-- ST output
- diag_req : in std_logic := '1'; -- '1' = request output, '0' = halt output
- out_cnt : out std_logic_vector(g_cnt_w - 1 downto 0); -- count valid output test sequence data
- out_dat : out std_logic_vector(g_dat_w - 1 downto 0); -- output test sequence data
- out_val : out std_logic -- '1' when out_dat is valid
+ -- '1' = request output, '0' = halt output
+ diag_req : in std_logic := '1';
+ -- count valid output test sequence data
+ out_cnt : out std_logic_vector(g_cnt_w - 1 downto 0);
+ -- output test sequence data
+ out_dat : out std_logic_vector(g_dat_w - 1 downto 0);
+ -- '1' when out_dat is valid
+ out_val : out std_logic
);
end diag_tx_seq;
@@ -74,8 +87,10 @@ architecture rtl of diag_tx_seq is
signal prsg : std_logic_vector(out_dat'range);
signal nxt_prsg : std_logic_vector(out_dat'range);
- signal cntr : std_logic_vector(out_dat'range) := (others => '0'); -- init to avoid Warning: "NUMERIC_STD."<": metavalue detected" with UNSIGNED()
- signal next_cntr : std_logic_vector(out_dat'range) := (others => '0'); -- init to avoid Warning: "NUMERIC_STD."<": metavalue detected" with UNSIGNED()
+ -- init to avoid Warning: "NUMERIC_STD."<": metavalue detected" with UNSIGNED()
+ signal cntr : std_logic_vector(out_dat'range) := (others => '0');
+ -- init to avoid Warning: "NUMERIC_STD."<": metavalue detected" with UNSIGNED()
+ signal next_cntr : std_logic_vector(out_dat'range) := (others => '0');
signal nxt_cntr : std_logic_vector(out_dat'range);
signal nxt_out_dat : std_logic_vector(out_dat'range);
@@ -116,32 +131,44 @@ begin
out_val <= nxt_out_val;
end generate;
- common_lfsr_nxt_seq(c_lfsr_nr, -- IN
- g_cnt_incr, -- IN
- diag_en, -- IN
- diag_req, -- IN
- diag_init, -- IN
- prsg, -- IN
- cntr, -- IN
- nxt_prsg, -- OUT
- next_cntr); -- OUT
+ -- IN
+ common_lfsr_nxt_seq(c_lfsr_nr,
+ -- IN
+ g_cnt_incr,
+ -- IN
+ diag_en,
+ -- IN
+ diag_req,
+ -- IN
+ diag_init,
+ -- IN
+ prsg,
+ -- IN
+ cntr,
+ -- OUT
+ nxt_prsg,
+ -- OUT
+ next_cntr);
nxt_cntr <= next_cntr when unsigned(next_cntr) < unsigned(diag_mod) else SUB_UVEC(next_cntr, diag_mod);
nxt_out_dat <= diag_init when diag_dc = '1' else prsg when diag_sel = '0' else cntr;
- nxt_out_val <= diag_en and diag_req; -- 'en' for entire test on/off, 'req' for dynamic invalid gaps in the stream
+ -- 'en' for entire test on/off, 'req' for dynamic invalid gaps in the stream
+ nxt_out_val <= diag_en and diag_req;
-- Count number of valid output data
u_common_counter : entity common_lib.common_counter
generic map (
- g_latency => g_latency, -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ g_latency => g_latency,
g_width => g_cnt_w
)
port map (
rst => rst,
clk => clk,
clken => clken,
- cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
+ -- synchronous cnt_clr is only interpreted when clken is active
+ cnt_clr => diag_dis,
cnt_en => nxt_out_val,
count => out_cnt
);
diff --git a/libraries/base/diag/src/vhdl/diag_wg.vhd b/libraries/base/diag/src/vhdl/diag_wg.vhd
index 93592adee83c80033b3e9f51e3de6b6070170d7a..cb82f9857d9d528ef2f6ceca40867f0282a1a759 100644
--- a/libraries/base/diag/src/vhdl/diag_wg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg.vhd
@@ -55,17 +55,24 @@ use technology_lib.technology_select_pkg.all;
entity diag_wg is
generic (
g_technology : natural := c_tech_select_default;
- g_buf_dat_w : natural := 18; -- Use >= g_calc_dat_w and typically <= DSP multiply 18x18 element
- g_buf_addr_w : natural := 11; -- Waveform buffer size 2**g_buf_addr_w nof samples
+ -- Use >= g_calc_dat_w and typically <= DSP multiply 18x18 element
+ g_buf_dat_w : natural := 18;
+ -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_buf_addr_w : natural := 11;
-- . in calc mode fill the entire buffer with one sinus wave, ctrl.phase and ctrl.freq will map on the entire range
-- . in single or repeat mode fill the buffer with an arbitrary signal and define actual the period via ctrl.nof_samples
- g_rate_factor : natural := 1; -- Default 1 for unit frequency Fs, else g_rate_factor * Fs using g_rate_factor nof parallel outputs
- g_rate_offset : natural := 0; -- Selects which of the parallel outputs [0:g_rate_factor-1] this WG should generate
- g_calc_support : boolean := true; -- When FALSE then calc mode falls back to repeat mode to save logic.
- g_calc_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
+ -- Default 1 for unit frequency Fs, else g_rate_factor * Fs using g_rate_factor nof parallel outputs
+ g_rate_factor : natural := 1;
+ -- Selects which of the parallel outputs [0:g_rate_factor-1] this WG should generate
+ g_rate_offset : natural := 0;
+ -- When FALSE then calc mode falls back to repeat mode to save logic.
+ g_calc_support : boolean := true;
+ -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
+ g_calc_gain_w : natural := 1;
-- . use gain 2**0 = 1 to have full scale without clipping
-- . use gain 2**g_calc_gain_w > 1 to cause clipping
- g_calc_dat_w : natural := 12 -- Effective range of the WG out_dat
+ -- Effective range of the WG out_dat
+ g_calc_dat_w : natural := 12
);
port (
rst : in std_logic;
@@ -83,24 +90,31 @@ entity diag_wg is
out_ovr : out std_logic;
out_dat : out std_logic_vector(g_buf_dat_w - 1 downto 0);
out_val : out std_logic;
- out_sync : out std_logic -- Pulse to mark WG start
+ -- Pulse to mark WG start
+ out_sync : out std_logic
);
end diag_wg;
architecture rtl of diag_wg is
- constant c_mult_pipeline_input : natural := 1; -- 0 or 1
- constant c_mult_pipeline_product : natural := 1; -- 0 or 1
- constant c_mult_pipeline_output : natural := 0; -- >= 0
+ -- 0 or 1
+ constant c_mult_pipeline_input : natural := 1;
+ -- 0 or 1
+ constant c_mult_pipeline_product : natural := 1;
+ -- >= 0
+ constant c_mult_pipeline_output : natural := 0;
constant c_mult_pipeline : natural := c_mult_pipeline_input + c_mult_pipeline_product + c_mult_pipeline_output;
constant c_clip_pipeline : natural := 1;
constant c_round_pipeline : natural := 1;
- constant c_sync_dly : natural := 2; -- Set to 2 to create a sync that is alligned with the sop.
+ -- Set to 2 to create a sync that is alligned with the sop.
+ constant c_sync_dly : natural := 2;
constant c_calc_pipeline : natural := c_mult_pipeline + c_round_pipeline + c_clip_pipeline;
- constant c_ampl_w : natural := c_diag_wg_ampl_w + 1; -- extra MSBit equal to '0' to have amplitude as signed value
- constant c_mult_w : natural := g_buf_dat_w + c_ampl_w; -- signed multiply
+ -- extra MSBit equal to '0' to have amplitude as signed value
+ constant c_ampl_w : natural := c_diag_wg_ampl_w + 1;
+ -- signed multiply
+ constant c_mult_w : natural := g_buf_dat_w + c_ampl_w;
-- Shift_left 1 to skip 'double sign bit' is safe, because +-rddat * +ampl will have MSbits "00" or "11", so the sign bit is preserved.
constant c_prod_w : natural := c_mult_w - 1;
@@ -126,7 +140,8 @@ architecture rtl of diag_wg is
signal i_mon_ctrl : t_diag_wg;
signal nxt_mon_ctrl : t_diag_wg;
- signal nof_samples : std_logic_vector(g_buf_addr_w downto 0); -- only use effective range of nof_samples+1
+ -- only use effective range of nof_samples+1
+ signal nof_samples : std_logic_vector(g_buf_addr_w downto 0);
signal nxt_nof_samples : std_logic_vector(g_buf_addr_w downto 0);
signal sample_cnt : natural range 0 to 2**g_buf_addr_w - 1;
signal nxt_sample_cnt : natural;
@@ -216,10 +231,12 @@ begin
nxt_state <= state;
nxt_init_sync <= '0';
if unsigned(ctrl.mode) = c_diag_wg_mode_off then
- nxt_state <= s_off; -- WG off takes effect immediately
+ -- WG off takes effect immediately
+ nxt_state <= s_off;
end if;
if restart = '1' then
- nxt_state <= s_init; -- Restart the WG
+ -- Restart the WG
+ nxt_state <= s_init;
else
case state is
when s_init =>
@@ -234,7 +251,8 @@ begin
if sample_cnt + sample_step >= unsigned(nof_samples) then
nxt_state <= s_off;
end if;
- when others => null; -- continue in state
+ -- continue in state
+ when others => null;
end case;
end if;
end process;
@@ -291,8 +309,10 @@ begin
init_calc_done <= '0';
if restart = '1' then
nxt_phase <= (others => '0');
- nxt_phase(phase'high downto phase'high - ctrl.phase'length + 1) <= ctrl.phase; -- initalize phase
- nxt_phase_step <= (others => '0'); -- initalize phase increment
+ -- initalize phase
+ nxt_phase(phase'high downto phase'high - ctrl.phase'length + 1) <= ctrl.phase;
+ -- initalize phase increment
+ nxt_phase_step <= (others => '0');
nxt_init_phase_cnt <= 0;
else
-- Determine the initial phase for each g_rate_offset and the frequency phase step. This can be done sequentially
@@ -300,9 +320,11 @@ begin
if init_phase_cnt < g_rate_factor then
nxt_init_phase_cnt <= init_phase_cnt + 1;
if init_phase_cnt < g_rate_offset then
- nxt_phase <= std_logic_vector(unsigned(phase) + unsigned(ctrl.freq)); -- sequentially calculate: g_rate_offset * ctrl.freq
+ -- sequentially calculate: g_rate_offset * ctrl.freq
+ nxt_phase <= std_logic_vector(unsigned(phase) + unsigned(ctrl.freq));
end if;
- nxt_phase_step <= std_logic_vector(unsigned(phase_step) + unsigned(ctrl.freq)); -- sequentially calculate: g_rate_factor * ctrl.freq
+ -- sequentially calculate: g_rate_factor * ctrl.freq
+ nxt_phase_step <= std_logic_vector(unsigned(phase_step) + unsigned(ctrl.freq));
elsif state = s_init then
init_calc_done <= '1';
end if;
@@ -316,14 +338,16 @@ begin
p_address_generator : process(restart, state, sample_cnt, phase)
begin
- nxt_buf_addr <= (others => '0'); -- reset address when s_off
+ -- reset address when s_off
+ nxt_buf_addr <= (others => '0');
nxt_buf_rden <= '0';
if state = s_single or state = s_repeat then
nxt_buf_addr <= std_logic_vector(to_unsigned(sample_cnt, buf_addr'length));
nxt_buf_rden <= '1';
elsif state = s_calc then
- nxt_buf_addr <= std_logic_vector(u_round(phase, phase'length - buf_addr'length)); -- For unsigned round the combinatorial function u_round is used.
+ -- For unsigned round the combinatorial function u_round is used.
+ nxt_buf_addr <= std_logic_vector(u_round(phase, phase'length - buf_addr'length));
nxt_buf_rden <= '1';
end if;
end process;
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
index bb2657dbd84c20cf1fc44d553717566f55a69238..bf5d1e698e417acfca30232a327891c846dd2f16 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
@@ -39,7 +39,8 @@ entity diag_wg_wideband is
g_buf_dir : string := "data/";
-- Wideband parameters
- g_wideband_factor : natural := 4; -- Wideband rate factor >= 1 for unit frequency of g_wideband_factor * Fs
+ -- Wideband rate factor >= 1 for unit frequency of g_wideband_factor * Fs
+ g_wideband_factor : natural := 4;
-- Basic WG parameters, see diag_wg.vhd for their meaning
g_buf_dat_w : natural := 18;
@@ -68,7 +69,8 @@ entity diag_wg_wideband is
st_ctrl : in t_diag_wg;
st_mon_ctrl : out t_diag_wg;
- out_ovr : out std_logic_vector(g_wideband_factor - 1 downto 0); -- big endian, so first output sample in MSBit, MSData
+ -- big endian, so first output sample in MSBit, MSData
+ out_ovr : out std_logic_vector(g_wideband_factor - 1 downto 0);
out_dat : out std_logic_vector(g_wideband_factor * g_buf_dat_w - 1 downto 0);
out_val : out std_logic_vector(g_wideband_factor - 1 downto 0);
out_sync : out std_logic_vector(g_wideband_factor - 1 downto 0)
@@ -78,8 +80,10 @@ end diag_wg_wideband;
architecture str of diag_wg_wideband is
constant c_buf : t_c_mem := (latency => 1,
adr_w => g_buf_addr_w,
- dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
- nof_dat => 2**g_buf_addr_w, -- = 2**adr_w
+ -- fit DSP multiply 18x18 element
+ dat_w => g_buf_dat_w,
+ -- = 2**adr_w
+ nof_dat => 2**g_buf_addr_w,
init_sl => '0');
constant c_buf_file : string := sel_a_b(c_buf.adr_w = 11 and c_buf.dat_w = 18, g_buf_dir & "diag_sin_2048x18.hex",
sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, g_buf_dir & "diag_sin_1024x18.hex",
@@ -106,7 +110,8 @@ begin
mm_rdval <= buf_rdval(0);
mm_rddata <= buf_rddata(0);
- st_mon_ctrl <= st_mon_ctrl_arr(0); -- same for all g_wideband_factor waveform generators
+ -- same for all g_wideband_factor waveform generators
+ st_mon_ctrl <= st_mon_ctrl_arr(0);
gen_wg : for I in 0 to g_wideband_factor - 1 generate
-- Waveform buffer
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
index b0d7b45dc644122ff823691236470fd37bf97c8e..1c38b4d852fc629cf71c6637a282692ac00a935d 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
@@ -48,22 +48,31 @@ use diag_lib.diag_pkg.all;
entity diag_wg_wideband_reg is
generic (
- g_cross_clock_domain : boolean := true -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
- st_wg_ctrl : out t_diag_wg; -- WG control write port
- st_mon_ctrl : in t_diag_wg -- WG control read port, for currently active control
+ -- WG control write port
+ st_wg_ctrl : out t_diag_wg;
+ -- WG control read port, for currently active control
+ st_mon_ctrl : in t_diag_wg
);
end diag_wg_wideband_reg;
@@ -71,7 +80,8 @@ architecture rtl of diag_wg_wideband_reg is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 2**2,
init_sl => '0');
@@ -111,32 +121,46 @@ begin
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
when 0 =>
mm_wg_ctrl_mode_wr <= '1';
- mm_wg_ctrl.mode <= sla_in.wrdata( 7 downto 0); -- = 8 = c_diag_wg_mode_w
- mm_wg_ctrl.nof_samples <= sla_in.wrdata(31 downto 16); -- = 16 = c_diag_wg_nof_samples_w
+ -- = 8 = c_diag_wg_mode_w
+ mm_wg_ctrl.mode <= sla_in.wrdata( 7 downto 0);
+ -- = 16 = c_diag_wg_nof_samples_w
+ mm_wg_ctrl.nof_samples <= sla_in.wrdata(31 downto 16);
when 1 =>
- mm_wg_ctrl.phase <= sla_in.wrdata(15 downto 0); -- = 16 = c_diag_wg_phase_w
+ -- = 16 = c_diag_wg_phase_w
+ mm_wg_ctrl.phase <= sla_in.wrdata(15 downto 0);
when 2 =>
- mm_wg_ctrl.freq <= sla_in.wrdata(30 downto 0); -- = 31 = c_diag_wg_freq_w
+ -- = 31 = c_diag_wg_freq_w
+ mm_wg_ctrl.freq <= sla_in.wrdata(30 downto 0);
when 3 =>
- mm_wg_ctrl.ampl <= sla_in.wrdata(16 downto 0); -- = 17 = c_diag_wg_ampl_w
- when others => null; -- not used MM addresses
+ -- = 17 = c_diag_wg_ampl_w
+ mm_wg_ctrl.ampl <= sla_in.wrdata(16 downto 0);
+ -- not used MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
when 0 =>
- sla_out.rddata( 7 downto 0) <= mm_mon_ctrl.mode; -- = 8 = c_diag_wg_mode_w
- sla_out.rddata(31 downto 16) <= mm_mon_ctrl.nof_samples; -- = 16 = c_diag_wg_nof_samples_w
+ -- = 8 = c_diag_wg_mode_w
+ sla_out.rddata( 7 downto 0) <= mm_mon_ctrl.mode;
+ -- = 16 = c_diag_wg_nof_samples_w
+ sla_out.rddata(31 downto 16) <= mm_mon_ctrl.nof_samples;
when 1 =>
- sla_out.rddata(15 downto 0) <= mm_mon_ctrl.phase; -- = 16 = c_diag_wg_phase_w
+ -- = 16 = c_diag_wg_phase_w
+ sla_out.rddata(15 downto 0) <= mm_mon_ctrl.phase;
when 2 =>
- sla_out.rddata(30 downto 0) <= mm_mon_ctrl.freq; -- = 31 = c_diag_wg_freq_w
+ -- = 31 = c_diag_wg_freq_w
+ sla_out.rddata(30 downto 0) <= mm_mon_ctrl.freq;
when 3 =>
- sla_out.rddata(16 downto 0) <= mm_mon_ctrl.ampl; -- = 17 = c_diag_wg_ampl_w
- when others => null; -- not used MM addresses
+ -- = 17 = c_diag_wg_ampl_w
+ sla_out.rddata(16 downto 0) <= mm_mon_ctrl.ampl;
+ -- not used MM addresses
+ when others => null;
end case;
end if;
end if;
@@ -159,7 +183,8 @@ begin
-- signals if it is necessary (to avoid using more logic than necessary).
------------------------------------------------------------------------------
- no_cross : if g_cross_clock_domain = false generate -- so mm_clk = st_clk
+ -- so mm_clk = st_clk
+ no_cross : if g_cross_clock_domain = false generate
-- Write: MM to ST clock domain
p_st_clk : process(st_rst, st_clk)
begin
@@ -184,13 +209,16 @@ begin
port map (
in_rst => mm_rst,
in_clk => mm_clk,
- in_new => mm_wg_ctrl_mode_wr, -- when '1' then new in_dat is available after g_in_new_latency
+ -- when '1' then new in_dat is available after g_in_new_latency
+ in_new => mm_wg_ctrl_mode_wr,
in_dat => mm_wg_ctrl.mode,
- in_done => OPEN, -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done => OPEN,
out_rst => st_rst,
out_clk => st_clk,
out_dat => st_wg_ctrl.mode,
- out_new => open -- when '1' then the out_dat was updated with in_dat due to in_new
+ -- when '1' then the out_dat was updated with in_dat due to in_new
+ out_new => open
);
end generate;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
index 60095ffc8cd08aad6673de21d5b4b13f759ecbe8..23a2634f9b402c8c077429754d475bf16de7df52 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
@@ -113,37 +113,52 @@ entity mms_diag_block_gen is
-- BG settings
g_use_bg_buffer_ram : boolean := true;
g_buf_dat_w : positive := 32;
- g_buf_addr_w : positive := 7; -- Waveform buffer size 2**g_buf_addr_w nof samples
- g_file_index_arr : t_nat_natural_arr := array_init(0, 128, 1); -- default use the instance index as file index 0, 1, 2, 3, 4 ...
- g_file_name_prefix : string := "data/bf_in_data"; -- Path to the hex files that contain the initial data for the memories. The sequence number and ".hex" are added within the entity.
+ -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_buf_addr_w : positive := 7;
+ -- default use the instance index as file index 0, 1, 2, 3, 4 ...
+ g_file_index_arr : t_nat_natural_arr := array_init(0, 128, 1);
+ -- Path to the hex files that contain the initial data for the memories. The sequence number and ".hex" are added within the entity.
+ g_file_name_prefix : string := "data/bf_in_data";
g_diag_block_gen_rst : t_diag_block_gen := c_diag_block_gen_rst;
-- User input multiplexer option
g_usr_bypass_xonoff : boolean := false;
-- Tx_seq
- g_seq_dat_w : natural := 32; -- >= 1, test sequence data width. Choose g_seq_dat_w <= g_buf_dat_w
+ -- >= 1, test sequence data width. Choose g_seq_dat_w <= g_buf_dat_w
+ g_seq_dat_w : natural := 32;
-- LOFAR Lofar style block sync that is active from SOP to EOP
g_blk_sync : boolean := false
);
port (
-- System
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- dp_rst : in std_logic; -- reset synchronous with st_clk
- dp_clk : in std_logic; -- streaming clock domain clock
- en_sync : in std_logic := '1'; -- block generator enable sync pulse in ST dp_clk domain
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ dp_rst : in std_logic;
+ -- streaming clock domain clock
+ dp_clk : in std_logic;
+ -- block generator enable sync pulse in ST dp_clk domain
+ en_sync : in std_logic := '1';
-- MM interface
- reg_bg_ctrl_mosi : in t_mem_mosi := c_mem_mosi_rst; -- BG control register (one for all streams)
+ -- BG control register (one for all streams)
+ reg_bg_ctrl_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_bg_ctrl_miso : out t_mem_miso;
- ram_bg_data_mosi : in t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream)
+ -- BG buffer RAM (one per stream)
+ ram_bg_data_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_bg_data_miso : out t_mem_miso;
- reg_tx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst; -- Tx seq control (one per stream because c_reg_tx_seq_broadcast=FALSE)
+ -- Tx seq control (one per stream because c_reg_tx_seq_broadcast=FALSE)
+ reg_tx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_tx_seq_miso : out t_mem_miso;
-- ST interface
bg_ctrl_hold_arr : out t_diag_block_gen_arr(g_nof_streams - 1 downto 0);
- usr_siso_arr : out t_dp_siso_arr(g_nof_streams - 1 downto 0); -- connect when g_use_usr_input=TRUE, else leave not connected
+ -- connect when g_use_usr_input=TRUE, else leave not connected
+ usr_siso_arr : out t_dp_siso_arr(g_nof_streams - 1 downto 0);
usr_sosi_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
- out_siso_arr : in t_dp_siso_arr(g_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy); -- Default xon='1'
- out_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0) -- Output SOSI that contains the waveform data
+ -- Default xon='1'
+ out_siso_arr : in t_dp_siso_arr(g_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
+ -- Output SOSI that contains the waveform data
+ out_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0)
);
end mms_diag_block_gen;
@@ -158,9 +173,11 @@ architecture rtl of mms_diag_block_gen is
constant c_use_mux : boolean := g_use_usr_input and g_use_bg;
constant c_use_tx_seq_input : boolean := g_use_usr_input or g_use_bg;
- constant c_mux_nof_input : natural := 2; -- fixed
+ -- fixed
+ constant c_mux_nof_input : natural := 2;
- constant c_reg_tx_seq_broadcast : boolean := false; -- fixed use dedicated MM register per stream
+ -- fixed use dedicated MM register per stream
+ constant c_reg_tx_seq_broadcast : boolean := false;
type t_buf_dat_arr is array (natural range <>) of std_logic_vector(g_buf_dat_w - 1 downto 0);
type t_buf_adr_arr is array (natural range <>) of std_logic_vector(g_buf_addr_w - 1 downto 0);
@@ -174,13 +191,17 @@ architecture rtl of mms_diag_block_gen is
signal bg_ctrl : t_diag_block_gen;
signal mux_ctrl : natural range 0 to c_mux_nof_input - 1;
- signal mux_snk_out_2arr_2 : t_dp_siso_2arr_2(g_nof_streams - 1 downto 0); -- [g_nof_streams-1:0][c_mux_nof_input-1:0] = [1:0]
- signal mux_snk_in_2arr_2 : t_dp_sosi_2arr_2(g_nof_streams - 1 downto 0); -- [g_nof_streams-1:0][c_mux_nof_input-1:0] = [1:0]
+ -- [g_nof_streams-1:0][c_mux_nof_input-1:0] = [1:0]
+ signal mux_snk_out_2arr_2 : t_dp_siso_2arr_2(g_nof_streams - 1 downto 0);
+ -- [g_nof_streams-1:0][c_mux_nof_input-1:0] = [1:0]
+ signal mux_snk_in_2arr_2 : t_dp_sosi_2arr_2(g_nof_streams - 1 downto 0);
- signal usr_xflow_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0); -- optionally use dp_xonoff to add siso.xon flow control to use input when g_usr_bypass_xonoff=FALSE
+ -- optionally use dp_xonoff to add siso.xon flow control to use input when g_usr_bypass_xonoff=FALSE
+ signal usr_xflow_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
signal usr_xflow_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal bg_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0); -- BG has siso.xon flow control but no siso.ready flow control
+ -- BG has siso.xon flow control but no siso.ready flow control
+ signal bg_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
signal bg_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal mux_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
@@ -202,11 +223,13 @@ begin
u_bg_ctrl : entity work.diag_block_gen_reg
generic map(
- g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain => true,
g_diag_block_gen_rst => g_diag_block_gen_rst
)
port map (
- mm_rst => mm_rst, -- Clocks and reset
+ -- Clocks and reset
+ mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
@@ -280,8 +303,10 @@ begin
buf_rden => st_rd_arr(I),
buf_rddat => st_rddata_arr(I),
buf_rdval => st_rdval_arr(I),
- ctrl => bg_ctrl, -- same BG control for all streams
- ctrl_hold => bg_ctrl_hold_arr(I), -- active BG control can differ in time per stream
+ -- same BG control for all streams
+ ctrl => bg_ctrl,
+ -- active BG control can differ in time per stream
+ ctrl_hold => bg_ctrl_hold_arr(I),
en_sync => en_sync,
out_siso => bg_src_in_arr(I),
out_sosi => bg_src_out_arr(I)
@@ -292,7 +317,8 @@ begin
---------------------------------------------------------------------------
-- No multiplexer, so only one input or no input at all
---------------------------------------------------------------------------
- no_dp_mux : if c_use_mux = false generate -- so g_use_usr_input and g_use_bg are not both TRUE
+ -- so g_use_usr_input and g_use_bg are not both TRUE
+ no_dp_mux : if c_use_mux = false generate
-- default pass on flow control
usr_siso_arr <= mux_src_in_arr;
bg_src_in_arr <= mux_src_in_arr;
@@ -306,13 +332,15 @@ begin
-----------------------------------------------------------------------------
-- Multiplex user input and BG
-----------------------------------------------------------------------------
- gen_dp_mux : if c_use_mux = true generate -- so g_use_usr_input and g_use_bg are both TRUE
+ -- so g_use_usr_input and g_use_bg are both TRUE
+ gen_dp_mux : if c_use_mux = true generate
gen_streams : for I in 0 to g_nof_streams - 1 generate
-- Add user xon flow control if the user input does not already support it
u_dp_xonoff : entity dp_lib.dp_xonoff
generic map (
- g_bypass => g_usr_bypass_xonoff -- if the user input already has xon flow control then bypass using g_usr_bypass_xonoff=TRUE
+ -- if the user input already has xon flow control then bypass using g_usr_bypass_xonoff=TRUE
+ g_bypass => g_usr_bypass_xonoff
)
port map (
rst => dp_rst,
@@ -321,7 +349,8 @@ begin
in_siso => usr_siso_arr(I),
in_sosi => usr_sosi_arr(I),
-- Frame out
- out_siso => usr_xflow_src_in_arr(I), -- flush control via out_siso.xon
+ -- flush control via out_siso.xon
+ out_siso => usr_xflow_src_in_arr(I),
out_sosi => usr_xflow_src_out_arr(I)
);
@@ -338,23 +367,31 @@ begin
generic map (
g_technology => g_technology,
-- MUX
- g_mode => 4, -- g_mode=4 for framed input select via sel_ctrl
- g_nof_input => c_mux_nof_input, -- >= 1
+ -- g_mode=4 for framed input select via sel_ctrl
+ g_mode => 4,
+ -- >= 1
+ g_nof_input => c_mux_nof_input,
g_append_channel_lo => false,
- g_sel_ctrl_invert => true, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ g_sel_ctrl_invert => true,
-- Input FIFO
g_use_fifo => false,
- g_fifo_size => array_init(1024, c_mux_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, c_mux_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_size => array_init(1024, c_mux_nof_input),
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, c_mux_nof_input)
)
port map (
rst => dp_rst,
clk => dp_clk,
-- Control
- sel_ctrl => mux_ctrl, -- 0 = usr, 1 = BG
+ -- 0 = usr, 1 = BG
+ sel_ctrl => mux_ctrl,
-- ST sinks
- snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
- snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
+ -- [c_mux_nof_input-1:0]
+ snk_out_arr => mux_snk_out_2arr_2(I),
+ -- [c_mux_nof_input-1:0]
+ snk_in_arr => mux_snk_in_2arr_2(I),
-- ST source
src_in => mux_src_in_arr(I),
src_out => mux_src_out_arr(I)
@@ -389,7 +426,8 @@ begin
reg_miso => reg_tx_seq_miso,
-- DP streaming interface
- usr_snk_out_arr => mux_src_in_arr, -- connect when g_use_usr_input=TRUE, else leave not connected
+ -- connect when g_use_usr_input=TRUE, else leave not connected
+ usr_snk_out_arr => mux_src_in_arr,
usr_snk_in_arr => mux_src_out_arr,
tx_src_out_arr => out_sosi_arr,
tx_src_in_arr => out_siso_arr
diff --git a/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd b/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
index 481104862a93ecb6f5472cdc59622b9bff0f40c0..4d8999a982a1c9b51570ad09479dd9f2c45681cf 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
@@ -73,16 +73,22 @@ entity mms_diag_data_buffer is
g_use_db : boolean := true;
g_use_rx_seq : boolean := false;
-- General
- g_nof_streams : positive := 16; -- each stream gets an data buffer
+ -- each stream gets an data buffer
+ g_nof_streams : positive := 16;
-- DB settings
- g_data_type : t_diag_data_type_enum := e_data; -- define the sosi field that gets stored: e_data=data, e_complex=im&re, e_real=re, e_imag=im
- g_data_w : natural := 32; -- the g_data_w is the width of the data, re, im values or of the combined im&re value
- g_buf_nof_data : natural := 1024; -- nof words per data buffer
- g_buf_use_sync : boolean := false; -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ -- define the sosi field that gets stored: e_data=data, e_complex=im&re, e_real=re, e_imag=im
+ g_data_type : t_diag_data_type_enum := e_data;
+ -- the g_data_w is the width of the data, re, im values or of the combined im&re value
+ g_data_w : natural := 32;
+ -- nof words per data buffer
+ g_buf_nof_data : natural := 1024;
+ -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ g_buf_use_sync : boolean := false;
-- Rx_seq
g_use_steps : boolean := false;
g_nof_steps : natural := c_diag_seq_rx_reg_nof_steps;
- g_seq_dat_w : natural := 32 -- >= 1, test sequence data width. Choose g_seq_dat_w <= g_data_w
+ -- >= 1, test sequence data width. Choose g_seq_dat_w <= g_data_w
+ g_seq_dat_w : natural := 32
);
port (
-- System
@@ -91,17 +97,21 @@ entity mms_diag_data_buffer is
dp_rst : in std_logic;
dp_clk : in std_logic;
-- MM interface
- reg_data_buf_mosi : in t_mem_mosi := c_mem_mosi_rst; -- DB control register (one per stream)
+ -- DB control register (one per stream)
+ reg_data_buf_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_data_buf_miso : out t_mem_miso;
- ram_data_buf_mosi : in t_mem_mosi := c_mem_mosi_rst; -- DB buffer RAM (one per streams)
+ -- DB buffer RAM (one per streams)
+ ram_data_buf_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_data_buf_miso : out t_mem_miso;
- reg_rx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst; -- Rx seq control register (one per streams)
+ -- Rx seq control register (one per streams)
+ reg_rx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_rx_seq_miso : out t_mem_miso;
-- ST interface
- in_sync : in std_logic := '0'; -- input sync pulse in ST dp_clk domain that starts data buffer when g_use_in_sync = TRUE
+ -- input sync pulse in ST dp_clk domain that starts data buffer when g_use_in_sync = TRUE
+ in_sync : in std_logic := '0';
in_sosi_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0)
);
end mms_diag_data_buffer;
@@ -158,14 +168,16 @@ begin
in_data_arr(I) <= in_sosi_arr(I).im(g_data_w / 2 - 1 downto 0) & in_sosi_arr(I).re(g_data_w / 2 - 1 downto 0) when g_data_type = e_complex else
in_sosi_arr(I).re(g_data_w - 1 downto 0) when g_data_type = e_real else
in_sosi_arr(I).im(g_data_w - 1 downto 0) when g_data_type = e_imag else
- in_sosi_arr(I).data(g_data_w - 1 downto 0); -- g_data_type=e_data is default
+ -- g_data_type=e_data is default
+ in_sosi_arr(I).data(g_data_w - 1 downto 0);
u_diag_data_buffer : entity work.diag_data_buffer
generic map (
g_technology => g_technology,
g_data_w => g_data_w,
g_nof_data => g_buf_nof_data,
- g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ g_use_in_sync => g_buf_use_sync
)
port map (
-- Memory-mapped clock domain
@@ -199,8 +211,10 @@ begin
g_nof_streams => g_nof_streams,
g_use_steps => g_use_steps,
g_nof_steps => g_nof_steps,
- g_seq_dat_w => g_seq_dat_w, -- >= 1, test sequence data width
- g_data_w => g_data_w -- >= g_seq_dat_w, user data width
+ -- >= 1, test sequence data width
+ g_seq_dat_w => g_seq_dat_w,
+ -- >= g_seq_dat_w, user data width
+ g_data_w => g_data_w
)
port map (
-- Clocks and reset
@@ -210,7 +224,8 @@ begin
dp_clk => dp_clk,
-- Memory Mapped Slave
- reg_mosi => reg_rx_seq_mosi, -- multiplexed port for g_nof_streams MM control/status registers
+ -- multiplexed port for g_nof_streams MM control/status registers
+ reg_mosi => reg_rx_seq_mosi,
reg_miso => reg_rx_seq_miso,
-- Streaming interface
diff --git a/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd b/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
index 6bfbb0dab81cfb0eead674bfed767537174eca87..2fe6d81b9d513ef763e83d1a0300c00127e4f32c 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
@@ -73,16 +73,22 @@ entity mms_diag_data_buffer_dev is
g_use_db : boolean := true;
g_use_rx_seq : boolean := false;
-- General
- g_nof_streams : positive := 16; -- each stream gets an data buffer
+ -- each stream gets an data buffer
+ g_nof_streams : positive := 16;
-- DB settings
- g_data_type : t_diag_data_type_enum := e_data; -- define the sosi field that gets stored: e_data=data, e_complex=im&re, e_real=re, e_imag=im
- g_data_w : natural := 32; -- the g_data_w is the width of the data, re, im values or of the combined im&re value
- g_buf_nof_data : natural := 1024; -- nof words per data buffer
- g_buf_use_sync : boolean := false; -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ -- define the sosi field that gets stored: e_data=data, e_complex=im&re, e_real=re, e_imag=im
+ g_data_type : t_diag_data_type_enum := e_data;
+ -- the g_data_w is the width of the data, re, im values or of the combined im&re value
+ g_data_w : natural := 32;
+ -- nof words per data buffer
+ g_buf_nof_data : natural := 1024;
+ -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ g_buf_use_sync : boolean := false;
-- Rx_seq
g_use_steps : boolean := false;
g_nof_steps : natural := c_diag_seq_rx_reg_nof_steps;
- g_seq_dat_w : natural := 32 -- >= 1, test sequence data width. Choose g_seq_dat_w <= g_data_w
+ -- >= 1, test sequence data width. Choose g_seq_dat_w <= g_data_w
+ g_seq_dat_w : natural := 32
);
port (
-- System
@@ -91,17 +97,21 @@ entity mms_diag_data_buffer_dev is
dp_rst : in std_logic;
dp_clk : in std_logic;
-- MM interface
- reg_data_buf_mosi : in t_mem_mosi := c_mem_mosi_rst; -- DB control register (one per stream)
+ -- DB control register (one per stream)
+ reg_data_buf_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_data_buf_miso : out t_mem_miso;
- ram_data_buf_mosi : in t_mem_mosi := c_mem_mosi_rst; -- DB buffer RAM (one per streams)
+ -- DB buffer RAM (one per streams)
+ ram_data_buf_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_data_buf_miso : out t_mem_miso;
- reg_rx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst; -- Rx seq control register (one per streams)
+ -- Rx seq control register (one per streams)
+ reg_rx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_rx_seq_miso : out t_mem_miso;
-- ST interface
- in_sync : in std_logic := '0'; -- input sync pulse in ST dp_clk domain that starts data buffer when g_use_in_sync = TRUE
+ -- input sync pulse in ST dp_clk domain that starts data buffer when g_use_in_sync = TRUE
+ in_sync : in std_logic := '0';
in_sosi_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0);
out_wr_done_arr : out std_logic_vector(g_nof_streams - 1 downto 0)
);
@@ -159,14 +169,16 @@ begin
in_data_arr(I) <= in_sosi_arr(I).im(g_data_w / 2 - 1 downto 0) & in_sosi_arr(I).re(g_data_w / 2 - 1 downto 0) when g_data_type = e_complex else
in_sosi_arr(I).re(g_data_w - 1 downto 0) when g_data_type = e_real else
in_sosi_arr(I).im(g_data_w - 1 downto 0) when g_data_type = e_imag else
- in_sosi_arr(I).data(g_data_w - 1 downto 0); -- g_data_type=e_data is default
+ -- g_data_type=e_data is default
+ in_sosi_arr(I).data(g_data_w - 1 downto 0);
u_diag_data_buffer : entity work.diag_data_buffer_dev
generic map (
g_technology => g_technology,
g_data_w => g_data_w,
g_nof_data => g_buf_nof_data,
- g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ g_use_in_sync => g_buf_use_sync
)
port map (
-- Memory-mapped clock domain
@@ -201,8 +213,10 @@ begin
g_nof_streams => g_nof_streams,
g_use_steps => g_use_steps,
g_nof_steps => g_nof_steps,
- g_seq_dat_w => g_seq_dat_w, -- >= 1, test sequence data width
- g_data_w => g_data_w -- >= g_seq_dat_w, user data width
+ -- >= 1, test sequence data width
+ g_seq_dat_w => g_seq_dat_w,
+ -- >= g_seq_dat_w, user data width
+ g_data_w => g_data_w
)
port map (
-- Clocks and reset
@@ -212,7 +226,8 @@ begin
dp_clk => dp_clk,
-- Memory Mapped Slave
- reg_mosi => reg_rx_seq_mosi, -- multiplexed port for g_nof_streams MM control/status registers
+ -- multiplexed port for g_nof_streams MM control/status registers
+ reg_mosi => reg_rx_seq_mosi,
reg_miso => reg_rx_seq_miso,
-- Streaming interface
diff --git a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
index f3c7d796454e03e08a8990fb66ca7c26beabd44d..658f0b2ccaa9f97093077bcad185d47026c83a10 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
@@ -108,18 +108,25 @@ entity mms_diag_rx_seq is
g_nof_streams : natural := 1;
g_use_steps : boolean := false;
g_nof_steps : natural := c_diag_seq_rx_reg_nof_steps;
- g_seq_dat_w : natural := c_word_w; -- >= 1, test sequence data width
- g_data_w : natural := c_word_w -- >= g_seq_dat_w, user data width
+ -- >= 1, test sequence data width
+ g_seq_dat_w : natural := c_word_w;
+ -- >= g_seq_dat_w, user data width
+ g_data_w : natural := c_word_w
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- MM bus clock
- dp_rst : in std_logic; -- reset synchronous with dp_clk
- dp_clk : in std_logic; -- DP streaming bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- MM bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with dp_clk
+ dp_rst : in std_logic;
+ -- DP streaming bus clock
+ dp_clk : in std_logic;
-- Memory Mapped Slave
- reg_mosi : in t_mem_mosi; -- multiplexed port for g_nof_streams MM control/status registers
+ -- multiplexed port for g_nof_streams MM control/status registers
+ reg_mosi : in t_mem_mosi;
reg_miso : out t_mem_miso;
-- Streaming interface
@@ -131,19 +138,28 @@ architecture str of mms_diag_rx_seq is
-- Define MM slave register size
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => c_diag_seq_rx_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_diag_seq_rx_reg_nof_dat,
init_sl => '0');
-- Define MM slave register fields for Python peripheral using pi_common.py (specify MM register access per word, not per individual bit because mm_fields assumes 1 field per MM word)
- constant c_mm_reg_field_arr : t_common_field_arr(c_mm_reg.nof_dat - 1 downto 0) := ( ( field_name_pad("step_3"), "RW", c_word_w, field_default(0) ), -- [7] = diag_steps_arr[3], c_diag_seq_rx_reg_nof_steps = 4
- ( field_name_pad("step_2"), "RW", c_word_w, field_default(0) ), -- [6] = diag_steps_arr[2]
- ( field_name_pad("step_1"), "RW", c_word_w, field_default(0) ), -- [5] = diag_steps_arr[1]
- ( field_name_pad("step_0"), "RW", c_word_w, field_default(0) ), -- [4] = diag_steps_arr[0]
- ( field_name_pad("rx_sample"), "RO", c_word_w, field_default(0) ), -- [3]
- ( field_name_pad("rx_cnt"), "RO", c_word_w, field_default(0) ), -- [2]
- ( field_name_pad("result"), "RO", 2, field_default(0) ), -- [1] = result[1:0] = res_val_n & res_ok_n
- ( field_name_pad("control"), "RW", 2, field_default(0) )); -- [0] = control[1:0] = diag_sel & diag_en
+ -- [7] = diag_steps_arr[3], c_diag_seq_rx_reg_nof_steps = 4
+ constant c_mm_reg_field_arr : t_common_field_arr(c_mm_reg.nof_dat - 1 downto 0) := ( ( field_name_pad("step_3"), "RW", c_word_w, field_default(0) ),
+ -- [6] = diag_steps_arr[2]
+ ( field_name_pad("step_2"), "RW", c_word_w, field_default(0) ),
+ -- [5] = diag_steps_arr[1]
+ ( field_name_pad("step_1"), "RW", c_word_w, field_default(0) ),
+ -- [4] = diag_steps_arr[0]
+ ( field_name_pad("step_0"), "RW", c_word_w, field_default(0) ),
+ -- [3]
+ ( field_name_pad("rx_sample"), "RO", c_word_w, field_default(0) ),
+ -- [2]
+ ( field_name_pad("rx_cnt"), "RO", c_word_w, field_default(0) ),
+ -- [1] = result[1:0] = res_val_n & res_ok_n
+ ( field_name_pad("result"), "RO", 2, field_default(0) ),
+ -- [0] = control[1:0] = diag_sel & diag_en
+ ( field_name_pad("control"), "RW", 2, field_default(0) ));
constant c_reg_slv_w : natural := c_mm_reg.nof_dat * c_mm_reg.dat_w;
constant c_reg_dat_w : natural := smallest(c_word_w, g_seq_dat_w);
@@ -166,7 +182,8 @@ architecture str of mms_diag_rx_seq is
signal diag_sel_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal diag_steps_2arr : t_steps_2arr(g_nof_streams - 1 downto 0);
- signal rx_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0); -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
+ -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
+ signal rx_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0);
signal rx_sample_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0);
signal rx_sample_diff_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0);
signal rx_sample_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -199,7 +216,8 @@ begin
-- keep sequence in low bits if the high bits match otherwise force low bits value to -1 to indicate the mismatch
p_rx_seq : process(dp_clk)
begin
- if rising_edge(dp_clk) then -- register to ease timing closure
+ -- register to ease timing closure
+ if rising_edge(dp_clk) then
if unsigned(rx_data_arr(I)(g_data_w - 1 downto g_seq_dat_w)) = 0 then
rx_seq_arr(I) <= rx_data_arr(I)(g_seq_dat_w - 1 downto 0);
else
@@ -217,7 +235,8 @@ begin
g_nof_steps => g_nof_steps,
g_cnt_w => c_word_w,
g_dat_w => g_seq_dat_w,
- g_diag_res_w => g_seq_dat_w -- do not use g_seq_dat_w+1 to include NOT diag_res_val in MSbit, instead use diag_res_val output
+ -- do not use g_seq_dat_w+1 to include NOT diag_res_val in MSbit, instead use diag_res_val output
+ g_diag_res_w => g_seq_dat_w
)
port map (
rst => dp_rst,
@@ -247,29 +266,38 @@ begin
-- Register mapping
-- . write ctrl_reg_arr
- diag_en_arr(I) <= ctrl_reg_arr(I)(0); -- address 0, data bit [0]
- diag_sel_arr(I) <= ctrl_reg_arr(I)(1); -- address 0, data bit [1]
+ -- address 0, data bit [0]
+ diag_en_arr(I) <= ctrl_reg_arr(I)(0);
+ -- address 0, data bit [1]
+ diag_sel_arr(I) <= ctrl_reg_arr(I)(1);
gen_diag_steps_2arr : for J in 0 to g_nof_steps - 1 generate
- diag_steps_2arr(I)(J) <= TO_SINT(ctrl_reg_arr(I)(c_reg_dat_w - 1 + (c_nof_steps_wi + J) * c_word_w downto (c_nof_steps_wi + J) * c_word_w)); -- address 4, 5, 6, 7
+ -- address 4, 5, 6, 7
+ diag_steps_2arr(I)(J) <= TO_SINT(ctrl_reg_arr(I)(c_reg_dat_w - 1 + (c_nof_steps_wi + J) * c_word_w downto (c_nof_steps_wi + J) * c_word_w));
end generate;
-- . read stat_reg_arr
p_stat_reg_arr : process(ctrl_reg_arr, stat_res_ok_n_arr, stat_res_val_n_arr, rx_cnt_arr, rx_sample_arr)
begin
-- Default write / readback:
- stat_reg_arr(I) <= ctrl_reg_arr(I); -- default control read back
+ -- default control read back
+ stat_reg_arr(I) <= ctrl_reg_arr(I);
-- Status read only:
- stat_reg_arr(I)( 0 + 1 * c_word_w) <= stat_res_ok_n_arr(I); -- address 1, data bit [0]
- stat_reg_arr(I)( 1 + 1 * c_word_w) <= stat_res_val_n_arr(I); -- address 1, data bit [1]
- stat_reg_arr(I)(3 * c_word_w - 1 downto 2 * c_word_w) <= rx_cnt_arr(I); -- address 2: read rx_cnt per stream
- stat_reg_arr(I)(4 * c_word_w - 1 downto 3 * c_word_w) <= RESIZE_UVEC(rx_sample_arr(I), c_word_w); -- address 3: read valid sample per stream
+ -- address 1, data bit [0]
+ stat_reg_arr(I)( 0 + 1 * c_word_w) <= stat_res_ok_n_arr(I);
+ -- address 1, data bit [1]
+ stat_reg_arr(I)( 1 + 1 * c_word_w) <= stat_res_val_n_arr(I);
+ -- address 2: read rx_cnt per stream
+ stat_reg_arr(I)(3 * c_word_w - 1 downto 2 * c_word_w) <= rx_cnt_arr(I);
+ -- address 3: read valid sample per stream
+ stat_reg_arr(I)(4 * c_word_w - 1 downto 3 * c_word_w) <= RESIZE_UVEC(rx_sample_arr(I), c_word_w);
end process;
u_reg : entity common_lib.common_reg_r_w_dc
generic map (
g_cross_clock_domain => true,
- g_readback => false, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+ -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+ g_readback => false,
g_reg => c_mm_reg
)
port map (
diff --git a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
index 879b31e63223a9fea3b2d43bb5e8465c5d81e3be..514e48912793ce0dadc7648c39fd4282bc90800c 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
@@ -149,7 +149,8 @@
-- which can be useful to ensure that reading e.g. address 2**g_seq_dat_w
-- yields a different CNTR value than reading 2**(g_seq_dat_w+1).
-library IEEE, common_lib, dp_lib; -- init value for out_dat when diag_en = '0'
+-- init value for out_dat when diag_en = '0'
+library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
@@ -162,24 +163,31 @@ entity mms_diag_tx_seq is
g_use_usr_input : boolean := false;
g_mm_broadcast : boolean := false;
g_nof_streams : natural := 1;
- g_seq_dat_w : natural := c_word_w -- >= 1, test sequence data width
+ -- >= 1, test sequence data width
+ g_seq_dat_w : natural := c_word_w
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- MM bus clock
- dp_rst : in std_logic; -- reset synchronous with dp_clk
- dp_clk : in std_logic; -- DP streaming bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- MM bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with dp_clk
+ dp_rst : in std_logic;
+ -- DP streaming bus clock
+ dp_clk : in std_logic;
-- MM interface
- reg_mosi : in t_mem_mosi; -- single MM control register applied to all g_nof_streams
+ -- single MM control register applied to all g_nof_streams
+ reg_mosi : in t_mem_mosi;
reg_miso : out t_mem_miso;
-- DP streaming interface
usr_snk_out_arr : out t_dp_siso_arr(g_nof_streams - 1 downto 0);
usr_snk_in_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
tx_src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- tx_src_in_arr : in t_dp_siso_arr(g_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy) -- Default xon='1';
+ -- Default xon='1';
+ tx_src_in_arr : in t_dp_siso_arr(g_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy)
);
end mms_diag_tx_seq;
@@ -187,7 +195,8 @@ architecture str of mms_diag_tx_seq is
-- Define MM slave register size
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => c_diag_seq_tx_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_diag_seq_tx_reg_nof_dat,
init_sl => '0');
@@ -195,11 +204,13 @@ architecture str of mms_diag_tx_seq is
constant c_mm_reg_field_arr : t_common_field_arr(c_mm_reg.nof_dat - 1 downto 0) := ( ( field_name_pad("modulo"), "RW", c_word_w, field_default(0) ),
( field_name_pad("tx_cnt"), "RO", c_word_w, field_default(0) ),
( field_name_pad("init"), "RW", c_word_w, field_default(0) ),
- ( field_name_pad("control"), "RW", 3, field_default(0) )); -- control[2:0] = diag_dc & diag_sel & diag_en
+ -- control[2:0] = diag_dc & diag_sel & diag_en
+ ( field_name_pad("control"), "RW", 3, field_default(0) ));
constant c_reg_slv_w : natural := c_mm_reg.nof_dat * c_mm_reg.dat_w;
- constant c_latency : natural := sel_a_b(g_use_usr_input, 0, 1); -- default 1 for registered diag_tx_seq out_cnt/dat/val output, use 0 for immediate combinatorial diag_tx_seq out_cnt/dat/val output
+ -- default 1 for registered diag_tx_seq out_cnt/dat/val output, use 0 for immediate combinatorial diag_tx_seq out_cnt/dat/val output
+ constant c_latency : natural := sel_a_b(g_use_usr_input, 0, 1);
type t_reg_slv_arr is array (integer range <>) of std_logic_vector(c_reg_slv_w - 1 downto 0);
type t_seq_dat_arr is array (integer range <>) of std_logic_vector(g_seq_dat_w - 1 downto 0);
@@ -216,13 +227,16 @@ architecture str of mms_diag_tx_seq is
signal diag_sel_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal diag_dc_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal diag_init_mm_arr : t_slv_32_arr(g_nof_streams - 1 downto 0) := (others => (others => '0')); -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
+ -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
+ signal diag_init_mm_arr : t_slv_32_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
signal diag_init_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
- signal diag_mod_mm_arr : t_slv_32_arr(g_nof_streams - 1 downto 0) := (others => (others => '0')); -- can use t_slv_32_arr because c -- init value for out_dat when diag_en = '0'_mm_reg.dat_w = c_word_w = 32 fixed
+ -- can use t_slv_32_arr because c -- init value for out_dat when diag_en = '0'_mm_reg.dat_w = c_word_w = 32 fixed
+ signal diag_mod_mm_arr : t_slv_32_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
signal diag_mod_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
- signal tx_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0); -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
+ -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
+ signal tx_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0);
signal tx_dat_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0);
signal tx_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal tx_req_arr : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -230,10 +244,12 @@ architecture str of mms_diag_tx_seq is
signal tx_replicate_dat_arr : t_dp_data_slv_arr(g_nof_streams - 1 downto 0);
signal tx_seq_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
- signal tx_seq_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst); -- default set all other fields then data and valid to inactive.
+ -- default set all other fields then data and valid to inactive.
+ signal tx_seq_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
-- Use user input or self generate
- signal mux_seq_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0); -- multiplex user sosi control with tx_seq data
+ -- multiplex user sosi control with tx_seq data
+ signal mux_seq_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
signal mux_seq_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
begin
@@ -272,11 +288,16 @@ begin
tx_seq_src_out_arr(I).valid <= tx_val_arr(I);
-- Register mapping
- diag_en_arr(I) <= ctrl_reg_arr(I)( 0); -- address 0, data bit [0]
- diag_sel_arr(I) <= ctrl_reg_arr(I)( 1); -- address 0, data bit [1]
- diag_dc_arr(I) <= ctrl_reg_arr(I)( 2); -- address 0, data bit [2]
- diag_init_mm_arr(I) <= ctrl_reg_arr(I)(2 * c_word_w - 1 downto c_word_w); -- address 1, data bits [31:0]
- diag_mod_mm_arr(I) <= ctrl_reg_arr(I)(4 * c_word_w - 1 downto 3 * c_word_w); -- address 3, data bits [31:0]
+ -- address 0, data bit [0]
+ diag_en_arr(I) <= ctrl_reg_arr(I)( 0);
+ -- address 0, data bit [1]
+ diag_sel_arr(I) <= ctrl_reg_arr(I)( 1);
+ -- address 0, data bit [2]
+ diag_dc_arr(I) <= ctrl_reg_arr(I)( 2);
+ -- address 1, data bits [31:0]
+ diag_init_mm_arr(I) <= ctrl_reg_arr(I)(2 * c_word_w - 1 downto c_word_w);
+ -- address 3, data bits [31:0]
+ diag_mod_mm_arr(I) <= ctrl_reg_arr(I)(4 * c_word_w - 1 downto 3 * c_word_w);
diag_init_arr(I) <= RESIZE_UVEC(diag_init_mm_arr(I), g_seq_dat_w);
diag_mod_arr(I) <= RESIZE_UVEC(diag_mod_mm_arr(I), g_seq_dat_w);
@@ -284,15 +305,18 @@ begin
p_stat_reg : process(ctrl_reg_arr(I), tx_cnt_arr)
begin
-- Default write / readback:
- stat_reg_arr(I) <= ctrl_reg_arr(I); -- address 0, 1: control read back
+ -- address 0, 1: control read back
+ stat_reg_arr(I) <= ctrl_reg_arr(I);
-- Status read only:
- stat_reg_arr(I)(3 * c_word_w - 1 downto 2 * c_word_w) <= tx_cnt_arr(I); -- address 2: read tx_cnt
+ -- address 2: read tx_cnt
+ stat_reg_arr(I)(3 * c_word_w - 1 downto 2 * c_word_w) <= tx_cnt_arr(I);
end process;
u_reg : entity common_lib.common_reg_r_w_dc
generic map (
g_cross_clock_domain => true,
- g_readback => false, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+ -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+ g_readback => false,
g_reg => c_mm_reg
)
port map (
@@ -307,7 +331,8 @@ begin
sla_out => reg_miso_arr(I),
-- MM registers in dp_clk domain
- in_reg => stat_reg_arr(I), -- connect out_reg to in_reg for write and readback register
+ -- connect out_reg to in_reg for write and readback register
+ in_reg => stat_reg_arr(I),
out_reg => ctrl_reg_arr(I)
);
end generate;
@@ -334,10 +359,12 @@ begin
-- data
p_tx_src_out_arr : process (usr_snk_in_arr, tx_seq_src_out_arr, diag_en_arr)
begin
- tx_src_out_arr <= usr_snk_in_arr; -- Default pass on the usr data
+ -- Default pass on the usr data
+ tx_src_out_arr <= usr_snk_in_arr;
for I in 0 to g_nof_streams - 1 loop
if diag_en_arr(I) = '1' then
- tx_src_out_arr(I) <= tx_seq_src_out_arr(I); -- When diag is enabled then pass on the Tx seq data
+ -- When diag is enabled then pass on the Tx seq data
+ tx_src_out_arr(I) <= tx_seq_src_out_arr(I);
end if;
end loop;
end process;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
index f23fda685ab1f622c0321940856a5ca84a576d68..ff5727656f959026592010d5efad464b24eee997 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
@@ -45,7 +45,8 @@ entity mms_diag_wg_wideband is
g_buf_dir : string := "data/";
-- Wideband parameters
- g_wideband_factor : natural := 4; -- Wideband rate factor >= 1 for unit frequency of g_wideband_factor * Fs
+ -- Wideband rate factor >= 1 for unit frequency of g_wideband_factor * Fs
+ g_wideband_factor : natural := 4;
-- Basic WG parameters, see diag_wg.vhd for their meaning
g_buf_dat_w : natural := 18;
@@ -70,7 +71,8 @@ entity mms_diag_wg_wideband is
st_clk : in std_logic;
st_restart : in std_logic := '0';
- out_ovr : out std_logic_vector(g_wideband_factor - 1 downto 0); -- big endian, so first output sample in MSBit, MSData
+ -- big endian, so first output sample in MSBit, MSData
+ out_ovr : out std_logic_vector(g_wideband_factor - 1 downto 0);
out_dat : out std_logic_vector(g_wideband_factor * g_buf_dat_w - 1 downto 0);
out_val : out std_logic_vector(g_wideband_factor - 1 downto 0);
out_sync : out std_logic_vector(g_wideband_factor - 1 downto 0)
@@ -78,8 +80,10 @@ entity mms_diag_wg_wideband is
end mms_diag_wg_wideband;
architecture str of mms_diag_wg_wideband is
- signal st_wg_ctrl : t_diag_wg; -- write
- signal st_mon_ctrl : t_diag_wg; -- read
+ -- write
+ signal st_wg_ctrl : t_diag_wg;
+ -- read
+ signal st_mon_ctrl : t_diag_wg;
begin
u_mm_reg : entity work.diag_wg_wideband_reg
generic map (
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
index aa5b1be2c4a74ae4c5562355099407b9ae6428c3..31adeff51cb26c14eefbf8262fc7382aef29c64d 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
@@ -46,7 +46,8 @@ entity mms_diag_wg_wideband_arr is
g_buf_dir : string := "data/";
-- Wideband parameters
- g_wideband_factor : natural := 4; -- Wideband rate factor >= 1 for unit frequency of g_wideband_factor * Fs
+ -- Wideband rate factor >= 1 for unit frequency of g_wideband_factor * Fs
+ g_wideband_factor : natural := 4;
-- Basic WG parameters, see diag_wg.vhd for their meaning
g_buf_dat_w : natural := 18;
@@ -83,7 +84,8 @@ architecture str of mms_diag_wg_wideband_arr is
signal buf_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal buf_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
- signal wg_ovr : std_logic_vector(g_nof_streams * g_wideband_factor - 1 downto 0); -- big endian, so first output sample in MSBit, MSData
+ -- big endian, so first output sample in MSBit, MSData
+ signal wg_ovr : std_logic_vector(g_nof_streams * g_wideband_factor - 1 downto 0);
signal wg_dat : std_logic_vector(g_nof_streams * g_wideband_factor * g_buf_dat_w - 1 downto 0);
signal wg_val : std_logic_vector(g_nof_streams * g_wideband_factor - 1 downto 0);
signal wg_sync : std_logic_vector(g_nof_streams * g_wideband_factor - 1 downto 0);
@@ -156,7 +158,8 @@ begin
out_sosi_arr(I).sync <= vector_or(wg_sync((I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ));
out_sosi_arr(I).err <= TO_DP_ERROR(0) when
vector_or(wg_ovr( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor )) = '0' else
- TO_DP_ERROR(2**7); -- pass ADC or WG overflow info on as an error signal
+ -- pass ADC or WG overflow info on as an error signal
+ TO_DP_ERROR(2**7);
end generate;
end str;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
index 4ec82902c6ca8e98b25b9a1fada143f717c71bd9..5ee894958643be9328ebdc4b2f8b44372ea6dcb3 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
@@ -43,14 +43,21 @@ use work.diag_pkg.all;
entity tb_diag_block_gen is
generic (
-- general
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
- g_nof_samples_per_packet : natural := 2; -- >= 2
- g_nof_blocks_per_sync : natural := 10; -- >= 1
- g_gapsize : natural := 32; -- >= 0
- g_buf_adr_w : natural := 7; -- Waveform buffer address width (requires corresponding c_buf_file)
- g_buf_dat_w : natural := 32; -- Waveform buffer stored data width (requires corresponding c_buf_file)
- g_try_phasor : boolean := false -- use TRUE to see BG phasor in wave window with out_sosi.re/im in radix
+ -- >= 2
+ g_nof_samples_per_packet : natural := 2;
+ -- >= 1
+ g_nof_blocks_per_sync : natural := 10;
+ -- >= 0
+ g_gapsize : natural := 32;
+ -- Waveform buffer address width (requires corresponding c_buf_file)
+ g_buf_adr_w : natural := 7;
+ -- Waveform buffer stored data width (requires corresponding c_buf_file)
+ g_buf_dat_w : natural := 32;
+ -- use TRUE to see BG phasor in wave window with out_sosi.re/im in radix
+ g_try_phasor : boolean := false
-- decimal and analogue format, no self test
);
end tb_diag_block_gen;
@@ -65,7 +72,8 @@ architecture tb of tb_diag_block_gen is
constant c_buf : t_c_mem := (latency => 1,
adr_w => g_buf_adr_w,
dat_w => g_buf_dat_w,
- nof_dat => 2**g_buf_adr_w, -- = 2**adr_w
+ -- = 2**adr_w
+ nof_dat => 2**g_buf_adr_w,
init_sl => '0');
constant c_buf_file : string := sel_a_b(c_buf.adr_w = 7 and c_buf.dat_w = 32, "data/diag_block.hex", "UNUSED");
@@ -79,9 +87,12 @@ architecture tb of tb_diag_block_gen is
-- To create an FFT input phasor with frequency in the middle of a channel use FREQ = ch.
constant c_phasor_nof_points : natural := 96;
constant c_phasor_dat_w : natural := g_buf_dat_w / c_nof_complex;
- constant c_phasor_unit_ampl : real := real(2**(c_phasor_dat_w - 1) - 1); -- max = full scale - 1
- constant c_phasor_ampl : real := 1.0 * c_phasor_unit_ampl; -- use g_phasor_ampl <= 1.0 to avoid wrapping
- constant c_phasor_freq : real := 2.0; -- in range -N/2 : N/2-1
+ -- max = full scale - 1
+ constant c_phasor_unit_ampl : real := real(2**(c_phasor_dat_w - 1) - 1);
+ -- use g_phasor_ampl <= 1.0 to avoid wrapping
+ constant c_phasor_ampl : real := 1.0 * c_phasor_unit_ampl;
+ -- in range -N/2 : N/2-1
+ constant c_phasor_freq : real := 2.0;
constant c_phasor_phase : real := 0.0;
constant c_phasor_exp_arr : t_slv_32_arr := common_math_create_look_up_table_phasor(c_phasor_nof_points,
c_phasor_dat_w,
@@ -134,7 +145,8 @@ architecture tb of tb_diag_block_gen is
signal bg_ctrl : t_diag_block_gen;
signal bg_ctrl_hold : t_diag_block_gen;
- signal random : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(14 downto 0) := (others => '0');
signal toggle : std_logic := '0';
signal out_siso_bg : t_dp_siso := c_dp_siso_rdy;
signal out_siso : t_dp_siso;
@@ -153,7 +165,8 @@ begin
begin
out_siso <= c_dp_siso_rdy;
bg_ctrl <= c_bg_ctrl;
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
+ -- Wait until reset has finished
+ proc_common_wait_until_low(clk, rst);
proc_common_wait_some_cycles(clk, 10);
-- Write waveform buffer
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd b/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
index 730f6e6fd09da0c50d49770af15a43ab66d7cb46..a15d8a44e689e7cfa06929ec40242f9f8a09905c 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
@@ -52,9 +52,11 @@ use work.diag_pkg.all;
entity tb_diag_data_buffer is
generic(
- g_nof_streams : positive := 2; -- = 16
+ -- = 16
+ g_nof_streams : positive := 2;
g_nof_data : positive := 128;
- g_data_w : positive := 16 -- = 16
+ -- = 16
+ g_data_w : positive := 16
);
end tb_diag_data_buffer;
@@ -111,8 +113,10 @@ architecture tb of tb_diag_data_buffer is
constant c_bg_nof_blocks_per_sync : natural := 8;
constant c_bg_mem_high_addr : natural := g_nof_data - 1;
- constant c_bg_ctrl : t_diag_block_gen := ( '0', -- enable: On by default in simulation; MM enable required on hardware.
- '0', -- enable_sync
+ -- enable: On by default in simulation; MM enable required on hardware.
+ constant c_bg_ctrl : t_diag_block_gen := ( '0',
+ -- enable_sync
+ '0',
TO_UVEC( c_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd b/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
index 0156020ba1138a03ae236d87d53eddbba45c1bfb..b1984e24cbe2649d4e7c5b0daacf393a316fc963 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
@@ -37,8 +37,10 @@ architecture tb of tb_diag_frm_generator is
constant c_period : time := 100 ns;
constant c_nof_cycles : natural := 200;
- constant c_sel : std_logic := '1'; -- select COUNTER sequence
- constant c_frame_len : natural := 20; -- >= 2, test frame length
+ -- select COUNTER sequence
+ constant c_sel : std_logic := '1';
+ -- >= 2, test frame length
+ constant c_frame_len : natural := 20;
constant c_frame_len_w : natural := ceil_log2(c_frame_len);
constant c_sof_period : natural := 35;
constant c_sof_period_w : natural := ceil_log2(c_sof_period);
@@ -64,7 +66,8 @@ architecture tb of tb_diag_frm_generator is
signal seq_val : std_logic;
signal seq_sop : std_logic;
signal seq_eop : std_logic;
- signal seq_empty : std_logic_vector(c_empty_w - 1 downto 0); -- nof empty symbols in last out_dat word marked by out_eop
+ -- nof empty symbols in last out_dat word marked by out_eop
+ signal seq_empty : std_logic_vector(c_empty_w - 1 downto 0);
signal init_dat : std_logic_vector(c_dat_w - 1 downto 0);
begin
@@ -83,16 +86,19 @@ begin
-- Keep seq_req='1'
seq_req <= '1';
wait for c_period;
- diag_en <= '1'; -- Enable frames generator
+ -- Enable frames generator
+ diag_en <= '1';
wait for c_nof_cycles * c_period;
wait for 10 * c_period;
- diag_en <= '0'; -- Disable frames generator
+ -- Disable frames generator
+ diag_en <= '0';
wait for c_nof_cycles * c_period;
-- Toggle seq_req='1'
seq_req <= '1';
wait for c_period;
- diag_en <= '1'; -- Enable frames generator
+ -- Enable frames generator
+ diag_en <= '1';
wait for 20 * c_period;
for I in 0 to c_sof_period loop
seq_req <= '0';
@@ -116,7 +122,8 @@ begin
end loop;
wait for c_nof_cycles * c_period;
wait for 10 * c_period;
- diag_en <= '0'; -- Disable frames generator
+ -- Disable frames generator
+ diag_en <= '0';
wait for c_nof_cycles * c_period;
tb_end <= '1';
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd b/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
index ef5aa9aa48e93ec8f7de2ecba6b89e29951dab31..e1ee6ca514ae2d0cee1c4c2f685da327f9ba7257 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
@@ -37,8 +37,10 @@ architecture tb of tb_diag_frm_monitor is
constant c_period : time := 100 ns;
constant c_nof_cycles : natural := 200;
- constant c_sel : std_logic := '1'; -- select COUNTER sequence
- constant c_frame_len : natural := 20; -- >= 2, test frame length
+ -- select COUNTER sequence
+ constant c_sel : std_logic := '1';
+ -- >= 2, test frame length
+ constant c_frame_len : natural := 20;
constant c_frame_len_w : natural := ceil_log2(c_frame_len);
constant c_sof_period : natural := 35;
constant c_sof_period_w : natural := ceil_log2(c_sof_period);
@@ -87,34 +89,45 @@ begin
-- Keep seq_req='1'
wait for c_period;
- gen_diag_en <= '1'; -- Enable frames generator
- mon_diag_en <= '1'; -- Enable frames monitor
+ -- Enable frames generator
+ gen_diag_en <= '1';
+ -- Enable frames monitor
+ mon_diag_en <= '1';
wait for c_nof_cycles * c_period;
- gen_diag_en <= '0'; -- Disable frames generator
- mon_diag_en <= '0'; -- Disable frames monitor
+ -- Disable frames generator
+ gen_diag_en <= '0';
+ -- Disable frames monitor
+ mon_diag_en <= '0';
wait for c_nof_cycles * c_period;
assert unsigned(gen_diag_frame_cnt) = unsigned(mon_diag_frame_cnt) report "wrong gen or mon count.";
wait for 10 * c_period;
-- Again
wait for c_period;
- gen_diag_en <= '1'; -- Enable frames generator
- mon_diag_en <= '1'; -- Enable frames monitor
+ -- Enable frames generator
+ gen_diag_en <= '1';
+ -- Enable frames monitor
+ mon_diag_en <= '1';
wait for c_nof_cycles * c_period;
- mon_diag_en <= '0'; -- Disable frames monitor
+ -- Disable frames monitor
+ mon_diag_en <= '0';
wait for 10 * c_period;
assert unsigned(mon_diag_frame_cnt) = unsigned(gen_diag_frame_cnt) report "Wrong gen or mon count.";
assert unsigned(mon_diag_error_cnt) = 0 report "Error count should be 0.";
hld_frame_cnt <= TO_UINT(gen_diag_frame_cnt);
- mon_diag_en <= '1'; -- Enable frames monitor
+ -- Enable frames monitor
+ mon_diag_en <= '1';
wait for 10 * c_period;
- seq_error <= '1'; -- force error for at leat one rx frame
+ -- force error for at leat one rx frame
+ seq_error <= '1';
wait for 2 * c_sof_period * c_period;
wait for 10 * c_period;
seq_error <= '0';
wait for 5 * c_nof_cycles * c_period;
- gen_diag_en <= '0'; -- Disable frames generator
- mon_diag_en <= '0'; -- Disable frames monitor
+ -- Disable frames generator
+ gen_diag_en <= '0';
+ -- Disable frames monitor
+ mon_diag_en <= '0';
assert unsigned(mon_diag_frame_cnt) = unsigned(gen_diag_frame_cnt) - hld_frame_cnt report "Wrong gen or mon count.";
assert unsigned(mon_diag_error_cnt) /= 0 report "Error count should be > 0.";
wait for 10 * c_period;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
index 9d1b3946753ba9eae94ac0768778b91611cb23a9..5f845c153ceb97098fc8267387da6260c8613a62 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
@@ -49,57 +49,75 @@ package tb_diag_pkg is
signal tx_mosi : out t_mem_mosi;
signal rx_miso : in t_mem_miso;
signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+ -- read all MM reg
+ signal rd_reg : out t_diag_seq_mm_reg);
procedure proc_diag_seq_tx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
+ -- "PSRG", "CNTR"
+ constant c_pattern : in string;
constant c_tx_init : in natural;
constant c_tx_mod : in natural;
signal mm_clk : in std_logic;
signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
+ -- tx ctrl
+ signal tx_miso : in t_mem_miso;
signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
+ -- rx ctrl
+ signal rx_miso : in t_mem_miso;
signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+ -- read all MM reg
+ signal rd_reg : out t_diag_seq_mm_reg);
procedure proc_diag_seq_rx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
+ -- "PSRG", "CNTR"
+ constant c_pattern : in string;
signal mm_clk : in std_logic;
signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
+ -- tx ctrl
+ signal tx_miso : in t_mem_miso;
signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
+ -- rx ctrl
+ signal rx_miso : in t_mem_miso;
signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+ -- read all MM reg
+ signal rd_reg : out t_diag_seq_mm_reg);
procedure proc_diag_seq_tx_disable(constant c_stream : in natural;
signal mm_clk : in std_logic;
signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
+ -- tx ctrl
+ signal tx_miso : in t_mem_miso;
signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
+ -- rx ctrl
+ signal rx_miso : in t_mem_miso;
signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+ -- read all MM reg
+ signal rd_reg : out t_diag_seq_mm_reg);
procedure proc_diag_seq_rx_disable(constant c_stream : in natural;
signal mm_clk : in std_logic;
signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
+ -- tx ctrl
+ signal tx_miso : in t_mem_miso;
signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
+ -- rx ctrl
+ signal rx_miso : in t_mem_miso;
signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+ -- read all MM reg
+ signal rd_reg : out t_diag_seq_mm_reg);
procedure proc_diag_seq_rx_write_steps(constant c_stream : in natural;
constant c_steps_arr : in t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0);
signal mm_clk : in std_logic;
signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
+ -- tx ctrl
+ signal tx_miso : in t_mem_miso;
signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
+ -- rx ctrl
+ signal rx_miso : in t_mem_miso;
signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+ -- read all MM reg
+ signal rd_reg : out t_diag_seq_mm_reg);
procedure proc_diag_seq_verify(constant c_stream : in natural;
signal mm_clk : in std_logic;
@@ -109,42 +127,67 @@ package tb_diag_pkg is
signal rx_mosi : out t_mem_mosi;
signal tb_mode : inout t_tb_diag_seq_mode_enum;
signal tb_verify : out std_logic;
- signal rd_reg : inout t_diag_seq_mm_reg); -- read all MM reg
+ -- read all MM reg
+ signal rd_reg : inout t_diag_seq_mm_reg);
-- Measure ADC/WG input power and determine effective sine amplitude
- procedure proc_diag_measure_cw_statistics(constant c_nof_samples : in natural; -- number of samples per in_start interval
+ -- number of samples per in_start interval
+ procedure proc_diag_measure_cw_statistics(constant c_nof_samples : in natural;
signal dp_clk : in std_logic;
signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of interval, e.g. sop or sync
+ -- start of interval, e.g. sop or sync
+ signal in_start : in std_logic;
signal in_val : in std_logic;
- signal track_max : inout real; -- store local tracker in signal
- signal track_min : inout real; -- store local tracker in signal
- signal accum_mean : inout real; -- store local accumulator in signal
- signal accum_power : inout real; -- store local accumulator in signal
- signal measured_max : out real; -- maximum sample value
- signal measured_min : out real; -- minimum sample value
- signal measured_mean : out real; -- average sample value (DC)
- signal measured_power : out real; -- average sample power
- signal measured_ampl : out real); -- corresponding sine amplitude
+ -- store local tracker in signal
+ signal track_max : inout real;
+ -- store local tracker in signal
+ signal track_min : inout real;
+ -- store local accumulator in signal
+ signal accum_mean : inout real;
+ -- store local accumulator in signal
+ signal accum_power : inout real;
+ -- maximum sample value
+ signal measured_max : out real;
+ -- minimum sample value
+ signal measured_min : out real;
+ -- average sample value (DC)
+ signal measured_mean : out real;
+ -- average sample power
+ signal measured_power : out real;
+ -- corresponding sine amplitude
+ signal measured_ampl : out real);
-- Measure ADC/WG amplitude and phase using local sin and cos
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_nof_samples : in natural; -- number of samples per in_start interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
+ -- number of samples per in_start interval
+ procedure proc_diag_measure_cw_ampl_and_phase(constant c_nof_samples : in natural;
+ -- number of points of FFT
+ constant c_fft_size : in natural;
+ -- subband index
+ constant c_sub : in real;
signal dp_clk : in std_logic;
signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ -- start of integration interval, e.g. sop or sync
+ signal in_start : in std_logic;
signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal ref_I : out real; -- output local I as signal for debugging in wave window
- signal ref_Q : out real; -- output local Q as signal for debugging in wave window
- signal accum_I : inout real; -- store local I accumulator in signal
- signal accum_Q : inout real; -- store local Q accumulator in signal
- signal measured_ampl : out real; -- measured CW amplitude
- signal measured_phase : out real; -- measured CW phase in radials
- signal measured_phase_Ts : out real); -- measured CW phase in sample periods
-
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
+ -- sample index in c_fft_size
+ signal in_cnt : in natural;
+ -- output local I as signal for debugging in wave window
+ signal ref_I : out real;
+ -- output local Q as signal for debugging in wave window
+ signal ref_Q : out real;
+ -- store local I accumulator in signal
+ signal accum_I : inout real;
+ -- store local Q accumulator in signal
+ signal accum_Q : inout real;
+ -- measured CW amplitude
+ signal measured_ampl : out real;
+ -- measured CW phase in radials
+ signal measured_phase : out real;
+ -- measured CW phase in sample periods
+ signal measured_phase_Ts : out real);
+
+ -- number of points of FFT = number of samples per in_start interval
+ procedure proc_diag_measure_cw_ampl_and_phase(constant c_fft_size : in natural;
constant c_sub : in real;
signal dp_clk : in std_logic;
signal in_dat : in std_logic_vector;
@@ -160,22 +203,34 @@ package tb_diag_pkg is
signal measured_phase_Ts : out real);
-- Use estimated CW to determine noise power in input sine (e.g. WG sine)
- procedure proc_diag_measure_cw_noise_power(constant c_nof_samples : in natural; -- number of samples per integration interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
+ -- number of samples per integration interval
+ procedure proc_diag_measure_cw_noise_power(constant c_nof_samples : in natural;
+ -- number of points of FFT
+ constant c_fft_size : in natural;
+ -- subband index
+ constant c_sub : in real;
signal dp_clk : in std_logic;
signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ -- start of integration interval, e.g. sop or sync
+ signal in_start : in std_logic;
signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal cw_ampl : in real; -- estimated CW amplitude of in_dat
- signal cw_phase : in real; -- estimated CW phase of in_dat
- signal cw_dat : out integer; -- estimated CW
- signal cw_noise : out real; -- estimated CW quantization noise
- signal accum_noise_power : inout real; -- store noise power accumulator in signal
- signal measured_noise_power : out real); -- measured noise power in in_dat
-
- procedure proc_diag_measure_cw_noise_power(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
+ -- sample index in c_fft_size
+ signal in_cnt : in natural;
+ -- estimated CW amplitude of in_dat
+ signal cw_ampl : in real;
+ -- estimated CW phase of in_dat
+ signal cw_phase : in real;
+ -- estimated CW
+ signal cw_dat : out integer;
+ -- estimated CW quantization noise
+ signal cw_noise : out real;
+ -- store noise power accumulator in signal
+ signal accum_noise_power : inout real;
+ -- measured noise power in in_dat
+ signal measured_noise_power : out real);
+
+ -- number of points of FFT = number of samples per in_start interval
+ procedure proc_diag_measure_cw_noise_power(constant c_fft_size : in natural;
constant c_sub : in real;
signal dp_clk : in std_logic;
signal in_dat : in std_logic_vector;
@@ -197,7 +252,8 @@ package body tb_diag_pkg is
signal tx_mosi : out t_mem_mosi;
signal rx_miso : in t_mem_miso;
signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ -- read all MM reg
+ signal rd_reg : out t_diag_seq_mm_reg) is
constant c_tx_offset : natural := c_stream * 2**c_diag_seq_tx_reg_adr_w;
constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
begin
@@ -252,87 +308,111 @@ package body tb_diag_pkg is
end proc_diag_seq_read_all;
procedure proc_diag_seq_tx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
+ -- "PSRG", "CNTR"
+ constant c_pattern : in string;
constant c_tx_init : in natural;
constant c_tx_mod : in natural;
signal mm_clk : in std_logic;
signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
+ -- tx ctrl
+ signal tx_miso : in t_mem_miso;
signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
+ -- rx ctrl
+ signal rx_miso : in t_mem_miso;
signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ -- read all MM reg
+ signal rd_reg : out t_diag_seq_mm_reg) is
constant c_tx_offset : natural := c_stream * 2**c_diag_seq_tx_reg_adr_w;
constant c_en : natural := 1;
variable v_sel : natural;
variable v_ctlr : natural;
begin
if c_pattern = "PSRG" then
- v_sel := 0; -- pseudo random data
+ -- pseudo random data
+ v_sel := 0;
else
- v_sel := 1; -- counter data
+ -- counter data
+ v_sel := 1;
end if;
- v_ctlr := v_sel * 2 + c_en; -- bits [1:0]
+ -- bits [1:0]
+ v_ctlr := v_sel * 2 + c_en;
-- Enable Tx
proc_mem_mm_bus_wr(c_tx_offset + 0, v_ctlr, mm_clk, tx_miso, tx_mosi);
proc_mem_mm_bus_wr(c_tx_offset + 1, c_tx_init, mm_clk, tx_miso, tx_mosi);
proc_mem_mm_bus_wr(c_tx_offset + 3, c_tx_mod, mm_clk, tx_miso, tx_mosi);
- proc_common_wait_some_cycles(mm_clk, dp_clk, 10); -- wait for clock domain crossing
+ -- wait for clock domain crossing
+ proc_common_wait_some_cycles(mm_clk, dp_clk, 10);
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_tx_enable;
procedure proc_diag_seq_rx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
+ -- "PSRG", "CNTR"
+ constant c_pattern : in string;
signal mm_clk : in std_logic;
signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
+ -- tx ctrl
+ signal tx_miso : in t_mem_miso;
signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
+ -- rx ctrl
+ signal rx_miso : in t_mem_miso;
signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ -- read all MM reg
+ signal rd_reg : out t_diag_seq_mm_reg) is
constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
constant c_en : natural := 1;
variable v_sel : natural;
variable v_ctlr : natural;
begin
if c_pattern = "PSRG" then
- v_sel := 0; -- pseudo random data
+ -- pseudo random data
+ v_sel := 0;
else
- v_sel := 1; -- counter data
+ -- counter data
+ v_sel := 1;
end if;
- v_ctlr := v_sel * 2 + c_en; -- bits [1:0]
+ -- bits [1:0]
+ v_ctlr := v_sel * 2 + c_en;
proc_mem_mm_bus_wr(c_rx_offset + 0, v_ctlr, mm_clk, rx_miso, rx_mosi);
- proc_common_wait_some_cycles(mm_clk, dp_clk, 10); -- wait for clock domain crossing
+ -- wait for clock domain crossing
+ proc_common_wait_some_cycles(mm_clk, dp_clk, 10);
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_rx_enable;
procedure proc_diag_seq_tx_disable(constant c_stream : in natural;
signal mm_clk : in std_logic;
signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
+ -- tx ctrl
+ signal tx_miso : in t_mem_miso;
signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
+ -- rx ctrl
+ signal rx_miso : in t_mem_miso;
signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ -- read all MM reg
+ signal rd_reg : out t_diag_seq_mm_reg) is
constant c_tx_offset : natural := c_stream * 2**c_diag_seq_tx_reg_adr_w;
begin
proc_mem_mm_bus_wr(c_tx_offset + 0, 0, mm_clk, tx_miso, tx_mosi);
- proc_common_wait_some_cycles(mm_clk, dp_clk, 10); -- wait for clock domain crossing
+ -- wait for clock domain crossing
+ proc_common_wait_some_cycles(mm_clk, dp_clk, 10);
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_tx_disable;
procedure proc_diag_seq_rx_disable(constant c_stream : in natural;
signal mm_clk : in std_logic;
signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
+ -- tx ctrl
+ signal tx_miso : in t_mem_miso;
signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
+ -- rx ctrl
+ signal rx_miso : in t_mem_miso;
signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ -- read all MM reg
+ signal rd_reg : out t_diag_seq_mm_reg) is
constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
begin
proc_mem_mm_bus_wr(c_rx_offset + 0, 0, mm_clk, rx_miso, rx_mosi);
- proc_common_wait_some_cycles(mm_clk, dp_clk, 10); -- wait for clock domain crossing
+ -- wait for clock domain crossing
+ proc_common_wait_some_cycles(mm_clk, dp_clk, 10);
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_rx_disable;
@@ -340,11 +420,14 @@ package body tb_diag_pkg is
constant c_steps_arr : in t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0);
signal mm_clk : in std_logic;
signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
+ -- tx ctrl
+ signal tx_miso : in t_mem_miso;
signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
+ -- rx ctrl
+ signal rx_miso : in t_mem_miso;
signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ -- read all MM reg
+ signal rd_reg : out t_diag_seq_mm_reg) is
constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
constant c_en : natural := 1;
variable v_sel : natural;
@@ -354,7 +437,8 @@ package body tb_diag_pkg is
for I in 0 to c_diag_seq_rx_reg_nof_steps - 1 loop
proc_mem_mm_bus_wr(c_rx_offset + c_diag_seq_rx_reg_nof_steps_wi + I, c_steps_arr(I), mm_clk, rx_miso, rx_mosi);
end loop;
- proc_common_wait_some_cycles(mm_clk, dp_clk, 10); -- wait for clock domain crossing
+ -- wait for clock domain crossing
+ proc_common_wait_some_cycles(mm_clk, dp_clk, 10);
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_rx_write_steps;
@@ -366,7 +450,8 @@ package body tb_diag_pkg is
signal rx_mosi : out t_mem_mosi;
signal tb_mode : inout t_tb_diag_seq_mode_enum;
signal tb_verify : out std_logic;
- signal rd_reg : inout t_diag_seq_mm_reg) is -- read all MM reg
+ -- read all MM reg
+ signal rd_reg : inout t_diag_seq_mm_reg) is
variable v_rx_stat : std_logic_vector(c_word_w - 1 downto 0);
variable v_rx_sample : std_logic_vector(c_word_w - 1 downto 0);
variable v_rx_cnt : natural;
@@ -459,20 +544,31 @@ package body tb_diag_pkg is
-- measure DC.
-- . accumulate samples during interval and calculate effective amplitude.
---------------------------------------------------------------------------
- procedure proc_diag_measure_cw_statistics(constant c_nof_samples : in natural; -- number of samples per in_start interval
+ -- number of samples per in_start interval
+ procedure proc_diag_measure_cw_statistics(constant c_nof_samples : in natural;
signal dp_clk : in std_logic;
signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of interval, e.g. sop or sync
+ -- start of interval, e.g. sop or sync
+ signal in_start : in std_logic;
signal in_val : in std_logic;
- signal track_max : inout real; -- store local tracker in signal
- signal track_min : inout real; -- store local tracker in signal
- signal accum_mean : inout real; -- store local accumulator in signal
- signal accum_power : inout real; -- store local accumulator in signal
- signal measured_max : out real; -- maximum sample value
- signal measured_min : out real; -- minimum sample value
- signal measured_mean : out real; -- average sample value (DC)
- signal measured_power : out real; -- average sample power
- signal measured_ampl : out real) is -- corresponding sine amplitude
+ -- store local tracker in signal
+ signal track_max : inout real;
+ -- store local tracker in signal
+ signal track_min : inout real;
+ -- store local accumulator in signal
+ signal accum_mean : inout real;
+ -- store local accumulator in signal
+ signal accum_power : inout real;
+ -- maximum sample value
+ signal measured_max : out real;
+ -- minimum sample value
+ signal measured_min : out real;
+ -- average sample value (DC)
+ signal measured_mean : out real;
+ -- average sample power
+ signal measured_power : out real;
+ -- corresponding sine amplitude
+ signal measured_ampl : out real) is
constant c_Nsamples : real := real(c_nof_samples);
constant c_dat : real := real(TO_SINT(in_dat));
constant c_mean : real := accum_mean / c_Nsamples;
@@ -490,7 +586,8 @@ package body tb_diag_pkg is
track_max <= real'low;
track_min <= real'high;
accum_mean <= c_dat;
- accum_power <= (abs(c_dat))**2.0; -- Must use ABS() with ** of real, because (negative)**2.0 yields error and value 0.0, also must use brackets (ABS()) to avoid compile error
+ -- Must use ABS() with ** of real, because (negative)**2.0 yields error and value 0.0, also must use brackets (ABS()) to avoid compile error
+ accum_power <= (abs(c_dat))**2.0;
elsif in_val = '1' then
-- Detect and accumulate during interval
track_max <= largest(track_max, c_dat);
@@ -539,29 +636,45 @@ package body tb_diag_pkg is
-- . the sine power of the perfect reference CW (carrier wave) is:
-- cwPower = (A**2)/2
---------------------------------------------------------------------------
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_nof_samples : in natural; -- number of samples per in_start interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
+ -- number of samples per in_start interval
+ procedure proc_diag_measure_cw_ampl_and_phase(constant c_nof_samples : in natural;
+ -- number of points of FFT
+ constant c_fft_size : in natural;
+ -- subband index
+ constant c_sub : in real;
signal dp_clk : in std_logic;
signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ -- start of integration interval, e.g. sop or sync
+ signal in_start : in std_logic;
signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal ref_I : out real; -- output local I as signal for debugging in wave window
- signal ref_Q : out real; -- output local Q as signal for debugging in wave window
- signal accum_I : inout real; -- store local I accumulator in signal
- signal accum_Q : inout real; -- store local Q accumulator in signal
- signal measured_ampl : out real; -- measured CW amplitude
- signal measured_phase : out real; -- measured CW phase in radials
- signal measured_phase_Ts : out real) is -- measured CW phase in sample periods
+ -- sample index in c_fft_size
+ signal in_cnt : in natural;
+ -- output local I as signal for debugging in wave window
+ signal ref_I : out real;
+ -- output local Q as signal for debugging in wave window
+ signal ref_Q : out real;
+ -- store local I accumulator in signal
+ signal accum_I : inout real;
+ -- store local Q accumulator in signal
+ signal accum_Q : inout real;
+ -- measured CW amplitude
+ signal measured_ampl : out real;
+ -- measured CW phase in radials
+ signal measured_phase : out real;
+ -- measured CW phase in sample periods
+ signal measured_phase_Ts : out real) is
constant c_Nsamples : real := real(c_nof_samples);
constant c_Nfft : real := real(c_fft_size);
constant c_omega : real := MATH_2_PI * c_sub / c_Nfft;
- constant c_lat : real := 1.0 * c_omega; -- the I and Q start when in_val='1', this introduces 1 dp_clk latency, so adjust phase of ref_I and ref_Q to compensate
+ -- the I and Q start when in_val='1', this introduces 1 dp_clk latency, so adjust phase of ref_I and ref_Q to compensate
+ constant c_lat : real := 1.0 * c_omega;
constant c_k : real := real(in_cnt);
- constant c_angle : real := (c_k * c_omega + c_lat) mod MATH_2_PI; -- keep angle in SIN(), COS() within 2pi to avoid "Error: XLOCAL <= 0.0 after reduction in COS(X)"
- constant c_I : real := SIN(c_angle); -- I = in phase reference
- constant c_Q : real := COS(c_angle); -- Q = quadrature reference
+ -- keep angle in SIN(), COS() within 2pi to avoid "Error: XLOCAL <= 0.0 after reduction in COS(X)"
+ constant c_angle : real := (c_k * c_omega + c_lat) mod MATH_2_PI;
+ -- I = in phase reference
+ constant c_I : real := SIN(c_angle);
+ -- Q = quadrature reference
+ constant c_Q : real := COS(c_angle);
constant c_dat : real := real(TO_SINT(in_dat));
constant c_phase : real := ARCTAN(accum_Q, accum_I + c_eps);
constant c_ampl : real := COMPLEX_RADIUS(accum_I, accum_Q) * 2.0 / c_Nsamples;
@@ -588,7 +701,8 @@ package body tb_diag_pkg is
end if;
end proc_diag_measure_cw_ampl_and_phase;
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
+ -- number of points of FFT = number of samples per in_start interval
+ procedure proc_diag_measure_cw_ampl_and_phase(constant c_fft_size : in natural;
constant c_sub : in real;
signal dp_clk : in std_logic;
signal in_dat : in std_logic_vector;
@@ -629,27 +743,40 @@ package body tb_diag_pkg is
--
-- SNR = 10*log10(cwPower / noisePower) [dB]
---------------------------------------------------------------------------
- procedure proc_diag_measure_cw_noise_power(constant c_nof_samples : in natural; -- number of samples per integration interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
+ -- number of samples per integration interval
+ procedure proc_diag_measure_cw_noise_power(constant c_nof_samples : in natural;
+ -- number of points of FFT
+ constant c_fft_size : in natural;
+ -- subband index
+ constant c_sub : in real;
signal dp_clk : in std_logic;
signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ -- start of integration interval, e.g. sop or sync
+ signal in_start : in std_logic;
signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal cw_ampl : in real; -- estimated CW amplitude of in_dat
- signal cw_phase : in real; -- estimated CW phase of in_dat
- signal cw_dat : out integer; -- estimated CW
- signal cw_noise : out real; -- estimated CW quantization noise
- signal accum_noise_power : inout real; -- store noise power accumulator in signal
- signal measured_noise_power : out real) is -- measured noise power in in_dat
+ -- sample index in c_fft_size
+ signal in_cnt : in natural;
+ -- estimated CW amplitude of in_dat
+ signal cw_ampl : in real;
+ -- estimated CW phase of in_dat
+ signal cw_phase : in real;
+ -- estimated CW
+ signal cw_dat : out integer;
+ -- estimated CW quantization noise
+ signal cw_noise : out real;
+ -- store noise power accumulator in signal
+ signal accum_noise_power : inout real;
+ -- measured noise power in in_dat
+ signal measured_noise_power : out real) is
constant c_Nsamples : real := real(c_nof_samples);
constant c_Nfft : real := real(c_fft_size);
constant c_omega : real := MATH_2_PI * c_sub / c_Nfft;
- constant c_lat : real := 1.0 * c_omega; -- adjust phase of c_cw to compensate for measurement latency
+ -- adjust phase of c_cw to compensate for measurement latency
+ constant c_lat : real := 1.0 * c_omega;
constant c_k : real := real(in_cnt);
constant c_dat : real := real(TO_SINT(in_dat));
- constant c_angle : real := (c_k * c_omega + cw_phase + c_lat) mod MATH_2_PI; -- keep angle in SIN(), COS() within 2pi to avoid "Error: XLOCAL <= 0.0 after reduction in COS(X)"
+ -- keep angle in SIN(), COS() within 2pi to avoid "Error: XLOCAL <= 0.0 after reduction in COS(X)"
+ constant c_angle : real := (c_k * c_omega + cw_phase + c_lat) mod MATH_2_PI;
constant c_cw : real := cw_ampl * SIN(c_angle);
constant c_noise : real := c_cw - c_dat;
constant c_noise_power : real := (abs(c_noise))**2.0;
@@ -671,7 +798,8 @@ package body tb_diag_pkg is
end if;
end proc_diag_measure_cw_noise_power;
- procedure proc_diag_measure_cw_noise_power(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
+ -- number of points of FFT = number of samples per in_start interval
+ procedure proc_diag_measure_cw_noise_power(constant c_fft_size : in natural;
constant c_sub : in real;
signal dp_clk : in std_logic;
signal in_dat : in std_logic_vector;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
index 35316f212a397ab0d11e1ec96573a1e7135f494a..452202662d8a60da8e55838853d11626848f1383 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
@@ -43,7 +43,8 @@ entity tb_diag_rx_seq is
g_tx_mod : integer := 0;
g_rx_use_steps : boolean := true;
g_rx_steps_arr : t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0) := (1, 0, -7, 3);
- g_seq_dat_w : natural := 16 -- = 12b for Lofar RCU test data, 16b for Lofar TBBI test data
+ -- = 12b for Lofar RCU test data, 16b for Lofar TBBI test data
+ g_seq_dat_w : natural := 16
);
end tb_diag_rx_seq;
@@ -99,29 +100,37 @@ begin
wait for c_period;
tx_diag_en <= '1';
wait for 10 * c_period;
- rx_diag_en <= '1'; -- restart diag_res
+ -- restart diag_res
+ rx_diag_en <= '1';
wait for c_nof_cycles * c_period;
- tx_diag_req <= '0'; -- inactive request cycle
+ -- inactive request cycle
+ tx_diag_req <= '0';
wait for c_period;
tx_diag_req <= '1';
wait for c_nof_cycles * c_period;
- rx_diag_en <= '0'; -- stop diag_res
+ -- stop diag_res
+ rx_diag_en <= '0';
wait for 10 * c_period;
- rx_diag_en <= '1'; -- restart diag_res
+ -- restart diag_res
+ rx_diag_en <= '1';
wait for c_nof_cycles * c_period;
- tx_diag_req <= '0'; -- inactive request cycles
+ -- inactive request cycles
+ tx_diag_req <= '0';
wait for 1 * c_period;
tx_diag_req <= '1';
wait for 2 * c_period;
- tx_diag_req <= '0'; -- inactive request cycles
+ -- inactive request cycles
+ tx_diag_req <= '0';
wait for 3 * c_period;
tx_diag_req <= '1';
wait for 4 * c_period;
- tx_diag_req <= '0'; -- inactive request cycles
+ -- inactive request cycles
+ tx_diag_req <= '0';
wait for 5 * c_period;
tx_diag_req <= '1';
wait for c_nof_cycles * c_period;
- rx_diag_en <= '0'; -- stop diag_res
+ -- stop diag_res
+ rx_diag_en <= '0';
wait for c_latency * c_period;
-- PRSG
@@ -132,59 +141,77 @@ begin
wait for c_period;
tx_diag_en <= '1';
wait for 10 * c_period;
- rx_diag_en <= '1'; -- restart diag_res
+ -- restart diag_res
+ rx_diag_en <= '1';
wait for c_nof_cycles * c_period;
- rx_diag_en <= '0'; -- stop diag_res
+ -- stop diag_res
+ rx_diag_en <= '0';
wait for c_latency * c_period;
-- COUNTER
wait for c_latency * c_period;
expected_res <= sel_a_b(g_rx_use_steps, c_diag_res_ok, c_diag_res_ok);
- tx_diag_en <= '0'; -- stop tx
+ -- stop tx
+ tx_diag_en <= '0';
wait for c_period;
tx_diag_sel <= '1';
rx_diag_sel <= '1';
- wait for 10 * c_period; -- wait until no more valid data arrives from tx
- rx_diag_en <= '1'; -- restart diag_res before tx is on
+ -- wait until no more valid data arrives from tx
+ wait for 10 * c_period;
+ -- restart diag_res before tx is on
+ rx_diag_en <= '1';
wait for 10 * c_period;
- tx_diag_en <= '1'; -- restart tx
+ -- restart tx
+ tx_diag_en <= '1';
wait for c_nof_cycles * c_period;
- tx_diag_req <= '0'; -- inactive request cycle
+ -- inactive request cycle
+ tx_diag_req <= '0';
wait for c_period;
tx_diag_req <= '1';
wait for c_nof_cycles * c_period;
- rx_diag_en <= '0'; -- stop diag_res
+ -- stop diag_res
+ rx_diag_en <= '0';
wait for c_latency * c_period;
-- COUNTER
expected_res <= sel_a_b(g_rx_use_steps, c_diag_res_ok, c_diag_res_ok);
- tx_diag_en <= '0'; -- stop tx
- tx_diag_req <= '0'; -- inactive tx request
+ -- stop tx
+ tx_diag_en <= '0';
+ -- inactive tx request
+ tx_diag_req <= '0';
wait for c_period;
tx_diag_sel <= '1';
rx_diag_sel <= '1';
- wait for 10 * c_period; -- wait until no more valid data arrives from tx
- rx_diag_en <= '1'; -- restart diag_res before tx is on
+ -- wait until no more valid data arrives from tx
+ wait for 10 * c_period;
+ -- restart diag_res before tx is on
+ rx_diag_en <= '1';
wait for 10 * c_period;
- tx_diag_en <= '1'; -- restart tx
- tx_diag_req <= '0'; -- inactive request cycle
+ -- restart tx
+ tx_diag_en <= '1';
+ -- inactive request cycle
+ tx_diag_req <= '0';
wait for c_period;
tx_diag_req <= '1';
wait for c_period;
- tx_diag_req <= '0'; -- inactive request cycles
+ -- inactive request cycles
+ tx_diag_req <= '0';
wait for 4 * c_period;
tx_diag_req <= '1';
wait for c_period;
- tx_diag_req <= '0'; -- inactive request cycles
+ -- inactive request cycles
+ tx_diag_req <= '0';
wait for 4 * c_period;
tx_diag_req <= '1';
wait for c_period;
- tx_diag_req <= '0'; -- inactive request cycles
+ -- inactive request cycles
+ tx_diag_req <= '0';
wait for 4 * c_period;
tx_diag_req <= '1';
wait for c_period;
wait for c_nof_cycles * c_period;
- rx_diag_en <= '0'; -- stop diag_res
+ -- stop diag_res
+ rx_diag_en <= '0';
wait for c_latency * c_period;
-- PRSG
@@ -195,12 +222,15 @@ begin
wait for c_period;
tx_diag_en <= '1';
wait for 10 * c_period;
- rx_diag_en <= '1'; -- restart diag_res
+ -- restart diag_res
+ rx_diag_en <= '1';
wait for c_nof_cycles * c_period;
wait for c_period;
- tx_diag_en <= '0'; -- stop tx
+ -- stop tx
+ tx_diag_en <= '0';
wait for c_nof_cycles * c_period;
- rx_diag_en <= '0'; -- stop diag_res
+ -- stop diag_res
+ rx_diag_en <= '0';
wait for c_latency * c_period;
-- PRSG
@@ -210,23 +240,32 @@ begin
rx_diag_sel <= '0';
tx_diag_en <= '1';
wait for 10 * c_period;
- rx_diag_en <= '1'; -- restart diag_res
+ -- restart diag_res
+ rx_diag_en <= '1';
wait for c_nof_cycles * c_period;
- rx_diag_en <= '0'; -- stop diag_res
+ -- stop diag_res
+ rx_diag_en <= '0';
wait for 1 * c_period;
- rx_diag_en <= '1'; -- fast restart diag_res
+ -- fast restart diag_res
+ rx_diag_en <= '1';
wait for c_nof_cycles * c_period;
- rx_diag_en <= '0'; -- stop diag_res
+ -- stop diag_res
+ rx_diag_en <= '0';
wait for 10 * c_period;
- rx_diag_en <= '1'; -- slow restart diag_res
+ -- slow restart diag_res
+ rx_diag_en <= '1';
wait for c_nof_cycles * c_period;
- rx_diag_en <= '0'; -- stop diag_res
+ -- stop diag_res
+ rx_diag_en <= '0';
wait for 10 * c_period;
- rx_diag_en <= '1'; -- slow restart diag_res
+ -- slow restart diag_res
+ rx_diag_en <= '1';
wait for c_nof_cycles * c_period;
- tx_diag_en <= '0'; -- stop tx
+ -- stop tx
+ tx_diag_en <= '0';
wait for c_nof_cycles * c_period;
- rx_diag_en <= '0'; -- stop diag_res
+ -- stop diag_res
+ rx_diag_en <= '0';
wait for c_latency * c_period;
-- COUNTER
@@ -237,14 +276,19 @@ begin
wait for c_period;
tx_diag_en <= '1';
wait for 10 * c_period;
- rx_diag_en <= '1'; -- restart diag_res
+ -- restart diag_res
+ rx_diag_en <= '1';
wait for c_nof_cycles * c_period;
--tx_diag_sel <= '0'; -- uncomment this line to force errors by using a different tx sequence
- wait for 5 * c_period; -- for multiple cycles to show that all bits get in error state
+ -- for multiple cycles to show that all bits get in error state
+ wait for 5 * c_period;
tx_diag_sel <= '1';
- wait for c_nof_cycles * c_period; -- some more cylces to show that the diag_res error state is preserved
- tx_diag_en <= '0'; -- stop tx
- rx_diag_en <= '0'; -- stop diag_res
+ -- some more cylces to show that the diag_res error state is preserved
+ wait for c_nof_cycles * c_period;
+ -- stop tx
+ tx_diag_en <= '0';
+ -- stop diag_res
+ rx_diag_en <= '0';
wait for c_latency * c_period;
wait for c_nof_cycles * c_period;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd b/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
index d526a763f07a372d583673d579eb1e007570c098..c00d2dfd73690c561ba98642a082b7e1c3b7927f 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
@@ -30,11 +30,15 @@ end tb_diag_tx_frm;
architecture tb of tb_diag_tx_frm is
constant c_period : time := 100 ns;
- constant c_nof_cycles : natural := 83; -- use prime number to avoid periodicity with sequence data, which can confuse interpretating the data
-
- constant c_sel : std_logic := '1'; -- select COUNTER sequence
- constant c_init : natural := 2; -- test sequence init value
- constant c_frame_len : natural := 20; -- >= 2, test frame length
+ -- use prime number to avoid periodicity with sequence data, which can confuse interpretating the data
+ constant c_nof_cycles : natural := 83;
+
+ -- select COUNTER sequence
+ constant c_sel : std_logic := '1';
+ -- test sequence init value
+ constant c_init : natural := 2;
+ -- >= 2, test frame length
+ constant c_frame_len : natural := 20;
constant c_frame_len_w : natural := ceil_log2(c_frame_len);
constant c_dat_w : natural := c_frame_len_w;
@@ -69,7 +73,8 @@ begin
-- Keep seq_req='1'
seq_req <= '1';
wait for c_period;
- diag_sop <= '1'; -- Generate one frame
+ -- Generate one frame
+ diag_sop <= '1';
wait for c_period;
diag_sop <= '0';
wait for c_nof_cycles * c_period;
@@ -79,7 +84,8 @@ begin
seq_req <= '1';
diag_init <= TO_UVEC(0, c_dat_w);
wait for 10 * c_period;
- diag_sop <= '1'; -- Generate one frame with actual c_init only during diag_sop
+ -- Generate one frame with actual c_init only during diag_sop
+ diag_sop <= '1';
diag_init <= TO_UVEC(c_init, c_dat_w);
wait for c_period;
diag_sop <= '0';
@@ -90,7 +96,8 @@ begin
-- Keep diag_sop='1' to immediately request a next frame again
seq_req <= '1';
- diag_sop <= '1'; -- Immediatly generate a frame when generator indicates ready
+ -- Immediatly generate a frame when generator indicates ready
+ diag_sop <= '1';
for I in 0 to 3 * c_frame_len loop
wait for c_period;
end loop;
@@ -101,7 +108,8 @@ begin
-- Use diag_ready to immediately request a next frame again
seq_req <= '1';
for I in 0 to 3 * c_frame_len loop
- diag_sop <= diag_ready; -- Immediatly generate a frame when generator indicates ready
+ -- Immediatly generate a frame when generator indicates ready
+ diag_sop <= diag_ready;
wait for c_period;
end loop;
diag_sop <= '0';
@@ -111,11 +119,13 @@ begin
-- Toggle seq_req='1'
seq_req <= '1';
wait for c_period;
- diag_sop <= '1'; -- Generate one frame
+ -- Generate one frame
+ diag_sop <= '1';
wait for c_period;
diag_sop <= '0';
wait for 10 * c_period;
- seq_req <= '0'; -- One inactive request cycle
+ -- One inactive request cycle
+ seq_req <= '0';
wait for c_period;
seq_req <= '1';
wait for c_nof_cycles * c_period;
@@ -124,11 +134,13 @@ begin
-- Make seq_req='0' near end of frame
seq_req <= '1';
wait for c_period;
- diag_sop <= '1'; -- Generate one frame
+ -- Generate one frame
+ diag_sop <= '1';
wait for c_period;
diag_sop <= '0';
wait for (c_frame_len - 1) * c_period;
- seq_req <= '0'; -- Some inactive request cycles
+ -- Some inactive request cycles
+ seq_req <= '0';
wait for 5 * c_period;
seq_req <= '1';
wait for c_nof_cycles * c_period;
@@ -137,11 +149,13 @@ begin
-- Keep diag_sop='1' and make seq_req='0' near end of frame
seq_req <= '1';
wait for c_period;
- diag_sop <= '1'; -- Generate one frame
+ -- Generate one frame
+ diag_sop <= '1';
wait for c_period;
diag_sop <= '1';
wait for (c_frame_len - 1) * c_period;
- seq_req <= '0'; -- Some inactive request cycles
+ -- Some inactive request cycles
+ seq_req <= '0';
wait for 5 * c_period;
seq_req <= '1';
wait for 5 * c_period;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
index a172bb172d22a2ec0f08150157428394181ee8a2..61cb8cafedc3f9b9a8202701073f3314d3a23a9b 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
@@ -35,7 +35,8 @@ end tb_diag_tx_seq;
architecture tb of tb_diag_tx_seq is
constant c_period : time := 100 ns;
- constant c_nof_cycles : natural := 83; -- use prime number to avoid periodicity with sequence data, which can confuse interpretating the data
+ -- use prime number to avoid periodicity with sequence data, which can confuse interpretating the data
+ constant c_nof_cycles : natural := 83;
constant c_dat_w : natural := 4;
@@ -74,17 +75,20 @@ begin
-- COUNTER
diag_sel <= '1';
wait for c_nof_cycles * c_period;
- diag_en <= '0'; -- let diag_en go low for 1 clk to restart the sequence
+ -- let diag_en go low for 1 clk to restart the sequence
+ diag_en <= '0';
wait for c_period;
diag_en <= '1';
wait for c_nof_cycles * c_period;
diag_en <= '0';
- wait for c_period; -- let diag_en go low for > 1 clk to restart the sequence
+ -- let diag_en go low for > 1 clk to restart the sequence
+ wait for c_period;
wait for c_period;
diag_en <= '1';
wait for c_nof_cycles * c_period;
diag_en <= '0';
- wait for c_period; -- let diag_en go low for > 1 clk to restart the sequence
+ -- let diag_en go low for > 1 clk to restart the sequence
+ wait for c_period;
wait for c_period;
wait for c_period;
diag_en <= '1';
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
index db0f7c42fe152b2ed7565cf2c64ee70674aa00b7..0c042b4cff9fb06861515e90950b492f027b7f56 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
@@ -38,41 +38,53 @@ use work.diag_pkg.all;
entity tb_diag_wg is
generic (
- g_buf_adr_w : natural := 10; -- Waveform buffer address width (requires corresponding c_buf_file)
- g_buf_dat_w : natural := 8; -- Waveform buffer stored data width (requires corresponding c_buf_file)
- g_wg_dat_w : natural := 8 -- Effective waveform sample output width must be <= g_buf_dat_w
+ -- Waveform buffer address width (requires corresponding c_buf_file)
+ g_buf_adr_w : natural := 10;
+ -- Waveform buffer stored data width (requires corresponding c_buf_file)
+ g_buf_dat_w : natural := 8;
+ -- Effective waveform sample output width must be <= g_buf_dat_w
+ g_wg_dat_w : natural := 8
);
end tb_diag_wg;
architecture tb of tb_diag_wg is
- constant c_clk_freq : natural := 200 * 10**6; -- Hz
+ -- Hz
+ constant c_clk_freq : natural := 200 * 10**6;
constant c_clk_period : time := (10**9 / c_clk_freq) * 1 ns;
-- Default settings
constant c_buf : t_c_mem := (latency => 1,
adr_w => g_buf_adr_w,
- dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
- nof_dat => 2**g_buf_adr_w, -- = 2**adr_w
+ -- fit DSP multiply 18x18 element
+ dat_w => g_buf_dat_w,
+ -- = 2**adr_w
+ nof_dat => 2**g_buf_adr_w,
init_sl => '0');
constant c_buf_file : string := sel_a_b(c_buf.adr_w = 11 and c_buf.dat_w = 18, "data/diag_sin_2048x18.hex",
sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, "data/diag_sin_1024x18.hex",
sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 8, "data/diag_sin_1024x8.hex", "UNUSED")));
- constant c_wg_nof_samples : natural := c_buf.nof_dat; -- must be <= c_buf.nof_dat
- constant c_wg_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
+ -- must be <= c_buf.nof_dat
+ constant c_wg_nof_samples : natural := c_buf.nof_dat;
+ -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
+ constant c_wg_gain_w : natural := 1;
-- . use gain 2**0 = 1 to have fulle scale without clipping
-- . use gain 2**g_calc_gain_w > 1 to cause clipping
- constant c_buf_full_scale : natural := 2**(g_buf_dat_w - 1) - 1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
+ -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
+ constant c_buf_full_scale : natural := 2**(g_buf_dat_w - 1) - 1;
constant c_wg_full_scale : natural := 2**(g_wg_dat_w - 1) - 1;
constant c_ampl_norm : real := sel_a_b(g_wg_dat_w < g_buf_dat_w, real(c_wg_full_scale) / real(c_wg_full_scale+1), 1.0);
--CONSTANT c_ampl_norm : REAL := REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1); -- Use this if g_wg_dat_w < g_buf_dat_w, to avoid clipping
--CONSTANT c_ampl_norm : REAL := 1.0; -- Use this if g_wg_dat_w = g_buf_dat_w, because the stored waveform range is already -+c_buf_full_scale
--CONSTANT c_ampl_norm : REAL := REAL(c_buf_full_scale)/REAL(c_buf_full_scale+1); -- No need to use this, because the stored waveform range is already -+c_buf_full_scale
- constant c_freq_unit : real := c_diag_wg_freq_unit; -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
- constant c_ampl_unit : real := c_diag_wg_ampl_unit * c_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
- constant c_phase_unit : real := c_diag_wg_phase_unit; -- ^= 1 degree
+ -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
+ constant c_freq_unit : real := c_diag_wg_freq_unit;
+ -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
+ constant c_ampl_unit : real := c_diag_wg_ampl_unit * c_ampl_norm;
+ -- ^= 1 degree
+ constant c_phase_unit : real := c_diag_wg_phase_unit;
signal tb_end : std_logic;
signal rst : std_logic;
@@ -137,11 +149,13 @@ begin
-- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
-- wg_phase <= INTEGER(0.0 * c_phase_unit);
- wg_ampl <= integer(1.0 * c_ampl_unit); -- yields amplitude of c_wg_full_scale
+ -- yields amplitude of c_wg_full_scale
+ wg_ampl <= integer(1.0 * c_ampl_unit);
-- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
-- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
- wait until rising_edge(clk); -- align to rising edge
+ -- align to rising edge
+ wait until rising_edge(clk);
wait for c_clk_period * 200;
---------------------------------------------------------------------------
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
index 8521629f7d0dbcaf8913ce9dbdb4c9504dd19d68..212d85801f3784da9fcacb37c980081cc8bb4d18 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
@@ -38,7 +38,8 @@ use work.diag_pkg.all;
entity tb_diag_wg_wideband is
generic (
-- Wideband parameters
- g_wideband_factor : natural := 4; -- Wideband rate factor >= 1 for unit frequency of g_wideband_factor * Fs
+ -- Wideband rate factor >= 1 for unit frequency of g_wideband_factor * Fs
+ g_wideband_factor : natural := 4;
-- Take care that the g_wideband_factor and c_clk_freq match the simulation time resolution of integer 1 ps
-- Basic WG parameters, see diag_wg.vhd for their meaning
g_buf_addr_w : natural := 10;
@@ -48,26 +49,32 @@ entity tb_diag_wg_wideband is
end tb_diag_wg_wideband;
architecture tb of tb_diag_wg_wideband is
- constant c_clk_freq : natural := 200; -- MHz
+ -- MHz
+ constant c_clk_freq : natural := 200;
constant c_clk_period : time := (10**6 / c_clk_freq) * 1 ps;
-- Default WG settings
constant c_buf_nof_dat : natural := 2**g_buf_addr_w;
- constant c_wg_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
+ -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
+ constant c_wg_gain_w : natural := 1;
-- . use gain 2**0 = 1 to have fulle scale without clipping
-- . use gain 2**g_calc_gain_w > 1 to cause clipping
- constant c_buf_full_scale : natural := 2**(g_buf_dat_w - 1) - 1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
+ -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
+ constant c_buf_full_scale : natural := 2**(g_buf_dat_w - 1) - 1;
constant c_wg_full_scale : natural := 2**(g_wg_dat_w - 1) - 1;
constant c_ampl_norm : real := sel_a_b(g_wg_dat_w < g_buf_dat_w, real(c_wg_full_scale) / real(c_wg_full_scale+1), 1.0);
--CONSTANT c_ampl_norm : REAL := REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1); -- Use this if g_wg_dat_w < g_buf_dat_w, to avoid clipping
--CONSTANT c_ampl_norm : REAL := 1.0; -- Use this if g_wg_dat_w = g_buf_dat_w, because the stored waveform range is already -+c_buf_full_scale
--CONSTANT c_ampl_norm : REAL := REAL(c_buf_full_scale)/REAL(c_buf_full_scale+1); -- No need to use this, because the stored waveform range is already -+c_buf_full_scale
- constant c_freq_unit : real := c_diag_wg_freq_unit; -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
- constant c_ampl_unit : real := c_diag_wg_ampl_unit * c_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
- constant c_phase_unit : real := c_diag_wg_phase_unit; -- ^= 1 degree
+ -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
+ constant c_freq_unit : real := c_diag_wg_freq_unit;
+ -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
+ constant c_ampl_unit : real := c_diag_wg_ampl_unit * c_ampl_norm;
+ -- ^= 1 degree
+ constant c_phase_unit : real := c_diag_wg_phase_unit;
-- Wideband WG settings
constant c_sample_period : time := (10**6 / (c_clk_freq * g_wideband_factor)) * 1 ps;
@@ -126,7 +133,8 @@ begin
---------------------------------------------------------------------------
-- >>> Single, repeat mode
- wg_nof_samples <= c_buf_nof_dat; -- must be <= c_buf_nof_dat
+ -- must be <= c_buf_nof_dat
+ wg_nof_samples <= c_buf_nof_dat;
-- >>> CALC mode
-- Cosinus with frequency Fs/2 (note sinus Fs/2 yields DC = 0)
@@ -149,11 +157,13 @@ begin
-- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
-- wg_phase <= INTEGER(0.0 * c_phase_unit);
- wg_ampl <= integer(1.0 * c_ampl_unit); -- yields amplitude of c_wg_full_scale
+ -- yields amplitude of c_wg_full_scale
+ wg_ampl <= integer(1.0 * c_ampl_unit);
-- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
-- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
- wait until rising_edge(clk); -- align to rising edge
+ -- align to rising edge
+ wait until rising_edge(clk);
cur_ctrl <= wg_ctrl;
wait for c_clk_period * 200;
@@ -173,7 +183,8 @@ begin
wait for c_clk_period * 3000;
- wg_ampl <= integer(0.5 * c_ampl_unit); -- change ampl immediately
+ -- change ampl immediately
+ wg_ampl <= integer(0.5 * c_ampl_unit);
wait for c_clk_period * 1;
cur_ctrl <= wg_ctrl;
wait for c_clk_period * 10;
@@ -181,8 +192,10 @@ begin
wait for c_clk_period * 3000;
- wg_phase <= integer(90.0 * c_phase_unit); -- no change phase without restart
- wg_freq <= integer(0.5 / 512.0 * c_freq_unit); -- no change freq without restart
+ -- no change phase without restart
+ wg_phase <= integer(90.0 * c_phase_unit);
+ -- no change freq without restart
+ wg_freq <= integer(0.5 / 512.0 * c_freq_unit);
wait for c_clk_period * 10;
assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected hold CALC phase and freq)" severity ERROR;
@@ -200,7 +213,8 @@ begin
-- OFF mode
wg_mode <= c_diag_wg_mode_off;
wait for c_clk_period * 1;
- cur_ctrl <= wg_ctrl; -- OFF mode takes effect immediately
+ -- OFF mode takes effect immediately
+ cur_ctrl <= wg_ctrl;
wait for c_clk_period * 10;
assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected immediately OFF)" severity ERROR;
restart <= '1';
@@ -244,7 +258,8 @@ begin
-- OFF mode
wg_mode <= c_diag_wg_mode_off;
wait for c_clk_period * 1;
- cur_ctrl <= wg_ctrl; -- OFF mode takes effect immediately, no need for restart
+ -- OFF mode takes effect immediately, no need for restart
+ cur_ctrl <= wg_ctrl;
wait for c_clk_period * 10;
assert mon_ctrl = cur_ctrl report "Wrong mon_ctrl (expected immediately OFF)" severity ERROR;
restart <= '1';
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
index f18f50f775d9317d6b96af634b670d2b0abf2c81..cd7558d257f29e85ef587084b955ffd5ef4d842a 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
@@ -46,7 +46,8 @@ entity tb_mms_diag_block_gen is
g_use_tx_seq : boolean := true;
g_use_bg_buffer_ram : boolean := false;
g_usr_bypass_xonoff : boolean := false;
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, or random flow control
+ -- always active, or random flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
g_nof_repeat : natural := 5;
g_nof_streams : natural := 1;
g_gap_size : natural := 0
@@ -78,10 +79,12 @@ architecture tb of tb_mms_diag_block_gen is
constant c_off_period : natural := 10 * c_period_size;
constant c_end_period : natural := 10 * c_period_size;
- constant c_usr_fifo_size : natural := 2 * g_nof_repeat * c_on_period; -- choose user input FIFO in tb sufficiently large to not overflow before tb_end
+ -- choose user input FIFO in tb sufficiently large to not overflow before tb_end
+ constant c_usr_fifo_size : natural := 2 * g_nof_repeat * c_on_period;
constant c_bsn_max : unsigned(c_dp_stream_bsn_w - 1 downto 0) := (others => '1');
- constant c_bsn_gap : unsigned(c_dp_stream_bsn_w - 1 downto 0) := to_unsigned(ceil_div(c_off_period, c_period_size), c_dp_stream_bsn_w); -- depends on c_off_period
+ -- depends on c_off_period
+ constant c_bsn_gap : unsigned(c_dp_stream_bsn_w - 1 downto 0) := to_unsigned(ceil_div(c_off_period, c_period_size), c_dp_stream_bsn_w);
constant c_tx_seq_init : natural := 10;
@@ -134,77 +137,110 @@ begin
begin
bg_en <= '0';
en_sync <= '0';
- out_siso_xon <= '1'; -- Flow control XON
+ -- Flow control XON
+ out_siso_xon <= '1';
if c_verify_usr_rflow = true then
tb_state <= s_user;
- proc_common_wait_some_cycles(clk, c_on_period); -- On time
+ -- On time
+ proc_common_wait_some_cycles(clk, c_on_period);
else
-- BG init
tb_state <= s_init;
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
- proc_mem_mm_bus_wr(1, c_block_size, clk, reg_bg_ctrl_mosi); -- Set the nof samples per block
- proc_mem_mm_bus_wr(2, c_sync_period, clk, reg_bg_ctrl_mosi); -- Set the nof blocks per sync
- proc_mem_mm_bus_wr(3, g_gap_size, clk, reg_bg_ctrl_mosi); -- Set the gapsize
- proc_mem_mm_bus_wr(4, c_mem_lo_addr, clk, reg_bg_ctrl_mosi); -- Set the mem low address
- proc_mem_mm_bus_wr(5, c_mem_hi_addr, clk, reg_bg_ctrl_mosi); -- Set the mem high address
- proc_mem_mm_bus_wr(6, c_bsn_offset, clk, reg_bg_ctrl_mosi); -- Set the lower part of the initial bsn
- proc_mem_mm_bus_wr(7, 0, clk, reg_bg_ctrl_mosi); -- Set the higher part of the initial bsn
+ -- Wait until reset has finished
+ proc_common_wait_until_low(clk, rst);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(clk, 10);
+ -- Set the nof samples per block
+ proc_mem_mm_bus_wr(1, c_block_size, clk, reg_bg_ctrl_mosi);
+ -- Set the nof blocks per sync
+ proc_mem_mm_bus_wr(2, c_sync_period, clk, reg_bg_ctrl_mosi);
+ -- Set the gapsize
+ proc_mem_mm_bus_wr(3, g_gap_size, clk, reg_bg_ctrl_mosi);
+ -- Set the mem low address
+ proc_mem_mm_bus_wr(4, c_mem_lo_addr, clk, reg_bg_ctrl_mosi);
+ -- Set the mem high address
+ proc_mem_mm_bus_wr(5, c_mem_hi_addr, clk, reg_bg_ctrl_mosi);
+ -- Set the lower part of the initial bsn
+ proc_mem_mm_bus_wr(6, c_bsn_offset, clk, reg_bg_ctrl_mosi);
+ -- Set the higher part of the initial bsn
+ proc_mem_mm_bus_wr(7, 0, clk, reg_bg_ctrl_mosi);
-- BG enable at en_sync pulse
- proc_mem_mm_bus_wr(0, 3, clk, reg_bg_ctrl_mosi); -- Enable the block generator at en_sync pulse.
+ -- Enable the block generator at en_sync pulse.
+ proc_mem_mm_bus_wr(0, 3, clk, reg_bg_ctrl_mosi);
tb_state <= s_bg_enable_sync;
- proc_common_wait_some_cycles(clk, c_pend_period); -- Wait an additional amount of cycles
- proc_common_gen_pulse(clk, en_sync); -- Issue the en_sync pulse to start the enabled block generator
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(clk, c_pend_period);
+ -- Issue the en_sync pulse to start the enabled block generator
+ proc_common_gen_pulse(clk, en_sync);
bg_en <= '1';
- proc_common_wait_some_cycles(clk, c_on_period); -- On time
- proc_common_wait_until_high(clk, out_sosi_0.valid); -- Wait until block generator [0] is active
- proc_common_wait_some_cycles(clk, 20); -- Wait an additional amount of cycles
+ -- On time
+ proc_common_wait_some_cycles(clk, c_on_period);
+ -- Wait until block generator [0] is active
+ proc_common_wait_until_high(clk, out_sosi_0.valid);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(clk, 20);
for I in 0 to g_nof_repeat - 1 loop
-- BG disable
- proc_mem_mm_bus_wr(0, 0, clk, reg_bg_ctrl_mosi); -- Disable the block generator.
+ -- Disable the block generator.
+ proc_mem_mm_bus_wr(0, 0, clk, reg_bg_ctrl_mosi);
tb_state <= s_bg_disable;
bg_en <= '0';
- proc_common_wait_some_cycles(clk, c_off_period); -- Off time
+ -- Off time
+ proc_common_wait_some_cycles(clk, c_off_period);
-- BG enable
- proc_mem_mm_bus_wr(0, 1, clk, reg_bg_ctrl_mosi); -- Enable the block generator.
+ -- Enable the block generator.
+ proc_mem_mm_bus_wr(0, 1, clk, reg_bg_ctrl_mosi);
tb_state <= s_bg_enable;
bg_en <= '1';
- proc_common_wait_some_cycles(clk, c_on_period); -- On time
- proc_common_wait_until_high(clk, out_sosi_0.valid); -- Wait until block generator [0] is active
- proc_common_wait_some_cycles(clk, 20); -- Wait an additional amount of cycles
+ -- On time
+ proc_common_wait_some_cycles(clk, c_on_period);
+ -- Wait until block generator [0] is active
+ proc_common_wait_until_high(clk, out_sosi_0.valid);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(clk, 20);
end loop;
for I in 0 to g_nof_repeat - 1 loop
-- BG flow off
- out_siso_xon <= '0'; -- Flow control XON
+ -- Flow control XON
+ out_siso_xon <= '0';
tb_state <= s_xoff;
bg_en <= '0';
- proc_common_wait_some_cycles(clk, c_off_period); -- Off time
+ -- Off time
+ proc_common_wait_some_cycles(clk, c_off_period);
-- BG flow on
- out_siso_xon <= '1'; -- Flow control XON
+ -- Flow control XON
+ out_siso_xon <= '1';
tb_state <= s_xon;
bg_en <= '1';
- proc_common_wait_some_cycles(clk, c_on_period); -- On time
+ -- On time
+ proc_common_wait_some_cycles(clk, c_on_period);
end loop;
end if;
- proc_common_wait_some_cycles(clk, c_end_period); -- Some extra time
+ -- Some extra time
+ proc_common_wait_some_cycles(clk, c_end_period);
tb_end <= '1';
wait;
end process;
p_dut_tx_seq_ctrl : process
begin
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
- proc_mem_mm_bus_wr(1, c_tx_seq_init, clk, reg_tx_seq_mosi); -- Init Tx sequence
- proc_common_wait_some_cycles(clk, 10); -- Wait for some latency
- proc_mem_mm_bus_wr(0, c_diag_seq_tx_reg_en_cntr, clk, reg_tx_seq_mosi); -- Enable Tx CNTR sequence
+ -- Wait until reset has finished
+ proc_common_wait_until_low(clk, rst);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(clk, 10);
+ -- Init Tx sequence
+ proc_mem_mm_bus_wr(1, c_tx_seq_init, clk, reg_tx_seq_mosi);
+ -- Wait for some latency
+ proc_common_wait_some_cycles(clk, 10);
+ -- Enable Tx CNTR sequence
+ proc_mem_mm_bus_wr(0, c_diag_seq_tx_reg_en_cntr, clk, reg_tx_seq_mosi);
wait;
end process;
@@ -217,7 +253,8 @@ begin
g_buf_dat_w => c_buf_dat_w,
g_buf_addr_w => c_buf_addr_w,
g_file_name_prefix => c_file_name_prefix,
- g_diag_block_gen_rst => c_diag_block_gen_enabled -- user BG is default enabled
+ -- user BG is default enabled
+ g_diag_block_gen_rst => c_diag_block_gen_enabled
)
port map (
-- System
@@ -291,7 +328,8 @@ begin
out_siso_arr(I).xon <= out_siso_xon;
end loop;
if c_verify_usr_rflow = true then
- out_siso_arr(0).ready <= out_siso_ready; -- only verify flow control via stream 0
+ -- only verify flow control via stream 0
+ out_siso_arr(0).ready <= out_siso_ready;
end if;
end process;
@@ -311,11 +349,13 @@ begin
g_buf_dat_w => c_buf_dat_w,
g_buf_addr_w => c_buf_addr_w,
g_file_name_prefix => c_file_name_prefix,
- g_diag_block_gen_rst => c_diag_block_gen_rst, -- user BG is default disabled, MM controlled by p_dut_bg_ctrl
+ -- user BG is default disabled, MM controlled by p_dut_bg_ctrl
+ g_diag_block_gen_rst => c_diag_block_gen_rst,
-- User input multiplexer option
g_usr_bypass_xonoff => g_usr_bypass_xonoff,
-- Tx_seq
- g_seq_dat_w => c_buf_dat_w -- >= 1, test sequence data width. Choose g_seq_dat_w <= g_buf_dat_w
+ -- >= 1, test sequence data width. Choose g_seq_dat_w <= g_buf_dat_w
+ g_seq_dat_w => c_buf_dat_w
)
port map (
-- System
@@ -346,7 +386,8 @@ begin
usr_src_out_0_data <= usr_src_out_arr(0).data(c_buf_dat_w - 1 downto 0);
- out_sosi_0 <= out_sosi_arr(0); -- use BG[0] as reference
+ -- use BG[0] as reference
+ out_sosi_0 <= out_sosi_arr(0);
out_sosi_0_data <= out_sosi_0.data(c_buf_dat_w - 1 downto 0);
-- Verify : Equal data in all g_nof_streams
@@ -386,11 +427,13 @@ begin
wait until rising_edge(clk);
end process;
- proc_dp_verify_data("BSN", c_bsn_max, c_bsn_gap, clk, verify_bsn_en, out_sosi_0.sop, out_sosi_0.bsn, prev_out_sosi_0.bsn); -- verify both BG and user
+ -- verify both BG and user
+ proc_dp_verify_data("BSN", c_bsn_max, c_bsn_gap, clk, verify_bsn_en, out_sosi_0.sop, out_sosi_0.bsn, prev_out_sosi_0.bsn);
-- Verify : sync
bg_en_dly <= bg_en'delayed(5 * clk_period);
- verify_sync_en <= verify_bsn_en and bg_en_dly when g_use_bg = true else '0'; -- only verify BG sync interval (ignore user sync interval)
+ -- only verify BG sync interval (ignore user sync interval)
+ verify_sync_en <= verify_bsn_en and bg_en_dly when g_use_bg = true else '0';
proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_sync_en, out_sosi_0.sync, out_sosi_0.sop, out_sosi_0.bsn);
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
index 57222de7e020adf7b3ca690ef9292a3d09157086..92cbb9494be093fd5ab2069eff6c344e0c6df542 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
@@ -42,24 +42,30 @@ use work.tb_diag_pkg.all;
entity tb_mms_diag_seq is
generic (
-- general
- g_flow_control_verify : t_dp_flow_control_enum := e_random; -- always active or random flow control
+ -- always active or random flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_random;
-- specific
g_nof_streams : natural := 1;
- g_use_steps : boolean := false; -- when TRUE this tb can only verify +1 increment (ie. using c_rx_steps_arr_ones)
+ -- when TRUE this tb can only verify +1 increment (ie. using c_rx_steps_arr_ones)
+ g_use_steps : boolean := false;
g_mm_broadcast_tx : boolean := false;
- g_data_w : natural := 40; -- >= g_seq_dat_w
+ -- >= g_seq_dat_w
+ g_data_w : natural := 40;
g_seq_dat_w : natural := 16
);
end entity tb_mms_diag_seq;
architecture str of tb_mms_diag_seq is
- constant mm_clk_period : time := 8 ns; -- 125 MHz
- constant dp_clk_period : time := 5 ns; -- 200 MHz
+ -- 125 MHz
+ constant mm_clk_period : time := 8 ns;
+ -- 200 MHz
+ constant dp_clk_period : time := 5 ns;
constant c_random_w : natural := 16;
constant c_rx_steps_arr_ones : t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0) := (1, 1, 1, 1);
constant c_rx_steps_arr_access : t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0) := (1, -2, -3, 4);
- signal random : std_logic_vector(c_random_w - 1 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(c_random_w - 1 downto 0) := (others => '0');
signal ready : std_logic;
signal tb_end : std_logic := '0';
@@ -77,7 +83,8 @@ architecture str of tb_mms_diag_seq is
signal reg_rx_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_rx_miso : t_mem_miso;
- signal rd_reg_arr : t_diag_seq_mm_reg_arr(g_nof_streams downto 0); -- use +1 to support g_nof_streams=1, 2 in p_stimuli_and_verify
+ -- use +1 to support g_nof_streams=1, 2 in p_stimuli_and_verify
+ signal rd_reg_arr : t_diag_seq_mm_reg_arr(g_nof_streams downto 0);
signal tx_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal tx_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
@@ -115,7 +122,8 @@ begin
constant c_st_0 : natural := 0;
constant c_st_1 : natural := 1;
begin
- stream_index <= 0; -- default verify stream 0
+ -- default verify stream 0
+ stream_index <= 0;
force_low_error <= '0';
force_replicate_error <= '0';
tb_mode <= s_off;
@@ -142,9 +150,11 @@ begin
-------------------------------------------------------------------------
proc_diag_seq_verify(c_st_0, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg_arr(c_st_0));
if g_nof_streams > 1 then
- stream_index <= 1; -- try stream 1
+ -- try stream 1
+ stream_index <= 1;
proc_diag_seq_verify(c_st_1, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode_multi, tb_verify, rd_reg_arr(c_st_1));
- stream_index <= 0; -- back to stream 0
+ -- back to stream 0
+ stream_index <= 0;
end if;
-------------------------------------------------------------------------
@@ -202,7 +212,8 @@ begin
tb_mode <= s_expect_error;
proc_common_wait_some_cycles(dp_clk, 1);
force_low_error <= '1';
- proc_common_wait_some_cycles(dp_clk, c_random_w); -- sufficently long to affect a valid data in case g_flow_control_verify=e_random
+ -- sufficently long to affect a valid data in case g_flow_control_verify=e_random
+ proc_common_wait_some_cycles(dp_clk, c_random_w);
force_low_error <= '0';
proc_common_wait_some_cycles(mm_clk, 200);
proc_diag_seq_verify(c_st_0, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg_arr(c_st_0));
@@ -225,14 +236,16 @@ begin
tb_mode <= s_expect_error;
proc_common_wait_some_cycles(dp_clk, 1);
force_replicate_error <= '1';
- proc_common_wait_some_cycles(dp_clk, c_random_w); -- sufficently long to affect a valid data in case g_flow_control_verify=e_random
+ -- sufficently long to affect a valid data in case g_flow_control_verify=e_random
+ proc_common_wait_some_cycles(dp_clk, c_random_w);
force_replicate_error <= '0';
proc_common_wait_some_cycles(mm_clk, 200);
proc_diag_seq_verify(c_st_0, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg_arr(c_st_0));
end if;
if g_mm_broadcast_tx = false and g_nof_streams > 1 then
- stream_index <= 1; -- try stream 1
+ -- try stream 1
+ stream_index <= 1;
-------------------------------------------------------------------------
-- Verify Tx and Rx on and both with the same pattern for stream 1
-------------------------------------------------------------------------
@@ -250,7 +263,8 @@ begin
if g_flow_control_verify = e_active then
assert rx_snk_in_arr(1).valid = '1' report "Wrong diag result: no valid data at rx_snk_in_arr(1)." severity ERROR;
end if;
- stream_index <= 0; -- back to stream 0
+ -- back to stream 0
+ stream_index <= 0;
end if;
-------------------------------------------------------------------------
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
index 6417e9d67f26ab6f9751be29c46d4892b68e9377..85aa8e81bcedb1611dca88124e744ea68bec193f 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
@@ -36,7 +36,8 @@ entity tb_tb_diag_block_gen is
end tb_tb_diag_block_gen;
architecture tb of tb_tb_diag_block_gen is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- general
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
index 09ecb0650a2a86b472f7f15fc096efcd0147a150..b015289312b87d57af39bc6856bbd807aff5afd7 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
@@ -27,7 +27,8 @@ entity tb_tb_diag_rx_seq is
end tb_tb_diag_rx_seq;
architecture tb of tb_tb_diag_rx_seq is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_tx_cnt_incr : INTEGER := 1;
-- g_tx_mod : INTEGER := 0;
@@ -38,7 +39,10 @@ begin
u_diag_sel : entity work.tb_diag_rx_seq generic map ( 1, 0, false, (1, 1, 1, 1), 8);
u_diag_steps_incr_1 : entity work.tb_diag_rx_seq generic map ( 1, 0, true, (1, 1, 1, 1), 8);
u_diag_steps_incr_neg_7 : entity work.tb_diag_rx_seq generic map (-7, 0, true, (1, -7, 1, 1), 8);
- u_diag_steps_tx_mod : entity work.tb_diag_rx_seq generic map ( 1, 255, true, (1, 2, 1, 1), 8); -- rx_step = 2**g_seq_dat_w - tx_mod + g_tx_cnt_incr = 256 - 255 + 1 = 2
- u_diag_steps_tx_mod_incr_7 : entity work.tb_diag_rx_seq generic map ( 7, 255, true, (7, 8, 7, 7), 8); -- rx_step = 2**g_seq_dat_w - tx_mod + g_tx_cnt_incr = 256 - 255 + 7 = 8
- u_diag_steps_tx_mod_incr_5 : entity work.tb_diag_rx_seq generic map ( 5, 127, true, (5, 134, 5, 5), 8); -- rx_step = 2**g_seq_dat_w - tx_mod + g_tx_cnt_incr = 256 - 127 + 5 = 134
+ -- rx_step = 2**g_seq_dat_w - tx_mod + g_tx_cnt_incr = 256 - 255 + 1 = 2
+ u_diag_steps_tx_mod : entity work.tb_diag_rx_seq generic map ( 1, 255, true, (1, 2, 1, 1), 8);
+ -- rx_step = 2**g_seq_dat_w - tx_mod + g_tx_cnt_incr = 256 - 255 + 7 = 8
+ u_diag_steps_tx_mod_incr_7 : entity work.tb_diag_rx_seq generic map ( 7, 255, true, (7, 8, 7, 7), 8);
+ -- rx_step = 2**g_seq_dat_w - tx_mod + g_tx_cnt_incr = 256 - 127 + 5 = 134
+ u_diag_steps_tx_mod_incr_5 : entity work.tb_diag_rx_seq generic map ( 5, 127, true, (5, 134, 5, 5), 8);
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
index 812024f273884f4a11e9362a4315ccb056723c59..06ca1c5471728a26ab38ad2843ad75bac316d372 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
@@ -37,7 +37,8 @@ end tb_tb_mms_diag_block_gen;
architecture tb of tb_tb_mms_diag_block_gen is
constant c_nof_repeat : natural := 2;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_use_usr_input : BOOLEAN := TRUE;
-- g_use_bg : BOOLEAN := TRUE;
@@ -60,7 +61,8 @@ begin
u_bg_tx_seq : entity work.tb_mms_diag_block_gen generic map (false, true, true, true, false, e_active, 2, 2, 0);
u_usr_bypass_all : entity work.tb_mms_diag_block_gen generic map ( true, false, false, true, false, e_active, 1, 2, 0);
- u_usr_tx_seq_random_stream_0 : entity work.tb_mms_diag_block_gen generic map ( true, false, true, true, false, e_random, 2, 2, 0); -- stream 1 is active, so both e_random and e_active are tested
+ -- stream 1 is active, so both e_random and e_active are tested
+ u_usr_tx_seq_random_stream_0 : entity work.tb_mms_diag_block_gen generic map ( true, false, true, true, false, e_random, 2, 2, 0);
u_bg_no_buffer_ram : entity work.tb_mms_diag_block_gen generic map (false, true, false, false, false, e_active, 1, 2, 0);
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
index 416cb26dec25e7b533578aa08175cf62ed7db77b..0087518b31d74d1a13e685abe2c54f1180507980 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
@@ -28,7 +28,8 @@ entity tb_tb_mms_diag_seq is
end tb_tb_mms_diag_seq;
architecture tb of tb_tb_mms_diag_seq is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random flow control
-- g_nof_streams : NATURAL := 2;
diff --git a/libraries/base/diagnostics/src/vhdl/diagnostics.vhd b/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
index 2fceec4f1a5a59d0e6a04d0a1d485ec702535944..e0310ff3ae127ddb7115f42d5b16564d55d9c4bc 100644
--- a/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
+++ b/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
@@ -40,12 +40,15 @@ use dp_lib.dp_stream_pkg.all;
entity diagnostics is
generic (
- g_dat_w : natural; -- data width per stream (8..256)
- g_block_len : natural := 0; -- 0: data+valid only; >0 add sop, eop
+ -- data width per stream (8..256)
+ g_dat_w : natural;
+ -- 0: data+valid only; >0 add sop, eop
+ g_block_len : natural := 0;
g_nof_streams : natural := 1;
g_src_latency : natural := 1;
g_snk_latency : natural := 1;
- g_separate_clk : boolean := false -- Use separate SRC and SNK clock domains
+ -- Use separate SRC and SNK clock domains
+ g_separate_clk : boolean := false
);
port (
rst : in std_logic := '0';
@@ -78,7 +81,8 @@ end diagnostics;
architecture str of diagnostics is
constant c_min_dat_w : natural := 8;
constant c_max_dat_w : natural := 32;
- constant c_sub_stream_dat_w : natural := split_w(g_dat_w, c_min_dat_w, c_max_dat_w); -- Calculate appropriate data width of internal streams
+ -- Calculate appropriate data width of internal streams
+ constant c_sub_stream_dat_w : natural := split_w(g_dat_w, c_min_dat_w, c_max_dat_w);
constant c_nof_substreams : natural := g_dat_w / c_sub_stream_dat_w;
type t_streams_x_substreams_arr is array(g_nof_streams - 1 downto 0) of std_logic_vector(c_nof_substreams - 1 downto 0);
@@ -103,7 +107,8 @@ architecture str of diagnostics is
signal rx_dpmon_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal tx_seq_out_val : t_streams_x_substreams_arr;
- signal tb_clken : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '1'); -- TB signal - can be forced to '0' to pause valid output and to '1' again to continue
+ -- TB signal - can be forced to '0' to pause valid output and to '1' again to continue
+ signal tb_clken : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '1');
signal tx_clk : std_logic_vector(g_nof_streams - 1 downto 0);
signal tx_rst : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -128,8 +133,10 @@ begin
rx_rst(i) <= rst;
end generate;
- snk_diag_res(i) <= orv(substream_snk_diag_res(i)); -- Create a one-bit diag_res per stream
- snk_diag_res_val(i) <= andv(substream_snk_diag_res_val(i)); -- If all substream diag results are valid, the stream's diag_res is valid.
+ -- Create a one-bit diag_res per stream
+ snk_diag_res(i) <= orv(substream_snk_diag_res(i));
+ -- If all substream diag results are valid, the stream's diag_res is valid.
+ snk_diag_res_val(i) <= andv(substream_snk_diag_res_val(i));
u_tx_latency_adpt: entity dp_lib.dp_latency_adapter
generic map (
@@ -223,7 +230,8 @@ begin
diag_en => snk_diag_en(i),
diag_sel => snk_diag_md(i),
- orv(diag_res) => substream_snk_diag_res(i)(j), -- vector-wise OR to create a one-bit diag_result per substream
+ -- vector-wise OR to create a one-bit diag_result per substream
+ orv(diag_res) => substream_snk_diag_res(i)(j),
diag_res_val => substream_snk_diag_res_val(i)(j),
in_dat => rx_sosi_arr(i).data( (j + 1) * c_sub_stream_dat_w - 1 downto (j + 1) * c_sub_stream_dat_w - c_sub_stream_dat_w),
@@ -233,8 +241,10 @@ begin
tx_sosi_arr(i).valid <= tx_seq_out_val(i)(0);
- rx_siso_arr(i).ready <= '1'; -- snk_diag_en(i);
- rx_siso_arr(i).xon <= '1'; -- snk_diag_en(i);
+ -- snk_diag_en(i);
+ rx_siso_arr(i).ready <= '1';
+ -- snk_diag_en(i);
+ rx_siso_arr(i).xon <= '1';
u_tx_dpmon : entity dp_lib.dp_mon
generic map (
diff --git a/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd b/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
index 6fd9e3ac98be7dc3c51517b8c11c03d38582c56d..a7a1bcf70cf06308c3bf7b40e379ea307d849084 100644
--- a/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
@@ -28,15 +28,20 @@ use diag_lib.diag_pkg.all;
entity diagnostics_reg is
generic (
g_nof_streams : natural;
- g_separate_clk : boolean := false -- Use separate SRC and SNK clock domains
+ -- Use separate SRC and SNK clock domains
+ g_separate_clk : boolean := false
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
- st_rst : in std_logic := '0'; -- reset synchronous with st_clk
- st_clk : in std_logic := '0'; -- other clock domain clock
+ -- reset synchronous with st_clk
+ st_rst : in std_logic := '0';
+ -- other clock domain clock
+ st_clk : in std_logic := '0';
src_clk : in std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0');
src_rst : in std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0');
@@ -45,8 +50,10 @@ entity diagnostics_reg is
snk_rst : in std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0');
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
st_src_en : out std_logic_vector(g_nof_streams - 1 downto 0);
@@ -64,23 +71,27 @@ entity diagnostics_reg is
end diagnostics_reg;
architecture rtl of diagnostics_reg is
- constant c_nof_registers : natural := 40; -- src_cnt and snk_cnt registers should be variable in size....but the CASE process makes that difficult.
+ -- src_cnt and snk_cnt registers should be variable in size....but the CASE process makes that difficult.
+ constant c_nof_registers : natural := 40;
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_registers),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_nof_registers,
init_sl => '0');
-- Registers in mm_clk domain
signal mm_src_en : std_logic_vector(g_nof_streams - 1 downto 0);
signal mm_src_md : std_logic_vector(g_nof_streams - 1 downto 0);
- signal mm_src_cnt : t_slv_32_arr(16 - 1 downto 0); -- g_nof_streams not used as we must support 16 (fixed number of regs)
+ -- g_nof_streams not used as we must support 16 (fixed number of regs)
+ signal mm_src_cnt : t_slv_32_arr(16 - 1 downto 0);
signal mm_src_cnt_clr_evt : std_logic_vector(g_nof_streams - 1 downto 0);
signal mm_snk_en : std_logic_vector(g_nof_streams - 1 downto 0);
signal mm_snk_md : std_logic_vector(g_nof_streams - 1 downto 0);
- signal mm_snk_cnt : t_slv_32_arr(16 - 1 downto 0); -- g_nof_streams not used as we must support 16 (fixed number of regs)
+ -- g_nof_streams not used as we must support 16 (fixed number of regs)
+ signal mm_snk_cnt : t_slv_32_arr(16 - 1 downto 0);
signal mm_snk_cnt_clr_evt : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -153,16 +164,20 @@ begin
mm_snk_md <= sla_in.wrdata(g_nof_streams - 1 downto 0);
when 21 =>
mm_snk_cnt_clr_evt <= sla_in.wrdata(g_nof_streams - 1 downto 0);
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
when 3 =>
- sla_out.rddata(c_word_w - 1 downto 0) <= mm_src_cnt(0); -- 16 src/snk counts supported for now.
+ -- 16 src/snk counts supported for now.
+ sla_out.rddata(c_word_w - 1 downto 0) <= mm_src_cnt(0);
when 4 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_src_cnt(1);
when 5 =>
@@ -232,7 +247,8 @@ begin
when 39 =>
sla_out.rddata(g_nof_streams - 1 downto 0) <= mm_snk_diag_res;
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
index 3f93466da3deca5dc5c350011a771d610a795da3..6b9a0bcffd9f5340c40d6b86dcd0f614d8250dcd 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
@@ -33,7 +33,8 @@ entity mm_rx_logger is
generic (
g_technology : natural := c_tech_select_default;
g_dat_w : natural;
- g_fifo_wr_depth : natural := 128 -- Only put powers of 2 here.
+ -- Only put powers of 2 here.
+ g_fifo_wr_depth : natural := 128
);
port (
rx_rst : in std_logic;
@@ -41,11 +42,14 @@ entity mm_rx_logger is
data_in : in std_logic_vector(g_dat_w - 1 downto 0);
- log_en_evt : in std_logic := '0'; -- Trigger inputs, can be overridden by MM control.
+ -- Trigger inputs, can be overridden by MM control.
+ log_en_evt : in std_logic := '0';
log_dis_evt : in std_logic := '0';
- mst_log_en : out std_logic; -- Can be used to enable a slave logger simultaneously. Then this output on the master instance...
- sla_log_en : in std_logic := '0'; -- ...connects to this input on the slave instance.
+ -- Can be used to enable a slave logger simultaneously. Then this output on the master instance...
+ mst_log_en : out std_logic;
+ -- ...connects to this input on the slave instance.
+ sla_log_en : in std_logic := '0';
mm_rst : in std_logic;
mm_clk : in std_logic;
@@ -77,7 +81,8 @@ architecture str of mm_rx_logger is
signal data_dpmm_fifo_sosi : t_dp_sosi;
signal data_dpmm_fifo_siso : t_dp_siso;
- signal ovr_data_dpmm_fifo_siso : t_dp_siso; -- overridden ready signal
+ -- overridden ready signal
+ signal ovr_data_dpmm_fifo_siso : t_dp_siso;
signal data_mm_sosi : t_dp_sosi;
signal data_mm_siso : t_dp_siso;
@@ -91,7 +96,8 @@ architecture str of mm_rx_logger is
signal trig_log_en : std_logic;
signal log_en : std_logic;
- signal mm_ovr : std_logic := '0'; -- Normal operation (mm_over='0') : trigger enable/disable inputs control log_en
+ -- Normal operation (mm_over='0') : trigger enable/disable inputs control log_en
+ signal mm_ovr : std_logic := '0';
-- Overridden operation (mm_over='1'): MM master controls log_en
signal mm_trig_on : std_logic;
@@ -130,8 +136,10 @@ begin
log_en => trig_log_en
);
- log_en <= trig_log_en or sla_log_en; -- Allow slave input to enable logging
- mst_log_en <= log_en; -- Forward log_en signal to master output
+ -- Allow slave input to enable logging
+ log_en <= trig_log_en or sla_log_en;
+ -- Forward log_en signal to master output
+ mst_log_en <= log_en;
data_log_fifo_sosi.valid <= log_en;
data_log_fifo_sosi.data(g_dat_w - 1 downto 0) <= data_in;
@@ -176,13 +184,16 @@ begin
flush_en => flush_en
);
- flush_en <= not data_log_fifo_siso.ready; -- We'll flush when the data log fifo is almost full.
+ -- We'll flush when the data log fifo is almost full.
+ flush_en <= not data_log_fifo_siso.ready;
-- overridden siso.ready signal from dpmm_fifo to flusher: we do not want any data in our dpmm FIFO until we've stopped logging
-- for mm readout. Otherwise our (shallow) dpmm FIFO will be filled to the max (and de-assert ready), then the data FIFO will fill
-- to the max which causes the flusher to flush new data, while outdated data remains in the dpmm FIFO.
- ovr_data_dpmm_fifo_siso.ready <= '0' when log_en = '1' else data_dpmm_fifo_siso.ready; -- not ready when logging is enabled
- ovr_data_dpmm_fifo_siso.xon <= data_dpmm_fifo_siso.xon; -- leave xon as it is
+ -- not ready when logging is enabled
+ ovr_data_dpmm_fifo_siso.ready <= '0' when log_en = '1' else data_dpmm_fifo_siso.ready;
+ -- leave xon as it is
+ ovr_data_dpmm_fifo_siso.xon <= data_dpmm_fifo_siso.xon;
u_data_dpmm_fifo : entity dp_lib.dp_fifo_dc_mixed_widths
generic map (
@@ -219,12 +230,14 @@ begin
snk_out => data_mm_siso,
snk_in => data_mm_sosi,
- usedw => data_dpmm_fifo_rd_usedw, -- used words from the clock crossing FIFO (NOT the logging FIFO)
+ -- used words from the clock crossing FIFO (NOT the logging FIFO)
+ usedw => data_dpmm_fifo_rd_usedw,
mm_rd => data_mm_rd,
mm_rddata => data_mm_rd_data,
mm_rdval => data_mm_rd_val,
- mm_usedw => data_mm_rd_usedw -- used words resized to 32 bits
+ -- used words resized to 32 bits
+ mm_usedw => data_mm_rd_usedw
);
-- data read output to mm bus
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
index fb6107194a79b5345849866333b306241a0f3e83..a23d0fe8a6c5f1f7c985ab331cb2984d4265d993 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
@@ -27,14 +27,20 @@ use common_lib.common_mem_pkg.all;
entity mm_rx_logger_reg is
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- rx_rst : in std_logic; -- reset synchronous with rx_clk
- rx_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with rx_clk
+ rx_rst : in std_logic;
+ -- other clock domain clock
+ rx_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in rx_clk domain
rx_trig_on : out std_logic;
@@ -54,7 +60,8 @@ end mm_rx_logger_reg;
architecture rtl of mm_rx_logger_reg is
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(8),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 8,
init_sl => '0');
-- Registers in mm_clk domain
@@ -111,20 +118,24 @@ begin
when 7 =>
mm_log_dis_evt <= sla_in.wrdata(0);
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read Block Sync
when 3 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_trig_nof_logged_words;
when 4 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_data_usedw;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
index cfe4fe951f828fd7bdd7b8fe289fac2d394e31ea..6518060a347c9813ea5d8448c176340acc8aaa36 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
@@ -30,10 +30,12 @@ entity mm_rx_logger_trig is
clk : in std_logic;
rst : in std_logic;
trig_on : in std_logic;
- one_shot : in std_logic; -- Enable this if you want to be absolutely positive that you've logged the first occurrence
+ -- Enable this if you want to be absolutely positive that you've logged the first occurrence
+ one_shot : in std_logic;
log_en_evt : in std_logic;
log_dis_evt : in std_logic;
- log_nof_words : in std_logic_vector(c_word_w - 1 downto 0); -- unlimited (as long as there's no dis_evt) when zero (log FIFO keeps flushing then)
+ -- unlimited (as long as there's no dis_evt) when zero (log FIFO keeps flushing then)
+ log_nof_words : in std_logic_vector(c_word_w - 1 downto 0);
log_cnt : out std_logic_vector(c_word_w - 1 downto 0);
log_en : out std_logic
);
@@ -71,7 +73,8 @@ begin
when s_logging =>
log_en <= '1';
- if log_dis_evt = '1' or i_log_cnt = log_nof_words then -- As we start with a log_cnt of 1, a log_nof_words of 0 will not disable logging.
+ -- As we start with a log_cnt of 1, a log_nof_words of 0 will not disable logging.
+ if log_dis_evt = '1' or i_log_cnt = log_nof_words then
log_en <= '0';
if one_shot = '1' then
nxt_state <= s_one_shot;
@@ -82,7 +85,8 @@ begin
nxt_log_cnt <= INCR_UVEC(i_log_cnt, 1);
end if;
- when s_one_shot => -- Remain in one-shot state until one_shot is set to '0'.
+ -- Remain in one-shot state until one_shot is set to '0'.
+ when s_one_shot =>
log_en <= '0';
if one_shot = '1' then
nxt_state <= s_idle;
@@ -92,13 +96,15 @@ begin
log_en <= '0';
if trig_on = '1' then
if log_en_evt = '1' then
- nxt_log_cnt <= x"00000001"; -- As we're enabling logging here already, we'll have logged 1 word on the next cycle.
+ -- As we're enabling logging here already, we'll have logged 1 word on the next cycle.
+ nxt_log_cnt <= x"00000001";
log_en <= '1';
nxt_state <= s_logging;
end if;
end if;
- when others => -- s_init
+ -- s_init
+ when others =>
log_en <= '0';
nxt_state <= s_idle;
end case;
diff --git a/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd b/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
index 6f31fd34b9a9b09fcd37b8ace2fa311475040de6..1bb1a74931d88ba6c76b61ee7eee37083cb85083 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
@@ -41,7 +41,8 @@ entity mm_tx_framer is
tx_clk : in std_logic;
tx_rst : in std_logic;
- ctrl_mosi : in t_mem_mosi := c_mem_mosi_rst; -- No need to connect the CTRL MM bus if this instance is not the master
+ -- No need to connect the CTRL MM bus if this instance is not the master
+ ctrl_mosi : in t_mem_mosi := c_mem_mosi_rst;
ctrl_miso : out t_mem_miso;
data_mosi : in t_mem_mosi := c_mem_mosi_rst;
@@ -50,8 +51,10 @@ entity mm_tx_framer is
data_out_default : in std_logic_vector(g_dat_out_w - 1 downto 0) := (others => '0');
data_out : out std_logic_vector(g_dat_out_w - 1 downto 0);
- master_release : out std_logic; -- If used this instance will provide master release control for other instance(s)
- slave_release : in std_logic := '0' -- If this instance is slave of another instance, the an MM write to the master's MM release will
+ -- If used this instance will provide master release control for other instance(s)
+ master_release : out std_logic;
+ -- If this instance is slave of another instance, the an MM write to the master's MM release will
+ slave_release : in std_logic := '0'
-- also release the frames in the slave(s)
);
end mm_tx_framer;
@@ -105,7 +108,8 @@ begin
snk_out => OPEN,
snk_in => mm_to_fifo_sosi,
- wr_usedw => wr_usedw, -- Using wr_usedw because that side is in mm_clk domain
+ -- Using wr_usedw because that side is in mm_clk domain
+ wr_usedw => wr_usedw,
rd_usedw => OPEN,
rd_emp => OPEN,
diff --git a/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd b/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
index 97ef6ed9f100d8c45d1336f8928e7f2762218ead..d1602035058931174109f2d8d0b645873e52487a 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
@@ -33,8 +33,10 @@ entity mm_tx_framer_reg is
tx_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
tx_release : out std_logic;
@@ -48,7 +50,8 @@ end mm_tx_framer_reg;
architecture rtl of mm_tx_framer_reg is
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(2),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 2,
init_sl => '0');
-- Registers in mm_clk domain
@@ -82,18 +85,22 @@ begin
-- Write Block Sync
when 1 =>
mm_release <= sla_in.wrdata(0);
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read Block Sync
when 0 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_availw;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd b/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
index a1c02e233098a2c5af52e6a1ce68cf92b02410cc..423fd8281286d6781591ed3176bf854ab9df1bf0 100644
--- a/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
@@ -31,7 +31,8 @@ entity mms_diagnostics is
generic (
g_sim : boolean := false;
g_data_w : natural;
- g_block_len : natural := 0; -- 0: data+valid only; >0 add sop, eop
+ -- 0: data+valid only; >0 add sop, eop
+ g_block_len : natural := 0;
g_nof_streams : natural;
g_src_latency : natural := 1;
g_snk_latency : natural := 1;
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
index 4df9f42fa1e970a993f3cb0115e8d9cde1271639..2edfdc26a1c2cbde7d6b6f0a315492c5f2535321 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
@@ -39,10 +39,13 @@ end entity tb_diagnostics;
architecture str of tb_diagnostics is
constant c_sim : boolean := true;
- constant clk_period : time := 5 ns; -- 200 MHz
+ -- 200 MHz
+ constant clk_period : time := 5 ns;
- constant c_nof_streams : natural := 2; -- any NATURAL number
- constant c_dat_w : natural := 64; -- 8..256
+ -- any NATURAL number
+ constant c_nof_streams : natural := 2;
+ -- 8..256
+ constant c_dat_w : natural := 64;
signal tb_end : std_logic := '0';
signal clk : std_logic := '0';
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
index 796aeba35b4cfc5f86b12b1aa6ac3f6a783a4873..9b9cbf553d5370bba2529009e099b51879530847 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
@@ -69,13 +69,15 @@ package body tb_diagnostics_trnb_pkg is
procedure proc_diagnostics_trnb_tx_set_mode_prbs(signal mm_clk : in std_logic;
signal mm_mosi : out t_mem_mosi) is
begin
- proc_mem_mm_bus_wr( 1, 0, mm_clk, mm_mosi); -- set source mode 0 = PRBS, 1 = COUNTER
+ -- set source mode 0 = PRBS, 1 = COUNTER
+ proc_mem_mm_bus_wr( 1, 0, mm_clk, mm_mosi);
end procedure proc_diagnostics_trnb_tx_set_mode_prbs;
procedure proc_diagnostics_trnb_rx_set_mode_prbs(signal mm_clk : in std_logic;
signal mm_mosi : out t_mem_mosi) is
begin
- proc_mem_mm_bus_wr(20, 0, mm_clk, mm_mosi); -- set sink mode 0 = PRBS, 1 = COUNTER
+ -- set sink mode 0 = PRBS, 1 = COUNTER
+ proc_mem_mm_bus_wr(20, 0, mm_clk, mm_mosi);
end procedure proc_diagnostics_trnb_rx_set_mode_prbs;
------------------------------------------------------------------------------
@@ -87,14 +89,16 @@ package body tb_diagnostics_trnb_pkg is
signal mm_clk : in std_logic;
signal mm_mosi : out t_mem_mosi) is
begin
- proc_mem_mm_bus_wr( 1, c_nof_gx_mask, mm_clk, mm_mosi); -- set source mode 0 = PRBS, 1 = COUNTER
+ -- set source mode 0 = PRBS, 1 = COUNTER
+ proc_mem_mm_bus_wr( 1, c_nof_gx_mask, mm_clk, mm_mosi);
end procedure proc_diagnostics_trnb_tx_set_mode_counter;
procedure proc_diagnostics_trnb_rx_set_mode_counter(constant c_nof_gx_mask : in natural;
signal mm_clk : in std_logic;
signal mm_mosi : out t_mem_mosi) is
begin
- proc_mem_mm_bus_wr(20, c_nof_gx_mask, mm_clk, mm_mosi); -- set source mode 0 = PRBS, 1 = COUNTER
+ -- set source mode 0 = PRBS, 1 = COUNTER
+ proc_mem_mm_bus_wr(20, c_nof_gx_mask, mm_clk, mm_mosi);
end procedure proc_diagnostics_trnb_rx_set_mode_counter;
------------------------------------------------------------------------------
@@ -116,18 +120,23 @@ package body tb_diagnostics_trnb_pkg is
variable v_diag_results : std_logic_vector(c_nof_gx - 1 downto 0);
begin
-- Enable diagnostics
- proc_mem_mm_bus_wr( 0, c_nof_gx_mask, mm_clk, mm_mosi); -- set source enable
- proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_link_delay); -- ensure source data has arrived before enabling the sink
- proc_mem_mm_bus_wr(19, c_nof_gx_mask, mm_clk, mm_mosi); -- set sink enable
+ -- set source enable
+ proc_mem_mm_bus_wr( 0, c_nof_gx_mask, mm_clk, mm_mosi);
+ -- ensure source data has arrived before enabling the sink
+ proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_link_delay);
+ -- set sink enable
+ proc_mem_mm_bus_wr(19, c_nof_gx_mask, mm_clk, mm_mosi);
-- Measurement interval
proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_diag_on_interval);
-- Read results
- proc_mem_mm_bus_rd(38, mm_clk, mm_miso, mm_mosi); -- get sink diag result valid
+ -- get sink diag result valid
+ proc_mem_mm_bus_rd(38, mm_clk, mm_miso, mm_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
v_diag_results_valid := mm_miso.rddata(c_nof_gx - 1 downto 0) and c_nof_gx_mask_slv;
- proc_mem_mm_bus_rd(39, mm_clk, mm_miso, mm_mosi); -- get sink diag result
+ -- get sink diag result
+ proc_mem_mm_bus_rd(39, mm_clk, mm_miso, mm_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
v_diag_results := mm_miso.rddata(c_nof_gx - 1 downto 0) and c_nof_gx_mask_slv;
proc_common_wait_some_cycles(mm_clk, 1);
@@ -136,9 +145,12 @@ package body tb_diagnostics_trnb_pkg is
assert TO_UINT(v_diag_results_valid) = c_nof_gx_mask and TO_UINT(v_diag_results) = 0 report "proc_diagnostics_trnb_run_and_verify: TRNB diagnostics on went wrong on node " & natural'image(c_chip_id) severity ERROR;
-- Disable diagnostics
- proc_mem_mm_bus_wr(19, 0, mm_clk, mm_mosi); -- set sink disable
- proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_link_delay); -- ensure disabling the sink before the source data has stopped arriving
- proc_mem_mm_bus_wr( 0, 0, mm_clk, mm_mosi); -- set source disable
+ -- set sink disable
+ proc_mem_mm_bus_wr(19, 0, mm_clk, mm_mosi);
+ -- ensure disabling the sink before the source data has stopped arriving
+ proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_link_delay);
+ -- set source disable
+ proc_mem_mm_bus_wr( 0, 0, mm_clk, mm_mosi);
-- Idle interval
proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_diag_off_interval);
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd b/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
index 9500074a594f10eb0193d53b0478c7a074c12758..bc564655dd58a28be0e78e83a372b5e3a9189930 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
@@ -33,8 +33,10 @@ entity tb_mm_tx_framer is
end tb_mm_tx_framer;
architecture tb of tb_mm_tx_framer is
- constant c_mm_clk_period : time := 8 ns; -- 125 MHz MM clock, altpll in SOPC will make this from the ETH 25 MHz XO clock
- constant c_tx_clk_period : time := 6.4 ns; -- 156.25 MHz
+ -- 125 MHz MM clock, altpll in SOPC will make this from the ETH 25 MHz XO clock
+ constant c_mm_clk_period : time := 8 ns;
+ -- 156.25 MHz
+ constant c_tx_clk_period : time := 6.4 ns;
signal tx_rst : std_logic := '1';
signal tx_clk : std_logic := '0';
@@ -52,9 +54,12 @@ architecture tb of tb_mm_tx_framer is
signal sla_data_miso : t_mem_miso;
-- Register offsets:
- constant c_ofs_ctrl_availw : natural := 0; -- RD
- constant c_ofs_ctrl_release : natural := 1; -- WR
- constant c_ofs_data : natural := 0; -- WR
+ -- RD
+ constant c_ofs_ctrl_availw : natural := 0;
+ -- WR
+ constant c_ofs_ctrl_release : natural := 1;
+ -- WR
+ constant c_ofs_data : natural := 0;
signal mst_data_out : std_logic_vector(63 downto 0);
signal sla_data_out : std_logic_vector(31 downto 0);
@@ -68,7 +73,8 @@ begin
mm_rst <= '0' after 700 ns;
tx_clk <= not tx_clk after c_tx_clk_period / 2;
- mm_clk <= not mm_clk after c_mm_clk_period / 2; -- MM clock (125 MHz)
+ -- MM clock (125 MHz)
+ mm_clk <= not mm_clk after c_mm_clk_period / 2;
-------------------------------------------------------------------------------------
-- PROCESS: Assemble 2 frames of equal length and assert 'release'
@@ -92,10 +98,12 @@ begin
-- Add some counter data to the frame
for i in 0 to 49 loop
- proc_mem_mm_bus_wr(c_ofs_data, i, mm_clk, mst_data_mosi); -- MS portion, 0 - 49
+ -- MS portion, 0 - 49
+ proc_mem_mm_bus_wr(c_ofs_data, i, mm_clk, mst_data_mosi);
proc_common_wait_some_cycles(mm_clk, 4);
- proc_mem_mm_bus_wr(c_ofs_data, i + 100, mm_clk, mst_data_mosi); -- LS portion, 100 - 149
+ -- LS portion, 100 - 149
+ proc_mem_mm_bus_wr(c_ofs_data, i + 100, mm_clk, mst_data_mosi);
proc_common_wait_some_cycles(mm_clk, 4);
end loop;
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
index 8e84c4b54cefa76aca3a7e8fbfb249f343f8a738..04af551b1618e0a45ffac8e9b1ce8d2c6179bdd9 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
@@ -57,7 +57,8 @@ use common_lib.common_network_layers_pkg.all;
entity mmm_unb1_dp_offload is
generic (
- g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
+ -- FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_nof_streams : natural;
@@ -135,7 +136,8 @@ architecture str of mmm_unb1_dp_offload is
constant c_ram_diag_bg_addr_w : natural := ceil_log2(g_nof_streams * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
- constant c_reg_dp_offload_tx_adr_w : natural := 1; -- Dev note: add to c_unb1_board_peripherals_mm_reg_default
+ -- Dev note: add to c_unb1_board_peripherals_mm_reg_default
+ constant c_reg_dp_offload_tx_adr_w : natural := 1;
constant c_reg_dp_offload_tx_multi_adr_w : natural := ceil_log2(g_nof_streams * pow2(c_reg_dp_offload_tx_adr_w));
constant c_reg_dp_offload_tx_hdr_dat_nof_words : natural := field_nof_words(g_hdr_field_arr, c_word_w);
@@ -234,7 +236,8 @@ begin
wait until rising_edge(i_mm_clk);
proc_tech_tse_setup(c_tech_stratixiv, false, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, i_mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, i_mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi);
sim_eth_mm_bus_switch <= '0';
wait;
@@ -262,10 +265,13 @@ begin
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_dp_offload
port map (
- clk_0 => xo_clk, -- 25 MHz from ETH_clk pin
+ -- 25 MHz from ETH_clk pin
+ clk_0 => xo_clk,
reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- 125 MHz system clock
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
+ -- 125 MHz system clock
+ mm_clk => i_mm_clk,
+ -- PLL clk[2] = 125 MHz calibration clock for the TSE
+ tse_clk => i_tse_clk,
dp_clk => i_dp_clk,
cal_reconf_clk => OPEN,
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
index 52877cb0357bc723d4edcafd150e1e950d0a9733..3c94ec2976fd8a6198727c74a8a5f12fe60a5869 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
@@ -43,12 +43,18 @@ use common_lib.common_field_pkg.all;
entity unb1_dp_offload is
generic (
- g_sim : boolean := false; -- set by ModelSim
- g_sim_unb_nr : natural := 0; -- set by ModelSim
- g_sim_node_nr : natural := 0; -- set by ModelSim
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- set by ModelSim
+ g_sim : boolean := false;
+ -- set by ModelSim
+ g_sim_unb_nr : natural := 0;
+ -- set by ModelSim
+ g_sim_node_nr : natural := 0;
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
@@ -82,9 +88,12 @@ architecture str of unb1_dp_offload is
-- Block generator
constant c_bg_block_size : natural := 900;
constant c_bg_gapsize : natural := 100;
- constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable
- '0', -- enable_sync
+ -- 200000*(900+100) = 200000000 cycles = 1 second
+ constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000);
+ -- enable
+ constant c_bg_ctrl : t_diag_block_gen := ('0',
+ -- enable_sync
+ '0',
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
@@ -93,7 +102,8 @@ architecture str of unb1_dp_offload is
TO_UVEC( 0, c_diag_bg_bsn_init_w));
-- dp_offload_tx
- constant c_nof_hdr_fields : natural := 4 + 12 + 4 + 9; -- Total header bits = 512
+ -- Total header bits = 512
+ constant c_nof_hdr_fields : natural := 4 + 12 + 4 + 9;
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(x"002286080000") ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
diff --git a/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
index 9faac986ed33160b6a3cb042cdb017a7fc23d1df..712a0da2df0ab4abf32199ace05f68449a886eda 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
@@ -50,8 +50,10 @@ end tb_unb1_dp_offload;
architecture tb of tb_unb1_dp_offload is
constant c_sim : boolean := true;
- constant c_unb1_board_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 0; -- FN0
+ -- UniBoard 0
+ constant c_unb1_board_nr : natural := 0;
+ -- FN0
+ constant c_node_nr : natural := 0;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb1_board_nr, c_unb1_board_nof_uniboard_w ) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
index 96e84bff329d7f69694decb02a38a5b9c9ec8825..37e6b74cbebd8f565f9f3687783f244c241fb99c 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
@@ -77,7 +77,8 @@ entity dp_block_from_mm is
g_step_size : natural;
g_nof_data : natural;
g_word_w : natural := c_word_w;
- g_mm_rd_latency : natural := 1; -- default 1 from rd_en to rd_val, use 2 to ease timing closure
+ -- default 1 from rd_en to rd_val, use 2 to ease timing closure
+ g_mm_rd_latency : natural := 1;
g_reverse_word_order : boolean := false;
g_bsn_w : natural := 1;
g_bsn_incr_enable : boolean := true
@@ -86,10 +87,12 @@ entity dp_block_from_mm is
rst : in std_logic;
clk : in std_logic;
start_pulse : in std_logic;
- sync_in : in std_logic := '0'; -- Must be syncronous with start_pulse.
+ -- Must be syncronous with start_pulse.
+ sync_in : in std_logic := '0';
bsn_at_sync : in std_logic_vector(g_bsn_w - 1 downto 0) := (others => '0');
start_address : in natural;
- mm_done : out std_logic; -- = out_sosi.eop
+ -- = out_sosi.eop
+ mm_done : out std_logic;
mm_mosi : out t_mem_mosi;
mm_miso : in t_mem_miso;
out_sosi : out t_dp_sosi;
@@ -107,10 +110,14 @@ architecture rtl of dp_block_from_mm is
eop : std_logic;
sync_in_detected : std_logic;
bsn : std_logic_vector(g_bsn_w - 1 downto 0);
- user_index : natural range 0 to g_user_size; -- word index in g_user_size
- data_index : natural range 0 to g_data_size; -- default word order index in g_data_size
- word_index : natural range 0 to g_data_size; -- default or reversed word order index in g_data_size
- step_address : natural range 0 to c_mem_size; -- step address offset
+ -- word index in g_user_size
+ user_index : natural range 0 to g_user_size;
+ -- default word order index in g_data_size
+ data_index : natural range 0 to g_data_size;
+ -- default or reversed word order index in g_data_size
+ word_index : natural range 0 to g_data_size;
+ -- step address offset
+ step_address : natural range 0 to c_mem_size;
end record;
constant c_reg_rst : t_reg := ('0', '0', '0', '0', '0', (others => '0'), 0, 0, 0, 0);
@@ -132,8 +139,10 @@ architecture rtl of dp_block_from_mm is
signal out_bsn : std_logic_vector(g_bsn_w - 1 downto 0);
begin
last_mm_address <= g_step_size * (g_nof_data - 1) + g_data_size + start_address - 1;
- mm_address <= start_address + r.data_index + r.step_address; -- default word order per g_user_size
- mm_address_rev <= start_address + r.word_index + r.step_address; -- reverse word order per g_user_size
+ -- default word order per g_user_size
+ mm_address <= start_address + r.data_index + r.step_address;
+ -- reverse word order per g_user_size
+ mm_address_rev <= start_address + r.word_index + r.step_address;
-- Take care of g_mm_rd_latency for out_sosi.sop and out_sosi.eop
r_sop_p <= r.sop when rising_edge(clk);
@@ -147,13 +156,19 @@ begin
p_out_sosi : process(mm_miso, out_sop, out_eop, out_sync, out_bsn)
begin
- out_sosi <= c_dp_sosi_rst; -- To avoid Modelsim warnings on conversion to integer from unused fields.
+ -- To avoid Modelsim warnings on conversion to integer from unused fields.
+ out_sosi <= c_dp_sosi_rst;
out_sosi.data <= RESIZE_DP_DATA(mm_miso.rddata(g_word_w - 1 downto 0));
- out_sosi.valid <= mm_miso.rdval; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
- out_sosi.sop <= out_sop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop
- out_sosi.eop <= out_eop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop
- out_sosi.sync <= out_sync; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sync can be used for output sync
- out_sosi.bsn <= RESIZE_DP_BSN(out_bsn); -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.bsn can be used for output bsn
+ -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
+ out_sosi.valid <= mm_miso.rdval;
+ -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop
+ out_sosi.sop <= out_sop;
+ -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop
+ out_sosi.eop <= out_eop;
+ -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sync can be used for output sync
+ out_sosi.sync <= out_sync;
+ -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.bsn can be used for output bsn
+ out_sosi.bsn <= RESIZE_DP_BSN(out_bsn);
end process;
mm_done <= out_eop;
@@ -240,8 +255,10 @@ begin
-- Account for g_reverse_word_order
if g_reverse_word_order then
- v_base := v.data_index - v.user_index; -- data_index of first word in g_user_size
- v_reverse := g_user_size - 1 - v.user_index; -- reverse word index in g_user_size
+ -- data_index of first word in g_user_size
+ v_base := v.data_index - v.user_index;
+ -- reverse word index in g_user_size
+ v_reverse := g_user_size - 1 - v.user_index;
v.word_index := v_base + v_reverse;
mm_mosi.address <= TO_MEM_ADDRESS(mm_address_rev);
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
index a5dbf8136b58958fbfc2b228b8f53ed13d73e326..1840a004f71f111b8f1003064006b0582a3737d9 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
@@ -67,10 +67,12 @@ entity dp_block_from_mm_dc is
dp_rst : in std_logic;
dp_clk : in std_logic;
start_pulse : in std_logic;
- sync_in : in std_logic := '0'; -- Must be syncronous with start_pulse.
+ -- Must be syncronous with start_pulse.
+ sync_in : in std_logic := '0';
bsn_at_sync : in std_logic_vector(g_bsn_w - 1 downto 0) := (others => '0');
start_address : in natural;
- out_sop : out std_logic; -- = out_sosi.sop
+ -- = out_sosi.sop
+ out_sop : out std_logic;
out_sosi : out t_dp_sosi;
out_siso : in t_dp_siso
);
@@ -97,7 +99,8 @@ architecture str of dp_block_from_mm_dc is
signal mm_sync_hi : std_logic := '0';
signal mm_sync_level : std_logic := '0';
signal mm_sync : std_logic := '0';
- signal mm_done : std_logic := '0'; -- not used, instead use out_sop
+ -- not used, instead use out_sop
+ signal mm_done : std_logic := '0';
signal mm_bsn_at_sync : std_logic_vector(g_bsn_w - 1 downto 0) := (others => '0');
signal start_address_slv : std_logic_vector(c_start_addr_w - 1 downto 0) := (others => '0');
signal mm_start_address_slv : std_logic_vector(c_start_addr_w - 1 downto 0) := (others => '0');
@@ -152,7 +155,8 @@ begin
end if;
end process;
- mm_sync <= mm_sync_level and mm_start_pulse; -- synchronous with mm_start_pulse
+ -- synchronous with mm_start_pulse
+ mm_sync <= mm_sync_level and mm_start_pulse;
start_address_slv <= TO_UVEC(start_address, c_start_addr_w);
mm_start_address <= TO_UINT(mm_start_address_slv);
@@ -221,7 +225,8 @@ begin
sync_in => mm_sync,
bsn_at_sync => mm_bsn_at_sync,
start_address => mm_start_address,
- mm_done => mm_done, -- = mm_fifo_sosi.eop
+ -- = mm_fifo_sosi.eop
+ mm_done => mm_done,
mm_mosi => mm_mosi,
mm_miso => mm_miso,
out_sosi => mm_fifo_sosi,
diff --git a/libraries/base/dp/src/vhdl/dp_block_gen.vhd b/libraries/base/dp/src/vhdl/dp_block_gen.vhd
index a9f997127f73a8d6713931cab1ede931fe4f6546..9a508beed589f3dba67305bb572e30fc0a2351c9 100644
--- a/libraries/base/dp/src/vhdl/dp_block_gen.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_gen.vhd
@@ -70,8 +70,10 @@ use work.dp_stream_pkg.all;
entity dp_block_gen is
generic (
- g_use_src_in : boolean := true; -- when true use src_in.ready else use snk_in.valid for flow control
- g_nof_data : positive := 1; -- nof data per block
+ -- when true use src_in.ready else use snk_in.valid for flow control
+ g_use_src_in : boolean := true;
+ -- nof data per block
+ g_nof_data : positive := 1;
g_nof_blk_per_sync : positive := 8;
g_empty : natural := 0;
g_channel : natural := 0;
@@ -85,7 +87,8 @@ entity dp_block_gen is
rst : in std_logic;
clk : in std_logic;
-- Streaming sink
- snk_out : out t_dp_siso; -- pass on src_in.xon, pass on or force snk_out.ready dependend on g_use_src_in
+ -- pass on src_in.xon, pass on or force snk_out.ready dependend on g_use_src_in
+ snk_out : out t_dp_siso;
snk_in : in t_dp_sosi := c_dp_sosi_rst;
-- Streaming source
src_in : in t_dp_siso := c_dp_siso_rdy;
@@ -98,7 +101,8 @@ end dp_block_gen;
architecture rtl of dp_block_gen is
type t_state is (s_sop, s_data, s_eop);
- type t_reg is record -- local registers
+ -- local registers
+ type t_reg is record
state : t_state;
data_cnt : natural range 0 to g_nof_data;
blk_cnt : natural range 0 to g_nof_blk_per_sync;
@@ -114,8 +118,10 @@ architecture rtl of dp_block_gen is
signal r : t_reg;
signal nxt_r : t_reg;
begin
- snk_out.ready <= src_in.ready when g_use_src_in = true else '1'; -- force snk_out.ready = '1' when src_in.ready is not used
- snk_out.xon <= src_in.xon; -- always pass on siso.xon
+ -- force snk_out.ready = '1' when src_in.ready is not used
+ snk_out.ready <= src_in.ready when g_use_src_in = true else '1';
+ -- always pass on siso.xon
+ snk_out.xon <= src_in.xon;
src_out <= r.src_out;
@@ -160,18 +166,24 @@ begin
case r.state is
when s_sop =>
- nxt_r.data_cnt <= 0; -- for clarity init data count to 0 (because it will become 1 anyway at sop)
- if en = '0' then -- if disabled then reset block generator and remain in this state
+ -- for clarity init data count to 0 (because it will become 1 anyway at sop)
+ nxt_r.data_cnt <= 0;
+ -- if disabled then reset block generator and remain in this state
+ if en = '0' then
nxt_r.blk_cnt <= 0;
nxt_r.bsn <= TO_DP_BSN(g_bsn);
- else -- enabled block generator
- if ready = '1' then -- once enabled the complete block will be output dependent on the flow control
+ -- enabled block generator
+ else
+ -- once enabled the complete block will be output dependent on the flow control
+ if ready = '1' then
-- use input sync or create local sync
if g_preserve_sync = false then
if r.blk_cnt = 0 then
- nxt_r.src_out.sync <= '1'; -- use local sync for this block, local sync starts at first ready
+ -- use local sync for this block, local sync starts at first ready
+ nxt_r.src_out.sync <= '1';
end if;
- if r.blk_cnt >= g_nof_blk_per_sync - 1 then -- maintain local sync interval
+ -- maintain local sync interval
+ if r.blk_cnt >= g_nof_blk_per_sync - 1 then
nxt_r.blk_cnt <= 0;
else
nxt_r.blk_cnt <= r.blk_cnt + 1;
@@ -182,8 +194,10 @@ begin
-- use input bsn or create local bsn
if g_preserve_bsn = false then
- nxt_r.bsn <= INCR_UVEC(r.bsn, 1); -- increment local bsn for next block
- nxt_r.src_out.bsn <= r.bsn; -- use local bsn for this block
+ -- increment local bsn for next block
+ nxt_r.bsn <= INCR_UVEC(r.bsn, 1);
+ -- use local bsn for this block
+ nxt_r.src_out.bsn <= r.bsn;
end if;
-- use input channel or create fixed local channel
@@ -192,14 +206,17 @@ begin
end if;
if g_nof_data = 1 then
- nxt_r.src_out.eop <= '1'; -- single word block
+ -- single word block
+ nxt_r.src_out.eop <= '1';
nxt_r.src_out.empty <= TO_DP_EMPTY(g_empty);
nxt_r.src_out.err <= TO_DP_ERROR(g_error);
elsif g_nof_data = 2 then
- nxt_r.data_cnt <= 1; -- start of two word block
+ -- start of two word block
+ nxt_r.data_cnt <= 1;
nxt_r.state <= s_eop;
else
- nxt_r.data_cnt <= 1; -- start of multi word block
+ -- start of multi word block
+ nxt_r.data_cnt <= 1;
nxt_r.state <= s_data;
end if;
end if;
@@ -212,7 +229,8 @@ begin
nxt_r.state <= s_eop;
end if;
end if;
- when others => -- s_eop
+ -- s_eop
+ when others =>
if ready = '1' then
nxt_r.src_out.valid <= '1';
nxt_r.src_out.eop <= '1';
diff --git a/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd b/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
index 0abb80fa529abc405fd5e652a2418086253a1683..0d5b75a18fb81a5c15942340e358bb380d05b7d4 100644
--- a/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
@@ -149,7 +149,8 @@ entity dp_block_gen_valid_arr is
generic (
g_nof_streams : positive := 1;
g_nof_data_per_block : positive := 1;
- g_nof_blk_per_sync : positive := 8; -- Maximum nof blocks per sync period, e.g 7.3 becomes 8.
+ -- Maximum nof blocks per sync period, e.g 7.3 becomes 8.
+ g_nof_blk_per_sync : positive := 8;
g_check_input_sync : boolean := false;
g_nof_pages_bsn : natural := 0;
g_restore_global_bsn : boolean := false
@@ -158,12 +159,14 @@ entity dp_block_gen_valid_arr is
rst : in std_logic;
clk : in std_logic;
-- Streaming sink
- snk_in : in t_dp_sosi; -- = snk_in_arr(0)
+ -- = snk_in_arr(0)
+ snk_in : in t_dp_sosi;
snk_in_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-- Streaming source
src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-- Control
- enable : in std_logic := '1' -- can connect via MM or could also connect to a src_in.xon
+ -- can connect via MM or could also connect to a src_in.xon
+ enable : in std_logic := '1'
);
end dp_block_gen_valid_arr;
@@ -186,7 +189,8 @@ architecture rtl of dp_block_gen_valid_arr is
type t_state is (s_sop, s_data, s_eop);
- type t_reg is record -- local registers
+ -- local registers
+ type t_reg is record
state : t_state;
data_cnt : natural range 0 to g_nof_data_per_block;
blk_cnt : natural range 0 to g_nof_blk_per_sync;
@@ -261,11 +265,16 @@ begin
case r.state is
when s_sop =>
- nxt_r.data_cnt <= 0; -- For clarity init data count to 0 (because it will become 1 anyway at sop)
- if enable = '0' then -- Check enable in state s_sop to ensure that disable cannot happen during a block
- nxt_r.blk_cnt <= 0; -- If disabled then reset block generator and remain in this state
- else -- Enabled block generator
- if snk_in.valid = '1' then -- Once enabled the complete block will be output dependent on the input valid
+ -- For clarity init data count to 0 (because it will become 1 anyway at sop)
+ nxt_r.data_cnt <= 0;
+ -- Check enable in state s_sop to ensure that disable cannot happen during a block
+ if enable = '0' then
+ -- If disabled then reset block generator and remain in this state
+ nxt_r.blk_cnt <= 0;
+ -- Enabled block generator
+ else
+ -- Once enabled the complete block will be output dependent on the input valid
+ if snk_in.valid = '1' then
-- maintain blk_cnt for output sync interval, the blk_cnt is the local bsn that wraps at every sync
if r.blk_cnt >= g_nof_blk_per_sync - 1 then
nxt_r.blk_cnt <= 0;
@@ -276,20 +285,26 @@ begin
end if;
-- create local sync and pass on input bsn at local sync
- if r.blk_cnt = 0 or (g_check_input_sync and snk_in.sync = '1') then -- output sync starts at first input valid
- nxt_r.reg_sosi.sync <= '1'; -- output sync for this block
- nxt_r.reg_sosi.bsn <= in_sosi.bsn; -- output input bsn at sync
+ -- output sync starts at first input valid
+ if r.blk_cnt = 0 or (g_check_input_sync and snk_in.sync = '1') then
+ -- output sync for this block
+ nxt_r.reg_sosi.sync <= '1';
+ -- output input bsn at sync
+ nxt_r.reg_sosi.bsn <= in_sosi.bsn;
else
- nxt_r.reg_sosi.bsn <= TO_DP_BSN(r.blk_cnt); -- output local bsn for the subsequent blocks
+ -- output local bsn for the subsequent blocks
+ nxt_r.reg_sosi.bsn <= TO_DP_BSN(r.blk_cnt);
end if;
nxt_r.reg_sosi.valid <= '1';
nxt_r.reg_sosi.sop <= '1';
if g_nof_data_per_block = 1 then
- nxt_r.reg_sosi.eop <= '1'; -- single word block
+ -- single word block
+ nxt_r.reg_sosi.eop <= '1';
else
- nxt_r.data_cnt <= 1; -- start of multi word block
+ -- start of multi word block
+ nxt_r.data_cnt <= 1;
nxt_r.state <= s_data;
end if;
@@ -297,12 +312,15 @@ begin
if g_check_input_sync = true then
if r.blk_cnt = 0 then
if snk_in.sync = '0' then
- nxt_r.reg_sosi.valid <= '0'; -- undo all ctrl preparations for the new block
+ -- undo all ctrl preparations for the new block
+ nxt_r.reg_sosi.valid <= '0';
nxt_r.reg_sosi.sop <= '0';
nxt_r.reg_sosi.eop <= '0';
nxt_r.reg_sosi.sync <= '0';
- nxt_r.blk_cnt <= 0; -- restart blk_cnt
- nxt_r.state <= s_sop; -- remain in this state and wait for snk_in.sync
+ -- restart blk_cnt
+ nxt_r.blk_cnt <= 0;
+ -- remain in this state and wait for snk_in.sync
+ nxt_r.state <= s_sop;
end if;
end if;
end if;
@@ -316,7 +334,8 @@ begin
nxt_r.state <= s_eop;
end if;
end if;
- when others => -- s_eop
+ -- s_eop
+ when others =>
if snk_in.valid = '1' then
nxt_r.reg_sosi.valid <= '1';
nxt_r.reg_sosi.eop <= '1';
@@ -334,7 +353,8 @@ begin
u_dp_bsn_restore_global : entity work.dp_bsn_restore_global
generic map (
g_bsn_w => c_dp_stream_bsn_w,
- g_pipeline => 0 -- pipeline registering is done via nxt_src_out_arr
+ -- pipeline registering is done via nxt_src_out_arr
+ g_pipeline => 0
)
port map (
rst => rst,
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
index 5e1dce61c28cd8686f0af5b7fc9d5db06be4f3af..9fd4de2c22e41ef0000a6fd91a85453d796acdc7 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
@@ -79,10 +79,14 @@ use work.dp_stream_pkg.all;
entity dp_block_reshape is
generic (
- g_input_nof_data_per_sync : natural := 2; -- nof data per input sync interval, used only for sop_index
- g_reshape_nof_data_per_blk : natural := 2; -- nof data per output block
- g_pipeline_src_out : natural := 1; -- Pipeline source outputs (all sosi)
- g_pipeline_src_in : natural := 0 -- Pipeline source inputs (all siso). This will also pipeline src_out.
+ -- nof data per input sync interval, used only for sop_index
+ g_input_nof_data_per_sync : natural := 2;
+ -- nof data per output block
+ g_reshape_nof_data_per_blk : natural := 2;
+ -- Pipeline source outputs (all sosi)
+ g_pipeline_src_out : natural := 1;
+ -- Pipeline source inputs (all siso). This will also pipeline src_out.
+ g_pipeline_src_in : natural := 0
);
port (
clk : in std_logic;
@@ -93,12 +97,14 @@ entity dp_block_reshape is
src_out : out t_dp_sosi;
src_in : in t_dp_siso := c_dp_siso_rdy;
- src_index_arr : out t_natural_arr(1 downto 0) -- [1] sop index, [0] valid index
+ -- [1] sop index, [0] valid index
+ src_index_arr : out t_natural_arr(1 downto 0)
);
end dp_block_reshape;
architecture str of dp_block_reshape is
- constant c_nof_counters : natural := 2; -- counter [0] is used for block reshape and valid index,
+ -- counter [0] is used for block reshape and valid index,
+ constant c_nof_counters : natural := 2;
-- counter [1] is only used for sop_index
constant c_nof_block_per_sync : natural := sel_a_b(g_input_nof_data_per_sync > g_reshape_nof_data_per_blk,
g_input_nof_data_per_sync / g_reshape_nof_data_per_blk, 1);
@@ -132,8 +138,10 @@ begin
count_src_out_arr => cnt_sosi_arr
);
- src_index_arr(1) <= TO_UINT(cnt_sosi_arr(1).data); -- sop index
- src_index_arr(0) <= TO_UINT(cnt_sosi_arr(0).data); -- valid index
+ -- sop index
+ src_index_arr(1) <= TO_UINT(cnt_sosi_arr(1).data);
+ -- valid index
+ src_index_arr(0) <= TO_UINT(cnt_sosi_arr(0).data);
p_wire : process(input_src_out, cnt_sosi_arr)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
index d0d7039eca77f37147710560ded3f457982c4f40..10712fbe9f64f0b208e6a562eb19f77ad7512370 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
@@ -40,12 +40,18 @@ use work.dp_stream_pkg.all;
entity dp_block_reshape_arr is
generic (
- g_nof_streams : natural := 1; -- nof streams
- g_shared_control : boolean := false; -- when TRUE then use snk_in_arr(0) for control, else use per snk_in_arr stream
- g_input_nof_data_per_sync : natural := 2; -- nof data per input sync interval, used only for sop_index
- g_reshape_nof_data_per_blk : natural := 2; -- nof data per output block
- g_pipeline_src_out : natural := 1; -- Pipeline source outputs (all sosi)
- g_pipeline_src_in : natural := 0 -- Pipeline source inputs (all siso). This will also pipeline src_out.
+ -- nof streams
+ g_nof_streams : natural := 1;
+ -- when TRUE then use snk_in_arr(0) for control, else use per snk_in_arr stream
+ g_shared_control : boolean := false;
+ -- nof data per input sync interval, used only for sop_index
+ g_input_nof_data_per_sync : natural := 2;
+ -- nof data per output block
+ g_reshape_nof_data_per_blk : natural := 2;
+ -- Pipeline source outputs (all sosi)
+ g_pipeline_src_out : natural := 1;
+ -- Pipeline source inputs (all siso). This will also pipeline src_out.
+ g_pipeline_src_in : natural := 0
);
port (
clk : in std_logic;
@@ -56,7 +62,8 @@ entity dp_block_reshape_arr is
src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0);
src_in_arr : in t_dp_siso_arr(g_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
- src_index_2arr_2 : out t_natural_2arr_2(g_nof_streams - 1 downto 0) -- [1] sop index, [0] valid index per stream
+ -- [1] sop index, [0] valid index per stream
+ src_index_2arr_2 : out t_natural_2arr_2(g_nof_streams - 1 downto 0)
);
end dp_block_reshape_arr;
@@ -70,7 +77,8 @@ architecture str of dp_block_reshape_arr is
signal out_sosi : t_dp_sosi;
signal out_siso : t_dp_siso;
- signal out_index_2arr_2 : t_natural_2arr_2(g_nof_streams - 1 downto 0); -- [1] sop index, [0] valid index per stream
+ -- [1] sop index, [0] valid index per stream
+ signal out_index_2arr_2 : t_natural_2arr_2(g_nof_streams - 1 downto 0);
begin
-- Dependent on g_shared_control use stream(0) to control all streams or use separate control per stream
in_sosi <= snk_in_arr(0);
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
index 2934cf719e37345e6970b6e9ab2353f0db9fd976..5cff04ac7c798ca848e10e1d41f65c28377bc169 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
@@ -72,12 +72,18 @@ use work.dp_stream_pkg.all;
entity dp_block_reshape_sync is
generic (
- g_input_nof_data_per_sync : natural := 0; -- nof data per input sync interval, used only for sync_index
- g_reshape_nof_data_per_blk : natural := 8; -- nof data per output block
- g_reshape_nof_blk_per_sync : natural := 12; -- nof blocks per output sync interval
- g_reshape_bsn : boolean := false; -- when TRUE reshape BSN else when FALSE pass on BSN
- g_pipeline_src_out : natural := 1; -- Pipeline source outputs (data,valid,sop,eop etc)
- g_pipeline_src_in : natural := 0 -- Pipeline source inputs (ready,xon). This will also pipeline src_out.
+ -- nof data per input sync interval, used only for sync_index
+ g_input_nof_data_per_sync : natural := 0;
+ -- nof data per output block
+ g_reshape_nof_data_per_blk : natural := 8;
+ -- nof blocks per output sync interval
+ g_reshape_nof_blk_per_sync : natural := 12;
+ -- when TRUE reshape BSN else when FALSE pass on BSN
+ g_reshape_bsn : boolean := false;
+ -- Pipeline source outputs (data,valid,sop,eop etc)
+ g_pipeline_src_out : natural := 1;
+ -- Pipeline source inputs (ready,xon). This will also pipeline src_out.
+ g_pipeline_src_in : natural := 0
);
port (
clk : in std_logic;
@@ -88,7 +94,8 @@ entity dp_block_reshape_sync is
src_out : out t_dp_sosi;
src_in : in t_dp_siso := c_dp_siso_rdy;
- src_index_arr : out t_natural_arr(2 downto 0) -- [2] = sync index, [1] sop index, [0] valid index
+ -- [2] = sync index, [1] sop index, [0] valid index
+ src_index_arr : out t_natural_arr(2 downto 0)
);
end dp_block_reshape_sync;
@@ -159,7 +166,8 @@ begin
sop_index <= TO_UINT(cnt_sosi_arr(1).data);
valid_index <= TO_UINT(cnt_sosi_arr(0).data);
- src_index_arr(2) <= sync_index; -- default 0, counting if c_nof_output_sync_per_input_sync > 1
+ -- default 0, counting if c_nof_output_sync_per_input_sync > 1
+ src_index_arr(2) <= sync_index;
src_index_arr(1) <= sop_index;
src_index_arr(0) <= valid_index;
diff --git a/libraries/base/dp/src/vhdl/dp_block_resize.vhd b/libraries/base/dp/src/vhdl/dp_block_resize.vhd
index db89a827502ab817b05dbe32f386bf4a6b1f0b75..6b2776d17331531a4b2154e15becafb63baf2308 100644
--- a/libraries/base/dp/src/vhdl/dp_block_resize.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_resize.vhd
@@ -46,8 +46,10 @@ use work.dp_stream_pkg.all;
entity dp_block_resize is
generic (
g_input_block_size : natural := 256;
- g_out_sop_index : natural := 0; -- >= 0
- g_out_eop_index : natural := 255 -- >= g_out_sop_index and < g_input_block_size
+ -- >= 0
+ g_out_sop_index : natural := 0;
+ -- >= g_out_sop_index and < g_input_block_size
+ g_out_eop_index : natural := 255
);
port (
rst : in std_logic;
@@ -127,7 +129,8 @@ begin
-- Register block_sosi to easy timing closure
u_pipeline : entity work.dp_pipeline
generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline => 1
)
port map (
rst => rst,
diff --git a/libraries/base/dp/src/vhdl/dp_block_select.vhd b/libraries/base/dp/src/vhdl/dp_block_select.vhd
index 773adcfb0d7a252de34f76baf399f7701a04fd35..4745d88cdbb035b08603236e7a8cf66ee3842566 100644
--- a/libraries/base/dp/src/vhdl/dp_block_select.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_select.vhd
@@ -80,8 +80,10 @@ use work.dp_stream_pkg.all;
architecture rtl of dp_block_select is
signal cnt_reg : natural range 0 to true_log_pow2(g_nof_blocks_per_sync);
signal cnt : natural;
- signal sync_sosi_reg : t_dp_sosi; -- hold snk_in.bsn
- signal sync_sosi : t_dp_sosi; -- hold snk_in.bsn
+ -- hold snk_in.bsn
+ signal sync_sosi_reg : t_dp_sosi;
+ -- hold snk_in.bsn
+ signal sync_sosi : t_dp_sosi;
signal block_sosi : t_dp_sosi;
begin
p_clk : process(rst, clk)
@@ -132,7 +134,8 @@ begin
-- Move input sync and bsn to first output block
if cnt = index_lo then
block_sosi.sync <= snk_in.sop;
- block_sosi.bsn <= sync_sosi.bsn; -- bsn is valid at sop
+ -- bsn is valid at sop
+ block_sosi.bsn <= sync_sosi.bsn;
end if;
end if;
end if;
@@ -141,7 +144,8 @@ begin
-- Register block_sosi to easy timing closure
u_pipeline : entity work.dp_pipeline
generic map (
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline => g_pipeline
)
port map (
rst => rst,
diff --git a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
index 0c1cb305606823ade252d499f0f6e54719c9547b..aaaa748e0ca69e20ce8876265a301736f1a89e2f 100644
--- a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
@@ -66,7 +66,8 @@ begin
p_mm_mosi : process(address, in_sosi, d)
begin
- mm_mosi <= c_mem_mosi_rst; -- default to avoid ** Warning: (vsim-8684) No drivers exist on out port mm_mosi.rd
+ -- default to avoid ** Warning: (vsim-8684) No drivers exist on out port mm_mosi.rd
+ mm_mosi <= c_mem_mosi_rst;
mm_mosi.address <= TO_MEM_ADDRESS(address);
mm_mosi.wrdata <= RESIZE_MEM_DATA(in_sosi.data);
mm_mosi.wr <= d.wr;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
index a9a587e8e43db9ad4f0e69d1abf47775d610c930..a1ca0037559f2217ae5c49788c4bdfa7a7a62301 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
@@ -95,8 +95,10 @@ architecture rtl of dp_block_validate_bsn_at_sync is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs, -- total counter + discarded counter
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
+ -- total counter + discarded counter
+ nof_dat => c_nof_regs,
init_sl => '0');
-- Registers in st_clk domain
@@ -183,8 +185,10 @@ begin
-- MM registers in st_clk domain
reg_wr_arr => OPEN,
reg_rd_arr => OPEN,
- in_reg => count_reg, -- read only
- out_reg => open -- no write
+ -- read only
+ in_reg => count_reg,
+ -- no write
+ out_reg => open
);
-- Process to check the bsn at sync. It captures the bsn at the sync of bs_sosi. Then compares that bsn to
@@ -224,11 +228,14 @@ begin
end if;
else
if in_sosi.sop = '1' then
- out_valid <= '1'; -- Packets with channel unequal to g_check_channel are always valid
+ -- Packets with channel unequal to g_check_channel are always valid
+ out_valid <= '1';
end if;
end if;
- bsn_ok <= v_bsn_ok; -- bsn_ok is used to indicate if the bsn is correct for the entire sync period of g_check_channel.
- bsn_at_sync <= v_bsn_at_sync; -- register to store the bsn at sync of bs_sosi.
+ -- bsn_ok is used to indicate if the bsn is correct for the entire sync period of g_check_channel.
+ bsn_ok <= v_bsn_ok;
+ -- register to store the bsn at sync of bs_sosi.
+ bsn_at_sync <= v_bsn_at_sync;
end process;
p_dp_clk : process(dp_rst, dp_clk)
@@ -255,7 +262,8 @@ begin
u_pipeline : entity work.dp_pipeline
generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline => 1
)
port map (
rst => dp_rst,
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
index 32c4a07830c6a5f317ef2d24be6d37f6d5332ca0..7b6d23df79b3d5b5bae95e0a9806238c7baaa170 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
@@ -40,7 +40,8 @@ use common_lib.common_mem_pkg.all;
entity dp_block_validate_channel is
generic (
- g_mode : string := "=" -- can be "=", "<", ">"
+ -- can be "=", "<", ">"
+ g_mode : string := "="
);
port (
dp_rst : in std_logic;
@@ -63,15 +64,18 @@ architecture rtl of dp_block_validate_channel is
signal keep_sosi : t_dp_sosi;
begin
assert g_mode = "=" or g_mode = "<" or g_mode = ">" report "g_mode must be one of three options: '=', '<' or '>'" severity ERROR;
- gen_equal : if g_mode = "=" generate -- remove all blocks with ch = remove_channel
+ -- remove all blocks with ch = remove_channel
+ gen_equal : if g_mode = "=" generate
remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
'1' when unsigned(in_sosi.channel) = unsigned(remove_channel) else '0';
end generate;
- gen_smaller : if g_mode = "<" generate -- remove all blocks with ch < remove_channel
+ -- remove all blocks with ch < remove_channel
+ gen_smaller : if g_mode = "<" generate
remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
'1' when unsigned(in_sosi.channel) < unsigned(remove_channel) else '0';
end generate;
- gen_larger : if g_mode = ">" generate -- remove all blocks with ch > remove_channel
+ -- remove all blocks with ch > remove_channel
+ gen_larger : if g_mode = ">" generate
remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
'1' when unsigned(in_sosi.channel) > unsigned(remove_channel) else '0';
end generate;
@@ -103,7 +107,8 @@ begin
u_pipe_remove : entity work.dp_pipeline
generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline => 1
)
port map (
rst => dp_rst,
@@ -116,7 +121,8 @@ begin
u_pipe_keep : entity work.dp_pipeline
generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline => 1
)
port map (
rst => dp_rst,
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
index 96b89286a11c2ef375bd06a7eb2b0189f41ebf85..a5a157bee83981e353992789fe0ac3ac7e44f96e 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
@@ -80,13 +80,18 @@ use common_lib.common_mem_pkg.all;
entity dp_block_validate_err is
generic (
- g_cnt_w : natural := c_word_w; -- max is c_word_w due to mm word width
- g_blk_cnt_w : natural := c_longword_w; -- max is c_longword_w due to two mm word width
- g_max_block_size : positive := 250; -- largest possible incoming block size.
- g_min_block_size : positive := 1; -- smallest possible incoming block size.
+ -- max is c_word_w due to mm word width
+ g_cnt_w : natural := c_word_w;
+ -- max is c_longword_w due to two mm word width
+ g_blk_cnt_w : natural := c_longword_w;
+ -- largest possible incoming block size.
+ g_max_block_size : positive := 250;
+ -- smallest possible incoming block size.
+ g_min_block_size : positive := 1;
g_nof_err_counts : natural := 8;
-- fifo generics
- g_fifo_size : positive := 256; -- fifo size to buffer incoming blocks, should be >= g_max_block_size
+ -- fifo size to buffer incoming blocks, should be >= g_max_block_size
+ g_fifo_size : positive := 256;
g_data_w : natural := 16;
g_bsn_w : natural := 1;
g_empty_w : natural := 1;
@@ -128,7 +133,8 @@ architecture rtl of dp_block_validate_err is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_nof_regs,
init_sl => '0');
@@ -259,13 +265,17 @@ begin
count_reg((g_nof_err_counts + 1) * c_word_w - 1 downto g_nof_err_counts * c_word_w ) <= RESIZE_UVEC(hold_cnt_discarded, c_word_w);
gen_blk_cnt_32b : if g_blk_cnt_w <= c_word_w generate
- count_reg((g_nof_err_counts + 2) * c_word_w - 1 downto (g_nof_err_counts + 1) * c_word_w ) <= RESIZE_UVEC(hold_cnt_blk, c_word_w); -- low part
- count_reg((g_nof_err_counts + 3) * c_word_w - 1 downto (g_nof_err_counts + 2) * c_word_w ) <= (others => '0'); -- high part (not used)
+ -- low part
+ count_reg((g_nof_err_counts + 2) * c_word_w - 1 downto (g_nof_err_counts + 1) * c_word_w ) <= RESIZE_UVEC(hold_cnt_blk, c_word_w);
+ -- high part (not used)
+ count_reg((g_nof_err_counts + 3) * c_word_w - 1 downto (g_nof_err_counts + 2) * c_word_w ) <= (others => '0');
end generate;
gen_blk_cnt_64b : if g_blk_cnt_w > c_word_w generate
- count_reg((g_nof_err_counts + 2) * c_word_w - 1 downto (g_nof_err_counts + 1) * c_word_w ) <= hold_cnt_blk(c_word_w - 1 downto 0); -- low part
- count_reg((g_nof_err_counts + 3) * c_word_w - 1 downto (g_nof_err_counts + 2) * c_word_w ) <= RESIZE_UVEC(hold_cnt_blk(g_blk_cnt_w - 1 downto c_word_w), c_word_w); -- high part
+ -- low part
+ count_reg((g_nof_err_counts + 2) * c_word_w - 1 downto (g_nof_err_counts + 1) * c_word_w ) <= hold_cnt_blk(c_word_w - 1 downto 0);
+ -- high part
+ count_reg((g_nof_err_counts + 3) * c_word_w - 1 downto (g_nof_err_counts + 2) * c_word_w ) <= RESIZE_UVEC(hold_cnt_blk(g_blk_cnt_w - 1 downto c_word_w), c_word_w);
end generate;
u_reg : entity common_lib.common_reg_r_w_dc
@@ -288,8 +298,10 @@ begin
-- MM registers in st_clk domain
reg_wr_arr => OPEN,
reg_rd_arr => OPEN,
- in_reg => count_reg, -- read only
- out_reg => open -- no write
+ -- read only
+ in_reg => count_reg,
+ -- no write
+ out_reg => open
);
u_fifo_fill_eop : entity work.dp_fifo_fill_eop
@@ -322,7 +334,8 @@ begin
u_pipeline : entity work.dp_pipeline
generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline => 1
)
port map (
rst => dp_rst,
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
index d523cc1506b921a52ff9e8f18b7ad7ee970946b8..c90fc26e74cb7a03081096bfc071bf15550d13b4 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
@@ -48,7 +48,8 @@ use work.dp_stream_pkg.all;
entity dp_block_validate_length is
generic (
- g_err_bi : natural := 0; -- bit index in error field
+ -- bit index in error field
+ g_err_bi : natural := 0;
g_expected_length : natural := 255
);
port (
@@ -112,7 +113,8 @@ begin
-- Register block_sosi to easy timing closure
u_pipeline : entity work.dp_pipeline
generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline => 1
)
port map (
rst => rst,
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
index f8c6daeaf27d4dc1e0a86bd3b0f4d462fa7e7f8f..25ee82c5227838175139d1fc7460b676f39aa699 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
@@ -135,13 +135,19 @@ use work.dp_stream_pkg.all;
entity dp_bsn_align is
generic (
- g_block_size : natural := 32; -- > 1, g_block_size=1 is not supported, g_block_size <= g_block_period
- g_block_period : natural := 256; -- number of clock cycles per block period or block interval (not used in the architecture, used in the comment only)
- g_nof_input : natural := 2; -- >= 1
- g_xoff_timeout : natural := 1536; -- e.g. g_bsn_latency * 2 * g_block_period
- g_sop_timeout : natural := 1024; -- e.g. (g_bsn_latency + 1) * g_block_period
+ -- > 1, g_block_size=1 is not supported, g_block_size <= g_block_period
+ g_block_size : natural := 32;
+ -- number of clock cycles per block period or block interval (not used in the architecture, used in the comment only)
+ g_block_period : natural := 256;
+ -- >= 1
+ g_nof_input : natural := 2;
+ -- e.g. g_bsn_latency * 2 * g_block_period
+ g_xoff_timeout : natural := 1536;
+ -- e.g. (g_bsn_latency + 1) * g_block_period
+ g_sop_timeout : natural := 1024;
g_bsn_latency : natural := 3;
- g_bsn_request_pipeline : natural := 2 -- = 1, 2, ..., c_bsn_nof_stages, requested total pipelining of the BSN max and BSN min operation
+ -- = 1, 2, ..., c_bsn_nof_stages, requested total pipelining of the BSN max and BSN min operation
+ g_bsn_request_pipeline : natural := 2
);
port (
rst : in std_logic;
@@ -150,11 +156,14 @@ entity dp_bsn_align is
snk_out_arr : out t_dp_siso_arr(g_nof_input - 1 downto 0);
snk_in_arr : in t_dp_sosi_arr(g_nof_input - 1 downto 0);
-- ST source
- src_in_arr : in t_dp_siso_arr(g_nof_input - 1 downto 0) := (others => c_dp_siso_rdy); -- only src_in_arr(0) is used for src_out flow control because all src_out need to stay aligned
+ -- only src_in_arr(0) is used for src_out flow control because all src_out need to stay aligned
+ src_in_arr : in t_dp_siso_arr(g_nof_input - 1 downto 0) := (others => c_dp_siso_rdy);
src_out_arr : out t_dp_sosi_arr(g_nof_input - 1 downto 0);
-- MM
- in_en_evt : in std_logic := '0'; -- pulse '1' indicates that the in_en_arr user input enables have been updated
- in_en_arr : in std_logic_vector(g_nof_input - 1 downto 0) := (others => '1') -- default all user inputs are enabled
+ -- pulse '1' indicates that the in_en_arr user input enables have been updated
+ in_en_evt : in std_logic := '0';
+ -- default all user inputs are enabled
+ in_en_arr : in std_logic_vector(g_nof_input - 1 downto 0) := (others => '1')
);
end dp_bsn_align;
@@ -171,17 +180,21 @@ architecture rtl of dp_bsn_align is
-- . Use g_bsn_request_pipeline=1 for fastest alignment detection with only 1 cycle lost
-- . Use g_bsn_request_pipeline>1 to more easily achieve timing closure at expense of more cycles lost
-- . The maximum g_bsn_request_pipeline = c_bsn_nof_stages provided that there is sufficient data not valid gap between the input packets to allow for these lost cycles
- constant c_bsn_nof_stages : natural := ceil_log2(g_nof_input); -- = nof operation stages for determining max BSN and min BSN
- constant c_bsn_stage_pipeline : natural := 1; -- = fixed 1, always use at least one register
+ -- = nof operation stages for determining max BSN and min BSN
+ constant c_bsn_nof_stages : natural := ceil_log2(g_nof_input);
+ -- = fixed 1, always use at least one register
+ constant c_bsn_stage_pipeline : natural := 1;
constant c_bsn_request_pipeline : natural := smallest(c_bsn_nof_stages, g_bsn_request_pipeline);
constant c_bsn_stage_pipeline_mod : natural := c_bsn_nof_stages / c_bsn_request_pipeline;
- constant c_bsn_actual_pipeline : natural := c_bsn_nof_stages / c_bsn_stage_pipeline_mod; -- = 1, 2, ..., c_bsn_nof_stages, actual nof operation stages that will get a register
+ -- = 1, 2, ..., c_bsn_nof_stages, actual nof operation stages that will get a register
+ constant c_bsn_actual_pipeline : natural := c_bsn_nof_stages / c_bsn_stage_pipeline_mod;
type t_state is (s_xoff, s_align, s_data);
-- Define the local registers in t_reg record to more clearly show the single registered process, conform the two process method of Gaisler. However
-- still do use multiple combinatorial processes, instead of the only one combinatiorial process of the Gaisler method that uses variables.
- type t_reg is record -- local registers
+ -- local registers
+ type t_reg is record
in_en_arr : std_logic_vector(g_nof_input - 1 downto 0);
timeout_cnt : std_logic_vector(c_timeout_w - 1 downto 0);
pend_sop_all : std_logic_vector(c_bsn_actual_pipeline-1 downto 0);
@@ -220,7 +233,8 @@ begin
snk_out_arr <= i_snk_out_arr;
src_out_arr <= r.src_out_arr;
- src_in <= src_in_arr(0); -- all src_in_arr are identical, so use element (0)
+ -- all src_in_arr are identical, so use element (0)
+ src_in <= src_in_arr(0);
p_clk: process(clk, rst)
begin
@@ -271,7 +285,8 @@ begin
rst => rst,
clk => clk,
-- ST sink
- snk_out => blk_siso, -- wired blk_siso = hold_blk_in
+ -- wired blk_siso = hold_blk_in
+ snk_out => blk_siso,
snk_in => blk_sosi,
-- ST source
src_in => hold_blk_in,
@@ -318,7 +333,8 @@ begin
begin
for I in g_nof_input - 1 downto 0 loop
pend_bsn_vec((I + 1) * c_bsn_align_w - 1 downto I * c_bsn_align_w) <= pend_src_buf_arr(I).bsn(c_bsn_align_w - 1 downto 0);
- pend_bsn_arr(I) <= TO_UINT(pend_src_buf_arr(I).bsn(c_bsn_align_w - 1 downto 0)); -- for debugging purposes in wave window
+ -- for debugging purposes in wave window
+ pend_bsn_arr(I) <= TO_UINT(pend_src_buf_arr(I).bsn(c_bsn_align_w - 1 downto 0));
end loop;
end process;
@@ -328,8 +344,10 @@ begin
generic map (
g_operation => "MAX",
g_representation => "UNSIGNED",
- g_pipeline => c_bsn_stage_pipeline, -- amount of output pipelining per stage
- g_pipeline_mod => c_bsn_stage_pipeline_mod, -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
+ -- amount of output pipelining per stage
+ g_pipeline => c_bsn_stage_pipeline,
+ -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
+ g_pipeline_mod => c_bsn_stage_pipeline_mod,
g_nof_inputs => g_nof_input,
g_dat_w => c_bsn_align_w
)
@@ -346,8 +364,10 @@ begin
generic map (
g_operation => "MIN",
g_representation => "UNSIGNED",
- g_pipeline => c_bsn_stage_pipeline, -- amount of output pipelining per stage
- g_pipeline_mod => c_bsn_stage_pipeline_mod, -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
+ -- amount of output pipelining per stage
+ g_pipeline => c_bsn_stage_pipeline,
+ -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
+ g_pipeline_mod => c_bsn_stage_pipeline_mod,
g_nof_inputs => g_nof_input,
g_dat_w => c_bsn_align_w
)
@@ -367,14 +387,17 @@ begin
variable v_siso_arr_rdy : t_dp_siso_arr(g_nof_input - 1 downto 0);
variable v_siso_arr_flush : t_dp_siso_arr(g_nof_input - 1 downto 0);
variable v_siso_arr_src : t_dp_siso_arr(g_nof_input - 1 downto 0);
- variable v_sosi_arr : t_dp_sosi_arr(g_nof_input - 1 downto 0); -- auxiliary sosi variable
- variable v_blk_buf : t_dp_sosi; -- auxiliary sosi variable
+ -- auxiliary sosi variable
+ variable v_sosi_arr : t_dp_sosi_arr(g_nof_input - 1 downto 0);
+ -- auxiliary sosi variable
+ variable v_blk_buf : t_dp_sosi;
constant c_init_all_zeros : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0) := array_init('0', c_dp_stream_dsp_data_w);
begin
-- default semi-constant v_siso_arr controls taking account of the dynamic r.in_en_arr
v_siso_arr_hold := func_dp_stream_arr_select(r.in_en_arr, c_dp_siso_hold, c_dp_siso_flush);
v_siso_arr_rdy := func_dp_stream_arr_select(r.in_en_arr, c_dp_siso_rdy, c_dp_siso_flush);
- v_siso_arr_flush := func_dp_stream_arr_select(r.in_en_arr, c_dp_siso_flush, c_dp_siso_flush); -- = (OTHERS=>c_dp_siso_flush)
+ -- = (OTHERS=>c_dp_siso_flush)
+ v_siso_arr_flush := func_dp_stream_arr_select(r.in_en_arr, c_dp_siso_flush, c_dp_siso_flush);
v_siso_arr_src := func_dp_stream_arr_select(r.in_en_arr, src_in, c_dp_siso_flush);
-- assume if any input has a sync then all enabled inputs will have the sync
@@ -396,31 +419,38 @@ begin
hold_src_in_arr <= v_siso_arr_flush;
nxt_r.state <= r.state;
- nxt_r.src_out_arr <= func_dp_stream_arr_reset_control(r.src_out_arr); -- default hold sosi data and reset sosi control
+ -- default hold sosi data and reset sosi control
+ nxt_r.src_out_arr <= func_dp_stream_arr_reset_control(r.src_out_arr);
case r.state is
when s_xoff =>
- in_en_ack <= '1'; -- accept any in_en_arr updates
+ -- accept any in_en_arr updates
+ in_en_ack <= '1';
-- remain in s_xoff for g_xoff_timeout cycles
if unsigned(r.timeout_cnt) = g_xoff_timeout then
hold_blk_in <= c_dp_siso_rdy;
i_snk_out_arr <= v_siso_arr_rdy;
hold_src_in_arr <= v_siso_arr_rdy;
- blk_en <= '1'; -- enable reference block input
+ -- enable reference block input
+ blk_en <= '1';
nxt_r.state <= s_align;
else
nxt_r.timeout_cnt <= INCR_UVEC(r.timeout_cnt, 1);
end if;
when s_align =>
- blk_en <= '1'; -- keep reference block input enabled
+ -- keep reference block input enabled
+ blk_en <= '1';
- hold_blk_in <= c_dp_siso_hold; -- the reference block sop is already there, because blk_siso.ready was '1' in previous state and dp_block_gen can always deliver valid data
- i_snk_out_arr <= v_siso_arr_rdy; -- wait for sop at the user inputs and then hold the sop of the enabled user inputs
+ -- the reference block sop is already there, because blk_siso.ready was '1' in previous state and dp_block_gen can always deliver valid data
+ hold_blk_in <= c_dp_siso_hold;
+ -- wait for sop at the user inputs and then hold the sop of the enabled user inputs
+ i_snk_out_arr <= v_siso_arr_rdy;
hold_src_in_arr <= v_siso_arr_hold;
for I in g_nof_input - 1 downto 0 loop
if pend_src_buf_arr(I).sop = '1' then
- i_snk_out_arr(I) <= c_dp_siso_hold; -- flush user input until sop, then stop further input and hold this sosi
+ -- flush user input until sop, then stop further input and hold this sosi
+ i_snk_out_arr(I) <= c_dp_siso_hold;
end if;
end loop;
@@ -442,8 +472,10 @@ begin
v_sosi_arr := (others => c_dp_sosi_rst);
v_sosi_arr := func_dp_stream_arr_select(r.in_en_arr, next_src_buf_arr, v_sosi_arr);
v_sosi_arr := func_dp_stream_arr_set_control(v_sosi_arr, v_blk_buf);
- v_sosi_arr := func_dp_stream_arr_copy_valid_bsn(v_sosi_arr, r.in_en_arr); -- Copy the BSN of one of the valid streams to all other streams
- v_sosi_arr := func_dp_stream_set_data(v_sosi_arr, c_init_all_zeros, "ALL", r.in_en_arr); -- Fill the RE and IM fields of the disabled channels with ones.
+ -- Copy the BSN of one of the valid streams to all other streams
+ v_sosi_arr := func_dp_stream_arr_copy_valid_bsn(v_sosi_arr, r.in_en_arr);
+ -- Fill the RE and IM fields of the disabled channels with ones.
+ v_sosi_arr := func_dp_stream_set_data(v_sosi_arr, c_init_all_zeros, "ALL", r.in_en_arr);
nxt_r.src_out_arr <= v_sosi_arr;
-- <<< End of same code as in s_data
@@ -452,7 +484,8 @@ begin
-- bsn differ but are within alignment range
for I in g_nof_input - 1 downto 0 loop
if unsigned(pend_src_buf_arr(I).bsn(c_bsn_align_w - 1 downto 0)) < unsigned(pend_bsn_max) then
- i_snk_out_arr(I) <= c_dp_siso_rdy; -- flush the pending sop and remain in s_align to wait for the next sop, then stop further input and hold this sosi
+ -- flush the pending sop and remain in s_align to wait for the next sop, then stop further input and hold this sosi
+ i_snk_out_arr(I) <= c_dp_siso_rdy;
hold_src_in_arr(I) <= c_dp_siso_rdy;
end if;
end loop;
@@ -472,8 +505,10 @@ begin
nxt_r.state <= s_xoff;
end if;
- when others => -- s_data
- blk_en <= '1'; -- keep reference block input enabled
+ -- s_data
+ when others =>
+ -- keep reference block input enabled
+ blk_en <= '1';
-- let downstream flow control the enabled inputs
hold_blk_in <= src_in;
@@ -481,11 +516,16 @@ begin
hold_src_in_arr <= v_siso_arr_src;
-- output the aligned user input frames
- v_sosi_arr := (others => c_dp_sosi_rst); -- default force the sosi data of unused user inputs to 0
- v_sosi_arr := func_dp_stream_arr_select(r.in_en_arr, next_src_buf_arr, v_sosi_arr); -- output the pending input frame of all enabled user inputs
- v_sosi_arr := func_dp_stream_arr_set_control(v_sosi_arr, v_blk_buf); -- use the same reference block sosi control for all outputs
- v_sosi_arr := func_dp_stream_arr_copy_valid_bsn(v_sosi_arr, r.in_en_arr); -- Copy the BSN of one of the valid streams to all other streams
- v_sosi_arr := func_dp_stream_set_data(v_sosi_arr, c_init_all_zeros, "ALL", r.in_en_arr); -- Fill the RE and IM fields of the disabled channels with ones.
+ -- default force the sosi data of unused user inputs to 0
+ v_sosi_arr := (others => c_dp_sosi_rst);
+ -- output the pending input frame of all enabled user inputs
+ v_sosi_arr := func_dp_stream_arr_select(r.in_en_arr, next_src_buf_arr, v_sosi_arr);
+ -- use the same reference block sosi control for all outputs
+ v_sosi_arr := func_dp_stream_arr_set_control(v_sosi_arr, v_blk_buf);
+ -- Copy the BSN of one of the valid streams to all other streams
+ v_sosi_arr := func_dp_stream_arr_copy_valid_bsn(v_sosi_arr, r.in_en_arr);
+ -- Fill the RE and IM fields of the disabled channels with ones.
+ v_sosi_arr := func_dp_stream_set_data(v_sosi_arr, c_init_all_zeros, "ALL", r.in_en_arr);
nxt_r.src_out_arr <= v_sosi_arr;
-- at end of every block
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
index e2f93b3baf63e0f68a8f584f62748b3f2ab159ec..e8b7acc1bfcb42aaab15991c27f12bb2c954a8d4 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
@@ -47,21 +47,29 @@ use common_lib.common_mem_pkg.all;
entity dp_bsn_align_reg is
generic (
g_nof_input : positive := 3;
- g_cross_clock_domain : boolean := true -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
- out_en_evt : out std_logic; -- pulses when new enable data is available
+ -- pulses when new enable data is available
+ out_en_evt : out std_logic;
out_en_arr : out std_logic_vector
);
end dp_bsn_align_reg;
@@ -70,7 +78,8 @@ architecture str of dp_bsn_align_reg is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(g_nof_input),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => g_nof_input,
init_sl => '0');
@@ -78,7 +87,8 @@ architecture str of dp_bsn_align_reg is
constant c_reg_init : std_logic_vector(g_nof_input * c_word_w - 1 downto 0) := array_init(1, g_nof_input, c_word_w);
-- Registers in st_clk domain
- signal out_en_arr_reg : std_logic_vector(g_nof_input * c_word_w - 1 downto 0); -- := (OTHERS => '1');
+ -- := (OTHERS => '1');
+ signal out_en_arr_reg : std_logic_vector(g_nof_input * c_word_w - 1 downto 0);
signal reg_wr_arr : std_logic_vector(g_nof_input - 1 downto 0) := (others => '0');
begin
u_reg : entity common_lib.common_reg_r_w_dc
@@ -87,7 +97,8 @@ begin
g_in_new_latency => 1,
g_readback => true,
g_reg => c_mm_reg,
- g_init_reg => RESIZE_UVEC(c_reg_init, c_mem_reg_init_w) -- RESIZE_UVEC(TO_UVEC(1, c_word_w), c_mem_reg_init_w)
+ -- RESIZE_UVEC(TO_UVEC(1, c_word_w), c_mem_reg_init_w)
+ g_init_reg => RESIZE_UVEC(c_reg_init, c_mem_reg_init_w)
)
port map (
-- Clocks and reset
@@ -104,8 +115,10 @@ begin
reg_wr_arr => reg_wr_arr,
reg_rd_arr => OPEN,
in_new => OPEN,
- in_reg => out_en_arr_reg, -- read
- out_reg => out_en_arr_reg, -- write
+ -- read
+ in_reg => out_en_arr_reg,
+ -- write
+ out_reg => out_en_arr_reg,
out_new => out_en_evt
);
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
index 9042f050f7797b53fec3194857d70a0b6aac009c..f2876d1eb6dd414ea7e6467a9fb4d7ae4906c2b1 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
@@ -56,23 +56,35 @@ use work.dp_stream_pkg.all;
entity dp_bsn_align_v2 is
generic (
- g_nof_streams : natural := 2; -- >= 2, number of input and output streams
- g_bsn_latency_max : natural := 2; -- maximum travel latency of a remote block in number of block periods T_blk
- g_nof_aligners_max : positive := 16; -- 1 when only align at last node, > 1 when align at every intermediate node
- g_block_size : natural := 1024; -- > 1, g_block_size=1 is not supported
- g_bsn_w : natural := c_dp_stream_bsn_w; -- number of bits in sosi BSN
- g_data_w : natural := 36; -- number of bits in sosi data
- g_data_replacement_value : integer := 0; -- output sosi data value for missing input blocks
- g_use_mm_output : boolean := false; -- output via MM or via streaming DP
- g_pipeline_input : natural := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr
- g_pipeline_output : natural := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of out_sosi_arr
- g_rd_latency : natural := 2 -- 1 or 2, choose 2 to ease timing closure
+ -- >= 2, number of input and output streams
+ g_nof_streams : natural := 2;
+ -- maximum travel latency of a remote block in number of block periods T_blk
+ g_bsn_latency_max : natural := 2;
+ -- 1 when only align at last node, > 1 when align at every intermediate node
+ g_nof_aligners_max : positive := 16;
+ -- > 1, g_block_size=1 is not supported
+ g_block_size : natural := 1024;
+ -- number of bits in sosi BSN
+ g_bsn_w : natural := c_dp_stream_bsn_w;
+ -- number of bits in sosi data
+ g_data_w : natural := 36;
+ -- output sosi data value for missing input blocks
+ g_data_replacement_value : integer := 0;
+ -- output via MM or via streaming DP
+ g_use_mm_output : boolean := false;
+ -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr
+ g_pipeline_input : natural := 1;
+ -- >= 0, choose 0 for wires, choose 1 to ease timing closure of out_sosi_arr
+ g_pipeline_output : natural := 1;
+ -- 1 or 2, choose 2 to ease timing closure
+ g_rd_latency : natural := 2
);
port (
dp_rst : in std_logic;
dp_clk : in std_logic;
- node_index : in natural range 0 to g_nof_aligners_max - 1 := 0; -- only used when g_nof_aligners_max > 1
+ -- only used when g_nof_aligners_max > 1
+ node_index : in natural range 0 to g_nof_aligners_max - 1 := 0;
-- MM control
stream_en_arr : in std_logic_vector(g_nof_streams - 1 downto 0) := (others => '1');
@@ -82,8 +94,10 @@ entity dp_bsn_align_v2 is
in_sosi_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-- Output via local MM interface in dp_clk domain, when g_use_mm_output = TRUE.
- mm_sosi : out t_dp_sosi; -- streaming information that signals that an output block can be read
- mm_copi : in t_mem_copi := c_mem_copi_rst; -- read access to output block, all output streams share same mm_copi
+ -- streaming information that signals that an output block can be read
+ mm_sosi : out t_dp_sosi;
+ -- read access to output block, all output streams share same mm_copi
+ mm_copi : in t_mem_copi := c_mem_copi_rst;
mm_cipo_arr : out t_mem_cipo_arr(g_nof_streams - 1 downto 0);
-- Output via streaming DP interface, when g_use_mm_output = FALSE.
@@ -133,12 +147,16 @@ architecture rtl of dp_bsn_align_v2 is
mm_sosi : t_dp_sosi;
dp_sosi : t_dp_sosi;
-- p_read
- rd_blk_pointer : integer; -- use integer to detect need to wrap to natural
+ -- use integer to detect need to wrap to natural
+ rd_blk_pointer : integer;
rd_offset : std_logic_vector(c_ram_buf.adr_w - 1 downto 0);
rd_copi : t_mem_copi;
- fill_cipo_arr : t_mem_cipo_arr(g_nof_streams - 1 downto 0); -- used combinatorial to contain rd_cipo_arr from buffer or replacement data
- out_bsn : std_logic_vector(g_bsn_w - 1 downto 0); -- hold BSN until next sop, for easy view in Wave window
- out_channel_arr : t_channel_arr(g_nof_streams - 1 downto 0); -- hold channel until next sop per stream, for easy view in Wave window
+ -- used combinatorial to contain rd_cipo_arr from buffer or replacement data
+ fill_cipo_arr : t_mem_cipo_arr(g_nof_streams - 1 downto 0);
+ -- hold BSN until next sop, for easy view in Wave window
+ out_bsn : std_logic_vector(g_bsn_w - 1 downto 0);
+ -- hold channel until next sop per stream, for easy view in Wave window
+ out_channel_arr : t_channel_arr(g_nof_streams - 1 downto 0);
replace_cnt_en_arr : std_logic_vector(g_nof_streams - 1 downto 0);
end record;
@@ -231,11 +249,14 @@ begin
end process;
p_comb : process(r, in_sosi_arr_p, mm_copi, dp_copi, rd_cipo_arr, rd_sosi_arr, stream_en_arr, node_index)
- variable v : t_reg; -- State variable
- variable w : t_comb; -- Local wires = memoryless auxiliary variables
+ -- State variable
+ variable v : t_reg;
+ -- Local wires = memoryless auxiliary variables
+ variable w : t_comb;
begin
w := c_comb_rst;
- v := r; -- state signals
+ -- state signals
+ v := r;
v.mm_sosi := func_dp_stream_reset_control(r.mm_sosi);
v.wr_copi_arr := RESET_MEM_COPI_CTRL(r.wr_copi_arr);
v.replace_cnt_en_arr := (others => '0');
@@ -304,11 +325,15 @@ begin
for I in 0 to g_nof_streams - 1 loop
w.lost_data_flags_arr(I) := not v.filled_arr(I)(v.rd_blk_pointer);
v.replace_cnt_en_arr(I) := w.lost_data_flags_arr(I);
- if stream_en_arr(I) = '1' then -- use MM bit at sop
- v.use_replacement_data(I) := w.lost_data_flags_arr(I); -- enabled stream, so replace the data if the data was lost
- v.mm_sosi.channel(I) := w.lost_data_flags_arr(I); -- enabled stream, so flag the data if the data was lost
+ -- use MM bit at sop
+ if stream_en_arr(I) = '1' then
+ -- enabled stream, so replace the data if the data was lost
+ v.use_replacement_data(I) := w.lost_data_flags_arr(I);
+ -- enabled stream, so flag the data if the data was lost
+ v.mm_sosi.channel(I) := w.lost_data_flags_arr(I);
else
- v.use_replacement_data(I) := '1'; -- disabled stream, so replace the data, but do not flag the data as lost
+ -- disabled stream, so replace the data, but do not flag the data as lost
+ v.use_replacement_data(I) := '1';
v.replace_cnt_en_arr(I) := '1';
end if;
end loop;
@@ -363,7 +388,8 @@ begin
end if;
-- . pass on input data from the buffer
- w.out_sosi_arr := rd_sosi_arr; -- = v.fill_cipo_arr in streaming format, contains the
+ -- = v.fill_cipo_arr in streaming format, contains the
+ w.out_sosi_arr := rd_sosi_arr;
-- input data from the buffer or replacement data
if rd_sosi_arr(0).sop = '1' then
-- . at sop pass on input info from r.dp_sosi to all streams in out_sosi_arr
@@ -457,7 +483,8 @@ begin
-- Use dp_copi_arr(0) to read same addresses in parallel for all streams
dp_copi <= dp_copi_arr(0);
- dp_done <= dp_done_arr(0); -- for viewing only
+ -- for viewing only
+ dp_done <= dp_done_arr(0);
end generate;
------------------------------------------------------------------------------
@@ -489,7 +516,8 @@ begin
u_in_sosi_arr_p : entity work.dp_pipeline_arr
generic map (
g_nof_streams => g_nof_streams,
- g_pipeline => g_pipeline_input -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline => g_pipeline_input
)
port map (
rst => dp_rst,
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd b/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
index fe7e3680603b023a0f66d06a3ef9fe760958e123..a85e64cc7a9bb4687a49cd0bd97938aa57794cef 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
@@ -66,8 +66,10 @@ use work.dp_stream_pkg.all;
entity dp_bsn_delay is
generic (
- g_nof_block_latency : natural := 0; -- >= 0
- g_bsn_w : natural := 48 -- use g_bsn_w to allow leaving in_bsn NC
+ -- >= 0
+ g_nof_block_latency : natural := 0;
+ -- use g_bsn_w to allow leaving in_bsn NC
+ g_bsn_w : natural := 48
);
port (
rst : in std_logic;
@@ -75,7 +77,8 @@ entity dp_bsn_delay is
in_sync : in std_logic;
in_bsn : in std_logic_vector(g_bsn_w - 1 downto 0) := (others => '0');
in_eop : in std_logic;
- out_release : in std_logic; -- input from the data path processing, used as output release pulse
+ -- input from the data path processing, used as output release pulse
+ out_release : in std_logic;
out_sync : out std_logic;
out_bsn : out std_logic_vector(g_bsn_w - 1 downto 0)
);
@@ -85,10 +88,12 @@ architecture rtl of dp_bsn_delay is
type t_bsn_arr is array (integer range <>) of std_logic_vector(g_bsn_w - 1 downto 0);
signal hold_sync : std_logic;
- signal sync_dly : std_logic_vector(0 to g_nof_block_latency); -- [0] is hold_sync, the combinatorial in_sync is not delayed, because the DP latency must be > 0
+ -- [0] is hold_sync, the combinatorial in_sync is not delayed, because the DP latency must be > 0
+ signal sync_dly : std_logic_vector(0 to g_nof_block_latency);
signal nxt_sync_dly : std_logic_vector(1 to g_nof_block_latency);
- signal bsn_dly : t_bsn_arr(0 to g_nof_block_latency); -- [0] is combinatorial in_bsn
+ -- [0] is combinatorial in_bsn
+ signal bsn_dly : t_bsn_arr(0 to g_nof_block_latency);
signal nxt_bsn_dly : t_bsn_arr(1 to g_nof_block_latency);
signal bsn_reg : std_logic_vector(g_bsn_w - 1 downto 0);
@@ -110,9 +115,12 @@ begin
-- Hold the in_sync during the block until the in_eop
u_hold_sync : entity common_lib.common_switch
generic map (
- g_priority_lo => false, -- in_sync has priority over in_eop, because they may occur simultaneously
- g_or_high => false, -- hold_sync goes high after in_sync
- g_and_low => false -- hold_sync goes low after in_eop
+ -- in_sync has priority over in_eop, because they may occur simultaneously
+ g_priority_lo => false,
+ -- hold_sync goes high after in_sync
+ g_or_high => false,
+ -- hold_sync goes low after in_eop
+ g_and_low => false
)
port map (
rst => rst,
@@ -130,7 +138,9 @@ begin
nxt_bsn_dly <= bsn_dly( 0 to g_nof_block_latency - 1) when in_eop = '1' else bsn_dly( 1 to g_nof_block_latency);
-- Output block alignment using the out_release
- out_sync <= sync_dly(g_nof_block_latency) when out_release = '1' else '0'; -- combinatorial pulse
- nxt_bsn_reg <= bsn_dly(g_nof_block_latency) when out_release = '1' else bsn_reg; -- register the BSN to hold it during the output block
+ -- combinatorial pulse
+ out_sync <= sync_dly(g_nof_block_latency) when out_release = '1' else '0';
+ -- register the BSN to hold it during the output block
+ nxt_bsn_reg <= bsn_dly(g_nof_block_latency) when out_release = '1' else bsn_reg;
out_bsn <= bsn_reg;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
index e32360c2085b7c1ce82fb1c07541d21957308aba..03bfa8b5971bd7649ffab187a95444b0f5f86253 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
@@ -48,9 +48,11 @@ use work.dp_stream_pkg.all;
entity dp_bsn_monitor is
generic (
- g_sync_timeout : natural := 200 * 10**6; -- choose >= nof clk cycles per sync period
+ -- choose >= nof clk cycles per sync period
+ g_sync_timeout : natural := 200 * 10**6;
g_error_bi : natural := 0;
- g_log_first_bsn : boolean := true -- Logs first BSN + cycle count. Useful when using BSN aligner.
+ -- Logs first BSN + cycle count. Useful when using BSN aligner.
+ g_log_first_bsn : boolean := true
);
port (
rst : in std_logic := '0';
@@ -59,11 +61,14 @@ entity dp_bsn_monitor is
-- ST interface
in_siso : in t_dp_siso;
in_sosi : in t_dp_sosi;
- sync_in : in std_logic := '0'; -- Sync input that samples the current bsn number and the number of clockcycles that have expired since the last sop
+ -- Sync input that samples the current bsn number and the number of clockcycles that have expired since the last sop
+ sync_in : in std_logic := '0';
-- MM interface
-- . control
- mon_evt : out std_logic; -- pulses when new monitor output is available regarding the previous sync interval
- mon_sync : out std_logic; -- pulses every in_sosi.sync interval
+ -- pulses when new monitor output is available regarding the previous sync interval
+ mon_evt : out std_logic;
+ -- pulses every in_sosi.sync interval
+ mon_sync : out std_logic;
mon_sync_timeout : out std_logic;
-- . siso
mon_ready_stable : out std_logic;
@@ -105,7 +110,8 @@ architecture rtl of dp_bsn_monitor is
signal nxt_bsn : std_logic_vector(c_bsn_w - 1 downto 0);
signal cnt_sop : std_logic_vector(c_cnt_sop_w - 1 downto 0);
signal nof_sop : std_logic_vector(c_cnt_sop_w - 1 downto 0);
- signal cnt_err : std_logic_vector(c_cnt_sop_w - 1 downto 0); -- use c_cnt_sop_w, because at maximium all frames have an error
+ -- use c_cnt_sop_w, because at maximium all frames have an error
+ signal cnt_err : std_logic_vector(c_cnt_sop_w - 1 downto 0);
signal nof_err : std_logic_vector(c_cnt_sop_w - 1 downto 0);
signal cnt_valid : std_logic_vector(c_cnt_valid_w - 1 downto 0);
signal nof_valid : std_logic_vector(c_cnt_valid_w - 1 downto 0);
@@ -157,9 +163,11 @@ begin
nxt_mon_nof_err <= nof_err when sync = '1' else i_mon_nof_err;
nxt_mon_nof_valid <= nof_valid when sync = '1' else i_mon_nof_valid;
- nof_sop <= INCR_UVEC(cnt_sop, 1); -- +1 because the sop at the sync also counts
+ -- +1 because the sop at the sync also counts
+ nof_sop <= INCR_UVEC(cnt_sop, 1);
nof_err <= cnt_err;
- nof_valid <= INCR_UVEC(cnt_valid, 1); -- +1 because the valid at the sync also counts
+ -- +1 because the valid at the sync also counts
+ nof_valid <= INCR_UVEC(cnt_valid, 1);
u_sync_timeout_cnt : entity common_lib.common_counter
generic map (
@@ -271,8 +279,10 @@ begin
nxt_valid <= in_sosi.valid;
nxt_sop <= in_sosi.sop;
nxt_sync <= in_sosi.sync;
- nxt_err <= in_sosi.err(g_error_bi) when in_sosi.eop = '1' else '0'; -- assume sosi.err(g_error_bi) = '1' at eop indicates an error
- nxt_bsn <= in_sosi.bsn(c_bsn_w - 1 downto 0) when in_sosi.sop = '1' else bsn; -- keep bsn as defined at sop
+ -- assume sosi.err(g_error_bi) = '1' at eop indicates an error
+ nxt_err <= in_sosi.err(g_error_bi) when in_sosi.eop = '1' else '0';
+ -- keep bsn as defined at sop
+ nxt_bsn <= in_sosi.bsn(c_bsn_w - 1 downto 0) when in_sosi.sop = '1' else bsn;
gen_log_first_bsn : if g_log_first_bsn = true generate
nxt_mon_bsn_first <= in_sosi.bsn(c_bsn_w - 1 downto 0) when first_sop = '0' and in_sosi.sop = '1' else i_mon_bsn_first;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
index 1eab6bd1e082841b8170239f4c1d338304203622..aa5b93637b9dec342606cf2b3be390e2b3d15a4e 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
@@ -52,21 +52,29 @@ use common_lib.common_mem_pkg.all;
entity dp_bsn_monitor_reg is
generic (
- g_cross_clock_domain : boolean := true -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
- mon_evt : in std_logic; -- pulses when new monitor data is available regarding the previous sync interval
+ -- pulses when new monitor data is available regarding the previous sync interval
+ mon_evt : in std_logic;
mon_sync_timeout : in std_logic;
-- . siso
mon_ready_stable : in std_logic;
@@ -85,7 +93,8 @@ architecture str of dp_bsn_monitor_reg is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 4,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 9,
init_sl => '0');
@@ -105,7 +114,8 @@ begin
u_reg : entity common_lib.common_reg_r_w_dc
generic map (
g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1, -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
+ -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
+ g_in_new_latency => 1,
g_readback => false,
g_reg => c_mm_reg
)
@@ -124,7 +134,9 @@ begin
reg_wr_arr => OPEN,
reg_rd_arr => OPEN,
in_new => mon_evt,
- in_reg => mon_reg, -- read only
- out_reg => open -- no write
+ -- read only
+ in_reg => mon_reg,
+ -- no write
+ out_reg => open
);
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
index 6f01dc61b677e6f289406c5eae62ebb6a52fb33c..2c86528558141b07ea15cd3258ab83b4790b20e7 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
@@ -49,21 +49,29 @@ use common_lib.common_mem_pkg.all;
entity dp_bsn_monitor_reg_v2 is
generic (
- g_cross_clock_domain : boolean := true -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
- mon_evt : in std_logic; -- pulses when new monitor data is available regarding the previous sync interval
+ -- pulses when new monitor data is available regarding the previous sync interval
+ mon_evt : in std_logic;
mon_sync_timeout : in std_logic;
-- . siso
mon_ready_stable : in std_logic;
@@ -81,7 +89,8 @@ architecture str of dp_bsn_monitor_reg_v2 is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 3,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 7,
init_sl => '0');
@@ -100,7 +109,8 @@ begin
u_reg : entity common_lib.common_reg_r_w_dc
generic map (
g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1, -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
+ -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
+ g_in_new_latency => 1,
g_readback => false,
g_reg => c_mm_reg
)
@@ -119,7 +129,9 @@ begin
reg_wr_arr => OPEN,
reg_rd_arr => OPEN,
in_new => mon_evt,
- in_reg => mon_reg, -- read only
- out_reg => open -- no write
+ -- read only
+ in_reg => mon_reg,
+ -- no write
+ out_reg => open
);
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
index 339533f55ebd8422d8fff957ae7cfeee69b0e07c..19b4e75be28b49b44e023770ab59f52e3d004e51 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
@@ -47,7 +47,8 @@ use work.dp_stream_pkg.all;
entity dp_bsn_monitor_v2 is
generic (
- g_sync_timeout : natural := 200 * 10**6; -- choose >= nof clk cycles per sync period
+ -- choose >= nof clk cycles per sync period
+ g_sync_timeout : natural := 200 * 10**6;
g_error_bi : natural := 0
);
port (
@@ -57,11 +58,14 @@ entity dp_bsn_monitor_v2 is
-- ST interface
in_siso : in t_dp_siso;
in_sosi : in t_dp_sosi;
- ref_sync : in std_logic := '0'; -- reference sync input
+ -- reference sync input
+ ref_sync : in std_logic := '0';
-- MM interface
-- . control
- mon_evt : out std_logic; -- pulses when new monitor output is available regarding the previous sync interval
- mon_sync : out std_logic; -- pulses every in_sosi.sync interval
+ -- pulses when new monitor output is available regarding the previous sync interval
+ mon_evt : out std_logic;
+ -- pulses every in_sosi.sync interval
+ mon_sync : out std_logic;
mon_sync_timeout : out std_logic;
-- . siso
mon_ready_stable : out std_logic;
@@ -109,7 +113,8 @@ architecture rtl of dp_bsn_monitor_v2 is
signal nxt_bsn : std_logic_vector(c_bsn_w - 1 downto 0);
signal cnt_sop : std_logic_vector(c_cnt_sop_w - 1 downto 0);
signal nof_sop : std_logic_vector(c_cnt_sop_w - 1 downto 0);
- signal cnt_err : std_logic_vector(c_cnt_sop_w - 1 downto 0); -- use c_cnt_sop_w, because at maximium all frames have an error
+ -- use c_cnt_sop_w, because at maximium all frames have an error
+ signal cnt_err : std_logic_vector(c_cnt_sop_w - 1 downto 0);
signal nof_err : std_logic_vector(c_cnt_sop_w - 1 downto 0);
signal cnt_valid : std_logic_vector(c_cnt_valid_w - 1 downto 0);
signal nof_valid : std_logic_vector(c_cnt_valid_w - 1 downto 0);
@@ -159,7 +164,8 @@ begin
nxt_mon_nof_sop <= nof_sop when sync = '1' else i_mon_nof_sop;
nxt_mon_nof_err <= nof_err when sync = '1' else i_mon_nof_err;
nxt_mon_nof_valid <= nof_valid when sync = '1' else i_mon_nof_valid;
- nxt_mon_latency <= latency when sync_reg2 = '1' else i_mon_latency; -- use sync_reg2 due to ref_sync_reg
+ -- use sync_reg2 due to ref_sync_reg
+ nxt_mon_latency <= latency when sync_reg2 = '1' else i_mon_latency;
nof_sop <= cnt_sop;
nof_err <= cnt_err;
@@ -283,8 +289,10 @@ begin
nxt_valid <= in_sosi.valid;
nxt_sop <= in_sosi.sop;
nxt_sync <= in_sosi.sync;
- nxt_err <= in_sosi.err(g_error_bi) when in_sosi.eop = '1' else '0'; -- assume sosi.err(g_error_bi) = '1' at eop indicates an error
- nxt_bsn <= in_sosi.bsn(c_bsn_w - 1 downto 0) when in_sosi.sop = '1' else bsn; -- keep bsn as defined at sop
+ -- assume sosi.err(g_error_bi) = '1' at eop indicates an error
+ nxt_err <= in_sosi.err(g_error_bi) when in_sosi.eop = '1' else '0';
+ -- keep bsn as defined at sop
+ nxt_bsn <= in_sosi.bsn(c_bsn_w - 1 downto 0) when in_sosi.sop = '1' else bsn;
u_cnt_sop : entity common_lib.common_counter
generic map (
@@ -293,7 +301,8 @@ begin
port map (
rst => rst,
clk => clk,
- cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the sop at the sync counts too.
+ -- using cnt_ld instead of cnt clr to reset to 1 as the sop at the sync counts too.
+ cnt_ld => sync,
cnt_en => sop,
load => TO_SVEC(1, c_cnt_sop_w),
count => cnt_sop
@@ -318,7 +327,8 @@ begin
port map (
rst => rst,
clk => clk,
- cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the valid at the sync counts too.
+ -- using cnt_ld instead of cnt clr to reset to 1 as the valid at the sync counts too.
+ cnt_ld => sync,
cnt_en => valid,
load => TO_SVEC(1, c_cnt_valid_w),
count => cnt_valid
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd b/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
index b4c524a869d42b2230682245fb7aa476432c610d..054415e6f66ceda23a76fe8be2622b5b361568ce 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
@@ -43,7 +43,8 @@ use work.dp_stream_pkg.all;
entity dp_bsn_restore_global is
generic (
g_bsn_w : natural := c_dp_stream_bsn_w;
- g_pipeline : natural := 1 -- 0 for wires, > 0 for registers
+ -- 0 for wires, > 0 for registers
+ g_pipeline : natural := 1
);
port (
rst : in std_logic;
@@ -80,16 +81,22 @@ begin
-- Create block sync from snk_in.sync, this blk_sync is active during entire first sop-eop block of sync interval
u_common_switch : entity common_lib.common_switch
generic map (
- g_rst_level => '0', -- Defines the output level at reset.
- g_priority_lo => false, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
- g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
- g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ -- Defines the output level at reset.
+ g_rst_level => '0',
+ -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
+ g_priority_lo => false,
+ -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
+ g_or_high => true,
+ -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ g_and_low => false
)
port map (
rst => rst,
clk => clk,
- switch_high => snk_in.sync, -- A pulse on switch_high makes the out_level go high
- switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
+ -- A pulse on switch_high makes the out_level go high
+ switch_high => snk_in.sync,
+ -- A pulse on switch_low makes the out_level go low
+ switch_low => snk_in.eop,
out_level => blk_sync
);
@@ -101,7 +108,8 @@ begin
-- Add pipeline to ensure timing closure for the restored BSN summation
u_pipeline : entity work.dp_pipeline
generic map (
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
+ -- 0 for wires, > 0 for registers
+ g_pipeline => g_pipeline
)
port map (
rst => rst,
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
index b095b03d52a965135e7aac88a20526843d3bd7a1..416eb0ba469db215300fc008f3fdb0fff561a5d6 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
@@ -47,7 +47,8 @@ entity dp_bsn_scheduler is
-- MM control
scheduled_bsn : in std_logic_vector(g_bsn_w - 1 downto 0) := (others => '0');
-- Streaming
- snk_in : in t_dp_sosi; -- only uses eop (= block sync), bsn[]
+ -- only uses eop (= block sync), bsn[]
+ snk_in : in t_dp_sosi;
trigger_out : out std_logic
);
end dp_bsn_scheduler;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
index 36d2d553ae37566374c310a39e4f1f0c651429fa..e943c619fa8c2e129362c39ef04c274eed33db25 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
@@ -38,18 +38,25 @@ use common_lib.common_mem_pkg.all;
entity dp_bsn_scheduler_reg is
generic (
- g_cross_clock_domain : boolean := true -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
st_current_bsn : in std_logic_vector;
@@ -63,7 +70,8 @@ architecture rtl of dp_bsn_scheduler_reg is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 1,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 2,
init_sl => '0');
@@ -105,24 +113,30 @@ begin
mm_scheduled_bsn(31 downto 0) <= sla_in.wrdata(31 downto 0);
when 1 =>
mm_scheduled_bsn(63 downto 32) <= sla_in.wrdata(31 downto 0);
- mm_scheduled_bsn_wr <= '1'; -- host must first write low then this high part
+ -- host must first write low then this high part
+ mm_scheduled_bsn_wr <= '1';
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read current BSN
when 0 =>
sla_out.rddata(31 downto 0) <= mm_current_bsn(31 downto 0);
- mm_current_bsn_hi <= mm_current_bsn(63 downto 32); -- first read low part and preserve high part
+ -- first read low part and preserve high part
+ mm_current_bsn_hi <= mm_current_bsn(63 downto 32);
when 1 =>
sla_out.rddata(31 downto 0) <= mm_current_bsn_hi;
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
end if;
end if;
@@ -146,7 +160,8 @@ begin
------------------------------------------------------------------------------
no_cross : if g_cross_clock_domain = false generate
- mm_current_bsn(c_bsn_w - 1 downto 0) <= st_current_bsn; -- MM user may read current_bsn twice to avoid small chance that the high part of the double word changed (i.e. incremented)
+ -- MM user may read current_bsn twice to avoid small chance that the high part of the double word changed (i.e. incremented)
+ mm_current_bsn(c_bsn_w - 1 downto 0) <= st_current_bsn;
p_st_clk : process(st_rst, st_clk)
begin
@@ -154,11 +169,13 @@ begin
st_scheduled_bsn <= TO_UVEC(0, c_bsn_w);
elsif rising_edge(st_clk) then
if mm_scheduled_bsn_wr = '1' then
- st_scheduled_bsn <= mm_scheduled_bsn(c_bsn_w - 1 downto 0); -- use wr of mm_scheduled_bsn high part for in_new to ensure proper transfer of double word
+ -- use wr of mm_scheduled_bsn high part for in_new to ensure proper transfer of double word
+ st_scheduled_bsn <= mm_scheduled_bsn(c_bsn_w - 1 downto 0);
end if;
end if;
end process;
- end generate; -- no_cross
+ -- no_cross
+ end generate;
gen_cross : if g_cross_clock_domain = true generate
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
@@ -166,9 +183,11 @@ begin
port map (
in_rst => mm_rst,
in_clk => mm_clk,
- in_new => mm_scheduled_bsn_wr, -- use wr of mm_scheduled_bsn high part for in_new to ensure proper transfer of double word
+ -- use wr of mm_scheduled_bsn high part for in_new to ensure proper transfer of double word
+ in_new => mm_scheduled_bsn_wr,
in_dat => mm_scheduled_bsn(c_bsn_w - 1 downto 0),
- in_done => OPEN, -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done => OPEN,
out_rst => st_rst,
out_clk => st_clk,
out_dat => st_scheduled_bsn,
@@ -180,14 +199,17 @@ begin
port map (
in_rst => st_rst,
in_clk => st_clk,
- in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ in_new => '1',
in_dat => st_current_bsn,
- in_done => OPEN, -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done => OPEN,
out_rst => mm_rst,
out_clk => mm_clk,
out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
out_new => open
);
- end generate; -- gen_cross
+ -- gen_cross
+ end generate;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
index b1909332630be2e4e9bc92977b5009de29141226..d7ae12d27908e4e5d105e1148ac01312788202e0 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
@@ -57,7 +57,8 @@ entity dp_bsn_source is
init_bsn : in std_logic_vector(g_bsn_w - 1 downto 0) := (others => '0');
nof_block_per_sync : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_nof_block_per_sync, c_word_w);
- src_out : out t_dp_sosi -- only uses sync, bsn[], valid, sop and eop
+ -- only uses sync, bsn[], valid, sop and eop
+ src_out : out t_dp_sosi
);
end dp_bsn_source;
@@ -148,7 +149,8 @@ begin
end if;
end if;
- when others => -- s_init
+ -- s_init
+ when others =>
nxt_state <= s_dp_off;
end case;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
index e6310abb8fd4fe3e288e0643536d7321e766a073..329fbec7ad5867b986ae988830ba036e202e7190 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
@@ -45,27 +45,39 @@ use common_lib.common_mem_pkg.all;
entity dp_bsn_source_reg is
generic (
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
g_nof_block_per_sync : natural := 8
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
- st_on : out std_logic := '1'; -- level
- st_on_pps : out std_logic := '0'; -- level
+ -- level
+ st_on : out std_logic := '1';
+ -- level
+ st_on_pps : out std_logic := '0';
st_on_status : in std_logic;
- st_nof_block_per_sync : out std_logic_vector(c_word_w - 1 downto 0); -- nof block per sync
- st_init_bsn : out std_logic_vector; -- wr init BSN
- st_current_bsn : in std_logic_vector -- rd current BSN
+ -- nof block per sync
+ st_nof_block_per_sync : out std_logic_vector(c_word_w - 1 downto 0);
+ -- wr init BSN
+ st_init_bsn : out std_logic_vector;
+ -- rd current BSN
+ st_current_bsn : in std_logic_vector
);
end dp_bsn_source_reg;
@@ -75,15 +87,18 @@ architecture rtl of dp_bsn_source_reg is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 2**2,
init_sl => '0');
-- Registers in mm_clk domain
signal mm_on : std_logic;
signal mm_on_pps : std_logic;
- signal mm_on_ctrl : std_logic_vector(1 downto 0); -- = mm_on_pps & mm_on
- signal st_on_ctrl : std_logic_vector(1 downto 0); -- = st_on_pps & st_on
+ -- = mm_on_pps & mm_on
+ signal mm_on_ctrl : std_logic_vector(1 downto 0);
+ -- = st_on_pps & st_on
+ signal st_on_ctrl : std_logic_vector(1 downto 0);
signal mm_on_status : std_logic;
signal mm_nof_block_per_sync : std_logic_vector(c_word_w - 1 downto 0);
@@ -139,13 +154,16 @@ begin
mm_init_bsn(63 downto 32) <= sla_in.wrdata(31 downto 0);
mm_init_bsn_wr <= '1';
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read Block Sync
when 0 =>
@@ -157,11 +175,13 @@ begin
-- Read current BSN
when 2 =>
sla_out.rddata(31 downto 0) <= mm_current_bsn(31 downto 0);
- mm_current_bsn_hi <= mm_current_bsn(63 downto 32); -- first read low part and preserve high part
+ -- first read low part and preserve high part
+ mm_current_bsn_hi <= mm_current_bsn(63 downto 32);
when 3 =>
sla_out.rddata(31 downto 0) <= mm_current_bsn_hi;
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
end if;
end if;
@@ -184,7 +204,8 @@ begin
-- signals if it is necessary (to avoid using more logic than necessary).
------------------------------------------------------------------------------
- no_cross : if g_cross_clock_domain = false generate -- so mm_clk = st_clk
+ -- so mm_clk = st_clk
+ no_cross : if g_cross_clock_domain = false generate
st_on <= mm_on;
st_on_pps <= mm_on_pps;
st_nof_block_per_sync <= mm_nof_block_per_sync;
@@ -196,13 +217,16 @@ begin
st_init_bsn <= TO_UVEC(0, c_bsn_w);
elsif rising_edge(st_clk) then
if mm_init_bsn_wr = '1' then
- st_init_bsn <= mm_init_bsn(c_bsn_w - 1 downto 0); -- use wr of mm_init_bsn high part for in_new to ensure proper transfer of double word
+ -- use wr of mm_init_bsn high part for in_new to ensure proper transfer of double word
+ st_init_bsn <= mm_init_bsn(c_bsn_w - 1 downto 0);
end if;
end if;
end process;
- mm_current_bsn(c_bsn_w - 1 downto 0) <= st_current_bsn; -- MM user may read current_bsn twice to avoid small chance that the high part of the double word changed (i.e. incremented)
- end generate; -- no_cross
+ -- MM user may read current_bsn twice to avoid small chance that the high part of the double word changed (i.e. incremented)
+ mm_current_bsn(c_bsn_w - 1 downto 0) <= st_current_bsn;
+ -- no_cross
+ end generate;
gen_cross : if g_cross_clock_domain = true generate
-- Block sync registers
@@ -211,7 +235,8 @@ begin
in_rst => mm_rst,
in_clk => mm_clk,
in_dat => mm_on_ctrl,
- in_done => OPEN, -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done => OPEN,
out_rst => st_rst,
out_clk => st_clk,
out_dat => st_on_ctrl,
@@ -241,7 +266,8 @@ begin
in_rst => mm_rst,
in_clk => mm_clk,
in_dat => mm_nof_block_per_sync,
- in_done => OPEN, -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done => OPEN,
out_rst => st_rst,
out_clk => st_clk,
out_dat => st_nof_block_per_sync,
@@ -253,9 +279,11 @@ begin
port map (
in_rst => mm_rst,
in_clk => mm_clk,
- in_new => mm_init_bsn_wr, -- use wr of mm_init_bsn high part for in_new to ensure proper transfer of double word
+ -- use wr of mm_init_bsn high part for in_new to ensure proper transfer of double word
+ in_new => mm_init_bsn_wr,
in_dat => mm_init_bsn(c_bsn_w - 1 downto 0),
- in_done => OPEN, -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done => OPEN,
out_rst => st_rst,
out_clk => st_clk,
out_dat => st_init_bsn,
@@ -267,14 +295,17 @@ begin
port map (
in_rst => st_rst,
in_clk => st_clk,
- in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ in_new => '1',
in_dat => st_current_bsn,
- in_done => OPEN, -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done => OPEN,
out_rst => mm_rst,
out_clk => mm_clk,
out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
out_new => open
);
- end generate; -- gen_cross
+ -- gen_cross
+ end generate;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
index 71eab87eda14396b01034520b7417afaf2385af0..ac9bf6dcb2f62c1c016948c108abb19f53a7afec 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
@@ -46,27 +46,39 @@ use common_lib.common_mem_pkg.all;
entity dp_bsn_source_reg_v2 is
generic (
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
g_nof_clk_per_sync : natural := 200 * 10**6
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
- st_on : out std_logic := '1'; -- level
- st_on_pps : out std_logic := '0'; -- level
+ -- level
+ st_on : out std_logic := '1';
+ -- level
+ st_on_pps : out std_logic := '0';
st_on_status : in std_logic;
- st_nof_clk_per_sync : out std_logic_vector(c_word_w - 1 downto 0); -- nof block per sync
- st_bsn_init : out std_logic_vector; -- wr init BSN
- st_current_bsn : in std_logic_vector; -- rd current BSN
+ -- nof block per sync
+ st_nof_clk_per_sync : out std_logic_vector(c_word_w - 1 downto 0);
+ -- wr init BSN
+ st_bsn_init : out std_logic_vector;
+ -- rd current BSN
+ st_current_bsn : in std_logic_vector;
st_bsn_time_offset : out std_logic_vector
);
end dp_bsn_source_reg_v2;
@@ -78,15 +90,18 @@ architecture rtl of dp_bsn_source_reg_v2 is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 3,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 2**3,
init_sl => '0');
-- Registers in mm_clk domain
signal mm_on : std_logic;
signal mm_on_pps : std_logic;
- signal mm_on_ctrl : std_logic_vector(1 downto 0); -- = mm_on_pps & mm_on
- signal st_on_ctrl : std_logic_vector(1 downto 0); -- = st_on_pps & st_on
+ -- = mm_on_pps & mm_on
+ signal mm_on_ctrl : std_logic_vector(1 downto 0);
+ -- = st_on_pps & st_on
+ signal st_on_ctrl : std_logic_vector(1 downto 0);
signal mm_on_status : std_logic;
signal mm_nof_clk_per_sync : std_logic_vector(c_word_w - 1 downto 0);
@@ -153,13 +168,16 @@ begin
mm_bsn_time_offset <= sla_in.wrdata(c_bsn_time_offset_w - 1 downto 0);
mm_bsn_time_offset_wr <= '1';
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read Block Sync
when 0 =>
@@ -171,15 +189,18 @@ begin
-- Read current BSN
when 2 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_current_bsn(31 downto 0);
- mm_current_bsn_hi <= mm_current_bsn(63 downto 32); -- first read low part and preserve high part
+ -- first read low part and preserve high part
+ mm_current_bsn_hi <= mm_current_bsn(63 downto 32);
when 3 =>
- sla_out.rddata(c_word_w - 1 downto 0) <= mm_current_bsn_hi; -- then read preserved high part
+ -- then read preserved high part
+ sla_out.rddata(c_word_w - 1 downto 0) <= mm_current_bsn_hi;
-- Read current bsn_time_offset
when 4 =>
sla_out.rddata(c_word_w - 1 downto 0) <= RESIZE_UVEC(mm_bsn_time_offset, c_word_w);
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
end if;
end if;
@@ -202,7 +223,8 @@ begin
-- signals if it is necessary (to avoid using more logic than necessary).
------------------------------------------------------------------------------
- no_cross : if g_cross_clock_domain = false generate -- so mm_clk = st_clk
+ -- so mm_clk = st_clk
+ no_cross : if g_cross_clock_domain = false generate
st_on <= mm_on;
st_on_pps <= mm_on_pps;
st_nof_clk_per_sync <= mm_nof_clk_per_sync;
@@ -226,7 +248,8 @@ begin
end process;
mm_current_bsn(c_bsn_w - 1 downto 0) <= st_current_bsn;
- end generate; -- no_cross
+ -- no_cross
+ end generate;
gen_cross : if g_cross_clock_domain = true generate
-- Block sync registers
@@ -235,7 +258,8 @@ begin
in_rst => mm_rst,
in_clk => mm_clk,
in_dat => mm_on_ctrl,
- in_done => OPEN, -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done => OPEN,
out_rst => st_rst,
out_clk => st_clk,
out_dat => st_on_ctrl,
@@ -265,7 +289,8 @@ begin
in_rst => mm_rst,
in_clk => mm_clk,
in_dat => mm_nof_clk_per_sync,
- in_done => OPEN, -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done => OPEN,
out_rst => st_rst,
out_clk => st_clk,
out_dat => st_nof_clk_per_sync,
@@ -277,9 +302,11 @@ begin
port map (
in_rst => mm_rst,
in_clk => mm_clk,
- in_new => mm_bsn_init_wr, -- use wr of mm_bsn_init high part for in_new to ensure proper transfer of double word
+ -- use wr of mm_bsn_init high part for in_new to ensure proper transfer of double word
+ in_new => mm_bsn_init_wr,
in_dat => mm_bsn_init(c_bsn_w - 1 downto 0),
- in_done => OPEN, -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done => OPEN,
out_rst => st_rst,
out_clk => st_clk,
out_dat => st_bsn_init,
@@ -291,9 +318,11 @@ begin
port map (
in_rst => st_rst,
in_clk => st_clk,
- in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ in_new => '1',
in_dat => st_current_bsn,
- in_done => OPEN, -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done => OPEN,
out_rst => mm_rst,
out_clk => mm_clk,
out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
@@ -307,12 +336,14 @@ begin
in_clk => mm_clk,
in_new => mm_bsn_time_offset_wr,
in_dat => mm_bsn_time_offset,
- in_done => OPEN, -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done => OPEN,
out_rst => st_rst,
out_clk => st_clk,
out_dat => st_bsn_time_offset,
out_new => open
);
- end generate; -- gen_cross
+ -- gen_cross
+ end generate;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
index 1d2ebf0fbbdcdbe4107083f2e8c8dbfafd8c45a2..6124284855ec36e36051407fdbd0b6905daa16d2 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
@@ -62,7 +62,8 @@ use work.dp_stream_pkg.all;
entity dp_bsn_source_v2 is
generic (
- g_block_size : natural := 256; -- >= 3, see state machine
+ -- >= 3, see state machine
+ g_block_size : natural := 256;
g_nof_clk_per_sync : natural := 200 * 10**6;
g_bsn_w : natural := 48;
g_bsn_time_offset_w : natural := 10
@@ -75,15 +76,19 @@ entity dp_bsn_source_v2 is
dp_on : in std_logic;
dp_on_pps : in std_logic;
- dp_on_status : out std_logic; -- = src_out.valid
- bs_restart : out std_logic; -- = src_out.sync for first sync after dp_on went high
- bs_new_interval : out std_logic; -- = active during first src_out.sync interval
+ -- = src_out.valid
+ dp_on_status : out std_logic;
+ -- = src_out.sync for first sync after dp_on went high
+ bs_restart : out std_logic;
+ -- = active during first src_out.sync interval
+ bs_new_interval : out std_logic;
nof_clk_per_sync : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w);
bsn_init : in std_logic_vector(g_bsn_w - 1 downto 0) := (others => '0');
bsn_time_offset : in std_logic_vector(g_bsn_time_offset_w - 1 downto 0) := (others => '0');
- src_out : out t_dp_sosi -- only uses sync, bsn[], valid, sop and eop
+ -- only uses sync, bsn[], valid, sop and eop
+ src_out : out t_dp_sosi
);
end dp_bsn_source_v2;
@@ -139,13 +144,15 @@ begin
nxt_sync <= sync;
nxt_sync_size_cnt <= INCR_UVEC(sync_size_cnt, 1);
if unsigned(sync_size_cnt) = unsigned(nof_clk_per_sync) - 1 then
- nxt_sync <= '1'; -- will set src_out.sync on next src_out.sop
+ -- will set src_out.sync on next src_out.sop
+ nxt_sync <= '1';
nxt_sync_size_cnt <= (others => '0');
end if;
-- State machine for src_out
nxt_state <= state;
- nxt_src_out <= i_src_out; -- hold src_out.bsn
+ -- hold src_out.bsn
+ nxt_src_out <= i_src_out;
nxt_src_out.sync <= '0';
nxt_src_out.valid <= '0';
nxt_src_out.sop <= '0';
@@ -161,7 +168,8 @@ begin
nxt_sync_size_cnt <= (others => '0');
nxt_block_size_cnt <= (others => '0');
if dp_on = '1' then
- nxt_sync <= '1'; -- ensure issue sync at first sync interval
+ -- ensure issue sync at first sync interval
+ nxt_sync <= '1';
if dp_on_pps = '1' then
-- start at pps
if pps = '1' then
@@ -225,7 +233,8 @@ begin
nxt_state <= s_dp_off;
end if;
- when others => -- reover from undefined state
+ -- reover from undefined state
+ when others =>
nxt_state <= s_dp_off;
end case;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
index f92809dc5488820c280468926a5ee741233aee97..9147075eff4b7396938b8da8af1c429a17d7c772 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
@@ -119,9 +119,12 @@ use work.dp_stream_pkg.all;
entity dp_bsn_sync_scheduler is
generic (
g_bsn_w : natural := c_dp_stream_bsn_w;
- g_block_size : natural := 256; -- = number of data valid per BSN block, must be >= 2
- g_ctrl_interval_size_min : natural := 1; -- Minimum interval size to use if MM write interval size is set too small.
- g_pipeline : natural := 1 -- use '1' on HW, use '0' for easier debugging in Wave window
+ -- = number of data valid per BSN block, must be >= 2
+ g_block_size : natural := 256;
+ -- Minimum interval size to use if MM write interval size is set too small.
+ g_ctrl_interval_size_min : natural := 1;
+ -- use '1' on HW, use '0' for easier debugging in Wave window
+ g_pipeline : natural := 1
);
port (
rst : in std_logic;
@@ -141,9 +144,12 @@ entity dp_bsn_sync_scheduler is
-- Streaming
in_sosi : in t_dp_sosi;
out_sosi : out t_dp_sosi;
- out_start : out std_logic; -- pulse at out_sosi.sync at ctrl_start_bsn
- out_start_interval : out std_logic; -- active during first out_sosi.sync interval
- out_enable : out std_logic -- for tb verification purposes
+ -- pulse at out_sosi.sync at ctrl_start_bsn
+ out_start : out std_logic;
+ -- active during first out_sosi.sync interval
+ out_start_interval : out std_logic;
+ -- for tb verification purposes
+ out_enable : out std_logic
);
end dp_bsn_sync_scheduler;
@@ -173,9 +179,12 @@ architecture rtl of dp_bsn_sync_scheduler is
signal nxt_r : t_reg;
signal output_enable : std_logic;
- signal output_next : std_logic; -- active at next output_sync's
- signal output_start : std_logic; -- active at first output_sync
- signal output_start_interval : std_logic; -- active during first output_sync interval
+ -- active at next output_sync's
+ signal output_next : std_logic;
+ -- active at first output_sync
+ signal output_start : std_logic;
+ -- active during first output_sync interval
+ signal output_start_interval : std_logic;
signal output_start_interval_reg : std_logic := '0';
signal output_sync : std_logic;
signal output_sosi : t_dp_sosi;
@@ -229,26 +238,36 @@ begin
v_size := r.blk_cnt * g_block_size;
if v_size = ctrl_interval_size then
-- Support integer number of blocks per output sync interval
- v.interval_size := ctrl_interval_size; -- hold ctrl_interval_size
- v.start_bsn := ctrl_start_bsn; -- hold ctrl_start_bsn
+ -- hold ctrl_interval_size
+ v.interval_size := ctrl_interval_size;
+ -- hold ctrl_start_bsn
+ v.start_bsn := ctrl_start_bsn;
-- Fixed sync interval control, effectively disable fractional sync interval control:
v.nof_blk_min := r.blk_cnt;
v.nof_blk_max := r.blk_cnt;
- v.nof_blk := r.blk_cnt; -- nof_blk = nof_blk_max = nof_blk_min
+ -- nof_blk = nof_blk_max = nof_blk_min
+ v.nof_blk := r.blk_cnt;
v.extra := 0;
v.accumulate := 0;
- v.enable_init := '0'; -- enable initialization is done
+ -- enable initialization is done
+ v.enable_init := '0';
elsif v_size > ctrl_interval_size then
-- Support fractional number of blocks per output sync interval
- v.interval_size := ctrl_interval_size; -- hold ctrl_interval_size
- v.start_bsn := ctrl_start_bsn; -- hold ctrl_start_bsn
+ -- hold ctrl_interval_size
+ v.interval_size := ctrl_interval_size;
+ -- hold ctrl_start_bsn
+ v.start_bsn := ctrl_start_bsn;
-- Fractional sync interval control:
v.nof_blk_min := r.blk_cnt - 1;
v.nof_blk_max := r.blk_cnt;
- v.nof_blk := r.blk_cnt; -- start with nof_blk_max sync interval
- v.extra := v_size - ctrl_interval_size; -- number of extra samples in nof_blk_max compared to ctrl_interval_size
- v.accumulate := v.extra; -- start with nof_blk_max sync interval
- v.enable_init := '0'; -- enable initialization is done
+ -- start with nof_blk_max sync interval
+ v.nof_blk := r.blk_cnt;
+ -- number of extra samples in nof_blk_max compared to ctrl_interval_size
+ v.extra := v_size - ctrl_interval_size;
+ -- start with nof_blk_max sync interval
+ v.accumulate := v.extra;
+ -- enable initialization is done
+ v.enable_init := '0';
else
v.blk_cnt := r.blk_cnt + 1;
end if;
@@ -301,8 +320,10 @@ begin
if in_sosi.sop = '1' then
if unsigned(in_sosi.bsn) = unsigned(r.start_bsn) then
v.output_enable := '1';
- output_start <= '1'; -- Pulse at start of output enable at start BSN of output sync intervals
- v.output_sync_bsn := r.start_bsn; -- Initialize output sync at start BSN of output sync intervals
+ -- Pulse at start of output enable at start BSN of output sync intervals
+ output_start <= '1';
+ -- Initialize output sync at start BSN of output sync intervals
+ v.output_sync_bsn := r.start_bsn;
end if;
end if;
else
@@ -320,7 +341,8 @@ begin
if in_sosi.sop = '1' then
if unsigned(in_sosi.bsn) = unsigned(v.output_sync_bsn) then
-- Matching input block
- output_sync <= '1'; -- The output sync interval
+ -- The output sync interval
+ output_sync <= '1';
v.update_bsn := '1';
elsif unsigned(in_sosi.bsn) > unsigned(v.output_sync_bsn) then
-- Missed one or more input blocks, so cannot output sync, look for
@@ -341,13 +363,16 @@ begin
-- ctrl_interval_size compared to nof_blk_min.
-- Both schemes are valid, by using different schemes here and in tb the
-- verification coverage improves.
- v.output_sync_bsn := ADD_UVEC(r.output_sync_bsn, TO_UVEC(r.nof_blk, c_natural_w)); -- next BSN
+ -- next BSN
+ v.output_sync_bsn := ADD_UVEC(r.output_sync_bsn, TO_UVEC(r.nof_blk, c_natural_w));
v.nof_blk := r.nof_blk_max;
- v.accumulate := r.accumulate + r.extra; -- account for nof_blk_max
+ -- account for nof_blk_max
+ v.accumulate := r.accumulate + r.extra;
if v.accumulate >= g_block_size then
v.nof_blk := r.nof_blk_min;
- v.accumulate := v.accumulate - g_block_size; -- adjust for nof_blk_min
+ -- adjust for nof_blk_min
+ v.accumulate := v.accumulate - g_block_size;
end if;
-- Assume output_sync_bsn is in future
diff --git a/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd b/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
index 0326cf21388a40649729228785f7f2148441ed95..7090a6d62058a8f570c3e89ebcd7e78be931a52f 100644
--- a/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
@@ -95,9 +95,11 @@ begin
-- Calculate CRC per block
nxt_calc_crc <= calc_crc;
- if snk_in.sop = '1' then -- restart CRC at begin of block
+ -- restart CRC at begin of block
+ if snk_in.sop = '1' then
nxt_calc_crc <= func_next_crc(data, c_crc_init);
- elsif snk_in.valid = '1' then -- calculate CRC during block
+ -- calculate CRC during block
+ elsif snk_in.valid = '1' then
nxt_calc_crc <= v_crc;
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_complex_add.vhd b/libraries/base/dp/src/vhdl/dp_complex_add.vhd
index 046cd7f80aff6a37fff1dbfddd8e936d75e57bde..6c2397e9faee5aa289506a4f219c2e5e994710e8 100644
--- a/libraries/base/dp/src/vhdl/dp_complex_add.vhd
+++ b/libraries/base/dp/src/vhdl/dp_complex_add.vhd
@@ -36,7 +36,8 @@ entity dp_complex_add is
generic (
g_technology : natural := c_tech_select_default;
g_nof_inputs : natural;
- g_data_w : natural -- Complex input data width
+ -- Complex input data width
+ g_data_w : natural
);
port (
rst : in std_logic;
diff --git a/libraries/base/dp/src/vhdl/dp_complex_mult.vhd b/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
index b41f0cfdf0a6008a676933865c476b5c2efb8e5e..420f0b3ffe91886de4a99b4558547f50dbd36ca6 100644
--- a/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
+++ b/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
@@ -40,8 +40,10 @@ entity dp_complex_mult is
generic (
g_technology : natural := c_tech_select_default;
g_nof_multipliers : natural;
- g_conjugate_b : boolean := false; -- Conjugate input 1 of snk_in_2arr2(i)(1 DOWNTO 0)
- g_data_w : natural; -- Input data width. Output data width = 2*input data width.
+ -- Conjugate input 1 of snk_in_2arr2(i)(1 DOWNTO 0)
+ g_conjugate_b : boolean := false;
+ -- Input data width. Output data width = 2*input data width.
+ g_data_w : natural;
g_variant : string := "IP"
);
port (
@@ -55,7 +57,8 @@ entity dp_complex_mult is
end dp_complex_mult;
architecture str of dp_complex_mult is
- constant c_pipeline : natural := 3; -- Delay introduces by IP multiplier used
+ -- Delay introduces by IP multiplier used
+ constant c_pipeline : natural := 3;
signal common_complex_mult_src_out_arr : t_dp_sosi_arr(g_nof_multipliers - 1 downto 0);
signal dp_pipeline_src_out_arr : t_dp_sosi_arr(g_nof_multipliers - 1 downto 0);
@@ -70,7 +73,8 @@ begin
g_variant => g_variant,
g_in_a_w => g_data_w,
g_in_b_w => g_data_w,
- g_out_p_w => 2 * g_data_w, -- default use g_out_p_w = g_in_a_w+g_in_b_w
+ -- default use g_out_p_w = g_in_a_w+g_in_b_w
+ g_out_p_w => 2 * g_data_w,
g_conjugate_b => g_conjugate_b
)
port map (
diff --git a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
index 2fafe0a210809bd5849bd512b51dc11ff4a022de..3083673b64c9675701eafd14a082a07b1f3ecbe2 100644
--- a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
@@ -30,16 +30,24 @@ use common_lib.common_pkg.all;
package dp_components_pkg is
constant c_dp_clk_MHz : natural := 200;
- constant c_dp_sync_timeout : natural := c_dp_clk_MHz * 10**6 + c_dp_clk_MHz * 10**5; -- 10% margin for nominal 1 s
+ -- 10% margin for nominal 1 s
+ constant c_dp_sync_timeout : natural := c_dp_clk_MHz * 10**6 + c_dp_clk_MHz * 10**5;
- constant c_dp_bsn_monitor_v2_reg_adr_w : natural := ceil_log2(7); -- = 3
- constant c_dp_bsn_monitor_v2_reg_adr_span : natural := 2**c_dp_bsn_monitor_v2_reg_adr_w; -- = 8
+ -- = 3
+ constant c_dp_bsn_monitor_v2_reg_adr_w : natural := ceil_log2(7);
+ -- = 8
+ constant c_dp_bsn_monitor_v2_reg_adr_span : natural := 2**c_dp_bsn_monitor_v2_reg_adr_w;
- constant c_dp_strobe_total_count_reg_nof_words : natural := 15 * 2 + 2; -- = 32
- constant c_dp_strobe_total_count_reg_adr_w : natural := ceil_log2(c_dp_strobe_total_count_reg_nof_words); -- = 5
- constant c_dp_strobe_total_count_reg_adr_span : natural := 2**c_dp_strobe_total_count_reg_adr_w; -- = 32
- constant c_dp_strobe_total_count_reg_nof_counts_max : natural := 2**c_dp_strobe_total_count_reg_adr_w / 2 - 1; -- = 15
- constant c_dp_strobe_total_count_reg_clear_adr : natural := c_dp_strobe_total_count_reg_nof_counts_max * 2; -- after counters in REGMAP
+ -- = 32
+ constant c_dp_strobe_total_count_reg_nof_words : natural := 15 * 2 + 2;
+ -- = 5
+ constant c_dp_strobe_total_count_reg_adr_w : natural := ceil_log2(c_dp_strobe_total_count_reg_nof_words);
+ -- = 32
+ constant c_dp_strobe_total_count_reg_adr_span : natural := 2**c_dp_strobe_total_count_reg_adr_w;
+ -- = 15
+ constant c_dp_strobe_total_count_reg_nof_counts_max : natural := 2**c_dp_strobe_total_count_reg_adr_w / 2 - 1;
+ -- after counters in REGMAP
+ constant c_dp_strobe_total_count_reg_clear_adr : natural := c_dp_strobe_total_count_reg_nof_counts_max * 2;
constant c_dp_strobe_total_count_reg_flush_adr : natural := c_dp_strobe_total_count_reg_nof_counts_max * 2 + 1;
end dp_components_pkg;
diff --git a/libraries/base/dp/src/vhdl/dp_concat.vhd b/libraries/base/dp/src/vhdl/dp_concat.vhd
index e2d6a58f0de31b72bf1c5cebac263981e076a05b..9b08dabaffd00ac93c0952c27ae1ae9af48fcb1f 100644
--- a/libraries/base/dp/src/vhdl/dp_concat.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat.vhd
@@ -68,8 +68,10 @@ use work.dp_stream_pkg.all;
entity dp_concat is
generic (
- g_data_w : natural := 16; -- >= 1
- g_symbol_w : natural := 8 -- >= 1, and g_data_w/g_symbol_w must be an integer
+ -- >= 1
+ g_data_w : natural := 16;
+ -- >= 1, and g_data_w/g_symbol_w must be an integer
+ g_symbol_w : natural := 8
);
port (
rst : in std_logic;
@@ -84,13 +86,16 @@ entity dp_concat is
end dp_concat;
architecture rtl of dp_concat is
- constant c_nof_symbols_per_data : natural := g_data_w / g_symbol_w; -- nof symbols per data
+ -- nof symbols per data
+ constant c_nof_symbols_per_data : natural := g_data_w / g_symbol_w;
constant c_empty_w : natural := ceil_log2(c_nof_symbols_per_data);
constant c_bsn_w : natural := c_dp_stream_bsn_w;
constant c_channel_w : natural := c_dp_stream_channel_w;
- constant c_head : natural := 0; -- head frame snk_in_arr port number
- constant c_tail : natural := 1; -- tail frame snk_in_arr port number
+ -- head frame snk_in_arr port number
+ constant c_head : natural := 0;
+ -- tail frame snk_in_arr port number
+ constant c_tail : natural := 1;
type t_state is (s_sop, s_head, s_tail, s_eop);
@@ -181,10 +186,13 @@ begin
p_state : process(state, src_in, i_src_out, pend_src_out_arr, prev_tail, head_bsn, head_channel, head_empty, head_empty_reg, tail_empty, out_empty_reg)
variable v_out_empty : std_logic_vector(c_empty_w - 1 downto 0);
begin
- i_snk_out_arr <= (others => c_dp_siso_rst); -- default not ready for input
- flush_arr <= (others => c_dp_siso_rst); -- default not ready to flush_arr hold input
+ -- default not ready for input
+ i_snk_out_arr <= (others => c_dp_siso_rst);
+ -- default not ready to flush_arr hold input
+ flush_arr <= (others => c_dp_siso_rst);
- nxt_src_out <= i_src_out; -- default no output
+ -- default no output
+ nxt_src_out <= i_src_out;
nxt_src_out.empty <= TO_DP_EMPTY(0);
nxt_src_out.sync <= '0';
nxt_src_out.valid <= '0';
@@ -210,8 +218,10 @@ begin
if pend_src_out_arr(c_head).sop = '0' then i_snk_out_arr(c_head) <= src_in; end if;
if pend_src_out_arr(c_tail).sop = '0' then i_snk_out_arr(c_tail) <= src_in; end if;
if pend_src_out_arr(c_head).sop = '1' and pend_src_out_arr(c_tail).sop = '1' then
- nxt_head_bsn <= pend_src_out_arr(c_head).bsn; -- keep head bsn during frame, the sync is defined at sop, so no need to keep sync during frame
- nxt_head_channel <= pend_src_out_arr(c_head).channel; -- keep head channel during frame
+ -- keep head bsn during frame, the sync is defined at sop, so no need to keep sync during frame
+ nxt_head_bsn <= pend_src_out_arr(c_head).bsn;
+ -- keep head channel during frame
+ nxt_head_channel <= pend_src_out_arr(c_head).channel;
nxt_state <= s_head;
end if;
@@ -220,42 +230,57 @@ begin
-- Input ready contol during head frame
if pend_src_out_arr(c_head).eop = '0' then
- i_snk_out_arr(c_head) <= src_in; -- head request until the eop has arrived
+ -- head request until the eop has arrived
+ i_snk_out_arr(c_head) <= src_in;
else
- flush_arr(c_head) <= src_in; -- also ready for hold input when the head eop is there
+ -- also ready for hold input when the head eop is there
+ flush_arr(c_head) <= src_in;
end if;
if src_in.ready = '1' then
-- Data output
- nxt_src_out <= pend_src_out_arr(c_head); -- head output (default data and control)
+ -- head output (default data and control)
+ nxt_src_out <= pend_src_out_arr(c_head);
if pend_src_out_arr(c_head).eop = '1' then
-- Concatenate last head data with the first tail data if the head has empty symbols, use head for control
nxt_src_out <= func_dp_data_shift_first(pend_src_out_arr(c_head), pend_src_out_arr(c_tail), g_symbol_w, c_nof_symbols_per_data, TO_UINT(head_empty));
end if;
- nxt_src_out.empty <= TO_DP_EMPTY(0); -- default keep output empty 0 when it is not known yet
+ -- default keep output empty 0 when it is not known yet
+ nxt_src_out.empty <= TO_DP_EMPTY(0);
-- Input ready contol at end of head frame
if pend_src_out_arr(c_head).eop = '1' then
-- End of head frame will be output
- nxt_head_empty_reg <= head_empty; -- capture the last head empty field (needed in s_tail and s_eop)
- nxt_prev_tail <= pend_src_out_arr(c_tail); -- capture the first tail data
+ -- capture the last head empty field (needed in s_tail and s_eop)
+ nxt_head_empty_reg <= head_empty;
+ -- capture the first tail data
+ nxt_prev_tail <= pend_src_out_arr(c_tail);
-- Begin the tail frame
- nxt_src_out.eop <= '0'; -- default assume the head eop will not be the output eop
- if pend_src_out_arr(c_tail).eop = '0' then -- use pend_src_out_arr because it shows the active control independent of hold_scr_in().ready
- i_snk_out_arr(c_tail) <= c_dp_siso_rdy; -- tail request until the eop has arrived
+ -- default assume the head eop will not be the output eop
+ nxt_src_out.eop <= '0';
+ -- use pend_src_out_arr because it shows the active control independent of hold_scr_in().ready
+ if pend_src_out_arr(c_tail).eop = '0' then
+ -- tail request until the eop has arrived
+ i_snk_out_arr(c_tail) <= c_dp_siso_rdy;
nxt_state <= s_tail;
else
-- Support tail frame of 1 word
- if TO_UINT(head_empty) + TO_UINT(tail_empty) >= c_nof_symbols_per_data then -- Output frame also fits in 1 word
+ -- Output frame also fits in 1 word
+ if TO_UINT(head_empty) + TO_UINT(tail_empty) >= c_nof_symbols_per_data then
nxt_src_out.empty <= RESIZE_DP_EMPTY(func_dp_empty_concat(head_empty, tail_empty, c_nof_symbols_per_data));
- nxt_src_out.eop <= '1'; -- output eop
- i_snk_out_arr <= (others => c_dp_siso_rdy); -- request next pair of frames
+ -- output eop
+ nxt_src_out.eop <= '1';
+ -- request next pair of frames
+ i_snk_out_arr <= (others => c_dp_siso_rdy);
nxt_state <= s_sop;
- else -- Output frame needs 2 words
- flush_arr(c_tail) <= c_dp_siso_rdy; -- also ready for hold input when the tail eop is there
+ -- Output frame needs 2 words
+ else
+ -- also ready for hold input when the tail eop is there
+ flush_arr(c_tail) <= c_dp_siso_rdy;
v_out_empty := func_dp_empty_concat(head_empty_reg, tail_empty, c_nof_symbols_per_data);
- nxt_out_empty_reg <= v_out_empty; -- capture the output empty field (needed in s_eop)
+ -- capture the output empty field (needed in s_eop)
+ nxt_out_empty_reg <= v_out_empty;
nxt_state <= s_eop;
end if;
end if;
@@ -267,34 +292,41 @@ begin
-- Input ready contol during tail frame
if pend_src_out_arr(c_tail).eop = '0' then
- i_snk_out_arr(c_tail) <= src_in; -- tail request until the eop has arrived
+ -- tail request until the eop has arrived
+ i_snk_out_arr(c_tail) <= src_in;
else
- flush_arr(c_tail) <= src_in; -- also ready for hold input when the tail eop is there
+ -- also ready for hold input when the tail eop is there
+ flush_arr(c_tail) <= src_in;
end if;
if src_in.ready = '1' then
-- Data output
if pend_src_out_arr(c_tail).valid = '1' then
-- Tail data will be passed on when src_in was ready and snk_in_arr() is valid, but the data part needs shift if head_empty_reg /= 0
- nxt_prev_tail <= pend_src_out_arr(c_tail); -- capture the tail data
+ -- capture the tail data
+ nxt_prev_tail <= pend_src_out_arr(c_tail);
-- Shift tail output if head had empty symbols, default prev_tail for head_empty_reg = 0
nxt_src_out <= func_dp_data_shift(prev_tail, pend_src_out_arr(c_tail), g_symbol_w, c_nof_symbols_per_data, TO_UINT(head_empty_reg));
end if;
- nxt_src_out.empty <= TO_DP_EMPTY(0); -- default keep output empty 0 when it is not known yet
+ -- default keep output empty 0 when it is not known yet
+ nxt_src_out.empty <= TO_DP_EMPTY(0);
-- Input ready contol at end of tail frame
if pend_src_out_arr(c_tail).eop = '1' then
v_out_empty := func_dp_empty_concat(head_empty_reg, tail_empty, c_nof_symbols_per_data);
- nxt_out_empty_reg <= v_out_empty; -- capture the output empty field (needed in s_eop)
+ -- capture the output empty field (needed in s_eop)
+ nxt_out_empty_reg <= v_out_empty;
-- End of tail frame will be output
if TO_UINT(head_empty_reg) + TO_UINT(tail_empty) >= c_nof_symbols_per_data then
-- last tail frame data also fits in this output frame data
nxt_src_out.empty <= RESIZE_DP_EMPTY(v_out_empty);
- i_snk_out_arr <= (others => c_dp_siso_rdy); -- request next pair of frames
+ -- request next pair of frames
+ i_snk_out_arr <= (others => c_dp_siso_rdy);
nxt_state <= s_sop;
else
-- output frame needs one more word
- nxt_src_out.eop <= '0'; -- no eop yet
+ -- no eop yet
+ nxt_src_out.eop <= '0';
nxt_state <= s_eop;
end if;
end if;
@@ -306,13 +338,15 @@ begin
nxt_src_out.bsn <= head_bsn;
nxt_src_out.channel <= head_channel;
- when others => -- s_eop
+ -- s_eop
+ when others =>
-- Tail output last symbols (default inactive control, use data from prev_tail when src_in ready)
if src_in.ready = '1' then
-- Shift tail output if head had empty symbols, default prev_tail for head_empty_reg = 0
nxt_src_out <= func_dp_data_shift(prev_tail, prev_tail, g_symbol_w, c_nof_symbols_per_data, TO_UINT(head_empty_reg));
nxt_src_out.empty <= RESIZE_DP_EMPTY(v_out_empty);
- i_snk_out_arr <= (others => c_dp_siso_rdy); -- request next pair of frames
+ -- request next pair of frames
+ i_snk_out_arr <= (others => c_dp_siso_rdy);
nxt_state <= s_sop;
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
index c115e41e883e85637f1ea7bc9eac1a4fbb1e4d4d..07c66eeeaea0cf552a601b2283103b8b36f83f16 100644
--- a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
@@ -49,8 +49,10 @@ entity dp_concat_field_blk is
g_nof_streams : natural;
g_data_w : natural;
g_symbol_w : natural;
- g_hdr_field_arr : t_common_field_arr; -- User defined header fields
- g_hdr_field_sel : std_logic_vector; -- For each header field, select the source: 0=data path, 1=MM controlled
+ -- User defined header fields
+ g_hdr_field_arr : t_common_field_arr;
+ -- For each header field, select the source: 0=data path, 1=MM controlled
+ g_hdr_field_sel : std_logic_vector;
g_pipeline_ready : boolean := false
);
port (
@@ -69,7 +71,8 @@ entity dp_concat_field_blk is
src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0);
src_in_arr : in t_dp_siso_arr(g_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
- hdr_fields_in_arr : in t_slv_1024_arr(g_nof_streams - 1 downto 0) -- hdr_fields_in_arr(i) is considered valid @ snk_in_arr(i).sop
+ -- hdr_fields_in_arr(i) is considered valid @ snk_in_arr(i).sop
+ hdr_fields_in_arr : in t_slv_1024_arr(g_nof_streams - 1 downto 0)
);
end dp_concat_field_blk;
@@ -111,8 +114,10 @@ begin
-- dp_field_blk_snk_in_arr as a single word header block.
dp_field_blk_snk_in_arr(i).data <= RESIZE_DP_DATA(hdr_fields_in_arr(i)(field_slv_len(g_hdr_field_arr) - 1 downto 0));
dp_field_blk_snk_in_arr(i).valid <= snk_in_arr(i).sop;
- dp_field_blk_snk_in_arr(i).sop <= snk_in_arr(i).sop; -- necessary for single word header block
- dp_field_blk_snk_in_arr(i).eop <= snk_in_arr(i).sop; -- necessary for single word header block
+ -- necessary for single word header block
+ dp_field_blk_snk_in_arr(i).sop <= snk_in_arr(i).sop;
+ -- necessary for single word header block
+ dp_field_blk_snk_in_arr(i).eop <= snk_in_arr(i).sop;
end loop;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_counter.vhd b/libraries/base/dp/src/vhdl/dp_counter.vhd
index 9748348ee2a86f2031e137f3ef2834fb75fdf7eb..da8db8a54cadaa3636bc9cea5c6ff0b586e943db 100644
--- a/libraries/base/dp/src/vhdl/dp_counter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter.vhd
@@ -71,11 +71,16 @@ use work.dp_stream_pkg.all;
entity dp_counter is
generic (
g_nof_counters : natural := 1;
- g_range_start : t_nat_natural_arr; -- range must fit (g_nof_counters-1 DOWNTO 0)
- g_range_stop : t_nat_natural_arr; -- range must fit (g_nof_counters-1 DOWNTO 0)
- g_range_step : t_nat_natural_arr; -- range must fit (g_nof_counters-1 DOWNTO 0)
- g_pipeline_src_out : natural := 1; -- Pipeline source outputs (data,valid,sop,eop etc)
- g_pipeline_src_in : natural := 0 -- Pipeline source inputs (ready,xon). This will also pipeline src_out.
+ -- range must fit (g_nof_counters-1 DOWNTO 0)
+ g_range_start : t_nat_natural_arr;
+ -- range must fit (g_nof_counters-1 DOWNTO 0)
+ g_range_stop : t_nat_natural_arr;
+ -- range must fit (g_nof_counters-1 DOWNTO 0)
+ g_range_step : t_nat_natural_arr;
+ -- Pipeline source outputs (data,valid,sop,eop etc)
+ g_pipeline_src_out : natural := 1;
+ -- Pipeline source inputs (ready,xon). This will also pipeline src_out.
+ g_pipeline_src_in : natural := 0
);
port (
clk : in std_logic;
@@ -94,7 +99,8 @@ end dp_counter;
architecture wrap of dp_counter is
-- force downto range for unconstraint g_range generics
- constant c_range_len : natural := g_range_start'length; -- g_nof_counters must be <= c_range_len
+ -- g_nof_counters must be <= c_range_len
+ constant c_range_len : natural := g_range_start'length;
constant c_range_start : t_nat_natural_arr(c_range_len - 1 downto 0) := g_range_start;
constant c_range_stop : t_nat_natural_arr(c_range_len - 1 downto 0) := g_range_stop;
constant c_range_step : t_nat_natural_arr(c_range_len - 1 downto 0) := g_range_step;
diff --git a/libraries/base/dp/src/vhdl/dp_counter_func.vhd b/libraries/base/dp/src/vhdl/dp_counter_func.vhd
index 89431450ddc9d374bc5029dfa76a666ae1b79374..2aa9b248063925946ef46df6a2478ff8580a5c83 100644
--- a/libraries/base/dp/src/vhdl/dp_counter_func.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter_func.vhd
@@ -46,9 +46,12 @@ use work.dp_stream_pkg.all;
entity dp_counter_func is
generic (
g_nof_counters : natural := 1;
- g_range_start : t_nat_natural_arr; -- range must fit (g_nof_counters-1 DOWNTO 0)
- g_range_stop : t_nat_natural_arr; -- range must fit (g_nof_counters-1 DOWNTO 0)
- g_range_step : t_nat_natural_arr -- range must fit (g_nof_counters-1 DOWNTO 0)
+ -- range must fit (g_nof_counters-1 DOWNTO 0)
+ g_range_start : t_nat_natural_arr;
+ -- range must fit (g_nof_counters-1 DOWNTO 0)
+ g_range_stop : t_nat_natural_arr;
+ -- range must fit (g_nof_counters-1 DOWNTO 0)
+ g_range_step : t_nat_natural_arr
);
port (
clk : in std_logic;
@@ -63,7 +66,8 @@ end dp_counter_func;
architecture str of dp_counter_func is
-- force downto range for unconstraint g_range generics
- constant c_range_len : natural := g_range_start'length; -- g_nof_counters must be <= c_range_len
+ -- g_nof_counters must be <= c_range_len
+ constant c_range_len : natural := g_range_start'length;
constant c_range_start : t_nat_natural_arr(c_range_len - 1 downto 0) := g_range_start;
constant c_range_stop : t_nat_natural_arr(c_range_len - 1 downto 0) := g_range_stop;
constant c_range_step : t_nat_natural_arr(c_range_len - 1 downto 0) := g_range_step;
@@ -123,7 +127,8 @@ begin
-- Counter outputs
-------------------------------------------------------------------------------
gen_dp_counter_func_single_output : for i in 0 to g_nof_counters - 1 generate
- count_src_out_arr(i).sync <= '0'; -- not used, force to '0' to avoid toggling between '0' and 'X' in Wave window
+ -- not used, force to '0' to avoid toggling between '0' and 'X' in Wave window
+ count_src_out_arr(i).sync <= '0';
-- when sync is passed on through other components
count_src_out_arr(i).sop <= count_min_arr(i);
count_src_out_arr(i).eop <= count_max_arr(i);
diff --git a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
index 01c3d94c4a083a11f3794596d02ae05a34bf6f91..9d8cbd7572fdcfc66b190ccac1f6b02f57f1b089 100644
--- a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
@@ -34,9 +34,11 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use work.dp_stream_pkg.all;
-entity dp_counter_func_single is -- FIXME move this to common
+-- FIXME move this to common
+entity dp_counter_func_single is
generic (
- g_range_start : natural; -- (start,stop,step) like python range(start, stop, step)
+ -- (start,stop,step) like python range(start, stop, step)
+ g_range_start : natural;
g_range_stop : natural;
g_range_step : natural
);
@@ -49,9 +51,12 @@ entity dp_counter_func_single is -- FIXME move this to common
count_offset : natural := 0;
count : out std_logic_vector(31 downto 0);
- count_init : out std_logic; -- Pulses at first init
- count_min : out std_logic; -- Pulses when count=start
- count_max : out std_logic -- Pulses when count=max
+ -- Pulses at first init
+ count_init : out std_logic;
+ -- Pulses when count=start
+ count_min : out std_logic;
+ -- Pulses when count=max
+ count_max : out std_logic
);
end dp_counter_func_single;
@@ -101,9 +106,11 @@ begin
-- keep counting
else
v.count := INCR_UVEC(r.count, g_range_step);
- if c_count_max > 0 and check_max = '1' and r.count = TO_UVEC(c_count_max - g_range_step, c_count_w) then -- count max almost reached
+ -- count max almost reached
+ if c_count_max > 0 and check_max = '1' and r.count = TO_UVEC(c_count_max - g_range_step, c_count_w) then
v.count_max := '1';
- elsif r.count = TO_UVEC(c_count_max, c_count_w) then -- count max reached
+ -- count max reached
+ elsif r.count = TO_UVEC(c_count_max, c_count_w) then
-- Reset count to start value
v.count := TO_UVEC(g_range_start, c_count_w);
v.count_min := '1';
@@ -115,7 +122,8 @@ begin
v.count_max := '1';
end if;
- elsif check_max = '1' and r.count = TO_UVEC(c_count_max, c_count_w) then -- count max reached
+ -- count max reached
+ elsif check_max = '1' and r.count = TO_UVEC(c_count_max, c_count_w) then
v.count_max := '1';
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_deinterleave.vhd b/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
index e652bad0f33602eaf96897dd7ae3742d9a380e17..29a6fe303ef6e7eabe4f9c3ab6c3bd14ec129421 100644
--- a/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
+++ b/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
@@ -43,12 +43,17 @@ entity dp_deinterleave is
generic (
g_dat_w : natural;
g_nof_out : natural;
- g_block_size_int : natural; -- Deinterleaver block size; outputs g_block_size_int words before switching to next output
- g_block_size_output : natural; -- Output block size: The number of samles in the blocks at the output
- g_use_ctrl : boolean := true; -- Requires: [input block size (sop:eop)] / [g_nof_out]/ [g_block_size_output] = integer number!
- g_use_sync_bsn : boolean := true; -- forwards (stored) input Sync+BSN to all output streams
+ -- Deinterleaver block size; outputs g_block_size_int words before switching to next output
+ g_block_size_int : natural;
+ -- Output block size: The number of samles in the blocks at the output
+ g_block_size_output : natural;
+ -- Requires: [input block size (sop:eop)] / [g_nof_out]/ [g_block_size_output] = integer number!
+ g_use_ctrl : boolean := true;
+ -- forwards (stored) input Sync+BSN to all output streams
+ g_use_sync_bsn : boolean := true;
g_use_complex : boolean;
- g_align_out : boolean := false -- Aligns the output streams
+ -- Aligns the output streams
+ g_align_out : boolean := false
);
port (
rst : in std_logic;
@@ -157,8 +162,10 @@ begin
rst => rst,
clk => clk,
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in, -- original snk_in info
+ -- delayed snk_in data
+ data_snk_in => dp_block_gen_src_out_arr(i),
+ -- original snk_in info
+ info_snk_in => snk_in,
src_in => c_dp_siso_rdy,
src_out => src_out_arr(i)
diff --git a/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd b/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
index aea3de86d75eeb404cded71d73fb6ba2e9b20b91..5eb2246f21bd6a1d524946e8852cd5a3e9368e72 100755
--- a/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
+++ b/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
@@ -49,7 +49,8 @@ use work.dp_stream_pkg.all;
entity dp_deinterleave_one_to_n is
generic (
- g_pipeline : natural := 1; -- 0 for combinatorial, > 0 for registers
+ -- 0 for combinatorial, > 0 for registers
+ g_pipeline : natural := 1;
g_nof_outputs : natural
);
port (
@@ -70,8 +71,10 @@ architecture rtl of dp_deinterleave_one_to_n is
input_arr : t_dp_sosi_arr(g_nof_outputs - 1 downto 0);
end record;
- signal s : t_reg; -- combinatoral state
- signal r : t_reg; -- register state
+ -- combinatoral state
+ signal s : t_reg;
+ -- register state
+ signal r : t_reg;
signal out_siso_arr : t_dp_siso_arr(g_nof_outputs - 1 downto 0);
signal out_sosi_arr : t_dp_sosi_arr(g_nof_outputs - 1 downto 0);
@@ -91,12 +94,14 @@ begin
begin
s.cnt <= r.cnt;
if snk_in.sop = '1' then
- s.cnt <= 0; -- wrap or force restart at sop
+ -- wrap or force restart at sop
+ s.cnt <= 0;
elsif snk_in.valid = '1' then
if r.cnt < g_nof_outputs - 1 then
s.cnt <= r.cnt + 1;
else
- s.cnt <= 0; -- wrap after every g_nof_outputs valid input samples
+ -- wrap after every g_nof_outputs valid input samples
+ s.cnt <= 0;
end if;
end if;
end process;
@@ -146,12 +151,14 @@ begin
end process;
-- Register and pass on flow control
- snk_out <= out_siso_arr(0); -- all out_siso_arr have the same siso, so wire output 0
+ -- all out_siso_arr have the same siso, so wire output 0
+ snk_out <= out_siso_arr(0);
u_pipeline_outputs : entity work.dp_pipeline_arr
generic map (
g_nof_streams => g_nof_outputs,
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
+ -- 0 for wires, > 0 for registers
+ g_pipeline => g_pipeline
)
port map (
rst => rst,
diff --git a/libraries/base/dp/src/vhdl/dp_demux.vhd b/libraries/base/dp/src/vhdl/dp_demux.vhd
index f70721856d148527ca0ca2e041dab4a0107c098d..89c03e982caf450ab232df5e88f6e80604c21704 100644
--- a/libraries/base/dp/src/vhdl/dp_demux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_demux.vhd
@@ -60,18 +60,23 @@ use work.dp_stream_pkg.all;
entity dp_demux is
generic (
g_mode : natural := 0;
- g_nof_output : natural := 2; -- >= 1
+ -- >= 1
+ g_nof_output : natural := 2;
g_remove_channel_lo : boolean := true;
g_combined : boolean := true;
- g_sel_ctrl_invert : boolean := false; -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
- g_sel_ctrl_pkt : boolean := false -- When TRUE and g_mode=2 and g_combined=FALSE, this selects a new output on packet boundaries only.
+ -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ g_sel_ctrl_invert : boolean := false;
+ -- When TRUE and g_mode=2 and g_combined=FALSE, this selects a new output on packet boundaries only.
+ g_sel_ctrl_pkt : boolean := false
);
port (
rst : in std_logic;
clk : in std_logic;
-- Control & Status
- sel_ctrl : in natural range 0 to g_nof_output - 1 := 0; -- used by g_mode = 2
- sel_stat : out natural range 0 to g_nof_output - 1; -- used by g_sel_ctrl_pkt = TRUE
+ -- used by g_mode = 2
+ sel_ctrl : in natural range 0 to g_nof_output - 1 := 0;
+ -- used by g_sel_ctrl_pkt = TRUE
+ sel_stat : out natural range 0 to g_nof_output - 1;
-- ST sinks
snk_out : out t_dp_siso;
snk_in : in t_dp_sosi;
@@ -86,8 +91,10 @@ architecture rtl of dp_demux is
constant c_sel_w : natural := true_log2(g_nof_output);
-- Output selection scheme
- signal sel_channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0); -- used by g_mode = 0
- signal sel_eop : std_logic; -- used by g_mode = 1
+ -- used by g_mode = 0
+ signal sel_channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0);
+ -- used by g_mode = 1
+ signal sel_eop : std_logic;
signal output_select : natural range 0 to g_nof_output - 1;
signal prev_output_select : natural range 0 to g_nof_output - 1;
signal pkt_det : std_logic;
@@ -102,7 +109,8 @@ begin
-- Collapse to wires
gen_one : if g_nof_output = 1 generate
snk_out <= src_in_arr(0);
- src_out_arr(0) <= snk_in; -- so c_sel_w = 0
+ -- so c_sel_w = 0
+ src_out_arr(0) <= snk_in;
end generate;
------------------------------------------------------------------------------
@@ -189,7 +197,8 @@ begin
rst => rst,
clk => clk,
sosi => adapt_sosi,
- siso => adapt_siso, -- We're using the adapted sink_in with RL=0
+ -- We're using the adapted sink_in with RL=0
+ siso => adapt_siso,
pkt_det => pkt_det
);
end generate;
@@ -216,7 +225,8 @@ begin
src_out_arr(I).sop <= '0';
src_out_arr(I).eop <= '0';
if g_remove_channel_lo = true then
- src_out_arr(I).channel <= SHIFT_UVEC(snk_in.channel, c_sel_w); -- strip the low part that is used for the demux from the channel field
+ -- strip the low part that is used for the demux from the channel field
+ src_out_arr(I).channel <= SHIFT_UVEC(snk_in.channel, c_sel_w);
end if;
if output_select = I then
src_out_arr(I).sync <= snk_in.sync;
@@ -251,7 +261,8 @@ begin
);
sel_channel <= adapt_sosi.channel;
- sel_eop <= adapt_sosi.eop and adapt_siso.ready; -- RL = 0, so eop is only valid when the ready acknowledges it
+ -- RL = 0, so eop is only valid when the ready acknowledges it
+ sel_eop <= adapt_sosi.eop and adapt_siso.ready;
-- Demux at RL = 0
p_output : process(adapt_sosi, prev_src_in_arr, output_select)
@@ -264,7 +275,8 @@ begin
pend_src_out_arr(I).sop <= '0';
pend_src_out_arr(I).eop <= '0';
if g_remove_channel_lo = true then
- pend_src_out_arr(I).channel <= SHIFT_UVEC(adapt_sosi.channel, c_sel_w); -- strip the low part that is used for the demux from the channel field
+ -- strip the low part that is used for the demux from the channel field
+ pend_src_out_arr(I).channel <= SHIFT_UVEC(adapt_sosi.channel, c_sel_w);
end if;
if output_select = I then
adapt_siso <= prev_src_in_arr(I);
diff --git a/libraries/base/dp/src/vhdl/dp_distribute.vhd b/libraries/base/dp/src/vhdl/dp_distribute.vhd
index 4165fd637055cd2ac3a3fb7b73ad9388147200f9..bf39a7cb07cbbec2db99f7a2e17bf5881f052798 100644
--- a/libraries/base/dp/src/vhdl/dp_distribute.vhd
+++ b/libraries/base/dp/src/vhdl/dp_distribute.vhd
@@ -87,14 +87,20 @@ entity dp_distribute is
g_technology : natural := c_tech_select_default;
-- Distribution IO
g_tx : boolean;
- g_nof_input : natural := 4; -- >= 1
- g_nof_output : natural := 3; -- >= 1
+ -- >= 1
+ g_nof_input : natural := 4;
+ -- >= 1
+ g_nof_output : natural := 3;
g_transpose : boolean := false;
- g_code_channel_lo : boolean := false; -- for DP packet optionaly transport the mux channel_lo bits via the CHAN field
- g_data_w : natural := 16; -- actual sosi data width, used for FIFO and for dp_packet_en_channel_lo
+ -- for DP packet optionaly transport the mux channel_lo bits via the CHAN field
+ g_code_channel_lo : boolean := false;
+ -- actual sosi data width, used for FIFO and for dp_packet_en_channel_lo
+ g_data_w : natural := 16;
-- Scheduling
- g_tx_mux_mode : natural := 0; -- default 0 for non-blocking mux, but 1 also works in simulation and on hardware provided that the inputs are garantueed to arrive
- g_rx_mux_mode : natural := 0; -- default 0 for non-blocking mux, but 1 also works in simulation and on hardware provided that the inputs are garantueed to arrive
+ -- default 0 for non-blocking mux, but 1 also works in simulation and on hardware provided that the inputs are garantueed to arrive
+ g_tx_mux_mode : natural := 0;
+ -- default 0 for non-blocking mux, but 1 also works in simulation and on hardware provided that the inputs are garantueed to arrive
+ g_rx_mux_mode : natural := 0;
-- Input FIFO
g_use_fifo : boolean := false;
g_bsn_w : natural := 1;
@@ -106,9 +112,11 @@ entity dp_distribute is
g_use_channel : boolean := false;
g_use_error : boolean := false;
g_use_sync : boolean := false;
- g_fifo_af_margin : natural := 4; -- Nof words below max (full) at which fifo is considered almost full
+ -- Nof words below max (full) at which fifo is considered almost full
+ g_fifo_af_margin : natural := 4;
g_fifo_fill : natural := 0;
- g_fifo_size : natural := 256 -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
+ -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size : natural := 256
);
port (
rst : in std_logic;
@@ -129,8 +137,10 @@ architecture str of dp_distribute is
constant c_mux_mode : natural := sel_a_b(g_tx, g_tx_mux_mode, g_rx_mux_mode);
constant c_mux_append_channel_lo : boolean := g_tx;
- constant g_encode_channel_lo : boolean := g_tx and g_code_channel_lo; -- true only for transmit to link
- constant g_decode_channel_lo : boolean := not g_tx and g_code_channel_lo; -- true only for receive from link
+ -- true only for transmit to link
+ constant g_encode_channel_lo : boolean := g_tx and g_code_channel_lo;
+ -- true only for receive from link
+ constant g_decode_channel_lo : boolean := not g_tx and g_code_channel_lo;
constant c_link_channel_lo : natural := sel_a_b(g_tx, ceil_log2(g_nof_input), ceil_log2(g_nof_output));
type t_demux_siso_2arr is array (integer range <>) of t_dp_siso_arr(0 to g_nof_output - 1);
@@ -138,15 +148,20 @@ architecture str of dp_distribute is
type t_mux_siso_2arr is array (integer range <>) of t_dp_siso_arr(0 to g_nof_input - 1);
type t_mux_sosi_2arr is array (integer range <>) of t_dp_sosi_arr(0 to g_nof_input - 1);
- signal in_siso_arr : t_dp_siso_arr(0 to g_nof_input - 1); -- from snk_* for ST after optional input FIFO
+ -- from snk_* for ST after optional input FIFO
+ signal in_siso_arr : t_dp_siso_arr(0 to g_nof_input - 1);
signal in_sosi_arr : t_dp_sosi_arr(0 to g_nof_input - 1);
- signal rx_siso_arr : t_dp_siso_arr(0 to g_nof_input - 1); -- ST after optional decoding
+ -- ST after optional decoding
+ signal rx_siso_arr : t_dp_siso_arr(0 to g_nof_input - 1);
signal rx_sosi_arr : t_dp_sosi_arr(0 to g_nof_input - 1);
- signal demux_siso_2arr : t_demux_siso_2arr(0 to g_nof_input - 1); -- ST at output of demux
+ -- ST at output of demux
+ signal demux_siso_2arr : t_demux_siso_2arr(0 to g_nof_input - 1);
signal demux_sosi_2arr : t_demux_sosi_2arr(0 to g_nof_input - 1);
- signal mux_siso_2arr : t_mux_siso_2arr(0 to g_nof_output - 1); -- ST rewired for input to mux
+ -- ST rewired for input to mux
+ signal mux_siso_2arr : t_mux_siso_2arr(0 to g_nof_output - 1);
signal mux_sosi_2arr : t_mux_sosi_2arr(0 to g_nof_output - 1);
- signal tx_siso_arr : t_dp_siso_arr(0 to g_nof_output - 1); -- ST at output of mux, to src_* for ST output after optional encoding
+ -- ST at output of mux, to src_* for ST output after optional encoding
+ signal tx_siso_arr : t_dp_siso_arr(0 to g_nof_output - 1);
signal tx_sosi_arr : t_dp_sosi_arr(0 to g_nof_output - 1);
begin
no_fifo : if g_use_fifo = false generate
@@ -255,8 +270,10 @@ begin
g_append_channel_lo => c_mux_append_channel_lo,
-- Input FIFO
g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, g_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_size => array_init(1024, g_nof_input),
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, g_nof_input)
)
port map (
rst => rst,
diff --git a/libraries/base/dp/src/vhdl/dp_dummy_source.vhd b/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
index 33b96ad56573de75c40d0db3be6ade34afc6d8a7..f51589e5597b7129dd39046688e500d79ba799df 100644
--- a/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
@@ -30,7 +30,8 @@ use work.dp_stream_pkg.all;
entity dp_dummy_source is
generic (
- g_dummy_nof_data : natural := 100; -- Nof words per block
+ -- Nof words per block
+ g_dummy_nof_data : natural := 100;
g_dummy_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := x"DDDDDDDD_DDDDDDDD";
g_dummy_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0) := x"DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD";
g_dummy_re : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0) := x"DDDDDDDD_DDDDDDDD";
diff --git a/libraries/base/dp/src/vhdl/dp_example_dut.vhd b/libraries/base/dp/src/vhdl/dp_example_dut.vhd
index 5492efb3861b530acbbba5423b04ea2eace9526c..921ba4219e07f5171764ba59791c6d478912a4dd 100644
--- a/libraries/base/dp/src/vhdl/dp_example_dut.vhd
+++ b/libraries/base/dp/src/vhdl/dp_example_dut.vhd
@@ -182,8 +182,10 @@ end dp_example_dut;
architecture rtl of dp_example_dut is
type t_reg is record
- src_out : t_dp_sosi; -- sosi output
- hold_out : t_dp_sosi; -- hold snk_in.sync/sop/eop until end of section and then hold valid src_out until src_in.ready
+ -- sosi output
+ src_out : t_dp_sosi;
+ -- hold snk_in.sync/sop/eop until end of section and then hold valid src_out until src_in.ready
+ hold_out : t_dp_sosi;
end record;
signal r_snk_out : t_dp_siso := c_dp_siso_rdy;
@@ -230,9 +232,11 @@ begin
if snk_in.valid = '1' then
--< start of component function >
- v.src_out.data := snk_in.data; -- pipeline function as example
+ -- pipeline function as example
+ v.src_out.data := snk_in.data;
- v.hold_out.valid := '1'; -- the function has new data to output
+ -- the function has new data to output
+ v.hold_out.valid := '1';
--< end of component function >
end if;
@@ -288,6 +292,8 @@ begin
end process;
-- combined local and remote src_in flow control
- snk_out.ready <= r_snk_out.ready when nxt_r.hold_out.valid = '0' else src_in.ready; -- if there is pending output then the src_in ready determines the flow control
- snk_out.xon <= src_in.xon; -- just pass on the xon/off frame flow control
+ -- if there is pending output then the src_in ready determines the flow control
+ snk_out.ready <= r_snk_out.ready when nxt_r.hold_out.valid = '0' else src_in.ready;
+ -- just pass on the xon/off frame flow control
+ snk_out.xon <= src_in.xon;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_field_blk.vhd b/libraries/base/dp/src/vhdl/dp_field_blk.vhd
index abab9714879e983e963cad92c815c9542e56e933..fd5d2da13074c86e3167f22d1dd7606f2b9b03b4 100644
--- a/libraries/base/dp/src/vhdl/dp_field_blk.vhd
+++ b/libraries/base/dp/src/vhdl/dp_field_blk.vhd
@@ -92,7 +92,8 @@ entity dp_field_blk is
g_in_symbol_w : natural := 1;
g_out_symbol_w : natural := 1;
g_pipeline_ready : boolean := false;
- g_mode : natural := 0 -- 0 = auto, 1 = source , 2 = sink
+ -- 0 = auto, 1 = source , 2 = sink
+ g_mode : natural := 0
);
port (
dp_rst : in std_logic;
@@ -139,10 +140,12 @@ architecture str of dp_field_blk is
constant c_mm_fields_slv_out_w : natural := sel_a_b(c_field_to_block, g_snk_data_w, 0);
signal mm_fields_slv_in : std_logic_vector(c_mm_fields_slv_in_w - 1 downto 0);
- signal mm_fields_slv_in_val : std_logic := '0'; -- default '0' when c_field_to_block = TRUE
+ -- default '0' when c_field_to_block = TRUE
+ signal mm_fields_slv_in_val : std_logic := '0';
signal mm_fields_slv_out : std_logic_vector(c_mm_fields_slv_out_w - 1 downto 0);
- signal field_override_arr : std_logic_vector(g_field_arr'range) := g_field_sel; -- 1 override bit per field
+ -- 1 override bit per field
+ signal field_override_arr : std_logic_vector(g_field_arr'range) := g_field_sel;
signal dp_repack_data_snk_in : t_dp_sosi := c_dp_sosi_rst;
signal dp_repack_data_snk_out : t_dp_siso;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
index b611fd279702d92d701adc16f58cdb88faec7984..85b3615766702e1bdbc1977a70a6f89de0f346c7 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
@@ -49,11 +49,15 @@ use technology_lib.technology_select_pkg.all;
entity dp_fifo_core is
generic (
g_technology : natural := c_tech_select_default;
- g_note_is_ful : boolean := true; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_note_is_ful : boolean := true;
g_use_dual_clock : boolean := false;
- g_use_lut_sc : boolean := false; -- when TRUE then force using LUTs instead of block RAM for single clock FIFO (bot available for dual clock FIFO)
- g_data_w : natural := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
- g_data_signed : boolean := false; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ -- when TRUE then force using LUTs instead of block RAM for single clock FIFO (bot available for dual clock FIFO)
+ g_use_lut_sc : boolean := false;
+ -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_w : natural := 16;
+ -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ g_data_signed : boolean := false;
g_bsn_w : natural := 1;
g_empty_w : natural := 1;
g_channel_w : natural := 1;
@@ -63,11 +67,16 @@ entity dp_fifo_core is
g_use_channel : boolean := false;
g_use_error : boolean := false;
g_use_sync : boolean := false;
- g_use_ctrl : boolean := true; -- sop & eop
- g_use_complex : boolean := false; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size : natural := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : natural := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
- g_fifo_af_xon : natural := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ -- sop & eop
+ g_use_ctrl : boolean := true;
+ -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_use_complex : boolean := false;
+ -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size : natural := 512;
+ -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_margin : natural := 4;
+ -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ g_fifo_af_xon : natural := 0;
g_fifo_rl : natural := 1
);
port (
@@ -76,7 +85,8 @@ entity dp_fifo_core is
rd_rst : in std_logic;
rd_clk : in std_logic;
-- Monitor FIFO filling
- wr_ful : out std_logic; -- corresponds to the carry bit of wr_usedw when FIFO is full
+ -- corresponds to the carry bit of wr_usedw when FIFO is full
+ wr_ful : out std_logic;
wr_usedw : out std_logic_vector(ceil_log2(g_fifo_size) - 1 downto 0);
rd_usedw : out std_logic_vector(ceil_log2(g_fifo_size) - 1 downto 0);
rd_emp : out std_logic;
@@ -91,14 +101,19 @@ end dp_fifo_core;
architecture str of dp_fifo_core is
constant c_use_data : boolean := true;
- constant c_ctrl_w : natural := 2; -- sop and eop
+ -- sop and eop
+ constant c_ctrl_w : natural := 2;
- constant c_complex_w : natural := smallest(c_dp_stream_dsp_data_w, g_data_w / 2); -- needed to cope with g_data_w > 2*c_dp_stream_dsp_data_w
+ -- needed to cope with g_data_w > 2*c_dp_stream_dsp_data_w
+ constant c_complex_w : natural := smallest(c_dp_stream_dsp_data_w, g_data_w / 2);
- constant c_fifo_almost_full : natural := g_fifo_size - g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
- constant c_fifo_almost_xon : natural := g_fifo_size - g_fifo_af_xon; -- FIFO almost full level for snk_out.xon
+ -- FIFO almost full level for snk_out.ready
+ constant c_fifo_almost_full : natural := g_fifo_size - g_fifo_af_margin;
+ -- FIFO almost full level for snk_out.xon
+ constant c_fifo_almost_xon : natural := g_fifo_size - g_fifo_af_xon;
constant c_fifo_dat_w : natural := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl,
- g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w); -- concat via FIFO
+ -- concat via FIFO
+ g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w);
signal nxt_snk_out : t_dp_siso := c_dp_siso_rst;
@@ -126,7 +141,8 @@ architecture str of dp_fifo_core is
signal rd_ctrl : std_logic_vector(1 downto 0);
signal rd_siso : t_dp_siso;
- signal rd_sosi : t_dp_sosi := c_dp_sosi_rst; -- initialize default values for unused sosi fields
+ -- initialize default values for unused sosi fields
+ signal rd_sosi : t_dp_sosi := c_dp_sosi_rst;
begin
-- Output monitor FIFO filling
wr_ful <= fifo_wr_ful;
@@ -190,7 +206,8 @@ begin
usedw => fifo_rd_usedw
);
- wr_init <= '0'; -- to avoid no driver warning in synthesis
+ -- to avoid no driver warning in synthesis
+ wr_init <= '0';
fifo_wr_usedw <= fifo_rd_usedw;
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
index b3a020284e31c610dbf1859094006f769ec39299..baf7c0c8ce7276daa21ea520f78feefa9ae7caba 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
@@ -54,11 +54,15 @@ entity dp_fifo_core_arr is
generic (
g_technology : natural := c_tech_select_default;
g_nof_streams : natural := 1;
- g_note_is_ful : boolean := true; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_note_is_ful : boolean := true;
g_use_dual_clock : boolean := false;
- g_use_lut_sc : boolean := false; -- when TRUE then force using LUTs instead of block RAM for single clock FIFO (bot available for dual clock FIFO)
- g_data_w : natural := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
- g_data_signed : boolean := false; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ -- when TRUE then force using LUTs instead of block RAM for single clock FIFO (bot available for dual clock FIFO)
+ g_use_lut_sc : boolean := false;
+ -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_w : natural := 16;
+ -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ g_data_signed : boolean := false;
g_bsn_w : natural := 1;
g_empty_w : natural := 1;
g_channel_w : natural := 1;
@@ -69,12 +73,18 @@ entity dp_fifo_core_arr is
g_use_channel : boolean := false;
g_use_error : boolean := false;
g_use_sync : boolean := false;
- g_use_aux : boolean := false; -- extra signal in_aux/out_aux
- g_use_ctrl : boolean := true; -- sop & eop
- g_use_complex : boolean := false; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size : natural := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : natural := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
- g_fifo_af_xon : natural := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ -- extra signal in_aux/out_aux
+ g_use_aux : boolean := false;
+ -- sop & eop
+ g_use_ctrl : boolean := true;
+ -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_use_complex : boolean := false;
+ -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size : natural := 512;
+ -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_margin : natural := 4;
+ -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ g_fifo_af_xon : natural := 0;
g_fifo_rl : natural := 1
);
port (
@@ -83,7 +93,8 @@ entity dp_fifo_core_arr is
rd_rst : in std_logic;
rd_clk : in std_logic;
-- Monitor FIFO filling
- wr_ful : out std_logic; -- corresponds to the carry bit of wr_usedw when FIFO is full
+ -- corresponds to the carry bit of wr_usedw when FIFO is full
+ wr_ful : out std_logic;
wr_usedw : out std_logic_vector(ceil_log2(g_fifo_size) - 1 downto 0);
rd_usedw : out std_logic_vector(ceil_log2(g_fifo_size) - 1 downto 0);
rd_emp : out std_logic;
@@ -101,14 +112,19 @@ end dp_fifo_core_arr;
architecture str of dp_fifo_core_arr is
constant c_use_data : boolean := true;
constant c_total_data_w : natural := g_nof_streams * g_data_w;
- constant c_ctrl_w : natural := 2; -- sop and eop
+ -- sop and eop
+ constant c_ctrl_w : natural := 2;
- constant c_complex_w : natural := smallest(c_dp_stream_dsp_data_w, g_data_w / 2); -- needed to cope with g_data_w > 2*c_dp_stream_dsp_data_w
+ -- needed to cope with g_data_w > 2*c_dp_stream_dsp_data_w
+ constant c_complex_w : natural := smallest(c_dp_stream_dsp_data_w, g_data_w / 2);
- constant c_fifo_almost_full : natural := g_fifo_size - g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
- constant c_fifo_almost_xon : natural := g_fifo_size - g_fifo_af_xon; -- FIFO almost full level for snk_out.xon
+ -- FIFO almost full level for snk_out.ready
+ constant c_fifo_almost_full : natural := g_fifo_size - g_fifo_af_margin;
+ -- FIFO almost full level for snk_out.xon
+ constant c_fifo_almost_xon : natural := g_fifo_size - g_fifo_af_xon;
constant c_fifo_dat_w : natural := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
- c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w); -- concat via FIFO
+ -- concat via FIFO
+ c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w);
signal nxt_snk_out : t_dp_siso := c_dp_siso_rst;
@@ -140,7 +156,8 @@ architecture str of dp_fifo_core_arr is
signal wr_aux : std_logic_vector(g_aux_w - 1 downto 0);
signal rd_siso_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
- signal rd_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst); -- initialize default values for unused sosi fields
+ -- initialize default values for unused sosi fields
+ signal rd_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
signal in_aux_sosi : t_dp_sosi := c_dp_sosi_rst;
signal out_aux_sosi : t_dp_sosi := c_dp_sosi_rst;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
index 3ec0c419a8368a0b4a1730d264765f4a3405d620..e0b05eca3ce45ceacf3f6fa111356263c72991b5 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
@@ -32,8 +32,10 @@ use technology_lib.technology_select_pkg.all;
entity dp_fifo_dc is
generic (
g_technology : natural := c_tech_select_default;
- g_data_w : natural := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
- g_data_signed : boolean := false; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_w : natural := 16;
+ -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ g_data_signed : boolean := false;
g_bsn_w : natural := 1;
g_empty_w : natural := 1;
g_channel_w : natural := 1;
@@ -43,11 +45,16 @@ entity dp_fifo_dc is
g_use_channel : boolean := false;
g_use_error : boolean := false;
g_use_sync : boolean := false;
- g_use_ctrl : boolean := true; -- sop & eop
- g_use_complex : boolean := false; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size : natural := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : natural := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
- g_fifo_af_xon : natural := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ -- sop & eop
+ g_use_ctrl : boolean := true;
+ -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_use_complex : boolean := false;
+ -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size : natural := 512;
+ -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_margin : natural := 4;
+ -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ g_fifo_af_xon : natural := 0;
g_fifo_rl : natural := 1
);
port (
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
index 5bc9dffb7f286cb79db7b3d6c6994c6cd236657c..2cfcd39475307249cbf936bf755249986bb3f22f 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
@@ -35,8 +35,10 @@ entity dp_fifo_dc_arr is
generic (
g_technology : natural := c_tech_select_default;
g_nof_streams : natural := 1;
- g_data_w : natural := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
- g_data_signed : boolean := false; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_w : natural := 16;
+ -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ g_data_signed : boolean := false;
g_bsn_w : natural := 1;
g_empty_w : natural := 1;
g_channel_w : natural := 1;
@@ -48,11 +50,16 @@ entity dp_fifo_dc_arr is
g_use_error : boolean := false;
g_use_sync : boolean := false;
g_use_aux : boolean := false;
- g_use_ctrl : boolean := true; -- sop & eop
- g_use_complex : boolean := false; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size : natural := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : natural := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
- g_fifo_af_xon : natural := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ -- sop & eop
+ g_use_ctrl : boolean := true;
+ -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_use_complex : boolean := false;
+ -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size : natural := 512;
+ -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_margin : natural := 4;
+ -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ g_fifo_af_xon : natural := 0;
g_fifo_rl : natural := 1
);
port (
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
index 2162fd4be1fbdf97b097a5e316bee168eca6e6cd..477fc33a8ce5be1a7c98235607a1dc2ade5f2ed2 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
@@ -113,9 +113,12 @@ entity dp_fifo_dc_mixed_widths is
g_wr_data_w : natural := 18;
g_rd_data_w : natural := 9;
g_use_ctrl : boolean := true;
- g_wr_fifo_size : natural := 512; -- FIFO size in nof wr_data words
- g_wr_fifo_af_margin : natural := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
- g_wr_fifo_af_xon : natural := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ -- FIFO size in nof wr_data words
+ g_wr_fifo_size : natural := 512;
+ -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_wr_fifo_af_margin : natural := 4;
+ -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ g_wr_fifo_af_xon : natural := 0;
g_rd_fifo_rl : natural := 1
);
port (
@@ -124,7 +127,8 @@ entity dp_fifo_dc_mixed_widths is
rd_rst : in std_logic;
rd_clk : in std_logic;
-- Monitor FIFO filling
- wr_ful : out std_logic; -- corresponds to the carry bit of wr_usedw when FIFO is full
+ -- corresponds to the carry bit of wr_usedw when FIFO is full
+ wr_ful : out std_logic;
wr_usedw : out std_logic_vector(ceil_log2(g_wr_fifo_size) - 1 downto 0);
rd_usedw : out std_logic_vector(ceil_log2(g_wr_fifo_size * g_wr_data_w / g_rd_data_w) - 1 downto 0);
rd_emp : out std_logic;
@@ -146,14 +150,19 @@ architecture str of dp_fifo_dc_mixed_widths is
constant c_narrow_data_w : natural := sel_a_b(g_wr_data_w > g_rd_data_w, g_rd_data_w, g_wr_data_w);
constant c_use_data : boolean := true;
- constant c_ctrl_w : natural := sel_a_b(g_use_ctrl, 2, 0); -- sop and eop, or no ctrl
+ -- sop and eop, or no ctrl
+ constant c_ctrl_w : natural := sel_a_b(g_use_ctrl, 2, 0);
constant c_empty_w : natural := ceil_log2(c_nof_narrow);
- constant c_fifo_wr_almost_full : natural := g_wr_fifo_size - g_wr_fifo_af_margin; -- FIFO almost full level for snk_out.ready
- constant c_fifo_wr_almost_xon : natural := g_wr_fifo_size - g_wr_fifo_af_xon; -- FIFO almost full level for snk_out.xon
+ -- FIFO almost full level for snk_out.ready
+ constant c_fifo_wr_almost_full : natural := g_wr_fifo_size - g_wr_fifo_af_margin;
+ -- FIFO almost full level for snk_out.xon
+ constant c_fifo_wr_almost_xon : natural := g_wr_fifo_size - g_wr_fifo_af_xon;
- constant c_fifo_narrow_data_w : natural := c_narrow_data_w + c_ctrl_w; -- if used concat control via FIFO
- constant c_fifo_wide_data_w : natural := c_nof_narrow * c_fifo_narrow_data_w; -- all through one FIFO
+ -- if used concat control via FIFO
+ constant c_fifo_narrow_data_w : natural := c_narrow_data_w + c_ctrl_w;
+ -- all through one FIFO
+ constant c_fifo_wide_data_w : natural := c_nof_narrow * c_fifo_narrow_data_w;
constant c_fifo_wr_dat_w : natural := sel_a_b(c_wr_wide, c_fifo_wide_data_w, c_fifo_narrow_data_w);
constant c_fifo_rd_dat_w : natural := sel_a_b(c_wr_wide, c_fifo_narrow_data_w, c_fifo_wide_data_w);
@@ -181,7 +190,8 @@ architecture str of dp_fifo_dc_mixed_widths is
signal rd_gap_val : std_logic;
signal rd_siso : t_dp_siso;
- signal rd_sosi : t_dp_sosi := c_dp_sosi_rst; -- initialize default values for unused sosi fields
+ -- initialize default values for unused sosi fields
+ signal rd_sosi : t_dp_sosi := c_dp_sosi_rst;
signal i_snk_out : t_dp_siso := c_dp_siso_rst;
signal nxt_snk_out : t_dp_siso := c_dp_siso_rst;
@@ -195,7 +205,8 @@ begin
-- if c_wr_wide = TRUE then generate FIFO write wide --> read narrow (uses common_fifo_dc_mixed_widths)
-- else generate FIFO write narrow --> read wide (uses common_fifo_dc_mixed_widths)
- gen_equal : if c_nof_narrow = 1 generate -- fall back to equal width FIFO
+ -- fall back to equal width FIFO
+ gen_equal : if c_nof_narrow = 1 generate
u_dp_fifo_dc : entity work.dp_fifo_dc
generic map (
g_technology => g_technology,
@@ -228,9 +239,11 @@ begin
src_in => src_in,
src_out => src_out
);
- end generate; -- gen_equal
+ -- gen_equal
+ end generate;
- gen_mixed : if c_nof_narrow > 1 generate -- mixed width FIFO
+ -- mixed width FIFO
+ gen_mixed : if c_nof_narrow > 1 generate
arst <= wr_rst or rd_rst;
@@ -268,7 +281,8 @@ begin
u_fifo_mw : entity common_lib.common_fifo_dc_mixed_widths
generic map (
g_technology => g_technology,
- g_nof_words => g_wr_fifo_size, -- FIFO size in nof wr_dat words
+ -- FIFO size in nof wr_dat words
+ g_nof_words => g_wr_fifo_size,
g_wr_dat_w => c_fifo_wr_dat_w,
g_rd_dat_w => c_fifo_rd_dat_w
)
@@ -298,7 +312,8 @@ begin
fifo_wr_dat <= (others => '0');
for I in 0 to c_nof_narrow - 1 loop
vB := c_nof_narrow - I - 1;
- fifo_wr_dat((I + 1) * c_fifo_narrow_data_w - 1 downto I * c_fifo_narrow_data_w + 2) <= snk_in.data((vB + 1) * c_narrow_data_w - 1 downto vB * c_narrow_data_w); -- c_ctrl_w = 2
+ -- c_ctrl_w = 2
+ fifo_wr_dat((I + 1) * c_fifo_narrow_data_w - 1 downto I * c_fifo_narrow_data_w + 2) <= snk_in.data((vB + 1) * c_narrow_data_w - 1 downto vB * c_narrow_data_w);
if vB = c_nof_narrow - 1 then
fifo_wr_dat(I * c_fifo_narrow_data_w + 1) <= snk_in.sop;
end if;
@@ -310,7 +325,8 @@ begin
end process;
-- Read the narrow SOSI
- rd_sosi.data <= RESIZE_DP_DATA(fifo_rd_dat(c_fifo_narrow_data_w - 1 downto 2)); -- c_ctrl_w = 2
+ -- c_ctrl_w = 2
+ rd_sosi.data <= RESIZE_DP_DATA(fifo_rd_dat(c_fifo_narrow_data_w - 1 downto 2));
rd_sosi.valid <= fifo_rd_val and not rd_gap_val;
rd_sosi.sop <= fifo_rd_val and fifo_rd_dat(1);
rd_sosi.eop <= fifo_rd_val and fifo_rd_dat(0);
@@ -330,13 +346,16 @@ begin
-- count narrow data
nxt_rd_eop_hld <= rd_eop_hld;
if fifo_rd_dat(1) = '1' then
- nxt_rd_eop_hld <= '0'; -- at next frame sop
+ -- at next frame sop
+ nxt_rd_eop_hld <= '0';
elsif fifo_rd_dat(0) = '1' then
- nxt_rd_eop_hld <= '1'; -- at this frame eop
+ -- at this frame eop
+ nxt_rd_eop_hld <= '1';
end if;
end process;
- rd_gap_val <= rd_eop_hld and not fifo_rd_dat(1); -- valid during gap between this frame eop and next frame sop
+ -- valid during gap between this frame eop and next frame sop
+ rd_gap_val <= rd_eop_hld and not fifo_rd_dat(1);
end generate;
no_ctrl : if g_use_ctrl = false generate
@@ -356,7 +375,8 @@ begin
rd_sosi.valid <= fifo_rd_val;
end generate;
- end generate; -- gen_wr_wide
+ -- gen_wr_wide
+ end generate;
-- FIFO write one serial --> read multiple parallel
gen_rd_wide : if c_wr_wide = false generate
@@ -403,12 +423,14 @@ begin
variable vB : natural;
variable v_sosi : t_dp_sosi;
begin
- v_sosi := c_dp_sosi_rst; -- must init variable here, init at declaration only causes a combinatorial loop
+ -- must init variable here, init at declaration only causes a combinatorial loop
+ v_sosi := c_dp_sosi_rst;
v_sosi.valid := fifo_rd_val;
for I in 0 to c_nof_narrow - 1 loop
-- Map little endian wide FIFO (index I) to big endian wide SOSI (index vB)
vB := c_nof_narrow - I - 1;
- v_sosi.data((vB + 1) * c_narrow_data_w - 1 downto vB * c_narrow_data_w) := fifo_rd_dat((I + 1) * c_fifo_narrow_data_w - 1 downto I * c_fifo_narrow_data_w + 2); -- c_ctrl_w = 2
+ -- c_ctrl_w = 2
+ v_sosi.data((vB + 1) * c_narrow_data_w - 1 downto vB * c_narrow_data_w) := fifo_rd_dat((I + 1) * c_fifo_narrow_data_w - 1 downto I * c_fifo_narrow_data_w + 2);
-- Or the control fields: sop and eop
v_sosi.sop := v_sosi.sop or fifo_rd_dat(I * c_fifo_narrow_data_w + 1);
v_sosi.eop := v_sosi.eop or fifo_rd_dat(I * c_fifo_narrow_data_w + 0);
@@ -431,7 +453,8 @@ begin
variable vB : natural;
variable v_sosi : t_dp_sosi;
begin
- v_sosi := c_dp_sosi_rst; -- must init variable here, init at declaration only causes a combinatorial loop
+ -- must init variable here, init at declaration only causes a combinatorial loop
+ v_sosi := c_dp_sosi_rst;
v_sosi.valid := fifo_rd_val;
for I in 0 to c_nof_narrow - 1 loop
-- Map little endian wide FIFO (index I) to big endian wide SOSI (index vB)
@@ -441,7 +464,8 @@ begin
rd_sosi <= v_sosi;
end process;
end generate;
- end generate; -- gen_rd_wide
+ -- gen_rd_wide
+ end generate;
-- Support show ahead FIFO with ready latency = 0 at read output
u_rl : entity work.dp_latency_adapter
@@ -459,5 +483,6 @@ begin
src_in => src_in,
src_out => src_out
);
- end generate; -- gen_mixed
+ -- gen_mixed
+ end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
index 5ba44fca042bd7a1f6e631bf2f9108469fc3c4e0..5c4f74960057bbfd0c411b8475458395a770758e 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
@@ -45,12 +45,17 @@ entity dp_fifo_fill is
g_use_channel : boolean := false;
g_use_error : boolean := false;
g_use_sync : boolean := false;
- g_use_complex : boolean := false; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_use_complex : boolean := false;
g_fifo_fill : natural := 0;
- g_fifo_size : natural := 256; -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : natural := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
- g_fifo_af_xon : natural := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
- g_fifo_rl : natural := 1 -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size : natural := 256;
+ -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_margin : natural := 4;
+ -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ g_fifo_af_xon : natural := 0;
+ -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ g_fifo_rl : natural := 1
);
port (
rst : in std_logic;
@@ -58,12 +63,15 @@ entity dp_fifo_fill is
-- Monitor FIFO filling
wr_ful : out std_logic;
- usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0);
rd_emp : out std_logic;
-- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = wr_usedw
- rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = rd_usedw
+ -- = wr_usedw
+ wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0);
+ -- = rd_usedw
+ rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0);
rd_fill_32b : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_fifo_fill, c_word_w);
-- ST sink
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
index f7c848b155e35b766066af8650195b02bf80287c..c88a6b5f40f70781193d8cdb54609b50120be26b 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
@@ -67,8 +67,10 @@ entity dp_fifo_fill_core is
generic (
g_technology : natural := c_tech_select_default;
g_use_dual_clock : boolean := false;
- g_data_w : natural := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
- g_data_signed : boolean := false; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_w : natural := 16;
+ -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ g_data_signed : boolean := false;
g_bsn_w : natural := 1;
g_empty_w : natural := 1;
g_channel_w : natural := 1;
@@ -78,12 +80,17 @@ entity dp_fifo_fill_core is
g_use_channel : boolean := false;
g_use_error : boolean := false;
g_use_sync : boolean := false;
- g_use_complex : boolean := false; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_use_complex : boolean := false;
g_fifo_fill : natural := 0;
- g_fifo_size : natural := 256; -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : natural := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
- g_fifo_af_xon : natural := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
- g_fifo_rl : natural := 1 -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size : natural := 256;
+ -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_margin : natural := 4;
+ -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ g_fifo_af_xon : natural := 0;
+ -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ g_fifo_rl : natural := 1
);
port (
wr_rst : in std_logic;
@@ -91,13 +98,18 @@ entity dp_fifo_fill_core is
rd_rst : in std_logic;
rd_clk : in std_logic;
-- Monitor FIFO filling
- wr_ful : out std_logic; -- corresponds to the carry bit of wr_usedw when FIFO is full
- wr_usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
- rd_usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ -- corresponds to the carry bit of wr_usedw when FIFO is full
+ wr_ful : out std_logic;
+ -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ wr_usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0);
+ -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ rd_usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0);
rd_emp : out std_logic;
-- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = wr_usedw
- rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = rd_usedw
+ -- = wr_usedw
+ wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0);
+ -- = rd_usedw
+ rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0);
rd_fill_32b : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_fifo_fill, c_word_w);
-- ST sink
snk_out : out t_dp_siso;
@@ -110,9 +122,11 @@ end dp_fifo_fill_core;
architecture rtl of dp_fifo_fill_core is
constant c_fifo_rl : natural := sel_a_b(g_fifo_fill = 0, 1, g_fifo_rl);
- constant c_fifo_fill_margin : natural := g_fifo_af_margin + 2; -- add +2 extra margin, with tb_dp_fifo_fill it follows that +1 is also enough to avoid almost full when fifo is operating near g_fifo_fill level
+ -- add +2 extra margin, with tb_dp_fifo_fill it follows that +1 is also enough to avoid almost full when fifo is operating near g_fifo_fill level
+ constant c_fifo_fill_margin : natural := g_fifo_af_margin + 2;
constant c_fifo_size : natural := largest(g_fifo_size, g_fifo_fill + c_fifo_fill_margin);
- constant c_fifo_size_w : natural := ceil_log2(c_fifo_size); -- = wr_usedw'LENGTH = rd_usedw'LENGTH
+ -- = wr_usedw'LENGTH = rd_usedw'LENGTH
+ constant c_fifo_size_w : natural := ceil_log2(c_fifo_size);
-- The FIFO filling relies on framed data, so contrary to dp_fifo_sc the sop and eop need to be used.
constant c_use_ctrl : boolean := true;
@@ -124,18 +138,24 @@ architecture rtl of dp_fifo_fill_core is
constant s_output : std_logic_vector(1 downto 0) := "10";
constant s_xoff : std_logic_vector(1 downto 0) := "11";
- signal state : std_logic_vector(1 downto 0); -- t_state
- signal nxt_state : std_logic_vector(1 downto 0); -- t_state
+ -- t_state
+ signal state : std_logic_vector(1 downto 0);
+ -- t_state
+ signal nxt_state : std_logic_vector(1 downto 0);
signal xon_reg : std_logic;
signal nxt_xon_reg : std_logic;
signal rd_siso : t_dp_siso;
- signal rd_sosi : t_dp_sosi := c_dp_sosi_rst; -- initialize default values for unused sosi fields;
+ -- initialize default values for unused sosi fields;
+ signal rd_sosi : t_dp_sosi := c_dp_sosi_rst;
- signal wr_fifo_usedw : std_logic_vector(c_fifo_size_w - 1 downto 0); -- = wr_usedw'RANGE
- signal rd_fifo_usedw : std_logic_vector(c_fifo_size_w - 1 downto 0); -- = rd_usedw'RANGE
- signal rd_fill_ctrl : std_logic_vector(c_fifo_size_w - 1 downto 0); -- used to resize rd_fill_32b to actual maximum width
+ -- = wr_usedw'RANGE
+ signal wr_fifo_usedw : std_logic_vector(c_fifo_size_w - 1 downto 0);
+ -- = rd_usedw'RANGE
+ signal rd_fifo_usedw : std_logic_vector(c_fifo_size_w - 1 downto 0);
+ -- used to resize rd_fill_32b to actual maximum width
+ signal rd_fill_ctrl : std_logic_vector(c_fifo_size_w - 1 downto 0);
signal i_src_out : t_dp_sosi;
signal nxt_src_out : t_dp_sosi;
@@ -187,7 +207,8 @@ begin
snk_out => snk_out,
snk_in => snk_in,
-- ST source
- src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, for RL = 1 rd_siso.ready acts as read request
+ -- for RL = 0 rd_siso.ready acts as read acknowledge, for RL = 1 rd_siso.ready acts as read request
+ src_in => rd_siso,
src_out => rd_sosi
);
@@ -230,15 +251,19 @@ begin
snk_out => snk_out,
snk_in => snk_in,
-- ST source
- src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
+ -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
+ src_in => rd_siso,
src_out => rd_sosi
);
end generate;
no_fill : if g_fifo_fill = 0 generate
- rd_siso <= src_in; -- SISO
- src_out <= rd_sosi; -- SOSI
- end generate; -- no_fill
+ -- SISO
+ rd_siso <= src_in;
+ -- SOSI
+ src_out <= rd_sosi;
+ -- no_fill
+ end generate;
gen_fill : if g_fifo_fill > 0 generate
src_out <= i_src_out;
@@ -256,18 +281,21 @@ begin
end if;
end process;
- nxt_xon_reg <= src_in.xon; -- register xon to easy timing closure
+ -- register xon to easy timing closure
+ nxt_xon_reg <= src_in.xon;
gen_rl_0 : if g_fifo_rl = 0 generate
p_state : process(state, rd_sosi, src_in, xon_reg, rd_fifo_usedw, rd_fill_ctrl)
begin
nxt_state <= state;
- rd_siso <= src_in; -- default acknowledge (RL=1) this input when output is ready
+ -- default acknowledge (RL=1) this input when output is ready
+ rd_siso <= src_in;
-- The output register stage increase RL=0 to 1, so it matches RL = 1 for src_in.ready
nxt_src_out <= rd_sosi;
- nxt_src_out.valid <= '0'; -- default no output
+ -- default no output
+ nxt_src_out.valid <= '0';
nxt_src_out.sop <= '0';
nxt_src_out.eop <= '0';
nxt_src_out.sync <= '0';
@@ -279,9 +307,11 @@ begin
else
-- read the FIFO until the sop is pending at the output, so discard any valid data between eop and sop
if rd_sosi.sop = '0' then
- rd_siso <= c_dp_siso_rdy; -- acknowledge (RL=0) this input independent of output ready
+ -- acknowledge (RL=0) this input independent of output ready
+ rd_siso <= c_dp_siso_rdy;
else
- rd_siso <= c_dp_siso_hold; -- stop the input, hold the rd_sosi.sop at FIFO output (RL=0)
+ -- stop the input, hold the rd_sosi.sop at FIFO output (RL=0)
+ rd_siso <= c_dp_siso_hold;
nxt_state <= s_fill;
end if;
end if;
@@ -291,11 +321,13 @@ begin
else
-- stop reading until the FIFO has been filled sufficiently
if unsigned(rd_fifo_usedw) < unsigned(rd_fill_ctrl) then
- rd_siso <= c_dp_siso_hold; -- stop the input, hold the pend_src_out.sop
+ -- stop the input, hold the pend_src_out.sop
+ rd_siso <= c_dp_siso_hold;
else
-- if the output is ready, then start outputting the frame
if src_in.ready = '1' then
- nxt_src_out <= rd_sosi; -- output sop that is still at FIFO output (RL=0)
+ -- output sop that is still at FIFO output (RL=0)
+ nxt_src_out <= rd_sosi;
nxt_state <= s_output;
end if;
end if;
@@ -303,12 +335,15 @@ begin
when s_output =>
-- if the output is ready continue outputting the frame, ignore xon_reg during this frame
if src_in.ready = '1' then
- nxt_src_out <= rd_sosi; -- output valid
+ -- output valid
+ nxt_src_out <= rd_sosi;
if rd_sosi.eop = '1' then
- nxt_state <= s_idle; -- output eop, so stop reading the FIFO
+ -- output eop, so stop reading the FIFO
+ nxt_state <= s_idle;
end if;
end if;
- when others => -- s_xoff
+ -- s_xoff
+ when others =>
-- Flush the fill FIFO when xon='0'
rd_siso <= c_dp_siso_flush;
if xon_reg = '1' then
@@ -319,7 +354,8 @@ begin
-- Pass on frame level flow control
rd_siso.xon <= src_in.xon;
end process;
- end generate; -- gen_rl_0
+ -- gen_rl_0
+ end generate;
gen_rl_1 : if g_fifo_rl = 1 generate
-- Use dp_hold_input to get equivalent implementation with default RL=1 FIFO.
@@ -330,11 +366,15 @@ begin
rst => rd_rst,
clk => rd_clk,
-- ST sink
- snk_out => rd_siso, -- SISO ready
- snk_in => rd_sosi, -- SOSI
+ -- SISO ready
+ snk_out => rd_siso,
+ -- SOSI
+ snk_in => rd_sosi,
-- ST source
- src_in => hold_src_in, -- SISO ready
- next_src_out => OPEN, -- SOSI
+ -- SISO ready
+ src_in => hold_src_in,
+ -- SOSI
+ next_src_out => OPEN,
pend_src_out => pend_src_out,
src_out_reg => i_src_out
);
@@ -343,11 +383,13 @@ begin
begin
nxt_state <= state;
- hold_src_in <= src_in; -- default request (RL=1) new input when output is ready
+ -- default request (RL=1) new input when output is ready
+ hold_src_in <= src_in;
-- The output register stage matches RL = 1 for src_in.ready
nxt_src_out <= pend_src_out;
- nxt_src_out.valid <= '0'; -- default no output
+ -- default no output
+ nxt_src_out.valid <= '0';
nxt_src_out.sop <= '0';
nxt_src_out.eop <= '0';
nxt_src_out.sync <= '0';
@@ -359,9 +401,11 @@ begin
else
-- read the FIFO until the sop is pending at the output, so discard any valid data between eop and sop
if pend_src_out.sop = '0' then
- hold_src_in <= c_dp_siso_rdy; -- request (RL=1) new input independent of output ready
+ -- request (RL=1) new input independent of output ready
+ hold_src_in <= c_dp_siso_rdy;
else
- hold_src_in <= c_dp_siso_hold; -- stop the input, hold the pend_src_out.sop in dp_hold_input
+ -- stop the input, hold the pend_src_out.sop in dp_hold_input
+ hold_src_in <= c_dp_siso_hold;
nxt_state <= s_fill;
end if;
end if;
@@ -371,11 +415,13 @@ begin
else
-- stop reading until the FIFO has been filled sufficiently
if unsigned(rd_fifo_usedw) < unsigned(rd_fill_ctrl) then
- hold_src_in <= c_dp_siso_hold; -- stop the input, hold the pend_src_out.sop
+ -- stop the input, hold the pend_src_out.sop
+ hold_src_in <= c_dp_siso_hold;
else
-- if the output is ready, then start outputting the input frame
if src_in.ready = '1' then
- nxt_src_out <= pend_src_out; -- output sop that is still pending in dp_hold_input
+ -- output sop that is still pending in dp_hold_input
+ nxt_src_out <= pend_src_out;
nxt_state <= s_output;
end if;
end if;
@@ -383,12 +429,15 @@ begin
when s_output =>
-- if the output is ready continue outputting the input frame, ignore xon_reg during this frame
if src_in.ready = '1' then
- nxt_src_out <= pend_src_out; -- output valid
+ -- output valid
+ nxt_src_out <= pend_src_out;
if pend_src_out.eop = '1' then
- nxt_state <= s_idle; -- output eop, so stop reading the FIFO
+ -- output eop, so stop reading the FIFO
+ nxt_state <= s_idle;
end if;
end if;
- when others => -- s_xon
+ -- s_xon
+ when others =>
-- Flush the fill FIFO when xon='0'
hold_src_in <= c_dp_siso_flush;
if xon_reg = '1' then
@@ -399,6 +448,8 @@ begin
-- Pass on frame level flow control
hold_src_in.xon <= src_in.xon;
end process;
- end generate; -- gen_rl_1
- end generate; -- gen_fill
+ -- gen_rl_1
+ end generate;
+ -- gen_fill
+ end generate;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
index e766edd8f673e76a7ca4f1af85467fc55e8ce88b..b75136d7b397feb18a9e637f0b703ced536d0ad9 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
@@ -33,8 +33,10 @@ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_dc is
generic (
g_technology : natural := c_tech_select_default;
- g_data_w : natural := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
- g_data_signed : boolean := false; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_w : natural := 16;
+ -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ g_data_signed : boolean := false;
g_bsn_w : natural := 1;
g_empty_w : natural := 1;
g_channel_w : natural := 1;
@@ -44,11 +46,15 @@ entity dp_fifo_fill_dc is
g_use_channel : boolean := false;
g_use_error : boolean := false;
g_use_sync : boolean := false;
- g_use_complex : boolean := false; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_use_complex : boolean := false;
g_fifo_fill : natural := 0;
- g_fifo_size : natural := 256; -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : natural := 4; -- Nof words below max (full) at which fifo is considered almost full
- g_fifo_rl : natural := 1 -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size : natural := 256;
+ -- Nof words below max (full) at which fifo is considered almost full
+ g_fifo_af_margin : natural := 4;
+ -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ g_fifo_rl : natural := 1
);
port (
wr_rst : in std_logic;
@@ -56,13 +62,18 @@ entity dp_fifo_fill_dc is
rd_rst : in std_logic;
rd_clk : in std_logic;
-- Monitor FIFO filling
- wr_ful : out std_logic; -- corresponds to the carry bit of wr_usedw when FIFO is full
- wr_usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
- rd_usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ -- corresponds to the carry bit of wr_usedw when FIFO is full
+ wr_ful : out std_logic;
+ -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ wr_usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0);
+ -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ rd_usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0);
rd_emp : out std_logic;
-- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = wr_usedw
- rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = rd_usedw
+ -- = wr_usedw
+ wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0);
+ -- = rd_usedw
+ rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0);
rd_fill_32b : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_fifo_fill, c_word_w);
-- ST sink
snk_out : out t_dp_siso;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index c7b793d0b5d61acaf586ec16a5808f174d31aae3..9b109bb8189fd181bc7237ea0848bf0dd0714645 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -64,8 +64,10 @@ entity dp_fifo_fill_eop is
g_technology : natural := c_tech_select_default;
g_note_is_ful : boolean := true;
g_use_dual_clock : boolean := false;
- g_data_w : natural := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
- g_data_signed : boolean := false; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_w : natural := 16;
+ -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ g_data_signed : boolean := false;
g_bsn_w : natural := 1;
g_empty_w : natural := 1;
g_channel_w : natural := 1;
@@ -75,12 +77,17 @@ entity dp_fifo_fill_eop is
g_use_channel : boolean := false;
g_use_error : boolean := false;
g_use_sync : boolean := false;
- g_use_complex : boolean := false; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_use_complex : boolean := false;
g_fifo_fill : natural := 0;
- g_fifo_size : natural := 256; -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : natural := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
- g_fifo_af_xon : natural := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
- g_fifo_rl : natural := 1 -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size : natural := 256;
+ -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_margin : natural := 4;
+ -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ g_fifo_af_xon : natural := 0;
+ -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ g_fifo_rl : natural := 1
);
port (
wr_rst : in std_logic;
@@ -88,13 +95,18 @@ entity dp_fifo_fill_eop is
rd_rst : in std_logic;
rd_clk : in std_logic;
-- Monitor FIFO filling
- wr_ful : out std_logic; -- corresponds to the carry bit of wr_usedw when FIFO is full
- wr_usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
- rd_usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ -- corresponds to the carry bit of wr_usedw when FIFO is full
+ wr_ful : out std_logic;
+ -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ wr_usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0);
+ -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ rd_usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0);
rd_emp : out std_logic;
-- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = wr_usedw
- rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = rd_usedw
+ -- = wr_usedw
+ wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0);
+ -- = rd_usedw
+ rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0);
rd_fill_32b : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_fifo_fill, c_word_w);
-- ST sink
snk_out : out t_dp_siso;
@@ -107,9 +119,11 @@ end dp_fifo_fill_eop;
architecture rtl of dp_fifo_fill_eop is
constant c_fifo_rl : natural := sel_a_b(g_fifo_fill = 0, 1, g_fifo_rl);
- constant c_fifo_fill_margin : natural := g_fifo_af_margin + 2; -- add +2 extra margin, with tb_dp_fifo_fill it follows that +1 is also enough to avoid almost full when fifo is operating near g_fifo_fill level
+ -- add +2 extra margin, with tb_dp_fifo_fill it follows that +1 is also enough to avoid almost full when fifo is operating near g_fifo_fill level
+ constant c_fifo_fill_margin : natural := g_fifo_af_margin + 2;
constant c_fifo_size : natural := largest(g_fifo_size, g_fifo_fill + c_fifo_fill_margin);
- constant c_fifo_size_w : natural := ceil_log2(c_fifo_size); -- = wr_usedw'LENGTH = rd_usedw'LENGTH
+ -- = wr_usedw'LENGTH = rd_usedw'LENGTH
+ constant c_fifo_size_w : natural := ceil_log2(c_fifo_size);
-- The FIFO filling relies on framed data, so contrary to dp_fifo_sc the sop and eop need to be used.
constant c_use_ctrl : boolean := true;
@@ -126,11 +140,15 @@ architecture rtl of dp_fifo_fill_eop is
signal nxt_xon_reg : std_logic;
signal rd_siso : t_dp_siso;
- signal rd_sosi : t_dp_sosi := c_dp_sosi_rst; -- initialize default values for unused sosi fields;
+ -- initialize default values for unused sosi fields;
+ signal rd_sosi : t_dp_sosi := c_dp_sosi_rst;
- signal wr_fifo_usedw : std_logic_vector(c_fifo_size_w - 1 downto 0); -- = wr_usedw'RANGE
- signal rd_fifo_usedw : std_logic_vector(c_fifo_size_w - 1 downto 0); -- = rd_usedw'RANGE
- signal rd_fill_ctrl : std_logic_vector(c_fifo_size_w - 1 downto 0); -- used to resize rd_fill_32b to actual maximum width
+ -- = wr_usedw'RANGE
+ signal wr_fifo_usedw : std_logic_vector(c_fifo_size_w - 1 downto 0);
+ -- = rd_usedw'RANGE
+ signal rd_fifo_usedw : std_logic_vector(c_fifo_size_w - 1 downto 0);
+ -- used to resize rd_fill_32b to actual maximum width
+ signal rd_fill_ctrl : std_logic_vector(c_fifo_size_w - 1 downto 0);
signal i_src_out : t_dp_sosi;
signal nxt_src_out : t_dp_sosi;
@@ -202,7 +220,8 @@ begin
snk_out => snk_out,
snk_in => snk_in,
-- ST source
- src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
+ -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
+ src_in => rd_siso,
src_out => rd_sosi
);
@@ -279,7 +298,8 @@ begin
p_eop_cnt_comb_sc: process(snk_in)
begin
if snk_in.eop = '1' then
- nxt_wr_eop_cnt <= 1; -- wr_eop_cnt can simply be set to 1 instead of counting as it is immidiatly processed due to having a single clock.
+ -- wr_eop_cnt can simply be set to 1 instead of counting as it is immidiatly processed due to having a single clock.
+ nxt_wr_eop_cnt <= 1;
else
nxt_wr_eop_cnt <= 0;
end if;
@@ -300,9 +320,12 @@ begin
end process;
no_fill : if g_fifo_fill = 0 generate
- rd_siso <= src_in; -- SISO
- src_out <= rd_sosi; -- SOSI
- end generate; -- no_fill
+ -- SISO
+ rd_siso <= src_in;
+ -- SOSI
+ src_out <= rd_sosi;
+ -- no_fill
+ end generate;
gen_fill : if g_fifo_fill > 0 generate
src_out <= i_src_out;
@@ -322,7 +345,8 @@ begin
end if;
end process;
- nxt_xon_reg <= src_in.xon; -- register xon to easy timing closure
+ -- register xon to easy timing closure
+ nxt_xon_reg <= src_in.xon;
gen_rl_1 : if g_fifo_rl = 1 generate
-- Use dp_hold_input to get equivalent implementation with default RL=1 FIFO.
@@ -333,11 +357,15 @@ begin
rst => rd_rst,
clk => rd_clk,
-- ST sink
- snk_out => rd_siso, -- SISO ready
- snk_in => rd_sosi, -- SOSI
+ -- SISO ready
+ snk_out => rd_siso,
+ -- SOSI
+ snk_in => rd_sosi,
-- ST source
- src_in => hold_src_in, -- SISO ready
- next_src_out => OPEN, -- SOSI
+ -- SISO ready
+ src_in => hold_src_in,
+ -- SOSI
+ next_src_out => OPEN,
pend_src_out => pend_src_out,
src_out_reg => i_src_out
);
@@ -352,11 +380,13 @@ begin
begin
nxt_state <= state;
- hold_src_in <= src_in; -- default request (RL=1) new input when output is ready
+ -- default request (RL=1) new input when output is ready
+ hold_src_in <= src_in;
-- The output register stage matches RL = 1 for src_in.ready
nxt_src_out <= pend_src_out;
- nxt_src_out.valid <= '0'; -- default no output
+ -- default no output
+ nxt_src_out.valid <= '0';
nxt_src_out.sop <= '0';
nxt_src_out.eop <= '0';
nxt_src_out.sync <= '0';
@@ -372,14 +402,17 @@ begin
else
-- read the FIFO until the sop is pending at the output, so discard any valid data between eop and sop
if pend_src_out.sop = '0' then
- hold_src_in <= c_dp_siso_rdy; -- request (RL=1) new input independent of output ready
+ -- request (RL=1) new input independent of output ready
+ hold_src_in <= c_dp_siso_rdy;
else
if unsigned(rd_fifo_usedw) < unsigned(rd_fill_ctrl) and eop_cnt <= 0 then
- hold_src_in <= c_dp_siso_hold; -- stop the input, hold the pend_src_out.sop
+ -- stop the input, hold the pend_src_out.sop
+ hold_src_in <= c_dp_siso_hold;
else
-- if the output is ready, then start outputting the input frame
if src_in.ready = '1' then
- nxt_src_out <= pend_src_out; -- output sop that is still pending in dp_hold_input
+ -- output sop that is still pending in dp_hold_input
+ nxt_src_out <= pend_src_out;
nxt_state <= s_output;
if rd_eop_new = '1' then
nxt_eop_cnt <= eop_cnt + rd_eop_cnt - 1;
@@ -393,12 +426,15 @@ begin
when s_output =>
-- if the output is ready continue outputting the input frame, ignore xon_reg during this frame
if src_in.ready = '1' then
- nxt_src_out <= pend_src_out; -- output valid
+ -- output valid
+ nxt_src_out <= pend_src_out;
if pend_src_out.eop = '1' then
- nxt_state <= s_fill; -- output eop, so stop reading the FIFO
+ -- output eop, so stop reading the FIFO
+ nxt_state <= s_fill;
end if;
end if;
- when others => -- s_xoff
+ -- s_xoff
+ when others =>
-- Flush the fill FIFO when xon='0'
hold_src_in <= c_dp_siso_flush;
if xon_reg = '1' then
@@ -409,5 +445,6 @@ begin
-- Pass on frame level flow control
hold_src_in.xon <= src_in.xon;
end process;
- end generate; -- gen_fill
+ -- gen_fill
+ end generate;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
index f7d22ea5bd6053f27f8290e42c3681052db1c360..c1d82efb63f9d123fef55bc42c6c02450936c512 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
@@ -35,8 +35,10 @@ entity dp_fifo_fill_eop_sc is
generic (
g_technology : natural := c_tech_select_default;
g_note_is_ful : boolean := true;
- g_data_w : natural := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
- g_data_signed : boolean := false; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_w : natural := 16;
+ -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ g_data_signed : boolean := false;
g_bsn_w : natural := 1;
g_empty_w : natural := 1;
g_channel_w : natural := 1;
@@ -46,23 +48,32 @@ entity dp_fifo_fill_eop_sc is
g_use_channel : boolean := false;
g_use_error : boolean := false;
g_use_sync : boolean := false;
- g_use_complex : boolean := false; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_use_complex : boolean := false;
g_fifo_fill : natural := 0;
- g_fifo_size : natural := 256; -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : natural := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
- g_fifo_af_xon : natural := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
- g_fifo_rl : natural := 1 -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size : natural := 256;
+ -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_margin : natural := 4;
+ -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ g_fifo_af_xon : natural := 0;
+ -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ g_fifo_rl : natural := 1
);
port (
rst : in std_logic;
clk : in std_logic;
-- Monitor FIFO filling
- wr_ful : out std_logic; -- corresponds to the carry bit of wr_usedw when FIFO is full
- usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ -- corresponds to the carry bit of wr_usedw when FIFO is full
+ wr_ful : out std_logic;
+ -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0);
rd_emp : out std_logic;
-- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = wr_usedw
- rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = rd_usedw
+ -- = wr_usedw
+ wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0);
+ -- = rd_usedw
+ rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0);
rd_fill_32b : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_fifo_fill, c_word_w);
-- ST sink
snk_out : out t_dp_siso;
@@ -79,7 +90,8 @@ begin
generic map (
g_technology => g_technology,
g_note_is_ful => g_note_is_ful,
- g_use_dual_clock => false, -- single clock
+ -- single clock
+ g_use_dual_clock => false,
g_data_w => g_data_w,
g_data_signed => g_data_signed,
g_bsn_w => g_bsn_w,
@@ -106,7 +118,8 @@ begin
-- Monitor FIFO filling
wr_ful => wr_ful,
wr_usedw => OPEN,
- rd_usedw => usedw, -- use rd_usedw, similar as in dp_fifo_sc, dp_fifo_fill_sc
+ -- use rd_usedw, similar as in dp_fifo_sc, dp_fifo_fill_sc
+ rd_usedw => usedw,
rd_emp => rd_emp,
-- MM control FIFO filling (assume 32 bit MM interface)
wr_usedw_32b => wr_usedw_32b,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
index d5dabeee58c1845758e978fef65d98da8efc2b78..8a5d45fb8d341134e11155f82e33a9be749cd4bb 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
@@ -57,21 +57,29 @@ use common_lib.common_mem_pkg.all;
entity dp_fifo_fill_reg is
generic (
g_nof_streams : positive := 3;
- g_cross_clock_domain : boolean := true -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
- used_w : in std_logic_vector; -- Actual used word of the fifo
+ -- Actual used word of the fifo
+ used_w : in std_logic_vector;
rd_emp : in std_logic_vector;
wr_ful : in std_logic_vector
);
@@ -79,12 +87,14 @@ end dp_fifo_fill_reg;
architecture str of dp_fifo_fill_reg is
constant c_reg_max_used_words_offset : natural := 2;
- constant c_nof_regs_per_stream : natural := 4; -- Must always be a power of 2 in order to meet the python register definition.
+ -- Must always be a power of 2 in order to meet the python register definition.
+ constant c_nof_regs_per_stream : natural := 4;
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(g_nof_streams * c_nof_regs_per_stream),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => g_nof_streams * c_nof_regs_per_stream,
init_sl => '0');
@@ -123,8 +133,10 @@ begin
reg_wr_arr => reg_wr_arr,
reg_rd_arr => reg_rd_arr,
in_new => OPEN,
- in_reg => in_arr_reg, -- read
- out_reg => OPEN, -- write
+ -- read
+ in_reg => in_arr_reg,
+ -- write
+ out_reg => OPEN,
out_new => open
);
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
index 2fc428f43218ee08a63c43c492cb3959b532feac..1176010c9d61e8b85b24a4bf977161e510c02e4a 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
@@ -33,8 +33,10 @@ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_sc is
generic (
g_technology : natural := c_tech_select_default;
- g_data_w : natural := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
- g_data_signed : boolean := false; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_w : natural := 16;
+ -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ g_data_signed : boolean := false;
g_bsn_w : natural := 1;
g_empty_w : natural := 1;
g_channel_w : natural := 1;
@@ -44,12 +46,17 @@ entity dp_fifo_fill_sc is
g_use_channel : boolean := false;
g_use_error : boolean := false;
g_use_sync : boolean := false;
- g_use_complex : boolean := false; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_use_complex : boolean := false;
g_fifo_fill : natural := 0;
- g_fifo_size : natural := 256; -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : natural := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
- g_fifo_af_xon : natural := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
- g_fifo_rl : natural := 1 -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size : natural := 256;
+ -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_margin : natural := 4;
+ -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ g_fifo_af_xon : natural := 0;
+ -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ g_fifo_rl : natural := 1
);
port (
rst : in std_logic;
@@ -57,12 +64,15 @@ entity dp_fifo_fill_sc is
-- Monitor FIFO filling
wr_ful : out std_logic;
- usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0);
rd_emp : out std_logic;
-- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = wr_usedw
- rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = rd_usedw
+ -- = wr_usedw
+ wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0);
+ -- = rd_usedw
+ rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0);
rd_fill_32b : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_fifo_fill, c_word_w);
-- ST sink
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
index 0ee926636df22b24bad3747be5df24c262dbfafe..06272b240f3e686990d8171b49934a6620fe1bfc 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
@@ -48,17 +48,20 @@ use work.dp_stream_pkg.all;
entity dp_fifo_from_mm is
generic (
g_fifo_size : natural := 512;
- g_fifo_af_margin : natural := 1; -- >=1, so > 0 to avoid FIFO full (which causes usedw=0, because value g_fifo_size then wraps to 0)
+ -- >=1, so > 0 to avoid FIFO full (which causes usedw=0, because value g_fifo_size then wraps to 0)
+ g_fifo_af_margin : natural := 1;
g_mm_word_w : natural := 32
);
port (
- rst : in std_logic; -- MM clock domain
+ -- MM clock domain
+ rst : in std_logic;
clk : in std_logic;
-- ST soure connected to FIFO input
src_out : out t_dp_sosi;
usedw : in std_logic_vector(ceil_log2(g_fifo_size) - 1 downto 0);
-- Control for FIFO read access
- mm_wr : in std_logic; -- MM write pulse to write the mm_wrdata to src_out.data
+ -- MM write pulse to write the mm_wrdata to src_out.data
+ mm_wr : in std_logic;
mm_wrdata : in std_logic_vector(g_mm_word_w - 1 downto 0);
mm_usedw : out std_logic_vector(g_mm_word_w - 1 downto 0);
mm_availw : out std_logic_vector(g_mm_word_w - 1 downto 0)
@@ -66,20 +69,24 @@ entity dp_fifo_from_mm is
end dp_fifo_from_mm;
architecture str of dp_fifo_from_mm is
- constant c_fifo_almost_full : natural := g_fifo_size - g_fifo_af_margin; -- FIFO almost full level, usedw will always be <= c_fifo_almost_full
+ -- FIFO almost full level, usedw will always be <= c_fifo_almost_full
+ constant c_fifo_almost_full : natural := g_fifo_size - g_fifo_af_margin;
constant c_usedw_w : natural := ceil_log2(g_fifo_size);
- signal availw : std_logic_vector(c_usedw_w - 1 downto 0); -- no need to use ceil_log2(g_fifo_size+1), because availw = g_fifo_size - g_fifo_af_margin < g_fifo_size when the FIFO is empty
+ -- no need to use ceil_log2(g_fifo_size+1), because availw = g_fifo_size - g_fifo_af_margin < g_fifo_size when the FIFO is empty
+ signal availw : std_logic_vector(c_usedw_w - 1 downto 0);
begin
assert g_fifo_af_margin /= 0 report "dp_fifo_from_mm.vhd : the g_fifo_af_margin must be > 0" severity FAILURE;
-- Combinatorial logic
- availw <= std_logic_vector(to_unsigned(c_fifo_almost_full, c_usedw_w) - unsigned(usedw)); -- No danger for underflow (< 0) because usedw will always be <= c_fifo_almost_full
+ -- No danger for underflow (< 0) because usedw will always be <= c_fifo_almost_full
+ availw <= std_logic_vector(to_unsigned(c_fifo_almost_full, c_usedw_w) - unsigned(usedw));
-- Wires
mm_usedw <= RESIZE_UVEC(usedw, g_mm_word_w);
mm_availw <= RESIZE_UVEC(availw, g_mm_word_w);
src_out.valid <= mm_wr;
- src_out.data <= RESIZE_DP_DATA(mm_wrdata); -- Unsigned resize to ST data width
+ -- Unsigned resize to ST data width
+ src_out.data <= RESIZE_DP_DATA(mm_wrdata);
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
index 56aa6909193970fe9fe24cbfadce3f3725cf3f49..8f38e7e0733d8d4c65573e65d4f130f131a28062 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
@@ -27,12 +27,16 @@ use common_lib.common_mem_pkg.all;
entity dp_fifo_from_mm_reg is
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
-- Memory Mapped Slave
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers
mm_wr_usedw : in std_logic_vector(c_word_w - 1 downto 0);
@@ -43,7 +47,8 @@ end dp_fifo_from_mm_reg;
architecture rtl of dp_fifo_from_mm_reg is
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(2),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 2,
init_sl => '0');
begin
@@ -59,15 +64,18 @@ begin
-- Read access: get register value
if sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read Block Sync
when 0 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_wr_usedw;
when 1 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_wr_availw;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_info.vhd b/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
index 05cdd07ee2c625ba31234ac61505d6e6fa31d82c..6fb2f1a845127a1e7379e73869934daedfe31bf4 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
@@ -95,13 +95,16 @@ entity dp_fifo_info is
rst : in std_logic;
clk : in std_logic;
-- Monitor info FIFO filling
- fifo_wr_ful : out std_logic; -- corresponds to the carry bit of usedw when FIFO is full
+ -- corresponds to the carry bit of usedw when FIFO is full
+ fifo_wr_ful : out std_logic;
fifo_usedw : out std_logic_vector(ceil_log2(g_fifo_size) - 1 downto 0);
fifo_rd_emp : out std_logic;
-- ST sink
data_snk_out : out t_dp_siso;
- data_snk_in : in t_dp_sosi; -- delayed snk_in data
- info_snk_in : in t_dp_sosi; -- original snk_in info
+ -- delayed snk_in data
+ data_snk_in : in t_dp_sosi;
+ -- original snk_in info
+ info_snk_in : in t_dp_sosi;
-- ST source
src_in : in t_dp_siso;
src_out : out t_dp_sosi
@@ -109,8 +112,10 @@ entity dp_fifo_info is
end dp_fifo_info;
architecture str of dp_fifo_info is
- constant c_fifo_sop_dat_w : natural := func_slv_concat_w(g_use_sync, g_use_bsn, g_use_channel, 1, g_bsn_w, g_channel_w); -- concat sop info via FIFO
- constant c_fifo_eop_dat_w : natural := func_slv_concat_w(g_use_empty, g_use_error, g_empty_w, g_error_w); -- concat eop info via FIFO
+ -- concat sop info via FIFO
+ constant c_fifo_sop_dat_w : natural := func_slv_concat_w(g_use_sync, g_use_bsn, g_use_channel, 1, g_bsn_w, g_channel_w);
+ -- concat eop info via FIFO
+ constant c_fifo_eop_dat_w : natural := func_slv_concat_w(g_use_empty, g_use_error, g_empty_w, g_error_w);
constant c_fifo_info_dat_w : natural := c_fifo_sop_dat_w + c_fifo_eop_dat_w;
signal dp_pipeline_data_src_in : t_dp_siso;
@@ -184,8 +189,10 @@ begin
u_common_fifo_sc : entity common_lib.common_fifo_sc
generic map (
g_technology => g_technology,
- g_note_is_ful => false, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_use_lut => true, -- when TRUE then force using LUTs via Altera eab="OFF",
+ -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_note_is_ful => false,
+ -- when TRUE then force using LUTs via Altera eab="OFF",
+ g_use_lut => true,
g_dat_w => c_fifo_sop_dat_w,
g_nof_words => g_fifo_size
)
@@ -222,8 +229,10 @@ begin
u_common_fifo_sc : entity common_lib.common_fifo_sc
generic map (
g_technology => g_technology,
- g_note_is_ful => false, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_use_lut => true, -- when TRUE then force using LUTs via Altera eab="OFF",
+ -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_note_is_ful => false,
+ -- when TRUE then force using LUTs via Altera eab="OFF",
+ g_use_lut => true,
g_dat_w => c_fifo_eop_dat_w,
g_nof_words => g_fifo_size
)
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd b/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
index fd0011ecacc88e7089e2ce55e3ffb927ba922d59..275f6ae4543a0eb4aef247be61d7bf180df3987b 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
@@ -72,7 +72,8 @@ begin
u_mm_fields: entity mm_lib.mm_fields
generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ -- use FALSE to save logic when always slv_in_val='1'
+ g_use_slv_in_val => false,
g_field_arr => c_field_arr
)
port map (
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
index 1ff22a1a71f019ff5204f1c73543dc5581a91022..b088e6257f7d149692201324428e3ca08c729623 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
@@ -32,10 +32,14 @@ use technology_lib.technology_select_pkg.all;
entity dp_fifo_sc is
generic (
g_technology : natural := c_tech_select_default;
- g_note_is_ful : boolean := true; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_use_lut : boolean := false; -- when TRUE then force using LUTs instead of block RAM
- g_data_w : natural := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
- g_data_signed : boolean := false; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_note_is_ful : boolean := true;
+ -- when TRUE then force using LUTs instead of block RAM
+ g_use_lut : boolean := false;
+ -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_w : natural := 16;
+ -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ g_data_signed : boolean := false;
g_bsn_w : natural := 1;
g_empty_w : natural := 1;
g_channel_w : natural := 1;
@@ -45,11 +49,16 @@ entity dp_fifo_sc is
g_use_channel : boolean := false;
g_use_error : boolean := false;
g_use_sync : boolean := false;
- g_use_ctrl : boolean := true; -- sop & eop
- g_use_complex : boolean := false; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size : natural := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : natural := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
- g_fifo_af_xon : natural := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ -- sop & eop
+ g_use_ctrl : boolean := true;
+ -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_use_complex : boolean := false;
+ -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size : natural := 512;
+ -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_margin : natural := 4;
+ -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ g_fifo_af_xon : natural := 0;
g_fifo_rl : natural := 1
);
port (
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
index 2c5adb850c1178c2c5db189113b50c86a1495f9b..b408f45c2a6c295c577be81ad263f27f523151bd 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
@@ -47,17 +47,20 @@ use work.dp_stream_pkg.all;
entity dp_fifo_to_mm is
generic (
g_fifo_size : natural := 512;
- g_mm_word_w : natural := c_word_w -- = 32
+ -- = 32
+ g_mm_word_w : natural := c_word_w
);
port (
- rst : in std_logic; -- MM clock domain
+ -- MM clock domain
+ rst : in std_logic;
clk : in std_logic;
-- ST sink connected to FIFO output
snk_out : out t_dp_siso;
snk_in : in t_dp_sosi;
usedw : in std_logic_vector(ceil_log2(g_fifo_size) - 1 downto 0);
-- Control for FIFO read access
- mm_rd : in std_logic; -- MM read pulse to read the mm_rddata from snk_in.data
+ -- MM read pulse to read the mm_rddata from snk_in.data
+ mm_rd : in std_logic;
mm_rddata : out std_logic_vector(g_mm_word_w - 1 downto 0);
mm_rdval : out std_logic;
mm_usedw : out std_logic_vector(g_mm_word_w - 1 downto 0)
@@ -72,7 +75,8 @@ begin
-- XON fixed to '1' after reset
snk_out.xon <= not rst;
- snk_out.ready <= mm_rd; -- Combinatorial, because FIFO RL=1 already fits MM read latency=1
+ -- Combinatorial, because FIFO RL=1 already fits MM read latency=1
+ snk_out.ready <= mm_rd;
mm_rddata <= RESIZE_UVEC(snk_in.data, g_mm_word_w);
mm_rdval <= snk_in.valid;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
index 364603eeaef910666ddf261ddd658e02ba435483..54db3770eb67f222d04e1669d63af3fff1c324e4 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
@@ -27,12 +27,16 @@ use common_lib.common_mem_pkg.all;
entity dp_fifo_to_mm_reg is
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
-- Memory Mapped Slave
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers
mm_rd_usedw : in std_logic_vector(c_word_w - 1 downto 0)
@@ -43,7 +47,8 @@ end dp_fifo_to_mm_reg;
architecture rtl of dp_fifo_to_mm_reg is
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 1,
init_sl => '0');
begin
@@ -59,13 +64,16 @@ begin
-- Read access: get register value
if sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read Block Sync
when 0 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_rd_usedw;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_flush.vhd b/libraries/base/dp/src/vhdl/dp_flush.vhd
index c800903a5ba46b3b4726c03b18eda17e58a71d6b..26fbd63a6a2b11e4885a26e682c20dfb87f8ec73 100644
--- a/libraries/base/dp/src/vhdl/dp_flush.vhd
+++ b/libraries/base/dp/src/vhdl/dp_flush.vhd
@@ -63,7 +63,8 @@ use work.dp_stream_pkg.all;
entity dp_flush is
generic (
- g_ready_latency : natural := 1; -- >= 0
+ -- >= 0
+ g_ready_latency : natural := 1;
g_framed_xon : boolean := true;
g_framed_xoff : boolean := false;
g_use_framed_channel : boolean := false;
@@ -85,7 +86,8 @@ entity dp_flush is
end dp_flush;
architecture rtl of dp_flush is
- signal flush_dly : std_logic_vector(0 to g_ready_latency); -- use 0 TO high for delay lines, rather than high DOWNTO 0
+ -- use 0 TO high for delay lines, rather than high DOWNTO 0
+ signal flush_dly : std_logic_vector(0 to g_ready_latency);
signal snk_flush : std_logic;
signal snk_flush_hi : std_logic;
signal snk_flush_lo : std_logic;
@@ -94,7 +96,8 @@ architecture rtl of dp_flush is
signal src_en_lo : std_logic;
begin
-- Combine MM control flush_en and streaming control src_in.xon
- flush_dly(0) <= flush_en or not src_in.xon; -- use flush_dly(0) combinatorially, so that flush_dly supports all g_ready_latency >= 0
+ -- use flush_dly(0) combinatorially, so that flush_dly supports all g_ready_latency >= 0
+ flush_dly(0) <= flush_en or not src_in.xon;
p_clk : process(rst, clk)
begin
if rst = '1' then
@@ -105,7 +108,8 @@ begin
end process;
-- Set snk_out.xon
- snk_out.xon <= '1'; -- the upsteam components can be always on, because if necessary this component does flush
+ -- the upsteam components can be always on, because if necessary this component does flush
+ snk_out.xon <= '1';
-- Apply snk_flush to the snk_out.ready
snk_out.ready <= src_in.ready or snk_flush;
@@ -113,8 +117,10 @@ begin
-- Apply src_en to the src_out control fields
p_src_out : process(snk_in, src_en)
begin
- src_out <= snk_in; -- default sosi
- src_out.valid <= snk_in.valid and src_en; -- overrule sosi control
+ -- default sosi
+ src_out <= snk_in;
+ -- overrule sosi control
+ src_out.valid <= snk_in.valid and src_en;
src_out.sop <= snk_in.sop and src_en;
src_out.eop <= snk_in.eop and src_en;
src_out.sync <= snk_in.sync and src_en;
@@ -126,17 +132,21 @@ begin
begin
-- for src_en there is no difference for RL = 0 or RL > 0
-- default for streaming XON/XOFF control
- v_lo := flush_dly(0); -- active flush disables the output immediately
- v_hi := not flush_dly(g_ready_latency); -- inactive flush must account g_ready_latency before enabling the output again
+ -- active flush disables the output immediately
+ v_lo := flush_dly(0);
+ -- inactive flush must account g_ready_latency before enabling the output again
+ v_hi := not flush_dly(g_ready_latency);
-- account for sop in case of framed XON or framed XOFF control
if g_framed_xoff = true then
- v_lo := v_lo and snk_in.sop; -- wait for sop to disable the output, to ensure that the output does not get disabled during a frame
+ -- wait for sop to disable the output, to ensure that the output does not get disabled during a frame
+ v_lo := v_lo and snk_in.sop;
if g_use_framed_channel = true and unsigned(snk_in.channel(g_framed_channel_w - 1 downto 0)) /= g_framed_channel then
v_lo := '0';
end if;
end if;
if g_framed_xon = true then
- v_hi := v_hi and snk_in.sop; -- wait for sop to enable the output, to ensure that the output does not get enabled during a frame
+ -- wait for sop to enable the output, to ensure that the output does not get enabled during a frame
+ v_hi := v_hi and snk_in.sop;
if g_use_framed_channel = true and unsigned(snk_in.channel(g_framed_channel_w - 1 downto 0)) /= g_framed_channel then
v_hi := '0';
end if;
@@ -167,20 +177,24 @@ begin
-- for snk_flush there is a difference between RL = 0 and RL > 0, because for RL = 0 it must keep on flushing until there is a valid or even until there is a sop
-- default for streaming XON/XOFF control
v_hi := flush_dly(0);
- v_lo := not flush_dly(0); -- equivalent snk_flush <= flush_dly(0)
+ -- equivalent snk_flush <= flush_dly(0)
+ v_lo := not flush_dly(0);
if g_ready_latency = 0 then
- v_lo := v_lo and snk_in.valid; -- keep on flushing until their is a valid, then stop flushing to let src_in.ready take over the acknowledge flow control
+ -- keep on flushing until their is a valid, then stop flushing to let src_in.ready take over the acknowledge flow control
+ v_lo := v_lo and snk_in.valid;
end if;
-- account for sop in case of framed XON or framed XOFF control
if g_framed_xoff = true then
- v_hi := v_hi and snk_in.sop; -- wait for sop before start flushing the input, to ensure that src_in.ready controls snk_out.ready during the ongoing frame
+ -- wait for sop before start flushing the input, to ensure that src_in.ready controls snk_out.ready during the ongoing frame
+ v_hi := v_hi and snk_in.sop;
if g_use_framed_channel = true and unsigned(snk_in.channel(g_framed_channel_w - 1 downto 0)) /= g_framed_channel then
v_hi := '0';
end if;
end if;
if g_framed_xon = true then
if g_ready_latency = 0 then
- v_lo := v_lo and snk_in.sop; -- keep on flushing until their is a sop
+ -- keep on flushing until their is a sop
+ v_lo := v_lo and snk_in.sop;
if g_use_framed_channel = true and unsigned(snk_in.channel(g_framed_channel_w - 1 downto 0)) /= g_framed_channel then
v_lo := '0';
end if;
@@ -193,7 +207,8 @@ begin
u_snk_flush : entity common_lib.common_switch
generic map (
g_rst_level => '1',
- g_priority_lo => true, -- priority does not matter
+ -- priority does not matter
+ g_priority_lo => true,
g_or_high => true,
g_and_low => true
)
diff --git a/libraries/base/dp/src/vhdl/dp_folder.vhd b/libraries/base/dp/src/vhdl/dp_folder.vhd
index 7b49530966b8140e84a36a88e751ae7407d0283f..2694744274975bee9fc21858f74a87d51ab738b4 100644
--- a/libraries/base/dp/src/vhdl/dp_folder.vhd
+++ b/libraries/base/dp/src/vhdl/dp_folder.vhd
@@ -52,11 +52,16 @@ use dp_lib.dp_stream_pkg.all;
entity dp_folder is
generic (
- g_nof_inputs : natural; -- Number of inputs to fold >0
- g_nof_folds : integer := -1; -- >0: Number of folds; 0: Wire out to in; <0: Fold until one output remains
- g_output_block_size : natural := 0; -- >0: Create SOP/EOP tagged output blocks of this size. 0: Forward incoming SOP,EOP.
- g_fwd_sync_bsn : boolean := false; -- TRUE: forwards (stored) input Sync+BSN (from snk_in_arr(0)) to all output streams
- g_use_channel : boolean := false -- TRUE: Also fold the channel field
+ -- Number of inputs to fold >0
+ g_nof_inputs : natural;
+ -- >0: Number of folds; 0: Wire out to in; <0: Fold until one output remains
+ g_nof_folds : integer := -1;
+ -- >0: Create SOP/EOP tagged output blocks of this size. 0: Forward incoming SOP,EOP.
+ g_output_block_size : natural := 0;
+ -- TRUE: forwards (stored) input Sync+BSN (from snk_in_arr(0)) to all output streams
+ g_fwd_sync_bsn : boolean := false;
+ -- TRUE: Also fold the channel field
+ g_use_channel : boolean := false
);
port (
clk : in std_logic;
@@ -86,7 +91,8 @@ architecture str of dp_folder is
);
end component;
- constant c_nof_muxes : natural := ceil_div(g_nof_inputs, 2); -- Using ceil_div always yields an even number of mux inputs
+ -- Using ceil_div always yields an even number of mux inputs
+ constant c_nof_muxes : natural := ceil_div(g_nof_inputs, 2);
signal mux_snk_in_arr : t_dp_sosi_arr(2 * c_nof_muxes - 1 downto 0);
signal mux_snk_in_2arr_2 : t_dp_sosi_2arr_2(c_nof_muxes - 1 downto 0);
@@ -226,8 +232,10 @@ begin
rst => rst,
clk => clk,
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in_arr(0), -- original snk_in info
+ -- delayed snk_in data
+ data_snk_in => dp_block_gen_src_out_arr(i),
+ -- original snk_in info
+ info_snk_in => snk_in_arr(0),
src_in => c_dp_siso_rdy,
src_out => src_out_arr(i)
diff --git a/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd b/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
index 7de5defbcacb7bec071fa47c44267f6e4aae3637..1331a6272b730f9cbe1b5f54131631484e8f5b54 100644
--- a/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
+++ b/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
@@ -68,7 +68,8 @@ use work.dp_stream_pkg.all;
entity dp_force_data_parallel is
generic (
- g_dat_w : natural := 32; -- must be <= 32 to fit INTEGER range
+ -- must be <= 32 to fit INTEGER range
+ g_dat_w : natural := 32;
g_increment_data : integer := 0;
g_increment_re : integer := 0;
g_increment_im : integer := 0;
@@ -87,9 +88,12 @@ entity dp_force_data_parallel is
clk : in std_logic;
-- MM control
force_en : in std_logic := '0';
- force_data : in integer := 0; -- used for sosi.data
- force_re : in integer := 0; -- used for sosi.re
- force_im : in integer := 0; -- used for sosi.im
+ -- used for sosi.data
+ force_data : in integer := 0;
+ -- used for sosi.re
+ force_re : in integer := 0;
+ -- used for sosi.im
+ force_im : in integer := 0;
-- ST sink
snk_out : out t_dp_siso;
snk_in : in t_dp_sosi;
diff --git a/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd b/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
index 85b4568abdd09dc6f0c369f4d25f6d78c44c0f82..b9bf25bb48b391c35a0652259bf933cdfbde7a5a 100644
--- a/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
+++ b/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
@@ -83,21 +83,30 @@ use work.dp_stream_pkg.all;
entity dp_force_data_serial is
generic (
- g_dat_w : natural := 32; -- must be <= 32 to fit INTEGER range
- g_index_period : natural := 10; -- number of indices in time
- g_index_sample_block_n : boolean := false -- when TRUE sample index in block, else block index in sync interval
+ -- must be <= 32 to fit INTEGER range
+ g_dat_w : natural := 32;
+ -- number of indices in time
+ g_index_period : natural := 10;
+ -- when TRUE sample index in block, else block index in sync interval
+ g_index_sample_block_n : boolean := false
);
port (
rst : in std_logic;
clk : in std_logic;
-- MM control
force_en : in std_logic := '0';
- force_value : in std_logic := '0'; -- when '1' force value when at force_index, else pass on snk_in when at force_index
- force_zero_n : in std_logic := '0'; -- when '0' force zero when not at force_index, else pass on snk_in when not at force_index
- force_data : in integer := 0; -- force value used for sosi.data
- force_re : in integer := 0; -- force value used for sosi.re
- force_im : in integer := 0; -- force value used for sosi.im
- force_index : in natural := 0; -- sample index or block index in time dependent on g_index_sample_block_n
+ -- when '1' force value when at force_index, else pass on snk_in when at force_index
+ force_value : in std_logic := '0';
+ -- when '0' force zero when not at force_index, else pass on snk_in when not at force_index
+ force_zero_n : in std_logic := '0';
+ -- force value used for sosi.data
+ force_data : in integer := 0;
+ -- force value used for sosi.re
+ force_re : in integer := 0;
+ -- force value used for sosi.im
+ force_im : in integer := 0;
+ -- sample index or block index in time dependent on g_index_sample_block_n
+ force_index : in natural := 0;
-- ST sink
snk_out : out t_dp_siso;
snk_in : in t_dp_sosi;
@@ -124,7 +133,8 @@ begin
u_common_counter : entity common_lib.common_counter
generic map (
- g_latency => 0, -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ g_latency => 0,
g_width => c_cnt_w,
g_max => g_index_period
)
diff --git a/libraries/base/dp/src/vhdl/dp_frame.vhd b/libraries/base/dp/src/vhdl/dp_frame.vhd
index c60355be35a771512e0c64b922e20d5eecd30133..7d4839ddc50272544f871500fabbedd25261ef0e 100644
--- a/libraries/base/dp/src/vhdl/dp_frame.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame.vhd
@@ -174,25 +174,30 @@ begin
p_output: process(i_out_dat, in_fsn_reg, in_dat_dly, in_val_dly, in_sof_reg, in_eof_dly2, in_err_dly2)
begin
-- set default nxt_out_dat
- nxt_out_dat <= i_out_dat; -- hold output dat when input is inactive
+ -- hold output dat when input is inactive
+ nxt_out_dat <= i_out_dat;
nxt_out_val <= '0';
nxt_out_sof <= '0';
nxt_out_eof <= '0';
-- overrule default nxt_out_dat
- if in_sof_reg = '1' then -- insert fsn, no need to delay input fsn, because it holds
- nxt_out_dat <= RESIZE_SVEC(in_fsn_reg,out_dat'length); -- sign extend is fsync,
+ -- insert fsn, no need to delay input fsn, because it holds
+ if in_sof_reg = '1' then
+ -- sign extend is fsync,
+ nxt_out_dat <= RESIZE_SVEC(in_fsn_reg,out_dat'length);
nxt_out_val <= '1';
nxt_out_sof <= '1';
elsif in_eof_dly2 = '1' then
- nxt_out_dat <= c_brc_ok; -- fill in brc, account for input err
+ -- fill in brc, account for input err
+ nxt_out_dat <= c_brc_ok;
if in_err_dly2 = '1' then
nxt_out_dat <= c_brc_err;
end if;
nxt_out_val <= '1';
nxt_out_eof <= '1';
elsif in_val_dly = '1' then
- nxt_out_dat <= in_dat_dly; -- pass on input dat
+ -- pass on input dat
+ nxt_out_dat <= in_dat_dly;
nxt_out_val <= '1';
end if;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_busy.vhd b/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
index 96e79e56f23fbc49a20294ae0568b61637825b17..9e10e83353ad553ec3454be2a2a81a9bec83fd9b 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
@@ -48,23 +48,31 @@ architecture str of dp_frame_busy is
begin
u_common_switch : entity common_lib.common_switch
generic map (
- g_rst_level => '0', -- Defines the output level at reset.
- g_priority_lo => true, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
- g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
- g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ -- Defines the output level at reset.
+ g_rst_level => '0',
+ -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
+ g_priority_lo => true,
+ -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
+ g_or_high => true,
+ -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ g_and_low => false
)
port map (
rst => rst,
clk => clk,
- switch_high => snk_in.sop, -- A pulse on switch_high makes the out_level go high
- switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
+ -- A pulse on switch_high makes the out_level go high
+ switch_high => snk_in.sop,
+ -- A pulse on switch_low makes the out_level go low
+ switch_low => snk_in.eop,
out_level => busy
);
u_common_pipeline_sl : entity common_lib.common_pipeline_sl
generic map (
- g_pipeline => g_pipeline, -- 0 for wires, > 0 for registers,
- g_reset_value => 0, -- 0 or 1, bit reset value,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline => g_pipeline,
+ -- 0 or 1, bit reset value,
+ g_reset_value => 0,
g_out_invert => false
)
port map (
diff --git a/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd b/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
index 76ab9717de7b403a02aea8eb7c09b693429c5ea9..9e534546950124ab2e13b1b8f4ccbd6bb6bd759d 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
@@ -116,7 +116,8 @@ architecture rtl of dp_frame_fsn is
-- frame sync and frame sequence number
signal fsync : std_logic;
signal nxt_fsync : std_logic;
- signal fsn : std_logic_vector(g_fsn_w - 2 downto 0); -- MSbit of out_fsn will hold fsync
+ -- MSbit of out_fsn will hold fsync
+ signal fsn : std_logic_vector(g_fsn_w - 2 downto 0);
signal nxt_fsn : std_logic_vector(fsn'range);
-- sample counter
@@ -196,8 +197,10 @@ begin
nxt_fsync <= fsync;
nxt_fsn <= fsn;
if sync_fevt = '1' then
- nxt_fsync <= '1'; -- store sync
- nxt_fsn <= (others => '0'); -- restart fsn
+ -- store sync
+ nxt_fsync <= '1';
+ -- restart fsn
+ nxt_fsn <= (others => '0');
elsif i_out_eof = '1' then
nxt_fsync <= '0';
nxt_fsn <= std_logic_vector(unsigned(fsn) + 1);
@@ -221,14 +224,16 @@ begin
end if;
case state is
- when s_idle => -- no output until in_sync_reg goes inactive
+ -- no output until in_sync_reg goes inactive
+ when s_idle =>
nxt_out_val <= '0';
nxt_cnt <= 0;
if sync_fevt = '1' then
nxt_state <= s_data;
end if;
when s_data =>
- if in_val_reg = '1' then -- block dat sof and eof
+ -- block dat sof and eof
+ if in_val_reg = '1' then
if cnt_is_zero = '1' then
nxt_out_sof <= '1';
elsif cnt_is_block_size = '1' then
@@ -236,16 +241,21 @@ begin
end if;
end if;
if sync_fevt = '1' and cnt_is_zero /= '1' then
- nxt_state <= s_flush; -- fractional nof data blocks in sync interval
+ -- fractional nof data blocks in sync interval
+ nxt_state <= s_flush;
end if;
- when others => -- s_flush
+ -- s_flush
+ when others =>
nxt_out_val <= '1';
- nxt_cnt <= cnt + 1; -- flush full block with undefined out_dat[]
+ -- flush full block with undefined out_dat[]
+ nxt_cnt <= cnt + 1;
if cnt_is_block_size = '1' then
- nxt_out_err <= '1'; -- signal error, will propagate via brc, crc
+ -- signal error, will propagate via brc, crc
+ nxt_out_err <= '1';
nxt_out_eof <= '1';
nxt_cnt <= 0;
- nxt_state <= s_idle; -- try to recover at next sync_fevt
+ -- try to recover at next sync_fevt
+ nxt_state <= s_idle;
end if;
end case;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_rd.vhd b/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
index 0a1b077acf385964ac688ecc358b7dcaff1186cc..d9a9fb231bc5d653055bb1d772637c6ae4453fb0 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
@@ -66,22 +66,33 @@ entity dp_frame_rd is
g_empty_w : natural := 1;
g_channel_w : natural := 1;
g_error_w : natural := 1;
- g_frm_cnt_max : natural := 0; -- maximum number of frames that may arrive while current frame is read, can be > 0 if subsequent frames are smaller or arrive in bursts
- g_throttle_num : positive := 1; -- numerator <= g_throttle_den
- g_throttle_den : positive := 1; -- denominator (use 1 for full speed, i.e no output throttling)
- g_throttle_sof : boolean := false; -- when false immediately do request next data after sof
- g_throttle_eof : boolean := false -- when false immediately wait for next frame request after eof
+ -- maximum number of frames that may arrive while current frame is read, can be > 0 if subsequent frames are smaller or arrive in bursts
+ g_frm_cnt_max : natural := 0;
+ -- numerator <= g_throttle_den
+ g_throttle_num : positive := 1;
+ -- denominator (use 1 for full speed, i.e no output throttling)
+ g_throttle_den : positive := 1;
+ -- when false immediately do request next data after sof
+ g_throttle_sof : boolean := false;
+ -- when false immediately wait for next frame request after eof
+ g_throttle_eof : boolean := false
);
port (
rst : in std_logic;
clk : in std_logic;
- frm_req : in std_logic; -- request a frame
- frm_flush : in std_logic; -- request to flush the frame
- frm_ack : out std_logic; -- acknowledge the request
- frm_busy : out std_logic; -- acknowledge indicates sof (busy) or no frame (not busy)
- frm_err : out std_logic; -- the busy frame is erroneous
- frm_done : out std_logic; -- the busy frame done indicates the eof
+ -- request a frame
+ frm_req : in std_logic;
+ -- request to flush the frame
+ frm_flush : in std_logic;
+ -- acknowledge the request
+ frm_ack : out std_logic;
+ -- acknowledge indicates sof (busy) or no frame (not busy)
+ frm_busy : out std_logic;
+ -- the busy frame is erroneous
+ frm_err : out std_logic;
+ -- the busy frame done indicates the eof
+ frm_done : out std_logic;
rd_req : out std_logic;
rd_dat : in std_logic_vector(g_dat_w - 1 downto 0);
@@ -90,8 +101,10 @@ entity dp_frame_rd is
rd_err : in std_logic_vector(g_error_w - 1 downto 0) := (others => '0');
rd_sync : in std_logic := '0';
rd_val : in std_logic;
- rd_sof : in std_logic; -- no default, because frame signaling must be used
- rd_eof : in std_logic; -- no default, because frame signaling must be used
+ -- no default, because frame signaling must be used
+ rd_sof : in std_logic;
+ -- no default, because frame signaling must be used
+ rd_eof : in std_logic;
out_dat : out std_logic_vector(g_dat_w - 1 downto 0);
out_empty : out std_logic_vector(g_empty_w - 1 downto 0);
@@ -211,7 +224,8 @@ begin
end if;
end process;
- next_out_throttle <= nxt_out_throttle; -- note next_out_throttle high in is same cycle as out_throttle when g_throttle_den=1
+ -- note next_out_throttle high in is same cycle as out_throttle when g_throttle_den=1
+ next_out_throttle <= nxt_out_throttle;
-- else next_out_throttle is high one cycle before out_throttle when g_throttle_den>1
p_frm_cnt : process(frm_cnt, frm_req, nxt_frm_done)
@@ -220,10 +234,12 @@ begin
if not (frm_req = '1' and nxt_frm_done = '1') then
-- check need to increment or decrement frm_cnt
if frm_req = '1' and frm_cnt < g_frm_cnt_max then
- nxt_frm_cnt <= frm_cnt + 1; -- clip at g_frm_cnt_max, application should set g_frm_cnt_max sufficiently large to avoid clipping or set g_frm_cnt_max=0 to effectively disable frame rd due to frm_cnt>0
+ -- clip at g_frm_cnt_max, application should set g_frm_cnt_max sufficiently large to avoid clipping or set g_frm_cnt_max=0 to effectively disable frame rd due to frm_cnt>0
+ nxt_frm_cnt <= frm_cnt + 1;
end if;
if nxt_frm_done = '1' and frm_cnt > 0 then
- nxt_frm_cnt <= frm_cnt - 1; -- to be sure do check that frm_cnt>0
+ -- to be sure do check that frm_cnt>0
+ nxt_frm_cnt <= frm_cnt - 1;
end if;
end if;
end process;
@@ -245,54 +261,80 @@ begin
case state is
when s_idle =>
- nxt_frm_busy <= '0'; -- default no frame
- nxt_frm_err <= '0'; -- default no error
- throttle_cnt_en <= '1'; -- keep on throttling after previous eof
+ -- default no frame
+ nxt_frm_busy <= '0';
+ -- default no error
+ nxt_frm_err <= '0';
+ -- keep on throttling after previous eof
+ throttle_cnt_en <= '1';
if out_throttle = '1' then
- throttle_cnt_en <= '0'; -- stop throttling until next sof
+ -- stop throttling until next sof
+ throttle_cnt_en <= '0';
end if;
if next_out_throttle = '1' then
- if frm_req = '1' or frm_cnt > 0 then -- check for new frame or any already pending frame(s)
- rd_req <= '1'; -- begin reading the FIFO, e.g. if eof is connected to frm_req then there is a frame pending
+ -- check for new frame or any already pending frame(s)
+ if frm_req = '1' or frm_cnt > 0 then
+ -- begin reading the FIFO, e.g. if eof is connected to frm_req then there is a frame pending
+ rd_req <= '1';
nxt_state <= s_sof;
- nxt_out_en <= not frm_flush; -- output enable for read frame or output disable for flush frame
+ -- output enable for read frame or output disable for flush frame
+ nxt_out_en <= not frm_flush;
end if;
end if;
- when s_sof => -- out_throttle='1', no need to check
- nxt_frm_ack <= '1'; -- acknowledge frame request
- if rd_sof = '1' then -- FIFO contains start of frame
+ -- out_throttle='1', no need to check
+ when s_sof =>
+ -- acknowledge frame request
+ nxt_frm_ack <= '1';
+ -- FIFO contains start of frame
+ if rd_sof = '1' then
nxt_frm_busy <= '1';
- throttle_cnt_en <= '1'; -- throttle during frame
- nxt_out_val <= out_en; -- take care in case last time the FIFO contained > 1 frames
- nxt_out_sof <= out_en; -- output pending rd_sof and valid rd_dat
+ -- throttle during frame
+ throttle_cnt_en <= '1';
+ -- take care in case last time the FIFO contained > 1 frames
+ nxt_out_val <= out_en;
+ -- output pending rd_sof and valid rd_dat
+ nxt_out_sof <= out_en;
nxt_state <= s_eof;
if g_throttle_den = 1 or g_throttle_sof = false then
- rd_req <= '1'; -- keep on reading the FIFO after the sof
+ -- keep on reading the FIFO after the sof
+ rd_req <= '1';
throttle_cnt_en <= '0';
end if;
- elsif rd_val = '0' then -- FIFO is empty, it did not contain a frame which. This can happen if frm_req is kept '1' always.
- nxt_state <= s_idle; -- wait for next frm_req
- else -- FIFO is out of frame sync
+ -- FIFO is empty, it did not contain a frame which. This can happen if frm_req is kept '1' always.
+ elsif rd_val = '0' then
+ -- wait for next frm_req
+ nxt_state <= s_idle;
+ -- FIFO is out of frame sync
+ else
nxt_frm_busy <= '1';
- nxt_frm_err <= '1'; -- report error unexpected valid data that is not sof
- rd_req <= '1'; -- try to recover by flush reading the partial frame from FIFO, no need to throttle
+ -- report error unexpected valid data that is not sof
+ nxt_frm_err <= '1';
+ -- try to recover by flush reading the partial frame from FIFO, no need to throttle
+ rd_req <= '1';
nxt_state <= s_err;
end if;
when s_eof =>
- throttle_cnt_en <= '1'; -- throttle during frame
+ -- throttle during frame
+ throttle_cnt_en <= '1';
if next_out_throttle = '1' then
- rd_req <= '1'; -- keep on reading the FIFO
+ -- keep on reading the FIFO
+ rd_req <= '1';
end if;
if out_throttle = '1' then
- if rd_val = '1' then -- for proper throttling there should be sufficient data in the FIFO
- nxt_out_val <= out_en; -- output val
+ -- for proper throttling there should be sufficient data in the FIFO
+ if rd_val = '1' then
+ -- output val
+ nxt_out_val <= out_en;
end if;
if rd_eof = '1' then
- nxt_out_eof <= out_en; -- output eof, stop reading the FIFO
+ -- output eof, stop reading the FIFO
+ nxt_out_eof <= out_en;
if rd_sync = '1' then
- nxt_out_sync <= out_en; -- Pass the rd_sync at the eop to get the LOFAR style of sync before sop that fits dp_frame_fsn, instead of at sop as is used in DP for UniBoard
+ -- Pass the rd_sync at the eop to get the LOFAR style of sync before sop that fits dp_frame_fsn, instead of at sop as is used in DP for UniBoard
+ nxt_out_sync <= out_en;
end if;
- rd_req <= '0'; -- stop reading the FIFO, necessary when g_throttle_den=1
+ -- stop reading the FIFO, necessary when g_throttle_den=1
+ rd_req <= '0';
nxt_frm_done <= '1';
nxt_state <= s_idle;
if g_throttle_eof = false then
@@ -300,11 +342,14 @@ begin
end if;
end if;
end if;
- when others => -- s_err -- try to recover from FIFO lost frame sync, no need to throttle
+ -- s_err -- try to recover from FIFO lost frame sync, no need to throttle
+ when others =>
if rd_eof = '0' then
- rd_req <= '1'; -- keep on flush reading the FIFO until there is an eof
+ -- keep on flush reading the FIFO until there is an eof
+ rd_req <= '1';
else
- nxt_frm_done <= '1'; -- wait for next frm_req
+ -- wait for next frm_req
+ nxt_frm_done <= '1';
nxt_state <= s_idle;
end if;
end case;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_remove.vhd b/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
index 41dbe3e5e8d7d9a21f5067063ecf6e4b986e1e5b..078b5d4d0bb351fcea751d718c91b55bfb2d9ea5 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
@@ -32,7 +32,8 @@ entity dp_frame_remove is
g_hdr_nof_words : natural;
g_tail_nof_words : natural;
g_snk_latency : natural := 1;
- g_internal_bypass : boolean := false -- can be used to eliminate external GENERATE-statements/wiring
+ -- can be used to eliminate external GENERATE-statements/wiring
+ g_internal_bypass : boolean := false
);
port (
mm_rst : in std_logic;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_repack.vhd b/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
index 7bda823b126ca1c283b9e3f0855b50426fbcf909..c6e9e624577f317f9dc49cdfaf5b1c1cdb8a2141 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
@@ -61,7 +61,8 @@ architecture str of dp_frame_repack is
signal repack_eof : std_logic;
begin
no_pack : if g_in_nof_words = g_out_nof_words generate
- out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack at the other end,
+ -- any extra bits will get stripped again by dp_repack at the other end,
+ out_dat <= RESIZE_UVEC(in_dat, out_dat'length);
-- typically g_out_dat_w=g_in_dat_w
out_val <= in_val;
out_sof <= in_sof;
@@ -110,7 +111,8 @@ begin
out_eof => repack_eof
);
- repack_fsn <= RESIZE_SVEC(pack_fsn,repack_fsn'length); -- pack_fsn remains valid
+ -- pack_fsn remains valid
+ repack_fsn <= RESIZE_SVEC(pack_fsn,repack_fsn'length);
frame : entity work.dp_frame
generic map (
@@ -125,7 +127,8 @@ begin
in_val => repack_val,
in_sof => repack_sof,
in_eof => repack_eof,
- in_err => pack_err, -- pack_err remains valid
+ -- pack_err remains valid
+ in_err => pack_err,
out_dat => out_dat,
out_val => out_val,
out_sof => out_sof,
diff --git a/libraries/base/dp/src/vhdl/dp_frame_rx.vhd b/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
index 6a5304e97b99986ec0aa59e0d2326aacebfceae3..8bad34b59acf9928e88779965b21f8c95472ee3b 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
@@ -79,10 +79,12 @@ use work.dp_packetizing_pkg.all;
entity dp_frame_rx is
generic (
g_sfd : std_logic_vector := c_dp_sfd;
- g_lofar : boolean := false; -- when TRUE use same CRC as for LOFAR
+ -- when TRUE use same CRC as for LOFAR
+ g_lofar : boolean := false;
g_dat_w : natural := c_dp_max_w;
g_block_size : natural := 1000;
- g_timeout_w : natural := 0 -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive in_val
+ -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive in_val
+ g_timeout_w : natural := 0
);
port (
rst : in std_logic;
@@ -143,14 +145,19 @@ architecture rtl of dp_frame_rx is
procedure proc_handle_rx_timeout(signal valid : in std_logic;
signal timeout_evt : in std_logic;
signal clr : out std_logic;
- variable v_state : inout t_state) is -- use variable v_state instead of signal to avoid getting latches
+ -- use variable v_state instead of signal to avoid getting latches
+ variable v_state : inout t_state) is
begin
if valid = '1' then
- clr <= '1'; -- restart timeout_cnt during frame rx and remain in current state
+ -- restart timeout_cnt during frame rx and remain in current state
+ clr <= '1';
else
- clr <= '0'; -- let valid inactive timeout count increment
- if timeout_evt = '1' then -- can only occur when g_timeout_w>0
- v_state := s_flush; -- exit to flush state to finish the current rx frame with void data
+ -- let valid inactive timeout count increment
+ clr <= '0';
+ -- can only occur when g_timeout_w>0
+ if timeout_evt = '1' then
+ -- exit to flush state to finish the current rx frame with void data
+ v_state := s_flush;
end if;
end if;
end proc_handle_rx_timeout;
@@ -222,7 +229,8 @@ begin
count => timeout_cnt
);
- timeout_evt <= timeout_cnt(g_timeout_w); -- check MSbit for timeout of 2**g_timeout_w clk cycles
+ -- check MSbit for timeout of 2**g_timeout_w clk cycles
+ timeout_evt <= timeout_cnt(g_timeout_w);
assert not(rising_edge(clk) and timeout_evt = '1') report "rad_frame_rx timeout occurred!" severity WARNING;
@@ -233,20 +241,24 @@ begin
------------------------------------------------------------------------------
-- XON/XOFF rx frame flow control
------------------------------------------------------------------------------
- nxt_xon_reg <= out_xon; -- register out_xon to ease timing closure, because out_xon may come from far on the chip and some more cycles latency for xon is acceptable
+ -- register out_xon to ease timing closure, because out_xon may come from far on the chip and some more cycles latency for xon is acceptable
+ nxt_xon_reg <= out_xon;
------------------------------------------------------------------------------
-- Rx state machine
------------------------------------------------------------------------------
p_state: process(state, crc, cnt, in_val_reg, in_dat_reg, prev_in_dat_reg, xon_reg, timeout_evt, flush_val)
- variable v_nxt_state : t_state; -- use variable instead of signal to avoid getting latches with proc_handle_rx_timeout()
+ -- use variable instead of signal to avoid getting latches with proc_handle_rx_timeout()
+ variable v_nxt_state : t_state;
begin
- nxt_timeout_cnt_clr <= '1'; -- default no timeout_cnt
+ -- default no timeout_cnt
+ nxt_timeout_cnt_clr <= '1';
nxt_flush_en <= '0';
nxt_crc <= crc;
nxt_cnt <= cnt;
- nxt_out_dat <= in_dat_reg; -- default pass on input dat
+ -- default pass on input dat
+ nxt_out_dat <= in_dat_reg;
nxt_out_val <= '0';
nxt_out_sof <= '0';
nxt_out_eof <= '0';
@@ -260,9 +272,11 @@ begin
when s_sof =>
nxt_crc <= (others => '1');
nxt_cnt <= 0;
- if xon_reg = '1' then -- flush any input rx frame if xon_reg is XOFF
+ -- flush any input rx frame if xon_reg is XOFF
+ if xon_reg = '1' then
if in_val_reg = '1' then
- if in_dat_reg = c_sfd and prev_in_dat_reg = c_idle then -- ignore in_val during c_idle
+ -- ignore in_val during c_idle
+ if in_dat_reg = c_sfd and prev_in_dat_reg = c_idle then
v_nxt_state := s_fsn;
end if;
end if;
@@ -278,7 +292,8 @@ begin
when s_eof =>
if in_val_reg = '1' then
nxt_out_val <= '1';
- if cnt = g_block_size then -- fill in brc based on rx crc result
+ -- fill in brc based on rx crc result
+ if cnt = g_block_size then
nxt_out_eof <= '1';
nxt_out_dat <= c_brc_ok;
if c_dp_crc_w > g_dat_w then
@@ -292,21 +307,27 @@ begin
end if;
v_nxt_state := s_sof;
else
- nxt_cnt <= cnt + 1; -- count payload data
+ -- count payload data
+ nxt_cnt <= cnt + 1;
end if;
end if;
-- Exit to s_flush in case of rx timeout
proc_handle_rx_timeout(in_val_reg, timeout_evt, nxt_timeout_cnt_clr, v_nxt_state);
- when others => -- s_flush -- this state can only be reached if g_timeout_w>0
- nxt_flush_en <= '1'; -- enable flush frame due to in_val_reg inactive timeout
+ -- s_flush -- this state can only be reached if g_timeout_w>0
+ when others =>
+ -- enable flush frame due to in_val_reg inactive timeout
+ nxt_flush_en <= '1';
if flush_val = '1' then
- nxt_out_val <= '1'; -- flush rx frame with void data
+ -- flush rx frame with void data
+ nxt_out_val <= '1';
if cnt >= g_block_size then
nxt_out_eof <= '1';
- nxt_out_dat <= c_brc_err; -- fill in c_brc_err for flushed rx frame
+ -- fill in c_brc_err for flushed rx frame
+ nxt_out_dat <= c_brc_err;
v_nxt_state := s_sof;
else
- nxt_cnt <= cnt + 1; -- count payload data
+ -- count payload data
+ nxt_cnt <= cnt + 1;
end if;
end if;
end case;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
index 6d587242c714b91955a5a045c0c90bd96e81b6fc..f3338aab780a38ebfe04638812cc1d842ae979e3 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
@@ -51,10 +51,14 @@ entity dp_frame_scheduler is
generic (
g_technology : natural := c_tech_select_default;
g_dat_w : natural := 16;
- g_nof_input : natural := 2; -- >= 1
- g_fifo_rl : natural := 1; -- for all input use 0 for look ahead FIFO, 1 for normal FIFO
- g_fifo_size : t_natural_arr := (1024, 1024); -- must match g_nof_input-1 DOWNTO 0
- g_fifo_fill : t_natural_arr := (0, 0) -- must match g_nof_input-1 DOWNTO 0
+ -- >= 1
+ g_nof_input : natural := 2;
+ -- for all input use 0 for look ahead FIFO, 1 for normal FIFO
+ g_fifo_rl : natural := 1;
+ -- must match g_nof_input-1 DOWNTO 0
+ g_fifo_size : t_natural_arr := (1024, 1024);
+ -- must match g_nof_input-1 DOWNTO 0
+ g_fifo_fill : t_natural_arr := (0, 0)
);
port (
rst : in std_logic;
@@ -64,7 +68,8 @@ entity dp_frame_scheduler is
in_val : in std_logic_vector(g_nof_input - 1 downto 0);
in_sof : in std_logic_vector(g_nof_input - 1 downto 0);
in_eof : in std_logic_vector(g_nof_input - 1 downto 0);
- in_dis : in std_logic_vector(g_nof_input - 1 downto 0) := (others => '0'); -- optional input disable control at frame level
+ -- optional input disable control at frame level
+ in_dis : in std_logic_vector(g_nof_input - 1 downto 0) := (others => '0');
out_dat : out std_logic_vector(g_dat_w - 1 downto 0);
out_val : out std_logic;
out_sof : out std_logic;
@@ -165,7 +170,8 @@ begin
in_siso => OPEN,
in_sosi => snk_in(I),
-- Frame out
- out_siso => wr_siso(I), -- flush control via xon, ready is not used and only passed on
+ -- flush control via xon, ready is not used and only passed on
+ out_siso => wr_siso(I),
out_sosi => wr_sosi(I)
);
@@ -195,10 +201,12 @@ begin
rst => rst,
clk => clk,
-- ST sink
- snk_out => OPEN, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out => OPEN,
snk_in => wr_sosi(I),
-- ST source
- src_in => rd_siso(I), -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => rd_siso(I),
src_out => rd_sosi(I),
wr_ful => gp_out(I)
@@ -252,11 +260,13 @@ begin
rd_req(in_sel + 1) <= '1';
end if;
end if;
- when others => -- s_output
+ -- s_output
+ when others =>
-- output the frame
rd_req(in_sel) <= '1';
if rd_eof(in_sel) = '1' then
- rd_req(in_sel) <= '0'; -- eof so stop reading the FIFO, this also prevents reading an immediate next rd_sof for this in_sel to allow selecting next input in s_idle
+ -- eof so stop reading the FIFO, this also prevents reading an immediate next rd_sof for this in_sel to allow selecting next input in s_idle
+ rd_req(in_sel) <= '0';
nxt_state <= s_idle;
end if;
end case;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_status.vhd b/libraries/base/dp/src/vhdl/dp_frame_status.vhd
index abff3ccbce1c083e43e0999622f2285906f6e407..9931d7db567efe67ccee5f625a06776837f6a114 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_status.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_status.vhd
@@ -64,23 +64,30 @@ architecture rtl of dp_frame_status is
signal debug_brc : std_logic;
signal debug_cnt : std_logic_vector(g_cnt_w - 1 downto 0);
- signal sync_dly : std_logic; -- fdelay sync one cycle to compensate for payevent delay in ei_evt.
+ -- fdelay sync one cycle to compensate for payevent delay in ei_evt.
+ signal sync_dly : std_logic;
- signal fsync : std_logic; -- frame sync from in_dat header at in_sof
+ -- frame sync from in_dat header at in_sof
+ signal fsync : std_logic;
signal fsync_det : std_logic;
signal fsync_hld : std_logic;
signal nxt_fsync_hld : std_logic;
- signal brc : std_logic; -- frame brc from in_dat brc at in_eof
- signal brc_det : std_logic; -- aggregate brc
+ -- frame brc from in_dat brc at in_eof
+ signal brc : std_logic;
+ -- aggregate brc
+ signal brc_det : std_logic;
signal brc_hld : std_logic;
signal nxt_brc_hld : std_logic;
- signal dis_det : std_logic; -- frame got discarded due to mis alignment
- signal dis_hld : std_logic; -- aggregate discarded
+ -- frame got discarded due to mis alignment
+ signal dis_det : std_logic;
+ -- aggregate discarded
+ signal dis_hld : std_logic;
signal nxt_dis_hld : std_logic;
- signal cnt : std_logic_vector(g_cnt_w - 1 downto 0); -- frame count
+ -- frame count
+ signal cnt : std_logic_vector(g_cnt_w - 1 downto 0);
signal nxt_cnt : std_logic_vector(cnt'range);
signal cnt_hld : std_logic_vector(cnt'range);
signal nxt_cnt_hld : std_logic_vector(cnt'range);
@@ -129,8 +136,10 @@ begin
port map (
clk => clk,
rst => rst,
- switch_high => fsync, -- frame sync
- switch_low => sync_dly, -- system sync
+ -- frame sync
+ switch_high => fsync,
+ -- system sync
+ switch_low => sync_dly,
out_level => fsync_det
);
@@ -139,8 +148,10 @@ begin
port map (
clk => clk,
rst => rst,
- switch_high => brc, -- frame brc
- switch_low => fsync, -- frame sync
+ -- frame brc
+ switch_high => brc,
+ -- frame sync
+ switch_low => fsync,
out_level => brc_det
);
@@ -149,8 +160,10 @@ begin
port map (
clk => clk,
rst => rst,
- switch_high => in_dis, -- frame discarded
- switch_low => fsync, -- frame sync
+ -- frame discarded
+ switch_high => in_dis,
+ -- frame sync
+ switch_low => fsync,
out_level => dis_det
);
diff --git a/libraries/base/dp/src/vhdl/dp_frame_tx.vhd b/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
index 01dbbf256a3037d038122e4ba592fdce060154ab..292583b891446ed9ef365deb78444c2e1cca1fc3 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
@@ -66,7 +66,8 @@ use work.dp_packetizing_pkg.all;
entity dp_frame_tx is
generic (
g_sfd : std_logic_vector := c_dp_sfd;
- g_lofar : boolean := false; -- when TRUE use same CRC as for LOFAR
+ -- when TRUE use same CRC as for LOFAR
+ g_lofar : boolean := false;
g_dat_w : natural := c_dp_max_w
);
port (
@@ -183,34 +184,42 @@ begin
end if;
-- set default nxt_out_dat
- nxt_out_dat <= in_dat_dly2; -- pass on input dat
+ -- pass on input dat
+ nxt_out_dat <= in_dat_dly2;
nxt_out_val <= in_val_dly2;
nxt_out_sof <= '0';
nxt_out_eof <= '0';
- nxt_frame_busy <= frame_busy; -- hold to know when a frame is being transmitted or not
+ -- hold to know when a frame is being transmitted or not
+ nxt_frame_busy <= frame_busy;
-- overrule default nxt_crc, nxt_out_dat
if in_sof_reg = '1' then
- nxt_crc <= (others => '1'); -- init crc
- nxt_out_dat <= c_idle; -- prepend idle word
+ -- init crc
+ nxt_crc <= (others => '1');
+ -- prepend idle word
+ nxt_out_dat <= c_idle;
nxt_out_val <= '1';
nxt_out_sof <= '1';
nxt_frame_busy <= '1';
elsif in_sof_dly = '1' then
- nxt_crc <= (others => '1'); -- init crc
- nxt_out_dat <= c_sfd; -- prepend sfd word
+ -- init crc
+ nxt_crc <= (others => '1');
+ -- prepend sfd word
+ nxt_out_dat <= c_sfd;
nxt_out_val <= '1';
elsif in_eof_dly2 = '1' then
nxt_frame_busy <= '0';
- nxt_out_dat <= RESIZE_UVEC(crc, g_dat_w); -- fill in calculated tx crc and account for brc
+ -- fill in calculated tx crc and account for brc
+ nxt_out_dat <= RESIZE_UVEC(crc, g_dat_w);
if in_dat_dly2 /= c_brc_ok then
nxt_out_dat <= not RESIZE_UVEC(crc, g_dat_w);
end if;
nxt_out_eof <= '1';
elsif in_val_dly2 = '0' then
if frame_busy = '0' then
- nxt_out_dat <= c_idle; -- insert idle word when out_val is inactive between frames
+ -- insert idle word when out_val is inactive between frames
+ nxt_out_dat <= c_idle;
--ELSE
-- do not transmit idle when out_val is inactive during a frame to reduce potential false sync at receiver
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_gap.vhd b/libraries/base/dp/src/vhdl/dp_gap.vhd
index 9f487ec1c7bec965e72ac55474c6c4f6720bea57..ced776dd59a5d51ee8985a5942b4d1cd85acd4e7 100644
--- a/libraries/base/dp/src/vhdl/dp_gap.vhd
+++ b/libraries/base/dp/src/vhdl/dp_gap.vhd
@@ -43,8 +43,10 @@ entity dp_gap is
generic (
g_dat_len : natural := 1000000;
g_gap_len : natural := 5;
- g_gap_extend : boolean := false -- if TRUE, the first valid='0' cycle is extended to g_gap_len by de-assertion of snk_out.ready.
- ); -- This results in all gaps having a minimum length of g_gap_len.
+ -- if TRUE, the first valid='0' cycle is extended to g_gap_len by de-assertion of snk_out.ready.
+ g_gap_extend : boolean := false
+ -- This results in all gaps having a minimum length of g_gap_len.
+ );
port (
clk : in std_logic;
rst : in std_logic;
@@ -93,43 +95,53 @@ begin
nxt_state <= state;
nxt_clk_cnt <= clk_cnt;
nxt_gap_cnt <= gap_cnt;
- snk_out <= src_in; -- Pass on the flow control by default
+ -- Pass on the flow control by default
+ snk_out <= src_in;
case state is
- when s_wait_for_val => -- Wait for valid data to come in
+ -- Wait for valid data to come in
+ when s_wait_for_val =>
if snk_in.valid = '1' then
nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w);
nxt_gap_cnt <= (others => '0');
nxt_state <= s_counting;
end if;
- when s_counting => -- Start counting cycles
+ -- Start counting cycles
+ when s_counting =>
nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
- if clk_cnt = TO_UVEC(g_dat_len - 1, c_dat_len_w) then -- time to force a gap
+ -- time to force a gap
+ if clk_cnt = TO_UVEC(g_dat_len - 1, c_dat_len_w) then
nxt_state <= s_force_not_rdy;
snk_out.ready <= '0';
- nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w); -- we already have 1 clk cycle with ready='0' here
+ -- we already have 1 clk cycle with ready='0' here
+ nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w);
end if;
- if snk_in.valid = '0' then -- Also start counting any invalid cycles
+ -- Also start counting any invalid cycles
+ if snk_in.valid = '0' then
if g_gap_extend = true then
- snk_out.ready <= '0'; -- Keep ready de-asserted. Gap_cnt will increment so it will be released again after g_gap_len.
+ -- Keep ready de-asserted. Gap_cnt will increment so it will be released again after g_gap_len.
+ snk_out.ready <= '0';
end if;
nxt_gap_cnt <= INCR_UVEC(gap_cnt, 1);
else
nxt_gap_cnt <= (others => '0');
end if;
- if gap_cnt = TO_UVEC(g_gap_len - 1, c_gap_len_w) and snk_in.valid = '0' then -- A gap of sufficient length occured by itself (or valid='0' was extended); no need to force gap
+ -- A gap of sufficient length occured by itself (or valid='0' was extended); no need to force gap
+ if gap_cnt = TO_UVEC(g_gap_len - 1, c_gap_len_w) and snk_in.valid = '0' then
-- We've counted g_gap_len-1, plus the current gap cycle = g_gap_len
nxt_gap_cnt <= (others => '0');
nxt_clk_cnt <= (others => '0');
nxt_state <= s_wait_for_val;
if g_gap_extend = true then
- snk_out.ready <= src_in.ready; -- Release the ready signal again if it was forced down because of gap extension
+ -- Release the ready signal again if it was forced down because of gap extension
+ snk_out.ready <= src_in.ready;
end if;
end if;
- when s_force_not_rdy => -- Force snk_out.ready to '0' for g_gap_len clk cycles
+ -- Force snk_out.ready to '0' for g_gap_len clk cycles
+ when s_force_not_rdy =>
snk_out.ready <= '0';
nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
if clk_cnt = TO_UVEC(g_gap_len - 1, c_dat_len_w) then
@@ -141,7 +153,8 @@ begin
end generate;
- no_rtl : if g_gap_len = 0 generate -- bypass
+ -- bypass
+ no_rtl : if g_gap_len = 0 generate
snk_out <= src_in;
end generate;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd b/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
index 4de916688351f6f59cc3429bbab94ce4432705dd..0a5e4d75e39e56638e7132fd01510b959aa178ca 100644
--- a/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
@@ -35,9 +35,11 @@ entity dp_hdr_insert is
g_data_w : natural;
g_symbol_w : natural;
g_hdr_nof_words : natural;
- g_internal_bypass : boolean := false; -- can be used to eliminate external GENERATE-statements/wiring
+ -- can be used to eliminate external GENERATE-statements/wiring
+ g_internal_bypass : boolean := false;
g_init_hdr : string := "UNUSED";
- g_dp_on_at_init : std_logic := '0' -- Enable data path at default
+ -- Enable data path at default
+ g_dp_on_at_init : std_logic := '0'
);
port (
mm_rst : in std_logic;
@@ -46,8 +48,10 @@ entity dp_hdr_insert is
st_rst : in std_logic;
st_clk : in std_logic;
- ram_mosi : in t_mem_mosi; -- Hdr write port
- reg_mosi : in t_mem_mosi; -- Hdr release
+ -- Hdr write port
+ ram_mosi : in t_mem_mosi;
+ -- Hdr release
+ reg_mosi : in t_mem_mosi;
snk_out : out t_dp_siso;
snk_in : in t_dp_sosi;
@@ -92,7 +96,8 @@ begin
concat_sosi_arr(0) <= hdr_sosi;
concat_sosi_arr(1) <= snk_in;
- u_dp_concat : entity work.dp_concat -- RL = 1
+ -- RL = 1
+ u_dp_concat : entity work.dp_concat
generic map (
g_data_w => g_data_w,
g_symbol_w => g_symbol_w
diff --git a/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd b/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
index c924c29515f109ca45763b7073f08a7e6e3641e1..11c719754b1e3ad8a0658627296fd3c34ec280a1 100644
--- a/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
@@ -78,7 +78,8 @@ begin
split_siso_arr(1) <= src_in;
src_out <= split_sosi_arr(1);
- u_split : entity work.dp_split -- RL = 1
+ -- RL = 1
+ u_split : entity work.dp_split
generic map (
g_data_w => g_data_w,
g_symbol_w => g_symbol_w,
diff --git a/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd b/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
index 18f45d4172772ae7d951e0ba97e3e48587ac4d40..86f8ff11b580a2dd55e538ba45aafbfbf41a8904 100644
--- a/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
@@ -51,8 +51,10 @@ architecture rtl of dp_hold_ctrl is
signal hi_ctrl : std_logic;
signal lo_ctrl : std_logic;
begin
- hi_ctrl <= in_ctrl and not ready; -- capture
- lo_ctrl <= not in_ctrl and ready; -- release
+ -- capture
+ hi_ctrl <= in_ctrl and not ready;
+ -- release
+ lo_ctrl <= not in_ctrl and ready;
u_hld_ctrl : entity common_lib.common_switch
port map (
diff --git a/libraries/base/dp/src/vhdl/dp_hold_input.vhd b/libraries/base/dp/src/vhdl/dp_hold_input.vhd
index f5e5dd457290a39832a7dcdf3dffa7825be25b59..64f413a45d7750af6ca27aa6d78313c8a895c98a 100644
--- a/libraries/base/dp/src/vhdl/dp_hold_input.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hold_input.vhd
@@ -64,19 +64,23 @@ entity dp_hold_input is
-- ST source
src_in : in t_dp_siso;
next_src_out : out t_dp_sosi;
- pend_src_out : out t_dp_sosi; -- the SOSI data fields are the same as for next_src_out
- src_out_reg : in t_dp_sosi -- uses only the SOSI data fields
+ -- the SOSI data fields are the same as for next_src_out
+ pend_src_out : out t_dp_sosi;
+ -- uses only the SOSI data fields
+ src_out_reg : in t_dp_sosi
);
end dp_hold_input;
architecture rtl of dp_hold_input is
signal i_pend_src_out : t_dp_sosi;
- signal hold_in : t_dp_sosi; -- uses only the SOSI ctrl fields
+ -- uses only the SOSI ctrl fields
+ signal hold_in : t_dp_sosi;
begin
pend_src_out <= i_pend_src_out;
-- SISO:
- snk_out <= src_in; -- No change in ready latency, pass on xon frame level flow control
+ -- No change in ready latency, pass on xon frame level flow control
+ snk_out <= src_in;
-- SOSI:
-- Take care of active snk_in.valid, snk_in.sync, snk_in.sop and snk_in.eop
@@ -129,9 +133,11 @@ begin
begin
-- Pend data
if snk_in.valid = '1' then
- i_pend_src_out <= snk_in; -- Input data
+ -- Input data
+ i_pend_src_out <= snk_in;
else
- i_pend_src_out <= src_out_reg; -- Hold data
+ -- Hold data
+ i_pend_src_out <= src_out_reg;
end if;
i_pend_src_out.valid <= snk_in.valid or hold_in.valid;
i_pend_src_out.sync <= snk_in.sync or hold_in.sync;
diff --git a/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd b/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
index 5335ee16ed78480f4a624009dcb6de60297a4bb6..1dbcb9865e947ae366b6b270a553e2d890c944a4 100755
--- a/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
+++ b/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
@@ -67,7 +67,8 @@ use work.dp_stream_pkg.all;
--
entity dp_interleave_n_to_one is
generic (
- g_pipeline : natural := 1; -- 0 for combinatorial, > 0 for registers
+ -- 0 for combinatorial, > 0 for registers
+ g_pipeline : natural := 1;
g_nof_inputs : natural
);
port (
@@ -90,8 +91,10 @@ architecture rtl of dp_interleave_n_to_one is
input_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
end record;
- signal s : t_reg; -- combinatoral state
- signal r : t_reg; -- register state
+ -- combinatoral state
+ signal s : t_reg;
+ -- register state
+ signal r : t_reg;
signal shift_ready : std_logic;
signal snk_out : t_dp_siso;
@@ -119,15 +122,18 @@ begin
s.cnt_en <= r.cnt_en;
s.cnt <= r.cnt;
if snk_in_arr(0).valid = '1' then
- s.cnt_en <= '1'; -- enable cnt for this valid g_nof_inputs
- s.cnt <= 0; -- wrap or force restart at valid
+ -- enable cnt for this valid g_nof_inputs
+ s.cnt_en <= '1';
+ -- wrap or force restart at valid
+ s.cnt <= 0;
elsif r.ready = '1' then
if r.cnt_en = '1' then
if r.cnt < g_nof_inputs - 1 then
s.cnt <= r.cnt + 1;
else
s.cnt_en <= '0';
- s.cnt <= 0; -- wrap after every g_nof_inputs valid output samples
+ -- wrap after every g_nof_inputs valid output samples
+ s.cnt <= 0;
end if;
end if;
end if;
@@ -136,12 +142,15 @@ begin
-- Use input_arr to load and shift parallel input via input_arr(0)
p_input_arr : process(snk_in_arr, s, r)
begin
- s.input_arr <= r.input_arr; -- default hold snk_in_arr in input_arr
+ -- default hold snk_in_arr in input_arr
+ s.input_arr <= r.input_arr;
if snk_in_arr(0).valid = '1'THEN
- s.input_arr <= snk_in_arr; -- load valid snk_in_arr
+ -- load valid snk_in_arr
+ s.input_arr <= snk_in_arr;
elsif r.ready = '1' then
if s.cnt > 0 then
- s.input_arr(g_nof_inputs - 2 downto 0) <= r.input_arr(g_nof_inputs - 1 downto 1); -- Shift out in series via input_arr(0)
+ -- Shift out in series via input_arr(0)
+ s.input_arr(g_nof_inputs - 2 downto 0) <= r.input_arr(g_nof_inputs - 1 downto 1);
end if;
end if;
end process;
@@ -158,19 +167,24 @@ begin
if snk_in_arr(0).valid = '1'THEN
-- Output first of parallel g_nof_inputs
- out_sosi <= s.input_arr(0); -- first can output sync, sop
+ -- first can output sync, sop
+ out_sosi <= s.input_arr(0);
if g_nof_inputs > 1 then
- out_sosi.eop <= '0'; -- output eop at last of g_nof_inputs
+ -- output eop at last of g_nof_inputs
+ out_sosi.eop <= '0';
end if;
elsif r.ready = '1' then
if s.cnt > 0 then
-- Output remaining of parallel g_nof_inputs in series
out_sosi <= s.input_arr(0);
- out_sosi.sync <= '0'; -- sync was output at first
- out_sosi.sop <= '0'; -- sop was output at first
+ -- sync was output at first
+ out_sosi.sync <= '0';
+ -- sop was output at first
+ out_sosi.sop <= '0';
if s.cnt < g_nof_inputs - 1 then
- out_sosi.eop <= '0'; -- output eop at last of g_nof_inputs
+ -- output eop at last of g_nof_inputs
+ out_sosi.eop <= '0';
end if;
end if;
end if;
@@ -190,7 +204,8 @@ begin
-- Pipeline output to easy timing closure
u_pipeline_output : entity work.dp_pipeline
generic map (
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
+ -- 0 for wires, > 0 for registers
+ g_pipeline => g_pipeline
)
port map (
rst => rst,
diff --git a/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd b/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
index 237ba315c23b67c8082df66a5a01bf0b5e270a41..d6eb865c3fe83c0e1f7f390553cc7964e8bc88e0 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
@@ -55,7 +55,8 @@ entity dp_latency_adapter is
rst : in std_logic;
clk : in std_logic;
-- Monitor internal FIFO filling
- fifo_usedw : out std_logic_vector(ceil_log2(2 + g_in_latency) - 1 downto 0); -- see description of c_fifo_size, c_usedw_w for explanation of why +2
+ -- see description of c_fifo_size, c_usedw_w for explanation of why +2
+ fifo_usedw : out std_logic_vector(ceil_log2(2 + g_in_latency) - 1 downto 0);
fifo_ful : out std_logic;
fifo_emp : out std_logic;
-- ST sink
@@ -76,31 +77,40 @@ architecture rtl of dp_latency_adapter is
-- Use g_in_latency+1 words for the FIFO data array, to go to zero latency
constant c_high : natural := g_in_latency;
- constant c_fifo_size : natural := g_in_latency + 1; -- +1 because RL=0 also requires a word
- constant c_usedw_w : natural := ceil_log2(c_fifo_size+1); -- +1 because to store value 2**n requires n+1 bits
+ -- +1 because RL=0 also requires a word
+ constant c_fifo_size : natural := g_in_latency + 1;
+ -- +1 because to store value 2**n requires n+1 bits
+ constant c_usedw_w : natural := ceil_log2(c_fifo_size+1);
signal fifo_reg : t_dp_sosi_arr(c_high downto 0);
signal nxt_fifo_reg : t_dp_sosi_arr(c_high downto 0);
- signal fifo_reg_valid : std_logic_vector(c_high downto 0); -- debug signal for Wave window
+ -- debug signal for Wave window
+ signal fifo_reg_valid : std_logic_vector(c_high downto 0);
signal nxt_fifo_usedw : std_logic_vector(c_usedw_w - 1 downto 0);
signal nxt_fifo_ful : std_logic;
signal nxt_fifo_emp : std_logic;
- signal ff_siso : t_dp_siso; -- SISO ready
- signal ff_sosi : t_dp_sosi; -- SOSI
+ -- SISO ready
+ signal ff_siso : t_dp_siso;
+ -- SOSI
+ signal ff_sosi : t_dp_sosi;
signal i_snk_out : t_dp_siso := c_dp_siso_rdy;
begin
-- Use i_snk_out with defaults to force unused snk_out bits and fields to '0'
snk_out <= i_snk_out;
- gen_wires : if c_diff_latency = 0 generate -- g_out_latency = g_in_latency
- i_snk_out <= src_in; -- SISO
- src_out <= snk_in; -- SOSI
+ -- g_out_latency = g_in_latency
+ gen_wires : if c_diff_latency = 0 generate
+ -- SISO
+ i_snk_out <= src_in;
+ -- SOSI
+ src_out <= snk_in;
end generate gen_wires;
- no_fifo : if c_diff_latency > 0 generate -- g_out_latency > g_in_latency
+ -- g_out_latency > g_in_latency
+ no_fifo : if c_diff_latency > 0 generate
-- Go from g_in_latency to required larger g_out_latency
u_latency : entity work.dp_latency_increase
generic map (
@@ -119,7 +129,8 @@ begin
);
end generate no_fifo;
- gen_fifo : if c_diff_latency < 0 generate -- g_out_latency < g_in_latency
+ -- g_out_latency < g_in_latency
+ gen_fifo : if c_diff_latency < 0 generate
-- Register [0] contains the FIFO output with zero ready latency
ff_sosi <= fifo_reg(0);
@@ -183,7 +194,8 @@ begin
-- Put input data at the first available location dependent on ff_siso.ready, no need to explicitly check snk_in.valid
if fifo_reg(0).valid = '0' then
- nxt_fifo_reg(0) <= snk_in; -- fifo_reg is empty
+ -- fifo_reg is empty
+ nxt_fifo_reg(0) <= snk_in;
else
-- The fifo_reg is not empty, so filled to some extend
for I in 1 to c_high loop
@@ -202,13 +214,18 @@ begin
if c_pass_sync_during_not_valid = true and snk_in.sync = '1' and snk_in.valid = '0' then
-- Otherwise for input sync during input data not valid we need to insert the input sync at the last location with valid data independent of ff_siso.ready, to avoid that it gets lost.
-- For streams that do not use the sync this logic will be void and optimize away by synthesis, because then snk_in.sync = '0' fixed.
- if fifo_reg(c_high).valid = '1' then -- fifo_reg is full
- nxt_fifo_reg(c_high).sync <= '1'; -- insert input sync
+ -- fifo_reg is full
+ if fifo_reg(c_high).valid = '1' then
+ -- insert input sync
+ nxt_fifo_reg(c_high).sync <= '1';
else
- for I in c_high - 1 downto 0 loop -- fifo_reg is filled to some extend, so not full and not empty
+ -- fifo_reg is filled to some extend, so not full and not empty
+ for I in c_high - 1 downto 0 loop
if fifo_reg(I).valid = '1' then
- nxt_fifo_reg(I + 1).sync <= '0'; -- overrule default sync assignment
- nxt_fifo_reg(I).sync <= '1'; -- insert input sync
+ -- overrule default sync assignment
+ nxt_fifo_reg(I + 1).sync <= '0';
+ -- insert input sync
+ nxt_fifo_reg(I).sync <= '1';
exit;
end if;
end loop;
@@ -230,7 +247,8 @@ begin
fifo_reg_valid <= func_dp_stream_arr_get(fifo_reg, "VALID");
- nxt_fifo_ful <= '1' when TO_UINT(nxt_fifo_usedw) >= c_high + 1 else '0'; -- using >= or = is equivalent here
+ -- using >= or = is equivalent here
+ nxt_fifo_ful <= '1' when TO_UINT(nxt_fifo_usedw) >= c_high + 1 else '0';
nxt_fifo_emp <= '1' when TO_UINT(nxt_fifo_usedw) = 0 else '0';
-- Go from 0 FIFO latency to required g_out_latency (only wires when g_out_latency=0)
diff --git a/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd b/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
index 77c10e03b932bb464eae94ee8ad2a69cc47d5968..b48c88b123de50f57b8c8b2e10cc5f031b3c1321 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
@@ -39,16 +39,21 @@ use work.dp_stream_pkg.all;
entity dp_latency_fifo is
generic (
- g_bypass : boolean := false; -- for clarity rather use g_bypass=TRUE than equivalent g_fifo_size=0
- g_input_rl : natural := 1; -- input ready latency
- g_output_rl : natural := 1; -- output ready latency
- g_fifo_size : natural := 1 -- must be g_fifo_size > g_output_rl - g_input_rl
+ -- for clarity rather use g_bypass=TRUE than equivalent g_fifo_size=0
+ g_bypass : boolean := false;
+ -- input ready latency
+ g_input_rl : natural := 1;
+ -- output ready latency
+ g_output_rl : natural := 1;
+ -- must be g_fifo_size > g_output_rl - g_input_rl
+ g_fifo_size : natural := 1
);
port (
rst : in std_logic;
clk : in std_logic;
-- Monitor FIFO filling
- usedw : out std_logic_vector(ceil_log2(2 + g_input_rl + g_fifo_size) - 1 downto 0); -- +3 to match dp_latency_adapter usedw width
+ -- +3 to match dp_latency_adapter usedw width
+ usedw : out std_logic_vector(ceil_log2(2 + g_input_rl + g_fifo_size) - 1 downto 0);
wr_ful : out std_logic;
rd_emp : out std_logic;
-- ST sink
@@ -81,17 +86,21 @@ begin
i_snk_out.xon <= src_in.xon;
-- pass on sample level flow control similar as in dp_latency_adapter but now with extra margin of g_fifo_size
- p_snk_out_ready : process(i_usedw, fifo_snk_out, snk_in) -- equivalent to p_snk_out_ready in dp_latency_adapter
+ -- equivalent to p_snk_out_ready in dp_latency_adapter
+ p_snk_out_ready : process(i_usedw, fifo_snk_out, snk_in)
begin
i_snk_out.ready <= '0';
- if fifo_snk_out.ready = '1' then -- equivalent to ff_siso.ready in dp_latency_adapter
+ -- equivalent to ff_siso.ready in dp_latency_adapter
+ if fifo_snk_out.ready = '1' then
-- Default snk_out ready when the source is ready.
i_snk_out.ready <= '1';
else
-- Extra snk_out ready to look ahead for fifo_snk_out RL = 0 and to fill the FIFO.
- if TO_UINT(i_usedw) < c_adapter_input_rl then -- equivalent to fifo_reg(0).valid='0' in dp_latency_adapter
+ -- equivalent to fifo_reg(0).valid='0' in dp_latency_adapter
+ if TO_UINT(i_usedw) < c_adapter_input_rl then
i_snk_out.ready <= '1';
- elsif TO_UINT(i_usedw) = c_adapter_input_rl then -- equivalent to fifo_reg(1).valid='0' in dp_latency_adapter
+ -- equivalent to fifo_reg(1).valid='0' in dp_latency_adapter
+ elsif TO_UINT(i_usedw) = c_adapter_input_rl then
i_snk_out.ready <= not(snk_in.valid);
end if;
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_latency_increase.vhd b/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
index 4ac0f424655f72c0f6114bed98c449bfec17a798..23e7ae2a808d7a19fa9ee43b0dd58de740525708 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
@@ -45,8 +45,10 @@ use work.dp_stream_pkg.all;
entity dp_latency_increase is
generic (
- g_in_latency : natural := 0; -- >= 0
- g_incr_latency : natural := 2 -- >= 0
+ -- >= 0
+ g_in_latency : natural := 0;
+ -- >= 0
+ g_incr_latency : natural := 2
);
port (
rst : in std_logic;
@@ -73,13 +75,16 @@ begin
-- Support wires only for g_incr_latency=0
no_latency : if g_incr_latency = 0 generate
- i_snk_out <= src_in; -- SISO
- src_out <= snk_in; -- SOSI
+ -- SISO
+ i_snk_out <= src_in;
+ -- SOSI
+ src_out <= snk_in;
end generate no_latency;
gen_latency : if g_incr_latency > 0 generate
-- SISO
- reg_ready(0) <= src_in.ready; -- use reg_ready(0) to combinatorially store src_in.ready
+ -- use reg_ready(0) to combinatorially store src_in.ready
+ reg_ready(0) <= src_in.ready;
p_clk : process(rst, clk)
begin
@@ -90,8 +95,10 @@ begin
end if;
end process;
- i_snk_out.xon <= src_in.xon; -- Pass on frame level flow control
- i_snk_out.ready <= reg_ready(g_incr_latency); -- Adjust ready latency
+ -- Pass on frame level flow control
+ i_snk_out.xon <= src_in.xon;
+ -- Adjust ready latency
+ i_snk_out.ready <= reg_ready(g_incr_latency);
-- SOSI
gen_out : if g_in_latency /= 0 generate
diff --git a/libraries/base/dp/src/vhdl/dp_loopback.vhd b/libraries/base/dp/src/vhdl/dp_loopback.vhd
index c28f0223b38c2075e710c0decdd323ac3b4d3bc6..c08496abfefe9350b7516a345c275523386ae704 100644
--- a/libraries/base/dp/src/vhdl/dp_loopback.vhd
+++ b/libraries/base/dp/src/vhdl/dp_loopback.vhd
@@ -50,8 +50,10 @@ use work.dp_stream_pkg.all;
entity dp_loopback is
generic (
g_use_pkt : boolean := true;
- g_flush_not_hold : boolean := true -- Use TRUE for uninterruptable sources,
- ); -- for flow-controlled sourced FALSE can be used.
+ -- Use TRUE for uninterruptable sources,
+ g_flush_not_hold : boolean := true
+ -- for flow-controlled sourced FALSE can be used.
+ );
port (
rst : in std_logic;
clk : in std_logic;
diff --git a/libraries/base/dp/src/vhdl/dp_mon.vhd b/libraries/base/dp/src/vhdl/dp_mon.vhd
index e1d72e765470b99f38d81a638c15b4030bac8aaa..780f5f057d5c3c351b98628f77ef09ff36164c8c 100644
--- a/libraries/base/dp/src/vhdl/dp_mon.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mon.vhd
@@ -43,10 +43,12 @@ entity dp_mon is
src_in : in t_dp_siso;
src_out : out t_dp_sosi;
- clr : in std_logic := '0'; -- clears the word count
+ -- clears the word count
+ clr : in std_logic := '0';
-- All output stats could be in a record (t_dp_mon) in the future
- word_cnt : out std_logic_vector(32 - 1 downto 0) -- Number of words accepted by the connected sink
+ -- Number of words accepted by the connected sink
+ word_cnt : out std_logic_vector(32 - 1 downto 0)
);
end dp_mon;
diff --git a/libraries/base/dp/src/vhdl/dp_mux.vhd b/libraries/base/dp/src/vhdl/dp_mux.vhd
index 9e15141bf0d0e2ed1434f088636abf7a57a8c1ce..0c644eafb9050d48916d1c6556742d3d9f33840c 100644
--- a/libraries/base/dp/src/vhdl/dp_mux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mux.vhd
@@ -90,9 +90,11 @@ entity dp_mux is
g_technology : natural := c_tech_select_default;
-- MUX
g_mode : natural := 0;
- g_nof_input : natural := 2; -- >= 1
+ -- >= 1
+ g_nof_input : natural := 2;
g_append_channel_lo : boolean := true;
- g_sel_ctrl_invert : boolean := false; -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ g_sel_ctrl_invert : boolean := false;
-- Input FIFO
g_use_fifo : boolean := false;
g_bsn_w : natural := 16;
@@ -105,16 +107,21 @@ entity dp_mux is
g_use_in_channel : boolean := false;
g_use_error : boolean := false;
g_use_sync : boolean := false;
- g_fifo_af_margin : natural := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
- g_fifo_af_xon : natural := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
- g_fifo_size : t_natural_arr := array_init(1024, 2); -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill : t_natural_arr := array_init( 0, 2) -- must match g_nof_input, even when g_use_fifo=FALSE
+ -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_margin : natural := 4;
+ -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ g_fifo_af_xon : natural := 0;
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_size : t_natural_arr := array_init(1024, 2);
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill : t_natural_arr := array_init( 0, 2)
);
port (
rst : in std_logic;
clk : in std_logic;
-- Control
- sel_ctrl : in natural range 0 to g_nof_input - 1 := 0; -- used by g_mode = 2, 3, 4
+ -- used by g_mode = 2, 3, 4
+ sel_ctrl : in natural range 0 to g_nof_input - 1 := 0;
-- ST sinks
snk_out_arr : out t_dp_siso_arr(0 to g_nof_input - 1);
snk_in_arr : in t_dp_sosi_arr(0 to g_nof_input - 1);
@@ -147,7 +154,8 @@ architecture rtl of dp_mux is
signal sel_ctrl_evt : std_logic;
signal nxt_sel_ctrl_evt : std_logic;
- signal in_sel : natural range 0 to g_nof_input - 1; -- input port low part of src_out.channel
+ -- input port low part of src_out.channel
+ signal in_sel : natural range 0 to g_nof_input - 1;
signal nxt_in_sel : natural;
signal next_sel : natural;
@@ -157,13 +165,15 @@ architecture rtl of dp_mux is
signal hold_src_in_arr : t_dp_siso_arr(0 to g_nof_input - 1);
signal next_src_out_arr : t_dp_sosi_arr(0 to g_nof_input - 1);
- signal pend_src_out_arr : t_dp_sosi_arr(0 to g_nof_input - 1); -- SOSI control
+ -- SOSI control
+ signal pend_src_out_arr : t_dp_sosi_arr(0 to g_nof_input - 1);
signal in_xon_arr : std_logic_vector(0 to g_nof_input - 1);
signal nxt_in_xon_arr : std_logic_vector(0 to g_nof_input - 1);
signal prev_src_in : t_dp_siso;
- signal src_out_hi : t_dp_sosi; -- snk_in_arr().channel as high part of src_out.channel
+ -- snk_in_arr().channel as high part of src_out.channel
+ signal src_out_hi : t_dp_sosi;
signal nxt_src_out_hi : t_dp_sosi;
signal channel_lo : std_logic_vector(c_sel_w - 1 downto 0);
signal nxt_channel_lo : std_logic_vector(c_sel_w - 1 downto 0);
@@ -252,11 +262,15 @@ begin
rst => rst,
clk => clk,
-- ST sink
- snk_out => OPEN, -- SISO ready
- snk_in => rd_sosi_arr(I), -- SOSI
+ -- SISO ready
+ snk_out => OPEN,
+ -- SOSI
+ snk_in => rd_sosi_arr(I),
-- ST source
- src_in => hold_src_in_arr(I), -- SISO ready
- next_src_out => next_src_out_arr(I), -- SOSI
+ -- SISO ready
+ src_in => hold_src_in_arr(I),
+ -- SOSI
+ next_src_out => next_src_out_arr(I),
pend_src_out => pend_src_out_arr(I),
src_out_reg => src_out_hi
);
@@ -269,18 +283,22 @@ begin
nxt_sel_ctrl_evt <= '1' when nxt_sel_ctrl_reg /= sel_ctrl_reg else '0';
-- The output register stage matches RL = 1 for src_in.ready
- nxt_src_out_hi <= next_src_out_arr(in_sel); -- default output selected next_src_out_arr
- nxt_channel_lo <= TO_UVEC(in_sel, c_sel_w); -- pass on input index via channel low
+ -- default output selected next_src_out_arr
+ nxt_src_out_hi <= next_src_out_arr(in_sel);
+ -- pass on input index via channel low
+ nxt_channel_lo <= TO_UVEC(in_sel, c_sel_w);
------------------------------------------------------------------------------
-- Unframed MM controlled input selection scheme
------------------------------------------------------------------------------
gen_sel_ctrl_direct : if g_mode = 2 generate
- hold_src_in_arr <= (others => src_in); -- pass src_in on to all inputs, only the selected input sosi gets used and the sosi from the other inputs will get lost
+ -- pass src_in on to all inputs, only the selected input sosi gets used and the sosi from the other inputs will get lost
+ hold_src_in_arr <= (others => src_in);
rd_siso_arr <= (others => src_in);
- nxt_in_sel <= sel_ctrl_reg; -- external MM control selects the input
+ -- external MM control selects the input
+ nxt_in_sel <= sel_ctrl_reg;
end generate;
------------------------------------------------------------------------------
@@ -291,7 +309,8 @@ begin
u_dp_frame_busy_arr : entity work.dp_frame_busy_arr
generic map (
g_nof_inputs => g_nof_input,
- g_pipeline => 1 -- register snk_in_busy to ease timing closure
+ -- register snk_in_busy to ease timing closure
+ g_pipeline => 1
)
port map (
rst => rst,
@@ -300,13 +319,16 @@ begin
snk_in_busy_arr => rd_sosi_busy_arr
);
- hold_src_in_arr <= (others => c_dp_siso_rdy); -- effectively bypass the dp_hold_input
+ -- effectively bypass the dp_hold_input
+ hold_src_in_arr <= (others => c_dp_siso_rdy);
p_rd_siso_arr : process(src_in, in_xon_arr)
begin
for I in 0 to g_nof_input - 1 loop
- rd_siso_arr(I).ready <= src_in.ready; -- default pass on src_in ready flow control to all inputs
- rd_siso_arr(I).xon <= in_xon_arr(I); -- use xon to enable one input and stop all other inputs
+ -- default pass on src_in ready flow control to all inputs
+ rd_siso_arr(I).ready <= src_in.ready;
+ -- use xon to enable one input and stop all other inputs
+ rd_siso_arr(I).xon <= in_xon_arr(I);
end loop;
end process;
@@ -314,7 +336,8 @@ begin
begin
nxt_state <= state;
nxt_in_sel <= in_sel;
- nxt_in_xon_arr <= (others => '0'); -- Default stop all inputs
+ -- Default stop all inputs
+ nxt_in_xon_arr <= (others => '0');
case state is
when s_idle =>
@@ -324,7 +347,8 @@ begin
nxt_state <= s_output;
end if;
- when others => -- s_output
+ -- s_output
+ when others =>
-- Enable only the selected input via xon='1'
nxt_in_xon_arr(sel_ctrl_reg) <= '1';
@@ -339,9 +363,11 @@ begin
gen_framed : if g_mode = 0 or g_mode = 1 or g_mode = 3 generate
p_hold_src_in_arr : process(rd_siso_arr, pend_src_out_arr, in_sel, src_in)
begin
- hold_src_in_arr <= rd_siso_arr; -- default ready for hold input when ready for sink input
+ -- default ready for hold input when ready for sink input
+ hold_src_in_arr <= rd_siso_arr;
if pend_src_out_arr(in_sel).eop = '1' then
- hold_src_in_arr(in_sel) <= src_in; -- also ready for hold input when the eop is there
+ -- also ready for hold input when the eop is there
+ hold_src_in_arr(in_sel) <= src_in;
end if;
end process;
@@ -349,7 +375,8 @@ begin
p_state : process(state, in_sel, next_sel, pend_src_out_arr, src_in, prev_src_in, sel_ctrl_reg)
begin
- rd_siso_arr <= (others => c_dp_siso_hold); -- default not ready for input, but xon='1'
+ -- default not ready for input, but xon='1'
+ rd_siso_arr <= (others => c_dp_siso_hold);
nxt_in_sel <= in_sel;
@@ -361,13 +388,16 @@ begin
-- because src_in.ready may be '0' and then next_src_out_arr(in_sel).sop is '0'
if pend_src_out_arr(in_sel).sop = '1' then
if pend_src_out_arr(in_sel).eop = '1' then
- rd_siso_arr <= (others => c_dp_siso_hold); -- the sop and the eop are there, it is a frame with only one data word, stop reading this input
+ -- the sop and the eop are there, it is a frame with only one data word, stop reading this input
+ rd_siso_arr <= (others => c_dp_siso_hold);
if src_in.ready = '1' then
- nxt_in_sel <= next_sel; -- the pend_src_out_arr(in_sel).eop will be output, so continue to next input.
+ -- the pend_src_out_arr(in_sel).eop will be output, so continue to next input.
+ nxt_in_sel <= next_sel;
rd_siso_arr(next_sel) <= src_in;
end if;
else
- rd_siso_arr(in_sel) <= src_in; -- the sop is there, so start outputting the frame from this input
+ -- the sop is there, so start outputting the frame from this input
+ rd_siso_arr(in_sel) <= src_in;
nxt_state <= s_output;
end if;
else
@@ -375,22 +405,30 @@ begin
when 0 | 3 =>
-- Framed round-robin with fair chance per input
if prev_src_in.ready = '0' then
- rd_siso_arr(in_sel) <= src_in; -- no sop, remain at current input to give it a chance
+ -- no sop, remain at current input to give it a chance
+ rd_siso_arr(in_sel) <= src_in;
else
- nxt_in_sel <= next_sel; -- no sop, select next input, because the current input has had a chance
+ -- no sop, select next input, because the current input has had a chance
+ nxt_in_sel <= next_sel;
rd_siso_arr(next_sel) <= src_in;
end if;
- when others => -- = 1
+ -- = 1
+ when others =>
-- Framed round-robin in forced order from each input
- rd_siso_arr(in_sel) <= src_in; -- no sop, remain at current input to wait for a frame
+ -- no sop, remain at current input to wait for a frame
+ rd_siso_arr(in_sel) <= src_in;
end case;
end if;
- when others => -- s_output
- rd_siso_arr(in_sel) <= src_in; -- output the rest of the selected input frame
+ -- s_output
+ when others =>
+ -- output the rest of the selected input frame
+ rd_siso_arr(in_sel) <= src_in;
if pend_src_out_arr(in_sel).eop = '1' then
- rd_siso_arr <= (others => c_dp_siso_hold); -- the eop is there, stop reading this input
+ -- the eop is there, stop reading this input
+ rd_siso_arr <= (others => c_dp_siso_hold);
if src_in.ready = '1' then
- nxt_in_sel <= next_sel; -- the pend_src_out_arr(in_sel).eop will be output, so continue to next input.
+ -- the pend_src_out_arr(in_sel).eop will be output, so continue to next input.
+ nxt_in_sel <= next_sel;
rd_siso_arr(next_sel) <= src_in;
nxt_state <= s_idle;
end if;
@@ -403,9 +441,11 @@ begin
if g_mode = 3 then
-- Framed MM control select input via XON
- rd_siso_arr(I).xon <= '0'; -- force xon='0' for not selected inputs
+ -- force xon='0' for not selected inputs
+ rd_siso_arr(I).xon <= '0';
if sel_ctrl_reg = I then
- rd_siso_arr(I).xon <= src_in.xon; -- pass on frame level flow control for selected input
+ -- pass on frame level flow control for selected input
+ rd_siso_arr(I).xon <= src_in.xon;
end if;
end if;
end loop;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
index 374201d300f1a3efa12bd2673c87a690242d40b7..1f2c2c42aef245825d70024bf4948c81c9fc9be9 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
@@ -51,7 +51,8 @@ entity dp_offload_rx is
generic (
g_nof_streams : natural;
g_data_w : natural;
- g_symbol_w : natural := 0; -- default 0 yields g_symbol_w = g_data_w
+ -- default 0 yields g_symbol_w = g_data_w
+ g_symbol_w : natural := 0;
g_hdr_field_arr : t_common_field_arr;
g_remove_crc : boolean := false;
g_crc_nof_words : natural := 0
@@ -72,8 +73,10 @@ entity dp_offload_rx is
src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0);
src_in_arr : in t_dp_siso_arr(g_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
- hdr_fields_out_arr : out t_slv_1024_arr(g_nof_streams - 1 downto 0); -- Valid at src_out_arr(i).sop, use for sosi.sync
- hdr_fields_raw_arr : out t_slv_1024_arr(g_nof_streams - 1 downto 0) -- Valid at src_out_arr(i).sop and beyond, use for sosi.bsn
+ -- Valid at src_out_arr(i).sop, use for sosi.sync
+ hdr_fields_out_arr : out t_slv_1024_arr(g_nof_streams - 1 downto 0);
+ -- Valid at src_out_arr(i).sop and beyond, use for sosi.bsn
+ hdr_fields_raw_arr : out t_slv_1024_arr(g_nof_streams - 1 downto 0)
);
end dp_offload_rx;
@@ -82,7 +85,8 @@ architecture str of dp_offload_rx is
constant c_nof_symbols_per_data : natural := g_data_w / c_symbol_w;
constant c_nof_header_symbols : natural := field_slv_len(g_hdr_field_arr) / c_symbol_w;
- constant c_field_sel : std_logic_vector(g_hdr_field_arr'range) := (others => '0'); -- Not used in sink mode but requires set range
+ -- Not used in sink mode but requires set range
+ constant c_field_sel : std_logic_vector(g_hdr_field_arr'range) := (others => '0');
signal dp_split_src_out_2arr : t_dp_sosi_2arr_2(g_nof_streams - 1 downto 0);
signal dp_split_src_in_2arr : t_dp_siso_2arr_2(g_nof_streams - 1 downto 0);
@@ -129,7 +133,8 @@ begin
-- 1 range and dp_split_src_in_2arr()() uses 1 DOWNTO 0 range, so:
-- . dp_split_src_in_2arr()(1) is the header part, and
-- . dp_split_src_in_2arr()(0) is the tail part.
- dp_split_src_in_2arr(i)(1) <= c_dp_siso_rdy; -- flow control for rx header to MM is always ready
+ -- flow control for rx header to MM is always ready
+ dp_split_src_in_2arr(i)(1) <= c_dp_siso_rdy;
end generate;
---------------------------------------------------------------------------------------
@@ -141,11 +146,14 @@ begin
generic map (
g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RO"),
g_field_sel => c_field_sel,
- g_snk_data_w => c_dp_field_blk_snk_data_w, -- g_data_w,
- g_src_data_w => c_dp_field_blk_src_data_w, -- field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"))
+ -- g_data_w,
+ g_snk_data_w => c_dp_field_blk_snk_data_w,
+ -- field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"))
+ g_src_data_w => c_dp_field_blk_src_data_w,
g_in_symbol_w => c_symbol_w,
g_out_symbol_w => c_symbol_w,
- g_mode => 2 -- sink mode
+ -- sink mode
+ g_mode => 2
)
port map (
dp_rst => dp_rst,
@@ -184,7 +192,8 @@ begin
st_clk => dp_clk,
snk_out => dp_split_src_in_2arr(i)(0),
- snk_in => dp_split_src_out_2arr(i)(0), -- tail part
+ -- tail part
+ snk_in => dp_split_src_out_2arr(i)(0),
src_in => dp_tail_remove_src_in_arr(i),
src_out => dp_tail_remove_src_out_arr(i)
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
index d091171e52e44be574bade197cb2ce51d162e2b2..aaa38a54eb4cb74cd7c4103d17931378155f6638 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
@@ -204,14 +204,20 @@ begin
)
port map(
-- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
- st_rst => dp_rst, -- reset synchronous with st_clk
- st_clk => dp_clk, -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst => mm_rst,
+ -- memory-mapped bus clock
+ mm_clk => mm_clk,
+ -- reset synchronous with st_clk
+ st_rst => dp_rst,
+ -- other clock domain clock
+ st_clk => dp_clk,
-- Memory Mapped Slave in mm_clk domain
- sla_in => common_mosi_arr(1), -- IN t_mem_mosi; -- actual ranges defined by g_reg
- sla_out => common_miso_arr(1), -- OUT t_mem_miso; -- actual ranges defined by g_reg
+ -- IN t_mem_mosi; -- actual ranges defined by g_reg
+ sla_in => common_mosi_arr(1),
+ -- OUT t_mem_miso; -- actual ranges defined by g_reg
+ sla_out => common_miso_arr(1),
-- MM registers in st_clk domain
reg_wr_arr => OPEN,
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
index e88d96a678f6c1bb1baa800c0e18d7eba17b0c01..a55907802f1bf0248bfbd6df846e3ae37724f0b0 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
@@ -54,11 +54,14 @@ entity dp_offload_tx is
g_technology : natural := c_tech_select_default;
g_nof_streams : natural;
g_data_w : natural;
- g_use_complex : boolean; -- TRUE uses re(0..g_data_w/2 -1) & im(0..g_data_w/2-1) as input instead of data(0..g_data_w-1).
+ -- TRUE uses re(0..g_data_w/2 -1) & im(0..g_data_w/2-1) as input instead of data(0..g_data_w-1).
+ g_use_complex : boolean;
g_nof_words_per_block : natural;
g_nof_blocks_per_packet : natural;
- g_hdr_field_arr : t_common_field_arr; -- User defined header fields
- g_hdr_field_sel : std_logic_vector; -- For each header field, select the source: 0=data path, 1=MM controlled
+ -- User defined header fields
+ g_hdr_field_arr : t_common_field_arr;
+ -- For each header field, select the source: 0=data path, 1=MM controlled
+ g_hdr_field_sel : std_logic_vector;
g_use_post_split_fifo : boolean := true;
g_pkt_merge_align_at_sync : boolean := false
);
@@ -78,7 +81,8 @@ entity dp_offload_tx is
src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0);
src_in_arr : in t_dp_siso_arr(g_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
- hdr_fields_in_arr : in t_slv_1024_arr(g_nof_streams - 1 downto 0) -- hdr_fields_in_arr(i) is considered valid @ snk_in_arr(i).sop
+ -- hdr_fields_in_arr(i) is considered valid @ snk_in_arr(i).sop
+ hdr_fields_in_arr : in t_slv_1024_arr(g_nof_streams - 1 downto 0)
);
end dp_offload_tx;
@@ -97,7 +101,8 @@ architecture str of dp_offload_tx is
constant c_dp_fifo_size : natural := c_dp_fifo_fill + c_nof_header_words + 10;
signal dp_split_snk_in_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal dp_split_hdr_fields_snk_in_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst); -- init to avoid 'X' in unused record fields
+ -- init to avoid 'X' in unused record fields
+ signal dp_split_hdr_fields_snk_in_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
signal dp_split_snk_out_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
@@ -154,7 +159,8 @@ begin
---------------------------------------------------------------------------------------
gen_dp_split : for i in 0 to g_nof_streams - 1 generate
snk_out_arr(i).ready <= dp_split_snk_out_arr(i).ready;
- snk_out_arr(i).xon <= src_in_arr(i).xon; -- Pass on XON from source side
+ -- Pass on XON from source side
+ snk_out_arr(i).xon <= src_in_arr(i).xon;
u_dp_split : entity work.dp_split
generic map (
@@ -173,7 +179,8 @@ begin
src_out_arr => dp_split_src_out_2arr(i)
);
- dp_split_src_in_2arr(i)(0) <= c_dp_siso_rdy; -- Always ready to throw away the tail
+ -- Always ready to throw away the tail
+ dp_split_src_in_2arr(i)(0) <= c_dp_siso_rdy;
end generate;
-- Introduce the same delay (as dp_plit) on the corresponding header fields
@@ -187,7 +194,8 @@ begin
clk => dp_clk,
snk_in_arr => dp_split_hdr_fields_snk_in_arr,
- snk_out_arr => OPEN, -- Flow control is already taken care of by dp_split
+ -- Flow control is already taken care of by dp_split
+ snk_out_arr => OPEN,
src_out_arr => dp_split_hdr_fields_src_out_arr,
src_in_arr => dp_split_hdr_fields_src_in_arr
@@ -277,7 +285,8 @@ begin
);
dp_fifo_fill_src_in_arr(i).ready <= dp_concat_snk_out_2arr(i)(0).ready;
- dp_fifo_fill_src_in_arr(i).xon <= '1'; -- Prevents flushing of frames
+ -- Prevents flushing of frames
+ dp_fifo_fill_src_in_arr(i).xon <= '1';
dp_concat_snk_in_2arr(i)(0) <= dp_fifo_fill_src_out_arr(i);
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
index b3101b542d49ef12cdf05b2c8b84defdf25134d4..59373c4f1ac71894fe9a2423c61bd0a3fb6d99ff 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
@@ -30,13 +30,20 @@ entity dp_offload_tx_legacy is
generic (
g_nof_streams : natural := 1;
g_data_w : natural;
- g_block_size : natural := 256; -- The number of words per input block
- g_block_nof_sel_words : natural := 20; -- The maximum number of words we select from each input block.
- g_nof_words_per_pkt : natural := 360; -- The maximum number of words per output Tx packet
- g_hdr_nof_words : natural; -- The number of words (of width g_data_w) to be added as header for each TX packet, e.g. c_eth_total_header_nof_words
- g_use_complex : boolean := false; -- TRUE uses re(0..g_data_w/2 -1) & im(0..g_data_w/2-1) as input instead of data(0..g_data_w-1).
- g_use_input_fifo : boolean := false; -- TRUE instantiates a shallow input FIFO, e.g. in case source has no flow control
- g_use_output_fifo : boolean := true; -- TRUE to instantiate an output FIFO that buffers an entire packet
+ -- The number of words per input block
+ g_block_size : natural := 256;
+ -- The maximum number of words we select from each input block.
+ g_block_nof_sel_words : natural := 20;
+ -- The maximum number of words per output Tx packet
+ g_nof_words_per_pkt : natural := 360;
+ -- The number of words (of width g_data_w) to be added as header for each TX packet, e.g. c_eth_total_header_nof_words
+ g_hdr_nof_words : natural;
+ -- TRUE uses re(0..g_data_w/2 -1) & im(0..g_data_w/2-1) as input instead of data(0..g_data_w-1).
+ g_use_complex : boolean := false;
+ -- TRUE instantiates a shallow input FIFO, e.g. in case source has no flow control
+ g_use_input_fifo : boolean := false;
+ -- TRUE to instantiate an output FIFO that buffers an entire packet
+ g_use_output_fifo : boolean := true;
g_input_fifo_bsn_w : natural := c_dp_stream_bsn_w;
g_input_fifo_empty_w : natural := c_dp_stream_empty_w;
g_input_fifo_channel_w : natural := c_dp_stream_channel_w;
@@ -76,7 +83,8 @@ architecture str of dp_offload_tx_legacy is
constant c_fifo_margin : natural := 10;
constant c_dp_pkt_overhead_nof_words : natural := 4 + 1;
- constant c_hdr_insert_reg_addr_w : natural := 1; -- Only 1 register used. A width of 1 still yields 2 addresses/instance though.
+ -- Only 1 register used. A width of 1 still yields 2 addresses/instance though.
+ constant c_hdr_insert_reg_addr_w : natural := 1;
constant c_hdr_insert_ram_addr_w : natural := ceil_log2( g_hdr_nof_words * (g_data_w / c_word_w) );
-- In case of an uninterruptable stream, the dp_hdr_insert's ready deassertion (during header insertion)
@@ -166,7 +174,8 @@ begin
g_use_error => g_input_fifo_use_error,
g_use_sync => g_input_fifo_use_sync,
g_use_ctrl => true,
- g_fifo_size => 10 -- Use 10 as there's a FIFO margin
+ -- Use 10 as there's a FIFO margin
+ g_fifo_size => 10
)
port map (
rst => st_rst,
@@ -261,7 +270,8 @@ begin
u_dp_packet_merge : entity work.mms_dp_packet_merge
generic map (
g_nof_streams => g_nof_streams,
- g_nof_pkt => g_nof_words_per_pkt -- Support merging 360*1 word
+ -- Support merging 360*1 word
+ g_nof_pkt => g_nof_words_per_pkt
)
port map (
mm_rst => mm_rst,
@@ -336,12 +346,14 @@ begin
g_empty_w => 0,
g_channel_w => 0,
g_error_w => 0,
- g_use_bsn => false, -- Don't forward these as all have been encoded by dp_packet_enc
+ -- Don't forward these as all have been encoded by dp_packet_enc
+ g_use_bsn => false,
g_use_empty => false,
g_use_channel => false,
g_use_error => false,
g_use_sync => false,
- g_fifo_fill => c_output_fifo_fill, -- Release packet only when available
+ -- Release packet only when available
+ g_fifo_fill => c_output_fifo_fill,
g_fifo_size => c_output_fifo_size,
g_fifo_rl => 1
)
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
index e95ac25810282d2f48184619c5af08280dfee4f5..18e8981a7084a40c8ac5f8138643b5e7a21760fe 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
@@ -41,7 +41,8 @@ entity dp_offload_tx_len_calc is
generic (
g_technology : natural := c_tech_select_default;
g_hdr_field_arr : t_common_field_arr;
- g_data_w : natural; -- Must be a power of 2
+ -- Must be a power of 2
+ g_data_w : natural;
g_word_align_len : natural := 2
);
port (
@@ -65,7 +66,8 @@ architecture str of dp_offload_tx_len_calc is
constant c_user_hdr_len : natural := c_total_hdr_len - g_word_align_len - c_eth_header_len - c_ip_header_len - c_udp_header_len;
constant c_product_w : natural := nof_words_per_block'length + nof_blocks_per_packet'length;
- constant c_nof_bits_to_shift : natural := true_log2(g_data_w / c_byte_w); -- number of bits to shift left to yield nof_data_bytes)
+ -- number of bits to shift left to yield nof_data_bytes)
+ constant c_nof_bits_to_shift : natural := true_log2(g_data_w / c_byte_w);
constant c_shift_left_int : integer := -1 * c_nof_bits_to_shift;
constant c_adder_in_w : natural := 16;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
index 9382254dc534548c4d079d4396cc91143c303f55..fbd7578149045e62cee7a373d2dcd676e358ba9e 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
@@ -53,8 +53,10 @@ entity dp_offload_tx_v3 is
g_nof_streams : natural;
g_data_w : natural;
g_symbol_w : natural;
- g_hdr_field_arr : t_common_field_arr; -- User defined header fields
- g_hdr_field_sel : std_logic_vector; -- For each header field, select the source: 0=data path, 1=MM controlled
+ -- User defined header fields
+ g_hdr_field_arr : t_common_field_arr;
+ -- For each header field, select the source: 0=data path, 1=MM controlled
+ g_hdr_field_sel : std_logic_vector;
g_pipeline_ready : boolean := false
);
port (
@@ -73,7 +75,8 @@ entity dp_offload_tx_v3 is
src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0);
src_in_arr : in t_dp_siso_arr(g_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
- hdr_fields_in_arr : in t_slv_1024_arr(g_nof_streams - 1 downto 0); -- hdr_fields_in_arr(i) is considered valid @ snk_in_arr(i).sop
+ -- hdr_fields_in_arr(i) is considered valid @ snk_in_arr(i).sop
+ hdr_fields_in_arr : in t_slv_1024_arr(g_nof_streams - 1 downto 0);
hdr_fields_out_arr : out t_slv_1024_arr(g_nof_streams - 1 downto 0)
);
end dp_offload_tx_v3;
@@ -98,7 +101,8 @@ architecture str of dp_offload_tx_v3 is
signal reg_hdr_dat_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
signal mm_fields_slv_out_arr : t_slv_1024_arr(g_nof_streams - 1 downto 0);
- signal field_override_arr : std_logic_vector(g_hdr_field_arr'range) := g_hdr_field_sel; -- 1 override bit per field
+ -- 1 override bit per field
+ signal field_override_arr : std_logic_vector(g_hdr_field_arr'range) := g_hdr_field_sel;
begin
assert c_dp_field_blk_snk_data_w <= c_dp_stream_data_w report "Number of header bits must fit in t_dp_sosi data field." severity FAILURE;
---------------------------------------------------------------------------------------
@@ -117,8 +121,10 @@ begin
-- dp_field_blk_snk_in_arr as a single word header block.
dp_field_blk_snk_in_arr(i).data <= RESIZE_DP_DATA(hdr_fields_in_arr(i)(field_slv_len(g_hdr_field_arr) - 1 downto 0));
dp_field_blk_snk_in_arr(i).valid <= snk_in_arr(i).sop;
- dp_field_blk_snk_in_arr(i).sop <= snk_in_arr(i).sop; -- necessary for single word header block
- dp_field_blk_snk_in_arr(i).eop <= snk_in_arr(i).sop; -- necessary for single word header block
+ -- necessary for single word header block
+ dp_field_blk_snk_in_arr(i).sop <= snk_in_arr(i).sop;
+ -- necessary for single word header block
+ dp_field_blk_snk_in_arr(i).eop <= snk_in_arr(i).sop;
end loop;
end process;
@@ -159,7 +165,8 @@ begin
mm_rst => mm_rst,
mm_mosi => reg_hdr_dat_mosi_arr(i),
- mm_miso => OPEN, -- Not used
+ -- Not used
+ mm_miso => OPEN,
slv_clk => dp_clk,
slv_rst => dp_rst,
@@ -177,7 +184,8 @@ begin
g_in_symbol_w => g_symbol_w,
g_out_symbol_w => g_symbol_w,
g_pipeline_ready => g_pipeline_ready,
- g_mode => 1 -- source mode
+ -- source mode
+ g_mode => 1
)
port map (
dp_clk => dp_clk,
diff --git a/libraries/base/dp/src/vhdl/dp_packet_dec.vhd b/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
index 6839ff8a6e9c3ed0002b16aa24b6797b05d973a1..23a5f90313d9882ce0135aee83d6f79bc394a895 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
@@ -79,9 +79,12 @@ entity dp_packet_dec is
generic (
g_data_w : natural := 32;
g_channel_lo : natural := 0;
- g_phy_err_bi : natural := 0; -- bit index in src_out.err for where to put the PHY snk_in.err bit when g_use_phy_err=TRUE, else not used
- g_use_phy_err : boolean := false; -- when FALSE pass on the DP packet err field, else merge the PHY snk_in.err field with the DP packet err field to get the output src_out.err.
- g_use_this_siso : boolean := true -- default use TRUE for best throughput performance
+ -- bit index in src_out.err for where to put the PHY snk_in.err bit when g_use_phy_err=TRUE, else not used
+ g_phy_err_bi : natural := 0;
+ -- when FALSE pass on the DP packet err field, else merge the PHY snk_in.err field with the DP packet err field to get the output src_out.err.
+ g_use_phy_err : boolean := false;
+ -- default use TRUE for best throughput performance
+ g_use_this_siso : boolean := true
);
port (
rst : in std_logic;
@@ -96,12 +99,14 @@ entity dp_packet_dec is
end dp_packet_dec;
architecture rtl of dp_packet_dec is
- constant c_output_reg : boolean := true; -- register dp_shiftreg output to ease timing closure
+ -- register dp_shiftreg output to ease timing closure
+ constant c_output_reg : boolean := true;
constant c_channel_len : natural := ceil_div(c_dp_packet_channel_w, g_data_w);
constant c_bsn_len : natural := ceil_div(c_dp_packet_bsn_w, g_data_w);
constant c_error_len : natural := ceil_div(c_dp_packet_error_w, g_data_w);
- constant c_len_max : natural := c_bsn_len; -- the BSN is the widest field
+ -- the BSN is the widest field
+ constant c_len_max : natural := c_bsn_len;
constant c_channel_vec_w : natural := c_channel_len * g_data_w;
constant c_bsn_vec_w : natural := c_bsn_len * g_data_w;
@@ -207,7 +212,8 @@ begin
nxt_bsn <= bsn;
nxt_cnt <= cnt;
- nxt_blk_sosi <= blk_sosi; -- blk_sosi outputs payload data and err field, the err field gets stripped later on
+ -- blk_sosi outputs payload data and err field, the err field gets stripped later on
+ nxt_blk_sosi <= blk_sosi;
nxt_blk_sosi.sync <= '0';
nxt_blk_sosi.valid <= '0';
nxt_blk_sosi.sop <= '0';
@@ -245,31 +251,41 @@ begin
if next_src_buf.valid = '1' then
nxt_bsn((cnt + 1) * g_data_w - 1 downto cnt * g_data_w) <= v_bsn_data;
if cnt = 0 then
- this_siso <= src_in; -- maintain active hold_src_in and now use the src_in for this_siso
- nxt_cnt <= c_channel_len - 1; -- prepare cnt for next DP packet, the error field c_error_len for this DP packet gets handled by dp_shiftreg
+ -- maintain active hold_src_in and now use the src_in for this_siso
+ this_siso <= src_in;
+ -- prepare cnt for next DP packet, the error field c_error_len for this DP packet gets handled by dp_shiftreg
+ nxt_cnt <= c_channel_len - 1;
nxt_state <= s_data_sop;
else
nxt_cnt <= cnt - 1;
end if;
end if;
when s_data_sop =>
- if next_src_buf.valid = '1' then -- first payload data
+ -- first payload data
+ if next_src_buf.valid = '1' then
nxt_blk_sosi.data <= next_src_buf.data;
nxt_blk_sosi.valid <= '1';
nxt_blk_sosi.sop <= '1';
nxt_blk_sosi.channel <= RESIZE_DP_CHANNEL(channel & v_in_channel);
- nxt_blk_sosi.sync <= bsn(bsn'high); -- support SOSI sync via MSbit of BSN field (sync active only at sop),
- nxt_blk_sosi.bsn <= RESIZE_DP_BSN(bsn(bsn'high - 1 downto 0)); -- the rest of the BSN field transports the SOSI BSN
- nxt_blk_sosi.err <= TO_DP_ERROR(0); -- initialy assume block has no error
- nxt_state <= s_data_eop; -- no need to check for eop, because DP packet has at least 1 data word and an error field, so eop can not occur yet
+ -- support SOSI sync via MSbit of BSN field (sync active only at sop),
+ nxt_blk_sosi.sync <= bsn(bsn'high);
+ -- the rest of the BSN field transports the SOSI BSN
+ nxt_blk_sosi.bsn <= RESIZE_DP_BSN(bsn(bsn'high - 1 downto 0));
+ -- initialy assume block has no error
+ nxt_blk_sosi.err <= TO_DP_ERROR(0);
+ -- no need to check for eop, because DP packet has at least 1 data word and an error field, so eop can not occur yet
+ nxt_state <= s_data_eop;
end if;
- when others => -- s_data_eop
- if next_src_buf.valid = '1' then -- rest of payload data and the error field
+ -- s_data_eop
+ when others =>
+ -- rest of payload data and the error field
+ if next_src_buf.valid = '1' then
nxt_blk_sosi.data <= next_src_buf.data;
nxt_blk_sosi.valid <= '1';
if next_src_buf.eop = '1' then
nxt_blk_sosi.eop <= '1';
- nxt_blk_sosi.err <= next_src_buf.err; -- the sosi error field contains the one bit PHY error status
+ -- the sosi error field contains the one bit PHY error status
+ nxt_blk_sosi.err <= next_src_buf.err;
nxt_state <= s_sop;
end if;
end if;
@@ -325,9 +341,11 @@ begin
new_src_out_inputs(0).eop <= '0';
-- move the eop and move the error data word to the SOSI error field at last payload data
new_src_out_inputs(c_shiftreg_len - 1).eop <= '1';
- new_src_out_inputs(c_shiftreg_len - 1).err <= RESIZE_DP_ERROR(src_err); -- output transported DP packet err field
+ -- output transported DP packet err field
+ new_src_out_inputs(c_shiftreg_len - 1).err <= RESIZE_DP_ERROR(src_err);
if g_use_phy_err = true then
- new_src_out_inputs(c_shiftreg_len - 1).err(g_phy_err_bi) <= cur_src_out_inputs(0).err(0); -- merge one bit PHY error status at bit index g_phy_err_bi
+ -- merge one bit PHY error status at bit index g_phy_err_bi
+ new_src_out_inputs(c_shiftreg_len - 1).err(g_phy_err_bi) <= cur_src_out_inputs(0).err(0);
end if;
end if;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd b/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
index 2fe927abf47a45fb41f062c448edc272edc57107..712377c3972e64b4db812bb9d3117f96d2e5a680 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
@@ -80,15 +80,18 @@ begin
nxt_channel_lo_hold <= channel_lo_hold;
if g_channel_lo > 0 then
- src_out.channel(g_channel_lo - 1 downto 0) <= channel_lo_hold; -- default combinatorially assign the held channel_lo bits to the sosi.channel field after the sop
+ -- default combinatorially assign the held channel_lo bits to the sosi.channel field after the sop
+ src_out.channel(g_channel_lo - 1 downto 0) <= channel_lo_hold;
if snk_in.sop = '1' then
-- clear the channel_lo bits in the MSWord of the CHAN field
src_out.data(g_data_w - 2 downto g_data_w - 1 - g_channel_lo) <= (others => '0');
-- extract the channel_lo bits from the MSWord of the CHAN field
v_channel_lo := snk_in.data(g_data_w - 2 downto g_data_w - 1 - g_channel_lo);
- src_out.channel(g_channel_lo - 1 downto 0) <= v_channel_lo; -- combinatorially assign the channel_lo bits to the sosi.channel field at the sop
- nxt_channel_lo_hold <= v_channel_lo; -- register the channel_lo bits so they can be assigned to the rest of the frame as well
+ -- combinatorially assign the channel_lo bits to the sosi.channel field at the sop
+ src_out.channel(g_channel_lo - 1 downto 0) <= v_channel_lo;
+ -- register the channel_lo bits so they can be assigned to the rest of the frame as well
+ nxt_channel_lo_hold <= v_channel_lo;
end if;
end if;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_detect.vhd b/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
index 08011772520ca371f8a98548e918e3421cd0749a..046f04e3275166c439ae911bbb6d5345ab1dcdf7 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
@@ -48,7 +48,8 @@ entity dp_packet_detect is
-- The SOSI/SISO buses of the stream we're probing
sosi : in t_dp_sosi;
- siso : in t_dp_siso := c_dp_siso_rst; -- Connect this when RL=0
+ -- Connect this when RL=0
+ siso : in t_dp_siso := c_dp_siso_rst;
pkt_det : out std_logic
);
diff --git a/libraries/base/dp/src/vhdl/dp_packet_enc.vhd b/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
index 489bdc80ecd39d220969de42577ec54e6c80d6ab..6051960b2916e7198f7ea9e05ac58dca44ac7043 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
@@ -75,7 +75,8 @@ entity dp_packet_enc is
generic (
g_data_w : natural := 32;
g_channel_lo : natural := 0;
- g_blk_sync : boolean := false -- when false force src_out.sync to '0' after the sop (= DP style), else keep src_out.sync value after this sop so until the next sop (= LOFAR style)
+ -- when false force src_out.sync to '0' after the sop (= DP style), else keep src_out.sync value after this sop so until the next sop (= LOFAR style)
+ g_blk_sync : boolean := false
);
port (
rst : in std_logic;
@@ -93,7 +94,8 @@ architecture rtl of dp_packet_enc is
constant c_channel_len : natural := ceil_div(c_dp_packet_channel_w, g_data_w);
constant c_bsn_len : natural := ceil_div(c_dp_packet_bsn_w, g_data_w);
constant c_error_len : natural := ceil_div(c_dp_packet_error_w, g_data_w);
- constant c_len_max : natural := c_bsn_len; -- the BSN is the widest field
+ -- the BSN is the widest field
+ constant c_len_max : natural := c_bsn_len;
constant c_channel_vec_w : natural := c_channel_len * g_data_w;
constant c_bsn_vec_w : natural := c_bsn_len * g_data_w;
@@ -167,13 +169,15 @@ begin
-- State machine
p_state : process(state, cnt, src_in, pend_src_buf, i_src_out, in_err)
variable v_in_channel : std_logic_vector(c_channel_vec_w - 1 downto 0);
- variable v_in_bsn : std_logic_vector(c_bsn_vec_w - 1 downto 0); -- sync & bsn[46:0]
+ -- sync & bsn[46:0]
+ variable v_in_bsn : std_logic_vector(c_bsn_vec_w - 1 downto 0);
variable v_in_err : std_logic_vector(c_error_vec_w - 1 downto 0);
variable v_out_channel : std_logic_vector(g_channel_lo - 1 downto 0);
begin
v_in_channel := RESIZE_UVEC(pend_src_buf.channel(c_dp_stream_channel_w - 1 downto g_channel_lo), v_in_channel'length);
v_in_bsn := RESIZE_UVEC(pend_src_buf.bsn, v_in_bsn'length);
- v_in_bsn(v_in_bsn'high) := pend_src_buf.sync; -- Transport SOSI sync via MSbit of BSN field
+ -- Transport SOSI sync via MSbit of BSN field
+ v_in_bsn(v_in_bsn'high) := pend_src_buf.sync;
v_in_err := RESIZE_UVEC(pend_src_buf.err, v_in_err'length);
v_out_channel := pend_src_buf.channel(g_channel_lo - 1 downto 0);
@@ -183,8 +187,10 @@ begin
nxt_src_out <= i_src_out;
if g_blk_sync = false then
- nxt_src_out.sync <= '0'; -- when true use dp style sync that is only active at sop,
- end if; -- else use LOFAR style block sync that keeps the sync until the next sop
+ -- when true use dp style sync that is only active at sop,
+ nxt_src_out.sync <= '0';
+ -- else use LOFAR style block sync that keeps the sync until the next sop
+ end if;
nxt_src_out.valid <= '0';
nxt_src_out.sop <= '0';
nxt_src_out.eop <= '0';
@@ -195,10 +201,12 @@ begin
case state is
when s_channel =>
- i_snk_out.ready <= not pend_src_buf.sop; -- flush until sop, then stop further input and hold this sosi
+ -- flush until sop, then stop further input and hold this sosi
+ i_snk_out.ready <= not pend_src_buf.sop;
hold_src_in.ready <= '0';
if src_in.ready = '1' then
- if pend_src_buf.sop = '1' then -- output SOSI channel field
+ -- output SOSI channel field
+ if pend_src_buf.sop = '1' then
nxt_src_out.data <= RESIZE_DP_DATA(v_in_channel((cnt + 1) * g_data_w - 1 downto cnt * g_data_w));
nxt_src_out.valid <= '1';
if cnt = c_channel_len - 1 then
@@ -217,7 +225,8 @@ begin
when s_bsn =>
i_snk_out.ready <= '0';
hold_src_in.ready <= '0';
- if src_in.ready = '1' then -- output SOSI BSN field
+ -- output SOSI BSN field
+ if src_in.ready = '1' then
nxt_src_out.data <= RESIZE_DP_DATA(v_in_bsn((cnt + 1) * g_data_w - 1 downto cnt * g_data_w));
nxt_src_out.valid <= '1';
if cnt = 0 then
@@ -236,10 +245,13 @@ begin
nxt_state <= s_error;
end if;
end if;
- when others => -- s_error
- i_snk_out.ready <= not pend_src_buf.sop; -- flush until next sop
+ -- s_error
+ when others =>
+ -- flush until next sop
+ i_snk_out.ready <= not pend_src_buf.sop;
hold_src_in.ready <= '0';
- if src_in.ready = '1' then -- output SOSI error field
+ -- output SOSI error field
+ if src_in.ready = '1' then
nxt_src_out.data <= RESIZE_DP_DATA(in_err((cnt + 1) * g_data_w - 1 downto cnt * g_data_w));
nxt_src_out.valid <= '1';
if cnt = 0 then
diff --git a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
index 78269fecf91b5630c8e666924ea27304019fed4c..2ec22e670135b49267c874c11eda9e9905e9c3d1 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
@@ -188,14 +188,16 @@ entity dp_packet_merge is
g_nof_pkt : natural;
g_align_at_sync : boolean := false;
g_bsn_increment : natural := 0;
- g_bsn_err_bi : natural := 0 -- bit index (bi) in scr_out.err for snk_in.bsn error
+ -- bit index (bi) in scr_out.err for snk_in.bsn error
+ g_bsn_err_bi : natural := 0
);
port (
rst : in std_logic;
clk : in std_logic;
nof_pkt : in std_logic_vector(ceil_log2(g_nof_pkt + 1) - 1 downto 0) := TO_UVEC(g_nof_pkt, ceil_log2(g_nof_pkt + 1));
- nof_pkt_out : out std_logic_vector(ceil_log2(g_nof_pkt + 1) - 1 downto 0); -- Valid at src_out.sop
+ -- Valid at src_out.sop
+ nof_pkt_out : out std_logic_vector(ceil_log2(g_nof_pkt + 1) - 1 downto 0);
snk_out : out t_dp_siso;
snk_in : in t_dp_sosi;
@@ -217,7 +219,8 @@ architecture rtl of dp_packet_merge is
src_out : t_dp_sosi;
end record;
- constant c_use_dp_latency_adapter : boolean := true; -- when TRUE adjust RL from 2 to 1, else use dp_hold_input to keep RL at 1.
+ -- when TRUE adjust RL from 2 to 1, else use dp_hold_input to keep RL at 1.
+ constant c_use_dp_latency_adapter : boolean := true;
signal r, nxt_r : t_reg;
@@ -310,13 +313,15 @@ begin
if g_align_at_sync then
if snk_in.sync = '1' then
if r.pkt_cnt > 0 then
- v.align_cnt := r.nof_pkt - r.pkt_cnt; -- = 0 when sync occurs at integer number of merged blocks, > 0 when (re)align to sync is needed
+ -- = 0 when sync occurs at integer number of merged blocks, > 0 when (re)align to sync is needed
+ v.align_cnt := r.nof_pkt - r.pkt_cnt;
end if;
end if;
end if;
if v.busy = '0' and v.src_out.eop = '1' then
- v.nof_pkt := TO_UINT(nof_pkt) - r.align_cnt; -- use shorter next merge to (re)align to sync (when g_align_at_sync=false then r.align_cnt=0)
+ -- use shorter next merge to (re)align to sync (when g_align_at_sync=false then r.align_cnt=0)
+ v.nof_pkt := TO_UINT(nof_pkt) - r.align_cnt;
v.align_cnt := 0;
end if;
@@ -333,20 +338,29 @@ begin
if snk_in.sop = '1' then
if r.pkt_cnt = 0 then
v.src_out.sop := '1';
- v.src_out.sync := r.sync; -- use sync from previous merged packet if it occurred on pkt_cnt /= 0.
- v.src_out.bsn := snk_in.bsn; -- use BSN of first packet for merged packet
- v.src_out.channel := snk_in.channel; -- use channel of first packet for merged packet
- v.sync := '0'; -- reset captured sync.
+ -- use sync from previous merged packet if it occurred on pkt_cnt /= 0.
+ v.src_out.sync := r.sync;
+ -- use BSN of first packet for merged packet
+ v.src_out.bsn := snk_in.bsn;
+ -- use channel of first packet for merged packet
+ v.src_out.channel := snk_in.channel;
+ -- reset captured sync.
+ v.sync := '0';
if snk_in.sync = '1' then
- v.src_out.sync := '1'; -- set out sync to '1' if this first block contains the sync.
+ -- set out sync to '1' if this first block contains the sync.
+ v.src_out.sync := '1';
end if;
- v.next_bsn := INCR_UVEC(snk_in.bsn, g_bsn_increment); -- expected bsn for next snk_in block
- v.bsn_err := '0'; -- bsn of first block is correct by default
+ -- expected bsn for next snk_in block
+ v.next_bsn := INCR_UVEC(snk_in.bsn, g_bsn_increment);
+ -- bsn of first block is correct by default
+ v.bsn_err := '0';
else
if snk_in.sync = '1' then
- v.sync := '1'; -- Capture sync if it occurs on a pkt_cnt /= 0 so we can use it in the next merged packet
+ -- Capture sync if it occurs on a pkt_cnt /= 0 so we can use it in the next merged packet
+ v.sync := '1';
end if;
- v.next_bsn := INCR_UVEC(r.next_bsn, g_bsn_increment); -- expected bsn for next snk_in block
+ -- expected bsn for next snk_in block
+ v.next_bsn := INCR_UVEC(r.next_bsn, g_bsn_increment);
if unsigned(snk_in.bsn) /= unsigned(r.next_bsn) then
v.bsn_err := '1';
end if;
@@ -357,10 +371,12 @@ begin
if r.pkt_cnt = 0 then
v.src_out.err := snk_in.err;
else
- v.src_out.err := r.src_out.err or snk_in.err; -- OR the err fields of the packets to reflect combined error status.
+ -- OR the err fields of the packets to reflect combined error status.
+ v.src_out.err := r.src_out.err or snk_in.err;
end if;
if g_bsn_increment > 0 then
- v.src_out.err(g_bsn_err_bi) := r.bsn_err; -- report bsn error bit in case of missing snk_in block
+ -- report bsn error bit in case of missing snk_in block
+ v.src_out.err(g_bsn_err_bi) := r.bsn_err;
end if;
if r.pkt_cnt = r.nof_pkt - 1 then
diff --git a/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd b/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
index 76c65b3a90f6e54de9e7edd5d6a88f58d74c8f24..fca9b4086069613450f1ab3a6479eea884a4a8d9 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
@@ -44,12 +44,17 @@ package dp_packet_pkg is
--
-- The DP packet field widths
- constant c_dp_packet_channel_w : natural := 32; -- 4 bytes
- constant c_dp_packet_bsn_w : natural := 64; -- 8 bytes
- constant c_dp_packet_error_w : natural := 32; -- 4 bytes
+ -- 4 bytes
+ constant c_dp_packet_channel_w : natural := 32;
+ -- 8 bytes
+ constant c_dp_packet_bsn_w : natural := 64;
+ -- 4 bytes
+ constant c_dp_packet_error_w : natural := 32;
- constant c_dp_packet_sync_bi : natural := c_dp_packet_bsn_w - 1; -- = use MSbit [63] of BSN field to transport the SOSI sync
- constant c_dp_packet_bsn_hi : natural := c_dp_packet_bsn_w - 2; -- = use rest [62:0] of BSN field to transport the SOSI BSN
+ -- = use MSbit [63] of BSN field to transport the SOSI sync
+ constant c_dp_packet_sync_bi : natural := c_dp_packet_bsn_w - 1;
+ -- = use rest [62:0] of BSN field to transport the SOSI BSN
+ constant c_dp_packet_bsn_hi : natural := c_dp_packet_bsn_w - 2;
-- Determine the length in nof data words to fit the DP packet overhead fields
function func_dp_packet_overhead_len(c_data_w : natural) return natural;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd b/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
index 1fe7ebd08f82c15f48ac1e5622692e84b2afd121..3535357ef66edc57cef9fcc4e37b7e02ad48fe3d 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
@@ -39,8 +39,10 @@ use work.dp_stream_pkg.all;
entity dp_packet_unmerge is
generic (
- g_nof_pkt : natural := 1; -- Nof packets to unmerge each incoming packet to
- g_pkt_len : natural := 1 -- Length of the unmerged packets
+ -- Nof packets to unmerge each incoming packet to
+ g_nof_pkt : natural := 1;
+ -- Length of the unmerged packets
+ g_pkt_len : natural := 1
);
port (
rst : in std_logic;
diff --git a/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd b/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
index cbc94af7224cb6c9b209aee2dfd9ec18a17a88c9..e5f8aab8fb40ea2de14961321da6fdbf542932ee 100644
--- a/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
@@ -61,11 +61,15 @@ package dp_packetizing_pkg is
--<constants>--
constant c_dp_max_w : natural := 64;
- constant c_dp_gap_min : natural := 4; -- minimal gap between valid data blocks (to insert >= 1 idle, sfd, fsn and brc/crc into the stream)
- constant c_dp_idle : std_logic_vector(c_dp_max_w - 1 downto 0) := "0101010101010101010101010101010101010101010101010101010101010101"; -- 0x..5555
- constant c_dp_sfd : std_logic_vector(c_dp_max_w - 1 downto 0) := "0101010101010101010101010101010101010101010101010101010101010100"; -- 0x..5554;
+ -- minimal gap between valid data blocks (to insert >= 1 idle, sfd, fsn and brc/crc into the stream)
+ constant c_dp_gap_min : natural := 4;
+ -- 0x..5555
+ constant c_dp_idle : std_logic_vector(c_dp_max_w - 1 downto 0) := "0101010101010101010101010101010101010101010101010101010101010101";
+ -- 0x..5554;
+ constant c_dp_sfd : std_logic_vector(c_dp_max_w - 1 downto 0) := "0101010101010101010101010101010101010101010101010101010101010100";
-- define more c_dp_sfd_* to have multiple independent dp frame streams per link, e.g. as was used for LOFAR:
- constant c_dp_sfd_lofar : std_logic_vector(c_dp_max_w - 1 downto 0) := "0101010101010101010101010101010101010101010101010001000011111010"; -- 0x..10FA;
+ -- 0x..10FA;
+ constant c_dp_sfd_lofar : std_logic_vector(c_dp_max_w - 1 downto 0) := "0101010101010101010101010101010101010101010101010001000011111010";
constant c_dp_brc_ok : natural := 0;
constant c_dp_brc_err : natural := 1;
diff --git a/libraries/base/dp/src/vhdl/dp_pad_insert.vhd b/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
index 7a0fe1975a1eb11518ad87dcc0650ae48120c3cc..ffbd353998dbfeec448c468d117cd07356b7f158 100644
--- a/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
@@ -43,9 +43,12 @@ use work.dp_stream_pkg.all;
entity dp_pad_insert is
generic (
g_data_w : natural := 64;
- g_symbol_w : natural := 8; -- g_data_w/g_symbol_w must be integer
- g_nof_padding : natural := 6; -- must be > 0 and <= g_data_w/g_symbol_w
- g_internal_bypass : boolean := false -- can be used to eliminate external GENERATE-statements/wiring
+ -- g_data_w/g_symbol_w must be integer
+ g_symbol_w : natural := 8;
+ -- must be > 0 and <= g_data_w/g_symbol_w
+ g_nof_padding : natural := 6;
+ -- can be used to eliminate external GENERATE-statements/wiring
+ g_internal_bypass : boolean := false
);
port (
rst : in std_logic;
@@ -121,10 +124,13 @@ begin
-- Prepend the padding octets to snk_in
pad_siso <= concat_siso_arr(0);
in_siso <= concat_siso_arr(1);
- concat_sosi_arr(0) <= pad_sosi; -- = head frame with in_sosi sop info thanks to p_pad_sosi
- concat_sosi_arr(1) <= in_sosi; -- = tail frame with in_sosi eop info
+ -- = head frame with in_sosi sop info thanks to p_pad_sosi
+ concat_sosi_arr(0) <= pad_sosi;
+ -- = tail frame with in_sosi eop info
+ concat_sosi_arr(1) <= in_sosi;
- u_concat : entity work.dp_concat -- RL = 1
+ -- RL = 1
+ u_concat : entity work.dp_concat
generic map (
g_data_w => g_data_w,
g_symbol_w => g_symbol_w
diff --git a/libraries/base/dp/src/vhdl/dp_pad_remove.vhd b/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
index 134fc740effe0bb5ddbd1251b300d03b4ed8e30b..f0eb8c9e26c9787281a0aeb5b2c2dcf5b6ea227b 100644
--- a/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
@@ -36,9 +36,12 @@ use work.dp_stream_pkg.all;
entity dp_pad_remove is
generic (
g_data_w : natural := 64;
- g_symbol_w : natural := 8; -- g_data_w/g_symbol_w must be integer
- g_nof_padding : natural := 6; -- must be >= 0 (because dp_split can support 0, although using g_nof_padding = 0 is void)
- g_internal_bypass : boolean := false -- can be used to eliminate external GENERATE-statements/wiring
+ -- g_data_w/g_symbol_w must be integer
+ g_symbol_w : natural := 8;
+ -- must be >= 0 (because dp_split can support 0, although using g_nof_padding = 0 is void)
+ g_nof_padding : natural := 6;
+ -- can be used to eliminate external GENERATE-statements/wiring
+ g_internal_bypass : boolean := false
);
port (
rst : in std_logic;
@@ -64,7 +67,8 @@ begin
src_out <= split_sosi_arr(1);
- u_split : entity work.dp_split -- RL = 1
+ -- RL = 1
+ u_split : entity work.dp_split
generic map (
g_data_w => g_data_w,
g_symbol_w => g_symbol_w,
diff --git a/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd b/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
index a2b024710c6caadc676a06a68937987cc0afd607..3a22f1aae8313e62df50fffeaa2fe51ff27bd572 100644
--- a/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
@@ -47,7 +47,8 @@ use work.dp_stream_pkg.all;
entity dp_paged_sop_eop_reg is
generic (
- g_nof_pages : natural := 2 -- >= 0
+ -- >= 0
+ g_nof_pages : natural := 2
);
port (
rst : in std_logic;
@@ -67,8 +68,10 @@ architecture str of dp_paged_sop_eop_reg is
signal src_out_sync : std_logic_vector(0 downto 0);
begin
-- Sosi info at sop
- snk_in_sync(0) <= snk_in.sync; -- convert sl to slv
- src_out.sync <= src_out_sync(0); -- convert slv to sl
+ -- convert sl to slv
+ snk_in_sync(0) <= snk_in.sync;
+ -- convert slv to sl
+ src_out.sync <= src_out_sync(0);
u_paged_sync : entity common_lib.common_paged_reg
generic map (
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline.vhd b/libraries/base/dp/src/vhdl/dp_pipeline.vhd
index 63f860246cf717d911bbb9282398d93d9ca88a97..3e7a46952b5dbd7a2ecc855eb689f2d597406d81 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline.vhd
@@ -46,7 +46,8 @@ use work.dp_stream_pkg.all;
entity dp_pipeline is
generic (
- g_pipeline : natural := 1 -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline : natural := 1
);
port (
rst : in std_logic;
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd b/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
index 57e45e045e4a8c287749f8c4c494ea63e4bda484..2f3ad727d0ed0fb0408c6e42849ef2822a2186a5 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
@@ -32,7 +32,8 @@ use work.dp_stream_pkg.all;
entity dp_pipeline_arr is
generic (
g_nof_streams : natural := 1;
- g_pipeline : natural := 1 -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline : natural := 1
);
port (
rst : in std_logic;
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd b/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
index b4dcc11aac1b11163a0422c6ac6a81bfc92136ac..534a28021fafd93c3ee37b092520361e538c6b37 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
@@ -40,8 +40,10 @@ use work.dp_stream_pkg.all;
entity dp_pipeline_ready is
generic (
- g_in_latency : natural := 1; -- >= 0
- g_out_latency : natural := 1 -- >= 0
+ -- >= 0
+ g_in_latency : natural := 1;
+ -- >= 0
+ g_out_latency : natural := 1
);
port (
rst : in std_logic;
diff --git a/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
index 25446267eae777e47c8216628519119729ec59e3..8bc2bf8e364174fd6da4ffe186c8878d5c08bb79 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
@@ -26,7 +26,8 @@ use common_lib.common_mem_pkg.all;
entity dp_ram_from_mm_reg is
generic (
- g_dp_on_at_init : std_logic := '0' -- Enable data path at default
+ -- Enable data path at default
+ g_dp_on_at_init : std_logic := '0'
);
port (
mm_rst : in std_logic;
@@ -61,7 +62,8 @@ begin
-- Write Block Sync
when 0 =>
mm_dp_on <= sla_in.wrdata(0);
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_ready.vhd b/libraries/base/dp/src/vhdl/dp_ready.vhd
index f1f8532c37cc45f6c750c6937012ad9fdff2068f..68b776b39a07cab252b0413183337f9d8ead6739 100644
--- a/libraries/base/dp/src/vhdl/dp_ready.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ready.vhd
@@ -34,7 +34,8 @@ use work.dp_stream_pkg.all;
entity dp_ready is
generic (
- g_ready_latency : natural := 1 -- >= 0
+ -- >= 0
+ g_ready_latency : natural := 1
);
port (
rst : in std_logic;
@@ -52,7 +53,8 @@ architecture rtl of dp_ready is
signal reg_val : std_logic;
begin
gen_latency : if g_ready_latency > 0 generate
- reg_ready(0) <= src_in.ready; -- use reg_ready(0) to combinatorially store src_in.ready
+ -- use reg_ready(0) to combinatorially store src_in.ready
+ reg_ready(0) <= src_in.ready;
p_clk : process(rst, clk)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
index d0f65d7299734d6a4c435283a0e453714cb7a57e..452339faeda45b3e9d5d91d8899f97491e907123 100644
--- a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
@@ -54,16 +54,23 @@ use work.dp_stream_pkg.all;
entity dp_reinterleave is
generic (
- g_dat_w : natural; -- Width of the data. Either the width of the datafield or the re and im field combined.
- g_nof_in : natural; -- Number of input streams
- g_deint_block_size : natural; -- Inputs streams will be de-interleaved using this block size. Should match block_size_out when g_use_ctrl=TRUE
- g_nof_out : natural; -- The number of output streams
- g_inter_block_size : natural; -- Outputs streams will be interleaved using this block size. Should match block_size_in when g_use_ctrl=TRUE
+ -- Width of the data. Either the width of the datafield or the re and im field combined.
+ g_dat_w : natural;
+ -- Number of input streams
+ g_nof_in : natural;
+ -- Inputs streams will be de-interleaved using this block size. Should match block_size_out when g_use_ctrl=TRUE
+ g_deint_block_size : natural;
+ -- The number of output streams
+ g_nof_out : natural;
+ -- Outputs streams will be interleaved using this block size. Should match block_size_in when g_use_ctrl=TRUE
+ g_inter_block_size : natural;
g_use_ctrl : boolean := true;
- g_use_sync_bsn : boolean := true; -- forwards (stored) input Sync+BSN to all output streams
+ -- forwards (stored) input Sync+BSN to all output streams
+ g_use_sync_bsn : boolean := true;
g_use_complex : boolean;
g_align_out : boolean := false;
- g_block_size_output : natural := 1 -- Output block size: The number of samles in the blocks at the output
+ -- Output block size: The number of samles in the blocks at the output
+ g_block_size_output : natural := 1
);
port (
rst : in std_logic;
@@ -188,8 +195,10 @@ begin
rst => rst,
clk => clk,
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in_arr(0), -- original snk_in info
+ -- delayed snk_in data
+ data_snk_in => dp_block_gen_src_out_arr(i),
+ -- original snk_in info
+ info_snk_in => snk_in_arr(0),
src_in => c_dp_siso_rdy,
src_out => src_out_arr(i)
diff --git a/libraries/base/dp/src/vhdl/dp_repack.vhd b/libraries/base/dp/src/vhdl/dp_repack.vhd
index ebc3dd4c1b829e0f05476741b0623d7f483619e9..64bd0d33148798dcb0dc79b7ff4053fa8e1a0547 100644
--- a/libraries/base/dp/src/vhdl/dp_repack.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack.vhd
@@ -43,7 +43,8 @@ entity dp_repack is
g_in_nof_words : natural;
g_out_dat_w : natural;
g_out_nof_words : natural;
- g_ls_to_ms : boolean := true -- Read input SLV from LS to MS word by default
+ -- Read input SLV from LS to MS word by default
+ g_ls_to_ms : boolean := true
);
port (
rst : in std_logic;
@@ -53,13 +54,15 @@ entity dp_repack is
in_val : in std_logic := '1';
in_sof : in std_logic := '0';
in_eof : in std_logic := '0';
- in_sync : in std_logic := '0'; -- DP style sync at sof
+ -- DP style sync at sof
+ in_sync : in std_logic := '0';
out_dat : out std_logic_vector(g_out_dat_w - 1 downto 0);
out_val : out std_logic;
out_sof : out std_logic;
out_eof : out std_logic;
- sof_sync : out std_logic -- DP style sync at sof, passes on in_sync
+ -- DP style sync at sof, passes on in_sync
+ sof_sync : out std_logic
);
end dp_repack;
@@ -83,8 +86,10 @@ architecture rtl of dp_repack is
signal out_eof_vec : std_logic_vector(g_out_nof_words - 1 downto 0);
signal nxt_out_eof_vec : std_logic_vector(out_eof_vec'range);
- signal buf_load : std_logic; -- input vec to buf
- signal buf_flush : std_logic; -- buf to output vec
+ -- input vec to buf
+ signal buf_load : std_logic;
+ -- buf to output vec
+ signal buf_flush : std_logic;
signal buf_sof : std_logic;
signal nxt_buf_sof : std_logic;
signal buf_sync : std_logic;
@@ -95,7 +100,8 @@ architecture rtl of dp_repack is
signal nxt_sof_sync : std_logic;
begin
no_pack : if g_in_nof_words = g_out_nof_words generate
- out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack at the other end,
+ -- any extra bits will get stripped again by dp_repack at the other end,
+ out_dat <= RESIZE_UVEC(in_dat, out_dat'length);
-- typically g_out_dat_w=g_in_dat_w
out_val <= in_val;
out_sof <= in_sof;
@@ -179,8 +185,10 @@ begin
p_buf : process(buf_load, buf_flush, in_sync, in_sof, in_eof, buf_sync, buf_sof, buf_eof, in_dat_vec, in_val_vec, buf_dat_vec, buf_val)
begin
- nxt_buf_sof <= buf_sof; -- buf_sof
- nxt_buf_sync <= buf_sync; -- buf_sync
+ -- buf_sof
+ nxt_buf_sof <= buf_sof;
+ -- buf_sync
+ nxt_buf_sync <= buf_sync;
if in_sof = '1' then
nxt_buf_sof <= '1';
nxt_buf_sync <= in_sync;
@@ -188,13 +196,15 @@ begin
nxt_buf_sof <= '0';
nxt_buf_sync <= '0';
end if;
- nxt_buf_eof <= buf_eof; -- buf_eof
+ -- buf_eof
+ nxt_buf_eof <= buf_eof;
if in_eof = '1' then
nxt_buf_eof <= '1';
elsif buf_flush = '1' and buf_load = '0' then
nxt_buf_eof <= '0';
end if;
- nxt_buf_dat_vec <= buf_dat_vec; -- buf_dat_vec, buf_val
+ -- buf_dat_vec, buf_val
+ nxt_buf_dat_vec <= buf_dat_vec;
nxt_buf_val <= buf_val;
if buf_load = '1' then
nxt_buf_dat_vec <= in_dat_vec;
@@ -207,7 +217,8 @@ begin
p_out: process(buf_flush, buf_load, buf_sync, buf_sof, buf_eof, buf_dat_vec, out_val_vec, out_dat_vec, out_eof_vec)
begin
- nxt_out_dat_vec <= out_dat_vec; -- out_dat, out_val, out_sof
+ -- out_dat, out_val, out_sof
+ nxt_out_dat_vec <= out_dat_vec;
if buf_flush = '1' then
nxt_out_dat_vec <= buf_dat_vec;
nxt_out_val_vec <= (others => '1');
@@ -228,7 +239,8 @@ begin
nxt_out_sof <= '0';
nxt_sof_sync <= '0';
end if;
- nxt_out_eof_vec <= out_eof_vec; -- out_eof
+ -- out_eof
+ nxt_out_eof_vec <= out_eof_vec;
if buf_flush = '1' and buf_load = '0' then
nxt_out_eof_vec <= (others => '0');
nxt_out_eof_vec(out_eof_vec'high) <= buf_eof;
diff --git a/libraries/base/dp/src/vhdl/dp_repack_data.vhd b/libraries/base/dp/src/vhdl/dp_repack_data.vhd
index fbc1849f6a79eb003fcbabc5ed3a4a8e6db5a95a..fbc91cf5ca00501620974f5d26b4e53aebafe95d 100644
--- a/libraries/base/dp/src/vhdl/dp_repack_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack_data.vhd
@@ -184,7 +184,8 @@ entity dp_repack_in is
g_bypass : boolean := false;
g_in_dat_w : natural;
g_in_nof_words : natural;
- g_in_symbol_w : natural := 1 -- default 1 for snk_in.empty in nof bits, else use power of 2
+ -- default 1 for snk_in.empty in nof bits, else use power of 2
+ g_in_symbol_w : natural := 1
);
port (
rst : in std_logic;
@@ -207,13 +208,20 @@ architecture rtl of dp_repack_in is
type t_dat_arr is array (integer range <>) of std_logic_vector(g_in_dat_w - 1 downto 0);
type t_reg is record
- dat_arr : t_dat_arr(g_in_nof_words - 1 downto 0); -- internally use dat_arr[] to represent v.src_out.data
- src_out : t_dp_sosi; -- sosi output
- src_out_data : std_logic_vector(c_in_buf_dat_w - 1 downto 0); -- Use seperate STD_LOGIC_VECTOR to carry the sosi data as c_in_buf_dat_w can be larger than c_dp_stream_data_w.
- hold_out : t_dp_sosi; -- hold snk_in.sync/sop/eop until end of section and then hold valid src_out until src_in.ready
- flush : std_logic; -- shift when snk_in.valid or flush in case the last subsection has < g_in_nof_words
- dat_bit_cnt : natural range 0 to c_bit_cnt_max; -- actual nof bits in subsection
- pack_bit_cnt : natural range 0 to c_bit_cnt_max; -- count nof bits in subsection
+ -- internally use dat_arr[] to represent v.src_out.data
+ dat_arr : t_dat_arr(g_in_nof_words - 1 downto 0);
+ -- sosi output
+ src_out : t_dp_sosi;
+ -- Use seperate STD_LOGIC_VECTOR to carry the sosi data as c_in_buf_dat_w can be larger than c_dp_stream_data_w.
+ src_out_data : std_logic_vector(c_in_buf_dat_w - 1 downto 0);
+ -- hold snk_in.sync/sop/eop until end of section and then hold valid src_out until src_in.ready
+ hold_out : t_dp_sosi;
+ -- shift when snk_in.valid or flush in case the last subsection has < g_in_nof_words
+ flush : std_logic;
+ -- actual nof bits in subsection
+ dat_bit_cnt : natural range 0 to c_bit_cnt_max;
+ -- count nof bits in subsection
+ pack_bit_cnt : natural range 0 to c_bit_cnt_max;
end record;
signal data_vec : std_logic_vector(c_in_buf_dat_w - 1 downto 0);
@@ -273,18 +281,22 @@ begin
end if;
if snk_in.eop = '1' then
v.hold_out.eop := '1';
- v.hold_out.empty := SHIFT_UVEC(snk_in.empty, -c_in_empty_lo); -- use snk_in.empty as offset for src_out.empty in nof bits
+ -- use snk_in.empty as offset for src_out.empty in nof bits
+ v.hold_out.empty := SHIFT_UVEC(snk_in.empty, -c_in_empty_lo);
v.src_out.err := snk_in.err;
end if;
-- Capture the data per subsection in a block
if snk_in.valid = '1' or r.flush = '1' then
-- shift in during block
- v.dat_arr(g_in_nof_words - 1 downto 1) := r.dat_arr(g_in_nof_words - 2 downto 0); -- shift up from low to high and shift in at index 0
+ -- shift up from low to high and shift in at index 0
+ v.dat_arr(g_in_nof_words - 1 downto 1) := r.dat_arr(g_in_nof_words - 2 downto 0);
if r.flush = '1' then
- v.dat_arr(0) := (others => '0'); -- shift in data=0 for flush
+ -- shift in data=0 for flush
+ v.dat_arr(0) := (others => '0');
else
- v.dat_arr(0) := snk_in.data(g_in_dat_w - 1 downto 0); -- shift in valid data
+ -- shift in valid data
+ v.dat_arr(0) := snk_in.data(g_in_dat_w - 1 downto 0);
end if;
-- pack subsection
@@ -293,18 +305,23 @@ begin
-- early end of pack subsection
if snk_in.eop = '1' then
- v.flush := '1'; -- enable flush in case eop occurs before end of pack subsection
- v.dat_bit_cnt := v.pack_bit_cnt; -- capture the current subsection pack_bit_cnt
+ -- enable flush in case eop occurs before end of pack subsection
+ v.flush := '1';
+ -- capture the current subsection pack_bit_cnt
+ v.dat_bit_cnt := v.pack_bit_cnt;
end if;
- else -- r.pack_bit_cnt=c_in_buf_dat_w-g_in_dat_w
+ -- r.pack_bit_cnt=c_in_buf_dat_w-g_in_dat_w
+ else
-- default end of pack subsection
v.pack_bit_cnt := 0;
v.flush := '0';
if r.flush = '0' then
- v.dat_bit_cnt := c_in_buf_dat_w; -- set default subsection pack_bit_cnt
+ -- set default subsection pack_bit_cnt
+ v.dat_bit_cnt := c_in_buf_dat_w;
end if;
- v.hold_out.valid := '1'; -- the function has new data to output
+ -- the function has new data to output
+ v.hold_out.valid := '1';
end if;
end if;
@@ -374,13 +391,16 @@ begin
begin
r_snk_out <= c_dp_siso_rdy;
if nxt_r.flush = '1' then
- r_snk_out.ready <= '0'; -- input shift in stage function is always ready except when flushing
+ -- input shift in stage function is always ready except when flushing
+ r_snk_out.ready <= '0';
end if;
end process;
-- combined local and remote src_in flow control
- snk_out.ready <= r_snk_out.ready when nxt_r.hold_out.valid = '0' else src_in.ready; -- if there is pending output then the src_in ready determines the flow control
- snk_out.xon <= src_in.xon; -- just pass on the xon/off frame flow control
+ -- if there is pending output then the src_in ready determines the flow control
+ snk_out.ready <= r_snk_out.ready when nxt_r.hold_out.valid = '0' else src_in.ready;
+ -- just pass on the xon/off frame flow control
+ snk_out.xon <= src_in.xon;
end generate;
end rtl;
@@ -396,7 +416,8 @@ entity dp_repack_out is
g_in_buf_dat_w : natural;
g_out_dat_w : natural;
g_out_nof_words : natural;
- g_out_symbol_w : natural := 1 -- default 1 for snk_in.empty in nof bits, else use power of 2
+ -- default 1 for snk_in.empty in nof bits, else use power of 2
+ g_out_symbol_w : natural := 1
);
port (
rst : in std_logic;
@@ -413,8 +434,10 @@ end dp_repack_out;
architecture rtl of dp_repack_out is
constant c_out_buf_dat_w : natural := g_out_dat_w * g_out_nof_words;
- constant c_out_buf_dat_lo : natural := sel_a_b(c_out_buf_dat_w > g_in_buf_dat_w, c_out_buf_dat_w - g_in_buf_dat_w, 0); -- pack into subsection with 0 or more padding bits
- constant c_snk_in_dat_lo : natural := sel_a_b(c_out_buf_dat_w < g_in_buf_dat_w, g_in_buf_dat_w - c_out_buf_dat_w, 0); -- unpack from subsection that has 0 or more padding bits
+ -- pack into subsection with 0 or more padding bits
+ constant c_out_buf_dat_lo : natural := sel_a_b(c_out_buf_dat_w > g_in_buf_dat_w, c_out_buf_dat_w - g_in_buf_dat_w, 0);
+ -- unpack from subsection that has 0 or more padding bits
+ constant c_snk_in_dat_lo : natural := sel_a_b(c_out_buf_dat_w < g_in_buf_dat_w, g_in_buf_dat_w - c_out_buf_dat_w, 0);
constant c_bit_cnt_max : natural := c_out_buf_dat_w;
constant c_out_empty_lo : natural := true_log2(g_out_symbol_w);
@@ -423,12 +446,18 @@ architecture rtl of dp_repack_out is
type t_reg is record
dat_arr : t_dat_arr(g_out_nof_words - 1 downto 0);
src_out : t_dp_sosi;
- hold_out : t_dp_sosi; -- hold src_out valid and sync/sop/eop until src_in.ready
- shift : std_logic; -- shift out the dat_arr
- dat_bit_cnt : natural range 0 to c_bit_cnt_max; -- actual nof bits in subsection
- pack_bit_cnt : natural range 0 to c_bit_cnt_max; -- count nof bits in subsection
- empty_bit_cnt : natural range 0 to c_bit_cnt_max; -- empty nof bits in subsection
- eos : std_logic; -- end of subsection
+ -- hold src_out valid and sync/sop/eop until src_in.ready
+ hold_out : t_dp_sosi;
+ -- shift out the dat_arr
+ shift : std_logic;
+ -- actual nof bits in subsection
+ dat_bit_cnt : natural range 0 to c_bit_cnt_max;
+ -- count nof bits in subsection
+ pack_bit_cnt : natural range 0 to c_bit_cnt_max;
+ -- empty nof bits in subsection
+ empty_bit_cnt : natural range 0 to c_bit_cnt_max;
+ -- end of subsection
+ eos : std_logic;
end record;
signal data_vec : std_logic_vector(c_out_buf_dat_w - 1 downto 0) := (others => '0');
@@ -502,7 +531,8 @@ begin
v.src_out.channel := snk_in.channel;
end if;
if snk_in.eop = '1' then
- v.hold_out.eop := '1'; -- local function will calculate src_out.empty based on snk_in.empty
+ -- local function will calculate src_out.empty based on snk_in.empty
+ v.hold_out.eop := '1';
v.src_out.err := snk_in.err;
end if;
@@ -510,15 +540,19 @@ begin
-- shift out rest of subsection
v.hold_out.valid := '1';
- v.dat_arr(g_out_nof_words - 1 downto 1) := r.dat_arr(g_out_nof_words - 2 downto 0); -- shift up from low to high and shift out at high index
- v.dat_arr(0) := (others => '0'); -- shift in data=0
+ -- shift up from low to high and shift out at high index
+ v.dat_arr(g_out_nof_words - 1 downto 1) := r.dat_arr(g_out_nof_words - 2 downto 0);
+ -- shift in data=0
+ v.dat_arr(0) := (others => '0');
v.pack_bit_cnt := r.pack_bit_cnt - g_out_dat_w;
-- end of pack subsection
if v.pack_bit_cnt <= r.empty_bit_cnt then
- v.eos := '1'; -- end of subsection, so ready for new snk_in
- v.shift := '0'; -- stop shifting
+ -- end of subsection, so ready for new snk_in
+ v.eos := '1';
+ -- stop shifting
+ v.shift := '0';
end if;
elsif snk_in.valid = '1' then
@@ -529,9 +563,11 @@ begin
v.dat_arr(I) := data_vec((I + 1) * g_out_dat_w - 1 downto I * g_out_dat_w);
end loop;
- v.dat_bit_cnt := g_in_buf_dat_w - c_snk_in_dat_lo; -- default dat_bit_cnt per subsection
+ -- default dat_bit_cnt per subsection
+ v.dat_bit_cnt := g_in_buf_dat_w - c_snk_in_dat_lo;
if snk_in.eop = '1' then
- v.dat_bit_cnt := g_in_buf_dat_w - TO_UINT(snk_in.empty); -- pass on last subsection dat_bit_cnt info via DP empty field
+ -- pass on last subsection dat_bit_cnt info via DP empty field
+ v.dat_bit_cnt := g_in_buf_dat_w - TO_UINT(snk_in.empty);
end if;
v.pack_bit_cnt := c_out_buf_dat_w - g_out_dat_w;
@@ -541,7 +577,8 @@ begin
-- end of pack subsection
if v.pack_bit_cnt <= v.empty_bit_cnt then
- v.eos := '1'; -- end of subsection, so ready for new snk_in
+ -- end of subsection, so ready for new snk_in
+ v.eos := '1';
v.shift := '0';
end if;
end if;
@@ -549,8 +586,10 @@ begin
-- fill in local empty if this is the last subsection of a block
if v.eos = '1' then
if v.hold_out.eop = '1' then
- v.src_out.empty := TO_DP_EMPTY(v.empty_bit_cnt - v.pack_bit_cnt); -- in nof bits
- v.src_out.empty := SHIFT_UVEC(v.src_out.empty, c_out_empty_lo); -- in nof symbols
+ -- in nof bits
+ v.src_out.empty := TO_DP_EMPTY(v.empty_bit_cnt - v.pack_bit_cnt);
+ -- in nof symbols
+ v.src_out.empty := SHIFT_UVEC(v.src_out.empty, c_out_empty_lo);
end if;
end if;
@@ -563,7 +602,8 @@ begin
v.src_out.valid := '1';
v.src_out.sync := v.hold_out.sync;
v.src_out.sop := v.hold_out.sop;
- v.src_out.eop := v.hold_out.eop and v.eos; -- output eop at end of subsection
+ -- output eop at end of subsection
+ v.src_out.eop := v.hold_out.eop and v.eos;
v.hold_out.valid := '0';
end if;
end if;
@@ -574,7 +614,8 @@ begin
v.src_out.valid := '1';
v.src_out.sync := r.hold_out.sync;
v.src_out.sop := r.hold_out.sop;
- v.src_out.eop := r.hold_out.eop and r.eos; -- output eop at end of subsection
+ -- output eop at end of subsection
+ v.src_out.eop := r.hold_out.eop and r.eos;
v.hold_out.valid := '0';
end if;
end if;
@@ -614,13 +655,16 @@ begin
begin
r_snk_out <= c_dp_siso_rdy;
if nxt_r.shift = '1' and nxt_r.eos = '0' then
- r_snk_out.ready <= '0'; -- output shift out stage function is only ready when it is not shifting or at the end of the subsection
+ -- output shift out stage function is only ready when it is not shifting or at the end of the subsection
+ r_snk_out.ready <= '0';
end if;
end process;
-- combined local and remote src_in flow control
- snk_out.ready <= r_snk_out.ready when nxt_r.hold_out.valid = '0' else src_in.ready; -- if there is pending output then the src_in ready determines the flow control
- snk_out.xon <= src_in.xon; -- just pass on the xon/off frame flow control
+ -- if there is pending output then the src_in ready determines the flow control
+ snk_out.ready <= r_snk_out.ready when nxt_r.hold_out.valid = '0' else src_in.ready;
+ -- just pass on the xon/off frame flow control
+ snk_out.xon <= src_in.xon;
end generate;
end rtl;
@@ -637,12 +681,15 @@ entity dp_repack_data is
g_in_bypass : boolean := false;
g_in_dat_w : natural;
g_in_nof_words : natural;
- g_in_symbol_w : natural := 1; -- default 1 for snk_in.empty in nof bits, else use power of 2
+ -- default 1 for snk_in.empty in nof bits, else use power of 2
+ g_in_symbol_w : natural := 1;
g_out_bypass : boolean := false;
g_out_dat_w : natural;
g_out_nof_words : natural;
- g_out_symbol_w : natural := 1; -- default 1 for src_out.empty in nof bits, else use power of 2
- g_pipeline_ready : boolean := false -- TRUE to pipeline ready from src_in to snk_out.
+ -- default 1 for src_out.empty in nof bits, else use power of 2
+ g_out_symbol_w : natural := 1;
+ -- TRUE to pipeline ready from src_in to snk_out.
+ g_pipeline_ready : boolean := false
);
port (
rst : in std_logic;
diff --git a/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd b/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
index 5149b5f2aa0e10f745d397dc9562715acf3a1058..e3db23fb7349046261753ce45719c68304cc1e00 100644
--- a/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
@@ -43,7 +43,8 @@ entity dp_repack_legacy is
g_in_nof_words : natural;
g_out_dat_w : natural;
g_out_nof_words : natural;
- g_ls_to_ms : boolean := true -- Read input SLV from LS to MS word by default
+ -- Read input SLV from LS to MS word by default
+ g_ls_to_ms : boolean := true
);
port (
rst : in std_logic;
@@ -53,13 +54,15 @@ entity dp_repack_legacy is
in_val : in std_logic := '1';
in_sof : in std_logic := '0';
in_eof : in std_logic := '0';
- in_sync : in std_logic := '0'; -- DP style sync at sof
+ -- DP style sync at sof
+ in_sync : in std_logic := '0';
out_dat : out std_logic_vector(g_out_dat_w - 1 downto 0);
out_val : out std_logic;
out_sof : out std_logic;
out_eof : out std_logic;
- sof_sync : out std_logic -- DP style sync at sof, passes on in_sync
+ -- DP style sync at sof, passes on in_sync
+ sof_sync : out std_logic
);
end dp_repack_legacy;
@@ -83,8 +86,10 @@ architecture rtl of dp_repack_legacy is
signal out_eof_vec : std_logic_vector(g_out_nof_words - 1 downto 0);
signal nxt_out_eof_vec : std_logic_vector(out_eof_vec'range);
- signal buf_load : std_logic; -- input vec to buf
- signal buf_flush : std_logic; -- buf to output vec
+ -- input vec to buf
+ signal buf_load : std_logic;
+ -- buf to output vec
+ signal buf_flush : std_logic;
signal buf_sof : std_logic;
signal nxt_buf_sof : std_logic;
signal buf_sync : std_logic;
@@ -95,7 +100,8 @@ architecture rtl of dp_repack_legacy is
signal nxt_sof_sync : std_logic;
begin
no_pack : if g_in_nof_words = g_out_nof_words generate
- out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack_legacy at the other end,
+ -- any extra bits will get stripped again by dp_repack_legacy at the other end,
+ out_dat <= RESIZE_UVEC(in_dat, out_dat'length);
-- typically g_out_dat_w=g_in_dat_w
out_val <= in_val;
out_sof <= in_sof;
@@ -179,8 +185,10 @@ begin
p_buf : process(buf_load, buf_flush, in_sync, in_sof, in_eof, buf_sync, buf_sof, buf_eof, in_dat_vec, in_val_vec, buf_dat_vec, buf_val)
begin
- nxt_buf_sof <= buf_sof; -- buf_sof
- nxt_buf_sync <= buf_sync; -- buf_sync
+ -- buf_sof
+ nxt_buf_sof <= buf_sof;
+ -- buf_sync
+ nxt_buf_sync <= buf_sync;
if in_sof = '1' then
nxt_buf_sof <= '1';
nxt_buf_sync <= in_sync;
@@ -188,13 +196,15 @@ begin
nxt_buf_sof <= '0';
nxt_buf_sync <= '0';
end if;
- nxt_buf_eof <= buf_eof; -- buf_eof
+ -- buf_eof
+ nxt_buf_eof <= buf_eof;
if in_eof = '1' then
nxt_buf_eof <= '1';
elsif buf_flush = '1' and buf_load = '0' then
nxt_buf_eof <= '0';
end if;
- nxt_buf_dat_vec <= buf_dat_vec; -- buf_dat_vec, buf_val
+ -- buf_dat_vec, buf_val
+ nxt_buf_dat_vec <= buf_dat_vec;
nxt_buf_val <= buf_val;
if buf_load = '1' then
nxt_buf_dat_vec <= in_dat_vec;
@@ -207,7 +217,8 @@ begin
p_out: process(buf_flush, buf_load, buf_sync, buf_sof, buf_eof, buf_dat_vec, out_val_vec, out_dat_vec, out_eof_vec)
begin
- nxt_out_dat_vec <= out_dat_vec; -- out_dat, out_val, out_sof
+ -- out_dat, out_val, out_sof
+ nxt_out_dat_vec <= out_dat_vec;
if buf_flush = '1' then
nxt_out_dat_vec <= buf_dat_vec;
nxt_out_val_vec <= (others => '1');
@@ -228,7 +239,8 @@ begin
nxt_out_sof <= '0';
nxt_sof_sync <= '0';
end if;
- nxt_out_eof_vec <= out_eof_vec; -- out_eof
+ -- out_eof
+ nxt_out_eof_vec <= out_eof_vec;
if buf_flush = '1' and buf_load = '0' then
nxt_out_eof_vec <= (others => '0');
nxt_out_eof_vec(out_eof_vec'high) <= buf_eof;
diff --git a/libraries/base/dp/src/vhdl/dp_requantize.vhd b/libraries/base/dp/src/vhdl/dp_requantize.vhd
index c063da2ad8305ae55fb422bd0f9299401e8a9d26..6793f78d96d7a0814a29dd2bd5aa2f7ddba7703a 100644
--- a/libraries/base/dp/src/vhdl/dp_requantize.vhd
+++ b/libraries/base/dp/src/vhdl/dp_requantize.vhd
@@ -34,22 +34,35 @@ use common_lib.common_pkg.all;
entity dp_requantize is
generic (
- g_complex : boolean := true; -- when TRUE, the re and im field are processed, when false, the data field is processed
- g_representation : string := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
- g_lsb_w : integer := 4; -- when > 0, number of LSbits to remove from in_dat
+ -- when TRUE, the re and im field are processed, when false, the data field is processed
+ g_complex : boolean := true;
+ -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
+ g_representation : string := "SIGNED";
+ -- when > 0, number of LSbits to remove from in_dat
+ g_lsb_w : integer := 4;
-- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
-- when 0 then no effect
- g_lsb_round : boolean := true; -- when TRUE round else truncate the input LSbits
- g_lsb_round_clip : boolean := false; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
- g_lsb_round_even : boolean := true; -- when TRUE round half to even, else round half away from zero
- g_msb_clip : boolean := true; -- when TRUE CLIP else WRAP the input MSbits
- g_msb_clip_symmetric : boolean := false; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
+ -- when TRUE round else truncate the input LSbits
+ g_lsb_round : boolean := true;
+ -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
+ g_lsb_round_clip : boolean := false;
+ -- when TRUE round half to even, else round half away from zero
+ g_lsb_round_even : boolean := true;
+ -- when TRUE CLIP else WRAP the input MSbits
+ g_msb_clip : boolean := true;
+ -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
+ g_msb_clip_symmetric : boolean := false;
-- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
- g_gain_w : natural := 0; -- do not use, must be 0, use negative g_lsb_w instead
- g_pipeline_remove_lsb : natural := 0; -- >= 0
- g_pipeline_remove_msb : natural := 0; -- >= 0, use g_pipeline_remove_lsb=0 and g_pipeline_remove_msb=0 for combinatorial output
- g_in_dat_w : natural := 36; -- input data width
- g_out_dat_w : natural := 18 -- output data width
+ -- do not use, must be 0, use negative g_lsb_w instead
+ g_gain_w : natural := 0;
+ -- >= 0
+ g_pipeline_remove_lsb : natural := 0;
+ -- >= 0, use g_pipeline_remove_lsb=0 and g_pipeline_remove_msb=0 for combinatorial output
+ g_pipeline_remove_msb : natural := 0;
+ -- input data width
+ g_in_dat_w : natural := 36;
+ -- output data width
+ g_out_dat_w : natural := 18
);
port (
rst : in std_logic;
@@ -59,7 +72,8 @@ entity dp_requantize is
-- ST source
src_out : out t_dp_sosi;
--
- out_ovr : out std_logic -- out_ovr is '1' when the removal of MSbits causes clipping or wrapping
+ -- out_ovr is '1' when the removal of MSbits causes clipping or wrapping
+ out_ovr : out std_logic
);
end dp_requantize;
@@ -156,7 +170,8 @@ begin
--------------------------------------------------------------
u_dp_pipeline : entity work.dp_pipeline
generic map (
- g_pipeline => c_pipeline -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline => c_pipeline
)
port map (
rst => rst,
diff --git a/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd b/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
index 7e76bc93ba2fda5f3dbb0ee1e46025cd77b1f1a0..8c5d15aa6133cb7893a40fa2cd1ca019b6c46959 100644
--- a/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
@@ -46,12 +46,15 @@ use work.dp_stream_pkg.all;
entity dp_reverse_n_data is
generic (
-- Pipeline: 0 for combinatorial, > 0 for registers
- g_pipeline_demux_in : natural := 1; -- serial to parallel section
+ -- serial to parallel section
+ g_pipeline_demux_in : natural := 1;
g_pipeline_demux_out : natural := 0;
- g_pipeline_mux_in : natural := 0; -- parallel to serial section
+ -- parallel to serial section
+ g_pipeline_mux_in : natural := 0;
g_pipeline_mux_out : natural := 1;
g_reverse_len : natural := 2;
- g_data_w : natural := 16; -- should be 2 times the c_complex_w if g_use_complex = TRUE
+ -- should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_w : natural := 16;
g_use_complex : boolean := false;
g_signed : boolean := true
);
@@ -89,9 +92,11 @@ begin
u_common_reverse_n : entity common_lib.common_reverse_n_data
generic map (
-- Pipeline: 0 for combinatorial, > 0 for registers
- g_pipeline_demux_in => g_pipeline_demux_in, -- serial to parallel demux
+ -- serial to parallel demux
+ g_pipeline_demux_in => g_pipeline_demux_in,
g_pipeline_demux_out => g_pipeline_demux_out,
- g_pipeline_mux_in => g_pipeline_mux_in, -- parallel to serial mux
+ -- parallel to serial mux
+ g_pipeline_mux_in => g_pipeline_mux_in,
g_pipeline_mux_out => g_pipeline_mux_out,
g_reverse_len => g_reverse_len,
g_data_w => g_data_w
@@ -104,7 +109,8 @@ begin
in_val => snk_in.valid,
in_eop => snk_in.eop,
out_data => reversed_data,
- out_val => reversed_val -- = snk_in_delayed.valid
+ -- = snk_in_delayed.valid
+ out_val => reversed_val
);
-- Pipeline other sosi fields
diff --git a/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd b/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
index 77741d7694fc2fd2e24368c07c94994743ee86ab..6672595da8c7fc715847d5ee5c41f1cff0aa1ea6 100644
--- a/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
@@ -45,8 +45,10 @@ use work.dp_stream_pkg.all;
entity dp_reverse_n_data_fc is
generic (
-- Pipeline: 0 for combinatorial, > 0 for registers
- g_pipeline_in : natural := 1; -- serial to parallel section
- g_pipeline_out : natural := 0; -- parallel to serial section
+ -- serial to parallel section
+ g_pipeline_in : natural := 1;
+ -- parallel to serial section
+ g_pipeline_out : natural := 0;
g_reverse_len : natural
);
port (
diff --git a/libraries/base/dp/src/vhdl/dp_rsn_source.vhd b/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
index db1c3512342323fb01cfcf219686b085bd84b435..089fd285c618108ddf61c27089ea737033e9ae84 100644
--- a/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
@@ -69,8 +69,10 @@ use work.dp_stream_pkg.all;
entity dp_rsn_source is
generic (
- g_bs_block_size : natural := 256; -- input bs_sosi block size, >= 3, see state machine
- g_rs_block_size : natural := 256; -- output rs_sosi block size, >= 3, see state machine
+ -- input bs_sosi block size, >= 3, see state machine
+ g_bs_block_size : natural := 256;
+ -- output rs_sosi block size, >= 3, see state machine
+ g_rs_block_size : natural := 256;
g_nof_clk_per_sync : natural := 200 * 10**6;
g_bsn_w : natural := 64
);
@@ -79,19 +81,25 @@ entity dp_rsn_source is
clk : in std_logic;
-- Input stream sosi control using BSN
- bs_sosi : in t_dp_sosi; -- input reference stream using BSN
+ -- input reference stream using BSN
+ bs_sosi : in t_dp_sosi;
-- Output stream sosi control using RSN
nof_clk_per_sync : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w);
- rs_sosi : out t_dp_sosi; -- output stream using RSN and g_rs_block_size, g_nof_clk_per_sync
- rs_restart : out std_logic; -- = rs_sosi.sync for first sync after bs_sosi.valid went high
- rs_new_interval : out std_logic -- = active during first rs_sosi.sync interval
+ -- output stream using RSN and g_rs_block_size, g_nof_clk_per_sync
+ rs_sosi : out t_dp_sosi;
+ -- = rs_sosi.sync for first sync after bs_sosi.valid went high
+ rs_restart : out std_logic;
+ -- = active during first rs_sosi.sync interval
+ rs_new_interval : out std_logic
);
end dp_rsn_source;
architecture rtl of dp_rsn_source is
- constant c_bs_block_size_cnt_w : natural := ceil_log2(g_bs_block_size) + 1; -- +1 because value 2**n requires n + 1 bits
- constant c_rs_block_size_cnt_w : natural := ceil_log2(g_rs_block_size) + 1; -- +1 because value 2**n requires n + 1 bits
+ -- +1 because value 2**n requires n + 1 bits
+ constant c_bs_block_size_cnt_w : natural := ceil_log2(g_bs_block_size) + 1;
+ -- +1 because value 2**n requires n + 1 bits
+ constant c_rs_block_size_cnt_w : natural := ceil_log2(g_rs_block_size) + 1;
constant c_rsn_product_w : natural := g_bsn_w + c_bs_block_size_cnt_w;
type t_state_enum is (s_off, s_on_sop, s_on, s_on_eop);
@@ -139,16 +147,19 @@ begin
nxt_sync <= sync;
nxt_sync_size_cnt <= INCR_UVEC(sync_size_cnt, 1);
if unsigned(sync_size_cnt) = unsigned(nof_clk_per_sync) - 1 then
- nxt_sync <= '1'; -- will set rs_sosi.sync on next rs_sosi.sop
+ -- will set rs_sosi.sync on next rs_sosi.sop
+ nxt_sync <= '1';
nxt_sync_size_cnt <= (others => '0');
end if;
if i_rs_sosi.sync = '1' then
- nxt_sync <= '0'; -- clear when sync has been applied in rs_sosi
+ -- clear when sync has been applied in rs_sosi
+ nxt_sync <= '0';
end if;
-- State machine for rs_sosi
nxt_state <= state;
- nxt_rs_sosi <= i_rs_sosi; -- hold rs_sosi.bsn
+ -- hold rs_sosi.bsn
+ nxt_rs_sosi <= i_rs_sosi;
nxt_rs_sosi.sync <= '0';
nxt_rs_sosi.valid <= '0';
nxt_rs_sosi.sop <= '0';
@@ -158,7 +169,8 @@ begin
case state is
when s_off =>
nxt_rs_sosi <= c_dp_sosi_rst;
- nxt_rs_sosi.bsn <= RESIZE_DP_BSN(rsn); -- RSN fits in g_bsn_w
+ -- RSN fits in g_bsn_w
+ nxt_rs_sosi.bsn <= RESIZE_DP_BSN(rsn);
nxt_sync <= '0';
nxt_sync_size_cnt <= (others => '0');
nxt_rs_block_size_cnt <= (others => '0');
@@ -181,7 +193,8 @@ begin
nxt_rs_block_size_cnt <= (others => '0');
-- after first block, increment bsn per block
if prev_state = s_on_eop then
- nxt_rs_sosi.bsn <= INCR_DP_BSN(i_rs_sosi.bsn, g_rs_block_size, g_bsn_w); -- RSN
+ -- RSN
+ nxt_rs_sosi.bsn <= INCR_DP_BSN(i_rs_sosi.bsn, g_rs_block_size, g_bsn_w);
end if;
-- check for pending sync
if nxt_sync = '1' then
@@ -209,7 +222,8 @@ begin
nxt_state <= s_off;
end if;
- when others => -- reover from undefined state
+ -- reover from undefined state
+ when others =>
nxt_state <= s_off;
end case;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_shiftreg.vhd b/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
index 0a6c63afa81d0216065f4c21d79df4095509133b..d7d2a0fd0d2a470095ab87560e851cd1c0924827 100644
--- a/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
@@ -53,7 +53,8 @@ entity dp_shiftreg is
g_output_reg : boolean := false;
g_flush_eop : boolean := true;
g_modify_support : boolean := false;
- g_nof_words : natural := 1 -- >= 1, shift register length
+ -- >= 1, shift register length
+ g_nof_words : natural := 1
);
port (
rst : in std_logic;
@@ -71,7 +72,8 @@ entity dp_shiftreg is
end dp_shiftreg;
architecture rtl of dp_shiftreg is
- constant c_high : natural := g_nof_words - 1; -- shift stream data from 0 to g_nof_words-1
+ -- shift stream data from 0 to g_nof_words-1
+ constant c_high : natural := g_nof_words - 1;
signal prev_src_in : t_dp_siso;
signal flush : std_logic;
@@ -91,7 +93,8 @@ begin
snk_out.xon <= src_in.xon;
-- No change in ready latency
- snk_out.ready <= src_in.ready; -- no need to allow snk_out.ready when shift register is not full yet while src_in.ready is low
+ -- no need to allow snk_out.ready when shift register is not full yet while src_in.ready is low
+ snk_out.ready <= src_in.ready;
------------------------------------------------------------------------------
-- Shift register
@@ -117,7 +120,8 @@ begin
variable v_eop : std_logic := '0';
begin
flush <= '0';
- if prev_src_in.ready = '1' then -- like valid, flush must also fit to RL=1, therefore use prev_src_in.ready
+ -- like valid, flush must also fit to RL=1, therefore use prev_src_in.ready
+ if prev_src_in.ready = '1' then
flush <= func_dp_stream_arr_or(shiftreg, "EOP");
end if;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_split.vhd b/libraries/base/dp/src/vhdl/dp_split.vhd
index 19ac1fb2b5140c73dc0ba9b4000292b702788c65..5797d3b4537e5921fbc2a7a206c401ea24a5e0b2 100644
--- a/libraries/base/dp/src/vhdl/dp_split.vhd
+++ b/libraries/base/dp/src/vhdl/dp_split.vhd
@@ -74,16 +74,21 @@ use work.dp_stream_pkg.all;
entity dp_split is
generic (
- g_data_w : natural := 16; -- >= 1
- g_symbol_w : natural := 8; -- >= 1, and g_data_w/g_symbol_w must be an integer
- g_nof_symbols : natural := 8; -- nof symbols for the head frame, rest will go to the tail frame
- g_use_head_tail_src : boolean := false -- FALSE: Use src_out_arr, src_in_arr. TRUE: use separate head_src_*, tail_src_*.
+ -- >= 1
+ g_data_w : natural := 16;
+ -- >= 1, and g_data_w/g_symbol_w must be an integer
+ g_symbol_w : natural := 8;
+ -- nof symbols for the head frame, rest will go to the tail frame
+ g_nof_symbols : natural := 8;
+ -- FALSE: Use src_out_arr, src_in_arr. TRUE: use separate head_src_*, tail_src_*.
+ g_use_head_tail_src : boolean := false
);
port (
rst : in std_logic;
clk : in std_logic;
-- Static control input (connect via MM or leave open to use default)
- nof_symbols : in std_logic_vector(ceil_log2(g_nof_symbols + 1) - 1 downto 0) := TO_UVEC(g_nof_symbols, ceil_log2(g_nof_symbols + 1)); -- +1 to also support power of 2 values for g_nof_symbols
+ -- +1 to also support power of 2 values for g_nof_symbols
+ nof_symbols : in std_logic_vector(ceil_log2(g_nof_symbols + 1) - 1 downto 0) := TO_UVEC(g_nof_symbols, ceil_log2(g_nof_symbols + 1));
nof_symbols_out : out std_logic_vector(ceil_log2(g_nof_symbols + 1) - 1 downto 0);
snk_out : out t_dp_siso;
@@ -92,7 +97,8 @@ entity dp_split is
src_in_arr : in t_dp_siso_arr(0 to 1) := (others => c_dp_siso_rdy);
src_out_arr : out t_dp_sosi_arr(0 to 1);
- head_src_in : in t_dp_siso := c_dp_siso_rdy; -- We don't need to create an arrayed TYPE for src_*_arr when using this output, making things easier.
+ -- We don't need to create an arrayed TYPE for src_*_arr when using this output, making things easier.
+ head_src_in : in t_dp_siso := c_dp_siso_rdy;
head_src_out : out t_dp_sosi;
tail_src_in : in t_dp_siso := c_dp_siso_rdy;
@@ -101,14 +107,18 @@ entity dp_split is
end dp_split;
architecture rtl of dp_split is
- constant c_nof_symbols_per_data : natural := g_data_w / g_symbol_w; -- nof symbols per data
+ -- nof symbols per data
+ constant c_nof_symbols_per_data : natural := g_data_w / g_symbol_w;
constant c_empty_w : natural := ceil_log2(c_nof_symbols_per_data);
constant c_nof_symbols_w : natural := nof_symbols'length;
- constant c_symbol_cnt_w : natural := ceil_log2(g_nof_symbols + 1 + c_nof_symbols_per_data); -- total symbols count with c_nof_symbols_per_data increments, +1 to also support power of 2 value
+ -- total symbols count with c_nof_symbols_per_data increments, +1 to also support power of 2 value
+ constant c_symbol_cnt_w : natural := ceil_log2(g_nof_symbols + 1 + c_nof_symbols_per_data);
- constant c_head : natural := 0; -- head frame snk_in port number
- constant c_tail : natural := 1; -- tail frame snk_in port number
+ -- head frame snk_in port number
+ constant c_head : natural := 0;
+ -- tail frame snk_in port number
+ constant c_tail : natural := 1;
type t_state is (s_head, s_tail, s_eop);
@@ -211,23 +221,29 @@ begin
p_state : process(state, busy, sync, nof_symbols_reg, i_nof_symbols_out, symbol_cnt, i_src_out_arr, src_in_arr, next_src_buf, tail, input_empty_reg, head_empty_reg, nof_remain_reg)
variable v_input_empty : std_logic_vector(c_empty_w - 1 downto 0);
variable v_head_empty : std_logic_vector(c_empty_w - 1 downto 0);
- variable v_symbol_cnt : std_logic_vector(c_symbol_cnt_w - 1 downto 0); -- total symbols count with c_nof_symbols_per_data increments
- variable v_head_symbol_cnt : std_logic_vector(c_symbol_cnt_w - 1 downto 0); -- head symbols count
+ -- total symbols count with c_nof_symbols_per_data increments
+ variable v_symbol_cnt : std_logic_vector(c_symbol_cnt_w - 1 downto 0);
+ -- head symbols count
+ variable v_head_symbol_cnt : std_logic_vector(c_symbol_cnt_w - 1 downto 0);
variable v_cnt : std_logic_vector(c_symbol_cnt_w - 1 downto 0);
variable v_nof_from_this : natural range 0 to c_nof_symbols_per_data;
begin
-- SISO default
- i_snk_out <= c_dp_siso_rst; -- no input request
- hold_src_in <= c_dp_siso_rst; -- no input request
+ -- no input request
+ i_snk_out <= c_dp_siso_rst;
+ -- no input request
+ hold_src_in <= c_dp_siso_rst;
-- SOSI defaults
- nxt_src_out_arr(c_head) <= i_src_out_arr(c_head); -- default no output
+ -- default no output
+ nxt_src_out_arr(c_head) <= i_src_out_arr(c_head);
nxt_src_out_arr(c_head).sync <= '0';
nxt_src_out_arr(c_head).valid <= '0';
nxt_src_out_arr(c_head).sop <= '0';
nxt_src_out_arr(c_head).eop <= '0';
- nxt_src_out_arr(c_tail) <= i_src_out_arr(c_tail); -- default no output
+ -- default no output
+ nxt_src_out_arr(c_tail) <= i_src_out_arr(c_tail);
nxt_src_out_arr(c_tail).sync <= '0';
nxt_src_out_arr(c_tail).valid <= '0';
nxt_src_out_arr(c_tail).sop <= '0';
@@ -254,7 +270,8 @@ begin
v_symbol_cnt := symbol_cnt;
if next_src_buf.sop = '1' then
v_symbol_cnt := TO_UVEC(c_nof_symbols_per_data, c_symbol_cnt_w);
- nxt_nof_symbols_out <= nof_symbols_reg; -- Report the current nof symbols as status at sop of head frame
+ -- Report the current nof symbols as status at sop of head frame
+ nxt_nof_symbols_out <= nof_symbols_reg;
elsif next_src_buf.valid = '1' then
v_symbol_cnt := INCR_UVEC(v_symbol_cnt, c_nof_symbols_per_data);
end if;
@@ -266,7 +283,8 @@ begin
v_head_symbol_cnt := TO_UVEC(TO_UINT(v_symbol_cnt) - TO_UINT(v_input_empty), c_symbol_cnt_w);
end if;
- nxt_symbol_cnt <= (others => '0'); -- default reset symbol count
+ -- default reset symbol count
+ nxt_symbol_cnt <= (others => '0');
-- preserve empty information for next state
nxt_input_empty_reg <= input_empty_reg;
@@ -274,7 +292,8 @@ begin
nxt_nof_remain_reg <= nof_remain_reg;
-- preserve tail data information for next state
- nxt_tail <= tail; -- keep the tail data part in case the split is at symbol boundary and not at word boundary,
+ -- keep the tail data part in case the split is at symbol boundary and not at word boundary,
+ nxt_tail <= tail;
-- keep the sop of the tail output, the valid and eop of tail are not used.
-- pass on output
@@ -282,63 +301,93 @@ begin
case state is
when s_head =>
- nxt_input_empty_reg <= (others => '0'); -- default assume tail will end at word boundary
- nxt_head_empty_reg <= (others => '0'); -- default assume tail will start at word boundary
- nxt_nof_remain_reg <= (others => '0'); -- default assume tail will start and end at word boundary
+ -- default assume tail will end at word boundary
+ nxt_input_empty_reg <= (others => '0');
+ -- default assume tail will start at word boundary
+ nxt_head_empty_reg <= (others => '0');
+ -- default assume tail will start and end at word boundary
+ nxt_nof_remain_reg <= (others => '0');
nxt_tail <= c_dp_sosi_rst;
- nxt_symbol_cnt <= symbol_cnt; -- default keep symbol count
+ -- default keep symbol count
+ nxt_symbol_cnt <= symbol_cnt;
-- Default ready for input to head or tail dependent on nof_symbols_reg
if TO_UINT(nof_symbols_reg) /= 0 then
- i_snk_out <= src_in_arr(c_head); -- default input request for head output when head src_in_arr is ready
- hold_src_in <= src_in_arr(c_head); -- hold_src_in will flush the next_src_buf output when i_snk_out is changed to tail src_in_arr
+ -- default input request for head output when head src_in_arr is ready
+ i_snk_out <= src_in_arr(c_head);
+ -- hold_src_in will flush the next_src_buf output when i_snk_out is changed to tail src_in_arr
+ hold_src_in <= src_in_arr(c_head);
else
- i_snk_out <= src_in_arr(c_tail); -- else in special of tail only split then input request for tail output when tail src_in_arr is ready
- hold_src_in <= src_in_arr(c_tail); -- hold_src_in will flush the next_src_buf output when i_snk_out is changed to tail src_in_arr
+ -- else in special of tail only split then input request for tail output when tail src_in_arr is ready
+ i_snk_out <= src_in_arr(c_tail);
+ -- hold_src_in will flush the next_src_buf output when i_snk_out is changed to tail src_in_arr
+ hold_src_in <= src_in_arr(c_tail);
end if;
-- Act when there is valid input ready for output
if next_src_buf.valid = '1' then
- if TO_UINT(nof_symbols_reg) = 0 then -- special case with no output head, so tail src_in_arr ready is already being used
+ -- special case with no output head, so tail src_in_arr ready is already being used
+ if TO_UINT(nof_symbols_reg) = 0 then
-- no head output, begin tail output
- nxt_symbol_cnt <= (others => '0'); -- reset symbol count
- nxt_src_out_arr(c_tail) <= next_src_buf; -- output tail start data immediately
+ -- reset symbol count
+ nxt_symbol_cnt <= (others => '0');
+ -- output tail start data immediately
+ nxt_src_out_arr(c_tail) <= next_src_buf;
if next_src_buf.eop = '0' then
- nxt_state <= s_tail; -- there will be more output tail data words
- end if; -- else output tail with one data word is done, remain in state s_head
+ -- there will be more output tail data words
+ nxt_state <= s_tail;
+ -- else output tail with one data word is done, remain in state s_head
+ end if;
else
-- begin or continue output head
if TO_UINT(nof_symbols_reg) > TO_UINT(v_symbol_cnt) then
- nxt_src_out_arr(c_head) <= next_src_buf; -- there will be more output head data words
- nxt_symbol_cnt <= v_symbol_cnt; -- keep symbol count for state s_head
+ -- there will be more output head data words
+ nxt_src_out_arr(c_head) <= next_src_buf;
+ -- keep symbol count for state s_head
+ nxt_symbol_cnt <= v_symbol_cnt;
elsif TO_UINT(nof_symbols_reg) = TO_UINT(v_symbol_cnt) then
-- split at word boundary
- nxt_src_out_arr(c_head) <= next_src_buf; -- output last head
+ -- output last head
+ nxt_src_out_arr(c_head) <= next_src_buf;
nxt_src_out_arr(c_head).eop <= '1';
if next_src_buf.eop = '0' then
- i_snk_out <= src_in_arr(c_tail); -- input request for tail output start, now depends on tail src_in_arr ready
- nxt_tail.sop <= '1'; -- keep the sop via tail, the first tail data itself will arrive with the next_src_buf
+ -- input request for tail output start, now depends on tail src_in_arr ready
+ i_snk_out <= src_in_arr(c_tail);
+ -- keep the sop via tail, the first tail data itself will arrive with the next_src_buf
+ nxt_tail.sop <= '1';
nxt_state <= s_tail;
- end if; -- else there will be no output tail, remain in state s_head
+ -- else there will be no output tail, remain in state s_head
+ end if;
elsif TO_UINT(nof_symbols_reg) >= TO_UINT(v_head_symbol_cnt) then
- nxt_src_out_arr(c_head) <= next_src_buf; -- output last head, there are no symbols left for the tail
- nxt_symbol_cnt <= (others => '0'); -- reset symbol count and remain in s_head
+ -- output last head, there are no symbols left for the tail
+ nxt_src_out_arr(c_head) <= next_src_buf;
+ -- reset symbol count and remain in s_head
+ nxt_symbol_cnt <= (others => '0');
else
-- split at symbol boundary
- v_cnt := TO_UVEC(TO_UINT(v_symbol_cnt) - TO_UINT(nof_symbols_reg), c_symbol_cnt_w); -- use v_cnt to avoid truncation warning
+ -- use v_cnt to avoid truncation warning
+ v_cnt := TO_UVEC(TO_UINT(v_symbol_cnt) - TO_UINT(nof_symbols_reg), c_symbol_cnt_w);
v_head_empty := v_cnt(c_empty_w - 1 downto 0);
- nxt_src_out_arr(c_head) <= next_src_buf; -- output last head
+ -- output last head
+ nxt_src_out_arr(c_head) <= next_src_buf;
nxt_src_out_arr(c_head).empty <= RESIZE_DP_EMPTY(v_head_empty);
nxt_src_out_arr(c_head).eop <= '1';
- nxt_head_empty_reg <= v_head_empty; -- keep tail start symbol boundary
- nxt_tail <= next_src_buf; -- keep tail start data part
+ -- keep tail start symbol boundary
+ nxt_head_empty_reg <= v_head_empty;
+ -- keep tail start data part
+ nxt_tail <= next_src_buf;
nxt_tail.sop <= '1';
if next_src_buf.eop = '0' then
- i_snk_out <= src_in_arr(c_tail); -- input request for tail output start, now depends on tail src_in_arr ready
- nxt_state <= s_tail; -- there will be more output tail data words
- else -- need one tail word to output the tail part
- i_snk_out <= c_dp_siso_rst; -- no input request for at least one clock cycle, to allow change in nof_symbols_reg and for state s_eop
- nxt_tail.sync <= sync; -- force the output tail sync for the tail start
+ -- input request for tail output start, now depends on tail src_in_arr ready
+ i_snk_out <= src_in_arr(c_tail);
+ -- there will be more output tail data words
+ nxt_state <= s_tail;
+ -- need one tail word to output the tail part
+ else
+ -- no input request for at least one clock cycle, to allow change in nof_symbols_reg and for state s_eop
+ i_snk_out <= c_dp_siso_rst;
+ -- force the output tail sync for the tail start
+ nxt_tail.sync <= sync;
nxt_input_empty_reg <= v_input_empty;
nxt_nof_remain_reg <= TO_UVEC(TO_UINT(v_head_empty) - TO_UINT(v_input_empty), c_empty_w);
nxt_state <= s_eop;
@@ -349,24 +398,33 @@ begin
when s_tail =>
-- Default ready for input to tail
- i_snk_out <= src_in_arr(c_tail); -- input request for tail output
- hold_src_in <= src_in_arr(c_tail); -- input request for tail output
+ -- input request for tail output
+ i_snk_out <= src_in_arr(c_tail);
+ -- input request for tail output
+ hold_src_in <= src_in_arr(c_tail);
-- Act when there is valid input ready for output
if next_src_buf.valid = '1' then
- nxt_tail <= next_src_buf; -- keep tail data part, needed in case head had empty symbols
- v_nof_from_this := c_nof_symbols_per_data - TO_UINT(head_empty_reg); -- default output is next_src_buf in case head had no empty symbols
+ -- keep tail data part, needed in case head had empty symbols
+ nxt_tail <= next_src_buf;
+ -- default output is next_src_buf in case head had no empty symbols
+ v_nof_from_this := c_nof_symbols_per_data - TO_UINT(head_empty_reg);
nxt_src_out_arr(c_tail) <= func_dp_data_shift(tail, next_src_buf, g_symbol_w, c_nof_symbols_per_data, v_nof_from_this);
- nxt_src_out_arr(c_tail).sop <= tail.sop; -- force the output tail sop for the tail start
- nxt_src_out_arr(c_tail).sync <= tail.sop and sync; -- force the output tail sync for the tail start
+ -- force the output tail sop for the tail start
+ nxt_src_out_arr(c_tail).sop <= tail.sop;
+ -- force the output tail sync for the tail start
+ nxt_src_out_arr(c_tail).sync <= tail.sop and sync;
if next_src_buf.eop = '1' then
- i_snk_out <= c_dp_siso_rst; -- no input request for at least one clock cycle, to allow change in nof_symbols_reg and/or for state s_eop
+ -- no input request for at least one clock cycle, to allow change in nof_symbols_reg and/or for state s_eop
+ i_snk_out <= c_dp_siso_rst;
if TO_UINT(v_input_empty) >= TO_UINT(head_empty_reg) then
-- this is the last tail output, the input eop marks the tail output eop
nxt_src_out_arr(c_tail).empty <= RESIZE_DP_EMPTY(func_dp_empty_split(v_input_empty, head_empty_reg, c_nof_symbols_per_data));
nxt_state <= s_head;
- else -- need one more tail word to output the last tail part
- nxt_src_out_arr(c_tail).eop <= '0'; -- the last will be flushed from tail in state s_eop
+ -- need one more tail word to output the last tail part
+ else
+ -- the last will be flushed from tail in state s_eop
+ nxt_src_out_arr(c_tail).eop <= '0';
nxt_input_empty_reg <= v_input_empty;
nxt_nof_remain_reg <= TO_UVEC(TO_UINT(head_empty_reg) - TO_UINT(v_input_empty), c_empty_w);
nxt_state <= s_eop;
@@ -374,15 +432,19 @@ begin
end if;
end if;
- when others => -- s_eop -- no input request until last tail word has been output
+ -- s_eop -- no input request until last tail word has been output
+ when others =>
-- Act when tail output port is ready
- if src_in_arr(c_tail).ready = '1' then -- finish the last tail part
- nxt_state <= s_head; -- no input request yet, allow one more idle cycle and input request again in state s_head
+ -- finish the last tail part
+ if src_in_arr(c_tail).ready = '1' then
+ -- no input request yet, allow one more idle cycle and input request again in state s_head
+ nxt_state <= s_head;
-- shift tail output because tail will have less empty symbols than the head had
nxt_src_out_arr(c_tail) <= func_dp_data_shift_last(tail, g_symbol_w, c_nof_symbols_per_data, TO_UINT(nof_remain_reg), TO_UINT(input_empty_reg));
nxt_src_out_arr(c_tail).empty <= RESIZE_DP_EMPTY(func_dp_empty_split(input_empty_reg, head_empty_reg, c_nof_symbols_per_data));
end if;
- end case; -- CASE state
+ -- CASE state
+ end case;
-- Pass on frame level flow control
i_snk_out.xon <= func_dp_stream_arr_and(src_in_arr, "XON");
diff --git a/libraries/base/dp/src/vhdl/dp_split_reg.vhd b/libraries/base/dp/src/vhdl/dp_split_reg.vhd
index dc7a67f30eac44f750775c73f8a7c851ede10554..92e5afa0dea99adf54c78afdf9d4a7eedd629107 100644
--- a/libraries/base/dp/src/vhdl/dp_split_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_split_reg.vhd
@@ -83,13 +83,16 @@ begin
when 0 =>
mm_nof_symbols <= sla_in.wrdata(ceil_log2(g_nof_symbols + 1) - 1 downto 0);
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read Block Sync
when 0 =>
diff --git a/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd b/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
index e47aa13cbc082f269f16527fd5c4d6bcc6e09aa2..d2a42115f8a1536dcc2321645f8256cd22db8c40 100644
--- a/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
+++ b/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
@@ -39,8 +39,10 @@ use work.dp_stream_pkg.all;
entity dp_src_out_timer is
generic (
g_init_valid_delay : natural := 0;
- g_block_period : natural := 1; -- Block period >1
- g_block_len : natural := 1 -- Nof words per valid block
+ -- Block period >1
+ g_block_period : natural := 1;
+ -- Nof words per valid block
+ g_block_len : natural := 1
);
port (
rst : in std_logic;
@@ -49,7 +51,8 @@ entity dp_src_out_timer is
init_valid_delay_ref : in std_logic := '1';
snk_in : in t_dp_sosi;
- snk_out : out t_dp_siso -- rl=1
+ -- rl=1
+ snk_out : out t_dp_siso
);
end dp_src_out_timer;
@@ -126,7 +129,8 @@ begin
nxt_state <= s_init;
end if;
- when others => -- s_init
+ -- s_init
+ when others =>
nxt_state <= s_wait;
nxt_snk_out_ready <= '0';
nxt_cycle_cnt <= (others => '0');
diff --git a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
index 22b5cc127b9cc70e12ff83e8c407b8fe20242199..0345f2d0ec39a5b2a149400edcf7ca1ca3dd664f 100644
--- a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
@@ -48,35 +48,59 @@ package dp_stream_pkg is
-- This grouping is useful for functions that operate on a t_dp_sosi signal.
-- * The info fields are valid at the sop or at the eop, but typically they hold their last active value to avoid unnessary
-- toggling and to ease viewing in the wave window.
- constant c_dp_stream_bsn_w : natural := 64; -- 64 is sufficient to count blocks of data for years
- constant c_dp_stream_data_w : natural := 1024; -- 72 is sufficient for max word 8 * 9-bit. 576 supports half rate DDR4 bus data width. The current 1024 is enough for wide single clock SLVs (e.g. headers)
- constant c_dp_stream_dsp_data_w : natural := 64; -- 64 is sufficient for DSP data, including complex power accumulates
- constant c_dp_stream_empty_w : natural := 16; -- 8 is sufficient for max 256 symbols per data word, still use 16 bit to be able to count c_dp_stream_data_w in bits
- constant c_dp_stream_channel_w : natural := 32; -- 32 is sufficient for several levels of hierarchy in mapping types of streams on to channels
- constant c_dp_stream_error_w : natural := 32; -- 32 is sufficient for several levels of hierarchy in mapping error numbers, e.g. 32 different one-hot encoded errors, bit [0] = 0 = OK
-
- constant c_dp_stream_ok : natural := 0; -- SOSI err field OK value
- constant c_dp_stream_err : natural := 1; -- SOSI err field error value /= OK
-
- constant c_dp_stream_rl : natural := 1; -- SISO default data path stream ready latency RL = 1
-
- type t_dp_siso is record -- Source In or Sink Out
- ready : std_logic; -- fine cycle based flow control using ready latency RL >= 0
- xon : std_logic; -- coarse typically block based flow control using xon/xoff
+ -- 64 is sufficient to count blocks of data for years
+ constant c_dp_stream_bsn_w : natural := 64;
+ -- 72 is sufficient for max word 8 * 9-bit. 576 supports half rate DDR4 bus data width. The current 1024 is enough for wide single clock SLVs (e.g. headers)
+ constant c_dp_stream_data_w : natural := 1024;
+ -- 64 is sufficient for DSP data, including complex power accumulates
+ constant c_dp_stream_dsp_data_w : natural := 64;
+ -- 8 is sufficient for max 256 symbols per data word, still use 16 bit to be able to count c_dp_stream_data_w in bits
+ constant c_dp_stream_empty_w : natural := 16;
+ -- 32 is sufficient for several levels of hierarchy in mapping types of streams on to channels
+ constant c_dp_stream_channel_w : natural := 32;
+ -- 32 is sufficient for several levels of hierarchy in mapping error numbers, e.g. 32 different one-hot encoded errors, bit [0] = 0 = OK
+ constant c_dp_stream_error_w : natural := 32;
+
+ -- SOSI err field OK value
+ constant c_dp_stream_ok : natural := 0;
+ -- SOSI err field error value /= OK
+ constant c_dp_stream_err : natural := 1;
+
+ -- SISO default data path stream ready latency RL = 1
+ constant c_dp_stream_rl : natural := 1;
+
+ -- Source In or Sink Out
+ type t_dp_siso is record
+ -- fine cycle based flow control using ready latency RL >= 0
+ ready : std_logic;
+ -- coarse typically block based flow control using xon/xoff
+ xon : std_logic;
end record;
- type t_dp_sosi is record -- Source Out or Sink In
- sync : std_logic; -- ctrl
- bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0); -- info at sop (block sequence number)
- data : std_logic_vector(c_dp_stream_data_w - 1 downto 0); -- data
- re : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0); -- data
- im : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0); -- data
- valid : std_logic; -- ctrl
- sop : std_logic; -- ctrl
- eop : std_logic; -- ctrl
- empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0); -- info at eop
- channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0); -- info at sop
- err : std_logic_vector(c_dp_stream_error_w - 1 downto 0); -- info at eop (name field 'err' to avoid the 'error' keyword)
+ -- Source Out or Sink In
+ type t_dp_sosi is record
+ -- ctrl
+ sync : std_logic;
+ -- info at sop (block sequence number)
+ bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ -- data
+ data : std_logic_vector(c_dp_stream_data_w - 1 downto 0);
+ -- data
+ re : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0);
+ -- data
+ im : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0);
+ -- ctrl
+ valid : std_logic;
+ -- ctrl
+ sop : std_logic;
+ -- ctrl
+ eop : std_logic;
+ -- info at eop
+ empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0);
+ -- info at sop
+ channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0);
+ -- info at eop (name field 'err' to avoid the 'error' keyword)
+ err : std_logic_vector(c_dp_stream_error_w - 1 downto 0);
end record;
-- Initialise signal declarations with c_dp_stream_rst/rdy to ease the interpretation of slv fields with unused bits
@@ -243,31 +267,47 @@ package dp_stream_pkg is
-- signed data in the simulation wave window it is easier to use sign extension in the record field. Therefore TO_DP_SDATA
-- and RESIZE_DP_SDATA are defined as well.
function TO_DP_BSN( n : natural) return std_logic_vector;
- function TO_DP_DATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
- function TO_DP_SDATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
- function TO_DP_UDATA( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector; -- for re and im fields, signed data
- function TO_DP_DSP_UDATA(n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
+ -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
+ function TO_DP_DATA( n : integer) return std_logic_vector;
+ -- use integer to support 32 bit range and signed
+ function TO_DP_SDATA( n : integer) return std_logic_vector;
+ -- alias of TO_DP_DATA()
+ function TO_DP_UDATA( n : integer) return std_logic_vector;
+ -- for re and im fields, signed data
+ function TO_DP_DSP_DATA(n : integer) return std_logic_vector;
+ -- for re and im fields, unsigned data (useful to carry indices)
+ function TO_DP_DSP_UDATA(n: integer) return std_logic_vector;
function TO_DP_EMPTY( n : natural) return std_logic_vector;
function TO_DP_CHANNEL( n : natural) return std_logic_vector;
function TO_DP_ERROR( n : natural) return std_logic_vector;
function RESIZE_DP_BSN( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
- function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
- function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
+ -- set unused MSBits to '0'
+ function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector;
+ -- sign extend unused MSBits
+ function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector;
+ -- set unused MSBits to 'X'
+ function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector;
+ -- sign extend unused MSBits of re and im fields
+ function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_EMPTY( vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_CHANNEL( vec : std_logic_vector) return std_logic_vector;
function RESIZE_DP_ERROR( vec : std_logic_vector) return std_logic_vector;
- function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
- function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
- function INCR_DP_BSN( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
- function INCR_DP_CHANNEL( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
-
- function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+ -- unsigned vec(w-1:0) + dec
+ function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
+ -- signed vec(w-1:0) + dec
+ function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
+ -- signed vec(w-1:0) + dec
+ function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
+ -- unsigned vec(w-1:0) + dec
+ function INCR_DP_BSN( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
+ -- unsigned vec(w-1:0) + dec
+ function INCR_DP_CHANNEL( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector;
+
+ -- replicate seq as often as fits in c_dp_stream_data_w
+ function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector;
+ -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+ function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector;
function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
@@ -303,7 +343,8 @@ package dp_stream_pkg is
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr; -- also support slv fields
+ -- also support slv fields
+ function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr;
function func_dp_stream_arr_set(dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr;
function func_dp_stream_arr_set(dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr;
function func_dp_stream_arr_get(dp : t_dp_siso_arr; str : string) return std_logic_vector;
@@ -343,12 +384,16 @@ package dp_stream_pkg is
-- Functions to combinatorially handle channels
-- Note that the *_select and *_remove function are equivalent to dp_demux with g_combined=TRUE
- function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
+ -- select channel nr, add the channel field
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
+ -- select channel nr, skip the channel field
+ function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
+ -- skip channel nr
+ function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi;
-- Functions to combinatorially handle the error field
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
+ -- force err = 0, is OK
+ function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi;
-- Functions to combinatorially handle the BSN field
function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
@@ -370,11 +415,15 @@ package dp_stream_pkg is
-- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
-- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ -- data_order_im_re = TRUE
+ function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi;
+ -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi;
function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ -- data_order_im_re = TRUE
+ function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi;
+ -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
@@ -384,8 +433,10 @@ package dp_stream_pkg is
function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
-- Concatenate the data and complex re,im fields from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
+ -- Concat SOSI_ARR data into single SOSI
+ function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi;
+ -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr;
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
-- . data_representation = "SIGNED" treat sosi.data field as signed
@@ -400,8 +451,10 @@ package dp_stream_pkg is
function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
-- Deconcatenate data and complex re,im fields from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
+ -- Deconcat SOSI data
+ function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr;
+ -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso;
-- Return TRUE when the sosi.data of both streams matches (and is valid)
function func_dp_data_match(snk_in_a, snk_in_b: t_dp_sosi; data_w: natural) return boolean;
@@ -446,7 +499,8 @@ package body dp_stream_pkg is
signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
- ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
+ -- SLV is used as an array: nof_streams*(0..c_ready_latency)
+ ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready;
end loop;
-- Register siso.ready in c_ready_latency registers
if rising_edge(clk) then
@@ -614,11 +668,14 @@ package body dp_stream_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0);
begin
v_data := RESIZE_UVEC(data, c_vec_w);
- v_seq := v_data(seq_w - 1 downto 0); -- low data part is the v_seq
- v_vec(seq_w - 1 downto 0) := v_seq; -- keep v_seq at low part of return value
+ -- low data part is the v_seq
+ v_seq := v_data(seq_w - 1 downto 0);
+ -- keep v_seq at low part of return value
+ v_vec(seq_w - 1 downto 0) := v_seq;
if c_nof_replications > 1 then
for I in 1 to c_nof_replications - 1 loop
- v_vec((I + 1) * seq_w - 1 downto I * seq_w) := v_data((I + 1) * seq_w - 1 downto I * seq_w) xor v_seq; -- set return bit to '1' for high part data bits that do not match low part v_seq
+ -- set return bit to '1' for high part data bits that do not match low part v_seq
+ v_vec((I + 1) * seq_w - 1 downto I * seq_w) := v_data((I + 1) * seq_w - 1 downto I * seq_w) xor v_seq;
end loop;
end if;
return v_vec(c_data_w - 1 downto 0);
@@ -671,8 +728,10 @@ package body dp_stream_pkg is
begin
assert nof_symbols_from_tail < vN report "func_dp_data_shift_first : no symbols from head" severity FAILURE;
-- use the other sosi from head_sosi
- v_sosi := head_sosi; -- I = nof_symbols_from_tail = 0
- for I in 1 to vN - 1 loop -- I > 0
+ -- I = nof_symbols_from_tail = 0
+ v_sosi := head_sosi;
+ -- I > 0
+ for I in 1 to vN - 1 loop
if nof_symbols_from_tail = I then
v_sosi.data(I * symbol_w - 1 downto 0) := tail_sosi.data(vN * symbol_w - 1 downto (vN - I) * symbol_w);
end if;
@@ -694,15 +753,18 @@ package body dp_stream_pkg is
end if;
-- use sosi data from both if 0 < nof_symbols_from_this < nof_symbols_per_data (i.e. 0 < I < vN)
- if vK < nof_symbols_per_data then -- I = vK = nof_symbols_from_this < vN
+ -- I = vK = nof_symbols_from_this < vN
+ if vK < nof_symbols_per_data then
-- Implementation using variable vK directly instead of via I in a LOOP
-- IF vK > 0 THEN
-- v_sosi.data(vN*symbol_w-1 DOWNTO vK*symbol_w) := prev_sosi.data((vN-vK)*symbol_w-1 DOWNTO 0);
-- v_sosi.data( vK*symbol_w-1 DOWNTO 0) := this_sosi.data( vN *symbol_w-1 DOWNTO (vN-vK)*symbol_w);
-- END IF;
-- Implementaion using LOOP vK rather than VARIABLE vK directly as index to help synthesis and avoid potential multiplier
- v_sosi.data := prev_sosi.data; -- I = vK = nof_symbols_from_this = 0
- for I in 1 to vN - 1 loop -- I = vK = nof_symbols_from_this > 0
+ -- I = vK = nof_symbols_from_this = 0
+ v_sosi.data := prev_sosi.data;
+ -- I = vK = nof_symbols_from_this > 0
+ for I in 1 to vN - 1 loop
if vK = I then
v_sosi.data(vN * symbol_w - 1 downto I * symbol_w) := prev_sosi.data((vN - I) * symbol_w - 1 downto 0);
v_sosi.data( I * symbol_w - 1 downto 0) := this_sosi.data( vN * symbol_w - 1 downto (vN - I) * symbol_w);
@@ -782,7 +844,8 @@ package body dp_stream_pkg is
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '1');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -797,14 +860,17 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_and(v_vec); -- return AND of the masked input fields
+ -- return AND of the masked input fields
+ return vector_and(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_and;
function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '1');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -821,9 +887,11 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_and(v_vec); -- return AND of the masked input fields
+ -- return AND of the masked input fields
+ return vector_and(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_and;
@@ -840,7 +908,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_and;
function func_dp_stream_arr_or(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '0');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -855,14 +924,17 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_or(v_vec); -- return OR of the masked input fields
+ -- return OR of the masked input fields
+ return vector_or(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_or;
function func_dp_stream_arr_or(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
- variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
+ -- set default v_vec such that unmasked input have no influence on operation result
+ variable v_vec : std_logic_vector(dp'range) := (others => '0');
variable v_any : std_logic := '0';
begin
-- map siso field to v_vec
@@ -879,9 +951,11 @@ package body dp_stream_pkg is
end loop;
-- do operation on the selected record field
if v_any = '1' then
- return vector_or(v_vec); -- return OR of the masked input fields
+ -- return OR of the masked input fields
+ return vector_or(v_vec);
else
- return '0'; -- return '0' if no input was masked
+ -- return '0' if no input was masked
+ return '0';
end if;
end func_dp_stream_arr_or;
@@ -899,8 +973,10 @@ package body dp_stream_pkg is
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
- variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
- variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
+ -- default
+ variable v_dp : t_dp_siso_arr(dp'range) := dp;
+ -- map to ensure same range as for dp
+ variable v_slv : std_logic_vector(dp'range) := slv;
begin
for I in dp'range loop
if str = "READY" then v_dp(I).ready := v_slv(I);
@@ -912,8 +988,10 @@ package body dp_stream_pkg is
end func_dp_stream_arr_set;
function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- default
- variable v_slv : std_logic_vector(dp'range) := slv(dp'range); -- map to ensure same range as for dp
+ -- default
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
+ -- map to ensure same range as for dp
+ variable v_slv : std_logic_vector(dp'range) := slv(dp'range);
begin
for I in dp'range loop
-- use v_slv(I) to set individual sl field
@@ -1111,29 +1189,40 @@ package body dp_stream_pkg is
-- Functions to combinatorially hold the data fields and to set or reset the info and control fields in an sosi array
function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- v_dp := func_dp_stream_arr_set_info( v_dp, info); -- set sosi info
- v_dp := func_dp_stream_arr_set_control(v_dp, ctrl); -- set sosi ctrl
+ -- set sosi info
+ v_dp := func_dp_stream_arr_set_info( v_dp, info);
+ -- set sosi ctrl
+ v_dp := func_dp_stream_arr_set_control(v_dp, ctrl);
return v_dp;
end func_dp_stream_arr_combine_data_info_ctrl;
function func_dp_stream_arr_set_info(dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- set sosi info
- v_dp(I).bsn := info.bsn; -- sop
- v_dp(I).channel := info.channel; -- sop
- v_dp(I).empty := info.empty; -- eop
- v_dp(I).err := info.err; -- eop
+ -- set sosi info
+ for I in dp'range loop
+ -- sop
+ v_dp(I).bsn := info.bsn;
+ -- sop
+ v_dp(I).channel := info.channel;
+ -- eop
+ v_dp(I).empty := info.empty;
+ -- eop
+ v_dp(I).err := info.err;
end loop;
return v_dp;
end func_dp_stream_arr_set_info;
function func_dp_stream_arr_set_control(dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- set sosi control
+ -- set sosi control
+ for I in dp'range loop
v_dp(I).valid := ctrl.valid;
v_dp(I).sop := ctrl.sop;
v_dp(I).eop := ctrl.eop;
@@ -1143,9 +1232,11 @@ package body dp_stream_pkg is
end func_dp_stream_arr_set_control;
function func_dp_stream_arr_reset_control(dp : t_dp_sosi_arr) return t_dp_sosi_arr is
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
- for I in dp'range loop -- reset sosi control
+ -- reset sosi control
+ for I in dp'range loop
v_dp(I).valid := '0';
v_dp(I).sop := '0';
v_dp(I).eop := '0';
@@ -1155,7 +1246,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_reset_control;
function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi is
- variable v_dp : t_dp_sosi := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi := dp;
begin
-- reset sosi control
v_dp.valid := '0';
@@ -1167,7 +1259,8 @@ package body dp_stream_pkg is
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
- variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0'); -- init max v_bsn with minimum value
+ -- init max v_bsn with minimum value
+ variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0');
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1186,7 +1279,8 @@ package body dp_stream_pkg is
end func_dp_stream_arr_bsn_max;
function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
- variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1'); -- init min v_bsn with maximum value
+ -- init min v_bsn with maximum value
+ variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1');
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1207,7 +1301,8 @@ package body dp_stream_pkg is
-- Function to copy the BSN number of one valid stream to all other streams.
function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
- variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
+ -- hold sosi data
+ variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
if mask(I) = '1' then
@@ -1265,10 +1360,12 @@ package body dp_stream_pkg is
end func_dp_stream_bsn_set;
function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
- variable v_rec : t_dp_sosi := data; -- Sosi data fields
+ -- Sosi data fields
+ variable v_rec : t_dp_sosi := data;
begin
-- Combine sosi data with the sosi info fields
- v_rec.sync := info.sync and data.sop; -- force sync only active at data.sop
+ -- force sync only active at data.sop
+ v_rec.sync := info.sync and data.sop;
v_rec.bsn := info.bsn;
v_rec.channel := info.channel;
v_rec.empty := info.empty;
@@ -1280,7 +1377,8 @@ package body dp_stream_pkg is
variable v_rec : t_dp_sosi_integer;
begin
v_rec.sync := slv_sosi.sync;
- v_rec.bsn := TO_UINT(slv_sosi.bsn(30 downto 0)); -- NATURAL'width = 31 bit
+ -- NATURAL'width = 31 bit
+ v_rec.bsn := TO_UINT(slv_sosi.bsn(30 downto 0));
v_rec.data := TO_SINT(slv_sosi.data(w - 1 downto 0));
v_rec.re := TO_SINT(slv_sosi.re(w - 1 downto 0));
v_rec.im := TO_SINT(slv_sosi.im(w - 1 downto 0));
@@ -1398,7 +1496,8 @@ package body dp_stream_pkg is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
- v_dp_arr(i) := func_dp_stream_complex_to_data(dp_arr(i), data_w, nof_data, data_order_im_re); -- nof_data per stream is 1
+ -- nof_data per stream is 1
+ v_dp_arr(i) := func_dp_stream_complex_to_data(dp_arr(i), data_w, nof_data, data_order_im_re);
end loop;
return v_dp_arr;
end;
@@ -1417,7 +1516,8 @@ package body dp_stream_pkg is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
- v_dp_arr(i) := func_dp_stream_data_to_complex(dp_arr(i), data_w, nof_data, data_order_im_re); -- nof_data per stream is 1
+ -- nof_data per stream is 1
+ v_dp_arr(i) := func_dp_stream_data_to_complex(dp_arr(i), data_w, nof_data, data_order_im_re);
end loop;
return v_dp_arr;
end;
@@ -1448,7 +1548,8 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
+ -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is
variable v_snk_out_arr : t_dp_siso_arr(nof_streams - 1 downto 0);
begin
for i in v_snk_out_arr'range loop
@@ -1463,7 +1564,8 @@ package body dp_stream_pkg is
constant c_compl_out_w : natural := out_w / 2;
variable v_src_out : t_dp_sosi := snk_in;
variable v_in_data : std_logic_vector(in_w - 1 downto 0);
- variable v_out_data : std_logic_vector(out_w - 1 downto 0) := (others => '0'); -- default set sosi.data to 0
+ -- default set sosi.data to 0
+ variable v_out_data : std_logic_vector(out_w - 1 downto 0) := (others => '0');
begin
v_src_out := snk_in;
v_src_out.data := (others => '0');
@@ -1471,10 +1573,12 @@ package body dp_stream_pkg is
v_src_out.im := (others => '0');
for i in 0 to nof_data - 1 loop
v_in_data := snk_in.data((i + 1) * in_w - 1 downto i * in_w);
- if data_representation = "UNSIGNED" then -- treat data as unsigned
+ -- treat data as unsigned
+ if data_representation = "UNSIGNED" then
v_out_data := RESIZE_UVEC(v_in_data, out_w);
else
- if data_representation = "SIGNED" then -- treat data as signed
+ -- treat data as signed
+ if data_representation = "SIGNED" then
v_out_data := RESIZE_SVEC(v_in_data, out_w);
else
-- treat data as complex
@@ -1532,7 +1636,8 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
+ -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is
begin
return src_out_arr(0);
end;
diff --git a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
index 82eb03aa00a6e8cd9e06eea8c36635d510a6a146..c5e10893aaca0298cfbca369f8966e6a1cdf1130 100644
--- a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
+++ b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
@@ -83,8 +83,10 @@ use work.dp_components_pkg.all;
entity dp_strobe_total_count is
generic (
g_mm_w : natural := c_word_w;
- g_nof_counts : natural := 1; -- actual nof counts, <= c_nof_counts_max
- g_count_w : natural := c_longword_w; -- actual count width, max is c_longword_w due to two mm word width
+ -- actual nof counts, <= c_nof_counts_max
+ g_nof_counts : natural := 1;
+ -- actual count width, max is c_longword_w due to two mm word width
+ g_count_w : natural := c_longword_w;
g_clip : boolean := true
);
port (
@@ -112,7 +114,8 @@ architecture rtl of dp_strobe_total_count is
-- Define the size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => c_dp_strobe_total_count_reg_adr_w,
- dat_w => g_mm_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => g_mm_w,
nof_dat => c_dp_strobe_total_count_reg_nof_words,
init_sl => '0');
@@ -230,13 +233,17 @@ begin
-- Register mapping
gen_cnt : for I in 0 to g_nof_counts - 1 generate
gen_reg_32b : if g_count_w <= g_mm_w generate
- rd_reg((2 * I + 1) * g_mm_w - 1 downto (2 * I + 0) * g_mm_w) <= RESIZE_UVEC(hold_cnt_arr(I), g_mm_w); -- low part
- rd_reg((2 * I + 2) * g_mm_w - 1 downto (2 * I + 1) * g_mm_w) <= (others => '0'); -- high part (not used)
+ -- low part
+ rd_reg((2 * I + 1) * g_mm_w - 1 downto (2 * I + 0) * g_mm_w) <= RESIZE_UVEC(hold_cnt_arr(I), g_mm_w);
+ -- high part (not used)
+ rd_reg((2 * I + 2) * g_mm_w - 1 downto (2 * I + 1) * g_mm_w) <= (others => '0');
end generate;
gen_reg_64b : if g_count_w > g_mm_w generate
- rd_reg((2 * I + 1) * g_mm_w - 1 downto (2 * I + 0) * g_mm_w) <= hold_cnt_arr(I)(g_mm_w - 1 downto 0); -- low part
- rd_reg((2 * I + 2) * g_mm_w - 1 downto (2 * I + 1) * g_mm_w) <= RESIZE_UVEC(hold_cnt_arr(I)(g_count_w - 1 downto g_mm_w), g_mm_w); -- high part
+ -- low part
+ rd_reg((2 * I + 1) * g_mm_w - 1 downto (2 * I + 0) * g_mm_w) <= hold_cnt_arr(I)(g_mm_w - 1 downto 0);
+ -- high part
+ rd_reg((2 * I + 2) * g_mm_w - 1 downto (2 * I + 1) * g_mm_w) <= RESIZE_UVEC(hold_cnt_arr(I)(g_count_w - 1 downto g_mm_w), g_mm_w);
end generate;
end generate;
@@ -260,7 +267,9 @@ begin
-- MM registers in st_clk domain
reg_wr_arr => OPEN,
reg_rd_arr => OPEN,
- in_reg => rd_reg, -- read only
- out_reg => open -- no write
+ -- read only
+ in_reg => rd_reg,
+ -- no write
+ out_reg => open
);
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_switch.vhd b/libraries/base/dp/src/vhdl/dp_switch.vhd
index e11631038321181d17ceb3c567f5fb6f25d21a0b..d2120053dc775b5d5ba4f5315e928a3374c6a403 100644
--- a/libraries/base/dp/src/vhdl/dp_switch.vhd
+++ b/libraries/base/dp/src/vhdl/dp_switch.vhd
@@ -41,9 +41,12 @@ use work.dp_stream_pkg.all;
entity dp_switch is
generic (
- g_nof_inputs : natural; -- Number of inputs
- g_default_enabled : natural := 0; -- This input number 0..g_nof_inputs-1 will be enabled by default
- g_use_fifo : boolean := false; -- This and the generics below are forwarded to dp_mux only
+ -- Number of inputs
+ g_nof_inputs : natural;
+ -- This input number 0..g_nof_inputs-1 will be enabled by default
+ g_default_enabled : natural := 0;
+ -- This and the generics below are forwarded to dp_mux only
+ g_use_fifo : boolean := false;
g_bsn_w : natural := 16;
g_data_w : natural := 16;
g_empty_w : natural := 1;
@@ -54,7 +57,8 @@ entity dp_switch is
g_use_in_channel : boolean := false;
g_use_error : boolean := false;
g_use_sync : boolean := false;
- g_fifo_af_margin : natural := 4; -- Nof words below max (full) at which fifo is considered almost full
+ -- Nof words below max (full) at which fifo is considered almost full
+ g_fifo_af_margin : natural := 4;
g_fifo_size : natural := 1024;
g_fifo_fill : natural := 0
);
@@ -121,7 +125,8 @@ begin
in_sosi => snk_in_arr(i),
in_siso => snk_out_arr(i),
-- Frame out
- out_siso => xonoff_src_in_arr(i), -- flush control done by dp_mux.snk_out_arr
+ -- flush control done by dp_mux.snk_out_arr
+ out_siso => xonoff_src_in_arr(i),
out_sosi => xonoff_src_out_arr(i)
);
end generate;
@@ -146,8 +151,10 @@ begin
------------------------------------------------------------------------------
u_dp_mux : entity work.dp_mux
generic map (
- g_mode => 4, -- Use sel_ctrl
- g_sel_ctrl_invert => false, -- Dont invert, data is already reverse mapped from DOWNTO >> TO arrays.
+ -- Use sel_ctrl
+ g_mode => 4,
+ -- Dont invert, data is already reverse mapped from DOWNTO >> TO arrays.
+ g_sel_ctrl_invert => false,
g_nof_input => g_nof_inputs,
g_use_fifo => g_use_fifo,
g_bsn_w => g_bsn_w,
diff --git a/libraries/base/dp/src/vhdl/dp_sync_checker.vhd b/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
index e17d04d777c8dd8c0464dc8658e8a8d563dc6122..c225ae74c311a33b42e4a9187b45d944ca28aa31 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
@@ -127,7 +127,8 @@ begin
-- Detect SYNC that is too early
if (snk_in.sync = '1' and r.cnt_sop < c_nof_blk_per_sync and r.wait_for_next_sync = '0') then
v.sync_too_early := '1';
- v.snk_in.sync := '0'; -- Remove sync from input.
+ -- Remove sync from input.
+ v.snk_in.sync := '0';
v.nof_early_syncs := r.nof_early_syncs + 1;
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_sync_insert.vhd b/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
index d1da545d1af2c068b214a8ac38babc8c2b7865da..c5961762a3b0fe2c8d3fbfefdcf730609da8501e 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
@@ -56,7 +56,8 @@ entity dp_sync_insert is
end dp_sync_insert;
architecture rtl of dp_sync_insert is
- type t_reg is record -- local registers
+ -- local registers
+ type t_reg is record
data_cnt : natural range 0 to g_nof_data_per_blk;
blk_cnt : natural range 0 to g_nof_blk_per_sync;
sync_out_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
diff --git a/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd b/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
index d5d54d2a23d6e683fe8936711552399d3e5bec2f..61bb35ae3260abf330f1a98dc69154d8868462e4 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
@@ -66,7 +66,8 @@ entity dp_sync_insert_v2 is
end dp_sync_insert_v2;
architecture rtl of dp_sync_insert_v2 is
- type t_reg is record -- local registers
+ -- local registers
+ type t_reg is record
blk_cnt : natural range 0 to g_nof_blk_per_sync;
nof_blk_per_sync : natural range 0 to g_nof_blk_per_sync;
out_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
diff --git a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
index 60fee25c8b2c1db2cef921d309acde526dcd4587..646dad1cb2cd47406dcc3245bc3c0345fc4ee6db 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
@@ -55,18 +55,24 @@ entity dp_sync_recover is
dp_clk : in std_logic;
in_sosi : in t_dp_sosi := c_dp_sosi_rst;
- recover_val : in std_logic; -- valid of the out_sosi that needs to be recoverd.
- restart : in std_logic := '0'; -- pulse to restart bsn counter
+ -- valid of the out_sosi that needs to be recoverd.
+ recover_val : in std_logic;
+ -- pulse to restart bsn counter
+ restart : in std_logic := '0';
out_sosi : out t_dp_sosi
);
end dp_sync_recover;
architecture rtl of dp_sync_recover is
- type t_reg is record -- local registers
- bsn_at_sync : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0); -- bsn to store at which to generate a sync pulse.
- bsn_before_restart : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0); -- bsn to store at which to restart te bsn counter.
- bsn_at_restart : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0); -- bsn to store inital bsn after (re)start.
+ -- local registers
+ type t_reg is record
+ -- bsn to store at which to generate a sync pulse.
+ bsn_at_sync : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ -- bsn to store at which to restart te bsn counter.
+ bsn_before_restart : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ -- bsn to store inital bsn after (re)start.
+ bsn_at_restart : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
restart : std_logic;
started : std_logic;
data_cnt : natural range 0 to g_nof_data_per_block;
@@ -99,35 +105,44 @@ begin
v.out_sosi.valid := recover_val;
v.out_sosi.bsn := r.out_sosi.bsn;
- if r.restart = '0' and restart = '0' then -- keep track of last bsn before restart
+ -- keep track of last bsn before restart
+ if r.restart = '0' and restart = '0' then
v.bsn_before_restart := in_sosi.bsn;
end if;
- if in_sosi.sync = '1' then -- capture bsn at sync
+ -- capture bsn at sync
+ if in_sosi.sync = '1' then
v.bsn_at_sync := in_sosi.bsn;
end if;
if recover_val = '1' then
v.data_cnt := r.data_cnt + 1;
- if r.data_cnt = 0 then -- generate sop + bsn
+ -- generate sop + bsn
+ if r.data_cnt = 0 then
v.out_sosi.sop := '1';
- v.out_bsn := std_logic_vector(unsigned(r.out_bsn) + 1); -- increase block counter
+ -- increase block counter
+ v.out_bsn := std_logic_vector(unsigned(r.out_bsn) + 1);
v.out_sosi.bsn := r.out_bsn;
- if r.out_bsn = r.bsn_at_sync then -- generate sync pulse
+ -- generate sync pulse
+ if r.out_bsn = r.bsn_at_sync then
v.out_sosi.sync := '1';
end if;
end if;
- if r.data_cnt = g_nof_data_per_block - 1 then -- reset data counter and generate eop.
+ -- reset data counter and generate eop.
+ if r.data_cnt = g_nof_data_per_block - 1 then
v.data_cnt := 0;
v.out_sosi.eop := '1';
end if;
end if;
-- overwrite v.out_bsn if a restart has occurd.
- if restart = '1' then -- Capture BSN at restart
- v.bsn_at_restart := in_sosi.bsn; -- initial bsn value
+ -- Capture BSN at restart
+ if restart = '1' then
+ -- initial bsn value
+ v.bsn_at_restart := in_sosi.bsn;
v.restart := '1';
- if r.started = '0' or r.out_sosi.bsn = r.bsn_before_restart then -- if restarted for the first time or if the restart should happen at the current bsn use the in_sosi.bsn immidiatly.
+ -- if restarted for the first time or if the restart should happen at the current bsn use the in_sosi.bsn immidiatly.
+ if r.started = '0' or r.out_sosi.bsn = r.bsn_before_restart then
v.started := '1';
v.restart := '0';
v.out_bsn := in_sosi.bsn;
@@ -135,7 +150,8 @@ begin
end if;
-- If the latency is larger than one block, it is needed wait with the restart until the last block has arrived.
- if r.restart = '1' and r.out_sosi.bsn = r.bsn_before_restart then -- set bsn to initial value after restart
+ -- set bsn to initial value after restart
+ if r.restart = '1' and r.out_sosi.bsn = r.bsn_before_restart then
v.out_bsn := r.bsn_at_restart;
v.restart := '0';
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_tail_remove.vhd b/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
index d27a5f17436bb879a14cf9b7a40a9b01b9df2dc0..5950a43acb0d1fa8e21314d43b8bfa73f4dd5310 100644
--- a/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
@@ -39,7 +39,8 @@ entity dp_tail_remove is
generic (
g_data_w : natural;
g_symbol_w : natural;
- g_nof_symbols : natural -- Nof symbols to be stripped from end of the packet,
+ -- Nof symbols to be stripped from end of the packet,
+ g_nof_symbols : natural
-- and accounting for the nof empty symbols.
);
port (
@@ -55,7 +56,8 @@ entity dp_tail_remove is
end dp_tail_remove;
architecture str of dp_tail_remove is
- constant c_output_reg : boolean := true; -- register dp_shiftreg output to ease timing closure
+ -- register dp_shiftreg output to ease timing closure
+ constant c_output_reg : boolean := true;
constant c_tail_nof_words : natural := ceil_div(g_nof_symbols * g_symbol_w, g_data_w);
-- The number of words we need to buffer equals c_tail_nof_words, plus one extra because we need to move the EOP to
@@ -84,8 +86,10 @@ begin
cur_shiftreg_inputs => rd_sosi_arr,
new_shiftreg_inputs => wr_sosi_arr,
-- ST source
- src_in => src_in, -- We correct the stream via new_shiftreg_inputs, so
- src_out => src_out -- the shiftreg sources everything but the tail.
+ -- We correct the stream via new_shiftreg_inputs, so
+ src_in => src_in,
+ -- the shiftreg sources everything but the tail.
+ src_out => src_out
);
p_shift: process(rd_sosi_arr)
diff --git a/libraries/base/dp/src/vhdl/dp_throttle.vhd b/libraries/base/dp/src/vhdl/dp_throttle.vhd
index 0c1ab51619cf7a0d151571c9c38778bfd870ed3f..2203f1855fb3e3f6c1ab29c667559b4d9aabab2c 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle.vhd
@@ -26,8 +26,10 @@ use work.dp_stream_pkg.all;
entity dp_throttle is
generic (
- g_dc_period : natural := 100; -- provides a resolution of 1% (1/100..100/100)
- g_throttle_valid : boolean := false -- FALSE: Stream passes through, snk_out.ready is AND'ed with pulse
+ -- provides a resolution of 1% (1/100..100/100)
+ g_dc_period : natural := 100;
+ -- FALSE: Stream passes through, snk_out.ready is AND'ed with pulse
+ g_throttle_valid : boolean := false
-- TRUE : Throttles src_out.valid instead of snk_out.ready; Onther entity I/O unused.
);
port (
@@ -61,11 +63,14 @@ begin
u_common_duty_cycle : entity common_lib.common_duty_cycle
generic map (
- g_rst_lvl => '0', -- Start with '0' on the output so our connected sink is not maxed out after reset
- g_dis_lvl => '0', -- Don't care - dc_out_en is not used.
+ -- Start with '0' on the output so our connected sink is not maxed out after reset
+ g_rst_lvl => '0',
+ -- Don't care - dc_out_en is not used.
+ g_dis_lvl => '0',
g_act_lvl => '1',
g_per_cnt => g_dc_period,
- g_act_cnt => 0 -- After init, stay in idle state until we write a new DC value
+ -- After init, stay in idle state until we write a new DC value
+ g_act_cnt => 0
)
port map (
rst => rst,
@@ -73,7 +78,8 @@ begin
dc_act_cnt => throttle,
- dc_out_en => '1', -- We can also disable the output by writing zero to dc_act_cnt.
+ -- We can also disable the output by writing zero to dc_act_cnt.
+ dc_out_en => '1',
dc_out => dc_out
);
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd b/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
index 3d755e41eef38b65af816033f904fbca74f1ee5f..469da70efb8b76f535b99166b543d134b9d71d6a 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
@@ -37,8 +37,10 @@ entity dp_throttle_reg is
st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso := c_mem_miso_rst; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso := c_mem_miso_rst;
throttle : out std_logic_vector(ceil_log2(g_dc_period + 1) - 1 downto 0)
);
@@ -48,7 +50,8 @@ architecture rtl of dp_throttle_reg is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 1,
init_sl => '0');
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd b/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
index dc6307419b85697a32049843aa797a4c6cff1c9c..78143e58f3cf6beaa90b5aaaf90722a7fe608ad9 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
@@ -35,10 +35,14 @@ use work.dp_stream_pkg.all;
entity dp_throttle_xon is
generic (
- g_restart_at_sync : boolean := false; -- if true restart xon control at each snk_in_sync, else and start at first valid and never restart
- g_block_size : natural := 100; -- number of valid data per block marked by sop and eop
- g_nof_block_on : natural := 10; -- number of blocks that snk_out.xon is active
- g_nof_clk_off : natural := 10 -- number of clock cycles that snk_out.xon is kept inactive
+ -- if true restart xon control at each snk_in_sync, else and start at first valid and never restart
+ g_restart_at_sync : boolean := false;
+ -- number of valid data per block marked by sop and eop
+ g_block_size : natural := 100;
+ -- number of blocks that snk_out.xon is active
+ g_nof_block_on : natural := 10;
+ -- number of clock cycles that snk_out.xon is kept inactive
+ g_nof_clk_off : natural := 10
);
port (
rst : in std_logic;
@@ -53,7 +57,8 @@ entity dp_throttle_xon is
end dp_throttle_xon;
architecture rtl of dp_throttle_xon is
- constant c_nof_block_on : natural := g_nof_block_on - 1; -- adjust by -1 to account for that first block already appears at cnt = 0
+ -- adjust by -1 to account for that first block already appears at cnt = 0
+ constant c_nof_block_on : natural := g_nof_block_on - 1;
constant c_nof_valid_on : natural := c_nof_block_on * g_block_size;
signal cnt : natural range 0 to largest(g_block_size * c_nof_block_on, g_nof_clk_off);
@@ -61,10 +66,13 @@ architecture rtl of dp_throttle_xon is
signal xon : std_logic;
signal nxt_xon : std_logic;
begin
- snk_out.ready <= src_in.ready; -- pass on ready
- snk_out.xon <= src_in.xon and xon; -- control xon
+ -- pass on ready
+ snk_out.ready <= src_in.ready;
+ -- control xon
+ snk_out.xon <= src_in.xon and xon;
- src_out <= snk_in; -- pass on sosi
+ -- pass on sosi
+ src_out <= snk_in;
p_clk : process(rst, clk)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_unfolder.vhd b/libraries/base/dp/src/vhdl/dp_unfolder.vhd
index 3df7cc4c185dbc765a534f033d12a27592ae1ab5..639c5a986bd605c201e04d3298bcfac06eaee1e9 100644
--- a/libraries/base/dp/src/vhdl/dp_unfolder.vhd
+++ b/libraries/base/dp/src/vhdl/dp_unfolder.vhd
@@ -39,12 +39,18 @@ use dp_lib.dp_stream_pkg.all;
entity dp_unfolder is
generic (
- g_nof_inputs : natural; -- Number of inputs
- g_nof_unfolds : natural := 0; -- Number of times to unfold
- g_output_block_size : natural := 0; -- >0: Create SOP/EOP tagged output blocks of this size.
- g_fwd_sync_bsn : boolean := false; -- TRUE: forwards (stored) input Sync+BSN (from snk_in_arr(0)) to all output streams
- g_use_channel : boolean := false; -- TRUE: Also fold the channel field
- g_output_align : boolean := true -- TRUE: Use pipeline stages to align the outputs
+ -- Number of inputs
+ g_nof_inputs : natural;
+ -- Number of times to unfold
+ g_nof_unfolds : natural := 0;
+ -- >0: Create SOP/EOP tagged output blocks of this size.
+ g_output_block_size : natural := 0;
+ -- TRUE: forwards (stored) input Sync+BSN (from snk_in_arr(0)) to all output streams
+ g_fwd_sync_bsn : boolean := false;
+ -- TRUE: Also fold the channel field
+ g_use_channel : boolean := false;
+ -- TRUE: Use pipeline stages to align the outputs
+ g_output_align : boolean := true
);
port (
rst : in std_logic;
@@ -152,7 +158,8 @@ begin
gen_dp_unfolder: if g_nof_unfolds > 1 generate
u_dp_unfolder : dp_unfolder
generic map (
- g_nof_inputs => c_nof_demuxes * 2, -- Next stage has all our demux outputs as inputs
+ -- Next stage has all our demux outputs as inputs
+ g_nof_inputs => c_nof_demuxes * 2,
g_nof_unfolds => g_nof_unfolds - 1,
g_output_block_size => g_output_block_size,
g_fwd_sync_bsn => g_fwd_sync_bsn,
@@ -238,8 +245,10 @@ begin
rst => rst,
clk => clk,
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in_arr(0), -- original snk_in info
+ -- delayed snk_in data
+ data_snk_in => dp_block_gen_src_out_arr(i),
+ -- original snk_in info
+ info_snk_in => snk_in_arr(0),
src_in => c_dp_siso_rdy,
src_out => src_out_arr(i)
diff --git a/libraries/base/dp/src/vhdl/dp_unframe.vhd b/libraries/base/dp/src/vhdl/dp_unframe.vhd
index 2e9d0f5b21e5c852c17edee51b699a5beabc3431..38ce305e280a7848bed5a0aef42dc139b8532f8f 100644
--- a/libraries/base/dp/src/vhdl/dp_unframe.vhd
+++ b/libraries/base/dp/src/vhdl/dp_unframe.vhd
@@ -65,8 +65,10 @@ entity dp_unframe is
in_eof : in std_logic;
out_fsn : out std_logic_vector(g_fsn_w - 1 downto 0);
- out_sync : out std_logic; -- LOFAR style sync before sof
- sof_sync : out std_logic; -- DP style sync at sof
+ -- LOFAR style sync before sof
+ out_sync : out std_logic;
+ -- DP style sync at sof
+ sof_sync : out std_logic;
out_dat : out std_logic_vector(g_dat_w - 1 downto 0);
out_val : out std_logic;
out_sof : out std_logic;
@@ -97,7 +99,8 @@ architecture rtl of dp_unframe is
-- Hold input sof and then adjust it to next input val to put out_sof on first valid out_dat word (in_sof is on fsn)
signal sof_hld : std_logic;
signal nxt_sof_hld : std_logic;
- signal sync_hld : std_logic; -- hold input sync from FSN to adjust to output sof as sof_sync
+ -- hold input sync from FSN to adjust to output sof as sof_sync
+ signal sync_hld : std_logic;
signal nxt_sync_hld : std_logic;
signal i_out_fsn : std_logic_vector(out_fsn'range);
@@ -188,13 +191,18 @@ begin
p_output: process(in_dat_reg, in_val_reg, sync_hld, sof_hld, in_sof_reg, in_eof_reg, dat_adj, val_adj, sof_adj, sync_adj, i_out_dat, i_out_fsn, i_out_err)
begin
- nxt_sof_hld <= sof_hld; -- hold input sof to first input dat
- nxt_sync_hld <= sync_hld; -- hold input sync to first input dat
- nxt_out_fsn <= i_out_fsn; -- hold out_fsn during a frame
+ -- hold input sof to first input dat
+ nxt_sof_hld <= sof_hld;
+ -- hold input sync to first input dat
+ nxt_sync_hld <= sync_hld;
+ -- hold out_fsn during a frame
+ nxt_out_fsn <= i_out_fsn;
nxt_out_sync <= '0';
- nxt_out_err <= i_out_err; -- hold out_err until next sof
+ -- hold out_err until next sof
+ nxt_out_err <= i_out_err;
- nxt_dat_adj <= dat_adj; -- delay out_dat, val, sof to meet out_eof
+ -- delay out_dat, val, sof to meet out_eof
+ nxt_dat_adj <= dat_adj;
nxt_val_adj <= val_adj;
nxt_sof_adj <= sof_adj;
nxt_sync_adj <= sync_adj;
@@ -212,28 +220,42 @@ begin
nxt_val_adj <= '0';
nxt_sof_adj <= '0';
nxt_sync_adj <= '0';
- nxt_out_dat <= dat_adj; -- dat output
- nxt_out_val <= val_adj; -- val output
- nxt_out_sof <= sof_adj; -- sof output
- nxt_sof_sync <= sync_adj; -- sync output
+ -- dat output
+ nxt_out_dat <= dat_adj;
+ -- val output
+ nxt_out_val <= val_adj;
+ -- sof output
+ nxt_out_sof <= sof_adj;
+ -- sync output
+ nxt_sof_sync <= sync_adj;
if in_sof_reg = '1' then
nxt_sof_hld <= '1';
- nxt_sync_hld <= in_dat_reg(out_fsn'high); -- sync pulse
- nxt_out_fsn <= in_dat_reg(out_fsn'range); -- new fsn
- nxt_out_sync <= in_dat_reg(out_fsn'high); -- sync pulse
- nxt_out_err <= '0'; -- clear previous err
+ -- sync pulse
+ nxt_sync_hld <= in_dat_reg(out_fsn'high);
+ -- new fsn
+ nxt_out_fsn <= in_dat_reg(out_fsn'range);
+ -- sync pulse
+ nxt_out_sync <= in_dat_reg(out_fsn'high);
+ -- clear previous err
+ nxt_out_err <= '0';
elsif sof_hld = '1' then
- nxt_val_adj <= '1'; -- val adjust
- nxt_sof_adj <= '1'; -- sof adjust
- nxt_sync_adj <= sync_hld; -- sync adjust
- elsif in_eof_reg = '1' then -- eof output
+ -- val adjust
+ nxt_val_adj <= '1';
+ -- sof adjust
+ nxt_sof_adj <= '1';
+ -- sync adjust
+ nxt_sync_adj <= sync_hld;
+ -- eof output
+ elsif in_eof_reg = '1' then
nxt_out_eof <= '1';
- nxt_out_err <= '0'; -- set err based on brc, already valid at out_eof
+ -- set err based on brc, already valid at out_eof
+ nxt_out_err <= '0';
if in_dat_reg /= c_brc_ok then
nxt_out_err <= '1';
end if;
else
- nxt_val_adj <= '1'; -- val adjust
+ -- val adjust
+ nxt_val_adj <= '1';
end if;
end if;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
index a12132a9ea42961ed3a9147d985556f51829be0d..672f1faeacf987ddc41389430f5f0bc5a0fbd2f8 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
@@ -58,19 +58,24 @@ entity dp_wideband_sp_arr_scope is
g_use_sclk : boolean := true;
g_complex : boolean := false;
g_nof_streams : natural := 4;
- g_wideband_factor : natural := 4; -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian : boolean := false; -- When true sp_sosi_arr[].data[3:0] = sample[t0,t1,t2,t3], else when false : sp_sosi_arr[].data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w : natural := 8 -- Actual g_dat_w width of the data field or g_dat_w/2 width in case of the re field, im field
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor : natural := 4;
+ -- When true sp_sosi_arr[].data[3:0] = sample[t0,t1,t2,t3], else when false : sp_sosi_arr[].data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian : boolean := false;
+ -- Actual g_dat_w width of the data field or g_dat_w/2 width in case of the re field, im field
+ g_dat_w : natural := 8
);
port (
-- Digital processing clk
DCLK : in std_logic := '0';
-- Sampling clk, for simulation only
- SCLK : in std_logic := '0'; -- SCLK rate = g_wideband_factor * DCLK rate
+ -- SCLK rate = g_wideband_factor * DCLK rate
+ SCLK : in std_logic := '0';
-- Streaming input samples for g_nof_streams
- sp_sosi_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- = [3:0] = Signal Paths [D,C,B,A]
+ -- = [3:0] = Signal Paths [D,C,B,A]
+ sp_sosi_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-- Scope output samples for g_nof_streams
scope_sosi_arr : out t_dp_sosi_integer_arr(g_nof_streams - 1 downto 0)
@@ -78,13 +83,15 @@ entity dp_wideband_sp_arr_scope is
end dp_wideband_sp_arr_scope;
architecture beh of dp_wideband_sp_arr_scope is
- signal SCLKi : std_logic; -- sampling clk, for simulation only
+ -- sampling clk, for simulation only
+ signal SCLKi : std_logic;
signal scope_cnt_arr : t_natural_arr(g_nof_streams - 1 downto 0);
signal st_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
begin
sim_only : if g_sim = true generate
use_sclk : if g_use_sclk = true generate
- SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
+ -- no worry about the delta cycle delay from SCLK to SCLKi
+ SCLKi <= SCLK;
end generate;
gen_sclk : if g_use_sclk = false generate
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
index fcedf587507c3e5aed27237bcec33f8be5d55e97..01eee0f7824543f43f8f22356270ea6308b7d3b8 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
@@ -48,19 +48,24 @@ entity dp_wideband_wb_arr_scope is
generic (
g_sim : boolean := false;
g_use_sclk : boolean := true;
- g_wideband_factor : natural := 4; -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian : boolean := false; -- When true wb_sosi_arr[3:0] = sample[t0,t1,t2,t3], else when false : wb_sosi_arr[3:0] = sample[t3,t2,t1,t0]
- g_dat_w : natural := 8 -- Actual width of the data field or of the re field, im field
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor : natural := 4;
+ -- When true wb_sosi_arr[3:0] = sample[t0,t1,t2,t3], else when false : wb_sosi_arr[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian : boolean := false;
+ -- Actual width of the data field or of the re field, im field
+ g_dat_w : natural := 8
);
port (
-- Digital processing clk
DCLK : in std_logic := '0';
-- Sampling clk, for simulation only
- SCLK : in std_logic := '0'; -- SCLK rate = g_wideband_factor * DCLK rate
+ -- SCLK rate = g_wideband_factor * DCLK rate
+ SCLK : in std_logic := '0';
-- Streaming input samples for one stream
- wb_sosi_arr : in t_dp_sosi_arr(g_wideband_factor - 1 downto 0); -- = [3:0] = Signal Path time samples [t3,t2,t1,t0]
+ -- = [3:0] = Signal Path time samples [t3,t2,t1,t0]
+ wb_sosi_arr : in t_dp_sosi_arr(g_wideband_factor - 1 downto 0);
-- Scope output samples for one stream
scope_sosi : out t_dp_sosi_integer
@@ -68,13 +73,15 @@ entity dp_wideband_wb_arr_scope is
end dp_wideband_wb_arr_scope;
architecture beh of dp_wideband_wb_arr_scope is
- signal SCLKi : std_logic; -- sampling clk, for simulation only
+ -- sampling clk, for simulation only
+ signal SCLKi : std_logic;
signal sample_cnt : natural range 0 to g_wideband_factor - 1 := 0;
signal st_sosi : t_dp_sosi;
begin
sim_only : if g_sim = true generate
use_sclk : if g_use_sclk = true generate
- SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
+ -- no worry about the delta cycle delay from SCLK to SCLKi
+ SCLKi <= SCLK;
end generate;
gen_sclk : if g_use_sclk = false generate
@@ -91,7 +98,8 @@ begin
st_sosi <= wb_sosi_arr(sample_cnt);
end if;
sample_cnt <= 0;
- if wb_sosi_arr(0).valid = '1' and sample_cnt < g_wideband_factor - 1 then -- all wb_sosi_arr().valid are the same, so use (0)
+ -- all wb_sosi_arr().valid are the same, so use (0)
+ if wb_sosi_arr(0).valid = '1' and sample_cnt < g_wideband_factor - 1 then
sample_cnt <= sample_cnt + 1;
end if;
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff.vhd b/libraries/base/dp/src/vhdl/dp_xonoff.vhd
index e9768eda7a94e66064fb093c00a703b5de5ef37d..c117a83e1dfba383cf0e102173d5f0d9faa31766 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff.vhd
@@ -106,9 +106,11 @@ entity dp_xonoff is
in_siso : out t_dp_siso;
in_sosi : in t_dp_sosi;
-- Frame out
- out_siso : in t_dp_siso; -- flush control via out_siso.xon
+ -- flush control via out_siso.xon
+ out_siso : in t_dp_siso;
out_sosi : out t_dp_sosi;
- out_en : out std_logic; -- for monitoring purposes in tb
+ -- for monitoring purposes in tb
+ out_en : out std_logic;
-- Optional override to force XOFF ('1' = enable override)
force_xoff : in std_logic := '0'
);
@@ -132,9 +134,12 @@ begin
end generate;
no_bypass : if g_bypass = false generate
- in_siso.ready <= out_siso.ready or (not i_out_en); -- pass on ready for detailed flow control per cycle only when output is enabled, otherwise ready = 1
- in_siso.xon <= '1'; -- upstream can remain on, because flush will handle out_siso.xon
- nxt_flush <= not out_siso.xon or force_xoff; -- use xon for flow control at frame level
+ -- pass on ready for detailed flow control per cycle only when output is enabled, otherwise ready = 1
+ in_siso.ready <= out_siso.ready or (not i_out_en);
+ -- upstream can remain on, because flush will handle out_siso.xon
+ in_siso.xon <= '1';
+ -- use xon for flow control at frame level
+ nxt_flush <= not out_siso.xon or force_xoff;
p_clk: process(clk, rst)
begin
@@ -144,8 +149,10 @@ begin
i_out_en <= '1';
elsif rising_edge(clk) then
frm_busy_reg <= frm_busy;
- flush <= nxt_flush; -- pipeline register flush to ease timing closure
- i_out_en <= nxt_out_en; -- state register out_en because it can only change between frames
+ -- pipeline register flush to ease timing closure
+ flush <= nxt_flush;
+ -- state register out_en because it can only change between frames
+ i_out_en <= nxt_out_en;
end if;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd b/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
index 7690cbfe3f5d12f8cafcec558220b4144ed6d28b..7c22a04fd48eb77124b14c44d6a5d1bad432382c 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
@@ -86,13 +86,16 @@ begin
when 0 =>
mm_xonoff_reg(0) <= sla_in.wrdata(0);
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read Block Sync
when 0 =>
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd b/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
index 4fd64c8f6e32acd2b9866efb3fe59b9d78607a17..9ac55df3f082d7637cc53505c44a13609ddbf220 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
@@ -40,8 +40,10 @@ use common_lib.common_mem_pkg.all;
entity dp_xonoff_reg_timeout is
generic (
g_default_value : std_logic := '1';
- g_mm_timeout : natural := 10; -- 10 Seconds, Max = 42
- g_sim : boolean := false -- When True, use micro seconds instead of seconds
+ -- 10 Seconds, Max = 42
+ g_mm_timeout : natural := 10;
+ -- When True, use micro seconds instead of seconds
+ g_sim : boolean := false
);
port (
-- Clocks and reset
@@ -65,7 +67,8 @@ architecture str of dp_xonoff_reg_timeout is
dat_w => c_word_w,
nof_dat => 1,
init_sl => g_default_value);
- constant c_mm_max_counter : natural := sel_a_b(g_sim, g_mm_timeout * 50, g_mm_timeout * (50 * 10**6)); -- @50MHz
+ -- @50MHz
+ constant c_mm_max_counter : natural := sel_a_b(g_sim, g_mm_timeout * 50, g_mm_timeout * (50 * 10**6));
signal mm_xonoff_reg : std_logic_vector(0 downto 0);
signal mm_xonoff_reg_out : std_logic_vector(0 downto 0);
@@ -103,13 +106,16 @@ begin
cnt_en <= '1';
end if;
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read Block Sync
when 0 =>
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
index 20456ab387ba3873e6a87d8843bafd78250ac876..76f4d26dde0f37a34a80f3e942c95902a7cad77c 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
@@ -44,17 +44,28 @@ use work.dp_stream_pkg.all;
entity mmp_dp_bsn_align_v2 is
generic (
-- for dp_bsn_align_v2
- g_nof_streams : natural; -- number of input and output streams
- g_bsn_latency_max : natural; -- Maximum travel latency of a remote block in number of block periods T_blk
- g_nof_aligners_max : natural := 1; -- 1 when only align at last node, > 1 when align at every intermediate node
- g_block_size : natural := 32; -- > 1, g_block_size=1 is not supported
- g_bsn_w : natural := c_dp_stream_bsn_w; -- number of bits in sosi BSN
- g_data_w : natural; -- number of bits in sosi data
- g_data_replacement_value : integer := 0; -- output sosi data value for missing input blocks
- g_use_mm_output : boolean := false; -- output via MM or via streaming DP
- g_pipeline_input : natural := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr
- g_pipeline_output : natural := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of out_sosi_arr
- g_rd_latency : natural := 2; -- 1 or 2, choose 2 to ease timing closure
+ -- number of input and output streams
+ g_nof_streams : natural;
+ -- Maximum travel latency of a remote block in number of block periods T_blk
+ g_bsn_latency_max : natural;
+ -- 1 when only align at last node, > 1 when align at every intermediate node
+ g_nof_aligners_max : natural := 1;
+ -- > 1, g_block_size=1 is not supported
+ g_block_size : natural := 32;
+ -- number of bits in sosi BSN
+ g_bsn_w : natural := c_dp_stream_bsn_w;
+ -- number of bits in sosi data
+ g_data_w : natural;
+ -- output sosi data value for missing input blocks
+ g_data_replacement_value : integer := 0;
+ -- output via MM or via streaming DP
+ g_use_mm_output : boolean := false;
+ -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr
+ g_pipeline_input : natural := 1;
+ -- >= 0, choose 0 for wires, choose 1 to ease timing closure of out_sosi_arr
+ g_pipeline_output : natural := 1;
+ -- 1 or 2, choose 2 to ease timing closure
+ g_rd_latency : natural := 2;
-- for mms_dp_bsn_monitor_v2
g_nof_clk_per_sync : natural := 200 * 10**6;
g_nof_input_bsn_monitors : natural := 0;
@@ -78,14 +89,17 @@ entity mmp_dp_bsn_align_v2 is
dp_rst : in std_logic;
dp_clk : in std_logic;
- node_index : in natural range 0 to g_nof_aligners_max - 1 := 0; -- only used when g_nof_aligners_max > 1
+ -- only used when g_nof_aligners_max > 1
+ node_index : in natural range 0 to g_nof_aligners_max - 1 := 0;
-- Streaming input
in_sosi_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-- Output via local MM interface in dp_clk domain, when g_use_mm_output = TRUE.
- mm_sosi : out t_dp_sosi; -- streaming information that signals that an output block can be read
- mm_copi : in t_mem_copi := c_mem_copi_rst; -- read access to output block, all output streams share same mm_copi
+ -- streaming information that signals that an output block can be read
+ mm_sosi : out t_dp_sosi;
+ -- read access to output block, all output streams share same mm_copi
+ mm_copi : in t_mem_copi := c_mem_copi_rst;
mm_cipo_arr : out t_mem_cipo_arr(g_nof_streams - 1 downto 0);
-- Output via streaming DP interface, when g_use_mm_output = FALSE.
@@ -120,7 +134,8 @@ begin
g_cross_clock_domain => true,
g_readback => false,
g_reg => c_mm_reg,
- g_init_reg => (others => '1') -- Default all g_nof_streams are enabled.
+ -- Default all g_nof_streams are enabled.
+ g_init_reg => (others => '1')
)
port map (
-- Clocks and reset
@@ -136,7 +151,8 @@ begin
-- MM registers in st_clk domain
reg_wr_arr => OPEN,
reg_rd_arr => OPEN,
- out_reg => reg_wr, -- readback via ST clock domain
+ -- readback via ST clock domain
+ out_reg => reg_wr,
in_reg => reg_rd
);
@@ -184,7 +200,8 @@ begin
gen_bsn_mon_output : if g_use_bsn_output_monitor generate
u_bsn_mon_output : entity work.mms_dp_bsn_monitor_v2
generic map (
- g_nof_streams => 1, -- all outputs have same BSN monitor information
+ -- all outputs have same BSN monitor information
+ g_nof_streams => 1,
g_cross_clock_domain => true,
g_sync_timeout => g_nof_clk_per_sync,
g_bsn_w => g_bsn_w,
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
index 4cab59e25a3a5fb7940625da40cb2af9a33d673f..1dd4523d33c8221e73ecc31be65039e3e552252f 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
@@ -63,8 +63,10 @@ use work.dp_stream_pkg.all;
entity mmp_dp_bsn_sync_scheduler is
generic (
g_bsn_w : natural := c_dp_stream_bsn_w;
- g_block_size : natural := 256; -- = number of data valid per BSN block, must be >= 2
- g_ctrl_interval_size_min : natural := 1 -- Minimum interval size to use if MM write interval size is set too small.
+ -- = number of data valid per BSN block, must be >= 2
+ g_block_size : natural := 256;
+ -- Minimum interval size to use if MM write interval size is set too small.
+ g_ctrl_interval_size_min : natural := 1
);
port (
-- Clocks and reset
@@ -128,8 +130,10 @@ begin
wr_ctrl_enable <= reg_wr( 0);
ctrl_interval_size <= TO_UINT(reg_wr( 2 * c_word_w - 1 downto 1 * c_word_w)) when
g_ctrl_interval_size_min < TO_UINT(reg_wr( 2 * c_word_w - 1 downto 1 * c_word_w)) else g_ctrl_interval_size_min;
- wr_start_bsn_64( c_word_w - 1 downto 0) <= reg_wr( 3 * c_word_w - 1 downto 2 * c_word_w); -- low word
- wr_start_bsn_64(2 * c_word_w - 1 downto 1 * c_word_w) <= reg_wr( 4 * c_word_w - 1 downto 3 * c_word_w); -- high word
+ -- low word
+ wr_start_bsn_64( c_word_w - 1 downto 0) <= reg_wr( 3 * c_word_w - 1 downto 2 * c_word_w);
+ -- high word
+ wr_start_bsn_64(2 * c_word_w - 1 downto 1 * c_word_w) <= reg_wr( 4 * c_word_w - 1 downto 3 * c_word_w);
-- Derive ctrl_enable_evt from change in wr_ctrl_enable, instead of using
-- reg_wr_arr(0), see description
@@ -149,17 +153,26 @@ begin
ctrl_enable_evt <= wr_ctrl_enable_evt when rising_edge(dp_clk);
-- . Read
- reg_rd( 0) <= ctrl_enable; -- read back internal ctrl_enable
+ -- read back internal ctrl_enable
+ reg_rd( 0) <= ctrl_enable;
reg_rd( 2 * c_word_w - 1 downto 1 * c_word_w) <= TO_UVEC(mon_output_interval_size, c_word_w);
- reg_rd( 3 * c_word_w - 1 downto 2 * c_word_w) <= wr_start_bsn_64( c_word_w - 1 downto 0); -- low word
- reg_rd( 4 * c_word_w - 1 downto 3 * c_word_w) <= wr_start_bsn_64( 2 * c_word_w - 1 downto c_word_w); -- high word
- reg_rd( 5 * c_word_w - 1 downto 4 * c_word_w) <= rd_current_input_bsn_64( c_word_w - 1 downto 0); -- low word
- reg_rd( 6 * c_word_w - 1 downto 5 * c_word_w) <= rd_current_input_bsn_64(2 * c_word_w - 1 downto c_word_w); -- high word
- reg_rd( 7 * c_word_w - 1 downto 6 * c_word_w) <= rd_input_bsn_at_sync_64( c_word_w - 1 downto 0); -- low word
- reg_rd( 8 * c_word_w - 1 downto 7 * c_word_w) <= rd_input_bsn_at_sync_64(2 * c_word_w - 1 downto c_word_w); -- high word
+ -- low word
+ reg_rd( 3 * c_word_w - 1 downto 2 * c_word_w) <= wr_start_bsn_64( c_word_w - 1 downto 0);
+ -- high word
+ reg_rd( 4 * c_word_w - 1 downto 3 * c_word_w) <= wr_start_bsn_64( 2 * c_word_w - 1 downto c_word_w);
+ -- low word
+ reg_rd( 5 * c_word_w - 1 downto 4 * c_word_w) <= rd_current_input_bsn_64( c_word_w - 1 downto 0);
+ -- high word
+ reg_rd( 6 * c_word_w - 1 downto 5 * c_word_w) <= rd_current_input_bsn_64(2 * c_word_w - 1 downto c_word_w);
+ -- low word
+ reg_rd( 7 * c_word_w - 1 downto 6 * c_word_w) <= rd_input_bsn_at_sync_64( c_word_w - 1 downto 0);
+ -- high word
+ reg_rd( 8 * c_word_w - 1 downto 7 * c_word_w) <= rd_input_bsn_at_sync_64(2 * c_word_w - 1 downto c_word_w);
reg_rd( 8 * c_word_w) <= mon_output_enable;
- reg_rd(10 * c_word_w - 1 downto 9 * c_word_w) <= rd_output_sync_bsn_64( c_word_w - 1 downto 0); -- low word
- reg_rd(11 * c_word_w - 1 downto 10 * c_word_w) <= rd_output_sync_bsn_64( 2 * c_word_w - 1 downto c_word_w); -- high word
+ -- low word
+ reg_rd(10 * c_word_w - 1 downto 9 * c_word_w) <= rd_output_sync_bsn_64( c_word_w - 1 downto 0);
+ -- high word
+ reg_rd(11 * c_word_w - 1 downto 10 * c_word_w) <= rd_output_sync_bsn_64( 2 * c_word_w - 1 downto c_word_w);
reg_rd(12 * c_word_w - 1 downto 11 * c_word_w) <= TO_UVEC(g_block_size, c_word_w);
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
@@ -182,7 +195,8 @@ begin
-- MM registers in st_clk domain
reg_wr_arr => reg_wr_arr,
reg_rd_arr => OPEN,
- out_reg => reg_wr, -- readback via ST clock domain
+ -- readback via ST clock domain
+ out_reg => reg_wr,
in_reg => reg_rd
);
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
index 85a154fa94cf94049225eab31c7d7e19d21e33c3..e8354ef74fae0b2f4c60242a301c9574b2c766a0 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
@@ -34,8 +34,10 @@ entity mmp_dp_bsn_sync_scheduler_arr is
generic (
g_nof_streams : positive := 1;
g_bsn_w : natural := c_dp_stream_bsn_w;
- g_block_size : natural := 256; -- = number of data valid per BSN block, must be >= 2
- g_ctrl_interval_size_min : natural := 1 -- Minimum interval size to use if MM write interval size is set too small.
+ -- = number of data valid per BSN block, must be >= 2
+ g_block_size : natural := 256;
+ -- Minimum interval size to use if MM write interval size is set too small.
+ g_ctrl_interval_size_min : natural := 1
);
port (
-- Clocks and reset
diff --git a/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd b/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
index 336f7e55650bcfe35676e4a5d72bfc1b5140ce16..a3cf94991fe2e2213b38e0be33e9ff7b5b486be3 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
@@ -73,7 +73,8 @@ begin
-- Use same control for all streams
u_mm_fields: entity mm_lib.mm_fields
generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ -- use FALSE to save logic when always slv_in_val='1'
+ g_use_slv_in_val => false,
g_field_arr => c_field_arr
)
port map (
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
index fd265dbd4009b7acff0a4d6d6da2de9065916e45..36549b0203282fe27d1bf6ad17c4f7c21e4ef022 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
@@ -31,14 +31,21 @@ use work.dp_stream_pkg.all;
entity mms_dp_bsn_align is
generic (
- g_block_size : natural := 32; -- > 1, g_block_size=1 is not supported, g_block_size <= g_block_period
- g_block_period : natural := 256; -- number of clock cycles per block period or block interval (not used in the architecture, used in the comment only)
- g_nof_input : natural := 2; -- >= 1
- g_xoff_timeout : natural := 1536; -- e.g. g_bsn_latency * 2 * g_block_period
- g_sop_timeout : natural := 1024; -- e.g. (g_bsn_latency + 1) * g_block_period
+ -- > 1, g_block_size=1 is not supported, g_block_size <= g_block_period
+ g_block_size : natural := 32;
+ -- number of clock cycles per block period or block interval (not used in the architecture, used in the comment only)
+ g_block_period : natural := 256;
+ -- >= 1
+ g_nof_input : natural := 2;
+ -- e.g. g_bsn_latency * 2 * g_block_period
+ g_xoff_timeout : natural := 1536;
+ -- e.g. (g_bsn_latency + 1) * g_block_period
+ g_sop_timeout : natural := 1024;
g_bsn_latency : natural := 3;
- g_bsn_request_pipeline : natural := 2; -- = 1, 2, ..., c_bsn_nof_stages, requested total pipelining of the BSN max and BSN min operation
- g_cross_clock_domain : boolean := true -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- = 1, 2, ..., c_bsn_nof_stages, requested total pipelining of the BSN max and BSN min operation
+ g_bsn_request_pipeline : natural := 2;
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true
);
port (
-- Memory-mapped clock domain
@@ -54,7 +61,8 @@ entity mms_dp_bsn_align is
snk_out_arr : out t_dp_siso_arr(g_nof_input - 1 downto 0);
snk_in_arr : in t_dp_sosi_arr(g_nof_input - 1 downto 0);
-- ST source
- src_in_arr : in t_dp_siso_arr(g_nof_input - 1 downto 0) := (others => c_dp_siso_rdy); -- only src_in_arr(0) is used for src_out flow control because all src_out need to stay aligned
+ -- only src_in_arr(0) is used for src_out flow control because all src_out need to stay aligned
+ src_in_arr : in t_dp_siso_arr(g_nof_input - 1 downto 0) := (others => c_dp_siso_rdy);
src_out_arr : out t_dp_sosi_arr(g_nof_input - 1 downto 0)
);
end mms_dp_bsn_align;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
index 645f43333ff9b7cb54ce3df380b8ba1a0f318484..668adfa01f25ad7200563214e4ade5386bf5c7e7 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
@@ -32,13 +32,15 @@ use work.dp_stream_pkg.all;
entity mms_dp_bsn_monitor is
generic (
g_nof_streams : positive := 1;
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
g_sync_timeout : natural := 200 * 10**6;
g_bsn_w : natural := c_dp_stream_bsn_w;
g_error_bi : natural := 0;
g_cnt_sop_w : natural := c_word_w;
g_cnt_valid_w : natural := c_word_w;
- g_log_first_bsn : boolean := true -- Logs first BSN + cycle count. Useful when using BSN aligner.
+ -- Logs first BSN + cycle count. Useful when using BSN aligner.
+ g_log_first_bsn : boolean := true
);
port (
-- Memory-mapped clock domain
@@ -50,7 +52,8 @@ entity mms_dp_bsn_monitor is
-- Streaming clock domain
dp_rst : in std_logic;
dp_clk : in std_logic;
- sync_in : in std_logic := '0'; -- Sync input that samples the current bsn number and the number of clockcycles that have expired since the last sop
+ -- Sync input that samples the current bsn number and the number of clockcycles that have expired since the last sop
+ sync_in : in std_logic := '0';
in_siso_arr : in t_dp_siso_arr(g_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
in_sosi_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0)
@@ -72,7 +75,8 @@ architecture str of mms_dp_bsn_monitor is
signal mon_bsn_at_sync_arr : t_mon_bsn_arr;
signal mon_nof_sop_arr : t_mon_sop_arr;
- signal mon_nof_err_arr : t_mon_sop_arr; -- use g_cnt_sop_w, because at maximium all frames have an error
+ -- use g_cnt_sop_w, because at maximium all frames have an error
+ signal mon_nof_err_arr : t_mon_sop_arr;
signal mon_nof_valid_arr : t_mon_val_arr;
signal mon_bsn_first_arr : t_mon_bsn_arr;
signal mon_bsn_first_cycle_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0);
@@ -142,7 +146,8 @@ begin
-- MM interface
-- . control
- mon_evt => mon_evt_arr(i), -- pulses when new monitor data is available regarding the previous sync interval
+ -- pulses when new monitor data is available regarding the previous sync interval
+ mon_evt => mon_evt_arr(i),
mon_sync => OPEN,
mon_sync_timeout => mon_sync_timeout_arr(i),
-- . siso
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
index 5ba8560094d70960cc11046750eb30bdc7120eeb..68390cb77a6e01484e3c74255e7b9f410f223abc 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
@@ -34,7 +34,8 @@ use work.dp_components_pkg.all;
entity mms_dp_bsn_monitor_v2 is
generic (
g_nof_streams : positive := 1;
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
g_sync_timeout : natural := c_dp_sync_timeout;
g_bsn_w : natural := c_dp_stream_bsn_w;
g_error_bi : natural := 0;
@@ -52,7 +53,8 @@ entity mms_dp_bsn_monitor_v2 is
-- Streaming clock domain
dp_rst : in std_logic;
dp_clk : in std_logic;
- ref_sync : in std_logic := '0'; -- ref Sync input
+ -- ref Sync input
+ ref_sync : in std_logic := '0';
in_siso_arr : in t_dp_siso_arr(g_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
in_sosi_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0)
@@ -75,7 +77,8 @@ architecture str of mms_dp_bsn_monitor_v2 is
signal mon_bsn_at_sync_arr : t_mon_bsn_arr;
signal mon_nof_sop_arr : t_mon_sop_arr;
- signal mon_nof_err_arr : t_mon_sop_arr; -- use g_cnt_sop_w, because at maximium all frames have an error
+ -- use g_cnt_sop_w, because at maximium all frames have an error
+ signal mon_nof_err_arr : t_mon_sop_arr;
signal mon_nof_valid_arr : t_mon_val_arr;
signal mon_latency_arr : t_mon_lat_arr;
@@ -141,7 +144,8 @@ begin
-- MM interface
-- . control
- mon_evt => mon_evt_arr(i), -- pulses when new monitor data is available regarding the previous sync interval
+ -- pulses when new monitor data is available regarding the previous sync interval
+ mon_evt => mon_evt_arr(i),
mon_sync => OPEN,
mon_sync_timeout => mon_sync_timeout_arr(i),
-- . siso
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
index bf03acd736f054fe9f9bdb4dd0f619088f8036d7..c4b3a43bb0896507518a6298d078e1c76cc887ba 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
@@ -31,7 +31,8 @@ use work.dp_stream_pkg.all;
entity mms_dp_bsn_scheduler is
generic (
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
g_bsn_w : natural := c_dp_stream_bsn_w
);
port (
@@ -46,7 +47,8 @@ entity mms_dp_bsn_scheduler is
dp_rst : in std_logic;
dp_clk : in std_logic;
- snk_in : in t_dp_sosi; -- only uses eop (= block sync), bsn[]
+ -- only uses eop (= block sync), bsn[]
+ snk_in : in t_dp_sosi;
trigger_out : out std_logic
);
end mms_dp_bsn_scheduler;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
index 9b7f13a519d752601ba4c88ebfd145c76e89d837..d303cb2eef2542f9a0dd6e9d012563c4348aa4f7 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
@@ -30,22 +30,32 @@ use work.dp_stream_pkg.all;
entity mms_dp_bsn_source is
generic (
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_block_size : natural := 256; -- 1024 samples @ 800M / 4 = 256 4 sample words @ 200 M
- g_nof_block_per_sync : natural := 8; -- 800M/1024 = 781250;
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
+ -- 1024 samples @ 800M / 4 = 256 4 sample words @ 200 M
+ g_block_size : natural := 256;
+ -- 800M/1024 = 781250;
+ g_nof_block_per_sync : natural := 8;
g_bsn_w : natural := 48
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- dp_rst : in std_logic; -- reset synchronous with st_clk
- dp_clk : in std_logic; -- other clock domain clock
- dp_pps : in std_logic := '1'; -- external PPS in captured in dp_clk domain
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ dp_rst : in std_logic;
+ -- other clock domain clock
+ dp_clk : in std_logic;
+ -- external PPS in captured in dp_clk domain
+ dp_pps : in std_logic := '1';
-- Memory-mapped clock domain
- reg_mosi : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- reg_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ reg_mosi : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ reg_miso : out t_mem_miso;
-- Streaming clock domain
bs_sosi : out t_dp_sosi
@@ -113,5 +123,6 @@ begin
--capture_bsn <= i_bs_sosi.bsn; -- capture current BSN
--capture_bsn <= i_bs_sosi.bsn WHEN rising_edge(dp_clk) AND dp_pps='1'; -- capture BSN at external PPS
- capture_bsn <= i_bs_sosi.bsn when rising_edge(dp_clk) and i_bs_sosi.sync = '1'; -- capture BSN at internal sync
+ -- capture BSN at internal sync
+ capture_bsn <= i_bs_sosi.bsn when rising_edge(dp_clk) and i_bs_sosi.sync = '1';
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
index 92388ecf1eaa14e91dc3a24c27d05dd1c1913648..1dcba0d1f6761bc7946722e3645548b92d40d6cf 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
@@ -30,29 +30,41 @@ use work.dp_stream_pkg.all;
entity mms_dp_bsn_source_v2 is
generic (
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_block_size : natural := 256; -- 1024 samples @ 800M / 4 = 256 4 sample words @ 200 M
- g_nof_clk_per_sync : natural := 200 * 10**6; -- ;
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
+ -- 1024 samples @ 800M / 4 = 256 4 sample words @ 200 M
+ g_block_size : natural := 256;
+ -- ;
+ g_nof_clk_per_sync : natural := 200 * 10**6;
g_bsn_w : natural := 48;
g_bsn_time_offset_w : natural := 10
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- dp_rst : in std_logic; -- reset synchronous with st_clk
- dp_clk : in std_logic; -- other clock domain clock
- dp_pps : in std_logic := '1'; -- external PPS in captured in dp_clk domain
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ dp_rst : in std_logic;
+ -- other clock domain clock
+ dp_clk : in std_logic;
+ -- external PPS in captured in dp_clk domain
+ dp_pps : in std_logic := '1';
-- Memory-mapped clock domain
- reg_mosi : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- reg_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ reg_mosi : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ reg_miso : out t_mem_miso;
-- Streaming clock domain
bs_sosi : out t_dp_sosi;
- bs_restart : out std_logic; -- pulse to indicate if the bsn_source has restarted
- bs_new_interval : out std_logic; -- level to indicate first sync interval if the bsn_source has restarted
+ -- pulse to indicate if the bsn_source has restarted
+ bs_restart : out std_logic;
+ -- level to indicate first sync interval if the bsn_source has restarted
+ bs_new_interval : out std_logic;
bs_nof_clk_per_sync : out std_logic_vector(c_word_w - 1 downto 0)
);
end mms_dp_bsn_source_v2;
@@ -122,5 +134,6 @@ begin
src_out => i_bs_sosi
);
- capture_bsn <= i_bs_sosi.bsn when rising_edge(dp_clk) and i_bs_sosi.sync = '1'; -- capture BSN at internal sync
+ -- capture BSN at internal sync
+ capture_bsn <= i_bs_sosi.bsn when rising_edge(dp_clk) and i_bs_sosi.sync = '1';
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
index 4cc0b97ba5c903ee48d33521efb305e9d000fda2..0a53287b5b21498134171caf87c9f911930d7956 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
@@ -38,7 +38,8 @@ entity mms_dp_fifo_fill is
generic (
g_technology : natural := c_tech_select_default;
g_nof_streams : natural := 3;
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
g_data_w : natural := 16;
g_bsn_w : natural := 1;
g_empty_w : natural := 1;
@@ -49,11 +50,15 @@ entity mms_dp_fifo_fill is
g_use_channel : boolean := false;
g_use_error : boolean := false;
g_use_sync : boolean := false;
- g_use_complex : boolean := false; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_use_complex : boolean := false;
g_fifo_fill : natural := 0;
- g_fifo_size : natural := 256; -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : natural := 4; -- Nof words below max (full) at which fifo is considered almost full
- g_fifo_rl : natural := 1 -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size : natural := 256;
+ -- Nof words below max (full) at which fifo is considered almost full
+ g_fifo_af_margin : natural := 4;
+ -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+ g_fifo_rl : natural := 1
);
port (
-- Memory-mapped clock domain
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
index 8298bcacd57667b2e9c8f5eabcc68edbe367e7bb..31bf7237590ee3708958705687be349cc97d4b3e 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
@@ -62,12 +62,15 @@ begin
clk => mm_clk,
src_out => wr_sosi,
- usedw => wr_usedw, -- used words from rd FIFO
+ -- used words from rd FIFO
+ usedw => wr_usedw,
mm_wr => mm_wr,
mm_wrdata => mm_wr_data,
- mm_usedw => mm_wr_usedw, -- resized to 32 bits
- mm_availw => mm_wr_availw -- resized to 32 bits
+ -- resized to 32 bits
+ mm_usedw => mm_wr_usedw,
+ -- resized to 32 bits
+ mm_availw => mm_wr_availw
);
u_dp_fifo_from_mm_reg: entity work.dp_fifo_from_mm_reg
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
index 982363aafe4d003065908446d703ce473d85c329..345d4d40e86b76fc88290c6d9f17b28e803cb4e8 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
@@ -65,12 +65,14 @@ begin
snk_out => rd_siso,
snk_in => rd_sosi,
- usedw => rd_usedw, -- used words from rd FIFO
+ -- used words from rd FIFO
+ usedw => rd_usedw,
mm_rd => mm_rd,
mm_rddata => mm_rd_data,
mm_rdval => mm_rd_val,
- mm_usedw => mm_rd_usedw -- resized to 32 bits
+ -- resized to 32 bits
+ mm_usedw => mm_rd_usedw
);
u_dp_fifo_to_mm_reg: entity work.dp_fifo_to_mm_reg
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
index 78ef7e85f096233c9e3db7bf78bfa5ab55ca2fad..f596b10a38f5d0d68624df106cda4f7f998bfc87 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
@@ -40,7 +40,8 @@ use work.dp_stream_pkg.all;
entity mms_dp_force_data_parallel is
generic (
- g_dat_w : natural := 32; -- must be <= 32 to fit INTEGER range
+ -- must be <= 32 to fit INTEGER range
+ g_dat_w : natural := 32;
g_increment_data : integer := 0;
g_increment_re : integer := 0;
g_increment_im : integer := 0;
@@ -87,13 +88,17 @@ architecture str of mms_dp_force_data_parallel is
signal reg_force_data_rd : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
signal force_en : std_logic := '0';
- signal force_data : integer := 0; -- used for sosi.data
- signal force_re : integer := 0; -- used for sosi.re
- signal force_im : integer := 0; -- used for sosi.im
+ -- used for sosi.data
+ signal force_data : integer := 0;
+ -- used for sosi.re
+ signal force_re : integer := 0;
+ -- used for sosi.im
+ signal force_im : integer := 0;
begin
-- wires
force_en <= reg_force_data_wr(0);
- reg_force_data_rd(0) <= reg_force_data_wr(0); -- other bits are not used and will read '0'
+ -- other bits are not used and will read '0'
+ reg_force_data_rd(0) <= reg_force_data_wr(0);
force_data <= TO_SINT(reg_force_data_wr(2 * c_mm_reg.dat_w - 1 downto c_mm_reg.dat_w));
reg_force_data_rd(2 * c_mm_reg.dat_w - 1 downto c_mm_reg.dat_w) <= reg_force_data_wr(2 * c_mm_reg.dat_w - 1 downto c_mm_reg.dat_w);
force_re <= TO_SINT(reg_force_data_wr(3 * c_mm_reg.dat_w - 1 downto 2 * c_mm_reg.dat_w));
@@ -122,7 +127,8 @@ begin
-- MM registers in st_clk domain
reg_wr_arr => OPEN,
reg_rd_arr => OPEN,
- out_reg => reg_force_data_wr, -- readback via ST clock domain
+ -- readback via ST clock domain
+ out_reg => reg_force_data_wr,
in_reg => reg_force_data_rd
);
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
index 405a23ba8e716ff027a88e514b2db030e8adfbbe..e16dc4b40ef4d7ab0c81b261460ef42c92284a1a 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
@@ -42,7 +42,8 @@ use work.dp_stream_pkg.all;
entity mms_dp_force_data_parallel_arr is
generic (
g_nof_streams : natural := 1;
- g_dat_w : natural := 32; -- must be <= 32 to fit INTEGER range
+ -- must be <= 32 to fit INTEGER range
+ g_dat_w : natural := 32;
g_increment_data : integer := 0;
g_increment_re : integer := 0;
g_increment_im : integer := 0;
@@ -75,7 +76,8 @@ entity mms_dp_force_data_parallel_arr is
end mms_dp_force_data_parallel_arr;
architecture str of mms_dp_force_data_parallel_arr is
- constant c_mm_reg_adr_w : natural := 2; -- = ceil_log2(c_mm_reg.adr_w), copied from mms_dp_force_data_parallel.vhd
+ -- = ceil_log2(c_mm_reg.adr_w), copied from mms_dp_force_data_parallel.vhd
+ constant c_mm_reg_adr_w : natural := 2;
signal reg_force_data_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0) := (others => c_mem_mosi_rst);
signal reg_force_data_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
index 63de286f7c454f9e294ebe2725b020774714f619..cfebf70d367c780fef1fb7fbb6656d696565c04f 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
@@ -44,9 +44,12 @@ use work.dp_stream_pkg.all;
entity mms_dp_force_data_serial is
generic (
- g_dat_w : natural := 32; -- number of bits per force data value, must be <= 32 to fit INTEGER range
- g_index_period : natural := 10; -- number of indices in time, must be <= 2*31 to fit in NATURAL range
- g_index_sample_block_n : boolean := false -- when TRUE sample index in block, else block index in sync interval
+ -- number of bits per force data value, must be <= 32 to fit INTEGER range
+ g_dat_w : natural := 32;
+ -- number of indices in time, must be <= 2*31 to fit in NATURAL range
+ g_index_period : natural := 10;
+ -- when TRUE sample index in block, else block index in sync interval
+ g_index_sample_block_n : boolean := false
);
port (
-- Clocks and reset
@@ -75,7 +78,8 @@ architecture str of mms_dp_force_data_serial is
-- dat_w : NATURAL;
-- nof_dat : NATURAL; -- optional, nof dat words <= 2**adr_w
-- init_sl : STD_LOGIC; -- optional, init all dat words to std_logic '0', '1' or 'X'
- constant c_mm_reg : t_c_mem := (1, 3, c_word_w, 5, 'X'); -- use c_word_w = 32 to fit both g_dat_w data values and force_index
+ -- use c_word_w = 32 to fit both g_dat_w data values and force_index
+ constant c_mm_reg : t_c_mem := (1, 3, c_word_w, 5, 'X');
constant c_mm_reg_init : std_logic_vector(c_mem_reg_init_w - 1 downto 0) := (others => '0');
@@ -84,11 +88,15 @@ architecture str of mms_dp_force_data_serial is
signal force_en : std_logic := '0';
signal force_value : std_logic := '0';
- signal force_zero_n : std_logic := '0'; -- use _n to preserve backwards compatibility when force zero MM control was not supported yet
+ -- use _n to preserve backwards compatibility when force zero MM control was not supported yet
+ signal force_zero_n : std_logic := '0';
signal force_index : natural := 0;
- signal force_data : integer := 0; -- used for sosi.data
- signal force_re : integer := 0; -- used for sosi.re
- signal force_im : integer := 0; -- used for sosi.im
+ -- used for sosi.data
+ signal force_data : integer := 0;
+ -- used for sosi.re
+ signal force_re : integer := 0;
+ -- used for sosi.im
+ signal force_im : integer := 0;
begin
-- write wires
force_en <= reg_force_data_wr(0);
@@ -137,7 +145,8 @@ begin
-- MM registers in st_clk domain
reg_wr_arr => OPEN,
reg_rd_arr => OPEN,
- out_reg => reg_force_data_wr, -- readback via ST clock domain
+ -- readback via ST clock domain
+ out_reg => reg_force_data_wr,
in_reg => reg_force_data_rd
);
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
index 38e1ad0980603a0032a483758b2b3676546ad9ff..f001103e23750b572ca6262983c7a0af6c1c3cc3 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
@@ -41,10 +41,14 @@ use work.dp_stream_pkg.all;
entity mms_dp_force_data_serial_arr is
generic (
- g_nof_streams : natural := 1; -- number of parallel streams
- g_dat_w : natural := 32; -- number of bits per force data value, must be <= 32 to fit INTEGER range
- g_index_period : natural := 10; -- number of indices in time, must be <= 2*31 to fit in NATURAL range
- g_index_sample_block_n : boolean := false -- when TRUE sample index in block, else block index in sync interval
+ -- number of parallel streams
+ g_nof_streams : natural := 1;
+ -- number of bits per force data value, must be <= 32 to fit INTEGER range
+ g_dat_w : natural := 32;
+ -- number of indices in time, must be <= 2*31 to fit in NATURAL range
+ g_index_period : natural := 10;
+ -- when TRUE sample index in block, else block index in sync interval
+ g_index_sample_block_n : boolean := false
);
port (
-- Clocks and reset
@@ -65,7 +69,8 @@ entity mms_dp_force_data_serial_arr is
end mms_dp_force_data_serial_arr;
architecture str of mms_dp_force_data_serial_arr is
- constant c_mm_reg_adr_w : natural := 3; -- = ceil_log2(c_mm_reg.adr_w), copied from mms_dp_force_data_serial.vhd
+ -- = ceil_log2(c_mm_reg.adr_w), copied from mms_dp_force_data_serial.vhd
+ constant c_mm_reg_adr_w : natural := 3;
signal reg_force_data_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0) := (others => c_mem_mosi_rst);
signal reg_force_data_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
index cfb48e893704fbe95f331b1cce09c3fc5acb5530..bd5cd1ee90703ce3b8ed7d71ff20a2b2d8050351 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
@@ -42,18 +42,26 @@ entity mms_dp_gain is
g_gain_init_im : integer := 0;
g_gain_w : natural := 16;
g_in_dat_w : natural := 9;
- g_out_dat_w : natural := 24; -- 16 + 9 - 1 = 24 (-1 to skip double sign bit in product)
+ -- 16 + 9 - 1 = 24 (-1 to skip double sign bit in product)
+ g_out_dat_w : natural := 24;
-- pipelining (typically use defaults)
-- . real multiplier
- g_pipeline_real_mult_input : natural := 1; -- 0 or 1
- g_pipeline_real_mult_product : natural := 1; -- 0 or 1
- g_pipeline_real_mult_output : natural := 1; -- >= 0
+ -- 0 or 1
+ g_pipeline_real_mult_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_real_mult_product : natural := 1;
+ -- >= 0
+ g_pipeline_real_mult_output : natural := 1;
-- . complex multiplier
- g_pipeline_complex_mult_input : natural := 1; -- 0 or 1
- g_pipeline_complex_mult_product : natural := 0; -- 0 or 1
- g_pipeline_complex_mult_adder : natural := 1; -- 0 or 1
- g_pipeline_complex_mult_output : natural := 1 -- >= 0
+ -- 0 or 1
+ g_pipeline_complex_mult_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_complex_mult_product : natural := 0;
+ -- 0 or 1
+ g_pipeline_complex_mult_adder : natural := 1;
+ -- >= 0
+ g_pipeline_complex_mult_output : natural := 1
);
port (
-- Clocks and reset
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
index f6915b5ef663b0b58dff63f1d6d0013cbc16f0e6..aee33bb52b9767348fca830af46cf487b40f354e 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
@@ -61,25 +61,34 @@ use technology_lib.technology_select_pkg.all;
entity mms_dp_gain_arr is
generic (
g_technology : natural := c_tech_select_default;
- g_nof_streams : natural := 3; -- for g_nof_streams=1 there is mms_dp_gain.vhd
+ -- for g_nof_streams=1 there is mms_dp_gain.vhd
+ g_nof_streams : natural := 3;
g_complex_data : boolean := true;
g_complex_gain : boolean := false;
g_gain_init_re : integer := 1;
g_gain_init_im : integer := 0;
g_gain_w : natural := 16;
g_in_dat_w : natural := 9;
- g_out_dat_w : natural := 24; -- 16 + 9 - 1 = 24 (-1 to skip double sign bit in product)
+ -- 16 + 9 - 1 = 24 (-1 to skip double sign bit in product)
+ g_out_dat_w : natural := 24;
-- pipelining (typically use defaults)
-- . real multiplier
- g_pipeline_real_mult_input : natural := 1; -- 0 or 1
- g_pipeline_real_mult_product : natural := 1; -- 0 or 1
- g_pipeline_real_mult_output : natural := 1; -- >= 0
+ -- 0 or 1
+ g_pipeline_real_mult_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_real_mult_product : natural := 1;
+ -- >= 0
+ g_pipeline_real_mult_output : natural := 1;
-- . complex multiplier
- g_pipeline_complex_mult_input : natural := 1; -- 0 or 1
- g_pipeline_complex_mult_product : natural := 0; -- 0 or 1
- g_pipeline_complex_mult_adder : natural := 1; -- 0 or 1
- g_pipeline_complex_mult_output : natural := 1 -- >= 0
+ -- 0 or 1
+ g_pipeline_complex_mult_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_complex_mult_product : natural := 0;
+ -- 0 or 1
+ g_pipeline_complex_mult_adder : natural := 1;
+ -- >= 0
+ g_pipeline_complex_mult_output : natural := 1
);
port (
-- Clocks and reset
@@ -154,7 +163,8 @@ begin
reg_wr_arr => OPEN,
reg_rd_arr => OPEN,
in_reg => i_reg_gain_re,
- out_reg => i_reg_gain_re -- readback via ST clock domain
+ -- readback via ST clock domain
+ out_reg => i_reg_gain_re
);
gen_real_multiply : if c_real_multiply = true generate
@@ -165,12 +175,14 @@ begin
g_variant => "IP",
g_in_a_w => g_gain_w,
g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ g_out_p_w => g_out_dat_w,
g_nof_mult => 1,
g_pipeline_input => g_pipeline_real_mult_input,
g_pipeline_product => g_pipeline_real_mult_product,
g_pipeline_output => g_pipeline_real_mult_output,
- g_representation => "SIGNED" -- or "UNSIGNED"
+ -- or "UNSIGNED"
+ g_representation => "SIGNED"
)
port map (
rst => dp_rst,
@@ -197,7 +209,8 @@ begin
begin
out_sosi_arr(I) <= pipelined_in_sosi_arr(I);
out_sosi_arr(I).valid <= mult_sosi_arr(I).valid;
- out_sosi_arr(I).data <= RESIZE_DP_SDATA(mult_sosi_arr(I).data(g_out_dat_w - 1 downto 0)); -- sign extend
+ -- sign extend
+ out_sosi_arr(I).data <= RESIZE_DP_SDATA(mult_sosi_arr(I).data(g_out_dat_w - 1 downto 0));
end process;
end generate gen_nof_streams;
@@ -227,7 +240,8 @@ begin
reg_wr_arr => OPEN,
reg_rd_arr => OPEN,
in_reg => i_reg_gain_im,
- out_reg => i_reg_gain_im -- readback via ST clock domain
+ -- readback via ST clock domain
+ out_reg => i_reg_gain_im
);
end generate gen_complex_gain;
@@ -240,7 +254,8 @@ begin
g_variant => "IP",
g_in_a_w => g_gain_w,
g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ g_out_p_w => g_out_dat_w,
g_conjugate_b => false,
g_pipeline_input => g_pipeline_complex_mult_input,
g_pipeline_product => g_pipeline_complex_mult_product,
@@ -254,7 +269,8 @@ begin
in_ai => i_reg_gain_im((I + 1) * g_gain_w - 1 downto I * g_gain_w),
in_br => in_sosi_arr(I).re(g_in_dat_w - 1 downto 0),
in_bi => in_sosi_arr(I).im(g_in_dat_w - 1 downto 0),
- in_val => in_sosi_arr(I).valid, -- only propagate valid, not used internally
+ -- only propagate valid, not used internally
+ in_val => in_sosi_arr(I).valid,
out_pr => mult_sosi_arr(I).re(g_out_dat_w - 1 downto 0),
out_pi => mult_sosi_arr(I).im(g_out_dat_w - 1 downto 0),
out_val => mult_sosi_arr(I).valid
@@ -275,8 +291,10 @@ begin
begin
out_sosi_arr(I) <= pipelined_in_sosi_arr(I);
out_sosi_arr(I).valid <= mult_sosi_arr(I).valid;
- out_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(mult_sosi_arr(I).re(g_out_dat_w - 1 downto 0)); -- sign extend
- out_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(mult_sosi_arr(I).im(g_out_dat_w - 1 downto 0)); -- sign extend
+ -- sign extend
+ out_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(mult_sosi_arr(I).re(g_out_dat_w - 1 downto 0));
+ -- sign extend
+ out_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(mult_sosi_arr(I).im(g_out_dat_w - 1 downto 0));
end process;
end generate gen_nof_streams;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
index f84253d771ccd9b74043b71ac88abce1dda33a1f..3df670954bd8126b60a93c977b53d6741b3cea9e 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
@@ -36,25 +36,37 @@ use technology_lib.technology_select_pkg.all;
entity mms_dp_gain_serial is
generic (
g_technology : natural := c_tech_select_default;
- g_nof_gains : natural := 256; -- number of gains in series per stream
+ -- number of gains in series per stream
+ g_nof_gains : natural := 256;
g_complex_data : boolean := true;
g_complex_gain : boolean := false;
- g_gain_w : natural := 16; -- to fit 32b MM data use <= 32 for real, <= 16 for complex
+ -- to fit 32b MM data use <= 32 for real, <= 16 for complex
+ g_gain_w : natural := 16;
g_in_dat_w : natural := 9;
- g_out_dat_w : natural := 24; -- 16 + 9 - 1 = 24 (-1 to skip double sign bit in product)
- g_gains_file_name : string := "UNUSED"; -- "UNUSED" or relative path to some "gains_#.hex" file, where # is the stream index
- g_gains_write_only : boolean := false; -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode to save memory. When FALSE it is True Dual Port.
+ -- 16 + 9 - 1 = 24 (-1 to skip double sign bit in product)
+ g_out_dat_w : natural := 24;
+ -- "UNUSED" or relative path to some "gains_#.hex" file, where # is the stream index
+ g_gains_file_name : string := "UNUSED";
+ -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode to save memory. When FALSE it is True Dual Port.
+ g_gains_write_only : boolean := false;
-- pipelining (typically use defaults)
-- . real multiplier
- g_pipeline_real_mult_input : natural := 1; -- 0 or 1
- g_pipeline_real_mult_product : natural := 1; -- 0 or 1
- g_pipeline_real_mult_output : natural := 1; -- >= 0
+ -- 0 or 1
+ g_pipeline_real_mult_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_real_mult_product : natural := 1;
+ -- >= 0
+ g_pipeline_real_mult_output : natural := 1;
-- . complex multiplier
- g_pipeline_complex_mult_input : natural := 1; -- 0 or 1
- g_pipeline_complex_mult_product : natural := 0; -- 0 or 1
- g_pipeline_complex_mult_adder : natural := 1; -- 0 or 1
- g_pipeline_complex_mult_output : natural := 1 -- >= 0
+ -- 0 or 1
+ g_pipeline_complex_mult_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_complex_mult_product : natural := 0;
+ -- 0 or 1
+ g_pipeline_complex_mult_adder : natural := 1;
+ -- >= 0
+ g_pipeline_complex_mult_output : natural := 1
);
port (
-- System
@@ -64,11 +76,13 @@ entity mms_dp_gain_serial is
dp_clk : in std_logic;
-- MM interface
- ram_gains_mosi : in t_mem_mosi := c_mem_mosi_rst; -- write side
+ -- write side
+ ram_gains_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_gains_miso : out t_mem_miso;
-- ST interface
- gains_rd_address : in std_logic_vector(ceil_log2(g_nof_gains) - 1 downto 0); -- read side, same read address for all streams
+ -- read side, same read address for all streams
+ gains_rd_address : in std_logic_vector(ceil_log2(g_nof_gains) - 1 downto 0);
in_sosi : in t_dp_sosi;
out_sosi : out t_dp_sosi
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
index e81bb5a6d051448e101a2ab40e71e463b3244cc2..1cd02fccd41fca88f7e2949a70f661c3f3a56463 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
@@ -52,25 +52,37 @@ entity mms_dp_gain_serial_arr is
generic (
g_technology : natural := c_tech_select_default;
g_nof_streams : natural := 1;
- g_nof_gains : natural := 256; -- number of gains in series per stream
+ -- number of gains in series per stream
+ g_nof_gains : natural := 256;
g_complex_data : boolean := true;
g_complex_gain : boolean := false;
- g_gain_w : natural := 16; -- to fit 32b MM data use <= 32 for real, <= 16 for complex
+ -- to fit 32b MM data use <= 32 for real, <= 16 for complex
+ g_gain_w : natural := 16;
g_in_dat_w : natural := 9;
- g_out_dat_w : natural := 24; -- 16 + 9 - 1 = 24 (-1 to skip double sign bit in product)
- g_gains_file_name : string := "UNUSED"; -- "UNUSED" or relative path to some "gains_#.hex" file, where # is the stream index
- g_gains_write_only : boolean := false; -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode to save memory. When FALSE it is True Dual Port.
+ -- 16 + 9 - 1 = 24 (-1 to skip double sign bit in product)
+ g_out_dat_w : natural := 24;
+ -- "UNUSED" or relative path to some "gains_#.hex" file, where # is the stream index
+ g_gains_file_name : string := "UNUSED";
+ -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode to save memory. When FALSE it is True Dual Port.
+ g_gains_write_only : boolean := false;
-- pipelining (typically use defaults)
-- . real multiplier
- g_pipeline_real_mult_input : natural := 1; -- 0 or 1
- g_pipeline_real_mult_product : natural := 1; -- 0 or 1
- g_pipeline_real_mult_output : natural := 1; -- >= 0
+ -- 0 or 1
+ g_pipeline_real_mult_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_real_mult_product : natural := 1;
+ -- >= 0
+ g_pipeline_real_mult_output : natural := 1;
-- . complex multiplier
- g_pipeline_complex_mult_input : natural := 1; -- 0 or 1
- g_pipeline_complex_mult_product : natural := 0; -- 0 or 1
- g_pipeline_complex_mult_adder : natural := 1; -- 0 or 1
- g_pipeline_complex_mult_output : natural := 1 -- >= 0
+ -- 0 or 1
+ g_pipeline_complex_mult_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_complex_mult_product : natural := 0;
+ -- 0 or 1
+ g_pipeline_complex_mult_adder : natural := 1;
+ -- >= 0
+ g_pipeline_complex_mult_output : natural := 1
);
port (
-- System
@@ -80,11 +92,13 @@ entity mms_dp_gain_serial_arr is
dp_clk : in std_logic;
-- MM interface
- ram_gains_mosi : in t_mem_mosi := c_mem_mosi_rst; -- write side
+ -- write side
+ ram_gains_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_gains_miso : out t_mem_miso;
-- ST interface
- gains_rd_address : in std_logic_vector(ceil_log2(g_nof_gains) - 1 downto 0); -- read side, same read address for all streams
+ -- read side, same read address for all streams
+ gains_rd_address : in std_logic_vector(ceil_log2(g_nof_gains) - 1 downto 0);
in_sosi_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0);
out_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0)
@@ -101,7 +115,8 @@ architecture str of mms_dp_gain_serial_arr is
-- dat_w : NATURAL;
-- nof_dat : NATURAL; -- optional, nof dat words <= 2**adr_w
-- init_sl : STD_LOGIC; -- optional, init all dat words to std_logic '0', '1' or 'X'
- constant c_mm_ram : t_c_mem := (latency => 2, -- set latency to 2 to ease timing
+ -- set latency to 2 to ease timing
+ constant c_mm_ram : t_c_mem := (latency => 2,
adr_w => ceil_log2(g_nof_gains),
dat_w => sel_a_b(g_complex_gain, c_nof_complex, 1) * g_gain_w,
nof_dat => g_nof_gains,
@@ -146,7 +161,8 @@ begin
u_pipeline_arr : entity work.dp_pipeline_arr
generic map (
g_nof_streams => g_nof_streams,
- g_pipeline => c_mm_ram.latency -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline => c_mm_ram.latency
)
port map (
rst => dp_rst,
@@ -222,12 +238,14 @@ begin
g_variant => "IP",
g_in_a_w => g_gain_w,
g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ g_out_p_w => g_out_dat_w,
g_nof_mult => 1,
g_pipeline_input => g_pipeline_real_mult_input,
g_pipeline_product => g_pipeline_real_mult_product,
g_pipeline_output => g_pipeline_real_mult_output,
- g_representation => "SIGNED" -- or "UNSIGNED"
+ -- or "UNSIGNED"
+ g_representation => "SIGNED"
)
port map (
rst => dp_rst,
@@ -241,9 +259,11 @@ begin
p_out_sosi_arr : process(out_val_arr, out_dat_re_arr, in_sosi_arr_pipe_ctrl)
begin
- out_sosi_arr(I) <= c_dp_sosi_rst; -- to avoid (vsim-8684) No drivers exist on out port out_sosi_arr
+ -- to avoid (vsim-8684) No drivers exist on out port out_sosi_arr
+ out_sosi_arr(I) <= c_dp_sosi_rst;
out_sosi_arr(I).valid <= out_val_arr(I);
- out_sosi_arr(I).data <= RESIZE_DP_SDATA(out_dat_re_arr(I)); -- sign extend
+ -- sign extend
+ out_sosi_arr(I).data <= RESIZE_DP_SDATA(out_dat_re_arr(I));
out_sosi_arr(I).sop <= in_sosi_arr_pipe_ctrl(I).sop;
out_sosi_arr(I).eop <= in_sosi_arr_pipe_ctrl(I).eop;
out_sosi_arr(I).sync <= in_sosi_arr_pipe_ctrl(I).sync;
@@ -294,10 +314,13 @@ begin
p_out_sosi_arr : process(out_val_arr, out_dat_re_arr, out_dat_im_arr, in_sosi_arr_pipe_ctrl)
begin
- out_sosi_arr(I) <= c_dp_sosi_rst; -- to avoid (vsim-8684) No drivers exist on out port out_sosi_arr
+ -- to avoid (vsim-8684) No drivers exist on out port out_sosi_arr
+ out_sosi_arr(I) <= c_dp_sosi_rst;
out_sosi_arr(I).valid <= out_val_arr(I);
- out_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(out_dat_re_arr(I)); -- sign extend
- out_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(out_dat_im_arr(I)); -- sign extend
+ -- sign extend
+ out_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(out_dat_re_arr(I));
+ -- sign extend
+ out_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(out_dat_im_arr(I));
out_sosi_arr(I).sop <= in_sosi_arr_pipe_ctrl(I).sop;
out_sosi_arr(I).eop <= in_sosi_arr_pipe_ctrl(I).eop;
out_sosi_arr(I).sync <= in_sosi_arr_pipe_ctrl(I).sync;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
index 47d9371bc9aa81f8bafb3e427e274f85ccaa46eb..46ff126f1415ebd8159cdbbe851b7966b34a76d4 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
@@ -30,7 +30,8 @@ entity mms_dp_ram_from_mm is
g_ram_wr_nof_words : natural;
g_ram_rd_dat_w : natural;
g_init_file : string := "UNUSED";
- g_dp_on_at_init : std_logic := '0' -- Enable data path at default
+ -- Enable data path at default
+ g_dp_on_at_init : std_logic := '0'
);
port (
mm_rst : in std_logic;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_scale.vhd b/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
index 37b2b5a73d502da1f556d1c78733a976eae220af..087ee0b1175fba5b811135da22cc80550bf94f9d 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
@@ -47,10 +47,14 @@ entity mms_dp_scale is
-- dp_requantize generics
g_out_dat_w : natural := 8;
g_lsb_w : natural := 16;
- g_lsb_round : boolean := true; -- when TRUE ROUND else TRUNCATE the input LSbits
- g_lsb_round_clip : boolean := false; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
- g_msb_clip : boolean := true; -- when TRUE CLIP else WRAP the input MSbits
- g_msb_clip_symmetric : boolean := false -- when TRUE CLIP signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
+ -- when TRUE ROUND else TRUNCATE the input LSbits
+ g_lsb_round : boolean := true;
+ -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
+ g_lsb_round_clip : boolean := false;
+ -- when TRUE CLIP else WRAP the input MSbits
+ g_msb_clip : boolean := true;
+ -- when TRUE CLIP signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
+ g_msb_clip_symmetric : boolean := false
-- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
);
port (
@@ -77,7 +81,8 @@ end mms_dp_scale;
architecture str of mms_dp_scale is
constant c_dp_requantize_complex : boolean := g_complex_gain or g_complex_data;
- constant c_gain_out_dat_w : natural := g_gain_w + g_in_dat_w - 1; -- -1 to compensate for double sign-bit
+ -- -1 to compensate for double sign-bit
+ constant c_gain_out_dat_w : natural := g_gain_w + g_in_dat_w - 1;
signal dp_gain_out_sosi : t_dp_sosi;
begin
diff --git a/libraries/base/dp/src/vhdl/mms_dp_split.vhd b/libraries/base/dp/src/vhdl/mms_dp_split.vhd
index ee7ade081fde5e7f57217c5313a7238ff945c635..276f0c41e2eebcaa28c3119f22949ed6a1d5a0ef 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_split.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_split.vhd
@@ -31,7 +31,8 @@ entity mms_dp_split is
g_nof_streams : natural := 1;
g_data_w : natural := 16;
g_symbol_w : natural := 8;
- g_nof_symbols_max : natural := 8 -- Sets maximum nof_symbols that can be selected
+ -- Sets maximum nof_symbols that can be selected
+ g_nof_symbols_max : natural := 8
);
port (
-- Memory-mapped clock domain
diff --git a/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd b/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
index ad8d312d44271b1ebad5b073a69b28b738348639..559291369c6838fc35e77804c826c2deab92a354 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
@@ -60,8 +60,10 @@ entity mms_dp_sync_checker is
g_nof_blk_per_sync : natural := 16
);
port (
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
dp_clk : in std_logic;
dp_rst : in std_logic;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
index 1d6a6bbdefe88010c2d0e35c81db0967b84ede59..74adbc883a750e629141f457a23f33355525b3d4 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
@@ -39,8 +39,10 @@ entity mms_dp_sync_checker_arr is
g_nof_streams : natural := 1
);
port (
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
dp_clk : in std_logic;
dp_rst : in std_logic;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd b/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
index 8194cddac1c46f57530f88d33649a57edd6a4d1b..6760ad52a2ffea6b12fbcf1227a5065ee044ed14 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
@@ -37,8 +37,10 @@ entity mms_dp_throttle is
dp_rst : in std_logic;
dp_clk : in std_logic;
- reg_mosi : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- reg_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ reg_mosi : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ reg_miso : out t_mem_miso;
snk_out : out t_dp_siso;
snk_in : in t_dp_sosi;
diff --git a/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd b/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
index 2df830e9506cd7a143f3bc6129cd843ca2b1edd7..d008738c9ca78581a91ebdc50d451ae54d29efe2 100644
--- a/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
@@ -36,11 +36,16 @@ entity dp_sosi_arr_recorder is
generic (
g_nof_streams : natural;
g_record_file : string := "dp_sosi_arr_recorder.rec";
- g_record_invalid : boolean := true; -- FALSE = record valid cycles only
- g_wait_for_valid : boolean := true; -- TRUE = Don't record anything until valid is high
- g_record_sync : boolean := true; -- TRUE = Write snk_in.sync to file, else write "0" to file
- g_record_bsn : boolean := true; -- TRUE = Write snk_in.bsn(g_bsn_w-1 DOWNTO 0) to file, else write "0" to file
- g_record_data : boolean := true; -- etc.
+ -- FALSE = record valid cycles only
+ g_record_invalid : boolean := true;
+ -- TRUE = Don't record anything until valid is high
+ g_wait_for_valid : boolean := true;
+ -- TRUE = Write snk_in.sync to file, else write "0" to file
+ g_record_sync : boolean := true;
+ -- TRUE = Write snk_in.bsn(g_bsn_w-1 DOWNTO 0) to file, else write "0" to file
+ g_record_bsn : boolean := true;
+ -- etc.
+ g_record_data : boolean := true;
g_record_re : boolean := true;
g_record_im : boolean := true;
g_record_sop : boolean := true;
@@ -74,7 +79,8 @@ architecture beh of dp_sosi_arr_recorder is
signal record_start : boolean := false;
file record_file : TEXT;
begin
- gen_record_start : if g_wait_for_valid = true generate -- Start recording after valid=1
+ -- Start recording after valid=1
+ gen_record_start : if g_wait_for_valid = true generate
p_record_start : process(snk_in.valid)
variable v_open_status : file_open_status;
begin
@@ -87,7 +93,8 @@ begin
end process;
end generate;
- no_record_start : if g_wait_for_valid = false generate -- Start recording immediately
+ -- Start recording immediately
+ no_record_start : if g_wait_for_valid = false generate
record_start <= true;
end generate;
diff --git a/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd b/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
index 4fa5cf10e3490970fbfaea866d6668bc5c5837ea..68e142dbc2eff3469f3c0be9b126ee80e9b7c645 100644
--- a/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
@@ -52,11 +52,16 @@ use common_lib.common_str_pkg.all;
entity dp_sosi_recorder is
generic (
g_record_file : string := "dp_sosi_recorder.rec";
- g_record_invalid : boolean := true; -- FALSE = record valid cycles only
- g_wait_for_valid : boolean := true; -- TRUE = Don't record anything until valid is high
- g_record_sync : boolean := true; -- TRUE = Write snk_in.sync to file, else write "0" to file
- g_record_bsn : boolean := true; -- TRUE = Write snk_in.bsn(g_bsn_w-1 DOWNTO 0) to file, else write "0" to file
- g_record_data : boolean := true; -- etc.
+ -- FALSE = record valid cycles only
+ g_record_invalid : boolean := true;
+ -- TRUE = Don't record anything until valid is high
+ g_wait_for_valid : boolean := true;
+ -- TRUE = Write snk_in.sync to file, else write "0" to file
+ g_record_sync : boolean := true;
+ -- TRUE = Write snk_in.bsn(g_bsn_w-1 DOWNTO 0) to file, else write "0" to file
+ g_record_bsn : boolean := true;
+ -- etc.
+ g_record_data : boolean := true;
g_record_re : boolean := true;
g_record_im : boolean := true;
g_record_sop : boolean := true;
@@ -90,7 +95,8 @@ architecture beh of dp_sosi_recorder is
signal record_start : boolean := false;
file record_file : TEXT;
begin
- gen_record_start : if g_wait_for_valid = true generate -- Start recording after valid=1
+ -- Start recording after valid=1
+ gen_record_start : if g_wait_for_valid = true generate
p_record_start : process(snk_in.valid)
variable v_open_status : file_open_status;
begin
@@ -103,7 +109,8 @@ begin
end process;
end generate;
- no_record_start : if g_wait_for_valid = false generate -- Start recording immediately
+ -- Start recording immediately
+ no_record_start : if g_wait_for_valid = false generate
record_start <= true;
end generate;
diff --git a/libraries/base/dp/tb/vhdl/dp_statistics.vhd b/libraries/base/dp/tb/vhdl/dp_statistics.vhd
index 90c09b5f2448bf0e3d3462be865e6cb8b8766fa3..afea418e165f4422a64e9cbcc79a8acedc135714 100644
--- a/libraries/base/dp/tb/vhdl/dp_statistics.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_statistics.vhd
@@ -46,11 +46,16 @@ use technology_lib.technology_select_pkg.all;
entity dp_statistics is
generic (
- g_runtime_nof_packets : natural; -- Run the test bench for nof_packets before asserting tb_end
- g_runtime_timeout : time; -- Report Failure if g_runtime_nof_packets is not reached before this time
- g_check_nof_valid : boolean := false; -- True enables valid count checking at dp_done. Reports Failure in case of mismatch.
- g_check_nof_valid_ref : natural := 0; -- Reference (= expected) valid count
- g_dp_word_w : natural := 32 -- Used to calculate data rate
+ -- Run the test bench for nof_packets before asserting tb_end
+ g_runtime_nof_packets : natural;
+ -- Report Failure if g_runtime_nof_packets is not reached before this time
+ g_runtime_timeout : time;
+ -- True enables valid count checking at dp_done. Reports Failure in case of mismatch.
+ g_check_nof_valid : boolean := false;
+ -- Reference (= expected) valid count
+ g_check_nof_valid_ref : natural := 0;
+ -- Used to calculate data rate
+ g_dp_word_w : natural := 32
);
port (
@@ -58,7 +63,8 @@ entity dp_statistics is
dp_rst : in std_logic;
snk_in : in t_dp_sosi;
- tb_end : out std_logic -- To be used to stop test-bench generated clocks
+ -- To be used to stop test-bench generated clocks
+ tb_end : out std_logic
);
end dp_statistics;
@@ -103,8 +109,10 @@ begin
p_dp_done_check: process(dp_clk)
begin
if timeout = '1' and dp_done = '0' then
- report "[dp_statistics] Timeout occured!" severity ERROR; -- report ERROR to have Error in log
- report "[dp_statistics] Timeout occured!" severity FAILURE; -- report FAILURE to stop simulation
+ -- report ERROR to have Error in log
+ report "[dp_statistics] Timeout occured!" severity ERROR;
+ -- report FAILURE to stop simulation
+ report "[dp_statistics] Timeout occured!" severity FAILURE;
elsif dp_done = '1' then
if rising_edge(dp_clk) then
-- report valid count
@@ -112,7 +120,8 @@ begin
if valid_count /= g_check_nof_valid_ref then
report "[dp_statistics] Valid count " & integer'image(valid_count) & " does not match reference " & integer'image(g_check_nof_valid_ref) severity ERROR;
else
- report "[dp_statistics] Valid count " & integer'image(valid_count) & " is OK" severity NOTE; -- Note to show that the check indeed did happen
+ -- Note to show that the check indeed did happen
+ report "[dp_statistics] Valid count " & integer'image(valid_count) & " is OK" severity NOTE;
end if;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_player.vhd b/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
index 2591a2fa72489cc5919f39008c3c547f7a99e185..492dd9ff5cf12bbd1b0a5ddfeb81efc4d60144d8 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
@@ -78,13 +78,15 @@ begin
-- Assign record fields
src_out.sync <= hex_to_slv(v_line_str( 1 to 1))(0);
src_out.bsn <= hex_to_slv(v_line_str( 3 to 18));
- src_out.data(255 downto 0) <= hex_to_slv(v_line_str( 20 to 83)); -- FIXME Should support full width of 768 (new in RadioHDL)
+ -- FIXME Should support full width of 768 (new in RadioHDL)
+ src_out.data(255 downto 0) <= hex_to_slv(v_line_str( 20 to 83));
src_out.re <= hex_to_slv(v_line_str( 85 to 100));
src_out.im <= hex_to_slv(v_line_str(102 to 117));
src_out.valid <= hex_to_slv(v_line_str(119 to 119))(0);
src_out.sop <= hex_to_slv(v_line_str(121 to 121))(0);
src_out.eop <= hex_to_slv(v_line_str(123 to 123))(0);
- src_out.empty(7 downto 0) <= hex_to_slv(v_line_str(125 to 126)); -- FIXME Should support full width also.
+ -- FIXME Should support full width also.
+ src_out.empty(7 downto 0) <= hex_to_slv(v_line_str(125 to 126));
src_out.channel <= hex_to_slv(v_line_str(128 to 135));
src_out.err <= hex_to_slv(v_line_str(137 to 144));
end if;
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd b/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
index 6b507231b2dc1ee37e5e5f5d516b299168c93e7f..98a59852960c6223bd080a34bcfd1d517fc9fc14 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
@@ -44,28 +44,39 @@ entity dp_stream_stimuli is
generic (
g_instance_nr : natural := 0;
-- flow control
- g_random_w : natural := 15; -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w : natural := 15;
g_pulse_active : natural := 1;
g_pulse_period : natural := 2;
- g_flow_control : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control : t_dp_flow_control_enum := e_active;
-- initializations
g_sync_period : natural := 10;
g_sync_offset : natural := 0;
g_use_complex : boolean := false;
- g_data_init : natural := 0; -- choose some easy to recognize and unique value, data will increment at every valid
- g_re_init : natural := 0; -- choose some easy to recognize and unique value, data will increment at every valid
- g_im_init : natural := 0; -- choose some easy to recognize and unique value, data will increment at every valid
- g_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := TO_DP_BSN(0); -- X"0877665544332211", bsn will increment at every sop
- g_err_init : natural := 247; -- choose some easy to recognize and unique value
- g_err_incr : natural := 1; -- when 0 keep fixed at init value, when 1 increment at every sop
- g_channel_init : natural := 5; -- choose some easy to recognize and unique value
- g_channel_incr : natural := 1; -- when 0 keep fixed at init value, when 1 increment at every sop
+ -- choose some easy to recognize and unique value, data will increment at every valid
+ g_data_init : natural := 0;
+ -- choose some easy to recognize and unique value, data will increment at every valid
+ g_re_init : natural := 0;
+ -- choose some easy to recognize and unique value, data will increment at every valid
+ g_im_init : natural := 0;
+ -- X"0877665544332211", bsn will increment at every sop
+ g_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := TO_DP_BSN(0);
+ -- choose some easy to recognize and unique value
+ g_err_init : natural := 247;
+ -- when 0 keep fixed at init value, when 1 increment at every sop
+ g_err_incr : natural := 1;
+ -- choose some easy to recognize and unique value
+ g_channel_init : natural := 5;
+ -- when 0 keep fixed at init value, when 1 increment at every sop
+ g_channel_incr : natural := 1;
-- specific
g_in_dat_w : natural := 32;
g_nof_repeat : natural := 5;
g_pkt_len : natural := 16;
g_pkt_gap : natural := 4;
- g_wait_last_evt : natural := 100 -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ g_wait_last_evt : natural := 100
);
port (
rst : in std_logic;
@@ -76,14 +87,18 @@ entity dp_stream_stimuli is
src_out : out t_dp_sosi;
-- End of stimuli
- last_snk_in : out t_dp_sosi; -- expected verify_snk_in after end of stimuli
- last_snk_in_evt : out std_logic; -- trigger verify to verify the last_snk_in
- tb_end : out std_logic -- signal end of tb as far as this dp_stream_stimuli is concerned
+ -- expected verify_snk_in after end of stimuli
+ last_snk_in : out t_dp_sosi;
+ -- trigger verify to verify the last_snk_in
+ last_snk_in_evt : out std_logic;
+ -- signal end of tb as far as this dp_stream_stimuli is concerned
+ tb_end : out std_logic
);
end dp_stream_stimuli;
architecture str of dp_stream_stimuli is
- signal random : std_logic_vector(g_random_w - 1 downto 0) := TO_UVEC(g_instance_nr, g_random_w); -- use different initialization to have different random sequences per stream
+ -- use different initialization to have different random sequences per stream
+ signal random : std_logic_vector(g_random_w - 1 downto 0) := TO_UVEC(g_instance_nr, g_random_w);
signal pulse : std_logic;
signal pulse_en : std_logic := '1';
@@ -135,17 +150,21 @@ begin
for I in 0 to g_nof_repeat - 1 loop
-- Auto increment v_sosi field values for this packet
v_sosi.bsn := INCR_UVEC(v_sosi.bsn, 1);
- v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod g_sync_period) = g_sync_offset, '1', '0'); -- insert sync starting at BSN=g_sync_offset and with period g_sync_period
+ -- insert sync starting at BSN=g_sync_offset and with period g_sync_period
+ v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod g_sync_period) = g_sync_offset, '1', '0');
v_sosi.channel := INCR_UVEC(v_sosi.channel, g_channel_incr);
v_sosi.err := INCR_UVEC(v_sosi.err, g_err_incr);
if g_use_complex = false then
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
else
v_sosi.re := INCR_UVEC(v_sosi.re, g_pkt_len);
- v_sosi.re := RESIZE_DP_DSP_DATA(v_sosi.re(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.re := RESIZE_DP_DSP_DATA(v_sosi.re(g_in_dat_w - 1 downto 0));
v_sosi.im := INCR_UVEC(v_sosi.im, g_pkt_len);
- v_sosi.im := RESIZE_DP_DSP_DATA(v_sosi.im(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.im := RESIZE_DP_DSP_DATA(v_sosi.im(g_in_dat_w - 1 downto 0));
end if;
-- Send packet
if g_use_complex = false then
@@ -178,11 +197,13 @@ begin
v_last.err := TO_DP_ERROR(g_err_init + (g_nof_repeat - 1) * g_err_incr);
-- . account for g_pkt_len
v_last.data := INCR_UVEC(v_sosi.data, g_pkt_len - 1);
- v_last.data := RESIZE_DP_DATA(v_last.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_last.data := RESIZE_DP_DATA(v_last.data(g_in_dat_w - 1 downto 0));
last_snk_in <= v_last;
-- Signal end of stimuli
- proc_common_wait_some_cycles(clk, g_wait_last_evt); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ proc_common_wait_some_cycles(clk, g_wait_last_evt);
proc_common_gen_pulse(clk, last_snk_in_evt);
proc_common_wait_some_cycles(clk, 50);
tb_end <= '1';
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd b/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
index 374ccc129dc01a07aa6b38b5c702eddcccabe463..8bbd668ae51727ee5db89d2978280deced989a51 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
@@ -51,15 +51,19 @@ entity dp_stream_verify is
generic (
g_instance_nr : natural := 0;
-- flow control
- g_random_w : natural := 14; -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w : natural := 14;
g_pulse_active : natural := 1;
g_pulse_period : natural := 2;
- g_flow_control : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control : t_dp_flow_control_enum := e_active;
-- initializations
g_sync_period : natural := 10;
g_sync_offset : natural := 7;
- g_snk_in_cnt_max : t_dp_sosi_unsigned := c_dp_sosi_unsigned_rst; -- default 0 is no wrap
- g_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones; -- default only accept increment +1
+ -- default 0 is no wrap
+ g_snk_in_cnt_max : t_dp_sosi_unsigned := c_dp_sosi_unsigned_rst;
+ -- default only accept increment +1
+ g_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones;
-- specific
g_in_dat_w : natural := 32;
g_pkt_len : natural := 16
@@ -73,11 +77,14 @@ entity dp_stream_verify is
snk_in : in t_dp_sosi;
-- During stimuli
- verify_snk_in_enable : in t_dp_sosi_sl; -- enable to verify that the snk_in fields are incrementing
+ -- enable to verify that the snk_in fields are incrementing
+ verify_snk_in_enable : in t_dp_sosi_sl;
-- End of stimuli
- expected_snk_in : in t_dp_sosi; -- expected snk_in at verify_expected_snk_in_evt
- verify_expected_snk_in_evt : in t_dp_sosi_sl -- trigger to verify the expected_snk_in
+ -- expected snk_in at verify_expected_snk_in_evt
+ expected_snk_in : in t_dp_sosi;
+ -- trigger to verify the expected_snk_in
+ verify_expected_snk_in_evt : in t_dp_sosi_sl
);
end dp_stream_verify;
@@ -85,13 +92,15 @@ architecture tb of dp_stream_verify is
constant c_rl : natural := 1;
constant c_no_dut : boolean := true;
- signal random : std_logic_vector(g_random_w - 1 downto 0) := TO_UVEC(g_instance_nr, g_random_w); -- use different initialization to have different random sequences per stream
+ -- use different initialization to have different random sequences per stream
+ signal random : std_logic_vector(g_random_w - 1 downto 0) := TO_UVEC(g_instance_nr, g_random_w);
signal pulse : std_logic;
signal pulse_en : std_logic := '1';
signal i_snk_out : t_dp_siso := c_dp_siso_rdy;
signal prev_snk_out : t_dp_siso;
- signal hold_snk_in_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0); -- used to hold valid data for verify at verify_expected_snk_in_evt
+ -- used to hold valid data for verify at verify_expected_snk_in_evt
+ signal hold_snk_in_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0);
signal snk_in_data : std_logic_vector(g_in_dat_w - 1 downto 0);
signal prev_snk_in : t_dp_sosi;
diff --git a/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
index a66fd6e3029ac11a1f05c4d16b57d111bb609fba..03d5201d900d747a58f3c1a4e4fb7dad694bd5f6 100644
--- a/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
@@ -56,10 +56,14 @@ use work.tb_dp_pkg.all;
entity tb2_dp_demux is
generic (
-- Try flow control
- g_in_en : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_out_ready : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
- g_in_channel : natural := 2; -- used for g_mode 0 and 2
- g_nof_repeat : natural := 50; -- >= 1, number of frames
+ -- always active, random or pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_random;
+ -- used for g_mode 0 and 2
+ g_in_channel : natural := 2;
+ -- >= 1, number of frames
+ g_nof_repeat : natural := 50;
-- Try DEMUX, MUX settings
g_nof_streams : natural := 3;
g_mode_demux : natural := 2;
@@ -73,7 +77,8 @@ architecture tb of tb2_dp_demux is
constant c_data_w : natural := 16;
constant c_rl : natural := 1;
constant c_data_init : integer := 0;
- constant c_frame_len_init : natural := 1; -- >= 1
+ -- >= 1
+ constant c_frame_len_init : natural := 1;
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 7;
@@ -82,8 +87,10 @@ architecture tb of tb2_dp_demux is
signal rst : std_logic := '1';
-- Flow control
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -96,7 +103,8 @@ architecture tb of tb2_dp_demux is
signal demux_siso_arr : t_dp_siso_arr(0 to g_nof_streams - 1);
signal demux_sosi_arr : t_dp_sosi_arr(0 to g_nof_streams - 1);
- signal out_siso : t_dp_siso := c_dp_siso_hold; -- ready='0', xon='1'
+ -- ready='0', xon='1'
+ signal out_siso : t_dp_siso := c_dp_siso_hold;
signal out_sosi : t_dp_sosi;
-- Verification
@@ -171,15 +179,22 @@ begin
------------------------------------------------------------------------------
-- Verification logistics
- verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1'; -- enable verify after first output sop
- count_eop <= count_eop + 1 when rising_edge(clk) and out_sosi.eop = '1'; -- count number of output eop
- verify_done <= '1' when rising_edge(clk) and count_eop = g_nof_repeat; -- signal verify done after g_nof_repeat frames
+ -- enable verify after first output sop
+ verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1';
+ -- count number of output eop
+ count_eop <= count_eop + 1 when rising_edge(clk) and out_sosi.eop = '1';
+ -- signal verify done after g_nof_repeat frames
+ verify_done <= '1' when rising_edge(clk) and count_eop = g_nof_repeat;
-- Actual verification of the output streams
- proc_dp_verify_data("out_sosi.data", c_rl, clk, verify_en, out_siso.ready, out_sosi.valid, out_data, prev_out_data); -- Verify that the output is incrementing data, like the input stimuli
- proc_dp_verify_valid(c_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_sosi.valid); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_sop_and_eop(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, hold_out_sop); -- Verify that sop and eop come in pairs
- proc_dp_verify_value(e_equal, clk, verify_done, expected_out_data, prev_out_data); -- Verify that the stimuli have been applied at all
+ -- Verify that the output is incrementing data, like the input stimuli
+ proc_dp_verify_data("out_sosi.data", c_rl, clk, verify_en, out_siso.ready, out_sosi.valid, out_data, prev_out_data);
+ -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_valid(c_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_sosi.valid);
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, hold_out_sop);
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done, expected_out_data, prev_out_data);
-- Monitoring
out_data <= out_sosi.data(c_data_w - 1 downto 0);
@@ -228,8 +243,10 @@ begin
g_nof_input => g_nof_streams,
g_append_channel_lo => g_use_channel_lo,
g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_streams), -- FIFO is not used, but generic must match g_nof_input
- g_fifo_fill => array_init( 0, g_nof_streams) -- FIFO is not used, but generic must match g_nof_input
+ -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_size => array_init(1024, g_nof_streams),
+ -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_fill => array_init( 0, g_nof_streams)
)
port map (
rst => rst,
diff --git a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
index de5f5139e019b4afd37b3280ca0e1788e993a306..8377c7b3ed8c9cdb4084f9660ae6bedbc40690f4 100644
--- a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
@@ -60,13 +60,18 @@ use dp_lib.tb_dp_pkg.all;
entity tb2_dp_mux is
generic (
- g_in_en : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_out_ready : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_mode_mux : natural := 0; -- Use 0 or 1
+ -- always active, random or pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_active;
+ -- Use 0 or 1
+ g_mode_mux : natural := 0;
g_mux_use_fifo : boolean := true;
g_mux_fifo_fill : natural := 10;
- g_combined_demux : boolean := false; -- FALSE, can also use TRUE because the same tb out_siso is used for all outputs
- g_nof_repeat : natural := 10 -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
+ -- FALSE, can also use TRUE because the same tb out_siso is used for all outputs
+ g_combined_demux : boolean := false;
+ -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
+ g_nof_repeat : natural := 10
);
end tb2_dp_mux;
@@ -85,8 +90,10 @@ architecture tb of tb2_dp_mux is
constant c_sync_offset : natural := 2;
constant c_nof_type_max : natural := 5;
- constant c_nof_type : natural := 5; -- Second multiplexing level
- constant c_nof_input : natural := 3; -- Input multiplexing level
+ -- Second multiplexing level
+ constant c_nof_type : natural := 5;
+ -- Input multiplexing level
+ constant c_nof_input : natural := 3;
constant c_nof_streams : natural := c_nof_type * c_nof_input;
constant c_len_arr : t_natural_arr(0 to c_nof_type_max - 1) := (3, 1, 1, 50, 7);
@@ -94,8 +101,10 @@ architecture tb of tb2_dp_mux is
constant c_len_min : natural := 1;
constant c_nof_repeat_extra : natural := sel_a_b(g_mux_use_fifo, (c_nof_streams + g_mux_fifo_fill) / c_len_min, 0);
constant c_in_nof_repeat : natural := g_nof_repeat + c_nof_repeat_extra;
- constant c_in_repeat_arr_mode_mux_0 : t_natural_arr(0 to c_nof_streams - 1) := array_init(c_in_nof_repeat, c_nof_streams, 1); -- use g_nof_repeat+cK to have different expected_out_data(I,J) per input, to verify that the output demultiplexing works correct
- constant c_in_repeat_arr_mode_mux_1 : t_natural_arr(0 to c_nof_streams - 1) := array_init(c_in_nof_repeat, c_nof_streams); -- use g_nof_repeat for all inputs
+ -- use g_nof_repeat+cK to have different expected_out_data(I,J) per input, to verify that the output demultiplexing works correct
+ constant c_in_repeat_arr_mode_mux_0 : t_natural_arr(0 to c_nof_streams - 1) := array_init(c_in_nof_repeat, c_nof_streams, 1);
+ -- use g_nof_repeat for all inputs
+ constant c_in_repeat_arr_mode_mux_1 : t_natural_arr(0 to c_nof_streams - 1) := array_init(c_in_nof_repeat, c_nof_streams);
constant c_in_repeat_arr : t_natural_arr := sel_a_b(g_mode_mux = 0, c_in_repeat_arr_mode_mux_0, c_in_repeat_arr_mode_mux_1);
constant c_out_repeat_arr_mode_mux_0 : t_natural_arr(0 to c_nof_streams - 1) := array_init(g_nof_repeat, c_nof_streams, 1);
constant c_out_repeat_arr_mode_mux_1 : t_natural_arr(0 to c_nof_streams - 1) := array_init(g_nof_repeat, c_nof_streams);
@@ -116,8 +125,10 @@ architecture tb of tb2_dp_mux is
signal clk : std_logic := '1';
signal rst : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -229,16 +240,22 @@ begin
gen_verify : for I in 0 to c_nof_type-1 generate
gen_output : for J in 0 to c_nof_input - 1 generate
-- Verification logistics
- verify_en(I,J) <= '1' when rising_edge(clk) and out_sosi_2arr(I)(J).sop = '1'; -- verify enable after first output sop
- count_eop(I,J) <= count_eop(I,J) + 1 when rising_edge(clk) and out_sosi_2arr(I)(J).eop = '1'; -- count number of output eop
+ -- verify enable after first output sop
+ verify_en(I,J) <= '1' when rising_edge(clk) and out_sosi_2arr(I)(J).sop = '1';
+ -- count number of output eop
+ count_eop(I,J) <= count_eop(I,J) + 1 when rising_edge(clk) and out_sosi_2arr(I)(J).eop = '1';
verify_done(I,J) <= '1' when rising_edge(clk) and count_eop(I,J) = c_out_repeat_arr(I * c_nof_input + J) and count_eop(I,J) /= prev_count_eop(I,J) else '0';
tb_end_vec(I * c_nof_input + J) <= '1' when rising_edge(clk) and count_eop(I,J) = c_out_repeat_arr(I * c_nof_input + J);
-- Actual verification of the output streams
- proc_dp_verify_data("out_sosi_2arr.data", c_rl, clk, verify_en(I,J), out_siso_2arr(I)(J).ready, out_sosi_2arr(I)(J).valid, out_data(I,J), prev_out_data(I,J)); -- Verify that the output is incrementing data, like the input stimuli
- proc_dp_verify_valid(c_rl, clk, verify_en(I,J), out_siso_2arr(I)(J).ready, prev_out_ready(I,J), out_sosi_2arr(I)(J).valid); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_sop_and_eop(clk, out_sosi_2arr(I)(J).valid, out_sosi_2arr(I)(J).sop, out_sosi_2arr(I)(J).eop, hold_out_sop(I,J)); -- Verify that sop and eop come in pairs
- proc_dp_verify_value(e_equal, clk, verify_done(I,J), expected_out_data(I,J), prev_out_data(I,J)); -- Verify that the stimuli have been applied at all
+ -- Verify that the output is incrementing data, like the input stimuli
+ proc_dp_verify_data("out_sosi_2arr.data", c_rl, clk, verify_en(I,J), out_siso_2arr(I)(J).ready, out_sosi_2arr(I)(J).valid, out_data(I,J), prev_out_data(I,J));
+ -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_valid(c_rl, clk, verify_en(I,J), out_siso_2arr(I)(J).ready, prev_out_ready(I,J), out_sosi_2arr(I)(J).valid);
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(clk, out_sosi_2arr(I)(J).valid, out_sosi_2arr(I)(J).sop, out_sosi_2arr(I)(J).eop, hold_out_sop(I,J));
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done(I,J), expected_out_data(I,J), prev_out_data(I,J));
proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en(I,J), out_sosi_2arr(I)(J).sync, out_sosi_2arr(I)(J).sop, out_sosi_2arr(I)(J).bsn);
end generate;
end generate;
@@ -261,8 +278,10 @@ begin
g_data_w => c_data_w,
g_use_bsn => c_use_bsn,
g_use_sync => c_use_sync,
- g_fifo_size => array_init( 1024, c_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_size => array_init( 1024, c_nof_input),
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_input)
)
port map (
rst => rst,
@@ -287,12 +306,15 @@ begin
g_use_fifo => g_mux_use_fifo,
g_bsn_w => c_data_w,
g_data_w => c_data_w,
- g_in_channel_w => c_channel_input_w, -- pass channel due to u_input_mux
+ -- pass channel due to u_input_mux
+ g_in_channel_w => c_channel_input_w,
g_use_in_channel => g_mux_use_fifo,
g_use_bsn => c_use_bsn,
g_use_sync => c_use_sync,
- g_fifo_size => array_init( 1024, c_nof_type), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_type) -- must match g_nof_input, even when g_use_fifo=FALSE
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_size => array_init( 1024, c_nof_type),
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_type)
)
port map (
rst => rst,
diff --git a/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
index 47b21dc98e8f1775f5560ee234ef8ac435f5a843..e7211c4e51cd73c7c43ca19f5dbf6a7c48a42bee 100644
--- a/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
@@ -47,24 +47,30 @@ use work.tb_dp_pkg.all;
entity tb3_dp_demux is
generic (
-- Try flow control
- g_in_en : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_out_ready : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
- g_nof_repeat : natural := 50; -- >= 1, number of frames
+ -- always active, random or pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_random;
+ -- >= 1, number of frames
+ g_nof_repeat : natural := 50;
-- Try MUX settings
g_nof_outputs : natural := 3
);
end tb3_dp_demux;
architecture tb of tb3_dp_demux is
- constant c_sel_ctrl_pkt : boolean := true; -- TRUE requires: c_mode_demux = 2 and c_combined_demux = FALSE
+ -- TRUE requires: c_mode_demux = 2 and c_combined_demux = FALSE
+ constant c_sel_ctrl_pkt : boolean := true;
constant c_mode_demux : natural := 2;
constant c_use_channel_lo : boolean := false;
- constant c_combined_demux : boolean := false; -- or TRUE
+ -- or TRUE
+ constant c_combined_demux : boolean := false;
constant c_data_w : natural := 16;
constant c_rl : natural := 1;
constant c_data_init : integer := 0;
- constant c_frame_len_init : natural := 1; -- >= 1
+ -- >= 1
+ constant c_frame_len_init : natural := 1;
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 7;
@@ -73,8 +79,10 @@ architecture tb of tb3_dp_demux is
signal rst : std_logic := '1';
-- Flow control
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -87,7 +95,8 @@ architecture tb of tb3_dp_demux is
signal out_siso_arr : t_dp_siso_arr(0 to g_nof_outputs - 1);
signal out_sosi_arr : t_dp_sosi_arr(0 to g_nof_outputs - 1);
- signal out_siso : t_dp_siso := c_dp_siso_hold; -- ready='0', xon='1'
+ -- ready='0', xon='1'
+ signal out_siso : t_dp_siso := c_dp_siso_hold;
signal out_sosi : t_dp_sosi;
-- Verification
@@ -165,15 +174,22 @@ begin
------------------------------------------------------------------------------
-- Verification logistics
- verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1'; -- enable verify after first output sop
- count_eop <= count_eop + 1 when rising_edge(clk) and out_sosi.eop = '1'; -- count number of output eop
- verify_done <= '1' when rising_edge(clk) and count_eop = g_nof_repeat; -- signal verify done after g_nof_repeat frames
+ -- enable verify after first output sop
+ verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1';
+ -- count number of output eop
+ count_eop <= count_eop + 1 when rising_edge(clk) and out_sosi.eop = '1';
+ -- signal verify done after g_nof_repeat frames
+ verify_done <= '1' when rising_edge(clk) and count_eop = g_nof_repeat;
-- Actual verification of the output streams
- proc_dp_verify_data("out_sosi.data", c_rl, clk, verify_en, out_siso.ready, out_sosi.valid, out_data, prev_out_data); -- Verify that the output is incrementing data, like the input stimuli
- proc_dp_verify_valid(c_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_sosi.valid); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_sop_and_eop(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, hold_out_sop); -- Verify that sop and eop come in pairs
- proc_dp_verify_value(e_equal, clk, verify_done, expected_out_data, prev_out_data); -- Verify that the stimuli have been applied at all
+ -- Verify that the output is incrementing data, like the input stimuli
+ proc_dp_verify_data("out_sosi.data", c_rl, clk, verify_en, out_siso.ready, out_sosi.valid, out_data, prev_out_data);
+ -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_valid(c_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_sosi.valid);
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, hold_out_sop);
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done, expected_out_data, prev_out_data);
-- Monitoring
out_data <= out_sosi.data(c_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
index 535656ce91e41885071b00fdc6466233f4bf37f7..f5bf4ababd6396c9525d6626115d5da5f2584db6 100644
--- a/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
@@ -44,9 +44,12 @@ use work.tb_dp_pkg.all;
entity tb3_dp_mux is
generic (
-- Try flow control
- g_in_en : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_out_ready : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
- g_nof_repeat : natural := 50; -- >= 1, number of frames
+ -- always active, random or pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_random;
+ -- >= 1, number of frames
+ g_nof_repeat : natural := 50;
-- Try MUX settings
g_nof_inputs : natural := 3
);
@@ -59,7 +62,8 @@ architecture tb of tb3_dp_mux is
constant c_data_w : natural := 16;
constant c_rl : natural := 1;
constant c_data_init : integer := 0;
- constant c_frame_len_init : natural := 1; -- >= 1
+ -- >= 1
+ constant c_frame_len_init : natural := 1;
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 7;
@@ -68,8 +72,10 @@ architecture tb of tb3_dp_mux is
signal rst : std_logic := '1';
-- Flow control
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -82,7 +88,8 @@ architecture tb of tb3_dp_mux is
signal in_siso_arr : t_dp_siso_arr(0 to g_nof_inputs - 1);
signal in_sosi_arr : t_dp_sosi_arr(0 to g_nof_inputs - 1);
- signal out_siso : t_dp_siso := c_dp_siso_hold; -- ready='0', xon='1'
+ -- ready='0', xon='1'
+ signal out_siso : t_dp_siso := c_dp_siso_hold;
signal out_sosi : t_dp_sosi;
-- Verification
@@ -168,15 +175,22 @@ begin
------------------------------------------------------------------------------
-- Verification logistics
- verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1'; -- enable verify after first output sop
- count_eop <= count_eop + 1 when rising_edge(clk) and out_sosi.eop = '1'; -- count number of output eop
- verify_done <= '1' when rising_edge(clk) and count_eop = g_nof_repeat; -- signal verify done after g_nof_repeat frames
+ -- enable verify after first output sop
+ verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1';
+ -- count number of output eop
+ count_eop <= count_eop + 1 when rising_edge(clk) and out_sosi.eop = '1';
+ -- signal verify done after g_nof_repeat frames
+ verify_done <= '1' when rising_edge(clk) and count_eop = g_nof_repeat;
-- Actual verification of the output streams
- proc_dp_verify_data("out_sosi.data", c_rl, clk, verify_en, out_siso.ready, out_sosi.valid, out_data, prev_out_data); -- Verify that the output is incrementing data, like the input stimuli
- proc_dp_verify_valid(c_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_sosi.valid); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_sop_and_eop(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, hold_out_sop); -- Verify that sop and eop come in pairs
- proc_dp_verify_value(e_equal, clk, verify_done, expected_out_data, prev_out_data); -- Verify that the stimuli have been applied at all
+ -- Verify that the output is incrementing data, like the input stimuli
+ proc_dp_verify_data("out_sosi.data", c_rl, clk, verify_en, out_siso.ready, out_sosi.valid, out_data, prev_out_data);
+ -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_valid(c_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_sosi.valid);
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, hold_out_sop);
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done, expected_out_data, prev_out_data);
-- Monitoring
out_data <= out_sosi.data(c_data_w - 1 downto 0);
@@ -196,8 +210,10 @@ begin
g_append_channel_lo => c_use_channel_lo,
-- Input FIFO
g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_inputs), -- FIFO is not used, but generic must match g_nof_input
- g_fifo_fill => array_init( 0, g_nof_inputs) -- FIFO is not used, but generic must match g_nof_input
+ -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_size => array_init(1024, g_nof_inputs),
+ -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_fill => array_init( 0, g_nof_inputs)
)
port map (
rst => rst,
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
index b8030bfb668188ed5d08feab8ba81c3d93ccd442..2302893480bb2c69acaed042cd67ba18f643a958 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
@@ -65,7 +65,8 @@ architecture tb of tb_dp_block_from_mm is
constant c_ram : t_c_mem := (1, c_ram_adr_w, c_word_w, 2**c_ram_adr_w, '0');
- constant c_init : natural := 42; -- inital data counter value, should be > 0 for better test coverage.
+ -- inital data counter value, should be > 0 for better test coverage.
+ constant c_init : natural := 42;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
@@ -109,7 +110,8 @@ begin
-- STIMULI
------------------------------------------------------------------------------
- start_address_dly <= start_address when rising_edge(clk); -- dp_block_to_mm is 1 clock behind so set address also 1 clock later.
+ -- dp_block_to_mm is 1 clock behind so set address also 1 clock later.
+ start_address_dly <= start_address when rising_edge(clk);
p_init_ram : process
begin
@@ -143,7 +145,8 @@ begin
stop_address <= start_address + (g_nof_data - 1) * g_step_size + g_data_size - 1;
proc_common_wait_until_high(clk, block_done);
end loop;
- proc_common_wait_some_cycles(clk, 1); -- Needed for dp_block_to_mm to proccess last word.
+ -- Needed for dp_block_to_mm to proccess last word.
+ proc_common_wait_some_cycles(clk, 1);
transfer_done <= '1';
wait;
end process;
@@ -191,7 +194,8 @@ begin
assert rd_data - c_init <= stop_address report "wrong RAM values, greater than block size" severity ERROR;
rd_nxt_data <= rd_nxt_data + 1;
end if;
- if ram_rd_val = '0' and ram_prev_rd_val = '1' then -- If ram_rd_val goes from hi tot lo.
+ -- If ram_rd_val goes from hi tot lo.
+ if ram_rd_val = '0' and ram_prev_rd_val = '1' then
assert rd_data - c_init = stop_address report "wrong last RAM values, not same as block size" severity ERROR;
end if;
end loop;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
index 0e4fc37681d2d540ac123e6169f513843cc75464..3f69df632ee4b2439c9745c627e451ecfe839638 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
@@ -40,8 +40,10 @@ entity tb_dp_block_gen is
g_use_src_in : boolean := false;
g_nof_data_per_block : natural := 11;
g_nof_blk_per_sync : natural := 5;
- g_enable : t_dp_flow_control_enum := e_pulse; -- always e_active or e_pulse block generator enable
- g_out_ready : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- always e_active or e_pulse block generator enable
+ g_enable : t_dp_flow_control_enum := e_pulse;
+ -- always e_active, e_random or e_pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_active;
g_nof_repeat : natural := 100
);
end tb_dp_block_gen;
@@ -58,7 +60,8 @@ architecture tb of tb_dp_block_gen is
signal rst : std_logic := '1';
signal sl1 : std_logic := '1';
- signal random : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(15 downto 0) := (others => '0');
signal pulse : std_logic;
signal pulse_en : std_logic := '1';
@@ -145,7 +148,8 @@ begin
begin
verify_bsn_en <= '0';
proc_common_wait_until_high(clk, enable);
- proc_common_wait_some_cycles(clk, 10); -- first sop will have occured, so start verification for subsequent BSN
+ -- first sop will have occured, so start verification for subsequent BSN
+ proc_common_wait_some_cycles(clk, 10);
while enable = '1' loop
verify_bsn_en <= '1';
wait until rising_edge(clk);
@@ -161,8 +165,10 @@ begin
proc_dp_verify_value("out_sosi.eop", clk, verify_done, sl1, verify_eop);
-- Verify some general streaming interface properties
- proc_dp_verify_valid(c_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_sosi.valid); -- Verify that the out_sosi valid fits with the ready latency
- proc_dp_verify_gap_invalid(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, out_gap); -- Verify that the out_sosi valid is low between blocks
+ -- Verify that the out_sosi valid fits with the ready latency
+ proc_dp_verify_valid(c_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_sosi.valid);
+ -- Verify that the out_sosi valid is low between blocks
+ proc_dp_verify_gap_invalid(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, out_gap);
proc_dp_verify_data("BSN", clk, verify_bsn_en, out_sosi.sop, out_sosi.bsn, prev_out_sosi.bsn);
-- Verify intervals
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
index 52b11dd5ce321c0ea9cc66a9cb3fbaa03a870c2b..48200e76cba94e42aa3b1f51024f56779dee6f8f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
@@ -44,8 +44,10 @@ entity tb_dp_block_gen_valid_arr is
g_check_input_sync : boolean := true;
g_nof_pages_bsn : natural := 0;
g_restore_global_bsn : boolean := false;
- g_enable : t_dp_flow_control_enum := e_active; -- always e_active or e_pulse block generator enable
- g_flow_control : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control for input valid
+ -- always e_active or e_pulse block generator enable
+ g_enable : t_dp_flow_control_enum := e_active;
+ -- always e_active, e_random or e_pulse flow control for input valid
+ g_flow_control : t_dp_flow_control_enum := e_active;
g_nof_repeat : natural := 1000
);
end tb_dp_block_gen_valid_arr;
@@ -55,14 +57,17 @@ architecture tb of tb_dp_block_gen_valid_arr is
constant c_nof_valid_per_sync : natural := g_nof_blk_per_sync * g_nof_data_per_block;
constant c_nof_valid_per_enable : natural := 3 * c_nof_valid_per_sync + 1;
- constant c_dsp_latency : natural := 1; -- >= 1 block and typically << g_nof_blk_per_sync blocks
+ -- >= 1 block and typically << g_nof_blk_per_sync blocks
+ constant c_dsp_latency : natural := 1;
- constant c_sync_offset : natural := 1; -- 0, < g_nof_blk_per_sync
+ -- 0, < g_nof_blk_per_sync
+ constant c_sync_offset : natural := 1;
constant c_bsn_init : natural := 37;
constant c_channel_init : natural := 17;
constant c_err_init : natural := 13;
- constant c_input_bsn_no_wrap : natural := 0; -- use 0 to indicate no max, so no wrap
+ -- use 0 to indicate no max, so no wrap
+ constant c_input_bsn_no_wrap : natural := 0;
constant c_input_bsn_gap : natural := g_nof_blk_per_sync;
constant c_local_bsn_max : natural := g_nof_blk_per_sync - 1;
constant c_local_bsn_gap : natural := 2;
@@ -136,7 +141,8 @@ begin
-- input data
u_dp_stream_stimuli : entity work.dp_stream_stimuli
generic map (
- g_flow_control => g_flow_control, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control,
-- initializations
g_sync_period => g_nof_blk_per_sync,
g_sync_offset => c_sync_offset,
@@ -160,15 +166,19 @@ begin
src_out => stimuli_sosi,
-- End of stimuli
- last_snk_in => OPEN, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => OPEN, -- trigger verify to verify the last_snk_in
- tb_end => tb_input_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ -- expected verify_snk_in after end of stimuli
+ last_snk_in => OPEN,
+ -- trigger verify to verify the last_snk_in
+ last_snk_in_evt => OPEN,
+ -- signal end of tb as far as this dp_stream_stimuli is concerned
+ tb_end => tb_input_end
);
-- Use dp_pipeline to model the latency introduced by upstream DSP components
u_dp_pipeline : entity work.dp_pipeline
generic map (
- g_pipeline => c_dsp_latency -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline => c_dsp_latency
)
port map (
rst => rst,
@@ -200,9 +210,11 @@ begin
verify_bsn_en <= '0';
proc_common_wait_until_high(clk, enable);
proc_common_wait_until_hi_lo(clk, out_sosi.sop);
- proc_common_wait_until_hi_lo(clk, out_sosi.sop); -- first two sop will have occured, so start verification for subsequent BSN
+ -- first two sop will have occured, so start verification for subsequent BSN
+ proc_common_wait_until_hi_lo(clk, out_sosi.sop);
if g_check_input_sync = true or g_nof_pages_bsn > 0 then
- proc_common_wait_until_hi_lo(clk, out_sosi.sync); -- if necessary also wait for first sync
+ -- if necessary also wait for first sync
+ proc_common_wait_until_hi_lo(clk, out_sosi.sync);
end if;
while enable = '1' loop
verify_bsn_en <= '1';
@@ -226,7 +238,8 @@ begin
proc_dp_verify_value("out_sosi.err", e_equal, clk, verify_done, exp_err, out_sosi.err);
-- Verify some general streaming interface properties
- proc_dp_verify_gap_invalid(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, out_gap); -- Verify that the out_sosi valid is low between blocks
+ -- Verify that the out_sosi valid is low between blocks
+ proc_dp_verify_gap_invalid(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, out_gap);
-- define out_sosi_local with sync = '0' to be able to verify local bsn incrementing during rest of sync interval
p_out_sosi_local : process(out_sosi)
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
index 91d7db77387553a526cad2717875624b73b592fd..45f590723a8786b35d81723eb0b013857f5d66b8 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
@@ -53,7 +53,8 @@ use work.tb_dp_pkg.all;
entity tb_dp_block_reshape is
generic (
- g_pipeline : natural := 1 -- use 0 or 1
+ -- use 0 or 1
+ g_pipeline : natural := 1
);
end tb_dp_block_reshape;
@@ -79,10 +80,12 @@ architecture tb of tb_dp_block_reshape is
signal stimuli_siso : t_dp_siso;
signal reshape_sosi : t_dp_sosi;
signal reshape_siso : t_dp_siso;
- signal reshape_index_arr : t_natural_arr(1 downto 0); -- [1] sop index, [0] valid index
+ -- [1] sop index, [0] valid index
+ signal reshape_index_arr : t_natural_arr(1 downto 0);
signal verify_sosi : t_dp_sosi;
signal verify_siso : t_dp_siso := c_dp_siso_rdy;
- signal verify_index_arr : t_natural_arr(1 downto 0); -- [1] sop index, [0] valid index
+ -- [1] sop index, [0] valid index
+ signal verify_index_arr : t_natural_arr(1 downto 0);
signal pipeline_sosi : t_dp_sosi;
signal pipeline_siso : t_dp_siso := c_dp_siso_rdy;
begin
@@ -121,7 +124,8 @@ begin
------------------------------------------------------------------------------
u_reshape : entity work.dp_block_reshape
generic map (
- g_input_nof_data_per_sync => c_input_nof_data_per_sync, -- nof data per input sync interval, used only for sop_index
+ -- nof data per input sync interval, used only for sop_index
+ g_input_nof_data_per_sync => c_input_nof_data_per_sync,
g_reshape_nof_data_per_blk => c_reshape_nof_data_per_blk,
g_pipeline_src_out => g_pipeline,
g_pipeline_src_in => 0
@@ -135,12 +139,14 @@ begin
src_out => reshape_sosi,
src_in => reshape_siso,
- src_index_arr => reshape_index_arr -- [1] sop index, [0] valid index
+ -- [1] sop index, [0] valid index
+ src_index_arr => reshape_index_arr
);
u_reshape_back : entity work.dp_block_reshape
generic map (
- g_input_nof_data_per_sync => c_input_nof_data_per_sync, -- nof data per input sync interval, used only for sop_index
+ -- nof data per input sync interval, used only for sop_index
+ g_input_nof_data_per_sync => c_input_nof_data_per_sync,
g_reshape_nof_data_per_blk => c_input_nof_data_per_blk,
g_pipeline_src_out => 0,
g_pipeline_src_in => g_pipeline
@@ -154,7 +160,8 @@ begin
src_out => verify_sosi,
src_in => verify_siso,
- src_index_arr => verify_index_arr -- [1] sop index, [0] valid index
+ -- [1] sop index, [0] valid index
+ src_index_arr => verify_index_arr
);
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
index d03c07a6ad4d70297f78a745c37894c86b227ce5..63ca33023cd2bea9633b7097c632e71ffe56e3b7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
@@ -50,10 +50,13 @@ use work.tb_dp_pkg.all;
entity tb_dp_block_reshape_sync is
generic (
g_input_nof_data_per_blk : natural := 9;
- g_input_nof_blk_per_sync : natural := 12; -- 6 * 108 = 12 * 9
+ -- 6 * 108 = 12 * 9
+ g_input_nof_blk_per_sync : natural := 12;
g_reshape_nof_data_per_blk : natural := 18;
- g_reshape_nof_blk_per_sync : natural := 3; -- 12 * 54 = 3 * 18
- g_reshape_bsn : boolean := true; -- when TRUE reshape BSN else when FALSE pass on BSN
+ -- 12 * 54 = 3 * 18
+ g_reshape_nof_blk_per_sync : natural := 3;
+ -- when TRUE reshape BSN else when FALSE pass on BSN
+ g_reshape_bsn : boolean := true;
g_pipeline_src_out : natural := 1;
g_pipeline_src_in : natural := 0
);
@@ -165,7 +168,8 @@ begin
u_pipeline_dut : entity work.dp_pipeline
generic map (
- g_pipeline => c_pipeline -- = c_pipeline in u_reshape_dut
+ -- = c_pipeline in u_reshape_dut
+ g_pipeline => c_pipeline
)
port map (
rst => rst,
@@ -180,7 +184,8 @@ begin
u_pipeline_total : entity work.dp_pipeline
generic map (
- g_pipeline => c_pipeline * 2 -- = c_pipeline in u_reshape_dut + c_pipeline in u_reshape_back
+ -- = c_pipeline in u_reshape_dut + c_pipeline in u_reshape_back
+ g_pipeline => c_pipeline * 2
)
port map (
rst => rst,
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
index 9ec17af29ee826356a73a2f2736357718c22de97..ec9d477ceab438b087b0ea7bab7a8e7203acb0ac 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
@@ -46,7 +46,8 @@ entity tb_dp_block_validate_bsn_at_sync is
generic (
g_nof_blocks_per_sync : natural := 5;
g_nof_data_per_blk : natural := 6;
- g_bsn_init : natural := 7 -- >= g_nof_blocks_per_sync for discarded sync, < g_nof_blocks_per_sync for no discarded sync.
+ -- >= g_nof_blocks_per_sync for discarded sync, < g_nof_blocks_per_sync for no discarded sync.
+ g_bsn_init : natural := 7
);
end tb_dp_block_validate_bsn_at_sync;
@@ -66,7 +67,8 @@ architecture tb of tb_dp_block_validate_bsn_at_sync is
-- the future. Hence this c_check_channel value will occur once in the tb,
-- because stimuli_sosi.channel keeps incrementing. Choosing c_check_channel
-- such that it corresponds with a channel from stimuli on a sync pulse.
- constant c_check_channel : natural := g_nof_blocks_per_sync; -- can be c_check_channel MOD g_nof_blocks_per_sync = 0 but not larger than c_nof_blk.
+ -- can be c_check_channel MOD g_nof_blocks_per_sync = 0 but not larger than c_nof_blk.
+ constant c_check_channel : natural := g_nof_blocks_per_sync;
signal dp_clk : std_logic := '1';
signal mm_clk : std_logic := '1';
@@ -192,7 +194,8 @@ begin
variable v_valid_blk : boolean := true;
begin
if rising_edge(dp_clk) then
- if reference_sosi.sop = '1' then -- Decide for each block if it should be valid.
+ -- Decide for each block if it should be valid.
+ if reference_sosi.sop = '1' then
-- A block can only be discarded if its channel field corresponds with the check_channel.
if g_bsn_init >= g_nof_blocks_per_sync and TO_UINT(reference_sosi.channel) = c_check_channel then
v_valid_blk := false;
@@ -201,9 +204,11 @@ begin
end if;
end if;
- if v_valid_blk then -- we expect a block
+ -- we expect a block
+ if v_valid_blk then
assert verify_sosi = reference_sosi report "Unexpected difference between in / out sosi" severity ERROR;
- else -- we expect no block
+ -- we expect no block
+ else
assert verify_sosi.valid = '0' report "Wrong, valid is not '0' which is unexpected." severity ERROR;
assert verify_sosi.sop = '0' report "Wrong, sop is not '0' which is unexpected." severity ERROR;
assert verify_sosi.eop = '0' report "Wrong, eop is not '0' which is unexpected." severity ERROR;
@@ -222,9 +227,11 @@ begin
proc_mem_mm_bus_rd(0, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
- if g_bsn_init >= g_nof_blocks_per_sync then -- should have 1 discarded sync
+ -- should have 1 discarded sync
+ if g_bsn_init >= g_nof_blocks_per_sync then
assert 1 = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0)) report "Wrong discarded sync count" severity ERROR;
- else -- 0 discarded sync
+ -- 0 discarded sync
+ else
assert 0 = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0)) report "Wrong discarded sync count" severity ERROR;
end if;
proc_common_wait_some_cycles(dp_clk, 100);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
index fd24928a064a105a47c92b0df9334a648f853af9..3e5d259719b97561c6d01db357054310770436a9 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
@@ -199,7 +199,8 @@ begin
p_verify : process(dp_clk)
begin
if rising_edge(dp_clk) then
- if reference_cnt_reg = 0 then -- no errors so we expect a block
+ -- no errors so we expect a block
+ if reference_cnt_reg = 0 then
assert verify_sosi.valid = reference_sosi.valid report "Unexpected difference between in / out sosi" severity ERROR;
assert verify_sosi.sop = reference_sosi.sop report "Unexpected difference between in / out sosi" severity ERROR;
assert verify_sosi.eop = reference_sosi.eop report "Unexpected difference between in / out sosi" severity ERROR;
@@ -208,7 +209,8 @@ begin
assert verify_sosi.bsn = reference_sosi.bsn report "Unexpected difference between in / out sosi" severity ERROR;
assert verify_sosi.empty = reference_sosi.empty report "Unexpected difference between in / out sosi" severity ERROR;
assert verify_sosi.sync = reference_sosi.sync report "Unexpected difference between in / out sosi" severity ERROR;
- else -- we expect no block as there are errors
+ -- we expect no block as there are errors
+ else
assert verify_sosi.valid = '0' report "Wrong, valid is not '0' which is unexpected." severity ERROR;
assert verify_sosi.sop = '0' report "Wrong, sop is not '0' which is unexpected." severity ERROR;
assert verify_sosi.eop = '0' report "Wrong, eop is not '0' which is unexpected." severity ERROR;
@@ -217,8 +219,10 @@ begin
end process;
p_verify_mm : process
- variable v_X : integer := 0; -- variable to hold 2**I * ((c_nof_blk-1) / 2**(I+1))
- variable v_Y : integer := 0; -- variable to hold (c_nof_blk-1) + 1 - (2 * v_X) - 2**I
+ -- variable to hold 2**I * ((c_nof_blk-1) / 2**(I+1))
+ variable v_X : integer := 0;
+ -- variable to hold (c_nof_blk-1) + 1 - (2 * v_X) - 2**I
+ variable v_Y : integer := 0;
-- v_N is a variable to hold the expected cnt number for the error counter registers = v_X + v_Y for v_Y > 0, else = v_x.
-- this can be calculated as the dp error field is a counter up to c_nof_blk - 1.
variable v_N : integer := 0;
@@ -240,14 +244,16 @@ begin
for I in 0 to g_nof_err_counts - 1 loop
v_X := 2**I * ((c_nof_blk - 1) / 2**(I + 1));
v_Y := c_nof_blk - 2 * v_X - 2**I;
- if v_Y < 0 then -- v_N = v_X + v_Y only holds for v_Y > 0.
+ -- v_N = v_X + v_Y only holds for v_Y > 0.
+ if v_Y < 0 then
v_N := v_X;
else
v_N := v_X + v_Y;
end if;
if v_N > c_max_cnt then
- v_N := c_max_cnt; -- the DUT clips the counters
+ -- the DUT clips the counters
+ v_N := c_max_cnt;
end if;
proc_mem_mm_bus_rd(I, mm_clk, reg_miso, reg_mosi);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
index 2ecc70415eef47ed08d8590555499cf4b2c6cf64..caa1b80879967c898d2e62d3b8889386eba1a8d7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
@@ -154,10 +154,12 @@ begin
begin
if rising_edge(clk) then
if reference_sosi.valid = '1' then
- if g_expected_length = g_nof_data_per_blk then -- in sosi should be identical to out sosi
+ -- in sosi should be identical to out sosi
+ if g_expected_length = g_nof_data_per_blk then
assert verify_sosi = reference_sosi report "Unexpected difference between in / out sosi" severity ERROR;
- elsif g_expected_length < g_nof_data_per_blk then -- expect an err bit to be set and the block length to be limited to g_expected_length
+ -- expect an err bit to be set and the block length to be limited to g_expected_length
+ elsif g_expected_length < g_nof_data_per_blk then
if reference_cnt < g_expected_length - 1 then
assert verify_sosi = reference_sosi report "Wrong block while reference_cnt < g_expected_length-1" severity ERROR;
elsif reference_cnt = g_expected_length - 1 then
@@ -169,11 +171,13 @@ begin
assert verify_sosi.sop = reference_sosi.sop report "Wrong sop, while reference_cnt = g_expected_length-1" severity ERROR;
assert verify_sosi.eop = '1' report "Wrong eop, while reference_cnt = g_expected_length-1" severity ERROR;
assert verify_sosi.err = c_exp_err report "Wrong err, while reference_cnt = g_expected_length-1" severity ERROR;
- else -- reference_cnt > g_expected_length-1
+ -- reference_cnt > g_expected_length-1
+ else
assert verify_sosi.valid = '0' report "Wrong, valid should be '0' when reference_cnt > g_expected_length-1" severity ERROR;
end if;
- else -- g_expected_length > g_nof_data_per_blk
+ -- g_expected_length > g_nof_data_per_blk
+ else
-- Expected an err bit to be set at eop
if reference_cnt = g_nof_data_per_blk - 1 then
assert verify_sosi.sync = reference_sosi.sync report "Wrong sync, while reference_cnt = g_nof_data_per_blk-1" severity ERROR;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
index 5b799b6b68ef81521aa853c858c3d117555e1925..8be0952cc13ed6fcfaa46830ce1ab1b7a70d72a1 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
@@ -45,12 +45,17 @@ entity tb_dp_bsn_align is
generic (
g_block_size : natural := 11;
g_diff_delay : natural := 20;
- g_diff_bsn : natural := 3; -- g_diff_bsn = g_bsn_latency can just be aligned
- g_nof_input : natural := 16; -- >= 1
+ -- g_diff_bsn = g_bsn_latency can just be aligned
+ g_diff_bsn : natural := 3;
+ -- >= 1
+ g_nof_input : natural := 16;
g_bsn_latency : natural := 3;
- g_bsn_request_pipeline : natural := 2; -- = 1, 2, ..., c_bsn_nof_stages, requested total pipelining of the BSN max and BSN min operation
- g_out_ready : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
- g_nof_repeat : natural := 100 -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
+ -- = 1, 2, ..., c_bsn_nof_stages, requested total pipelining of the BSN max and BSN min operation
+ g_bsn_request_pipeline : natural := 2;
+ -- always e_active, e_random or e_pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_active;
+ -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
+ g_nof_repeat : natural := 100
);
end tb_dp_bsn_align;
@@ -70,10 +75,13 @@ architecture tb of tb_dp_bsn_align is
constant c_gap_size : natural := 10;
constant c_block_period : natural := g_block_size + c_gap_size;
- constant c_xoff_timeout : natural := c_block_period * g_bsn_latency * 2; -- xoff timeout to recover for next alignment attempt
- constant c_sop_timeout : natural := c_block_period * g_bsn_latency; -- sop timeout to end current aligment attempt
+ -- xoff timeout to recover for next alignment attempt
+ constant c_xoff_timeout : natural := c_block_period * g_bsn_latency * 2;
+ -- sop timeout to end current aligment attempt
+ constant c_sop_timeout : natural := c_block_period * g_bsn_latency;
- constant c_event_input : natural := smallest(1, g_nof_input - 1); -- select special event input at which the event will apply, use >= g_nof_input to disable the special events
+ -- select special event input at which the event will apply, use >= g_nof_input to disable the special events
+ constant c_event_input : natural := smallest(1, g_nof_input - 1);
type t_data_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(c_data_w - 1 downto 0);
type t_bsn_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(c_bsn_w - 1 downto 0);
@@ -88,7 +96,8 @@ architecture tb of tb_dp_bsn_align is
signal rst : std_logic := '1';
signal sl1 : std_logic := '1';
- signal random : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(15 downto 0) := (others => '0');
signal pulse : std_logic;
signal pulse_en : std_logic := '1';
@@ -136,11 +145,14 @@ architecture tb of tb_dp_bsn_align is
signal verify_extra_end : std_logic := '0';
signal bsn_diff : integer;
signal bsn_offset : integer;
- signal bsn_event : std_logic := '0'; -- pulse '1' triggers a BSN offset for an input
+ -- pulse '1' triggers a BSN offset for an input
+ signal bsn_event : std_logic := '0';
signal bsn_event_ack_arr : std_logic_vector(g_nof_input - 1 downto 0) := (others => '0');
signal bsn_event_ack : std_logic;
- signal in_en_event : std_logic := '0'; -- pulse '1' indicates that the input enables in in_en_arr have been updated
- signal in_en_arr : std_logic_vector(g_nof_input - 1 downto 0) := (others => '1'); -- default all inputs are enabled
+ -- pulse '1' indicates that the input enables in in_en_arr have been updated
+ signal in_en_event : std_logic := '0';
+ -- default all inputs are enabled
+ signal in_en_arr : std_logic_vector(g_nof_input - 1 downto 0) := (others => '1');
begin
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -192,14 +204,16 @@ begin
proc_dp_gen_block_data(c_rl, true, c_data_w, c_data_w, v_data, 0, 0, g_block_size, v_channel, v_err, v_sync, v_bsn, clk, in_en_arr(I), in_siso_arr(I), in_sosi_arr(I));
v_bsn := INCR_UVEC(v_bsn, 1);
v_data := v_data + g_block_size;
- proc_common_wait_some_cycles(clk, c_gap_size); -- create gap between frames
+ -- create gap between frames
+ proc_common_wait_some_cycles(clk, c_gap_size);
end loop;
-- End of default stimuli
expected_out_bsn(I) <= INCR_UVEC(v_bsn, -1);
expected_out_data(I) <= TO_UVEC(v_data - 1, c_data_w);
- proc_common_wait_some_cycles(clk, 100); -- depends on stream control
+ -- depends on stream control
+ proc_common_wait_some_cycles(clk, 100);
default_end_arr(I) <= '1';
verify_done_arr(I) <= '1';
proc_common_wait_some_cycles(clk, 1);
@@ -220,7 +234,8 @@ begin
bsn_event_ack_arr(I) <= '1';
end if;
v_data := v_data + g_block_size;
- proc_common_wait_some_cycles(clk, c_gap_size); -- create gap between frames
+ -- create gap between frames
+ proc_common_wait_some_cycles(clk, c_gap_size);
end loop;
-- End of extra stimuli
@@ -316,17 +331,20 @@ begin
tb_state <= s_disable_one_input;
verify_dis_arr <= (others => '1');
in_en_event <= '1';
- in_en_arr(c_event_input) <= '0'; -- switch an input off
+ -- switch an input off
+ in_en_arr(c_event_input) <= '0';
proc_common_wait_some_cycles(clk, 1);
in_en_event <= '0';
proc_common_wait_some_cycles(clk, 100);
verify_dis_arr <= (others => '0');
- proc_common_wait_some_cycles(clk, 2000); -- keep this input off for a while
+ -- keep this input off for a while
+ proc_common_wait_some_cycles(clk, 2000);
tb_state <= s_enable_inputs;
verify_dis_arr <= (others => '1');
in_en_event <= '1';
- in_en_arr(c_event_input) <= '1'; -- switch this input on
+ -- switch this input on
+ in_en_arr(c_event_input) <= '1';
proc_common_wait_some_cycles(clk, 1);
in_en_event <= '0';
proc_common_wait_some_cycles(clk, 100);
@@ -335,7 +353,8 @@ begin
tb_state <= s_restore_bsn;
verify_dis_arr <= (others => '1');
- bsn_offset <= bsn_diff; -- use input 0 to restore original BSN sequence for input c_event_input, that got lost due to input disable
+ -- use input 0 to restore original BSN sequence for input c_event_input, that got lost due to input disable
+ bsn_offset <= bsn_diff;
bsn_event <= '1';
proc_common_wait_until_high(clk, bsn_event_ack);
bsn_event <= '0';
@@ -359,7 +378,8 @@ begin
gen_verify : for I in g_nof_input - 1 downto 0 generate
-- Verification logistics
verify_en_arr(I) <= '1' when rising_edge(clk) and verify_dis_arr(I) = '0' and in_en_arr(I) = '1' and out_sosi_arr(I).sop = '1' else
- '0' when rising_edge(clk) and verify_dis_arr(I) = '1'; -- verify enable after first output sop
+ -- verify enable after first output sop
+ '0' when rising_edge(clk) and verify_dis_arr(I) = '1';
-- Ease in_siso_arr monitoring
in_ready(I) <= in_siso_arr(I).ready;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
index c6db289f9ed18f783f7200c0011a250f934233b7..602602f991ee5f97b7375848f3062c90a5e403b0 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
@@ -84,28 +84,47 @@ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_align_v2 is
generic (
-- DUT
- g_nof_streams : natural := 2; -- number of input and output streams
- g_bsn_latency_max : natural := 1; -- Maximum travel latency of a remote block in number of block periods T_blk
- g_nof_aligners_max : positive := 1; -- 1 when only align at last node, > 1 when align at every intermediate node
- g_block_size : natural := 11; -- > 1, g_block_size=1 is not supported
- g_block_period : natural := 20; -- >= g_block_size, = g_block_size + c_gap_size
- g_bsn_w : natural := c_dp_stream_bsn_w; -- number of bits in sosi BSN
- g_data_w : natural := 16; -- number of bits in sosi data
- g_data_replacement_value : integer := 17; -- output sosi data replacement value for missing input blocks
- g_disable_stream_id : natural := 0; -- default 0 to enable all streams, > 0 selects stream that will be disabled
- g_lost_stream_id : natural := 0; -- default 0 to have all streams, > 0 selects stream that will be lost
- g_lost_bsn_id : natural := 0; -- for stream 1 the block with bsn = g_lost_bsn_id will be lost
- g_bsn_init : natural := 3; -- use > 0 to have no lost data for g_lost_bsn_id = 0
- g_use_mm_output : boolean := false; -- output via MM or via streaming DP
- g_pipeline_input : natural := 0; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr
- g_pipeline_output : natural := 0; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of out_sop_arr
- g_rd_latency : natural := 1; -- 1 or 2, choose 2 to ease timing closure
+ -- number of input and output streams
+ g_nof_streams : natural := 2;
+ -- Maximum travel latency of a remote block in number of block periods T_blk
+ g_bsn_latency_max : natural := 1;
+ -- 1 when only align at last node, > 1 when align at every intermediate node
+ g_nof_aligners_max : positive := 1;
+ -- > 1, g_block_size=1 is not supported
+ g_block_size : natural := 11;
+ -- >= g_block_size, = g_block_size + c_gap_size
+ g_block_period : natural := 20;
+ -- number of bits in sosi BSN
+ g_bsn_w : natural := c_dp_stream_bsn_w;
+ -- number of bits in sosi data
+ g_data_w : natural := 16;
+ -- output sosi data replacement value for missing input blocks
+ g_data_replacement_value : integer := 17;
+ -- default 0 to enable all streams, > 0 selects stream that will be disabled
+ g_disable_stream_id : natural := 0;
+ -- default 0 to have all streams, > 0 selects stream that will be lost
+ g_lost_stream_id : natural := 0;
+ -- for stream 1 the block with bsn = g_lost_bsn_id will be lost
+ g_lost_bsn_id : natural := 0;
+ -- use > 0 to have no lost data for g_lost_bsn_id = 0
+ g_bsn_init : natural := 3;
+ -- output via MM or via streaming DP
+ g_use_mm_output : boolean := false;
+ -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr
+ g_pipeline_input : natural := 0;
+ -- >= 0, choose 0 for wires, choose 1 to ease timing closure of out_sop_arr
+ g_pipeline_output : natural := 0;
+ -- 1 or 2, choose 2 to ease timing closure
+ g_rd_latency : natural := 1;
-- TB
- g_tb_diff_delay : integer := 0; -- 0 = aligned inputs, -1 = max input delay for no loss,
+ -- 0 = aligned inputs, -1 = max input delay for no loss,
+ g_tb_diff_delay : integer := 0;
-- >~ g_bsn_latency_max * g_block_period will give loss
- g_tb_nof_restart : natural := 2; -- number of times to restart the input stimuli
- g_tb_nof_blocks : natural := 20 -- number of input blocks per restart
+ -- number of times to restart the input stimuli
+ g_tb_nof_restart : natural := 2;
+ -- number of input blocks per restart
+ g_tb_nof_blocks : natural := 20
);
end tb_dp_bsn_align_v2;
@@ -114,7 +133,8 @@ architecture tb of tb_dp_bsn_align_v2 is
constant c_data_w : natural := 16;
constant c_data_init : integer := 0;
- constant c_bsn_w : natural := 16; -- use <= 31 bit to fit NATURAL
+ -- use <= 31 bit to fit NATURAL
+ constant c_bsn_w : natural := 16;
constant c_channel_init : integer := 0;
constant c_err_init : natural := 247;
constant c_sync_period : natural := 7;
@@ -139,7 +159,8 @@ architecture tb of tb_dp_bsn_align_v2 is
constant c_gap_size : natural := g_block_period - g_block_size;
- constant c_lost_bsn_stream_id : natural := sel_a_b(g_nof_streams > 1, 1, 0); -- fixed use stream 1 to verify g_lost_bsn_id. Use 0 for g_nof_streams = 1.
+ -- fixed use stream 1 to verify g_lost_bsn_id. Use 0 for g_nof_streams = 1.
+ constant c_lost_bsn_stream_id : natural := sel_a_b(g_nof_streams > 1, 1, 0);
-- In the tb only support MM interface verification for c_nof_aligners_max = 1
constant c_nof_aligners_max : positive := sel_a_b(g_use_mm_output, 1, g_nof_aligners_max);
@@ -151,13 +172,17 @@ architecture tb of tb_dp_bsn_align_v2 is
constant c_dut_latency : natural := g_pipeline_input + g_rd_latency + c_mm_to_dp_latency + g_pipeline_output;
-- DUT buffer latency for chain of DUTs
- constant c_align_latency_nof_blocks : natural := g_bsn_latency_max * c_nof_aligners_max; -- in number blocks
- constant c_align_latency_nof_valid : natural := g_bsn_latency_max * c_nof_aligners_max * g_block_size; -- in number of data samples
- constant c_align_latency_nof_clk : natural := g_bsn_latency_max * c_nof_aligners_max * g_block_period; -- in number clk cycles
+ -- in number blocks
+ constant c_align_latency_nof_blocks : natural := g_bsn_latency_max * c_nof_aligners_max;
+ -- in number of data samples
+ constant c_align_latency_nof_valid : natural := g_bsn_latency_max * c_nof_aligners_max * g_block_size;
+ -- in number clk cycles
+ constant c_align_latency_nof_clk : natural := g_bsn_latency_max * c_nof_aligners_max * g_block_period;
-- Total DUT chain latency
constant c_total_latency : natural := c_dut_latency + c_align_latency_nof_clk;
- constant c_verify_nof_blocks : natural := g_tb_nof_blocks - c_align_latency_nof_blocks; -- skip last blocks that are still in the DUT buffer
+ -- skip last blocks that are still in the DUT buffer
+ constant c_verify_nof_blocks : natural := g_tb_nof_blocks - c_align_latency_nof_blocks;
type t_tb_state is (s_idle, s_start, s_restart);
@@ -183,16 +208,24 @@ architecture tb of tb_dp_bsn_align_v2 is
signal node_index_arr : t_nat_natural_arr(0 to c_nof_aligners_max - 1) := array_init(0, c_nof_aligners_max, 1);
- signal stream_en_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '1'); -- default all streams are enabled
- signal stream_lost_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0'); -- default no streams are lost
- signal in_bsn_lost_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0'); -- default no blocks are lost
- signal in_bsn_lost : std_logic; -- = in_bsn_lost_arr(c_lost_bsn_stream_id)
- signal exp_bsn_lost_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0'); -- default no blocks are lost
+ -- default all streams are enabled
+ signal stream_en_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '1');
+ -- default no streams are lost
+ signal stream_lost_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0');
+ -- default no blocks are lost
+ signal in_bsn_lost_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0');
+ -- = in_bsn_lost_arr(c_lost_bsn_stream_id)
+ signal in_bsn_lost : std_logic;
+ -- default no blocks are lost
+ signal exp_bsn_lost_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0');
signal ref_siso_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
- signal ref_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- generated stimuli
- signal rx_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst); -- received stimuli
- signal in_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst); -- input stimuli
+ -- generated stimuli
+ signal ref_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ -- received stimuli
+ signal rx_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
+ -- input stimuli
+ signal in_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
signal in_sync_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal in_sop_arr : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -204,15 +237,18 @@ architecture tb of tb_dp_bsn_align_v2 is
signal in_err_arr : t_err_arr;
signal mm_copi_arr : t_mem_copi_arr(g_nof_streams - 1 downto 0);
- signal mm_copi : t_mem_copi; -- read access to output block, all output streams share same mm_copi
+ -- read access to output block, all output streams share same mm_copi
+ signal mm_copi : t_mem_copi;
signal mm_cipo_arr : t_mem_cipo_arr(g_nof_streams - 1 downto 0);
- signal mm_sosi : t_dp_sosi; -- streaming information that signals that an output block can be read
+ -- streaming information that signals that an output block can be read
+ signal mm_sosi : t_dp_sosi;
signal mm_done_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal mm_done : std_logic;
signal mm_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal dut_in_sosi_2arr : t_dut_sosi_2arr(0 to c_nof_aligners_max - 1);
signal dut_out_sosi_2arr : t_dut_sosi_2arr(0 to c_nof_aligners_max - 1);
- signal dut_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- last BSN aligner output
+ -- last BSN aligner output
+ signal dut_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal r : t_reg;
signal nxt_r : t_reg;
@@ -254,12 +290,18 @@ architecture tb of tb_dp_bsn_align_v2 is
signal dbg_c_verify_nof_blocks : natural := c_verify_nof_blocks;
-- Debug signals to view that verification conditions actually occur
- signal dbg_verify_sosi_control_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0'); -- '1' when sosi control is verified
- signal dbg_verify_passed_on_data_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0'); -- '1' when passed on data is verified
- signal dbg_verify_replaced_data_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0'); -- '1' when replaced data is verified
- signal dbg_verify_bsn_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0'); -- '1' when bsn in all streams is verified
- signal dbg_verify_no_lost_flag_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0'); -- '1' when lost data flag = 0 is verified
- signal dbg_verify_lost_flag_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0'); -- '1' when lost data flag = 1 is verified
+ -- '1' when sosi control is verified
+ signal dbg_verify_sosi_control_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0');
+ -- '1' when passed on data is verified
+ signal dbg_verify_passed_on_data_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0');
+ -- '1' when replaced data is verified
+ signal dbg_verify_replaced_data_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0');
+ -- '1' when bsn in all streams is verified
+ signal dbg_verify_bsn_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0');
+ -- '1' when lost data flag = 0 is verified
+ signal dbg_verify_no_lost_flag_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0');
+ -- '1' when lost data flag = 1 is verified
+ signal dbg_verify_lost_flag_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0');
begin
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -291,7 +333,8 @@ begin
proc_dp_gen_block_data(c_rl, true, c_data_w, c_data_w, v_data, 0, 0, g_block_size, v_channel, v_err, v_sync, TO_UVEC(v_bsn, c_bsn_w), clk, sl1, ref_siso_arr(I), ref_sosi_arr(I));
v_bsn := v_bsn + 1;
v_data := v_data + g_block_size;
- proc_common_wait_some_cycles(clk, c_gap_size); -- create gap between frames
+ -- create gap between frames
+ proc_common_wait_some_cycles(clk, c_gap_size);
end loop;
-- no gap between restarts, to ease verification by maintaining fixed
-- latency of out_sosi_arr_exp
@@ -394,9 +437,11 @@ begin
out_err_arr(I) <= out_sosi_arr(I).err;
end generate;
- out_sosi <= out_sosi_arr(0); -- take out_sosi control and info from out_sosi_arr(0)
+ -- take out_sosi control and info from out_sosi_arr(0)
+ out_sosi <= out_sosi_arr(0);
- out_bsn <= TO_UINT(out_sosi.bsn); -- = out_bsn_arr().bsn = out_sosi_arr(I).bsn
+ -- = out_bsn_arr().bsn = out_sosi_arr(I).bsn
+ out_bsn <= TO_UINT(out_sosi.bsn);
------------------------------------------------------------------------------
-- DATA VERIFICATION, use multiple ways to increase coverage
@@ -406,7 +451,8 @@ begin
ref_sosi_arr_dly <= transport ref_sosi_arr after c_total_latency * clk_period;
out_sosi_arr_exp <= ref_sosi_arr_dly when rising_edge(clk);
- out_sosi_exp <= out_sosi_arr_exp(0); -- take out_sosi_exp control and info from out_sosi_arr_exp(0)
+ -- take out_sosi_exp control and info from out_sosi_arr_exp(0)
+ out_sosi_exp <= out_sosi_arr_exp(0);
gen_verify_ctrl : for I in g_nof_streams - 1 downto 0 generate
-- . Verify that sop and eop come in pairs
@@ -415,7 +461,8 @@ begin
-- . No data verification here, using p_verify_sosi is easier than using proc_dp_verify_data().
-- . Verify that the stimuli have been applied at all
- hold_data_arr(I) <= out_data_arr(I) when out_val_arr(I) = '1'; -- hold last valid data
+ -- hold last valid data
+ hold_data_arr(I) <= out_data_arr(I) when out_val_arr(I) = '1';
proc_dp_verify_value("out_data_arr", e_equal, clk, verify_done_arr(I), expected_out_data_arr(I), hold_data_arr(I));
proc_dp_verify_value("out_bsn_arr", e_equal, clk, verify_done_arr(I), expected_out_bsn_arr(I), out_bsn_arr(I));
proc_dp_verify_value("out_channel_arr", e_equal, clk, verify_done_arr(I), expected_out_channel_arr(I), out_channel_arr(I));
@@ -598,7 +645,8 @@ begin
gen_use_mm_output : if g_use_mm_output generate
mm_copi <= mm_copi_arr(0);
- mm_done <= mm_done_arr(0); -- for viewing only
+ -- for viewing only
+ mm_done <= mm_done_arr(0);
gen_mm_to_dp : for I in 0 to g_nof_streams - 1 generate
u_mm_to_dp: entity work.dp_block_from_mm
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
index 2003d4327fcff14a6b85e468cb94ad4f94db4e84..cf1ca8afea9425505d83155100239a8ad01c040f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
@@ -38,7 +38,8 @@ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_monitor is
generic (
- g_in_en : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- always e_active, e_random or e_pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_active;
g_nof_sync : natural := 11
);
end tb_dp_bsn_monitor;
@@ -56,15 +57,18 @@ architecture tb of tb_dp_bsn_monitor is
constant c_nof_repeat : natural := g_nof_sync * c_sync_period + 1;
-- Error control
- constant c_skip_sync_nr : integer := -1; -- use e.g. 5 >= 0 to introduce a sync timeout at that sync interval 5 (causes missing sinc error by proc_dp_verify_sync), use -1 to disable skipping a sync
- constant c_nof_err : natural := 2; -- <= c_sync_period -- introduce frame errors
+ -- use e.g. 5 >= 0 to introduce a sync timeout at that sync interval 5 (causes missing sinc error by proc_dp_verify_sync), use -1 to disable skipping a sync
+ constant c_skip_sync_nr : integer := -1;
+ -- <= c_sync_period -- introduce frame errors
+ constant c_nof_err : natural := 2;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
signal rst : std_logic := '1';
-- Flow control
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_en : std_logic := '1';
@@ -78,8 +82,10 @@ architecture tb of tb_dp_bsn_monitor is
signal out_siso : t_dp_siso;
-- Monitor in_sosi and out_siso
- signal mon_evt : std_logic; -- pulses when new monitor output is available regarding the previous sync interval
- signal mon_sync : std_logic; -- pulses every in_sync interval
+ -- pulses when new monitor output is available regarding the previous sync interval
+ signal mon_evt : std_logic;
+ -- pulses every in_sync interval
+ signal mon_sync : std_logic;
signal mon_sync_timeout : std_logic;
signal mon_ready_stable : std_logic;
signal mon_xon_stable : std_logic;
@@ -251,15 +257,18 @@ begin
begin
sync_in <= '0';
proc_common_wait_until_low(clk, rst);
- proc_common_wait_some_cycles(clk, 25); -- on SOP
+ -- on SOP
+ proc_common_wait_some_cycles(clk, 25);
sync_in <= '1';
proc_common_wait_some_cycles(clk, 1);
sync_in <= '0';
- proc_common_wait_some_cycles(clk, 38); -- on EOP
+ -- on EOP
+ proc_common_wait_some_cycles(clk, 38);
sync_in <= '1';
proc_common_wait_some_cycles(clk, 1);
sync_in <= '0';
- proc_common_wait_some_cycles(clk, 67); -- random
+ -- random
+ proc_common_wait_some_cycles(clk, 67);
sync_in <= '1';
proc_common_wait_some_cycles(clk, 1);
sync_in <= '0';
@@ -272,14 +281,20 @@ begin
------------------------------------------------------------------------------
-- Verification logistics
- verify_en <= '1' when rising_edge(clk) and in_sosi.sop = '1'; -- enable verify after first input sop
- count_eop <= count_eop + 1 when rising_edge(clk) and in_sosi.eop = '1'; -- count number of input eop
- verify_done <= '1' when rising_edge(clk) and count_eop = c_nof_repeat; -- signal verify done after c_nof_repeat frames
+ -- enable verify after first input sop
+ verify_en <= '1' when rising_edge(clk) and in_sosi.sop = '1';
+ -- count number of input eop
+ count_eop <= count_eop + 1 when rising_edge(clk) and in_sosi.eop = '1';
+ -- signal verify done after c_nof_repeat frames
+ verify_done <= '1' when rising_edge(clk) and count_eop = c_nof_repeat;
-- Actual verification of the input streams
- proc_dp_verify_data("in_sosi.data", c_rl, clk, verify_en, in_siso.ready, in_sosi.valid, in_data, prev_in_data); -- Verify that the input is incrementing data, like the input stimuli
- proc_dp_verify_valid(c_rl, clk, verify_en, in_siso.ready, prev_in_ready, in_sosi.valid); -- Verify that the input valid fits with the input ready latency
- proc_dp_verify_value(e_equal, clk, verify_done, expected_in_data, prev_in_data); -- Verify that the stimuli have been applied at all
+ -- Verify that the input is incrementing data, like the input stimuli
+ proc_dp_verify_data("in_sosi.data", c_rl, clk, verify_en, in_siso.ready, in_sosi.valid, in_data, prev_in_data);
+ -- Verify that the input valid fits with the input ready latency
+ proc_dp_verify_valid(c_rl, clk, verify_en, in_siso.ready, prev_in_ready, in_sosi.valid);
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done, expected_in_data, prev_in_data);
proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en, in_sosi.sync, in_sosi.sop, in_sosi.bsn);
-- Monitoring
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
index 8f76b0058e0f43e23babe9cff785b82e7f463c94..f2eae37c1f0572c15069ac3fe0415b638351c5b4 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
@@ -38,7 +38,8 @@ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_monitor_v2 is
generic (
- g_in_en : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- always e_active, e_random or e_pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_active;
g_nof_sync : natural := 11
);
end tb_dp_bsn_monitor_v2;
@@ -55,19 +56,23 @@ architecture tb of tb_dp_bsn_monitor_v2 is
constant c_sync_timeout : natural := c_frame_len * c_sync_period;
constant c_nof_repeat : natural := g_nof_sync * c_sync_period + 1;
constant c_ref_sync_latency : natural := 7;
- constant c_mon_sync_latency : natural := 1; -- due to sync_reg2 in dp_bsn_monitor_v2
+ -- due to sync_reg2 in dp_bsn_monitor_v2
+ constant c_mon_sync_latency : natural := 1;
constant c_exp_sync_latency : natural := c_ref_sync_latency + c_mon_sync_latency;
-- Error control
- constant c_skip_sync_nr : integer := -1; -- use e.g. 5 >= 0 to introduce a sync timeout at that sync interval 5 (causes missing sinc error by proc_dp_verify_sync), use -1 to disable skipping a sync
- constant c_nof_err : natural := 2; -- <= c_sync_period -- introduce frame errors
+ -- use e.g. 5 >= 0 to introduce a sync timeout at that sync interval 5 (causes missing sinc error by proc_dp_verify_sync), use -1 to disable skipping a sync
+ constant c_skip_sync_nr : integer := -1;
+ -- <= c_sync_period -- introduce frame errors
+ constant c_nof_err : natural := 2;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
signal rst : std_logic := '1';
-- Flow control
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_en : std_logic := '1';
@@ -81,8 +86,10 @@ architecture tb of tb_dp_bsn_monitor_v2 is
signal out_siso : t_dp_siso;
-- Monitor in_sosi and out_siso
- signal mon_evt : std_logic; -- pulses when new monitor output is available regarding the previous sync interval
- signal mon_sync : std_logic; -- pulses every in_sync interval
+ -- pulses when new monitor output is available regarding the previous sync interval
+ signal mon_evt : std_logic;
+ -- pulses every in_sync interval
+ signal mon_sync : std_logic;
signal mon_sync_timeout : std_logic;
signal mon_ready_stable : std_logic;
signal mon_xon_stable : std_logic;
@@ -271,14 +278,20 @@ begin
------------------------------------------------------------------------------
-- Verification logistics
- verify_en <= '1' when rising_edge(clk) and in_sosi.sop = '1'; -- enable verify after first input sop
- count_eop <= count_eop + 1 when rising_edge(clk) and in_sosi.eop = '1'; -- count number of input eop
- verify_done <= '1' when rising_edge(clk) and count_eop = c_nof_repeat; -- signal verify done after c_nof_repeat frames
+ -- enable verify after first input sop
+ verify_en <= '1' when rising_edge(clk) and in_sosi.sop = '1';
+ -- count number of input eop
+ count_eop <= count_eop + 1 when rising_edge(clk) and in_sosi.eop = '1';
+ -- signal verify done after c_nof_repeat frames
+ verify_done <= '1' when rising_edge(clk) and count_eop = c_nof_repeat;
-- Actual verification of the input streams
- proc_dp_verify_data("in_sosi.data", c_rl, clk, verify_en, in_siso.ready, in_sosi.valid, in_data, prev_in_data); -- Verify that the input is incrementing data, like the input stimuli
- proc_dp_verify_valid(c_rl, clk, verify_en, in_siso.ready, prev_in_ready, in_sosi.valid); -- Verify that the input valid fits with the input ready latency
- proc_dp_verify_value(e_equal, clk, verify_done, expected_in_data, prev_in_data); -- Verify that the stimuli have been applied at all
+ -- Verify that the input is incrementing data, like the input stimuli
+ proc_dp_verify_data("in_sosi.data", c_rl, clk, verify_en, in_siso.ready, in_sosi.valid, in_data, prev_in_data);
+ -- Verify that the input valid fits with the input ready latency
+ proc_dp_verify_valid(c_rl, clk, verify_en, in_siso.ready, prev_in_ready, in_sosi.valid);
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done, expected_in_data, prev_in_data);
proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en, in_sosi.sync, in_sosi.sop, in_sosi.bsn);
-- Monitoring
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
index 77429b4b4f377149a3435a54dc6a1463df928a56..c9e5f3a2f2f4a12072b8d6428b658325fb999c1a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
@@ -44,7 +44,8 @@ architecture tb of tb_dp_bsn_source is
--CONSTANT c_block_size : NATURAL := 32;
constant c_bsn_w : natural := 16;
constant c_sync_period : natural := 7;
- constant c_sync_offset : natural := 3; -- must be < c_sync_period for proc_dp_verify_sync
+ -- must be < c_sync_period for proc_dp_verify_sync
+ constant c_sync_offset : natural := 3;
-- The state name tells what kind of test is being done
type t_state_enum is (
@@ -115,7 +116,8 @@ begin
-- Stop by making dp_on low
tb_state <= s_disable;
dp_on <= '0';
- dp_on_pps <= '0'; -- No PPS trigger next time
+ -- No PPS trigger next time
+ dp_on_pps <= '0';
proc_common_wait_some_cycles(clk, 1000);
-- Start by making dp_on high
@@ -147,8 +149,10 @@ begin
-----------------------------------------------------------------------------
-- Verification
-----------------------------------------------------------------------------
- proc_dp_verify_sop_and_eop(clk, bs_sosi.valid, bs_sosi.sop, bs_sosi.eop, hold_bs_sop); -- Verify that sop and eop come in pairs
- proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_sync, bs_sosi.sync, bs_sosi.sop, bs_sosi.bsn); -- Verify sync at sop and at expected BSN
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(clk, bs_sosi.valid, bs_sosi.sop, bs_sosi.eop, hold_bs_sop);
+ -- Verify sync at sop and at expected BSN
+ proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_sync, bs_sosi.sync, bs_sosi.sop, bs_sosi.bsn);
-----------------------------------------------------------------------------
-- DUT: dp_bsn_source
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
index d8de93d6138f6fe1a4a6956b3721ea95596ed6c8..cd63f22599377ad1c16728e586b689a0dc8af06e 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
@@ -52,8 +52,10 @@ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_source_v2 is
generic (
- g_pps_interval : natural := 16; -- 101;
- g_block_size : natural := 5 -- 23
+ -- 101;
+ g_pps_interval : natural := 16;
+ -- 23
+ g_block_size : natural := 5
);
end tb_dp_bsn_source_v2;
@@ -96,12 +98,18 @@ architecture tb of tb_dp_bsn_source_v2 is
-- Define the PPS (SSN) and BSN grid that both start at 0 according to Figure 3.1 in [1]:
type t_time_grid is record
- pps : std_logic; -- pulse per second, g_pps_interval clk per pps interval
- ssn : natural; -- seconds sequence number
- bsn : natural; -- block sequence number, g_block_size clk per block
- sync : std_logic; -- active at sop when pps is active or was active
- sop : std_logic; -- start of block
- eop : std_logic; -- end of block
+ -- pulse per second, g_pps_interval clk per pps interval
+ pps : std_logic;
+ -- seconds sequence number
+ ssn : natural;
+ -- block sequence number, g_block_size clk per block
+ bsn : natural;
+ -- active at sop when pps is active or was active
+ sync : std_logic;
+ -- start of block
+ sop : std_logic;
+ -- end of block
+ eop : std_logic;
end record;
constant c_time_grid_rst : t_time_grid := ('0', 0, 0, '0', '0', '0');
@@ -167,15 +175,18 @@ begin
if ref_grid.pps = '1' then
if ref_grid.sop = '1' then
- ref_grid.sync <= '1'; -- immediately issue sync
+ -- immediately issue sync
+ ref_grid.sync <= '1';
else
- nxt_hold_pps <= '1'; -- wait until next block
+ -- wait until next block
+ nxt_hold_pps <= '1';
end if;
end if;
if hold_pps = '1' then
if ref_grid.sop = '1' then
- ref_grid.sync <= '1'; -- issue pending sync
+ -- issue pending sync
+ ref_grid.sync <= '1';
nxt_hold_pps <= '0';
end if;
end if;
@@ -198,7 +209,8 @@ begin
proc_common_wait_some_cycles(clk, 10);
-- Start asynchronously by making dp_on high
- verify_en <= '0'; -- only verify visualy in wave window
+ -- only verify visualy in wave window
+ verify_en <= '0';
tb_state <= s_dp_on;
dp_on_pps <= '0';
dp_on <= '1';
@@ -209,7 +221,8 @@ begin
proc_common_wait_some_cycles(clk, 10);
-- Start synchronously by making dp_on and dp_on_pps high
- verify_en <= '1'; -- verify automatically in test bench
+ -- verify automatically in test bench
+ verify_en <= '1';
for I in 0 to c_nof_repeat - 1 loop
-- Wait some variable time between tests, to enforce testing different
@@ -224,10 +237,14 @@ begin
-- Determine bsn_init and bsn_time_offset for BSN source start
-- . bsn_init = BSN at sync
-- . bsn_time_offset = number of clk that sync occurs after PPS
- v_ssn := ref_grid.ssn + 1; -- +1 to prepare start in next PPS interval
- v_bsn_init := ceil_div(v_SSN * g_pps_interval, g_block_size); -- Equation 3.6 in [1]
- v_bsn_time_offset := v_bsn_init * g_block_size - v_SSN * g_pps_interval; -- Equation 3.7 in [1]
- bsn_init <= TO_UVEC(v_bsn_init, c_bsn_w); --
+ -- +1 to prepare start in next PPS interval
+ v_ssn := ref_grid.ssn + 1;
+ -- Equation 3.6 in [1]
+ v_bsn_init := ceil_div(v_SSN * g_pps_interval, g_block_size);
+ -- Equation 3.7 in [1]
+ v_bsn_time_offset := v_bsn_init * g_block_size - v_SSN * g_pps_interval;
+ --
+ bsn_init <= TO_UVEC(v_bsn_init, c_bsn_w);
bsn_time_offset <= TO_UVEC(v_bsn_time_offset, c_bsn_time_offset_w);
-- Start synchronously by making dp_on and dp_on_pps high
tb_state <= s_dp_on_pps;
@@ -254,11 +271,13 @@ begin
-----------------------------------------------------------------------------
verify_sync <= verify_en and bs_sosi.valid;
- proc_dp_verify_sop_and_eop(clk, bs_sosi.valid, bs_sosi.sop, bs_sosi.eop, hold_bs_sop); -- Verify that sop and eop come in pairs
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(clk, bs_sosi.valid, bs_sosi.sop, bs_sosi.eop, hold_bs_sop);
--proc_dp_verify_sync(clk, verify_sync, bs_sosi.sync, exp_grid.sop, exp_grid.sync); -- Verify sync at sop and at expected_sync
-- Verify sync at sop and at expected_sync
- proc_dp_verify_sync(0, -- start bsn of PPS grid and BSN grid is 0, see [1]
+ -- start bsn of PPS grid and BSN grid is 0, see [1]
+ proc_dp_verify_sync(0,
g_pps_interval,
g_block_size,
clk,
@@ -338,9 +357,12 @@ begin
dp_on => dp_on,
dp_on_pps => dp_on_pps,
- dp_on_status => dp_on_status, -- = src_out.valid
- bs_restart => bs_restart, -- = src_out.sync for first sync after dp_on went high
- bs_new_interval => bs_new_interval, -- active during first src_out.sync interval
+ -- = src_out.valid
+ dp_on_status => dp_on_status,
+ -- = src_out.sync for first sync after dp_on went high
+ bs_restart => bs_restart,
+ -- active during first src_out.sync interval
+ bs_new_interval => bs_new_interval,
bsn_init => bsn_init,
bsn_time_offset => bsn_time_offset,
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
index 5a8bde3e8658d01b4f4fe76d577230b2c2f63738..b09ddc19e3fc5346ebd5e6204e7ae0edc43ff433 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
@@ -80,14 +80,17 @@ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_sync_scheduler is
generic (
-- Input sync period and sosi ctrl
- g_nof_input_sync : natural := 10; -- Use c_nof_input_sync > g_block_size, see tb_tb_dp_bsn_sync_scheduler
+ -- Use c_nof_input_sync > g_block_size, see tb_tb_dp_bsn_sync_scheduler
+ g_nof_input_sync : natural := 10;
g_nof_block_per_input_sync : natural := 17;
g_block_size : natural := 2;
g_input_gap_size : natural := 0;
-- Output sync period
- g_nof_samples_per_output_sync : natural := 45; -- 45 / g_block_size = 4.5
- g_pipeline : natural := 0 -- 0 or 1
+ -- 45 / g_block_size = 4.5
+ g_nof_samples_per_output_sync : natural := 45;
+ -- 0 or 1
+ g_pipeline : natural := 0
);
end tb_dp_bsn_sync_scheduler;
@@ -97,15 +100,20 @@ architecture tb of tb_dp_bsn_sync_scheduler is
constant c_dut_latency : natural := 1;
-- Test intervals
- constant c_nof_test_intervals : natural := 4; -- nof should be large enough for p_stimuli
+ -- nof should be large enough for p_stimuli
+ constant c_nof_test_intervals : natural := 4;
constant c_nof_block_per_test_interval : natural := g_nof_block_per_input_sync * g_nof_input_sync;
constant c_nof_lost_input_blocks : natural := g_nof_block_per_input_sync * 4 + 3;
constant c_nof_clk_per_block : natural := g_block_size + g_input_gap_size;
constant c_nof_clk_per_test_interval : natural := c_nof_clk_per_block * c_nof_block_per_test_interval;
- constant c_begin_of_test_interval : natural := 0 + c_nof_clk_per_block * 4; -- just after start
- constant c_early_in_test_interval : natural := c_nof_clk_per_test_interval / 3; -- just after begin and before mid
- constant c_mid_of_test_interval : natural := c_nof_clk_per_test_interval / 2; -- at mid
- constant c_end_of_test_interval : natural := c_nof_clk_per_test_interval - c_nof_clk_per_block * 3; -- just before end
+ -- just after start
+ constant c_begin_of_test_interval : natural := 0 + c_nof_clk_per_block * 4;
+ -- just after begin and before mid
+ constant c_early_in_test_interval : natural := c_nof_clk_per_test_interval / 3;
+ -- at mid
+ constant c_mid_of_test_interval : natural := c_nof_clk_per_test_interval / 2;
+ -- just before end
+ constant c_end_of_test_interval : natural := c_nof_clk_per_test_interval - c_nof_clk_per_block * 3;
constant c_sim_nof_blocks : natural := c_nof_block_per_test_interval * c_nof_test_intervals;
@@ -120,14 +128,21 @@ architecture tb of tb_dp_bsn_sync_scheduler is
signal test_interval : integer := 0;
signal tb_end : std_logic := '0';
- type t_stimuli_state_enum is ( -- use short names to ease unzoomed view in Wave window
- e_dis, -- disable
- e_en, -- enable
- e_re, -- re-enable
- e_lost, -- lost input blocks
- e_old -- start bsn in passed
+ -- use short names to ease unzoomed view in Wave window
+ type t_stimuli_state_enum is (
+ -- disable
+ e_dis,
+ -- enable
+ e_en,
+ -- re-enable
+ e_re,
+ -- lost input blocks
+ e_lost,
+ -- start bsn in passed
+ e_old
);
- signal stimuli_state : t_stimuli_state_enum := e_dis; -- to show what tb does in Wave window
+ -- to show what tb does in Wave window
+ signal stimuli_state : t_stimuli_state_enum := e_dis;
-- Stimuli
signal ctrl_enable : std_logic := '0';
@@ -141,15 +156,18 @@ architecture tb of tb_dp_bsn_sync_scheduler is
signal out_sop_dly : std_logic;
signal stimuli_sosi : t_dp_sosi := c_dp_sosi_init;
- signal stimuli_sync : std_logic; -- declared next to stimuli_sosi and out_sync for easier comparison in Wave window
+ -- declared next to stimuli_sosi and out_sync for easier comparison in Wave window
+ signal stimuli_sync : std_logic;
-- Input stimuli
signal in_lost : std_logic := '0';
- signal in_sosi : t_dp_sosi := c_dp_sosi_init; -- = stimuli_sosi, with option for lost blocks
+ -- = stimuli_sosi, with option for lost blocks
+ signal in_sosi : t_dp_sosi := c_dp_sosi_init;
signal in_sync : std_logic;
-- Output
- signal out_sync : std_logic; -- declared next to in_sync, out_start and out_sosi for easier comparison in Wave window
+ -- declared next to in_sync, out_start and out_sosi for easier comparison in Wave window
+ signal out_sync : std_logic;
signal out_start : std_logic;
signal out_start_interval : std_logic;
signal exp_start_interval : std_logic := '0';
@@ -199,9 +217,11 @@ architecture tb of tb_dp_bsn_sync_scheduler is
signal ctrl_enable : out std_logic;
signal ctrl_enable_evt : out std_logic) is
begin
- proc_common_wait_until_hi_lo(clk, sync); -- (re)enable at begin of sync interval
+ -- (re)enable at begin of sync interval
+ proc_common_wait_until_hi_lo(clk, sync);
stimuli_state <= e_en;
- ctrl_start_bsn <= ADD_UVEC(mon_input_bsn_at_sync, TO_UVEC(c_enable_init_nof_bsn, c_natural_w)); -- determine BSN in the future
+ -- determine BSN in the future
+ ctrl_start_bsn <= ADD_UVEC(mon_input_bsn_at_sync, TO_UVEC(c_enable_init_nof_bsn, c_natural_w));
ctrl_enable <= '1';
ctrl_enable_evt <= '1';
proc_common_wait_some_cycles(clk, 1);
@@ -290,16 +310,19 @@ begin
proc_common_wait_until_value(test_interval * c_nof_clk_per_test_interval + c_early_in_test_interval, clk, cnt);
stimuli_state <= e_lost;
proc_common_wait_until_high(clk, stimuli_sosi.eop);
- in_lost <= '1'; -- high after eop, so high at next sop
+ -- high after eop, so high at next sop
+ in_lost <= '1';
recover_from_in_lost <= '1';
for I in 0 to c_nof_lost_input_blocks - 1 loop
proc_common_wait_some_cycles(clk, 1);
proc_common_wait_until_high(clk, stimuli_sosi.eop);
end loop;
- in_lost <= '0'; -- low after eop, so low at next sop
+ -- low after eop, so low at next sop
+ in_lost <= '0';
stimuli_state <= e_en;
-- Wait for some cycles that DUT needs to catch up after lost input (see nxt_r.update_bsn in DUT)
- for I in 0 to c_nof_lost_input_blocks / c_output_nof_blocks_min + 5 loop -- + for some extra margin
+ -- + for some extra margin
+ for I in 0 to c_nof_lost_input_blocks / c_output_nof_blocks_min + 5 loop
proc_common_wait_some_cycles(clk, 1);
end loop;
recover_from_in_lost <= '0';
@@ -316,9 +339,11 @@ begin
generic map (
g_sync_period => g_nof_block_per_input_sync,
g_err_init => 0,
- g_err_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
+ -- do not increment, to not distract from viewing of BSN in Wave window
+ g_err_incr => 0,
g_channel_init => 0,
- g_channel_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
+ -- do not increment, to not distract from viewing of BSN in Wave window
+ g_channel_incr => 0,
g_nof_repeat => c_sim_nof_blocks,
g_pkt_len => g_block_size,
g_pkt_gap => g_input_gap_size
@@ -508,7 +533,8 @@ begin
-- . Verify out_sosi.sync = in_sosi.sync, when sync interval is not changed
-----------------------------------------------------------------------------
gen_verify_sync_equal : if g_nof_samples_per_output_sync = g_nof_block_per_input_sync * g_block_size generate
- verifying_sync_equal <= '1'; -- to show in Wave window that this check is active
+ -- to show in Wave window that this check is active
+ verifying_sync_equal <= '1';
proc_dp_verify_sosi_equal( "sync", clk, verify_sosi_equal, out_sosi_integer, in_sosi_integer);
end generate;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd b/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
index e4ceabe74ded544ff68ac1da6ed7d0e1ece038e7..81137da534ec75677bafba684b3d8a4ef305a98d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
@@ -30,9 +30,11 @@ use work.tb_dp_pkg.all;
entity tb_dp_concat is
generic (
- g_data_w : natural := 16 * 3; -- g_data_w/g_symbol_w must be an integer
+ -- g_data_w/g_symbol_w must be an integer
+ g_data_w : natural := 16 * 3;
g_symbol_w : natural := 16;
- g_random_control : boolean := true -- use TRUE for random snk_in.valid and src_in.ready control
+ -- use TRUE for random snk_in.valid and src_in.ready control
+ g_random_control : boolean := true
);
end tb_dp_concat;
@@ -45,13 +47,15 @@ architecture tb of tb_dp_concat is
constant c_sync_period : natural := 3;
constant c_sync_offset : natural := 1;
- constant c_verify_mode : boolean := c_nof_symbols_per_data = 1; -- when FALSE verify per frame
+ -- when FALSE verify per frame
+ constant c_verify_mode : boolean := c_nof_symbols_per_data = 1;
signal tb_end : std_logic := '0';
signal rst : std_logic;
signal clk : std_logic := '0';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal random_2 : std_logic_vector(17 downto 0) := (others => '0');
@@ -95,7 +99,8 @@ begin
in_en(0) <= random_0(random_0'high);
in_en(1) <= random_1(random_1'high);
out_siso.ready <= random_2(random_2'high);
- end generate; -- -- else the in_en and out_siso lines are always active
+ -- -- else the in_en and out_siso lines are always active
+ end generate;
-- For output verify the p_stimuli_0 and p_stimuli_1 must generate head and tail frames that result in concatenated output frames that
-- have ever incrementing valid data.
@@ -108,10 +113,14 @@ begin
-- Head frames
-- . Stimulus c_sync='1' must match v_bsn MOD c_sync_period(=3) = c_sync_offset(=1) to fit proc_dp_verify_sync()
- proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 1, 1, v_bsn + 0, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0)); -- 1
- proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 3, 1, v_bsn + 1, '1', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0)); -- 3
- proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 5, 5, v_bsn + 2, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0)); -- 5, 6, 7, 8, 9
- proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 16, 10, v_bsn + 3, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0)); -- 16, 17, 18, 19, 20, 21, 22, 23, 24, 25
+ -- 1
+ proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 1, 1, v_bsn + 0, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0));
+ -- 3
+ proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 3, 1, v_bsn + 1, '1', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0));
+ -- 5, 6, 7, 8, 9
+ proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 5, 5, v_bsn + 2, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0));
+ -- 16, 17, 18, 19, 20, 21, 22, 23, 24, 25
+ proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 16, 10, v_bsn + 3, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0));
proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 37, 50, v_bsn + 4, '1', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0));
proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 137,101, v_bsn + 5, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0));
@@ -126,11 +135,15 @@ begin
-- Tail frames
-- . Set c_sync='1' for tail frame to verify that it is ignored
- proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 2, 1, 0, '1', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1)); -- 2
- proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 4, 1, 0, '1', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1)); -- 4
- proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 10, 6, 0, '1', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1)); -- 10, 11, 12, 13, 14, 15
+ -- 2
+ proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 2, 1, 0, '1', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1));
+ -- 4
+ proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 4, 1, 0, '1', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1));
+ -- 10, 11, 12, 13, 14, 15
+ proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 10, 6, 0, '1', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1));
wait for 15 * c_period;
- proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 26, 11, 0, '1', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1)); -- 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36
+ -- 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36
+ proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 26, 11, 0, '1', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1));
proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 87, 50, 0, '1', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1));
proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 238,100, 0, '1', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1));
@@ -155,9 +168,11 @@ begin
port map (
rst => rst,
clk => clk,
- snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out_arr => in_siso_arr,
snk_in_arr => in_sosi_arr,
- src_in => out_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => out_siso,
src_out => out_sosi
);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd b/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
index aea02918e9685a84717f4ac60a9619278e7919e2..c2c08848f04eae1e54ba5be01d518690d3f87d96 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
@@ -49,8 +49,10 @@ use work.tb_dp_pkg.all;
entity tb_dp_concat_field_blk is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always e_active, e_random or e_pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- always e_active, e_random or e_pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse;
+ -- always e_active, e_random or e_pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
g_data_w : natural := 64;
g_nof_repeat : natural := 100;
@@ -76,7 +78,8 @@ architecture tb of tb_dp_concat_field_blk is
--CONSTANT c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := c_dp_sosi_unsigned_rst; -- default 0 is no wrap
constant c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := TO_DP_SOSI_UNSIGNED('0', '0', '0', '0', c_data_max, c_dsp_max, c_dsp_max, c_unsigned_0, c_unsigned_0, c_unsigned_0, c_unsigned_0);
- constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones; -- default only accept increment +1
+ -- default only accept increment +1
+ constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones;
constant c_expected_pkt_len : natural := g_pkt_len;
constant c_sync_period : natural := 5;
@@ -89,7 +92,8 @@ architecture tb of tb_dp_concat_field_blk is
-- Tx offload
-----------------------------------------------------------------------------
-- From apertif_udp_offload_pkg.vhd:
- constant c_udp_offload_nof_hdr_fields : natural := 3 + 12 + 4 + 3; -- 448b; 7 64b words
+ -- 448b; 7 64b words
+ constant c_udp_offload_nof_hdr_fields : natural := 3 + 12 + 4 + 3;
-- Notes:
-- . pre-calculated ip_header_checksum is valid only for UNB0, FN0 targeting IP 10.10.10.10
-- . udp_total_length = 176 beamlets * 64b / 8b = 1408B + 14 DP bytes + 8 UDP bytes = 1430B
@@ -195,12 +199,15 @@ begin
u_dp_stream_stimuli : entity work.dp_stream_stimuli
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 15,
g_pulse_active => c_stimuli_pulse_active,
g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_stimuli,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -220,9 +227,12 @@ begin
src_out => stimuli_src_out,
-- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ -- expected verify_snk_in after end of stimuli
+ last_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ last_snk_in_evt => last_snk_in_evt,
+ -- signal end of tb as far as this dp_stream_stimuli is concerned
+ tb_end => tb_end
);
------------------------------------------------------------------------------
@@ -245,7 +255,8 @@ begin
-- . after the test
verify_last_snk_in_evt.sync <= last_snk_in_evt;
- verify_last_snk_in_evt.bsn <= last_snk_in_evt; -- thanks to using rx_hdr_fields_raw_arr for bsn field
+ -- thanks to using rx_hdr_fields_raw_arr for bsn field
+ verify_last_snk_in_evt.bsn <= last_snk_in_evt;
verify_last_snk_in_evt.data <= last_snk_in_evt;
verify_last_snk_in_evt.re <= '0';
verify_last_snk_in_evt.im <= '0';
@@ -258,12 +269,15 @@ begin
u_dp_stream_verify : entity work.dp_stream_verify
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 14,
g_pulse_active => c_verify_pulse_active,
g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_verify,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -282,11 +296,14 @@ begin
snk_in => verify_snk_in,
-- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+ -- enable verify to verify that the verify_snk_in fields are incrementing
+ verify_snk_in_enable => verify_snk_in_enable,
-- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ -- expected verify_snk_in after end of stimuli
+ expected_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ verify_expected_snk_in_evt => verify_last_snk_in_evt
);
------------------------------------------------------------------------------
@@ -308,7 +325,8 @@ begin
rst => dp_rst,
clk => dp_clk,
- snk_out => OPEN, -- stimuli_src_in
+ -- stimuli_src_in
+ snk_out => OPEN,
snk_in => stimuli_src_out,
src_in => dp_fifo_sc_src_in,
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
index 50c0401ffe35f78b823caac59d9754c36cfe1961..632fbf760ba800c6fa7e95dcc5a76a75566f3b3f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
@@ -44,11 +44,15 @@ use work.tb_dp_pkg.all;
entity tb_dp_counter is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- dut
- g_pipeline_src_out : natural := 1; -- Pipeline source outputs (data,valid,sop,eop etc)
- g_pipeline_src_in : natural := 0; -- Pipeline source inputs (ready,xon). This will also pipeline src_out.
+ -- Pipeline source outputs (data,valid,sop,eop etc)
+ g_pipeline_src_out : natural := 1;
+ -- Pipeline source inputs (ready,xon). This will also pipeline src_out.
+ g_pipeline_src_in : natural := 0;
g_nof_counters : natural := 3;
-- min range = [0,2,1] => (0,1) 'the Python way'
g_range_start : t_nat_natural_arr(9 downto 0) := (0,0,0,0,0,0,0, 1, 0, 0);
@@ -87,7 +91,8 @@ architecture tb of tb_dp_counter is
variable v_period : natural := 1;
begin
for I in 0 to g_counter loop
- v_range_period(I) := (g_range_stop(I) - 1 - g_range_start(I)) / g_range_step(I) + 1; -- Python style range(start, stop, step)
+ -- Python style range(start, stop, step)
+ v_range_period(I) := (g_range_stop(I) - 1 - g_range_start(I)) / g_range_step(I) + 1;
v_period := v_period * v_range_period(I);
end loop;
return v_period;
@@ -97,7 +102,8 @@ architecture tb of tb_dp_counter is
-- flow control
------------------------------------------------------------------------------
constant c_in_random_w : natural := 15;
- constant c_out_random_w : natural := 16; -- use different length per random source
+ -- use different length per random source
+ constant c_out_random_w : natural := 16;
constant c_in_pulse_active : natural := 1;
constant c_out_pulse_active : natural := 1;
constant c_in_pulse_period : natural := 2;
@@ -131,7 +137,8 @@ begin
out_pulse when g_flow_control_verify = e_pulse;
src_in.ready <= out_ready;
- src_in.xon <= not src_in.xon when rising_edge(clk); -- should have no effect, only passed on from src_in to snk_out
+ -- should have no effect, only passed on from src_in to snk_out
+ src_in.xon <= not src_in.xon when rising_edge(clk);
------------------------------------------------------------------------------
-- Clock & reset
@@ -157,7 +164,8 @@ begin
begin
-- run some more intervals for slowest counter, to more view how the slowest counter behaves
for I in 0 to 2 loop
- proc_common_wait_until_hi_lo(clk, count_src_out_arr(g_nof_counters - 1).eop); -- wait for carry over
+ -- wait for carry over
+ proc_common_wait_until_hi_lo(clk, count_src_out_arr(g_nof_counters - 1).eop);
end loop;
tb_end <= '1';
@@ -201,7 +209,8 @@ begin
variable v_cnt : natural := 0;
begin
- period <= c_period; -- to view c_period in wave window
+ -- to view c_period in wave window
+ period <= c_period;
if rising_edge(clk) then
if count_src_out_arr(g_nof_counters - 1).valid = '1' then
assert v_cnt = TO_UINT(src_out.data) report "Wrong cnt at valid : " & int_to_str(v_cnt) severity ERROR;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
index f9ff61dc0cde12b083755783d457d3e0a4726a7e..c197e4845b75c15665a96d3731b1d6f74e5a6750 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
@@ -111,29 +111,42 @@ architecture tb of tb_dp_counter_func is
report "Start tb dp_counter_func";
- dp_counter_func_count_en <= '1'; -- start counting
- proc_common_gen_pulse(clk, tb_start_en); -- check start value
+ -- start counting
+ dp_counter_func_count_en <= '1';
+ -- check start value
+ proc_common_gen_pulse(clk, tb_start_en);
- proc_common_wait_some_cycles(clk, 10); -- wait some time
- dp_counter_func_count_en <= '0'; -- stop counting
- proc_common_wait_some_cycles(clk, 10); -- wait some time
- proc_common_gen_pulse(clk, tb_stopped_en); -- check if counting is stopped
+ -- wait some time
+ proc_common_wait_some_cycles(clk, 10);
+ -- stop counting
+ dp_counter_func_count_en <= '0';
+ -- wait some time
+ proc_common_wait_some_cycles(clk, 10);
+ -- check if counting is stopped
+ proc_common_gen_pulse(clk, tb_stopped_en);
- dp_counter_func_count_en <= '1'; -- start counting again
- tb_step_en <= '1'; -- enable step-size check
+ -- start counting again
+ dp_counter_func_count_en <= '1';
+ -- enable step-size check
+ tb_step_en <= '1';
if g_nof_counters > 1 then
-- issue strobe to check counter carry over
- proc_common_wait_until_lo_hi(clk, dp_counter_func_count_src_out_arr(g_nof_counters - 2).eop); -- wait for carryover
- proc_common_gen_pulse(clk, tb_carryover_en); -- check if dimension carryover is going right
+ -- wait for carryover
+ proc_common_wait_until_lo_hi(clk, dp_counter_func_count_src_out_arr(g_nof_counters - 2).eop);
+ -- check if dimension carryover is going right
+ proc_common_gen_pulse(clk, tb_carryover_en);
end if;
-- keep running for full range counting of the slowest counter
- proc_common_wait_until_hi_lo(clk, dp_counter_func_count_src_out_arr(g_nof_counters - 1).eop); -- wait for carryover
+ -- wait for carryover
+ proc_common_wait_until_hi_lo(clk, dp_counter_func_count_src_out_arr(g_nof_counters - 1).eop);
-- run some more intervals for slowest counter, to more clearly view how the slowest counter behaves
- proc_common_wait_until_hi_lo(clk, dp_counter_func_count_src_out_arr(g_nof_counters - 1).eop); -- wait for carryover
- proc_common_wait_until_hi_lo(clk, dp_counter_func_count_src_out_arr(g_nof_counters - 1).eop); -- wait for carryover
+ -- wait for carryover
+ proc_common_wait_until_hi_lo(clk, dp_counter_func_count_src_out_arr(g_nof_counters - 1).eop);
+ -- wait for carryover
+ proc_common_wait_until_hi_lo(clk, dp_counter_func_count_src_out_arr(g_nof_counters - 1).eop);
report "Stop tb dp_counter_func";
tb_end <= '1';
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
index 0d79d8e8f69e8bfae23a695169653267af9d8078..8d3c6f53aaa7405e6bc1ae750bb1396c771b09ed 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
@@ -44,11 +44,15 @@ use work.tb_dp_pkg.all;
entity tb_dp_counter_offset is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- dut
- g_pipeline_src_out : natural := 1; -- Pipeline source outputs (data,valid,sop,eop etc)
- g_pipeline_src_in : natural := 0; -- Pipeline source inputs (ready,xon). This will also pipeline src_out.
+ -- Pipeline source outputs (data,valid,sop,eop etc)
+ g_pipeline_src_out : natural := 1;
+ -- Pipeline source inputs (ready,xon). This will also pipeline src_out.
+ g_pipeline_src_in : natural := 0;
g_nof_counters : natural := 3;
-- min range = [0,2,1] => (0,1) 'the Python way'
--g_range_start : t_nat_natural_arr(9 DOWNTO 0) := (0,0,0,0,0,0,0, 1, 0, 0);
@@ -88,7 +92,8 @@ architecture tb of tb_dp_counter_offset is
variable v_period : natural := 1;
begin
for I in 0 to g_counter loop
- v_range_period(I) := (g_range_stop(I) - 1 - g_range_start(I)) / g_range_step(I) + 1; -- Python style range(start, stop, step)
+ -- Python style range(start, stop, step)
+ v_range_period(I) := (g_range_stop(I) - 1 - g_range_start(I)) / g_range_step(I) + 1;
v_period := v_period * v_range_period(I);
end loop;
return v_period;
@@ -98,7 +103,8 @@ architecture tb of tb_dp_counter_offset is
-- flow control
------------------------------------------------------------------------------
constant c_in_random_w : natural := 15;
- constant c_out_random_w : natural := 16; -- use different length per random source
+ -- use different length per random source
+ constant c_out_random_w : natural := 16;
constant c_in_pulse_active : natural := 1;
constant c_out_pulse_active : natural := 1;
constant c_in_pulse_period : natural := 2;
@@ -134,7 +140,8 @@ begin
out_pulse when g_flow_control_verify = e_pulse;
src_in.ready <= out_ready;
- src_in.xon <= not src_in.xon when rising_edge(clk); -- should have no effect, only passed on from src_in to snk_out
+ -- should have no effect, only passed on from src_in to snk_out
+ src_in.xon <= not src_in.xon when rising_edge(clk);
------------------------------------------------------------------------------
-- Clock & reset
@@ -160,7 +167,8 @@ begin
begin
-- run some more intervals for slowest counter, to more view how the slowest counter behaves
for I in 0 to 2 loop
- proc_common_wait_until_hi_lo(clk, count_src_out_arr(g_nof_counters - 1).eop); -- wait for carry over
+ -- wait for carry over
+ proc_common_wait_until_hi_lo(clk, count_src_out_arr(g_nof_counters - 1).eop);
end loop;
tb_end <= '1';
@@ -206,7 +214,8 @@ begin
variable v_cnt : natural := 0;
begin
- period <= c_period; -- to view c_period in wave window
+ -- to view c_period in wave window
+ period <= c_period;
if rising_edge(clk) then
if count_src_out_arr(g_nof_counters - 1).valid = '1' then
assert v_cnt = TO_UINT(src_out.data) report "Wrong cnt at valid : " & int_to_str(v_cnt) severity ERROR;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
index 9d28335701b636c9b8b312b85bd018a63ecb8759..afaf3ac1baeb09309e6bbf62474c6620c64abaf9 100755
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
@@ -55,19 +55,22 @@ use work.tb_dp_pkg.all;
entity tb_dp_deinterleave_interleave_to_one is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- always e_active, e_random or e_pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
-- specific
g_use_complex : boolean := false;
g_nof_repeat : natural := 5;
g_nof_streams : natural := 4;
- g_pkt_len : natural := 12; -- typcially multiple of g_nof_streams
+ -- typcially multiple of g_nof_streams
+ g_pkt_len : natural := 12;
g_pkt_gap : natural := 10
);
end tb_dp_deinterleave_interleave_to_one;
architecture tb of tb_dp_deinterleave_interleave_to_one is
constant c_flow_control_verify : t_dp_flow_control_enum := e_active;
- constant c_pipeline : natural := 1; -- 0 for combinatorial, > 0 for registers
+ -- 0 for combinatorial, > 0 for registers
+ constant c_pipeline : natural := 1;
-- Only verify the sosi data fields when g_pkt_len is an integer multiple of g_nof_streams,
-- the sosi info and control fields are always verified using c_out_pkt_len
@@ -87,9 +90,11 @@ architecture tb of tb_dp_deinterleave_interleave_to_one is
constant c_data_init : natural := 0;
constant c_re_init : natural := 7;
constant c_im_init : natural := 17;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
- constant c_channel_init : natural := 5; -- fixed
+ -- fixed
+ constant c_channel_init : natural := 5;
-- dp_stream_verify
constant c_verify_pulse_active : natural := 1;
@@ -99,14 +104,16 @@ architecture tb of tb_dp_deinterleave_interleave_to_one is
constant c_flow_control_latency_rnd : natural := g_nof_repeat * g_pkt_len;
constant c_flow_control_latency : natural := sel_a_b(g_flow_control_stimuli = e_pulse or c_flow_control_verify = e_pulse,
c_flow_control_latency_pls,
- c_flow_control_latency_rnd); -- worst case value
+ -- worst case value
+ c_flow_control_latency_rnd);
constant c_data_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
constant c_dsp_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
--CONSTANT c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := c_dp_sosi_unsigned_rst; -- default 0 is no wrap
constant c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := TO_DP_SOSI_UNSIGNED('0', '0', '0', '0', c_data_max, c_dsp_max, c_dsp_max, c_unsigned_0, c_unsigned_0, c_unsigned_0, c_unsigned_0);
- constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones; -- default only accept increment +1
+ -- default only accept increment +1
+ constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones;
-- both
constant c_sync_period : natural := 10;
@@ -143,12 +150,15 @@ begin
u_dp_stream_stimuli : entity work.dp_stream_stimuli
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 15,
g_pulse_active => c_stimuli_pulse_active,
g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_stimuli,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -164,7 +174,8 @@ begin
g_nof_repeat => g_nof_repeat,
g_pkt_len => g_pkt_len,
g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ g_wait_last_evt => c_flow_control_latency
)
port map (
rst => rst,
@@ -175,9 +186,12 @@ begin
src_out => stimuli_src_out,
-- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ -- expected verify_snk_in after end of stimuli
+ last_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ last_snk_in_evt => last_snk_in_evt,
+ -- signal end of tb as far as this dp_stream_stimuli is concerned
+ tb_end => tb_end
);
-- Throttle stimuli to ensure active = 1, period = 3, level '1'
@@ -189,7 +203,8 @@ begin
-- Select fields that need to be verified
-- . during the test
- verify_snk_in_enable.sync <= '1'; -- or '0'
+ -- or '0'
+ verify_snk_in_enable.sync <= '1';
verify_snk_in_enable.bsn <= '1';
verify_snk_in_enable.data <= '1' when c_verify_data else '0';
verify_snk_in_enable.re <= '1' when c_verify_complex else '0';
@@ -216,12 +231,15 @@ begin
u_dp_stream_verify : entity work.dp_stream_verify
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 14,
g_pulse_active => c_verify_pulse_active,
g_pulse_period => c_verify_pulse_period,
- g_flow_control => c_flow_control_verify, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => c_flow_control_verify,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -240,11 +258,14 @@ begin
snk_in => verify_snk_in,
-- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+ -- enable verify to verify that the verify_snk_in fields are incrementing
+ verify_snk_in_enable => verify_snk_in_enable,
-- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ -- expected verify_snk_in after end of stimuli
+ expected_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ verify_expected_snk_in_evt => verify_last_snk_in_evt
);
------------------------------------------------------------------------------
@@ -255,11 +276,15 @@ begin
g_dat_w => c_data_w,
g_nof_out => g_nof_streams,
g_block_size_int => 1,
- g_block_size_output => c_par_pkt_len, -- Output block size: The number of samles in the blocks at the output
- g_use_ctrl => true, -- Requires: [input block size (sop:eop)] / [g_nof_out]/ [g_block_size_output] = integer number!
- g_use_sync_bsn => true, -- forwards (stored) input Sync+BSN to all output streams
+ -- Output block size: The number of samles in the blocks at the output
+ g_block_size_output => c_par_pkt_len,
+ -- Requires: [input block size (sop:eop)] / [g_nof_out]/ [g_block_size_output] = integer number!
+ g_use_ctrl => true,
+ -- forwards (stored) input Sync+BSN to all output streams
+ g_use_sync_bsn => true,
g_use_complex => g_use_complex,
- g_align_out => true -- Aligns the output streams
+ -- Aligns the output streams
+ g_align_out => true
)
port map (
rst => rst,
@@ -283,9 +308,12 @@ begin
g_use_channel => true,
g_use_error => true,
g_use_sync => true,
- g_use_ctrl => true, -- sop & eop
- g_use_complex => g_use_complex, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size => c_fifo_size -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ -- sop & eop
+ g_use_ctrl => true,
+ -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_use_complex => g_use_complex,
+ -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size => c_fifo_size
)
port map (
rst => rst,
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
index 85bdf4243f1a90661baa7591005d9f1f51df3cd9..9312aa2533ff067714dc2d4a5595d0d8de353a8a 100755
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
@@ -49,15 +49,20 @@ use work.tb_dp_pkg.all;
entity tb_dp_deinterleave_one_to_n_to_one is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- always e_active, e_random or e_pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ -- always e_active, e_random or e_pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
- g_use_fifo : boolean := true; -- use TRUE to break flow control between 1 to N and N to 1
+ -- use TRUE to break flow control between 1 to N and N to 1
+ g_use_fifo : boolean := true;
g_use_complex : boolean := false;
- g_pipeline : natural := 1; -- 0 for combinatorial, > 0 for registers
+ -- 0 for combinatorial, > 0 for registers
+ g_pipeline : natural := 1;
g_nof_repeat : natural := 5;
g_nof_streams : natural := 4;
- g_pkt_len : natural := 12; -- typcially multiple of g_nof_streams
+ -- typcially multiple of g_nof_streams
+ g_pkt_len : natural := 12;
g_pkt_gap : natural := 10
);
end tb_dp_deinterleave_one_to_n_to_one;
@@ -79,9 +84,11 @@ architecture tb of tb_dp_deinterleave_one_to_n_to_one is
constant c_data_init : natural := 0;
constant c_re_init : natural := 7;
constant c_im_init : natural := 17;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
- constant c_channel_init : natural := 5; -- fixed
+ -- fixed
+ constant c_channel_init : natural := 5;
-- dp_stream_verify
constant c_verify_pulse_active : natural := 1;
@@ -91,14 +98,16 @@ architecture tb of tb_dp_deinterleave_one_to_n_to_one is
constant c_flow_control_latency_rnd : natural := g_nof_repeat * g_pkt_len;
constant c_flow_control_latency : natural := sel_a_b(g_flow_control_stimuli = e_pulse or g_flow_control_verify = e_pulse,
c_flow_control_latency_pls,
- c_flow_control_latency_rnd); -- worst case value
+ -- worst case value
+ c_flow_control_latency_rnd);
constant c_data_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
constant c_dsp_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
--CONSTANT c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := c_dp_sosi_unsigned_rst; -- default 0 is no wrap
constant c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := TO_DP_SOSI_UNSIGNED('0', '0', '0', '0', c_data_max, c_dsp_max, c_dsp_max, c_unsigned_0, c_unsigned_0, c_unsigned_0, c_unsigned_0);
- constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones; -- default only accept increment +1
+ -- default only accept increment +1
+ constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones;
-- both
constant c_sync_period : natural := 10;
@@ -135,12 +144,15 @@ begin
u_dp_stream_stimuli : entity work.dp_stream_stimuli
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 15,
g_pulse_active => c_stimuli_pulse_active,
g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_stimuli,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -156,7 +168,8 @@ begin
g_nof_repeat => g_nof_repeat,
g_pkt_len => g_pkt_len,
g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ g_wait_last_evt => c_flow_control_latency
)
port map (
rst => rst,
@@ -167,9 +180,12 @@ begin
src_out => stimuli_src_out,
-- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ -- expected verify_snk_in after end of stimuli
+ last_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ last_snk_in_evt => last_snk_in_evt,
+ -- signal end of tb as far as this dp_stream_stimuli is concerned
+ tb_end => tb_end
);
------------------------------------------------------------------------------
@@ -178,7 +194,8 @@ begin
-- Select fields that need to be verified
-- . during the test
- verify_snk_in_enable.sync <= '1'; -- or '0'
+ -- or '0'
+ verify_snk_in_enable.sync <= '1';
verify_snk_in_enable.bsn <= '1';
verify_snk_in_enable.data <= '1' when c_verify_data else '0';
verify_snk_in_enable.re <= '1' when c_verify_complex else '0';
@@ -205,12 +222,15 @@ begin
u_dp_stream_verify : entity work.dp_stream_verify
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 14,
g_pulse_active => c_verify_pulse_active,
g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_verify,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -229,11 +249,14 @@ begin
snk_in => verify_snk_in,
-- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+ -- enable verify to verify that the verify_snk_in fields are incrementing
+ verify_snk_in_enable => verify_snk_in_enable,
-- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ -- expected verify_snk_in after end of stimuli
+ expected_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ verify_expected_snk_in_evt => verify_last_snk_in_evt
);
------------------------------------------------------------------------------
@@ -274,9 +297,12 @@ begin
g_use_channel => true,
g_use_error => true,
g_use_sync => true,
- g_use_ctrl => true, -- sop & eop
- g_use_complex => g_use_complex, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size => c_fifo_size -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ -- sop & eop
+ g_use_ctrl => true,
+ -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_use_complex => g_use_complex,
+ -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size => c_fifo_size
)
port map (
rst => rst,
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
index 16b878e5441c78ac0f30b5f18b92ea15c83eb997..740dd35d38615a1a2234e23c85d0b67c6ab1ce67 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
@@ -30,7 +30,8 @@ use work.tb_dp_pkg.all;
entity tb_dp_demux is
generic (
-- Try DEMUX settings
- g_dut_nof_output : natural := 1; -- >= 1, when 1 then use array_init() to assign the unconstrained t_natural_arr generic arrays
+ -- >= 1, when 1 then use array_init() to assign the unconstrained t_natural_arr generic arrays
+ g_dut_nof_output : natural := 1;
g_combined : boolean := false
);
end tb_dp_demux;
@@ -39,8 +40,10 @@ architecture tb of tb_dp_demux is
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT
- constant c_dut_in_latency : natural := 1; -- fixed for dp_demux
- constant c_dut_out_latency : natural := 1; -- fixed for dp_demux
+ -- fixed for dp_demux
+ constant c_dut_in_latency : natural := 1;
+ -- fixed for dp_demux
+ constant c_dut_out_latency : natural := 1;
-- The mux input streams have a channel field (c_dp_channel_user_w) and the mux will add some LSBits to represent the
-- input port numbers (c_dut_nof_port_w) in the mux output stream channel field. The total mux output stream channel
@@ -50,17 +53,25 @@ architecture tb of tb_dp_demux is
constant c_mux_channel_w : natural := c_dut_out_channel_w + c_dut_nof_port_w;
-- Stimuli
- constant c_tx_latency : natural := c_dut_in_latency; -- TX ready latency of TB
- constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ -- TX ready latency of TB
+ constant c_tx_latency : natural := c_dut_in_latency;
+ -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0);
constant c_tx_offset_sop : natural := 3;
- constant c_tx_period_sop : natural := 7; -- sop in data valid cycle 3, 10, 17, ...
- constant c_tx_offset_eop : natural := 9; -- eop in data valid cycle 9, 16, 23, ...
+ -- sop in data valid cycle 3, 10, 17, ...
+ constant c_tx_period_sop : natural := 7;
+ -- eop in data valid cycle 9, 16, 23, ...
+ constant c_tx_offset_eop : natural := 9;
constant c_tx_period_eop : natural := c_tx_period_sop;
- constant c_rx_latency : natural := c_dut_out_latency; -- RX ready latency from DUT
- constant c_verify_en_wait : natural := 20; -- wait some cycles before asserting verify enable
+ -- RX ready latency from DUT
+ constant c_rx_latency : natural := c_dut_out_latency;
+ -- wait some cycles before asserting verify enable
+ constant c_verify_en_wait : natural := 20;
- constant c_empty_offset : natural := 1; -- dummy number to distinghuis the empty field from the data field value
- constant c_channel_offset : natural := 2; -- dummy number to distinghuis the channel field from the data field value
+ -- dummy number to distinghuis the empty field from the data field value
+ constant c_empty_offset : natural := 1;
+ -- dummy number to distinghuis the channel field from the data field value
+ constant c_channel_offset : natural := 2;
constant c_random_w : natural := 19;
@@ -163,8 +174,10 @@ begin
-- Stimuli control
-- proc_dp_count_en(rst, clk, sync, lfsr1(I)(c_random_w-1 DOWNTO 0), state(I), verify_done(I), tb_end_vec(I), cnt_en(I)); -- all cnt_en behave the same
-- proc_dp_out_ready(rst, clk, sync, lfsr2(I)(c_random_w DOWNTO 0), out_ready(I)); -- all out_ready behave the same
- proc_dp_count_en(rst, clk, sync_dly(I), lfsr1(I)(c_random_w - 1 downto 0), state(I), verify_done(I), tb_end_vec(I), cnt_en(I)); -- all cnt_en are relatively delayed
- proc_dp_out_ready(rst, clk, sync_dly(I), lfsr2(I)(c_random_w downto 0), out_ready(I)); -- all out_ready are relatively delayed
+ -- all cnt_en are relatively delayed
+ proc_dp_count_en(rst, clk, sync_dly(I), lfsr1(I)(c_random_w - 1 downto 0), state(I), verify_done(I), tb_end_vec(I), cnt_en(I));
+ -- all out_ready are relatively delayed
+ proc_dp_out_ready(rst, clk, sync_dly(I), lfsr2(I)(c_random_w downto 0), out_ready(I));
-- Output mapping
out_data(I) <= demux_data( (I + 1) * c_dp_data_w - 1 downto I * c_dp_data_w);
@@ -181,7 +194,8 @@ begin
proc_dp_verify_valid(c_rx_latency, clk, verify_en, out_ready(I), prev_out_ready(I), out_val(I));
proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", clk, verify_en, out_data(I), out_val(I), out_sop(I));
proc_dp_verify_ctrl(c_tx_offset_eop, c_tx_period_eop, "eop", clk, verify_en, out_data(I), out_val(I), out_eop(I));
- proc_dp_verify_sop_and_eop(clk, out_val(I), out_sop(I), out_eop(I), hold_out_sop(I)); -- Verify that sop and eop come in pairs
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(clk, out_val(I), out_sop(I), out_eop(I), hold_out_sop(I));
-- No need to use g_dut_use_empty, because empty is taken care of by default when the FIFO is not used in dp_mux
proc_dp_verify_other_sosi("empty", INCR_UVEC(out_data(I), c_empty_offset), clk, verify_en, out_empty(I));
@@ -196,8 +210,10 @@ begin
p_in : process(in_siso, in_data_vec, in_empty_vec, in_channel_vec, in_val, in_sop, in_eop)
begin
for I in 0 to g_dut_nof_output - 1 loop
- in_ready(I) <= in_siso(I).ready; -- SISO
- in_sosi(I).data( c_dp_data_w - 1 downto 0) <= in_data_vec( (I + 1) * c_dp_data_w - 1 downto I * c_dp_data_w); -- SOSI
+ -- SISO
+ in_ready(I) <= in_siso(I).ready;
+ -- SOSI
+ in_sosi(I).data( c_dp_data_w - 1 downto 0) <= in_data_vec( (I + 1) * c_dp_data_w - 1 downto I * c_dp_data_w);
in_sosi(I).empty <= in_empty_vec( c_dp_empty_w + I * c_dp_data_w - 1 downto I * c_dp_data_w);
in_sosi(I).channel <= in_channel_vec(c_dp_channel_w + I * c_dp_data_w - 1 downto I * c_dp_data_w);
in_sosi(I).valid <= in_val(I);
@@ -209,8 +225,10 @@ begin
p_out : process(demux_ready, demux_sosi)
begin
for I in 0 to g_dut_nof_output - 1 loop
- demux_siso(I).ready <= demux_ready(I); -- SISO
- demux_data( (I + 1) * c_dp_data_w - 1 downto I * c_dp_data_w) <= demux_sosi(I).data( c_dp_data_w - 1 downto 0); -- SOSI
+ -- SISO
+ demux_siso(I).ready <= demux_ready(I);
+ -- SOSI
+ demux_data( (I + 1) * c_dp_data_w - 1 downto I * c_dp_data_w) <= demux_sosi(I).data( c_dp_data_w - 1 downto 0);
demux_empty( c_dp_empty_w + I * c_dp_data_w - 1 downto I * c_dp_data_w) <= demux_sosi(I).empty;
demux_channel(c_dp_channel_w + I * c_dp_data_w - 1 downto I * c_dp_data_w) <= demux_sosi(I).channel;
demux_val(I) <= demux_sosi(I).valid;
@@ -230,17 +248,21 @@ begin
g_use_error => false,
g_nof_input => g_dut_nof_output,
g_use_fifo => false,
- g_fifo_size => array_init(1024, g_dut_nof_output), -- FIFO is not used, but generic must match g_nof_input
- g_fifo_fill => array_init( 0, g_dut_nof_output) -- FIFO is not used, but generic must match g_nof_input
+ -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_size => array_init(1024, g_dut_nof_output),
+ -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_fill => array_init( 0, g_dut_nof_output)
)
port map (
rst => rst,
clk => clk,
-- ST sinks
- snk_out_arr => in_siso, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out_arr => in_siso,
snk_in_arr => in_sosi,
-- ST source
- src_in => mux_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => mux_siso,
src_out => mux_sosi
);
@@ -257,10 +279,12 @@ begin
rst => rst,
clk => clk,
-- ST sinks
- snk_out => mux_siso, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out => mux_siso,
snk_in => mux_sosi,
-- ST source
- src_in_arr => demux_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in_arr => demux_siso,
src_out_arr => demux_sosi
);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd b/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
index 6fe69179dad03f809521fe4c9c25d49f673c7552..a6d7f36ed07ce954b3e6b9b445953f9a3dae5001 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
@@ -50,9 +50,12 @@ use work.tb_dp_pkg.all;
entity tb_dp_distribute is
generic (
-- Try flow control
- g_in_en : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_out_ready : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
- g_nof_repeat : natural := 100; -- >= 1, number of frames
+ -- always active, random or pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_random;
+ -- >= 1, number of frames
+ g_nof_repeat : natural := 100;
-- Try DP link decoding or encoding
g_code_channel_lo : boolean := true;
-- Try input FIFO for Tx distribute
@@ -65,8 +68,10 @@ entity tb_dp_distribute is
g_data_init_offset : integer := 10;
g_frame_len_offset : integer := 0;
-- Try distribute settings
- g_nof_input : natural := 4; -- = n
- g_nof_serial : natural := 3; -- = m
+ -- = n
+ g_nof_input : natural := 4;
+ -- = m
+ g_nof_serial : natural := 3;
g_transpose : boolean := false
);
end tb_dp_distribute;
@@ -85,11 +90,14 @@ architecture tb of tb_dp_distribute is
constant c_sync_offset : natural := 2;
constant c_data_w : natural := 16;
- constant c_fifo_size : natural := 32; -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
+ -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
+ constant c_fifo_size : natural := 32;
constant c_link_channel_lo : natural := ceil_log2(g_nof_serial);
- constant c_rx_use_fifo_link_channel_lo : boolean := not g_code_channel_lo; -- FALSE when the link_channel_lo is coded in the CHAN field of the DP packet data, else it needs to go in parallel through the Rx FIFO
+ -- FALSE when the link_channel_lo is coded in the CHAN field of the DP packet data, else it needs to go in parallel through the Rx FIFO
+ constant c_rx_use_fifo_link_channel_lo : boolean := not g_code_channel_lo;
- subtype t_data_arr is t_slv_16_arr(0 to g_nof_input - 1); -- width 16 must match c_data_w
+ -- width 16 must match c_data_w
+ subtype t_data_arr is t_slv_16_arr(0 to g_nof_input - 1);
type t_rl_vec_arr is array (0 to g_nof_input - 1) of std_logic_vector(0 to c_rl);
signal tb_end_vec : std_logic_vector(0 to g_nof_input - 1) := (others => '0');
@@ -97,8 +105,10 @@ architecture tb of tb_dp_distribute is
signal clk : std_logic := '1';
signal rst : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -169,8 +179,10 @@ begin
variable v_frame_len : natural;
variable v_sync : std_logic;
begin
- v_data_init := c_data_init + I * g_data_init_offset; -- offset the frame data for each input, so the inputs can be recognized at the output
- v_frame_len := c_frame_len + I * g_frame_len_offset; -- offset the frame length for each input, so the inputs can be recognized at the output
+ -- offset the frame data for each input, so the inputs can be recognized at the output
+ v_data_init := c_data_init + I * g_data_init_offset;
+ -- offset the frame length for each input, so the inputs can be recognized at the output
+ v_frame_len := c_frame_len + I * g_frame_len_offset;
in_sosi_arr(I) <= c_dp_sosi_rst;
proc_common_wait_until_low(clk, rst);
proc_common_wait_some_cycles(clk, 5);
@@ -188,8 +200,10 @@ begin
end loop;
-- End of stimuli
- proc_common_wait_until_high(clk, verify_end(I)); -- in case of using FIFOs verify_done is issued somewhat before the output will stop due to c_nof_expected
- proc_common_wait_some_cycles(clk, 10 * c_frame_len_max); -- continue some more after verify_done to see that the output has stopped
+ -- in case of using FIFOs verify_done is issued somewhat before the output will stop due to c_nof_expected
+ proc_common_wait_until_high(clk, verify_end(I));
+ -- continue some more after verify_done to see that the output has stopped
+ proc_common_wait_some_cycles(clk, 10 * c_frame_len_max);
tb_end_vec(I) <= '1';
wait;
end process;
@@ -201,27 +215,36 @@ begin
gen_verify : for I in 0 to g_nof_input - 1 generate
-- Verification logistics
- verify_en(I) <= '1' when rising_edge(clk) and out_sosi_arr(I).sop = '1'; -- enable verify after first output sop
- count_eop(I) <= count_eop(I) + 1 when rising_edge(clk) and out_sosi_arr(I).eop = '1'; -- count number of output eop
+ -- enable verify after first output sop
+ verify_en(I) <= '1' when rising_edge(clk) and out_sosi_arr(I).sop = '1';
+ -- count number of output eop
+ count_eop(I) <= count_eop(I) + 1 when rising_edge(clk) and out_sosi_arr(I).eop = '1';
prev_count_eop(I) <= count_eop(I) when rising_edge(clk);
verify_done(I) <= '1' when rising_edge(clk) and count_eop(I) = c_nof_expected and count_eop(I) /= prev_count_eop(I) else
- '0' when rising_edge(clk); -- signal verify done after c_nof_expected frames, use pulse to have only one assert from proc_dp_verify_value()
- verify_end(I) <= '1' when rising_edge(clk) and verify_done(I) = '1'; -- signal verify_end after verify_done pulse, use level to ensure tb_end even if the stimuli are still busy
+ -- signal verify done after c_nof_expected frames, use pulse to have only one assert from proc_dp_verify_value()
+ '0' when rising_edge(clk);
+ -- signal verify_end after verify_done pulse, use level to ensure tb_end even if the stimuli are still busy
+ verify_end(I) <= '1' when rising_edge(clk) and verify_done(I) = '1';
-- Actual verification of the output streams
- proc_dp_verify_data("out_sosi_arr.data", c_rl, clk, verify_en(I), out_siso_arr(I).ready, out_sosi_arr(I).valid, out_data(I), prev_out_data(I)); -- Verify that the output is incrementing data, like the input stimuli
- proc_dp_verify_valid(c_rl, clk, verify_en(I), out_siso_arr(I).ready, prev_out_ready(I), out_sosi_arr(I).valid); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_sop_and_eop(clk, out_sosi_arr(I).valid, out_sosi_arr(I).sop, out_sosi_arr(I).eop, hold_out_sop(I)); -- Verify that sop and eop come in pairs
+ -- Verify that the output is incrementing data, like the input stimuli
+ proc_dp_verify_data("out_sosi_arr.data", c_rl, clk, verify_en(I), out_siso_arr(I).ready, out_sosi_arr(I).valid, out_data(I), prev_out_data(I));
+ -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_valid(c_rl, clk, verify_en(I), out_siso_arr(I).ready, prev_out_ready(I), out_sosi_arr(I).valid);
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(clk, out_sosi_arr(I).valid, out_sosi_arr(I).sop, out_sosi_arr(I).eop, hold_out_sop(I));
proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en(I), out_sosi_arr(I).sync, out_sosi_arr(I).sop, out_sosi_arr(I).bsn);
gen_at_least : if g_tx_use_fifo = true or g_tx_use_fifo = true generate
-- Use at least because there will still be some frames in the FIFO due to the required fill level
- proc_dp_verify_value(e_at_least, clk, verify_done(I), expected_out_data(I), prev_out_data(I)); -- Verify that the stimuli have been applied at all
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_at_least, clk, verify_done(I), expected_out_data(I), prev_out_data(I));
end generate;
gen_equal : if g_tx_use_fifo = false and g_tx_use_fifo = false generate
-- Use equal because without FIFOs all frames must come through
- proc_dp_verify_value(e_equal, clk, verify_done(I), expected_out_data(I), prev_out_data(I)); -- Verify that the stimuli have been applied at all
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done(I), expected_out_data(I), prev_out_data(I));
end generate;
-- Monitoring
@@ -286,7 +309,8 @@ begin
g_use_fifo => g_rx_use_fifo,
g_bsn_w => c_data_w,
g_empty_w => 1,
- g_channel_w => c_link_channel_lo, -- c_link_channel_lo-1 DOWNTO 0
+ -- c_link_channel_lo-1 DOWNTO 0
+ g_channel_w => c_link_channel_lo,
g_error_w => 1,
g_use_bsn => g_rx_use_fifo,
g_use_empty => false,
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd b/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
index 464fd24ca51e27772f1d3b83c3c6d3d085ec2eb5..2a0d17a3fbd7b612028feb2b6b2ad2040994b6f5 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
@@ -131,8 +131,10 @@ use work.tb_dp_pkg.all;
entity tb_dp_example_dut is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_random;
-- specific
g_no_dut : boolean := false;
g_dat_w : natural := 16;
@@ -148,9 +150,11 @@ architecture tb of tb_dp_example_dut is
constant c_stimuli_pulse_period : natural := 7;
constant c_data_init : natural := 0;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
- constant c_channel_init : natural := 5; -- fixed
+ -- fixed
+ constant c_channel_init : natural := 5;
-- dp_stream_verify
constant c_verify_pulse_active : natural := 1;
@@ -161,7 +165,8 @@ architecture tb of tb_dp_example_dut is
--CONSTANT c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := c_dp_sosi_unsigned_rst; -- default 0 is no wrap
constant c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := TO_DP_SOSI_UNSIGNED('0', '0', '0', '0', c_data_max, c_dsp_max, c_dsp_max, c_unsigned_0, c_unsigned_0, c_unsigned_0, c_unsigned_0);
- constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones; -- default only accept increment +1
+ -- default only accept increment +1
+ constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones;
-- both
constant c_sync_period : natural := 10;
@@ -199,12 +204,15 @@ begin
u_dp_stream_stimuli : entity work.dp_stream_stimuli
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 15,
g_pulse_active => c_stimuli_pulse_active,
g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_stimuli,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -227,9 +235,12 @@ begin
src_out => stimuli_src_out,
-- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ -- expected verify_snk_in after end of stimuli
+ last_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ last_snk_in_evt => last_snk_in_evt,
+ -- signal end of tb as far as this dp_stream_stimuli is concerned
+ tb_end => tb_end
);
------------------------------------------------------------------------------
@@ -238,7 +249,8 @@ begin
-- Select fields that need to be verified
-- . during the test
- verify_snk_in_enable.sync <= '1'; -- or '0'
+ -- or '0'
+ verify_snk_in_enable.sync <= '1';
verify_snk_in_enable.bsn <= '1';
verify_snk_in_enable.data <= '1';
verify_snk_in_enable.re <= '0';
@@ -265,12 +277,15 @@ begin
u_dp_stream_verify : entity work.dp_stream_verify
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 14,
g_pulse_active => c_verify_pulse_active,
g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_verify,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -289,11 +304,14 @@ begin
snk_in => verify_snk_in,
-- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+ -- enable verify to verify that the verify_snk_in fields are incrementing
+ verify_snk_in_enable => verify_snk_in_enable,
-- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ -- expected verify_snk_in after end of stimuli
+ expected_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ verify_expected_snk_in_evt => verify_last_snk_in_evt
);
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd b/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
index 7cf8b884b245a1a100016b9349c80f8aae027225..ef9bf013ea40e72365eb954c2f791535477252c8 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
@@ -122,13 +122,16 @@ use work.tb_dp_pkg.all;
entity tb_dp_example_no_dut is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse;
+ -- always active, random or pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
g_in_dat_w : natural := 32;
g_in_nof_words : natural := 1;
g_nof_repeat : natural := 5;
- g_pkt_len : natural := 16; -- must be a multiple of g_in_nof_words
+ -- must be a multiple of g_in_nof_words
+ g_pkt_len : natural := 16;
g_pkt_gap : natural := 4
);
end tb_dp_example_no_dut;
@@ -145,17 +148,21 @@ architecture tb of tb_dp_example_no_dut is
constant c_data_max : unsigned(g_in_dat_w - 1 downto 0) := (others => '1');
constant c_data_init : integer := -1;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
- constant c_channel_init : integer := 5; -- fixed
+ -- fixed
+ constant c_channel_init : integer := 5;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal sl1 : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -174,7 +181,8 @@ architecture tb of tb_dp_example_no_dut is
signal prev_verify_snk_out : t_dp_siso;
signal verify_snk_out : t_dp_siso := c_dp_siso_rdy;
signal verify_snk_in : t_dp_sosi;
- signal verify_snk_in_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0); -- used to hold valid data for verify at verify_done
+ -- used to hold valid data for verify at verify_done
+ signal verify_snk_in_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0);
signal verify_data : std_logic_vector(g_in_dat_w - 1 downto 0);
signal prev_verify_snk_in : t_dp_sosi;
@@ -231,10 +239,12 @@ begin
for I in 0 to g_nof_repeat - 1 loop
-- Auto increment v_sosi field values for this packet
v_sosi.bsn := INCR_UVEC(v_sosi.bsn, 1);
- v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_sync_period) = c_sync_offset, '1', '0'); -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_sync_period) = c_sync_offset, '1', '0');
v_sosi.channel := INCR_UVEC(v_sosi.channel, 1);
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
v_sosi.err := INCR_UVEC(v_sosi.err, 1);
-- Send packet
@@ -251,11 +261,13 @@ begin
v_sosi.err := TO_DP_ERROR(c_err_init + g_nof_repeat - 1);
-- . account for g_pkt_len
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len - 1);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
expected_verify_snk_in <= v_sosi;
-- Signal end of stimuli
- proc_common_wait_some_cycles(clk, 100); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ proc_common_wait_some_cycles(clk, 100);
proc_common_gen_pulse(clk, verify_done);
proc_common_wait_some_cycles(clk, 50);
tb_end <= '1';
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
index 2c5c009486395e7a4878c2fc6831f797ae1edb3a..b96553c2d512906e7ee323d674844a9cd81c8de8 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
@@ -30,14 +30,17 @@ use work.tb_dp_pkg.all;
entity tb_dp_fifo_dc is
generic (
-- Try FIFO settings
- g_dut_wr_clk_freq : positive := 2; -- normalized write clock frequency
- g_dut_rd_clk_freq : positive := 3; -- normalized read clock frequency
+ -- normalized write clock frequency
+ g_dut_wr_clk_freq : positive := 2;
+ -- normalized read clock frequency
+ g_dut_rd_clk_freq : positive := 3;
g_dut_use_bsn : boolean := true;
g_dut_use_empty : boolean := true;
g_dut_use_channel : boolean := true;
g_dut_use_sync : boolean := true;
g_dut_use_ctrl : boolean := true;
- g_dut_out_latency : natural := 1 -- selectable for dp_fifo_dc: default 1 or 0 for look ahead FIFO
+ -- selectable for dp_fifo_dc: default 1 or 0 for look ahead FIFO
+ g_dut_out_latency : natural := 1
);
end tb_dp_fifo_dc;
@@ -46,19 +49,27 @@ architecture tb of tb_dp_fifo_dc is
-- DUT
constant c_dut_fifo_size : natural := 64;
- constant c_dut_in_latency : natural := 1; -- fixed for dp_fifo_dc
+ -- fixed for dp_fifo_dc
+ constant c_dut_in_latency : natural := 1;
-- Stimuli
- constant c_tx_latency : natural := c_dut_in_latency; -- TX ready latency of TB
- constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ -- TX ready latency of TB
+ constant c_tx_latency : natural := c_dut_in_latency;
+ -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0);
constant c_tx_offset_sop : natural := 3;
- constant c_tx_period_sop : natural := 7; -- sop in data valid cycle 3, 10, 17, ...
- constant c_tx_offset_eop : natural := 5; -- eop in data valid cycle 5, 12, 19, ...
+ -- sop in data valid cycle 3, 10, 17, ...
+ constant c_tx_period_sop : natural := 7;
+ -- eop in data valid cycle 5, 12, 19, ...
+ constant c_tx_offset_eop : natural := 5;
constant c_tx_period_eop : natural := c_tx_period_sop;
- constant c_tx_offset_sync : natural := 3; -- sync in data valid cycle 3, 20, 37, ...
+ -- sync in data valid cycle 3, 20, 37, ...
+ constant c_tx_offset_sync : natural := 3;
constant c_tx_period_sync : natural := 17;
- constant c_rx_latency : natural := g_dut_out_latency; -- RX ready latency from DUT
- constant c_verify_en_wait : natural := 20; -- wait some cycles before asserting verify enable
+ -- RX ready latency from DUT
+ constant c_rx_latency : natural := g_dut_out_latency;
+ -- wait some cycles before asserting verify enable
+ constant c_verify_en_wait : natural := 20;
constant c_bsn_offset : natural := 1;
constant c_empty_offset : natural := 2;
@@ -175,8 +186,10 @@ begin
------------------------------------------------------------------------------
-- map sl, slv to record
- in_ready <= in_siso.ready; -- SISO
- in_sosi.data(c_dp_data_w - 1 downto 0) <= in_data; -- SOSI
+ -- SISO
+ in_ready <= in_siso.ready;
+ -- SOSI
+ in_sosi.data(c_dp_data_w - 1 downto 0) <= in_data;
in_sosi.bsn(c_dp_bsn_w - 1 downto 0) <= in_bsn(c_dp_bsn_w - 1 downto 0);
in_sosi.empty <= in_empty(c_dp_empty_w - 1 downto 0);
in_sosi.channel <= in_channel(c_dp_channel_w - 1 downto 0);
@@ -185,8 +198,10 @@ begin
in_sosi.sop <= in_sop;
in_sosi.eop <= in_eop;
- out_siso.ready <= out_ready; -- SISO
- out_data <= out_sosi.data(c_dp_data_w - 1 downto 0); -- SOSI
+ -- SISO
+ out_siso.ready <= out_ready;
+ -- SOSI
+ out_data <= out_sosi.data(c_dp_data_w - 1 downto 0);
out_bsn(c_dp_bsn_w - 1 downto 0) <= out_sosi.bsn(c_dp_bsn_w - 1 downto 0);
out_empty(c_dp_empty_w - 1 downto 0) <= out_sosi.empty;
out_channel(c_dp_channel_w - 1 downto 0) <= out_sosi.channel;
@@ -216,11 +231,13 @@ begin
wr_clk => wr_clk,
rd_rst => rst,
rd_clk => rd_clk,
- snk_out => in_siso, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out => in_siso,
snk_in => in_sosi,
wr_usedw => usedw,
rd_usedw => OPEN,
- src_in => out_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => out_siso,
src_out => out_sosi
);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
index 5c75f0d420d57874dea2b76072bc5b1309c7d920..c0fcbbb40408ca94cb5538a398620cacdef748a7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
@@ -36,15 +36,18 @@ entity tb_dp_fifo_dc_arr is
generic (
-- Try FIFO settings
g_dut_nof_streams : natural := 3;
- g_dut_wr_clk_freq : positive := 2; -- normalized write clock frequency
- g_dut_rd_clk_freq : positive := 3; -- normalized read clock frequency
+ -- normalized write clock frequency
+ g_dut_wr_clk_freq : positive := 2;
+ -- normalized read clock frequency
+ g_dut_rd_clk_freq : positive := 3;
g_dut_use_bsn : boolean := true;
g_dut_use_empty : boolean := true;
g_dut_use_channel : boolean := true;
g_dut_use_sync : boolean := true;
g_dut_use_ctrl : boolean := true;
g_dut_use_aux : boolean := true;
- g_dut_out_latency : natural := 1 -- selectable for dp_fifo_dc_arr: default 1 or 0 for look ahead FIFO
+ -- selectable for dp_fifo_dc_arr: default 1 or 0 for look ahead FIFO
+ g_dut_out_latency : natural := 1
);
end tb_dp_fifo_dc_arr;
@@ -53,19 +56,27 @@ architecture tb of tb_dp_fifo_dc_arr is
-- DUT
constant c_dut_fifo_size : natural := 64;
- constant c_dut_in_latency : natural := 1; -- fixed for dp_fifo_dc_arr
+ -- fixed for dp_fifo_dc_arr
+ constant c_dut_in_latency : natural := 1;
-- Stimuli
- constant c_tx_latency : natural := c_dut_in_latency; -- TX ready latency of TB
- constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ -- TX ready latency of TB
+ constant c_tx_latency : natural := c_dut_in_latency;
+ -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0);
constant c_tx_offset_sop : natural := 3;
- constant c_tx_period_sop : natural := 7; -- sop in data valid cycle 3, 10, 17, ...
- constant c_tx_offset_eop : natural := 5; -- eop in data valid cycle 5, 12, 19, ...
+ -- sop in data valid cycle 3, 10, 17, ...
+ constant c_tx_period_sop : natural := 7;
+ -- eop in data valid cycle 5, 12, 19, ...
+ constant c_tx_offset_eop : natural := 5;
constant c_tx_period_eop : natural := c_tx_period_sop;
- constant c_tx_offset_sync : natural := 3; -- sync in data valid cycle 3, 20, 37, ...
+ -- sync in data valid cycle 3, 20, 37, ...
+ constant c_tx_offset_sync : natural := 3;
constant c_tx_period_sync : natural := 17;
- constant c_rx_latency : natural := g_dut_out_latency; -- RX ready latency from DUT
- constant c_verify_en_wait : natural := 20; -- wait some cycles before asserting verify enable
+ -- RX ready latency from DUT
+ constant c_rx_latency : natural := g_dut_out_latency;
+ -- wait some cycles before asserting verify enable
+ constant c_verify_en_wait : natural := 20;
constant c_bsn_offset : natural := 1;
constant c_empty_offset : natural := 2;
@@ -188,11 +199,14 @@ begin
------------------------------------------------------------------------------
-- map sl, slv to record
- in_ready <= in_siso_arr(0).ready; -- SISO
- in_aux <= in_sync; -- use sync to test aux data
+ -- SISO
+ in_ready <= in_siso_arr(0).ready;
+ -- use sync to test aux data
+ in_aux <= in_sync;
gen_streams : for I in 0 to g_dut_nof_streams - 1 generate
- in_sosi_arr(I).data(c_dp_data_w - 1 downto 0) <= in_data; -- SOSI
+ -- SOSI
+ in_sosi_arr(I).data(c_dp_data_w - 1 downto 0) <= in_data;
in_sosi_arr(I).bsn(c_dp_bsn_w - 1 downto 0) <= in_bsn(c_dp_bsn_w - 1 downto 0);
in_sosi_arr(I).empty <= in_empty(c_dp_empty_w - 1 downto 0);
in_sosi_arr(I).channel <= in_channel(c_dp_channel_w - 1 downto 0);
@@ -200,10 +214,12 @@ begin
in_sosi_arr(I).valid <= in_val;
in_sosi_arr(I).sop <= in_sop;
in_sosi_arr(I).eop <= in_eop;
- out_siso_arr(I).ready <= out_ready; -- SISO
+ -- SISO
+ out_siso_arr(I).ready <= out_ready;
end generate;
- out_data <= out_sosi_arr(0).data(c_dp_data_w - 1 downto 0); -- SOSI
+ -- SOSI
+ out_data <= out_sosi_arr(0).data(c_dp_data_w - 1 downto 0);
out_bsn(c_dp_bsn_w - 1 downto 0) <= out_sosi_arr(0).bsn(c_dp_bsn_w - 1 downto 0);
out_empty(c_dp_empty_w - 1 downto 0) <= out_sosi_arr(0).empty;
out_channel(c_dp_channel_w - 1 downto 0) <= out_sosi_arr(0).channel;
@@ -236,12 +252,14 @@ begin
wr_clk => wr_clk,
rd_rst => rst,
rd_clk => rd_clk,
- snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out_arr => in_siso_arr,
snk_in_arr => in_sosi_arr,
in_aux(0) => in_aux,
wr_usedw => usedw,
rd_usedw => OPEN,
- src_in_arr => out_siso_arr, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in_arr => out_siso_arr,
src_out_arr => out_sosi_arr,
out_aux(0) => out_aux
);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
index 58dfd08b6b86182b08636a4040a432cc9bccb9f0..7fa16e1bc32b20bf637e7b8426a41af0610e3525 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
@@ -44,11 +44,13 @@ end tb_dp_fifo_dc_mixed_widths;
architecture tb of tb_dp_fifo_dc_mixed_widths is
constant c_rl : natural := 1;
- constant c_wr_fifo_size : natural := 128; -- use same nof words for both n2w FIFO and w2n FIFO, hence the w2n FIFO is bigger
+ -- use same nof words for both n2w FIFO and w2n FIFO, hence the w2n FIFO is bigger
+ constant c_wr_fifo_size : natural := 128;
constant c_long_frame_len : natural := c_wr_fifo_size * 5;
constant c_wide_w : natural := g_nof_narrow * g_narrow_w;
- constant c_verify_mode : boolean := sel_a_b(g_use_ctrl, false, true); -- use mode FALSE to verify per frame
+ -- use mode FALSE to verify per frame
+ constant c_verify_mode : boolean := sel_a_b(g_use_ctrl, false, true);
signal tb_end : std_logic := '0';
signal narrow_rst : std_logic;
@@ -57,7 +59,8 @@ architecture tb of tb_dp_fifo_dc_mixed_widths is
signal wide_clk : std_logic := '0';
signal arst : std_logic;
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal in_en : std_logic := '1';
@@ -125,12 +128,18 @@ begin
p_test_fifo_afull : process
begin
out_en <= '1';
- wait until test_fifo_afull = '1'; -- default enable output ready until the fifo almost full test has to start
- out_en <= '0'; -- disable the output to start the fifo almost full test
- proc_common_wait_some_cycles(narrow_clk, 10); -- wait some more cycles
- wait until in_siso.ready = '0'; -- when the n2w FIFO is almost full then it will pull its ready low
- proc_common_wait_some_cycles(narrow_clk, 10); -- wait some more cycles
- out_en <= '1'; -- enable the output again to leave this dead lock state
+ -- default enable output ready until the fifo almost full test has to start
+ wait until test_fifo_afull = '1';
+ -- disable the output to start the fifo almost full test
+ out_en <= '0';
+ -- wait some more cycles
+ proc_common_wait_some_cycles(narrow_clk, 10);
+ -- when the n2w FIFO is almost full then it will pull its ready low
+ wait until in_siso.ready = '0';
+ -- wait some more cycles
+ proc_common_wait_some_cycles(narrow_clk, 10);
+ -- enable the output again to leave this dead lock state
+ out_en <= '1';
end process;
p_stimuli : process
@@ -141,7 +150,8 @@ begin
verify_done <= '0';
wait until arst = '0';
proc_common_wait_some_cycles(wide_clk, 10);
- proc_common_wait_some_cycles(narrow_clk, 10); -- ensure that n2w and w2n FIFOs are out of internal reset, and align to narrow_clk
+ -- ensure that n2w and w2n FIFOs are out of internal reset, and align to narrow_clk
+ proc_common_wait_some_cycles(narrow_clk, 10);
-- Frame data with incrementing data over all frames, so the data can also be used as unframed stimuli
v_init := 0; v_len := 0;
@@ -176,10 +186,13 @@ begin
test_fifo_afull <= '0';
v_init := v_init + v_len;
- expected_exact <= TO_UVEC(v_init - 1, g_narrow_w); -- used for framed data
- expected_about <= TO_UVEC(v_init - g_nof_narrow, g_narrow_w); -- for unframed data there may still be some symbols pending in the n2w FIFO, waiting for a wide word to have filled
+ -- used for framed data
+ expected_exact <= TO_UVEC(v_init - 1, g_narrow_w);
+ -- for unframed data there may still be some symbols pending in the n2w FIFO, waiting for a wide word to have filled
+ expected_about <= TO_UVEC(v_init - g_nof_narrow, g_narrow_w);
- wait until fifo_w2n_rd_emp = '1'; -- ensure that FIFOs have been read empty
+ -- ensure that FIFOs have been read empty
+ wait until fifo_w2n_rd_emp = '1';
proc_common_wait_some_cycles(narrow_clk, 20);
verify_done <= '1';
proc_common_wait_some_cycles(narrow_clk, 1);
@@ -283,10 +296,12 @@ begin
proc_dp_verify_gap_invalid(narrow_clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, out_gap);
-- . Check that the test has ran at all
- proc_dp_verify_value(e_at_least, narrow_clk, verify_done, expected_about, prev_out_data); -- for unframed data we know at least what to expect
+ -- for unframed data we know at least what to expect
+ proc_dp_verify_value(e_at_least, narrow_clk, verify_done, expected_about, prev_out_data);
gen_exact : if g_use_ctrl = true generate
- proc_dp_verify_value(e_equal, narrow_clk, verify_done, expected_exact, prev_out_data); -- for framed data we know exactly what to expect
+ -- for framed data we know exactly what to expect
+ proc_dp_verify_value(e_equal, narrow_clk, verify_done, expected_exact, prev_out_data);
end generate;
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
index d6ad771c2a194788d7163a489de69e9fd2f48d52..f8bf6e92d40d22a3538d84317d01fdccf3561287 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
@@ -48,9 +48,11 @@ entity tb_dp_fifo_fill is
g_dut_use_empty : boolean := false;
g_dut_use_channel : boolean := false;
g_dut_use_sync : boolean := false;
- g_dut_fifo_rl : natural := 1; -- internal RL, use 0 for look ahead FIFO, default 1 for normal FIFO
+ -- internal RL, use 0 for look ahead FIFO, default 1 for normal FIFO
+ g_dut_fifo_rl : natural := 1;
g_dut_fifo_size : natural := 64;
- g_dut_fifo_fill : natural := 64 -- selectable >= 0 for dp_fifo_fill
+ -- selectable >= 0 for dp_fifo_fill
+ g_dut_fifo_fill : natural := 64
);
end tb_dp_fifo_fill;
@@ -58,20 +60,29 @@ architecture tb of tb_dp_fifo_fill is
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT
- constant c_dut_in_latency : natural := 1; -- fixed for dp_fifo_fill
- constant c_dut_out_latency : natural := 1; -- fixed for dp_fifo_fill, only internally dp_fifo_fill may use RL=0 or 1 dependent on g_dut_fifo_rl
+ -- fixed for dp_fifo_fill
+ constant c_dut_in_latency : natural := 1;
+ -- fixed for dp_fifo_fill, only internally dp_fifo_fill may use RL=0 or 1 dependent on g_dut_fifo_rl
+ constant c_dut_out_latency : natural := 1;
-- Stimuli
- constant c_tx_latency : natural := c_dut_in_latency; -- TX ready latency of TB
- constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ -- TX ready latency of TB
+ constant c_tx_latency : natural := c_dut_in_latency;
+ -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0);
constant c_tx_offset_sop : natural := 3;
- constant c_tx_period_sop : natural := 7; -- sop in data valid cycle 3, 10, 17, ...
- constant c_tx_offset_eop : natural := 9; -- eop in data valid cycle 9, 16, 23, ...
+ -- sop in data valid cycle 3, 10, 17, ...
+ constant c_tx_period_sop : natural := 7;
+ -- eop in data valid cycle 9, 16, 23, ...
+ constant c_tx_offset_eop : natural := 9;
constant c_tx_period_eop : natural := c_tx_period_sop;
- constant c_tx_offset_sync : natural := 3; -- sync in data valid cycle 3, 20, 37, ...
+ -- sync in data valid cycle 3, 20, 37, ...
+ constant c_tx_offset_sync : natural := 3;
constant c_tx_period_sync : natural := 17;
- constant c_rx_latency : natural := c_dut_out_latency; -- RX ready latency from DUT
- constant c_verify_en_wait : natural := 20 + g_dut_fifo_fill; -- wait some cycles before asserting verify enable
+ -- RX ready latency from DUT
+ constant c_rx_latency : natural := c_dut_out_latency;
+ -- wait some cycles before asserting verify enable
+ constant c_verify_en_wait : natural := 20 + g_dut_fifo_fill;
constant c_verify_data_en : boolean := c_tx_offset_eop - c_tx_offset_sop = c_tx_period_sop - 1;
constant c_bsn_offset : natural := 1;
@@ -189,8 +200,10 @@ begin
------------------------------------------------------------------------------
-- map sl, slv to record
- in_ready <= in_siso.ready; -- SISO
- in_sosi.data(c_dp_data_w - 1 downto 0) <= in_data; -- SOSI
+ -- SISO
+ in_ready <= in_siso.ready;
+ -- SOSI
+ in_sosi.data(c_dp_data_w - 1 downto 0) <= in_data;
in_sosi.bsn(c_dp_bsn_w - 1 downto 0) <= in_bsn(c_dp_bsn_w - 1 downto 0);
in_sosi.empty <= in_empty(c_dp_empty_w - 1 downto 0);
in_sosi.channel <= in_channel(c_dp_channel_w - 1 downto 0);
@@ -199,9 +212,11 @@ begin
in_sosi.sop <= in_sop;
in_sosi.eop <= in_eop;
- out_siso.ready <= out_ready; -- SISO
+ -- SISO
+ out_siso.ready <= out_ready;
out_siso.xon <= '1';
- out_data <= out_sosi.data(c_dp_data_w - 1 downto 0); -- SOSI
+ -- SOSI
+ out_data <= out_sosi.data(c_dp_data_w - 1 downto 0);
out_bsn(c_dp_bsn_w - 1 downto 0) <= out_sosi.bsn(c_dp_bsn_w - 1 downto 0);
out_empty(c_dp_empty_w - 1 downto 0) <= out_sosi.empty;
out_channel(c_dp_channel_w - 1 downto 0) <= out_sosi.channel;
@@ -230,9 +245,11 @@ begin
rst => rst,
clk => clk,
wr_ful => wr_ful,
- snk_out => in_siso, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out => in_siso,
snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => out_siso,
src_out => out_sosi
);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
index aeceefb25f8bc843758debbb6a078bbd2bd24980..0ab703c1760078065448346b9c6c729db02daffa 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
@@ -52,10 +52,13 @@ entity tb_dp_fifo_fill_eop is
g_dut_use_empty : boolean := false;
g_dut_use_channel : boolean := false;
g_dut_use_sync : boolean := false;
- g_dut_fifo_rl : natural := 1; -- internal RL, use 0 for look ahead FIFO, default 1 for normal FIFO
+ -- internal RL, use 0 for look ahead FIFO, default 1 for normal FIFO
+ g_dut_fifo_rl : natural := 1;
g_dut_fifo_size : natural := 128;
- g_dut_fifo_fill : natural := 100; -- selectable >= 0 for dp_fifo_fill
- g_block_size : natural := 14; -- to verify g_block_size > or < g_dut_fifo_fill
+ -- selectable >= 0 for dp_fifo_fill
+ g_dut_fifo_fill : natural := 100;
+ -- to verify g_block_size > or < g_dut_fifo_fill
+ g_block_size : natural := 14;
g_dut_use_rd_fill_32b : boolean := false;
g_dut_use_gap : boolean := false;
g_dut_use_random_ctrl : boolean := false
@@ -66,23 +69,33 @@ architecture tb of tb_dp_fifo_fill_eop is
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT
- constant c_dut_in_latency : natural := 1; -- fixed for dp_fifo_fill
- constant c_dut_out_latency : natural := 1; -- fixed for dp_fifo_fill, only internally dp_fifo_fill may use RL=0 or 1 dependent on g_dut_fifo_rl
+ -- fixed for dp_fifo_fill
+ constant c_dut_in_latency : natural := 1;
+ -- fixed for dp_fifo_fill, only internally dp_fifo_fill may use RL=0 or 1 dependent on g_dut_fifo_rl
+ constant c_dut_out_latency : natural := 1;
constant c_dut_fifo_af_margin : natural := 4;
-- Stimuli
- constant c_tx_latency : natural := c_dut_in_latency; -- TX ready latency of TB
- constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ -- TX ready latency of TB
+ constant c_tx_latency : natural := c_dut_in_latency;
+ -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0);
constant c_tx_offset_sop : natural := 3;
- constant c_tx_period_sop : natural := g_block_size; -- sop in data valid cycle 3, 17, 31, ...
- constant c_tx_offset_eop : natural := sel_a_b(g_dut_use_gap, 12, 16); -- eop in data valid cycle 12, 26, 40, ...
+ -- sop in data valid cycle 3, 17, 31, ...
+ constant c_tx_period_sop : natural := g_block_size;
+ -- eop in data valid cycle 12, 26, 40, ...
+ constant c_tx_offset_eop : natural := sel_a_b(g_dut_use_gap, 12, 16);
constant c_tx_period_eop : natural := c_tx_period_sop;
- constant c_tx_offset_sync : natural := 3; -- sync in data valid cycle 3, 20, 37, ...
+ -- sync in data valid cycle 3, 20, 37, ...
+ constant c_tx_offset_sync : natural := 3;
constant c_tx_period_sync : natural := 17;
- constant c_tx_offset_gap : natural := 5; -- gap in data valid cycle 5, 19, 33, ...
+ -- gap in data valid cycle 5, 19, 33, ...
+ constant c_tx_offset_gap : natural := 5;
constant c_tx_period_gap : natural := c_tx_period_sop;
- constant c_rx_latency : natural := c_dut_out_latency; -- RX ready latency from DUT
- constant c_verify_en_wait : natural := 20 + g_dut_fifo_fill; -- wait some cycles before asserting verify enable
+ -- RX ready latency from DUT
+ constant c_rx_latency : natural := c_dut_out_latency;
+ -- wait some cycles before asserting verify enable
+ constant c_verify_en_wait : natural := 20 + g_dut_fifo_fill;
constant c_verify_data_en : boolean := c_tx_offset_eop - c_tx_offset_sop = c_tx_period_sop - 1;
constant c_bsn_offset : natural := 1;
@@ -100,7 +113,8 @@ architecture tb of tb_dp_fifo_fill_eop is
signal cnt_dat : std_logic_vector(c_dp_data_w - 1 downto 0);
signal cnt_val : std_logic;
- signal cnt_en : std_logic := '1'; -- default always active input control.
+ -- default always active input control.
+ signal cnt_en : std_logic := '1';
signal tx_data : t_dp_data_arr(0 to c_tx_latency + c_tx_void) := (others => (others => '0'));
signal tx_val : std_logic_vector(0 to c_tx_latency + c_tx_void) := (others => '0');
@@ -124,7 +138,8 @@ architecture tb of tb_dp_fifo_fill_eop is
signal out_siso : t_dp_siso;
signal out_sosi : t_dp_sosi;
- signal out_ready : std_logic := '1'; -- default always active output flow control.
+ -- default always active output flow control.
+ signal out_ready : std_logic := '1';
signal prev_out_ready : std_logic_vector(0 to c_rx_latency);
signal out_data : std_logic_vector(c_dp_data_w - 1 downto 0);
signal out_bsn : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
@@ -245,8 +260,10 @@ begin
------------------------------------------------------------------------------
-- map sl, slv to record
- in_ready <= in_siso.ready; -- SISO
- in_sosi.data(c_dp_data_w - 1 downto 0) <= in_data; -- SOSI
+ -- SISO
+ in_ready <= in_siso.ready;
+ -- SOSI
+ in_sosi.data(c_dp_data_w - 1 downto 0) <= in_data;
in_sosi.bsn(c_dp_bsn_w - 1 downto 0) <= in_bsn(c_dp_bsn_w - 1 downto 0);
in_sosi.empty <= in_empty(c_dp_empty_w - 1 downto 0);
in_sosi.channel <= in_channel(c_dp_channel_w - 1 downto 0);
@@ -255,9 +272,11 @@ begin
in_sosi.sop <= in_en and in_sop;
in_sosi.eop <= in_en and in_eop;
- out_siso.ready <= out_ready; -- SISO
+ -- SISO
+ out_siso.ready <= out_ready;
out_siso.xon <= '1';
- out_data <= out_sosi.data(c_dp_data_w - 1 downto 0); -- SOSI
+ -- SOSI
+ out_data <= out_sosi.data(c_dp_data_w - 1 downto 0);
out_bsn(c_dp_bsn_w - 1 downto 0) <= out_sosi.bsn(c_dp_bsn_w - 1 downto 0);
out_empty(c_dp_empty_w - 1 downto 0) <= out_sosi.empty;
out_channel(c_dp_channel_w - 1 downto 0) <= out_sosi.channel;
@@ -291,9 +310,11 @@ begin
wr_ful => wr_ful,
rd_usedw => rd_usedw,
rd_fill_32b => rd_fill_32b,
- snk_out => in_siso, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out => in_siso,
snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => out_siso,
src_out => out_sosi
);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
index bd1ccdaaa0c07ae157a96cc4a067bcf8cd611fcb..60e9e72714d034d525124327fea9ddc7124bced6 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
@@ -49,9 +49,11 @@ entity tb_dp_fifo_fill_sc is
g_dut_use_empty : boolean := false;
g_dut_use_channel : boolean := false;
g_dut_use_sync : boolean := false;
- g_dut_fifo_rl : natural := 1; -- internal RL, use 0 for look ahead FIFO, default 1 for normal FIFO
+ -- internal RL, use 0 for look ahead FIFO, default 1 for normal FIFO
+ g_dut_fifo_rl : natural := 1;
g_dut_fifo_size : natural := 64;
- g_dut_fifo_fill : natural := 64; -- selectable >= 0 for dp_fifo_fill
+ -- selectable >= 0 for dp_fifo_fill
+ g_dut_fifo_fill : natural := 64;
g_dut_use_rd_fill_32b : boolean := true
);
end tb_dp_fifo_fill_sc;
@@ -60,21 +62,30 @@ architecture tb of tb_dp_fifo_fill_sc is
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT
- constant c_dut_in_latency : natural := 1; -- fixed for dp_fifo_fill
- constant c_dut_out_latency : natural := 1; -- fixed for dp_fifo_fill, only internally dp_fifo_fill may use RL=0 or 1 dependent on g_dut_fifo_rl
+ -- fixed for dp_fifo_fill
+ constant c_dut_in_latency : natural := 1;
+ -- fixed for dp_fifo_fill, only internally dp_fifo_fill may use RL=0 or 1 dependent on g_dut_fifo_rl
+ constant c_dut_out_latency : natural := 1;
constant c_dut_fifo_af_margin : natural := 4;
-- Stimuli
- constant c_tx_latency : natural := c_dut_in_latency; -- TX ready latency of TB
- constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ -- TX ready latency of TB
+ constant c_tx_latency : natural := c_dut_in_latency;
+ -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0);
constant c_tx_offset_sop : natural := 3;
- constant c_tx_period_sop : natural := 7; -- sop in data valid cycle 3, 10, 17, ...
- constant c_tx_offset_eop : natural := 9; -- eop in data valid cycle 9, 16, 23, ...
+ -- sop in data valid cycle 3, 10, 17, ...
+ constant c_tx_period_sop : natural := 7;
+ -- eop in data valid cycle 9, 16, 23, ...
+ constant c_tx_offset_eop : natural := 9;
constant c_tx_period_eop : natural := c_tx_period_sop;
- constant c_tx_offset_sync : natural := 3; -- sync in data valid cycle 3, 20, 37, ...
+ -- sync in data valid cycle 3, 20, 37, ...
+ constant c_tx_offset_sync : natural := 3;
constant c_tx_period_sync : natural := 17;
- constant c_rx_latency : natural := c_dut_out_latency; -- RX ready latency from DUT
- constant c_verify_en_wait : natural := 20 + g_dut_fifo_fill; -- wait some cycles before asserting verify enable
+ -- RX ready latency from DUT
+ constant c_rx_latency : natural := c_dut_out_latency;
+ -- wait some cycles before asserting verify enable
+ constant c_verify_en_wait : natural := 20 + g_dut_fifo_fill;
constant c_verify_data_en : boolean := c_tx_offset_eop - c_tx_offset_sop = c_tx_period_sop - 1;
constant c_bsn_offset : natural := 1;
@@ -219,8 +230,10 @@ begin
------------------------------------------------------------------------------
-- map sl, slv to record
- in_ready <= in_siso.ready; -- SISO
- in_sosi.data(c_dp_data_w - 1 downto 0) <= in_data; -- SOSI
+ -- SISO
+ in_ready <= in_siso.ready;
+ -- SOSI
+ in_sosi.data(c_dp_data_w - 1 downto 0) <= in_data;
in_sosi.bsn(c_dp_bsn_w - 1 downto 0) <= in_bsn(c_dp_bsn_w - 1 downto 0);
in_sosi.empty <= in_empty(c_dp_empty_w - 1 downto 0);
in_sosi.channel <= in_channel(c_dp_channel_w - 1 downto 0);
@@ -229,9 +242,11 @@ begin
in_sosi.sop <= in_sop;
in_sosi.eop <= in_eop;
- out_siso.ready <= out_ready; -- SISO
+ -- SISO
+ out_siso.ready <= out_ready;
out_siso.xon <= '1';
- out_data <= out_sosi.data(c_dp_data_w - 1 downto 0); -- SOSI
+ -- SOSI
+ out_data <= out_sosi.data(c_dp_data_w - 1 downto 0);
out_bsn(c_dp_bsn_w - 1 downto 0) <= out_sosi.bsn(c_dp_bsn_w - 1 downto 0);
out_empty(c_dp_empty_w - 1 downto 0) <= out_sosi.empty;
out_channel(c_dp_channel_w - 1 downto 0) <= out_sosi.channel;
@@ -262,9 +277,11 @@ begin
wr_ful => wr_ful,
usedw => rd_usedw,
rd_fill_32b => rd_fill_32b,
- snk_out => in_siso, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out => in_siso,
snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => out_siso,
src_out => out_sosi
);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
index aea359818b59eaab5fd1f1bcd8211b06d3c54fd4..0666fac63c8302b7dc403f8050705fea67556edc 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
@@ -43,15 +43,18 @@ use work.tb_dp_pkg.all;
entity tb_dp_fifo_info is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse;
+ -- always active, random or pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_pulse;
-- specific
g_info_use_sync : boolean := true;
g_info_use_bsn : boolean := true;
g_info_use_channel : boolean := true;
g_info_use_empty : boolean := true;
g_info_use_error : boolean := true;
- g_info_fifo_size : natural := 8; -- >= ceil_div(g_data_delay, g_data_block_len)
+ -- >= ceil_div(g_data_delay, g_data_block_len)
+ g_info_fifo_size : natural := 8;
g_nof_data_block : natural := 25;
g_data_block_len : natural := 10;
g_data_delay : natural := 35
@@ -59,12 +62,14 @@ entity tb_dp_fifo_info is
end tb_dp_fifo_info;
architecture tb of tb_dp_fifo_info is
- constant c_rl : natural := 1; -- fixed
+ -- fixed
+ constant c_rl : natural := 1;
constant c_data_w : natural := 16;
constant c_data_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
constant c_data_init : integer := -1;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
constant c_channel_init : integer := 5;
@@ -78,8 +83,10 @@ architecture tb of tb_dp_fifo_info is
signal rst : std_logic := '1';
signal sl1 : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -91,7 +98,8 @@ architecture tb of tb_dp_fifo_info is
signal dp_pipeline_src_in : t_dp_siso;
signal dp_pipeline_src_out : t_dp_sosi;
- signal fifo_wr_ful : std_logic; -- corresponds to the carry bit of usedw when FIFO is full
+ -- corresponds to the carry bit of usedw when FIFO is full
+ signal fifo_wr_ful : std_logic;
signal fifo_usedw : std_logic_vector(ceil_log2(g_info_fifo_size) - 1 downto 0);
signal fifo_rd_emp : std_logic;
@@ -159,10 +167,12 @@ begin
for I in 0 to g_nof_data_block - 1 loop
-- Auto increment v_sosi field values for this packet
v_sosi.bsn := INCR_UVEC(v_sosi.bsn, 1);
- v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_sync_period) = c_sync_offset, '1', '0'); -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_sync_period) = c_sync_offset, '1', '0');
v_sosi.channel := INCR_UVEC(v_sosi.channel, 1);
v_sosi.data := INCR_UVEC(v_sosi.data, g_data_block_len);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(c_data_w - 1 downto 0)); -- wrap when >= 2**c_data_w
+ -- wrap when >= 2**c_data_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(c_data_w - 1 downto 0));
v_sosi.err := INCR_UVEC(v_sosi.err, 1);
-- Send packet
@@ -175,11 +185,13 @@ begin
v_sosi.err := TO_DP_ERROR(c_err_init + g_nof_data_block - 1);
-- . account for g_data_block_len
v_sosi.data := INCR_UVEC(v_sosi.data, g_data_block_len - 1);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(c_data_w - 1 downto 0)); -- wrap when >= 2**c_data_w
+ -- wrap when >= 2**c_data_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(c_data_w - 1 downto 0));
expected_verify_snk_in <= v_sosi;
-- Signal end of stimuli
- proc_common_wait_some_cycles(clk, 500); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ proc_common_wait_some_cycles(clk, 500);
proc_common_gen_pulse(clk, verify_done);
proc_common_wait_some_cycles(clk, 50);
tb_end <= '1';
@@ -227,8 +239,10 @@ begin
fifo_rd_emp => fifo_rd_emp,
-- ST sink
data_snk_out => dp_pipeline_src_in,
- data_snk_in => dp_pipeline_src_out, -- delayed snk_in data
- info_snk_in => stimuli_src_out, -- original snk_in info
+ -- delayed snk_in data
+ data_snk_in => dp_pipeline_src_out,
+ -- original snk_in info
+ info_snk_in => stimuli_src_out,
-- ST source
src_in => verify_snk_out,
src_out => verify_snk_in
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
index 0597d8e0dc06249db6a37dd459e363922ab17a03..83251e1495911a3d6a70f13491edf8d9708e1b5b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
@@ -30,15 +30,18 @@ use work.tb_dp_pkg.all;
entity tb_dp_fifo_sc is
generic (
-- Try FIFO settings
- g_dut_use_lut : boolean := false; -- when TRUE then force using LUTs instead of block RAM
+ -- when TRUE then force using LUTs instead of block RAM
+ g_dut_use_lut : boolean := false;
g_dut_fifo_size : natural := 64;
- g_dut_fifo_af_margin : natural := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
+ -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_dut_fifo_af_margin : natural := 4;
g_dut_use_bsn : boolean := true;
g_dut_use_empty : boolean := true;
g_dut_use_channel : boolean := true;
g_dut_use_sync : boolean := true;
g_dut_use_ctrl : boolean := true;
- g_dut_out_latency : natural := 0 -- selectable for dp_fifo_sc: default 1 or 0 for look ahead FIFO
+ -- selectable for dp_fifo_sc: default 1 or 0 for look ahead FIFO
+ g_dut_out_latency : natural := 0
);
end tb_dp_fifo_sc;
@@ -46,19 +49,27 @@ architecture tb of tb_dp_fifo_sc is
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT
- constant c_dut_in_latency : natural := 1; -- fixed for dp_fifo_sc
+ -- fixed for dp_fifo_sc
+ constant c_dut_in_latency : natural := 1;
-- Stimuli
- constant c_tx_latency : natural := c_dut_in_latency; -- TX ready latency of TB
- constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ -- TX ready latency of TB
+ constant c_tx_latency : natural := c_dut_in_latency;
+ -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0);
constant c_tx_offset_sop : natural := 3;
- constant c_tx_period_sop : natural := 7; -- sop in data valid cycle 3, 10, 17, ...
- constant c_tx_offset_eop : natural := 5; -- eop in data valid cycle 5, 12, 19, ...
+ -- sop in data valid cycle 3, 10, 17, ...
+ constant c_tx_period_sop : natural := 7;
+ -- eop in data valid cycle 5, 12, 19, ...
+ constant c_tx_offset_eop : natural := 5;
constant c_tx_period_eop : natural := c_tx_period_sop;
- constant c_tx_offset_sync : natural := 3; -- sync in data valid cycle 3, 20, 37, ...
+ -- sync in data valid cycle 3, 20, 37, ...
+ constant c_tx_offset_sync : natural := 3;
constant c_tx_period_sync : natural := 17;
- constant c_rx_latency : natural := g_dut_out_latency; -- RX ready latency from DUT
- constant c_verify_en_wait : natural := 5; -- wait some cycles before asserting verify enable
+ -- RX ready latency from DUT
+ constant c_rx_latency : natural := g_dut_out_latency;
+ -- wait some cycles before asserting verify enable
+ constant c_verify_en_wait : natural := 5;
constant c_bsn_offset : natural := 1;
constant c_empty_offset : natural := 2;
@@ -173,8 +184,10 @@ begin
------------------------------------------------------------------------------
-- map sl, slv to record
- in_ready <= in_siso.ready; -- SISO
- in_sosi.data(c_dp_data_w - 1 downto 0) <= in_data; -- SOSI
+ -- SISO
+ in_ready <= in_siso.ready;
+ -- SOSI
+ in_sosi.data(c_dp_data_w - 1 downto 0) <= in_data;
in_sosi.bsn(c_dp_bsn_w - 1 downto 0) <= in_bsn;
in_sosi.empty <= in_empty(c_dp_empty_w - 1 downto 0);
in_sosi.channel <= in_channel(c_dp_channel_w - 1 downto 0);
@@ -183,8 +196,10 @@ begin
in_sosi.sop <= in_sop;
in_sosi.eop <= in_eop;
- out_siso.ready <= out_ready; -- SISO
- out_data <= out_sosi.data(c_dp_data_w - 1 downto 0); -- SOSI
+ -- SISO
+ out_siso.ready <= out_ready;
+ -- SOSI
+ out_data <= out_sosi.data(c_dp_data_w - 1 downto 0);
out_bsn(c_dp_bsn_w - 1 downto 0) <= out_sosi.bsn(c_dp_bsn_w - 1 downto 0);
out_empty(c_dp_empty_w - 1 downto 0) <= out_sosi.empty;
out_channel(c_dp_channel_w - 1 downto 0) <= out_sosi.channel;
@@ -214,10 +229,12 @@ begin
port map (
rst => rst,
clk => clk,
- snk_out => in_siso, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out => in_siso,
snk_in => in_sosi,
usedw => usedw,
- src_in => out_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => out_siso,
src_out => out_sosi
);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
index 141127e58cb195aa67381dc8d13cf96e47d40e12..c26d6be75fe7b5156179fb564e1a4394c01a5195 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
@@ -57,13 +57,16 @@ architecture tb of tb_dp_fifo_to_mm is
constant c_run_time : natural := 9000;
- constant c_rl : natural := 1; -- Fixed RL = 1
+ -- Fixed RL = 1
+ constant c_rl : natural := 1;
constant c_fifo_size : natural := 32;
constant c_fifo_usedw_w : natural := ceil_log2(c_fifo_size);
- constant c_fifo_af_margin : natural := 1; -- >= 1
+ -- >= 1
+ constant c_fifo_af_margin : natural := 1;
- constant c_mm_data_w : natural := 16; -- must be >= c_fifo_usedw_w
+ -- must be >= c_fifo_usedw_w
+ constant c_mm_data_w : natural := 16;
type t_state is (s_idle, s_one_go, s_random);
@@ -71,7 +74,8 @@ architecture tb of tb_dp_fifo_to_mm is
signal rst : std_logic;
signal clk : std_logic := '1';
- signal random_wr : std_logic_vector(c_fifo_usedw_w downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_wr : std_logic_vector(c_fifo_usedw_w downto 0) := (others => '0');
signal random_rd : std_logic_vector(c_fifo_usedw_w + 1 downto 0) := (others => '0');
-- DUT
@@ -132,7 +136,8 @@ begin
mm_wr <= '0';
case state_wr is
when s_idle =>
- v_burst := TO_UINT(random_wr(c_fifo_usedw_w - 1 downto 0)); -- no write for random nof cycles < g_fifo_size
+ -- no write for random nof cycles < g_fifo_size
+ v_burst := TO_UINT(random_wr(c_fifo_usedw_w - 1 downto 0));
if unsigned(wr_availw) < c_fifo_size / 4 then
state_wr <= s_one_go;
else
@@ -142,19 +147,22 @@ begin
when s_one_go =>
if unsigned(wr_availw) > 0 then
mm_wr <= '1';
- v_burst := TO_UINT(wr_availw); -- use wr_availw to try to fill the FIFO in one go
+ -- use wr_availw to try to fill the FIFO in one go
+ v_burst := TO_UINT(wr_availw);
end if;
state_wr <= s_idle;
when s_random =>
if unsigned(wr_availw) > 0 then
mm_wr <= '1';
- v_burst := (TO_UINT(wr_availw) * TO_UINT(random_wr)) / 2**random_wr'length; -- determine a random write burst size < wr_availw to fill part of the FIFO
+ -- determine a random write burst size < wr_availw to fill part of the FIFO
+ v_burst := (TO_UINT(wr_availw) * TO_UINT(random_wr)) / 2**random_wr'length;
end if;
state_wr <= s_idle;
end case;
if v_burst = 0 then v_burst := 1; end if;
burst_wr <= v_burst;
- proc_common_wait_some_cycles(clk, v_burst); -- clock the burst size
+ -- clock the burst size
+ proc_common_wait_some_cycles(clk, v_burst);
end loop;
end process;
@@ -170,7 +178,8 @@ begin
mm_rd <= '0';
case state_rd is
when s_idle =>
- v_burst := TO_UINT(random_rd(c_fifo_usedw_w - 1 downto 0)); -- no read for random nof cycles < g_fifo_size
+ -- no read for random nof cycles < g_fifo_size
+ v_burst := TO_UINT(random_rd(c_fifo_usedw_w - 1 downto 0));
if unsigned(rd_usedw) < c_fifo_size / 4 then
state_rd <= s_one_go;
else
@@ -180,19 +189,22 @@ begin
when s_one_go =>
if unsigned(rd_usedw) > 0 then
mm_rd <= '1';
- v_burst := TO_UINT(rd_usedw); -- use rd_usedw to try to empty the FIFO in one go
+ -- use rd_usedw to try to empty the FIFO in one go
+ v_burst := TO_UINT(rd_usedw);
end if;
state_rd <= s_idle;
when s_random =>
if unsigned(rd_usedw) > 0 then
mm_rd <= '1';
- v_burst := (TO_UINT(rd_usedw) * TO_UINT(random_rd)) / 2**random_rd'length; -- determine a random read burst size < rd_usedw to empty part of the FIFO
+ -- determine a random read burst size < rd_usedw to empty part of the FIFO
+ v_burst := (TO_UINT(rd_usedw) * TO_UINT(random_rd)) / 2**random_rd'length;
end if;
state_rd <= s_idle;
end case;
if v_burst = 0 then v_burst := 1; end if;
burst_rd <= v_burst;
- proc_common_wait_some_cycles(clk, v_burst); -- clock the burst size
+ -- clock the burst size
+ proc_common_wait_some_cycles(clk, v_burst);
end loop;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd
index 2c7c60352a14a2f1c1517802ef2d84570db53a80..8eca6a2d4f7ab07380c39bdc33007defca5a2d22 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd
@@ -170,7 +170,8 @@ begin
c_symbol_w,
c_symbol_init,
c_nof_symbols,
- c_bsn + I, -- use bsn to identify the inputs
+ -- use bsn to identify the inputs
+ c_bsn + I,
c_sync,
clk,
in_en,
@@ -207,8 +208,10 @@ begin
generic map (
g_data_w => c_data_w,
g_bsn_w => c_nof_input_w,
- g_use_bsn => true, -- use bsn to identify the inputs
- g_use_ctrl => true, -- sop & eop
+ -- use bsn to identify the inputs
+ g_use_bsn => true,
+ -- sop & eop
+ g_use_ctrl => true,
g_fifo_size => c_in_fifo_size,
g_fifo_af_margin => c_fifo_af_ready,
g_fifo_af_xon => c_fifo_af_xon,
@@ -222,7 +225,8 @@ begin
usedw => in_fifo_usedw_arr(I),
rd_emp => in_fifo_rd_emp_arr(I),
-- ST sink
- snk_out => fifo_in_siso_arr(I), -- flush control via out_siso.xon
+ -- flush control via out_siso.xon
+ snk_out => fifo_in_siso_arr(I),
snk_in => fifo_in_sosi_arr(I),
-- ST source
src_in => mux_in_siso_arr(I),
@@ -248,8 +252,10 @@ begin
u_dp_mux : entity work.dp_mux
generic map (
g_nof_input => g_nof_inputs,
- g_fifo_size => array_init(1024, g_nof_inputs), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, g_nof_inputs) -- must match g_nof_input, even when g_use_fifo=FALSE
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_size => array_init(1024, g_nof_inputs),
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, g_nof_inputs)
)
port map (
rst => rst,
@@ -292,7 +298,8 @@ begin
generic map (
g_data_w => c_data_w,
g_bsn_w => c_nof_input_w,
- g_use_bsn => true, -- use bsn to identify the inputs
+ -- use bsn to identify the inputs
+ g_use_bsn => true,
g_fifo_fill => c_out_fifo_fill,
g_fifo_size => c_out_fifo_size,
g_fifo_af_margin => c_fifo_af_ready,
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd b/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
index bb5e1dce668631c35da92367a168cdf38465c06b..ffcb519dacab08f0e9616c2da580793cff30f68e 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
@@ -39,11 +39,14 @@ use dp_lib.tb_dp_pkg.all;
entity tb_dp_flush is
generic (
- g_rl : natural := 0; -- this tb supports ready latency is 0 or 1
+ -- this tb supports ready latency is 0 or 1
+ g_rl : natural := 0;
g_framed_xon : boolean := true;
g_framed_xoff : boolean := true;
- g_in_en : t_dp_flow_control_enum := e_random; -- always e_active, e_random or e_pulse flow control
- g_out_ready : t_dp_flow_control_enum := e_random; -- always e_active, e_random or e_pulse flow control
+ -- always e_active, e_random or e_pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_random;
+ -- always e_active, e_random or e_pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_random;
g_nof_repeat : natural := 100
);
end tb_dp_flush;
@@ -58,8 +61,10 @@ architecture tb of tb_dp_flush is
signal clk : std_logic := '1';
signal rst : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -127,7 +132,8 @@ begin
random_1(random_1'high) when g_out_ready = e_random else
pulse_1 when g_out_ready = e_pulse;
- out_siso.ready <= out_ready when g_rl /= 0 else out_ready and out_sosi.valid; -- request for RL > 0, acknowledge for RL = 0
+ -- request for RL > 0, acknowledge for RL = 0
+ out_siso.ready <= out_ready when g_rl /= 0 else out_ready and out_sosi.valid;
------------------------------------------------------------------------------
-- DATA GENERATION
@@ -155,7 +161,8 @@ begin
while true loop
-- No gaps between the blocks
proc_dp_gen_block_data(g_rl, true, c_data_w, c_data_w, v_data, 0, 0, c_block_size, c_channel_init, c_err_init, v_sync, v_bsn, clk, in_en, in_siso, in_sosi);
- v_sync := sel_a_b(unsigned(v_bsn(c_sync_period_w - 1 downto 0)) = c_sync_bsn - 1, '1', '0'); -- sync pulse every at 2**c_sync_period_w block
+ -- sync pulse every at 2**c_sync_period_w block
+ v_sync := sel_a_b(unsigned(v_bsn(c_sync_period_w - 1 downto 0)) = c_sync_bsn - 1, '1', '0');
v_bsn := INCR_UVEC(v_bsn, 1);
v_data := v_data + c_block_size;
end loop;
@@ -172,11 +179,15 @@ begin
for I in 1 to g_nof_repeat loop
flush_en <= '1';
- proc_common_wait_some_cycles(clk, 1); -- at least one cycle
- proc_common_wait_some_cycles(clk, TO_UINT(random_0(c_flush_en_w - 1 downto 0))); -- random nof cycles
+ -- at least one cycle
+ proc_common_wait_some_cycles(clk, 1);
+ -- random nof cycles
+ proc_common_wait_some_cycles(clk, TO_UINT(random_0(c_flush_en_w - 1 downto 0)));
flush_en <= '0';
- proc_common_wait_some_cycles(clk, 1); -- at least one cycle
- proc_common_wait_some_cycles(clk, TO_UINT(random_1(c_flush_en_w - 1 downto 0))); -- random nof cycles
+ -- at least one cycle
+ proc_common_wait_some_cycles(clk, 1);
+ -- random nof cycles
+ proc_common_wait_some_cycles(clk, TO_UINT(random_1(c_flush_en_w - 1 downto 0)));
end loop;
proc_common_wait_some_cycles(clk, 100);
tb_end <= '1';
@@ -189,7 +200,8 @@ begin
-- These flush_en mode signals suit both g_rl=0 and g_rl>0
-- Use registered signals to avoid issues with different delta-cycle delays between both actors in_sosi.sop and flush_en_dly
reg_mode_flush_en_streaming <= '1' when rising_edge(clk) and flush_en_dly(0) = '1' else
- '0' when rising_edge(clk) and flush_en_dly(g_rl) = '0'; -- equivalent to: reg_mode_flush_en_streaming <= vector_or(flush_en_dly);
+ -- equivalent to: reg_mode_flush_en_streaming <= vector_or(flush_en_dly);
+ '0' when rising_edge(clk) and flush_en_dly(g_rl) = '0';
reg_mode_flush_en_framed <= '1' when rising_edge(clk) and in_sosi.sop = '1' and flush_en_dly(0) = '1' else
'0' when rising_edge(clk) and in_sosi.sop = '1' and flush_en_dly(g_rl) = '0';
reg_mode_flush_en_framed_xon <= '1' when rising_edge(clk) and flush_en_dly(0) = '1' else
@@ -200,7 +212,8 @@ begin
reg_mode_flush_en <= reg_mode_flush_en_streaming when g_framed_xon = false and g_framed_xoff = false else
reg_mode_flush_en_framed when g_framed_xon = true and g_framed_xoff = true else
reg_mode_flush_en_framed_xon when g_framed_xon = true and g_framed_xoff = false else
- reg_mode_flush_en_framed_xoff; -- g_framed_xon=FALSE AND g_framed_xoff=TRUE
+ -- g_framed_xon=FALSE AND g_framed_xoff=TRUE
+ reg_mode_flush_en_framed_xoff;
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -209,10 +222,12 @@ begin
verify_en <= '1';
-- Verify some general streaming interface properties
- proc_dp_verify_valid(g_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_sosi.valid); -- Verify that the out_sosi valid fits with the ready latency
+ -- Verify that the out_sosi valid fits with the ready latency
+ proc_dp_verify_valid(g_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_sosi.valid);
gen_framed : if g_framed_xon = true and g_framed_xoff = true generate
- proc_dp_verify_gap_invalid(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, m.src_out_gap); -- Verify that there is no valid data between frames, init out_gap at '1'
+ -- Verify that there is no valid data between frames, init out_gap at '1'
+ proc_dp_verify_gap_invalid(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, m.src_out_gap);
end generate;
-- Verify the flush modes
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd b/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
index 1a752aaa71ad8deac703a7c386a827a560fae434..993c3c5529535ed6b2264193c2c521d0c6209e0e 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
@@ -39,7 +39,8 @@ end tb_dp_folder;
architecture tb of tb_dp_folder is
constant c_nof_inputs : natural := 1;
- constant c_nof_unfolds : natural := 1; -- 5 folds = 1->2->4->8->16->32 unfolded streams
+ -- 5 folds = 1->2->4->8->16->32 unfolded streams
+ constant c_nof_unfolds : natural := 1;
constant c_nof_unfolded_streams : natural := c_nof_inputs * pow2(c_nof_unfolds);
constant c_data_w : natural := 32;
@@ -47,8 +48,10 @@ architecture tb of tb_dp_folder is
constant c_packet_len : natural := 20;
constant c_packet_gap : natural := 0;
- constant c_clk_period : time := 5 ns; -- 200 MHz
- constant c_mm_clk_period : time := 20 ns; -- 50 MHz
+ -- 200 MHz
+ constant c_clk_period : time := 5 ns;
+ -- 50 MHz
+ constant c_mm_clk_period : time := 20 ns;
signal clk : std_logic := '1';
signal rst : std_logic;
@@ -97,7 +100,8 @@ begin
generic map (
g_nof_inputs => c_nof_inputs,
g_nof_unfolds => c_nof_unfolds,
- g_output_align => false -- We're going to fold these outputs again, so don't align them!
+ -- We're going to fold these outputs again, so don't align them!
+ g_output_align => false
)
port map (
clk => clk,
@@ -110,7 +114,8 @@ begin
u_dp_folder : entity work.dp_folder
generic map (
g_nof_inputs => c_nof_unfolded_streams,
- g_nof_folds => -1 -- Fold until 1 output remains,
+ -- Fold until 1 output remains,
+ g_nof_folds => -1
-- g_output_block_size => c_packet_len
)
port map (
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd b/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
index 8b0d02b22bb7ea8f243399277cd8e93dda14e2a5..b037d6ba1752d8b362f1076a0c8c2c56cc21e80d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
@@ -34,7 +34,8 @@ architecture tb of tb_dp_frame_rd is
-- > as 5
-- > run 10 us, at 4335 ns expect Warning: Frame with valid data but no sof.
- constant clk_period : time := 10 ns; -- 100 MHz
+ -- 100 MHz
+ constant clk_period : time := 10 ns;
constant c_init_length : natural := 100;
constant c_empty_length : natural := 50;
@@ -45,14 +46,18 @@ architecture tb of tb_dp_frame_rd is
constant c_data_w : natural := 16;
constant c_fifo_nof_words : natural := 1024;
- constant c_fifo_dat_w : natural := 1 + 1 + c_data_w; -- = 1+1+32=34
- constant c_throttle_num : natural := 1; -- numerator <= g_throttle_den
- constant c_throttle_den : natural := 4; -- denominator (use 1 for full speed, i.e no output throttling)
+ -- = 1+1+32=34
+ constant c_fifo_dat_w : natural := 1 + 1 + c_data_w;
+ -- numerator <= g_throttle_den
+ constant c_throttle_num : natural := 1;
+ -- denominator (use 1 for full speed, i.e no output throttling)
+ constant c_throttle_den : natural := 4;
--CONSTANT c_throttle_sof : BOOLEAN := TRUE; -- when false immediately do request next data after sof
constant c_throttle_sof : boolean := false;
--CONSTANT c_throttle_eof : BOOLEAN := TRUE; -- when false immediately continue request next frame after eof
constant c_throttle_eof : boolean := false;
- constant c_frame_request : std_logic := '1'; -- when '1' then always request, else only in state s_request when not frm_ack
+ -- when '1' then always request, else only in state s_request when not frm_ack
+ constant c_frame_request : std_logic := '1';
-- use '1' to verify c_throttle_eof=FALSE
type t_state_enum is (s_request, s_eof, s_err);
@@ -187,13 +192,16 @@ begin
end process;
-- map sl, slv to record
- in_sosi.data(c_data_w - 1 downto 0) <= in_data; -- SOSI
+ -- SOSI
+ in_sosi.data(c_data_w - 1 downto 0) <= in_data;
in_sosi.valid <= in_val;
in_sosi.sop <= in_sof;
in_sosi.eop <= in_eof;
- rd_siso.ready <= fifo_rd_req; -- SISO
- fifo_rd_data <= rd_sosi.data(c_data_w - 1 downto 0); -- SOSI
+ -- SISO
+ rd_siso.ready <= fifo_rd_req;
+ -- SOSI
+ fifo_rd_data <= rd_sosi.data(c_data_w - 1 downto 0);
fifo_rd_val <= rd_sosi.valid;
fifo_rd_sof <= rd_sosi.sop;
fifo_rd_eof <= rd_sosi.eop;
@@ -214,10 +222,12 @@ begin
port map (
rst => rst,
clk => clk,
- snk_out => OPEN, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out => OPEN,
snk_in => in_sosi,
usedw => fifo_usedw,
- src_in => rd_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => rd_siso,
src_out => rd_sosi
);
@@ -270,17 +280,21 @@ begin
if frm_ack = '0' then
frm_req <= '1';
elsif frm_err = '1' then
- state <= s_err; -- frame with valid data but no sof
+ -- frame with valid data but no sof
+ state <= s_err;
elsif frm_busy = '1' then
- state <= s_eof; -- frame with sof, read rest of frame
+ -- frame with sof, read rest of frame
+ state <= s_eof;
else
- state <= s_request; -- no frame, request again
+ -- no frame, request again
+ state <= s_request;
end if;
when s_eof =>
if frm_done = '1' then
state <= s_request;
end if;
- when others => -- s_err
+ -- s_err
+ when others =>
report "Frame with valid data but no sof" severity WARNING;
state <= s_request;
end case;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
index 3030dbaa28114bd9073add030febfc9be0e991fc..51cccdc5f9acc0e7e7c3e29feae3f2461ea9322a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
@@ -29,8 +29,10 @@ use work.dp_packetizing_pkg.all;
entity tb_dp_frame_scheduler is
generic (
- g_dut_verify_mux : boolean := true; -- when FALSE verify dp_frame_scheduler else verify dp_mux
- g_dut_fifo_rl : natural := 0 -- setting for dp_fifo_fill in dp_frame_scheduler, fixed 1 for dp_mux via c_dut_fifo_rl
+ -- when FALSE verify dp_frame_scheduler else verify dp_mux
+ g_dut_verify_mux : boolean := true;
+ -- setting for dp_fifo_fill in dp_frame_scheduler, fixed 1 for dp_mux via c_dut_fifo_rl
+ g_dut_fifo_rl : natural := 0
);
end tb_dp_frame_scheduler;
@@ -41,32 +43,47 @@ architecture tb of tb_dp_frame_scheduler is
constant c_rst_delay : natural := 4;
constant c_dut_delay : natural := 11;
- constant c_dut_fifo_rl : natural := sel_a_b(g_dut_verify_mux, 1, g_dut_fifo_rl); -- fixed for dp_mux
+ -- fixed for dp_mux
+ constant c_dut_fifo_rl : natural := sel_a_b(g_dut_verify_mux, 1, g_dut_fifo_rl);
- constant c_nof_input : natural := 2; -- two input streams, crosslets (x) and beamlets (b)
+ -- two input streams, crosslets (x) and beamlets (b)
+ constant c_nof_input : natural := 2;
constant c_nof_input_w : natural := ceil_log2(c_nof_input);
- constant c_packet_size_x : natural := 147; -- 3/2 * 96 dual pol antennes * 4 word/let / 4 lanes + 3 header
- constant c_packet_size_b : natural := 375; -- 3/2 * 248 beamlets * 4 word/let / 4 lanes + 3 header
+ -- 3/2 * 96 dual pol antennes * 4 word/let / 4 lanes + 3 header
+ constant c_packet_size_x : natural := 147;
+ -- 3/2 * 248 beamlets * 4 word/let / 4 lanes + 3 header
+ constant c_packet_size_b : natural := 375;
constant c_slice_size : natural := 1024;
constant c_idle_size_x : natural := c_slice_size - c_packet_size_x;
constant c_idle_size_b : natural := c_slice_size - c_packet_size_b;
- constant c_sfd_x : std_logic_vector(c_dp_max_w - 1 downto 0) := "0101010101010101010101010101010101010101010101010101010101010100"; -- 0x..5554;
- constant c_sfd_b : std_logic_vector(c_dp_max_w - 1 downto 0) := "0101010101010101010101010101010101010101010101010101010101010011"; -- 0x..5553;
-
- constant c_fsn_x : natural := 16#C000#; -- Crosslet packet
- constant c_fsn_b : natural := 16#B000#; -- Beamlet packet
- constant c_fsn_max : natural := 16#1000#; -- Reserve [15:12] for X ID or B ID
-
- constant c_burst_nof_packets : natural := 2; -- nof frames to store to handle SERDES lane bursts
- constant c_x_scheduler_size : natural := c_burst_nof_packets * c_packet_size_x; -- = 294;
- constant c_b_scheduler_size : natural := c_burst_nof_packets * c_packet_size_b; -- = 750;
- constant c_x_scheduler_fill : natural := sel_a_b(g_dut_fifo_rl, 0, 1); -- need to fill > 0 to force use of dp_fifo_fill with the RL adapter
- constant c_b_scheduler_fill : natural := sel_a_b(g_dut_fifo_rl, 0, 1); -- when fill=0 then the dp_fifo_fill used fixed RL=1
-
- constant c_lane_dat_w : natural := 16; -- = c_rsp_lane_dat_w = 16
+ -- 0x..5554;
+ constant c_sfd_x : std_logic_vector(c_dp_max_w - 1 downto 0) := "0101010101010101010101010101010101010101010101010101010101010100";
+ -- 0x..5553;
+ constant c_sfd_b : std_logic_vector(c_dp_max_w - 1 downto 0) := "0101010101010101010101010101010101010101010101010101010101010011";
+
+ -- Crosslet packet
+ constant c_fsn_x : natural := 16#C000#;
+ -- Beamlet packet
+ constant c_fsn_b : natural := 16#B000#;
+ -- Reserve [15:12] for X ID or B ID
+ constant c_fsn_max : natural := 16#1000#;
+
+ -- nof frames to store to handle SERDES lane bursts
+ constant c_burst_nof_packets : natural := 2;
+ -- = 294;
+ constant c_x_scheduler_size : natural := c_burst_nof_packets * c_packet_size_x;
+ -- = 750;
+ constant c_b_scheduler_size : natural := c_burst_nof_packets * c_packet_size_b;
+ -- need to fill > 0 to force use of dp_fifo_fill with the RL adapter
+ constant c_x_scheduler_fill : natural := sel_a_b(g_dut_fifo_rl, 0, 1);
+ -- when fill=0 then the dp_fifo_fill used fixed RL=1
+ constant c_b_scheduler_fill : natural := sel_a_b(g_dut_fifo_rl, 0, 1);
+
+ -- = c_rsp_lane_dat_w = 16
+ constant c_lane_dat_w : natural := 16;
signal rst_dut : std_logic := '1';
signal rst : std_logic := '1';
@@ -95,8 +112,10 @@ architecture tb of tb_dp_frame_scheduler is
signal lane_tx_channel : std_logic_vector(c_nof_input_w - 1 downto 0);
signal lane_tx_sosi : t_dp_sosi;
- signal fsn_x : natural := c_fsn_x; -- Init crosslet packet count with crosslet ID
- signal fsn_b : natural := c_fsn_b; -- Init beamlet packet count with beamlet ID
+ -- Init crosslet packet count with crosslet ID
+ signal fsn_x : natural := c_fsn_x;
+ -- Init beamlet packet count with beamlet ID
+ signal fsn_b : natural := c_fsn_b;
signal mark_slice_sof : std_logic := '0';
signal mark_in_sof : std_logic := '0';
@@ -157,21 +176,28 @@ architecture tb of tb_dp_frame_scheduler is
out_sof <= '1';
out_val <= '1';
out_dat <= c_dp_idle(out_dat'range);
- wait until rising_edge(clk); -- start frame with idle word
+ -- start frame with idle word
+ wait until rising_edge(clk);
out_sof <= '0';
out_dat <= c_sfd(out_dat'range);
- wait until rising_edge(clk); -- then the frame delimiter word
+ -- then the frame delimiter word
+ wait until rising_edge(clk);
out_dat <= std_logic_vector(to_unsigned(c_fsn_word, out_dat'length));
- wait until rising_edge(clk); -- then the frame sequence number
+ -- then the frame sequence number
+ wait until rising_edge(clk);
out_dat <= std_logic_vector(to_unsigned(0, out_dat'length));
- wait until rising_edge(clk); -- then the first counter data word (= 0)
+ -- then the first counter data word (= 0)
+ wait until rising_edge(clk);
for I in 4 to c_packet_size-2 loop
out_dat <= std_logic_vector(unsigned(out_dat) + 1);
- wait until rising_edge(clk); -- then loop from 4 because idle, sfd, fsn and first data word have been issued already
- end loop; -- and loop until 1 but last to be able to issue the end of frame
+ -- then loop from 4 because idle, sfd, fsn and first data word have been issued already
+ wait until rising_edge(clk);
+ -- and loop until 1 but last to be able to issue the end of frame
+ end loop;
out_eof <= '1';
out_dat <= std_logic_vector(unsigned(out_dat) + 1);
- wait until rising_edge(clk); -- end frame with last counter data word
+ -- end frame with last counter data word
+ wait until rising_edge(clk);
out_val <= '0';
out_eof <= '0';
end if;
@@ -195,7 +221,8 @@ architecture tb of tb_dp_frame_scheduler is
signal cnt : inout natural) is
begin
if rst = '0' then
- cnt <= cnt + 1; -- increment packet counter
+ -- increment packet counter
+ cnt <= cnt + 1;
if cnt = c_max - 1 then
cnt <= 0;
end if;
@@ -253,7 +280,8 @@ begin
lane_tx_xval,
lane_tx_xdat);
proc_cnt(c_fsn_max, rst, fsn_x);
- proc_idle(c_idle_size_x - 1, -- min 1 to tx one cycle earlier in every slice
+ -- min 1 to tx one cycle earlier in every slice
+ proc_idle(c_idle_size_x - 1,
rst,
clk);
end process;
@@ -271,7 +299,8 @@ begin
lane_tx_bval,
lane_tx_bdat);
proc_cnt(c_fsn_max, rst, fsn_b);
- proc_idle(c_idle_size_b, -- tx at start of every slice
+ -- tx at start of every slice
+ proc_idle(c_idle_size_b,
rst,
clk);
end process;
@@ -291,8 +320,10 @@ begin
g_dat_w => c_lane_dat_w,
g_nof_input => c_nof_input,
g_fifo_rl => c_dut_fifo_rl,
- g_fifo_size => (c_x_scheduler_size, c_b_scheduler_size), -- 1 DOWNTO 0
- g_fifo_fill => (c_x_scheduler_fill, c_b_scheduler_fill) -- 1 DOWNTO 0
+ -- 1 DOWNTO 0
+ g_fifo_size => (c_x_scheduler_size, c_b_scheduler_size),
+ -- 1 DOWNTO 0
+ g_fifo_fill => (c_x_scheduler_fill, c_b_scheduler_fill)
)
port map (
rst => rst_dut,
@@ -328,25 +359,32 @@ begin
dut : entity work.dp_mux
generic map (
g_data_w => c_lane_dat_w,
- g_empty_w => 1, -- not used
- g_in_channel_w => 1, -- not used
- g_error_w => 1, -- not used
+ -- not used
+ g_empty_w => 1,
+ -- not used
+ g_in_channel_w => 1,
+ -- not used
+ g_error_w => 1,
g_use_empty => false,
g_use_in_channel => false,
g_use_error => false,
g_nof_input => c_nof_input,
g_use_fifo => true,
- g_fifo_size => (c_b_scheduler_size, c_x_scheduler_size), -- 0 TO 1
- g_fifo_fill => (c_b_scheduler_fill, c_x_scheduler_fill) -- 0 TO 1
+ -- 0 TO 1
+ g_fifo_size => (c_b_scheduler_size, c_x_scheduler_size),
+ -- 0 TO 1
+ g_fifo_fill => (c_b_scheduler_fill, c_x_scheduler_fill)
)
port map (
rst => rst_dut,
clk => clk,
-- ST sinks
- snk_out_arr => OPEN, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out_arr => OPEN,
snk_in_arr => scheduler_sosi,
-- ST source
- src_in => c_dp_siso_rdy, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => c_dp_siso_rdy,
src_out => lane_tx_sosi
);
end generate;
@@ -356,7 +394,8 @@ begin
------------------------------------------------------------------------------
-- DUT input
- mark_in_sof <= lane_tx_xsof and lane_tx_bsof; -- signal when crosslet and beamlet frame are in phase
+ -- signal when crosslet and beamlet frame are in phase
+ mark_in_sof <= lane_tx_xsof and lane_tx_bsof;
-- DUT output
@@ -390,8 +429,10 @@ begin
mark_out_data_x_0 <= mark_out_fsn_x_hld_d and lane_tx_val;
mark_out_data_b_0 <= mark_out_fsn_b_hld_d and lane_tx_val;
- mark_out_eof_x <= '1' when unsigned(lane_tx_dat) = c_packet_size_x - 1 - 3 and mark_out_data_x = '1' and lane_tx_val = '1' else '0'; -- data 0..n-1 -3 to account for: idle, sfd, fsn
- mark_out_eof_b <= '1' when unsigned(lane_tx_dat) = c_packet_size_b - 1 - 3 and mark_out_data_b = '1' and lane_tx_val = '1' else '0'; -- data 0..n-1 -3 to account for: idle, sfd, fsn
+ -- data 0..n-1 -3 to account for: idle, sfd, fsn
+ mark_out_eof_x <= '1' when unsigned(lane_tx_dat) = c_packet_size_x - 1 - 3 and mark_out_data_x = '1' and lane_tx_val = '1' else '0';
+ -- data 0..n-1 -3 to account for: idle, sfd, fsn
+ mark_out_eof_b <= '1' when unsigned(lane_tx_dat) = c_packet_size_b - 1 - 3 and mark_out_data_b = '1' and lane_tx_val = '1' else '0';
mark_out_eof <= mark_out_eof_x or mark_out_eof_b;
mark_out_eof_x_d <= mark_out_eof_x when rising_edge(clk);
@@ -433,13 +474,15 @@ begin
if unsigned(lane_tx_dat) /= expected_fsn_x then
report "Scheduler crosslet out_fsn error" severity FAILURE;
end if;
- proc_cnt(c_fsn_max, rst, expected_fsn_x); -- increment for next packet
+ -- increment for next packet
+ proc_cnt(c_fsn_max, rst, expected_fsn_x);
end if;
if mark_out_fsn_b = '1' then
if unsigned(lane_tx_dat) /= expected_fsn_b then
report "Scheduler beamlet out_fsn error" severity FAILURE;
end if;
- proc_cnt(c_fsn_max, rst, expected_fsn_b); -- increment for next packet
+ -- increment for next packet
+ proc_cnt(c_fsn_max, rst, expected_fsn_b);
end if;
end if;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd b/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd
index 45705b5ea188f3ebf05af2bfc14cf766d55a2fb4..25504eb94599aa9885822020f0547a2ddd4a55c2 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd
@@ -32,7 +32,8 @@ end tb_dp_gap;
architecture tb of tb_dp_gap is
constant c_clk_period : time := 10 ns;
- constant c_dat_w : natural := c_dp_stream_data_w; -- use full SOSI data width to ease viewing in wave window
+ -- use full SOSI data width to ease viewing in wave window
+ constant c_dat_w : natural := c_dp_stream_data_w;
constant c_rl : natural := 1;
constant c_tx_init : natural := 0;
@@ -65,7 +66,8 @@ begin
gap_siso.ready <= '0';
wait until rst = '0';
- wait until rising_edge(clk); -- get synchronous to clk
+ -- get synchronous to clk
+ wait until rising_edge(clk);
tx_enable <= '1';
-- Run for 200 cycles; dp_gap should not interfere with the ready signal here.
@@ -78,15 +80,18 @@ begin
-- Deassert sink's ready and re-assert after 100 cycles. Dp_gap should reset its counters
-- after the first 5 invalid cycles already: it does not touch its ready signal because
-- a very long gap occured on its own.
- gap_siso.ready <= '0'; -- dp_gap will wait in s_wait_for_val here
+ -- dp_gap will wait in s_wait_for_val here
+ gap_siso.ready <= '0';
wait for c_clk_period * 100;
gap_siso.ready <= '1';
-- Now let's create a gap of exactly 5 cycles
wait for c_clk_period * 50;
gap_siso.ready <= '0';
- wait for c_clk_period * 5; -- gap of 5 cycles
- gap_siso.ready <= '1'; -- dp_gap should reset its counters
+ -- gap of 5 cycles
+ wait for c_clk_period * 5;
+ -- dp_gap should reset its counters
+ gap_siso.ready <= '1';
-- As a final test we'll create a series of smaller (than 5) gaps. dp_gap should force a gap
-- of 5 cycles every 100 cycles.
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd b/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
index 901fe867b80e92fcc4a8244fcc5a8b6d714009ea..a395243752268154c4e06802339906a25ee362cc 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
@@ -34,11 +34,13 @@ use common_lib.common_str_pkg.all;
entity tb_dp_hdr_insert_remove is
generic (
- g_data_w : natural := 96; -- Testing with uncommon data width. 96 is OK as it a a multiple of both c_word_w and g_symbol_w.
+ -- Testing with uncommon data width. 96 is OK as it a a multiple of both c_word_w and g_symbol_w.
+ g_data_w : natural := 96;
g_symbol_w : natural := 8;
g_nof_symbols : natural := 21;
g_in_en : t_dp_flow_control_enum := e_random;
- g_out_ready : t_dp_flow_control_enum := e_random -- e_active
+ -- e_active
+ g_out_ready : t_dp_flow_control_enum := e_random
);
end tb_dp_hdr_insert_remove;
@@ -52,7 +54,8 @@ architecture tb of tb_dp_hdr_insert_remove is
constant c_nof_repeat : natural := 100;
constant c_bsn_w : natural := 16;
constant c_symbol_init : natural := 0;
- constant c_symbol_mod : integer := 2**g_symbol_w; -- used to avoid TO_UVEC warning for smaller g_symbol_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ -- used to avoid TO_UVEC warning for smaller g_symbol_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ constant c_symbol_mod : integer := 2**g_symbol_w;
constant c_channel_init : integer := 0;
constant c_err_init : natural := 0;
constant c_sync_period : natural := 7;
@@ -68,8 +71,10 @@ architecture tb of tb_dp_hdr_insert_remove is
signal st_rst : std_logic;
signal st_clk : std_logic := '0';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -82,7 +87,8 @@ architecture tb of tb_dp_hdr_insert_remove is
signal prev_out_ready : std_logic_vector(0 to c_rl);
signal prev_out_data : std_logic_vector(g_data_w - 1 downto 0);
- signal prev_out_bsn : std_logic_vector(c_bsn_w - 1 downto 0) := (others => '1'); -- = -1
+ -- = -1
+ signal prev_out_bsn : std_logic_vector(c_bsn_w - 1 downto 0) := (others => '1');
signal prev_out_channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0) := TO_SVEC(c_channel_init - 1, c_dp_stream_channel_w);
signal prev_out_err : std_logic_vector(c_dp_stream_error_w - 1 downto 0) := TO_SVEC(c_err_init - 1, c_dp_stream_error_w);
-- SIGNAL expected_out_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
@@ -114,7 +120,8 @@ architecture tb of tb_dp_hdr_insert_remove is
signal hdr_channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0);
signal hdr_err : std_logic_vector(c_dp_stream_error_w - 1 downto 0);
- signal out_siso : t_dp_siso := c_dp_siso_hold; -- default xon = '1' is needed for proc_dp_gen_block_data()
+ -- default xon = '1' is needed for proc_dp_gen_block_data()
+ signal out_siso : t_dp_siso := c_dp_siso_hold;
signal out_sosi : t_dp_sosi;
signal out_data : std_logic_vector(g_data_w - 1 downto 0);
signal out_bsn : std_logic_vector(c_bsn_w - 1 downto 0);
@@ -133,7 +140,8 @@ architecture tb of tb_dp_hdr_insert_remove is
signal hdr_data_miso : t_mem_miso;
- constant c_hdr_nof_words : natural := 3; -- we're using a header of 3 96-bit words.
+ -- we're using a header of 3 96-bit words.
+ constant c_hdr_nof_words : natural := 3;
constant c_hdr_nof_mm_words : natural := c_hdr_nof_words * (g_data_w / c_word_w);
constant c_ram_header_start : std_logic_vector(c_word_w - 1 downto 0) := x"DEADBEEF";
@@ -199,7 +207,8 @@ begin
proc_common_wait_some_cycles(st_clk, 50);
for R in 0 to c_nof_repeat - 1 loop
- v_sync := sel_a_b(R mod c_sync_period = c_sync_offset, '1', '0'); -- v_bsn = R
+ -- v_bsn = R
+ v_sync := sel_a_b(R mod c_sync_period = c_sync_offset, '1', '0');
proc_dp_gen_block_data(c_rl, true, g_data_w, g_symbol_w, v_symbol, 0, 0, g_nof_symbols, v_channel, v_err, v_sync, TO_DP_BSN(R), st_clk, in_en, in_siso, in_sosi);
v_bsn := INCR_UVEC(v_bsn, 1);
v_symbol := (v_symbol + g_nof_symbols) mod c_symbol_mod;
@@ -213,7 +222,8 @@ begin
-- expected_out_channel <= TO_UVEC(v_channel-1, c_dp_stream_channel_w);
-- expected_out_err <= TO_UVEC(v_err-1, c_dp_stream_error_w);
- proc_common_wait_some_cycles(st_clk, 50); -- depends on stream control
+ -- depends on stream control
+ proc_common_wait_some_cycles(st_clk, 50);
verify_done <= '1';
proc_common_wait_some_cycles(st_clk, 1);
verify_done <= '0';
@@ -235,11 +245,14 @@ begin
-- DATA VERIFICATION
------------------------------------------------------------------------------
- verify_en <= '1' when rising_edge(st_clk) and out_sosi.sop = '1'; -- verify enable after first output sop
+ -- verify enable after first output sop
+ verify_en <= '1' when rising_edge(st_clk) and out_sosi.sop = '1';
-- SOSI control
- proc_dp_verify_valid(c_rl, st_clk, verify_en, out_siso.ready, prev_out_ready, out_val); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_gap_invalid(st_clk, out_val, out_sop, out_eop, out_gap); -- Verify that the output valid is low between blocks from eop to sop
+ -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_valid(c_rl, st_clk, verify_en, out_siso.ready, prev_out_ready, out_val);
+ -- Verify that the output valid is low between blocks from eop to sop
+ proc_dp_verify_gap_invalid(st_clk, out_val, out_sop, out_eop, out_gap);
-- SOSI data
-- . verify that the output is incrementing symbols, like the input stimuli
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
index cb7c1b30aed2a2c3b3e7c93429b7e97b91369b95..d205373d88318fbeb717ecccba41c848cd97602b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
@@ -37,17 +37,22 @@ architecture tb of tb_dp_latency_adapter is
type t_dut_natural_arr is array (t_dut_range range <>) of natural;
type t_dut_data_arr is array (t_dut_range range <>) of std_logic_vector(c_dp_data_w - 1 downto 0);
- type t_dut_logic_arr is array (t_dut_range range <>) of std_logic; -- can not use STD_LOGIC_VECTOR because of integer range
+ -- can not use STD_LOGIC_VECTOR because of integer range
+ type t_dut_logic_arr is array (t_dut_range range <>) of std_logic;
-- TX ready latency to DUT chain
constant c_tx_latency : natural := 3;
- constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0);
constant c_tx_offset_sop : natural := 3;
- constant c_tx_period_sop : natural := 7; -- sop in data valid cycle 3, 10, 17, ...
- constant c_tx_offset_eop : natural := 5; -- eop in data valid cycle 5, 12, 19, ...
+ -- sop in data valid cycle 3, 10, 17, ...
+ constant c_tx_period_sop : natural := 7;
+ -- eop in data valid cycle 5, 12, 19, ...
+ constant c_tx_offset_eop : natural := 5;
constant c_tx_period_eop : natural := c_tx_period_sop;
- constant c_tx_offset_sync : natural := 3; -- sync in data valid cycle 3, 20, 37, ...
+ -- sync in data valid cycle 3, 20, 37, ...
+ constant c_tx_offset_sync : natural := 3;
constant c_tx_period_sync : natural := 17;
-- The TB supports using 1 or more dp_latency_adapter Devices Under Test in a chain. DUT 0 is the first DUT and it
@@ -66,7 +71,8 @@ architecture tb of tb_dp_latency_adapter is
-- RX ready latency from DUT chain
constant c_rx_latency : natural := c_dut_latency(c_nof_dut - 1);
- constant c_verify_en_wait : natural := 10 + c_nof_dut * 2; -- wait some cycles before asserting verify enable
+ -- wait some cycles before asserting verify enable
+ constant c_verify_en_wait : natural := 10 + c_nof_dut * 2;
constant c_empty_offset : natural := 1;
constant c_channel_offset : natural := 2;
@@ -95,8 +101,10 @@ architecture tb of tb_dp_latency_adapter is
signal in_eop : std_logic;
-- DUT index -1 = in_data
- signal dut_ready : t_dut_logic_arr(-1 to c_nof_dut - 1); -- SISO
- signal dut_data : t_dut_data_arr(-1 to c_nof_dut - 1); -- SOSI
+ -- SISO
+ signal dut_ready : t_dut_logic_arr(-1 to c_nof_dut - 1);
+ -- SOSI
+ signal dut_data : t_dut_data_arr(-1 to c_nof_dut - 1);
signal dut_empty : t_dut_data_arr(-1 to c_nof_dut - 1) := (others => (others => '0'));
signal dut_channel : t_dut_data_arr(-1 to c_nof_dut - 1) := (others => (others => '0'));
signal dut_sync : t_dut_logic_arr(-1 to c_nof_dut - 1);
@@ -175,7 +183,8 @@ begin
proc_dp_verify_ctrl(c_tx_offset_sync, c_tx_period_sync, "sync", clk, verify_en, out_data, out_val, out_sync);
proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", clk, verify_en, out_data, out_val, out_sop);
proc_dp_verify_ctrl(c_tx_offset_eop, c_tx_period_eop, "eop", clk, verify_en, out_data, out_val, out_eop);
- proc_dp_verify_sop_and_eop(c_rx_latency, false, clk, out_val, out_val, out_sop, out_eop, hold_out_sop); -- Verify that sop and eop come in pairs, no check on valid between eop and sop
+ -- Verify that sop and eop come in pairs, no check on valid between eop and sop
+ proc_dp_verify_sop_and_eop(c_rx_latency, false, clk, out_val, out_val, out_sop, out_eop, hold_out_sop);
proc_dp_verify_other_sosi("empty", INCR_UVEC(out_data, c_empty_offset), clk, verify_en, out_empty);
proc_dp_verify_other_sosi("channel", INCR_UVEC(out_data, c_channel_offset), clk, verify_en, out_channel);
@@ -200,8 +209,10 @@ begin
dut_eop(-1) <= in_eop;
-- map sl, slv to record
- dut_ready(-1) <= dut_siso(-1).ready; -- SISO
- dut_sosi(-1).data(c_dp_data_w - 1 downto 0) <= dut_data(-1); -- SOSI
+ -- SISO
+ dut_ready(-1) <= dut_siso(-1).ready;
+ -- SOSI
+ dut_sosi(-1).data(c_dp_data_w - 1 downto 0) <= dut_data(-1);
dut_sosi(-1).empty <= dut_empty(-1)(c_dp_empty_w - 1 downto 0);
dut_sosi(-1).channel <= dut_channel(-1)(c_dp_channel_w - 1 downto 0);
dut_sosi(-1).sync <= dut_sync(-1);
@@ -228,8 +239,10 @@ begin
end generate;
-- map record to sl, slv
- dut_siso(c_nof_dut - 1).ready <= dut_ready(c_nof_dut - 1); -- SISO
- dut_data(c_nof_dut - 1) <= dut_sosi(c_nof_dut - 1).data(c_dp_data_w - 1 downto 0); -- SOSI
+ -- SISO
+ dut_siso(c_nof_dut - 1).ready <= dut_ready(c_nof_dut - 1);
+ -- SOSI
+ dut_data(c_nof_dut - 1) <= dut_sosi(c_nof_dut - 1).data(c_dp_data_w - 1 downto 0);
dut_empty(c_nof_dut - 1)(c_dp_empty_w - 1 downto 0) <= dut_sosi(c_nof_dut - 1).empty;
dut_channel(c_nof_dut - 1)(c_dp_channel_w - 1 downto 0) <= dut_sosi(c_nof_dut - 1).channel;
dut_sync(c_nof_dut - 1) <= dut_sosi(c_nof_dut - 1).sync;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd b/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
index a0a272ebb63ad809adc286fd1c76455cac57acf7..8b815f874573dc66a289492f984458753c1a3d44 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
@@ -38,14 +38,19 @@ use work.tb_dp_pkg.all;
entity tb_dp_latency_fifo is
generic (
- g_bypass : boolean := false; -- for clarity rather use g_bypass=TRUE than equivalent g_fifo_size=0
- g_input_rl : natural := 1; -- input ready latency
- g_output_rl : natural := 1; -- output ready latency
+ -- for clarity rather use g_bypass=TRUE than equivalent g_fifo_size=0
+ g_bypass : boolean := false;
+ -- input ready latency
+ g_input_rl : natural := 1;
+ -- output ready latency
+ g_output_rl : natural := 1;
g_fifo_size : natural := 1;
g_nof_symbols_per_block : natural := 51;
g_nof_symbols_per_data : natural := 4;
- g_in_en : t_dp_flow_control_enum := e_pulse; -- always e_active, e_random or e_pulse flow control
- g_out_ready : t_dp_flow_control_enum := e_random -- always e_active, e_random or e_pulse flow control
+ -- always e_active, e_random or e_pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_pulse;
+ -- always e_active, e_random or e_pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_random
);
end tb_dp_latency_fifo;
@@ -65,15 +70,18 @@ architecture tb of tb_dp_latency_fifo is
constant c_symbol_w : natural := 8;
constant c_data_w : natural := g_nof_symbols_per_data * c_symbol_w;
constant c_symbol_init : natural := 0;
- constant c_symbol_mod : integer := 2**c_symbol_w; -- used to avoid TO_UVEC warning for smaller c_symbol_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ -- used to avoid TO_UVEC warning for smaller c_symbol_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ constant c_symbol_mod : integer := 2**c_symbol_w;
-- tb default
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
signal rst : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -98,11 +106,13 @@ architecture tb of tb_dp_latency_fifo is
signal in_sop : std_logic;
signal in_eop : std_logic;
- signal fifo_usedw : std_logic_vector(ceil_log2(2 + g_input_rl + g_fifo_size) - 1 downto 0); -- +2+g_input_rl to match dp_latency_fifo usedw width
+ -- +2+g_input_rl to match dp_latency_fifo usedw width
+ signal fifo_usedw : std_logic_vector(ceil_log2(2 + g_input_rl + g_fifo_size) - 1 downto 0);
signal fifo_ful : std_logic;
signal fifo_emp : std_logic;
- signal out_siso : t_dp_siso := c_dp_siso_hold; -- default xon = '1' is needed for proc_dp_gen_block_data()
+ -- default xon = '1' is needed for proc_dp_gen_block_data()
+ signal out_siso : t_dp_siso := c_dp_siso_hold;
signal out_sosi : t_dp_sosi;
signal out_data : std_logic_vector(c_data_w - 1 downto 0);
signal out_sync : std_logic;
@@ -162,7 +172,8 @@ begin
-- End of stimuli
expected_out_data <= in_sosi.data(c_data_w - 1 downto 0);
- proc_common_wait_some_cycles(clk, 50); -- depends on stream control
+ -- depends on stream control
+ proc_common_wait_some_cycles(clk, 50);
verify_done <= '1';
proc_common_wait_some_cycles(clk, 1);
verify_done <= '0';
@@ -175,11 +186,14 @@ begin
-- DATA VERIFICATION
------------------------------------------------------------------------------
- verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1'; -- verify enable after first output sop
+ -- verify enable after first output sop
+ verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1';
-- SOSI control
- proc_dp_verify_valid(g_output_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_val); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_gap_invalid(clk, out_val, out_sop, out_eop, out_gap); -- Verify that the output valid is low between blocks from eop to sop
+ -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_valid(g_output_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_val);
+ -- Verify that the output valid is low between blocks from eop to sop
+ proc_dp_verify_gap_invalid(clk, out_val, out_sop, out_eop, out_gap);
-- SOSI data
-- . verify that the output is incrementing symbols, like the input stimuli
@@ -195,8 +209,10 @@ begin
dut : entity work.dp_latency_fifo
generic map (
g_bypass => g_bypass,
- g_input_rl => g_input_rl, -- input ready latency
- g_output_rl => g_output_rl, -- output ready latency
+ -- input ready latency
+ g_input_rl => g_input_rl,
+ -- output ready latency
+ g_output_rl => g_output_rl,
g_fifo_size => g_fifo_size
)
port map (
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
index bc34fa7cc535d23e5712b149b74f831293305c4d..dbf148f0e67c271a6c6015d6dcb6647b6eef6677 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
@@ -35,10 +35,13 @@ entity tb_dp_mux is
g_dut_use_in_channel : boolean := false;
g_dut_use_sync : boolean := true;
g_mode : natural := 3;
- g_dut_nof_input : natural := 2; -- >= 1, when 1 then use array_init() to assign the unconstrained t_natural_arr generic arrays
+ -- >= 1, when 1 then use array_init() to assign the unconstrained t_natural_arr generic arrays
+ g_dut_nof_input : natural := 2;
g_dut_use_fifo : boolean := false;
- g_dut_fifo_size : t_natural_arr := array_init(1024, 2); -- must match g_dut_nof_input
- g_dut_fifo_fill : t_natural_arr := array_init( 0, 2) -- must match g_dut_nof_input
+ -- must match g_dut_nof_input
+ g_dut_fifo_size : t_natural_arr := array_init(1024, 2);
+ -- must match g_dut_nof_input
+ g_dut_fifo_fill : t_natural_arr := array_init( 0, 2)
);
end tb_dp_mux;
@@ -46,8 +49,10 @@ architecture tb of tb_dp_mux is
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT
- constant c_dut_in_latency : natural := 1; -- fixed for dp_mux
- constant c_dut_out_latency : natural := 1; -- fixed for dp_mux
+ -- fixed for dp_mux
+ constant c_dut_in_latency : natural := 1;
+ -- fixed for dp_mux
+ constant c_dut_out_latency : natural := 1;
-- The mux input streams can have a channel field (c_dp_channel_user_w) and the mux will add some LSBits to represent the
-- input port numbers (c_dut_nof_input_w) in the mux output stream channel field. The total mux output stream channel
@@ -55,22 +60,32 @@ architecture tb of tb_dp_mux is
constant c_dut_in_channel_w : natural := c_dp_channel_user_w;
constant c_dut_nof_input_w : natural := true_log2(g_dut_nof_input);
constant c_dut_out_channel_w : natural := sel_a_b(g_dut_use_in_channel, c_dp_channel_user_w + c_dut_nof_input_w, c_dut_nof_input_w);
- constant c_dut_use_out_channel : boolean := true; -- fixed for tb
+ -- fixed for tb
+ constant c_dut_use_out_channel : boolean := true;
-- Stimuli
- constant c_tx_latency : natural := c_dut_in_latency; -- TX ready latency of TB
- constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ -- TX ready latency of TB
+ constant c_tx_latency : natural := c_dut_in_latency;
+ -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0);
constant c_tx_offset_sop : natural := 3;
- constant c_tx_period_sop : natural := 7; -- sop in data valid cycle 3, 10, 17, ...
- constant c_tx_offset_eop : natural := 9; -- eop in data valid cycle 9, 16, 23, ...
+ -- sop in data valid cycle 3, 10, 17, ...
+ constant c_tx_period_sop : natural := 7;
+ -- eop in data valid cycle 9, 16, 23, ...
+ constant c_tx_offset_eop : natural := 9;
constant c_tx_period_eop : natural := c_tx_period_sop;
- constant c_tx_offset_sync : natural := c_tx_offset_sop; -- sync in data valid at every n-th sop
+ -- sync in data valid at every n-th sop
+ constant c_tx_offset_sync : natural := c_tx_offset_sop;
constant c_tx_period_sync : natural := c_tx_period_sop * 3;
- constant c_rx_latency : natural := c_dut_out_latency; -- RX ready latency from DUT
- constant c_verify_en_wait : natural := 10 * g_dut_nof_input + largest(g_dut_fifo_fill); -- wait some cycles before asserting verify enable
+ -- RX ready latency from DUT
+ constant c_rx_latency : natural := c_dut_out_latency;
+ -- wait some cycles before asserting verify enable
+ constant c_verify_en_wait : natural := 10 * g_dut_nof_input + largest(g_dut_fifo_fill);
- constant c_empty_offset : natural := 1; -- dummy number to distinghuis the empty field from the data field value
- constant c_channel_offset : natural := 2; -- dummy number to distinghuis the channel field from the data field value
+ -- dummy number to distinghuis the empty field from the data field value
+ constant c_empty_offset : natural := 1;
+ -- dummy number to distinghuis the channel field from the data field value
+ constant c_channel_offset : natural := 2;
constant c_random_w : natural := 19;
@@ -97,7 +112,8 @@ architecture tb of tb_dp_mux is
signal tx_data : t_tx_data_arr_arr(0 to g_dut_nof_input - 1) := (others => (others => (others => '0')));
signal tx_val : t_tx_val_arr_arr( 0 to g_dut_nof_input - 1) := (others => (others => '0'));
- signal sel_ctrl : natural range 0 to g_dut_nof_input - 1 := 0; -- used by g_mode = 2, 3
+ -- used by g_mode = 2, 3
+ signal sel_ctrl : natural range 0 to g_dut_nof_input - 1 := 0;
signal in_ready : std_logic_vector(0 to g_dut_nof_input - 1);
signal in_data : t_dp_data_arr(0 to g_dut_nof_input - 1) := (others => (others => '0'));
@@ -175,15 +191,18 @@ begin
in_channel_vec((I + 1) * c_dp_data_w - 1 downto I * c_dp_data_w) <= in_channel(I);
-- Stimuli control
- proc_dp_count_en(rst, clk, sync, lfsr1, state(I), verify_done(I), tb_end_vec(I), cnt_en(I)); -- all cnt_en behave the same
- proc_dp_out_ready(rst, clk, sync, lfsr2, out_ready(I)); -- all out_ready behave the same
+ -- all cnt_en behave the same
+ proc_dp_count_en(rst, clk, sync, lfsr1, state(I), verify_done(I), tb_end_vec(I), cnt_en(I));
+ -- all out_ready behave the same
+ proc_dp_out_ready(rst, clk, sync, lfsr2, out_ready(I));
--proc_dp_count_en(rst, clk, sync_dly(I), lfsr1, state(I), verify_done(I), tb_end_vec(I), cnt_en(I)); -- all cnt_en are relatively delayed
--proc_dp_out_ready(rst, clk, sync_dly(I), lfsr2, out_ready(I)); -- all out_ready are relatively delayed
-- Output demux
out_data(I) <= mux_data;
out_empty(I) <= mux_empty;
- out_val(I) <= mux_val when c_dut_nof_input_w = 0 else -- avoid Warning: NUMERIC_STD.TO_INTEGER: null detected, returning 0
+ -- avoid Warning: NUMERIC_STD.TO_INTEGER: null detected, returning 0
+ out_val(I) <= mux_val when c_dut_nof_input_w = 0 else
mux_val when TO_UINT(mux_channel(c_dut_nof_input_w - 1 downto 0)) = I else '0';
out_sync(I) <= mux_sync when c_dut_nof_input_w = 0 else
mux_sync when TO_UINT(mux_channel(c_dut_nof_input_w - 1 downto 0)) = I else '0';
@@ -198,7 +217,8 @@ begin
proc_dp_verify_valid(c_rx_latency, clk, verify_en, out_ready(I), prev_out_ready(I), out_val(I));
proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", clk, verify_en, out_data(I), out_val(I), out_sop(I));
proc_dp_verify_ctrl(c_tx_offset_eop, c_tx_period_eop, "eop", clk, verify_en, out_data(I), out_val(I), out_eop(I));
- proc_dp_verify_sop_and_eop(clk, out_val(I), out_sop(I), out_eop(I), hold_out_sop(I)); -- Verify that sop and eop come in pairs
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(clk, out_val(I), out_sop(I), out_eop(I), hold_out_sop(I));
gen_verify_sync : if g_dut_use_sync = true generate
proc_dp_verify_ctrl(c_tx_offset_sync, c_tx_period_sync, "sync", clk, verify_en, out_data(I), out_val(I), out_sync(I));
@@ -227,8 +247,10 @@ begin
p_in : process(in_siso, in_data_vec, in_empty_vec, in_channel_vec, in_val, in_sop, in_eop)
begin
for I in 0 to g_dut_nof_input - 1 loop
- in_ready(I) <= in_siso(I).ready; -- SISO
- in_sosi(I).data(c_dp_data_w - 1 downto 0) <= in_data_vec( (I + 1) * c_dp_data_w - 1 downto I * c_dp_data_w); -- SOSI
+ -- SISO
+ in_ready(I) <= in_siso(I).ready;
+ -- SOSI
+ in_sosi(I).data(c_dp_data_w - 1 downto 0) <= in_data_vec( (I + 1) * c_dp_data_w - 1 downto I * c_dp_data_w);
in_sosi(I).empty <= in_empty_vec( c_dp_empty_w + I * c_dp_data_w - 1 downto I * c_dp_data_w);
in_sosi(I).channel <= in_channel_vec(c_dp_channel_w + I * c_dp_data_w - 1 downto I * c_dp_data_w);
in_sosi(I).sync <= in_sync(I);
@@ -238,8 +260,10 @@ begin
end loop;
end process;
- mux_siso.ready <= mux_ready; -- SISO
- mux_data <= mux_sosi.data(c_dp_data_w - 1 downto 0); -- SOSI
+ -- SISO
+ mux_siso.ready <= mux_ready;
+ -- SOSI
+ mux_data <= mux_sosi.data(c_dp_data_w - 1 downto 0);
mux_empty(c_dp_empty_w - 1 downto 0) <= mux_sosi.empty;
mux_channel <= mux_sosi.channel(c_dut_out_channel_w - 1 downto 0);
mux_sync <= mux_sosi.sync;
@@ -279,10 +303,12 @@ begin
-- Control
sel_ctrl => sel_ctrl,
-- ST sinks
- snk_out_arr => in_siso, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out_arr => in_siso,
snk_in_arr => in_sosi,
-- ST source
- src_in => mux_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => mux_siso,
src_out => mux_sosi
);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
index 4cca345bbd35100172c94b8936b40d15d0071eff..12eeab2c498520d1eecf4aebc137a1c14e159f24 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
@@ -158,7 +158,8 @@ begin
in_sosi.valid <= '0';
proc_common_wait_some_cycles(dp_clk, 1);
end loop;
- wait; -- add void WAIT statement to avoid (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+ -- add void WAIT statement to avoid (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+ wait;
end process;
gen_connect : for I in 0 to c_nof_streams - 1 generate
@@ -186,13 +187,20 @@ begin
dut : entity work.dp_offload_rx_filter
generic map(
- g_nof_streams => c_nof_streams, -- : POSITIVE;
- g_data_w => c_data_w, -- : NATURAL;
- g_hdr_field_arr => c_hdr_field_arr, -- : t_common_field_arr;
- g_eth_dst_mac_ena => true, -- : BOOLEAN;
- g_ip_dst_addr_ena => true, -- : BOOLEAN;
- g_ip_total_length_ena => true, -- : BOOLEAN;
- g_udp_dst_port_ena => true -- : BOOLEAN
+ -- : POSITIVE;
+ g_nof_streams => c_nof_streams,
+ -- : NATURAL;
+ g_data_w => c_data_w,
+ -- : t_common_field_arr;
+ g_hdr_field_arr => c_hdr_field_arr,
+ -- : BOOLEAN;
+ g_eth_dst_mac_ena => true,
+ -- : BOOLEAN;
+ g_ip_dst_addr_ena => true,
+ -- : BOOLEAN;
+ g_ip_total_length_ena => true,
+ -- : BOOLEAN
+ g_udp_dst_port_ena => true
)
port map(
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
index 41811773fe9a84b049f0d11b505e6d614e1f287b..8fe09d511dc2ab492235135f268b12f3a71503c1 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
@@ -68,13 +68,16 @@ use work.tb_dp_pkg.all;
entity tb_dp_offload_tx_v3 is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always e_active, e_random or e_pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- always e_active, e_random or e_pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse;
+ -- always e_active, e_random or e_pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
g_print_en : boolean := true;
-- specific
g_data_w : natural := 64;
g_symbol_w : natural := 8;
- g_empty : natural := 6; -- number of empty symbols in header when g_symbol_w < g_data_w, must be < c_nof_symbols_per_data
+ -- number of empty symbols in header when g_symbol_w < g_data_w, must be < c_nof_symbols_per_data
+ g_empty : natural := 6;
g_pkt_len : natural := 240;
g_pkt_gap : natural := 16
);
@@ -90,7 +93,8 @@ architecture tb of tb_dp_offload_tx_v3 is
-- . If g_symbol_w = g_data_w then boundary is at g_data_w, so empty is 0.
-- . If g_symbol_w < g_data_w then boundary is at last symbol, so empty is 1.
constant c_nof_symbols_per_data : natural := g_data_w / g_symbol_w;
- constant c_nof_symbols_per_bsn : natural := c_dp_stream_bsn_w / g_symbol_w; -- = 64 / g_symbol_w
+ -- = 64 / g_symbol_w
+ constant c_nof_symbols_per_bsn : natural := c_dp_stream_bsn_w / g_symbol_w;
constant c_bsn_w : natural := sel_a_b(c_nof_symbols_per_data = 1,
g_symbol_w * c_nof_symbols_per_bsn,
g_symbol_w * (c_nof_symbols_per_bsn - g_empty));
@@ -109,7 +113,8 @@ architecture tb of tb_dp_offload_tx_v3 is
--CONSTANT c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := c_dp_sosi_unsigned_rst; -- default 0 is no wrap
constant c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := TO_DP_SOSI_UNSIGNED('0', '0', '0', '0', c_data_max, c_dsp_max, c_dsp_max, c_unsigned_0, c_unsigned_0, c_unsigned_0, c_unsigned_0);
- constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones; -- default only accept increment +1
+ -- default only accept increment +1
+ constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones;
constant c_expected_pkt_len : natural := g_pkt_len;
constant c_sync_period : natural := 5;
@@ -126,150 +131,281 @@ architecture tb of tb_dp_offload_tx_v3 is
-- Tx offload
-----------------------------------------------------------------------------
-- From apertif_udp_offload_pkg.vhd:
- constant c_udp_offload_nof_hdr_fields : natural := 3 + 12 + 4 + 3; -- 22, 448b; 7 64b words
- constant c_udp_offload_nof_hdr_words_default : natural := 26; -- 23 single word + 3 double word = 26 32b words
+ -- 22, 448b; 7 64b words
+ constant c_udp_offload_nof_hdr_fields : natural := 3 + 12 + 4 + 3;
+ -- 23 single word + 3 double word = 26 32b words
+ constant c_udp_offload_nof_hdr_words_default : natural := 26;
constant c_udp_offload_nof_hdr_words_shortened : natural := c_udp_offload_nof_hdr_words_default - 1;
constant c_udp_offload_nof_hdr_words : natural := sel_a_b(c_use_shortened_header, c_udp_offload_nof_hdr_words_shortened, c_udp_offload_nof_hdr_words_default);
-- Notes:
-- . pre-calculated ip_header_checksum is valid only for UNB0, FN0 targeting IP 10.10.10.10
-- . udp_total_length = 176 beamlets * 64b / 8b = 1408B + 14 DP bytes + 8 UDP bytes = 1430B
- constant c_udp_offload_hdr_field_arr : t_common_field_arr(c_udp_offload_nof_hdr_fields - 1 downto 0) := ( -- index
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ), -- 21
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(x"0123456789AB") ), -- 20
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ), -- 19
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), -- 18
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ), -- 17
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ), -- 16
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ), -- 15
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ), -- 14
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ), -- 13
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ), -- 12
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ), -- 11
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ), -- 10
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(29928) ), -- 9
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ), -- 8
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ), -- 7
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ), -- 6
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- 5
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ), -- 4
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ), -- 3
- ( field_name_pad("dp_reserved" ), "RW", 47, field_default(x"010203040506") ), -- 2
- ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ), -- 1
- ( field_name_pad("dp_bsn" ), "RW", c_bsn_w, field_default(0) ) ); -- 0
+ -- index
+ constant c_udp_offload_hdr_field_arr : t_common_field_arr(c_udp_offload_nof_hdr_fields - 1 downto 0) := (
+ -- 21
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ),
+ -- 20
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(x"0123456789AB") ),
+ -- 19
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
+ -- 18
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
+ -- 17
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
+ -- 16
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
+ -- 15
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ),
+ -- 14
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
+ -- 13
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
+ -- 12
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ -- 11
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
+ -- 10
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
+ -- 9
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(29928) ),
+ -- 8
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ),
+ -- 7
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ),
+ -- 6
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
+ -- 5
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
+ -- 4
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ),
+ -- 3
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+ -- 2
+ ( field_name_pad("dp_reserved" ), "RW", 47, field_default(x"010203040506") ),
+ -- 1
+ ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
+ -- 0
+ ( field_name_pad("dp_bsn" ), "RW", c_bsn_w, field_default(0) ) );
-- TX: Corresponding storage of c_udp_offload_hdr_field_arr in MM register words
-- . Note: It appears that the tx_hdr_word read values are the MM write values, so read of value from logic fields (with MM override '0', e.g. dp_bsn, eth_src_mac) is not supported.
- constant c_expected_tx_hdr_word_arr_default : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_default - 1) := ( -- word address
- X"00000000", -- 0 = dp_bsn[31:0] -- readback is MM value, not the logic value
- X"00000000", -- 1 = dp_bsn[c_bsn_w-1:32]
- X"00000000", -- 2 = dp_sync
- X"03040506", -- 3 = dp_reserved[31:0]
- X"00000102", -- 4 = dp_reserved[47:32]
- X"00000000", -- 5 = udp_checksum
- X"00000596", -- 6 = udp_total_length
- X"00000000", -- 7 = udp_dst_port
- X"00000000", -- 8 = udp_src_port -- readback is MM value, not the logic value
- X"C0A80001", -- 9 = ip_dst_addr
- X"C0A80009", -- 10 = ip_src_addr
- X"000074E8", -- 11 = ip_header_checksum
- X"00000011", -- 12 = ip_protocol
- X"0000007F", -- 13 = ip_time_to_live
- X"00000000", -- 14 = ip_fragment_offset
- X"00000002", -- 15 = ip_flags
- X"00000000", -- 16 = ip_identification
- X"000005AA", -- 17 = ip_total_length
- X"00000000", -- 18 = ip_services
- X"00000005", -- 19 = ip_header_length
- X"00000004", -- 20 = ip_version
- X"00000800", -- 21 = eth_type[15:0]
- X"456789AB", -- 22 = eth_src_mac[31:0] -- readback is MM value, not the logic value
- X"00000123", -- 23 = eth_src_mac[47:32]
- X"214368AC", -- 24 = eth_dst_mac[31:0]
- X"0000001B"); -- 25 = eth_dst_mac[47:32]
-
- constant c_expected_tx_hdr_word_arr_shortened : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_shortened - 1) := ( -- word address
- X"00000000", -- 0 = dp_bsn[c_bsn_w-1:0] -- readback is MM value, not the logic value
- X"00000000", -- 1 = dp_sync
- X"03040506", -- 2 = dp_reserved[31:0]
- X"00000102", -- 3 = dp_reserved[47:32]
- X"00000000", -- 4 = udp_checksum
- X"00000596", -- 5 = udp_total_length
- X"00000000", -- 6 = udp_dst_port
- X"00000000", -- 7 = udp_src_port -- readback is MM value, not the logic value
- X"C0A80001", -- 8 = ip_dst_addr
- X"C0A80009", -- 9 = ip_src_addr
- X"000074E8", -- 10 = ip_header_checksum
- X"00000011", -- 11 = ip_protocol
- X"0000007F", -- 12 = ip_time_to_live
- X"00000000", -- 13 = ip_fragment_offset
- X"00000002", -- 14 = ip_flags
- X"00000000", -- 15 = ip_identification
- X"000005AA", -- 16 = ip_total_length
- X"00000000", -- 17 = ip_services
- X"00000005", -- 18 = ip_header_length
- X"00000004", -- 19 = ip_version
- X"00000800", -- 20 = eth_type[15:0]
- X"456789AB", -- 21 = eth_src_mac[31:0] -- readback is MM value, not the logic value
- X"00000123", -- 22 = eth_src_mac[47:32]
- X"214368AC", -- 23 = eth_dst_mac[31:0]
- X"0000001B"); -- 24 = eth_dst_mac[47:32]
+ -- word address
+ constant c_expected_tx_hdr_word_arr_default : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_default - 1) := (
+ -- 0 = dp_bsn[31:0] -- readback is MM value, not the logic value
+ X"00000000",
+ -- 1 = dp_bsn[c_bsn_w-1:32]
+ X"00000000",
+ -- 2 = dp_sync
+ X"00000000",
+ -- 3 = dp_reserved[31:0]
+ X"03040506",
+ -- 4 = dp_reserved[47:32]
+ X"00000102",
+ -- 5 = udp_checksum
+ X"00000000",
+ -- 6 = udp_total_length
+ X"00000596",
+ -- 7 = udp_dst_port
+ X"00000000",
+ -- 8 = udp_src_port -- readback is MM value, not the logic value
+ X"00000000",
+ -- 9 = ip_dst_addr
+ X"C0A80001",
+ -- 10 = ip_src_addr
+ X"C0A80009",
+ -- 11 = ip_header_checksum
+ X"000074E8",
+ -- 12 = ip_protocol
+ X"00000011",
+ -- 13 = ip_time_to_live
+ X"0000007F",
+ -- 14 = ip_fragment_offset
+ X"00000000",
+ -- 15 = ip_flags
+ X"00000002",
+ -- 16 = ip_identification
+ X"00000000",
+ -- 17 = ip_total_length
+ X"000005AA",
+ -- 18 = ip_services
+ X"00000000",
+ -- 19 = ip_header_length
+ X"00000005",
+ -- 20 = ip_version
+ X"00000004",
+ -- 21 = eth_type[15:0]
+ X"00000800",
+ -- 22 = eth_src_mac[31:0] -- readback is MM value, not the logic value
+ X"456789AB",
+ -- 23 = eth_src_mac[47:32]
+ X"00000123",
+ -- 24 = eth_dst_mac[31:0]
+ X"214368AC",
+ -- 25 = eth_dst_mac[47:32]
+ X"0000001B");
+
+ -- word address
+ constant c_expected_tx_hdr_word_arr_shortened : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_shortened - 1) := (
+ -- 0 = dp_bsn[c_bsn_w-1:0] -- readback is MM value, not the logic value
+ X"00000000",
+ -- 1 = dp_sync
+ X"00000000",
+ -- 2 = dp_reserved[31:0]
+ X"03040506",
+ -- 3 = dp_reserved[47:32]
+ X"00000102",
+ -- 4 = udp_checksum
+ X"00000000",
+ -- 5 = udp_total_length
+ X"00000596",
+ -- 6 = udp_dst_port
+ X"00000000",
+ -- 7 = udp_src_port -- readback is MM value, not the logic value
+ X"00000000",
+ -- 8 = ip_dst_addr
+ X"C0A80001",
+ -- 9 = ip_src_addr
+ X"C0A80009",
+ -- 10 = ip_header_checksum
+ X"000074E8",
+ -- 11 = ip_protocol
+ X"00000011",
+ -- 12 = ip_time_to_live
+ X"0000007F",
+ -- 13 = ip_fragment_offset
+ X"00000000",
+ -- 14 = ip_flags
+ X"00000002",
+ -- 15 = ip_identification
+ X"00000000",
+ -- 16 = ip_total_length
+ X"000005AA",
+ -- 17 = ip_services
+ X"00000000",
+ -- 18 = ip_header_length
+ X"00000005",
+ -- 19 = ip_version
+ X"00000004",
+ -- 20 = eth_type[15:0]
+ X"00000800",
+ -- 21 = eth_src_mac[31:0] -- readback is MM value, not the logic value
+ X"456789AB",
+ -- 22 = eth_src_mac[47:32]
+ X"00000123",
+ -- 23 = eth_dst_mac[31:0]
+ X"214368AC",
+ -- 24 = eth_dst_mac[47:32]
+ X"0000001B");
-- RX: Corresponding storage of c_udp_offload_hdr_field_arr in MM register words
- constant c_expected_rx_hdr_word_arr_default : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_default - 1) := ( -- word address
- X"00000002", -- 0 = dp_bsn[31:0] -- dynamic value obtained from simulation
- X"00000000", -- 1 = dp_bsn[c_bsn_w-1:32]
- X"00000001", -- 2 = dp_sync -- dynamic value obtained from simulation
- X"03040506", -- 3 = dp_reserved[31:0]
- X"00000102", -- 4 = dp_reserved[47:32]
- X"00000000", -- 5 = udp_checksum
- X"00000596", -- 6 = udp_total_length
- X"00000000", -- 7 = udp_dst_port
- X"00000000", -- 8 = udp_src_port
- X"C0A80001", -- 9 = ip_dst_addr
- X"C0A80009", -- 10 = ip_src_addr
- X"000074E8", -- 11 = ip_header_checksum
- X"00000011", -- 12 = ip_protocol
- X"0000007F", -- 13 = ip_time_to_live
- X"00000000", -- 14 = ip_fragment_offset
- X"00000002", -- 15 = ip_flags
- X"00000000", -- 16 = ip_identification
- X"000005AA", -- 17 = ip_total_length
- X"00000000", -- 18 = ip_services
- X"00000005", -- 19 = ip_header_length
- X"00000004", -- 20 = ip_version
- X"00000800", -- 21 = eth_type[15:0]
- X"86080000", -- 22 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
- X"00000022", -- 23 = eth_src_mac[47:32]
- X"214368AC", -- 24 = eth_dst_mac[31:0]
- X"0000001B"); -- 25 = eth_dst_mac[47:32]
-
- constant c_expected_rx_hdr_word_arr_shortened : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_shortened - 1) := ( -- word address
- X"00000002", -- 0 = dp_bsn[c_bsn_w-1:0] -- dynamic value obtained from simulation
- X"00000001", -- 1 = dp_sync -- dynamic value obtained from simulation
- X"03040506", -- 2 = dp_reserved[31:0]
- X"00000102", -- 3 = dp_reserved[47:32]
- X"00000000", -- 4 = udp_checksum
- X"00000596", -- 5 = udp_total_length
- X"00000000", -- 6 = udp_dst_port
- X"00000000", -- 7 = udp_src_port
- X"C0A80001", -- 8 = ip_dst_addr
- X"C0A80009", -- 9 = ip_src_addr
- X"000074E8", -- 10 = ip_header_checksum
- X"00000011", -- 11 = ip_protocol
- X"0000007F", -- 12 = ip_time_to_live
- X"00000000", -- 13 = ip_fragment_offset
- X"00000002", -- 14 = ip_flags
- X"00000000", -- 15 = ip_identification
- X"000005AA", -- 16 = ip_total_length
- X"00000000", -- 17 = ip_services
- X"00000005", -- 18 = ip_header_length
- X"00000004", -- 19 = ip_version
- X"00000800", -- 20 = eth_type[15:0]
- X"86080000", -- 21 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
- X"00000022", -- 22 = eth_src_mac[47:32]
- X"214368AC", -- 23 = eth_dst_mac[31:0]
- X"0000001B"); -- 24 = eth_dst_mac[47:32]
+ -- word address
+ constant c_expected_rx_hdr_word_arr_default : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_default - 1) := (
+ -- 0 = dp_bsn[31:0] -- dynamic value obtained from simulation
+ X"00000002",
+ -- 1 = dp_bsn[c_bsn_w-1:32]
+ X"00000000",
+ -- 2 = dp_sync -- dynamic value obtained from simulation
+ X"00000001",
+ -- 3 = dp_reserved[31:0]
+ X"03040506",
+ -- 4 = dp_reserved[47:32]
+ X"00000102",
+ -- 5 = udp_checksum
+ X"00000000",
+ -- 6 = udp_total_length
+ X"00000596",
+ -- 7 = udp_dst_port
+ X"00000000",
+ -- 8 = udp_src_port
+ X"00000000",
+ -- 9 = ip_dst_addr
+ X"C0A80001",
+ -- 10 = ip_src_addr
+ X"C0A80009",
+ -- 11 = ip_header_checksum
+ X"000074E8",
+ -- 12 = ip_protocol
+ X"00000011",
+ -- 13 = ip_time_to_live
+ X"0000007F",
+ -- 14 = ip_fragment_offset
+ X"00000000",
+ -- 15 = ip_flags
+ X"00000002",
+ -- 16 = ip_identification
+ X"00000000",
+ -- 17 = ip_total_length
+ X"000005AA",
+ -- 18 = ip_services
+ X"00000000",
+ -- 19 = ip_header_length
+ X"00000005",
+ -- 20 = ip_version
+ X"00000004",
+ -- 21 = eth_type[15:0]
+ X"00000800",
+ -- 22 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
+ X"86080000",
+ -- 23 = eth_src_mac[47:32]
+ X"00000022",
+ -- 24 = eth_dst_mac[31:0]
+ X"214368AC",
+ -- 25 = eth_dst_mac[47:32]
+ X"0000001B");
+
+ -- word address
+ constant c_expected_rx_hdr_word_arr_shortened : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_shortened - 1) := (
+ -- 0 = dp_bsn[c_bsn_w-1:0] -- dynamic value obtained from simulation
+ X"00000002",
+ -- 1 = dp_sync -- dynamic value obtained from simulation
+ X"00000001",
+ -- 2 = dp_reserved[31:0]
+ X"03040506",
+ -- 3 = dp_reserved[47:32]
+ X"00000102",
+ -- 4 = udp_checksum
+ X"00000000",
+ -- 5 = udp_total_length
+ X"00000596",
+ -- 6 = udp_dst_port
+ X"00000000",
+ -- 7 = udp_src_port
+ X"00000000",
+ -- 8 = ip_dst_addr
+ X"C0A80001",
+ -- 9 = ip_src_addr
+ X"C0A80009",
+ -- 10 = ip_header_checksum
+ X"000074E8",
+ -- 11 = ip_protocol
+ X"00000011",
+ -- 12 = ip_time_to_live
+ X"0000007F",
+ -- 13 = ip_fragment_offset
+ X"00000000",
+ -- 14 = ip_flags
+ X"00000002",
+ -- 15 = ip_identification
+ X"00000000",
+ -- 16 = ip_total_length
+ X"000005AA",
+ -- 17 = ip_services
+ X"00000000",
+ -- 18 = ip_header_length
+ X"00000005",
+ -- 19 = ip_version
+ X"00000004",
+ -- 20 = eth_type[15:0]
+ X"00000800",
+ -- 21 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
+ X"86080000",
+ -- 22 = eth_src_mac[47:32]
+ X"00000022",
+ -- 23 = eth_dst_mac[31:0]
+ X"214368AC",
+ -- 24 = eth_dst_mac[47:32]
+ X"0000001B");
-- From apertif_unb1_fn_beamformer_udp_offload.vhd: 221 111111111000 0000 000
-- Override ('1') only the Ethernet fields so we can use MM defaults there. 109 876543210987 6543 210
@@ -354,12 +490,15 @@ begin
u_dp_stream_stimuli : entity work.dp_stream_stimuli
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 15,
g_pulse_active => c_stimuli_pulse_active,
g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_stimuli,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -381,9 +520,12 @@ begin
src_out => stimuli_src_out,
-- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ -- expected verify_snk_in after end of stimuli
+ last_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ last_snk_in_evt => last_snk_in_evt,
+ -- signal end of tb as far as this dp_stream_stimuli is concerned
+ tb_end => tb_end
);
------------------------------------------------------------------------------
@@ -406,7 +548,8 @@ begin
-- . after the test
verify_last_snk_in_evt.sync <= last_snk_in_evt;
- verify_last_snk_in_evt.bsn <= last_snk_in_evt; -- thanks to using rx_hdr_fields_raw_arr for bsn field
+ -- thanks to using rx_hdr_fields_raw_arr for bsn field
+ verify_last_snk_in_evt.bsn <= last_snk_in_evt;
verify_last_snk_in_evt.data <= last_snk_in_evt;
verify_last_snk_in_evt.re <= '0';
verify_last_snk_in_evt.im <= '0';
@@ -419,12 +562,15 @@ begin
u_dp_stream_verify : entity work.dp_stream_verify
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 14,
g_pulse_active => c_verify_pulse_active,
g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_verify,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -443,11 +589,14 @@ begin
snk_in => verify_snk_in,
-- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+ -- enable verify to verify that the verify_snk_in fields are incrementing
+ verify_snk_in_enable => verify_snk_in_enable,
-- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ -- expected verify_snk_in after end of stimuli
+ expected_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ verify_expected_snk_in_evt => verify_last_snk_in_evt
);
------------------------------------------------------------------------------
@@ -469,7 +618,8 @@ begin
rst => dp_rst,
clk => dp_clk,
- snk_out => OPEN, -- stimuli_src_in
+ -- stimuli_src_in
+ snk_out => OPEN,
snk_in => stimuli_src_out,
src_in => dp_fifo_sc_src_in,
@@ -567,7 +717,8 @@ begin
-- at the eop has no impact. However the tb will still eventually fail
-- the stimuli is always active, because then the u_dp_fifo_sc will run
-- full.
- tx_offload_siso_arr <= link_offload_siso_arr; -- (OTHERS=>c_dp_siso_rdy);
+ -- (OTHERS=>c_dp_siso_rdy);
+ tx_offload_siso_arr <= link_offload_siso_arr;
end process;
------------------------------------------------------------------------------
@@ -646,7 +797,8 @@ begin
proc_mem_mm_bus_rd(0, mm_clk, reg_dp_offload_rx_hdr_dat_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
v_word := reg_dp_offload_rx_hdr_dat_miso.rddata(31 downto 0);
- rx_hdr_word <= v_word; -- View word in wave window
+ -- View word in wave window
+ rx_hdr_word <= v_word;
if c_use_shortened_header then
assert v_word = INCR_UVEC(c_expected_rx_hdr_word_arr_shortened(0), 1) report "Unexpected dp_bsn from MM" severity ERROR;
else
@@ -660,7 +812,8 @@ begin
end if;
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
v_word := reg_dp_offload_rx_hdr_dat_miso.rddata(31 downto 0);
- rx_hdr_word <= v_word; -- View word in wave window
+ -- View word in wave window
+ rx_hdr_word <= v_word;
assert v_word = TO_UVEC(0, 32) report "Unexpected dp_sync from MM" severity ERROR;
wait;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
index f0d5e7bde9cc567b2d583ebaf038e3f8adf32b95..a1a2f0b51f99f8025a31f646e40de84684d8310b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
@@ -38,24 +38,34 @@ use work.tb_dp_pkg.all;
entity tb_dp_packet is
generic (
g_data_w : natural := 16;
- g_in_en : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_out_ready : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_nof_repeat : natural := 2 -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
+ -- always active, random or pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_active;
+ -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
+ g_nof_repeat : natural := 2
);
end tb_dp_packet;
architecture tb of tb_dp_packet is
constant c_rl : natural := 1;
constant c_data_init : integer := 0;
- constant c_data_w : integer := sel_a_b(g_data_w < 30, g_data_w, 30); -- used to avoid INTEGER range error for 2**31 and 2**32
- constant c_data_mod : integer := 2**c_data_w; -- used to avoid TO_UVEC warning for smaller g_data_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ -- used to avoid INTEGER range error for 2**31 and 2**32
+ constant c_data_w : integer := sel_a_b(g_data_w < 30, g_data_w, 30);
+ -- used to avoid TO_UVEC warning for smaller g_data_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ constant c_data_mod : integer := 2**c_data_w;
constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0877665544332211";
constant c_err_init : natural := 247;
- constant c_err_w : integer := sel_a_b(c_dp_stream_error_w < 30, c_dp_stream_error_w, 30); -- used to avoid INTEGER range error for 2**31 and 2**32
- constant c_err_mod : integer := 2**c_err_w; -- used to avoid TO_UVEC warning for smaller c_dp_stream_error_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
- constant c_channel_init : integer := 0; -- fixed
- constant c_channel_w : integer := sel_a_b(c_dp_stream_channel_w < 30, c_dp_stream_channel_w, 30); -- used to avoid INTEGER range error for 2**31 and 2**32
- constant c_channel_mod : integer := 2**c_channel_w; -- used to avoid TO_UVEC warning for smaller c_dp_stream_channel_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ -- used to avoid INTEGER range error for 2**31 and 2**32
+ constant c_err_w : integer := sel_a_b(c_dp_stream_error_w < 30, c_dp_stream_error_w, 30);
+ -- used to avoid TO_UVEC warning for smaller c_dp_stream_error_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ constant c_err_mod : integer := 2**c_err_w;
+ -- fixed
+ constant c_channel_init : integer := 0;
+ -- used to avoid INTEGER range error for 2**31 and 2**32
+ constant c_channel_w : integer := sel_a_b(c_dp_stream_channel_w < 30, c_dp_stream_channel_w, 30);
+ -- used to avoid TO_UVEC warning for smaller c_dp_stream_channel_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ constant c_channel_mod : integer := 2**c_channel_w;
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 7;
constant c_sync_period_w : natural := 3;
@@ -73,8 +83,10 @@ architecture tb of tb_dp_packet is
signal clk : std_logic := '1';
signal rst : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -170,7 +182,8 @@ begin
-- No gaps between the blocks
for I in 0 to c_nof_ch - 1 loop
proc_dp_gen_block_data(c_rl, true, g_data_w, g_data_w, v_data, 0, 0, c_len_arr(I), v_channel, v_err, v_sync, v_bsn, clk, in_en, in_siso, in_sosi);
- v_sync := sel_a_b(unsigned(v_bsn(c_sync_period_w - 1 downto 0)) = c_sync_offset - 1, '1', '0'); -- sync pulse every at 2**c_sync_period_w block
+ -- sync pulse every at 2**c_sync_period_w block
+ v_sync := sel_a_b(unsigned(v_bsn(c_sync_period_w - 1 downto 0)) = c_sync_offset - 1, '1', '0');
v_bsn := INCR_UVEC(v_bsn, 1);
v_channel := ((v_channel + 1) mod c_nof_ch) mod c_channel_mod;
v_data := (v_data + c_len_arr(I)) mod c_data_mod;
@@ -190,9 +203,11 @@ begin
-- Signal end of stimuli
expected_rx_bsn <= INCR_UVEC(v_bsn, -1);
- expected_rx_data <= TO_UVEC(sel_a_b(v_data > 0, v_data, c_data_mod) - 1, g_data_w); -- account for data wrap, which is quite likely for small g_data_w
+ -- account for data wrap, which is quite likely for small g_data_w
+ expected_rx_data <= TO_UVEC(sel_a_b(v_data > 0, v_data, c_data_mod) - 1, g_data_w);
expected_rx_err <= TO_UVEC(v_err - 1, expected_rx_err'length);
- proc_common_wait_some_cycles(clk, 100); -- depends on stream control
+ -- depends on stream control
+ proc_common_wait_some_cycles(clk, 100);
verify_done <= '1';
proc_common_wait_some_cycles(clk, 1);
verify_done <= '0';
@@ -217,23 +232,35 @@ begin
verify_en <= '1';
- proc_dp_verify_data("rx_sosi.data", c_rl, clk, verify_en, rx_siso.ready, rx_val, rx_data, prev_rx_data); -- Verify that the output is incrementing data, like the input stimuli
- proc_dp_verify_value(e_equal, clk, verify_done, expected_rx_data, prev_rx_data); -- Verify that the stimuli have been applied at all
-
- proc_dp_verify_data("rx_sosi.bsn", c_rl, clk, verify_en, rx_siso.ready, rx_sop, rx_bsn, prev_rx_bsn); -- Verify that the output is incrementing bsn, like the input stimuli
- proc_dp_verify_value(e_equal, clk, verify_done, expected_rx_bsn, prev_rx_bsn); -- Verify that the stimuli have been applied at all
-
- proc_dp_verify_data("rx_sosi.err", c_rl, clk, verify_en, rx_siso.ready, rx_eop, rx_err, prev_rx_err); -- Verify that the output is incrementing err, like the input stimuli
- proc_dp_verify_value(e_equal, clk, verify_done, expected_rx_err, prev_rx_err); -- Verify that the stimuli have been applied at all
-
- proc_dp_verify_data("rx_sosi.channel", c_rl, to_unsigned(c_nof_ch - 1,32), clk, verify_en, rx_siso.ready, rx_sop, rx_channel, prev_rx_channel); -- Verify that the output is incrementing channel MOD c_nof_ch, like the input stimuli
-
- proc_dp_verify_valid(c_rl, clk, verify_en, pkt_siso.ready, prev_pkt_ready, pkt_val); -- Verify that the encoder output valid fits with the output ready latency
- proc_dp_verify_valid(c_rl, clk, verify_en, rx_siso.ready, prev_rx_ready, rx_val); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_gap_invalid(clk, rx_val, rx_sop, rx_eop, rx_gap); -- Verify that the output valid is low between blocks
- proc_dp_verify_sop_and_eop(clk, rx_val, rx_sop, rx_eop, hold_rx_sop); -- Verify that sop and eop come in pairs
-
- proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en, rx_sync, rx_sop, rx_bsn); -- Verify that the output sync occurs when expected
+ -- Verify that the output is incrementing data, like the input stimuli
+ proc_dp_verify_data("rx_sosi.data", c_rl, clk, verify_en, rx_siso.ready, rx_val, rx_data, prev_rx_data);
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done, expected_rx_data, prev_rx_data);
+
+ -- Verify that the output is incrementing bsn, like the input stimuli
+ proc_dp_verify_data("rx_sosi.bsn", c_rl, clk, verify_en, rx_siso.ready, rx_sop, rx_bsn, prev_rx_bsn);
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done, expected_rx_bsn, prev_rx_bsn);
+
+ -- Verify that the output is incrementing err, like the input stimuli
+ proc_dp_verify_data("rx_sosi.err", c_rl, clk, verify_en, rx_siso.ready, rx_eop, rx_err, prev_rx_err);
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done, expected_rx_err, prev_rx_err);
+
+ -- Verify that the output is incrementing channel MOD c_nof_ch, like the input stimuli
+ proc_dp_verify_data("rx_sosi.channel", c_rl, to_unsigned(c_nof_ch - 1,32), clk, verify_en, rx_siso.ready, rx_sop, rx_channel, prev_rx_channel);
+
+ -- Verify that the encoder output valid fits with the output ready latency
+ proc_dp_verify_valid(c_rl, clk, verify_en, pkt_siso.ready, prev_pkt_ready, pkt_val);
+ -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_valid(c_rl, clk, verify_en, rx_siso.ready, prev_rx_ready, rx_val);
+ -- Verify that the output valid is low between blocks
+ proc_dp_verify_gap_invalid(clk, rx_val, rx_sop, rx_eop, rx_gap);
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(clk, rx_val, rx_sop, rx_eop, hold_rx_sop);
+
+ -- Verify that the output sync occurs when expected
+ proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en, rx_sync, rx_sop, rx_bsn);
------------------------------------------------------------------------------
-- DP SOSI ==> DP PACKET
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
index 6466f7e36b7f408b3d2687d849b74e35654a6358..d5a59808742504fe703ab90196ef18b15c216904 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
@@ -56,8 +56,10 @@ use work.tb_dp_pkg.all;
entity tb_dp_packet_merge is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
g_data_w : natural := 4;
g_nof_repeat : natural := 24;
@@ -67,7 +69,8 @@ entity tb_dp_packet_merge is
g_align_at_sync : boolean := false;
g_verify_bsn_err : boolean := false;
g_bsn_increment : natural := 2;
- g_bsn_err_at_pkt_index : natural := 6; -- force wrong snk_in.bsn for packet with this index, in range(g_nof_repeat)
+ -- force wrong snk_in.bsn for packet with this index, in range(g_nof_repeat)
+ g_bsn_err_at_pkt_index : natural := 6;
g_use_dp_packet_unmerge : boolean := false
);
end tb_dp_packet_merge;
@@ -83,15 +86,20 @@ architecture tb of tb_dp_packet_merge is
constant c_data_max : unsigned(g_data_w - 1 downto 0) := (others => '1');
constant c_data_init : integer := -1;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
- constant c_bsn_error : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '1'); -- use -1 as bsn error value
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
+ -- use -1 as bsn error value
+ constant c_bsn_error : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '1');
constant c_err_init : natural := 247;
- constant c_bsn_err_bi : natural := 31; -- use sufficiently high bsn error bit index, that is outside counter range of c_err_init
- constant c_channel_init : integer := 5; -- fixed
+ -- use sufficiently high bsn error bit index, that is outside counter range of c_err_init
+ constant c_bsn_err_bi : natural := 31;
+ -- fixed
+ constant c_channel_init : integer := 5;
constant c_nof_pkt_not_zero : natural := sel_a_b(g_nof_pkt = 0, 1, g_nof_pkt);
constant c_nof_merged_sop : natural := sel_a_b(g_nof_pkt = 0, 0, ceil_div(g_nof_repeat, c_nof_pkt_not_zero));
- constant c_verify_at_least : natural := largest(1,c_nof_merged_sop / 2); -- verify that at least some packets have been merged, not exact to allow variation by p_stimuli_mm
+ -- verify that at least some packets have been merged, not exact to allow variation by p_stimuli_mm
+ constant c_verify_at_least : natural := largest(1,c_nof_merged_sop / 2);
constant c_verify_data_gap : natural := g_nof_pkt;
constant c_verify_bsn_gap : natural := g_nof_pkt * g_bsn_increment;
constant c_exp_err_at_pkt_index : natural := g_bsn_err_at_pkt_index / sel_a_b(g_nof_pkt = 0, 1, g_nof_pkt);
@@ -101,8 +109,10 @@ architecture tb of tb_dp_packet_merge is
signal rst : std_logic := '1';
signal sl1 : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -184,10 +194,12 @@ begin
-- Auto increment v_sosi field values for this packet
v_bsn := INCR_UVEC(v_bsn, g_bsn_increment);
v_sosi.bsn := v_bsn;
- v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_sync_period) = c_sync_offset, '1', '0'); -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_sync_period) = c_sync_offset, '1', '0');
v_sosi.channel := INCR_UVEC(v_sosi.channel, 1);
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_data_w - 1 downto 0)); -- wrap when >= 2**g_data_w
+ -- wrap when >= 2**g_data_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_data_w - 1 downto 0));
v_sosi.err := INCR_UVEC(v_sosi.err, 1);
-- Force bsn error in one snk_in block, to verify src_out.err(g_bsn_err_bi) bit
@@ -213,11 +225,13 @@ begin
-- . account for g_pkt_len
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len - 1);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_data_w - 1 downto 0)); -- wrap when >= 2**g_data_w
+ -- wrap when >= 2**g_data_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_data_w - 1 downto 0));
expected_verify_snk_in <= v_sosi;
-- Signal end of stimuli
- proc_common_wait_some_cycles(clk, 100); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ proc_common_wait_some_cycles(clk, 100);
if verify_value_en = '1' then
proc_common_gen_pulse(clk, verify_done);
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
index 7046fe0e483ecbc27af54c2431eedc0d8feb2e42..971ff9f0b58f350a4c479ed317e9fa49e08bda42 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
@@ -31,10 +31,14 @@ use work.tb_dp_pkg.all;
entity tb_dp_packetizing is
generic (
-- Try different packing
- g_usr_nof_words : natural := 4; -- 1; -- g_phy_dat_w/g_usr_dat_w = 16/16 = 1/1
- g_phy_nof_words : natural := 1; -- 1;
- g_usr_dat_w : natural := 8; -- 10;
- g_phy_dat_w : natural := 32 -- 10 -- < c_dp_crc_w
+ -- 1; -- g_phy_dat_w/g_usr_dat_w = 16/16 = 1/1
+ g_usr_nof_words : natural := 4;
+ -- 1;
+ g_phy_nof_words : natural := 1;
+ -- 10;
+ g_usr_dat_w : natural := 8;
+ -- 10 -- < c_dp_crc_w
+ g_phy_dat_w : natural := 32
);
end tb_dp_packetizing;
@@ -48,12 +52,14 @@ architecture tb of tb_dp_packetizing is
--CONSTANT c_phy_link_valid_support : BOOLEAN := TRUE;
constant c_phy_link_valid_support : boolean := false;
- constant c_fsn_w : natural := 8; -- <= g_usr_dat_w
+ -- <= g_usr_dat_w
+ constant c_fsn_w : natural := 8;
------------------------------------------------------------------------------
-- Try different block sizes
- constant c_usr_block_size : natural := 60; -- = 2*2*3*5, so suitable for g_usr_nof_words = 1, 2, 3, 4, 5, 6 and with c_dp_gap_min=4 yields minimal c_interval_size
+ -- = 2*2*3*5, so suitable for g_usr_nof_words = 1, 2, 3, 4, 5, 6 and with c_dp_gap_min=4 yields minimal c_interval_size
+ constant c_usr_block_size : natural := 60;
--CONSTANT c_usr_block_size : NATURAL := 20 * g_usr_nof_words; -- dp_repack does not support padding, so the g_usr_nof_words must fit the block size
constant c_usr_block_size_w : natural := ceil_log2(c_usr_block_size + c_dp_gap_min);
constant c_interval_size : natural := 2**c_usr_block_size_w;
@@ -67,8 +73,10 @@ architecture tb of tb_dp_packetizing is
constant c_fifo_size : natural := c_usr_block_size;
constant c_fifo_fill : integer := sel_a_b(g_usr_nof_words <= g_phy_nof_words,
- 0, -- no_xmt_pacer (dummy value)
- c_usr_block_size - c_phy_block_size); -- gen_xmt_pacer
+ -- no_xmt_pacer (dummy value)
+ 0,
+ -- gen_xmt_pacer
+ c_usr_block_size - c_phy_block_size);
constant c_rcv_fifo_nof_words : natural := c_phy_block_size;
@@ -149,7 +157,8 @@ architecture tb of tb_dp_packetizing is
signal rcv_eof : std_logic;
signal rcv_err : std_logic := '0';
- signal prev_rcv_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '1'); -- -1 to also verify first sample 0 correctly
+ -- -1 to also verify first sample 0 correctly
+ signal prev_rcv_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '1');
begin
clk <= not clk after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -162,7 +171,8 @@ begin
proc_dp_gen_block_data(c_nof_block_per_sync,
c_usr_block_size,
c_gap_size,
- g_usr_nof_words, -- apply throttle at generator
+ -- apply throttle at generator
+ g_usr_nof_words,
g_phy_nof_words,
rst,
clk,
@@ -174,10 +184,13 @@ begin
-- Verify the data path output data
proc_dp_verify_data("rcv_dat",
- 1, -- c_ready_latency, any value > 0 suits here
+ -- c_ready_latency, any value > 0 suits here
+ 1,
clk,
- sl1, -- verify_en
- sl1, -- out_ready
+ -- verify_en
+ sl1,
+ -- out_ready
+ sl1,
rcv_val,
rcv_dat,
prev_rcv_dat);
@@ -331,7 +344,8 @@ begin
rcv_throttle_val <= rcv_pack_val;
rcv_throttle_sof <= rcv_pack_sof;
rcv_throttle_eof <= rcv_pack_eof;
- end generate; -- gen_valid_support
+ -- gen_valid_support
+ end generate;
no_valid_support : if c_phy_link_valid_support = false generate
-- The u_transceiver_link will not pass on the phy_tx_val to phy_rx_val.
@@ -363,12 +377,14 @@ begin
gen_xmt_pacer : if g_usr_nof_words > g_phy_nof_words generate
-- map sl, slv to record
- xmt_pace_sosi.data(g_phy_dat_w - 1 downto 0) <= xmt_pace_dat; -- SOSI
+ -- SOSI
+ xmt_pace_sosi.data(g_phy_dat_w - 1 downto 0) <= xmt_pace_dat;
xmt_pace_sosi.valid <= xmt_pace_val(0);
xmt_pace_sosi.sop <= xmt_pace_sof(0);
xmt_pace_sosi.eop <= xmt_pace_eof(0);
- phy_tx_dat <= phy_tx_sosi.data(g_phy_dat_w - 1 downto 0); -- SOSI
+ -- SOSI
+ phy_tx_dat <= phy_tx_sosi.data(g_phy_dat_w - 1 downto 0);
phy_tx_val <= phy_tx_sosi.valid;
u_fifo_fill : entity work.dp_fifo_fill
@@ -387,9 +403,11 @@ begin
port map (
rst => rst,
clk => clk,
- snk_out => OPEN, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out => OPEN,
snk_in => xmt_pace_sosi,
- src_in => c_dp_siso_rdy, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => c_dp_siso_rdy,
src_out => phy_tx_sosi
);
end generate;
@@ -400,17 +418,21 @@ begin
rcv_throttle_val <= rcv_pack_val;
rcv_throttle_sof <= rcv_pack_sof;
rcv_throttle_eof <= rcv_pack_eof;
- end generate; -- no_rcv_throttle
+ -- no_rcv_throttle
+ end generate;
gen_rcv_throttle : if g_usr_nof_words > g_phy_nof_words generate
-- map sl, slv to record
- rcv_pack_sosi.data(g_phy_dat_w - 1 downto 0) <= rcv_pack_dat; -- SOSI
+ -- SOSI
+ rcv_pack_sosi.data(g_phy_dat_w - 1 downto 0) <= rcv_pack_dat;
rcv_pack_sosi.valid <= rcv_pack_val;
rcv_pack_sosi.sop <= rcv_pack_sof;
rcv_pack_sosi.eop <= rcv_pack_eof;
- rcv_fifo_rd_siso.ready <= rcv_fifo_rd_req; -- SISO
- rcv_fifo_rd_dat <= rcv_fifo_rd_sosi.data(g_phy_dat_w - 1 downto 0); -- SOSI
+ -- SISO
+ rcv_fifo_rd_siso.ready <= rcv_fifo_rd_req;
+ -- SOSI
+ rcv_fifo_rd_dat <= rcv_fifo_rd_sosi.data(g_phy_dat_w - 1 downto 0);
rcv_fifo_rd_val <= rcv_fifo_rd_sosi.valid;
rcv_fifo_rd_sof <= rcv_fifo_rd_sosi.sop;
rcv_fifo_rd_eof <= rcv_fifo_rd_sosi.eop;
@@ -431,10 +453,12 @@ begin
port map (
rst => rst,
clk => clk,
- snk_out => OPEN, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out => OPEN,
snk_in => rcv_pack_sosi,
usedw => OPEN,
- src_in => rcv_fifo_rd_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => rcv_fifo_rd_siso,
src_out => rcv_fifo_rd_sosi
);
@@ -468,8 +492,10 @@ begin
out_sof => rcv_throttle_sof,
out_eof => rcv_throttle_eof
);
- end generate; -- gen_rcv_throttle
- end generate; -- no_valid_support
+ -- gen_rcv_throttle
+ end generate;
+ -- no_valid_support
+ end generate;
------------------------------------------------------------------------------
-- RECEIVER
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
index f5bfc3ebe3ed4aac611671101f78a9e9cebe7082..2f3a434a6b71e28b291a92b2edb330af8c39fa25 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
@@ -39,11 +39,15 @@ use work.tb_dp_pkg.all;
entity tb_dp_pad_insert_remove is
generic (
g_data_w : natural := 16;
- g_symbol_w : natural := 8; -- g_data_w/g_symbol_w must be an integer
+ -- g_data_w/g_symbol_w must be an integer
+ g_symbol_w : natural := 8;
g_nof_symbols : natural := 21;
- g_nof_padding : natural := 2; -- must be > 0 and <= g_data_w/g_symbol_w
- g_in_en : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
- g_out_ready : t_dp_flow_control_enum := e_active -- always e_active, e_random or e_pulse flow control
+ -- must be > 0 and <= g_data_w/g_symbol_w
+ g_nof_padding : natural := 2;
+ -- always e_active, e_random or e_pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_active;
+ -- always e_active, e_random or e_pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_active
);
end tb_dp_pad_insert_remove;
@@ -57,7 +61,8 @@ architecture tb of tb_dp_pad_insert_remove is
constant c_nof_repeat : natural := 100;
constant c_bsn_w : natural := 16;
constant c_symbol_init : natural := 0;
- constant c_symbol_mod : integer := 2**g_symbol_w; -- used to avoid TO_UVEC warning for smaller g_symbol_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ -- used to avoid TO_UVEC warning for smaller g_symbol_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ constant c_symbol_mod : integer := 2**g_symbol_w;
constant c_channel_init : integer := 0;
constant c_err_init : natural := 0;
constant c_sync_period : natural := 7;
@@ -68,8 +73,10 @@ architecture tb of tb_dp_pad_insert_remove is
signal clk : std_logic := '1';
signal rst : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -82,7 +89,8 @@ architecture tb of tb_dp_pad_insert_remove is
signal prev_out_ready : std_logic_vector(0 to c_rl);
signal prev_out_data : std_logic_vector(g_data_w - 1 downto 0);
- signal prev_out_bsn : std_logic_vector(c_bsn_w - 1 downto 0) := (others => '1'); -- = -1
+ -- = -1
+ signal prev_out_bsn : std_logic_vector(c_bsn_w - 1 downto 0) := (others => '1');
signal prev_out_channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0) := TO_SVEC(c_channel_init - 1, c_dp_stream_channel_w);
signal prev_out_err : std_logic_vector(c_dp_stream_error_w - 1 downto 0) := TO_SVEC(c_err_init - 1, c_dp_stream_error_w);
signal expected_out_bsn : std_logic_vector(c_bsn_w - 1 downto 0);
@@ -114,7 +122,8 @@ architecture tb of tb_dp_pad_insert_remove is
signal pad_channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0);
signal pad_err : std_logic_vector(c_dp_stream_error_w - 1 downto 0);
- signal out_siso : t_dp_siso := c_dp_siso_hold; -- default xon = '1' is needed for proc_dp_gen_block_data()
+ -- default xon = '1' is needed for proc_dp_gen_block_data()
+ signal out_siso : t_dp_siso := c_dp_siso_hold;
signal out_sosi : t_dp_sosi;
signal out_data : std_logic_vector(g_data_w - 1 downto 0);
signal out_bsn : std_logic_vector(c_bsn_w - 1 downto 0);
@@ -167,7 +176,8 @@ begin
-- Begin of stimuli
for R in 0 to c_nof_repeat - 1 loop
- v_sync := sel_a_b(R mod c_sync_period = c_sync_offset, '1', '0'); -- v_bsn = R
+ -- v_bsn = R
+ v_sync := sel_a_b(R mod c_sync_period = c_sync_offset, '1', '0');
proc_dp_gen_block_data(c_rl, true, g_data_w, g_symbol_w, v_symbol, 0, 0, g_nof_symbols, v_channel, v_err, v_sync, TO_DP_BSN(R), clk, in_en, in_siso, in_sosi);
v_bsn := INCR_UVEC(v_bsn, 1);
v_symbol := (v_symbol + g_nof_symbols) mod c_symbol_mod;
@@ -181,7 +191,8 @@ begin
expected_out_channel <= TO_UVEC(v_channel - 1, c_dp_stream_channel_w);
expected_out_err <= TO_UVEC(v_err - 1, c_dp_stream_error_w);
- proc_common_wait_some_cycles(clk, 50); -- depends on stream control
+ -- depends on stream control
+ proc_common_wait_some_cycles(clk, 50);
verify_done <= '1';
proc_common_wait_some_cycles(clk, 1);
verify_done <= '0';
@@ -194,11 +205,14 @@ begin
-- DATA VERIFICATION
------------------------------------------------------------------------------
- verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1'; -- verify enable after first output sop
+ -- verify enable after first output sop
+ verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1';
-- SOSI control
- proc_dp_verify_valid(c_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_val); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_gap_invalid(clk, out_val, out_sop, out_eop, out_gap); -- Verify that the output valid is low between blocks from eop to sop
+ -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_valid(c_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_val);
+ -- Verify that the output valid is low between blocks from eop to sop
+ proc_dp_verify_gap_invalid(clk, out_val, out_sop, out_eop, out_gap);
-- SOSI data
-- . verify that the output is incrementing symbols, like the input stimuli
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
index aec011b91bd00c5ee57c1657d886a3fb050e7e97..0e01074caf0ac73de7cd379912b5dbffc863c676 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
@@ -37,17 +37,25 @@ architecture tb of tb_dp_pipeline is
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT ready latency
- constant c_dut_latency : natural := 1; -- fixed 1 for dp_pipeline
- constant c_tx_latency : natural := c_dut_latency; -- TX ready latency of TB
- constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ -- fixed 1 for dp_pipeline
+ constant c_dut_latency : natural := 1;
+ -- TX ready latency of TB
+ constant c_tx_latency : natural := c_dut_latency;
+ -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0);
constant c_tx_offset_sop : natural := 3;
- constant c_tx_period_sop : natural := 7; -- sop in data valid cycle 3, 10, 17, ...
- constant c_tx_offset_eop : natural := 5; -- eop in data valid cycle 5, 12, 19, ...
+ -- sop in data valid cycle 3, 10, 17, ...
+ constant c_tx_period_sop : natural := 7;
+ -- eop in data valid cycle 5, 12, 19, ...
+ constant c_tx_offset_eop : natural := 5;
constant c_tx_period_eop : natural := c_tx_period_sop;
- constant c_tx_offset_sync : natural := 3; -- sync in data valid cycle 3, 20, 37, ...
+ -- sync in data valid cycle 3, 20, 37, ...
+ constant c_tx_offset_sync : natural := 3;
constant c_tx_period_sync : natural := 17;
- constant c_rx_latency : natural := c_dut_latency; -- RX ready latency from DUT
- constant c_verify_en_wait : natural := 4 + g_pipeline; -- wait some cycles before asserting verify enable
+ -- RX ready latency from DUT
+ constant c_rx_latency : natural := c_dut_latency;
+ -- wait some cycles before asserting verify enable
+ constant c_verify_en_wait : natural := 4 + g_pipeline;
constant c_random_w : natural := 19;
@@ -117,7 +125,8 @@ begin
proc_dp_verify_en(c_verify_en_wait, rst, clk, sync, verify_en);
proc_dp_verify_data("out_sosi.data", c_rx_latency, clk, verify_en, out_ready, out_val, out_data, prev_out_data);
proc_dp_verify_valid(c_rx_latency, clk, verify_en, out_ready, prev_out_ready, out_val);
- proc_dp_verify_sop_and_eop(c_rx_latency, false, clk, out_val, out_val, out_sop, out_eop, hold_out_sop); -- Verify that sop and eop come in pairs, no check on valid between eop and sop
+ -- Verify that sop and eop come in pairs, no check on valid between eop and sop
+ proc_dp_verify_sop_and_eop(c_rx_latency, false, clk, out_val, out_val, out_sop, out_eop, hold_out_sop);
proc_dp_verify_ctrl(c_tx_offset_sync, c_tx_period_sync, "sync", clk, verify_en, out_data, out_val, out_sync);
proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", clk, verify_en, out_data, out_val, out_sop);
proc_dp_verify_ctrl(c_tx_offset_eop, c_tx_period_eop, "eop", clk, verify_en, out_data, out_val, out_eop);
@@ -130,15 +139,19 @@ begin
------------------------------------------------------------------------------
-- map sl, slv to record
- in_ready <= in_siso.ready; -- SISO
- in_sosi.data(c_dp_data_w - 1 downto 0) <= in_data; -- SOSI
+ -- SISO
+ in_ready <= in_siso.ready;
+ -- SOSI
+ in_sosi.data(c_dp_data_w - 1 downto 0) <= in_data;
in_sosi.sync <= in_sync;
in_sosi.valid <= in_val;
in_sosi.sop <= in_sop;
in_sosi.eop <= in_eop;
- out_siso.ready <= out_ready; -- SISO
- out_data <= out_sosi.data(c_dp_data_w - 1 downto 0); -- SOSI
+ -- SISO
+ out_siso.ready <= out_ready;
+ -- SOSI
+ out_data <= out_sosi.data(c_dp_data_w - 1 downto 0);
out_sync <= out_sosi.sync;
out_val <= out_sosi.valid;
out_sop <= out_sosi.sop;
@@ -151,9 +164,11 @@ begin
port map (
rst => rst,
clk => clk,
- snk_out => in_siso, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out => in_siso,
snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => out_siso,
src_out => out_sosi
);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
index 87366a33880b4f7b5a43161f5a3e0912711d917b..e30f518a8e4dac8fb041ec5c8f11a578aed009a8 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
@@ -38,10 +38,14 @@ use dp_lib.tb_dp_pkg.all;
entity tb_dp_pipeline_ready is
generic (
- g_in_en : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
- g_out_ready : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
- g_in_latency : natural := 1; -- >= 0
- g_out_latency : natural := 0; -- >= 0
+ -- always active, random or pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_random;
+ -- always active, random or pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_random;
+ -- >= 0
+ g_in_latency : natural := 1;
+ -- >= 0
+ g_out_latency : natural := 0;
g_nof_repeat : natural := 50
);
end tb_dp_pipeline_ready;
@@ -50,7 +54,8 @@ architecture tb of tb_dp_pipeline_ready is
constant c_data_w : natural := 16;
constant c_rl : natural := 1;
constant c_data_init : integer := 0;
- constant c_frame_len_init : natural := 1; -- >= 1
+ -- >= 1
+ constant c_frame_len_init : natural := 1;
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 7;
constant c_sync_period : natural := 7;
@@ -61,8 +66,10 @@ architecture tb of tb_dp_pipeline_ready is
signal rst : std_logic := '1';
-- Flow control
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -74,7 +81,8 @@ architecture tb of tb_dp_pipeline_ready is
signal adapt_siso : t_dp_siso;
signal adapt_sosi : t_dp_sosi;
- signal out_siso : t_dp_siso := c_dp_siso_hold; -- ready='0', xon='1'
+ -- ready='0', xon='1'
+ signal out_siso : t_dp_siso := c_dp_siso_hold;
signal out_sosi : t_dp_sosi;
-- Verification
@@ -170,16 +178,23 @@ begin
------------------------------------------------------------------------------
-- Verification logistics
- verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1'; -- enable verify after first output sop
+ -- enable verify after first output sop
+ verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1';
count_eop <= count_eop + 1 when rising_edge(clk) and out_sosi.eop = '1' and((g_out_latency > 0) or
- (g_out_latency = 0 and out_siso.ready = '1')); -- count number of output eop
- verify_done <= '1' when rising_edge(clk) and count_eop = g_nof_repeat; -- signal verify done after g_nof_repeat frames
+ -- count number of output eop
+ (g_out_latency = 0 and out_siso.ready = '1'));
+ -- signal verify done after g_nof_repeat frames
+ verify_done <= '1' when rising_edge(clk) and count_eop = g_nof_repeat;
-- Actual verification of the output streams
- proc_dp_verify_data("out_sosi.data", g_out_latency, clk, verify_en, out_siso.ready, out_sosi.valid, out_data, prev_out_data); -- Verify that the output is incrementing data, like the input stimuli
- proc_dp_verify_valid(g_out_latency, clk, verify_en, out_siso.ready, prev_out_ready, out_sosi.valid); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_sop_and_eop(g_out_latency, clk, out_siso.ready, out_sosi.valid, out_sosi.sop, out_sosi.eop, hold_out_sop); -- Verify that sop and eop come in pairs
- proc_dp_verify_value(e_equal, clk, verify_done, expected_out_data, prev_out_data); -- Verify that the stimuli have been applied at all
+ -- Verify that the output is incrementing data, like the input stimuli
+ proc_dp_verify_data("out_sosi.data", g_out_latency, clk, verify_en, out_siso.ready, out_sosi.valid, out_data, prev_out_data);
+ -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_valid(g_out_latency, clk, verify_en, out_siso.ready, prev_out_ready, out_sosi.valid);
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(g_out_latency, clk, out_siso.ready, out_sosi.valid, out_sosi.sop, out_sosi.eop, hold_out_sop);
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done, expected_out_data, prev_out_data);
proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en, out_sosi.sync, out_sosi.sop, out_sosi.bsn);
-- Monitoring
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
index 3cb638a976fa37e0b8803b2ae627751a143a2cde..08a32a48635e2a95bec7716b1b7409b6346bc3a4 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
@@ -53,7 +53,8 @@ package tb_dp_pkg is
-- > run 400 us
------------------------------------------------------------------------------
- constant clk_period : time := 10 ns; -- 100 MHz
+ -- 100 MHz
+ constant clk_period : time := 10 ns;
constant c_dp_sync_interval : natural := 3000;
constant c_dp_test_interval : natural := 100;
constant c_dp_nof_toggle : natural := 40;
@@ -64,12 +65,16 @@ package tb_dp_pkg is
-- . c_dp_data_w > c_dp_stream_empty_w
-- . c_dp_data_w > c_dp_stream_channel_w
-- . c_dp_data_w > c_dp_stream_error_w
- constant c_dp_data_w : natural := c_word_w; -- =32, choose wide enough to avoid out_data wrap around issue for p_verify
- constant c_dp_bsn_w : natural := c_dp_data_w; -- c_dp_stream_bsn_w;
+ -- =32, choose wide enough to avoid out_data wrap around issue for p_verify
+ constant c_dp_data_w : natural := c_word_w;
+ -- c_dp_stream_bsn_w;
+ constant c_dp_bsn_w : natural := c_dp_data_w;
constant c_dp_empty_w : natural := c_dp_stream_empty_w;
constant c_dp_channel_w : natural := c_dp_stream_channel_w;
- constant c_dp_channel_user_w : natural := c_dp_stream_channel_w / 2; -- support some bits for mux input user streams channel widths
- constant c_dp_channel_mux_w : natural := (c_dp_stream_channel_w + 1) / 2; -- support rest bits for the nof input ports of a mux
+ -- support some bits for mux input user streams channel widths
+ constant c_dp_channel_user_w : natural := c_dp_stream_channel_w / 2;
+ -- support rest bits for the nof input ports of a mux
+ constant c_dp_channel_mux_w : natural := (c_dp_stream_channel_w + 1) / 2;
constant c_dp_error_w : natural := c_dp_stream_error_w;
type t_dp_data_arr is array (natural range <>) of std_logic_vector(c_dp_data_w - 1 downto 0);
@@ -103,7 +108,8 @@ package tb_dp_pkg is
type t_dp_flow_control_enum_arr is array (natural range <>) of t_dp_flow_control_enum;
- constant c_dp_flow_control_enum_arr : t_dp_flow_control_enum_arr := (e_active, e_random, e_pulse); -- array all possible values that can be iterated over
+ -- array all possible values that can be iterated over
+ constant c_dp_flow_control_enum_arr : t_dp_flow_control_enum_arr := (e_active, e_random, e_pulse);
------------------------------------------------------------------------------
-- Stream source functions
@@ -126,47 +132,77 @@ package tb_dp_pkg is
signal cnt_dat : inout std_logic_vector);
-- Block data generator with ready flow control and symbols counter
- procedure proc_dp_gen_block_data(constant c_ready_latency : in natural; -- 0, 1 are supported by proc_dp_stream_ready_latency()
- constant c_use_data : in boolean; -- when TRUE use data field, else use re, im fields, and keep unused fields at 'X'
- constant c_data_w : in natural; -- data width for the data, re and im fields
- constant c_symbol_w : in natural; -- c_data_w/c_symbol_w must be an integer
- constant c_symbol_init : in natural; -- init counter for symbols in data field
- constant c_symbol_re_init : in natural; -- init counter for symbols in re field
- constant c_symbol_im_init : in natural; -- init counter for symbols in im field
- constant c_nof_symbols : in natural; -- nof symbols per frame for the data, re and im fields
- constant c_channel : in natural; -- channel field
- constant c_error : in natural; -- error field
- constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
- constant c_bsn : in std_logic_vector; -- bsn field
+ -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ procedure proc_dp_gen_block_data(constant c_ready_latency : in natural;
+ -- when TRUE use data field, else use re, im fields, and keep unused fields at 'X'
+ constant c_use_data : in boolean;
+ -- data width for the data, re and im fields
+ constant c_data_w : in natural;
+ -- c_data_w/c_symbol_w must be an integer
+ constant c_symbol_w : in natural;
+ -- init counter for symbols in data field
+ constant c_symbol_init : in natural;
+ -- init counter for symbols in re field
+ constant c_symbol_re_init : in natural;
+ -- init counter for symbols in im field
+ constant c_symbol_im_init : in natural;
+ -- nof symbols per frame for the data, re and im fields
+ constant c_nof_symbols : in natural;
+ -- channel field
+ constant c_channel : in natural;
+ -- error field
+ constant c_error : in natural;
+ -- when '1' issue sync pulse during this block
+ constant c_sync : in std_logic;
+ -- bsn field
+ constant c_bsn : in std_logic_vector;
signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ -- when '0' then no valid output even when src_in is ready
+ signal in_en : in std_logic;
signal src_in : in t_dp_siso;
signal src_out : out t_dp_sosi);
-- Increment only sosi.data, keep complex re,im = 0
- procedure proc_dp_gen_block_data(constant c_data_w : in natural; -- data width for the data field
- constant c_symbol_init : in natural; -- init counter for the data in the data field
- constant c_nof_symbols : in natural; -- nof symbols = nof data per frame for the data fields
- constant c_channel : in natural; -- channel field
- constant c_error : in natural; -- error field
- constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
- constant c_bsn : in std_logic_vector; -- bsn field
+ -- data width for the data field
+ procedure proc_dp_gen_block_data(constant c_data_w : in natural;
+ -- init counter for the data in the data field
+ constant c_symbol_init : in natural;
+ -- nof symbols = nof data per frame for the data fields
+ constant c_nof_symbols : in natural;
+ -- channel field
+ constant c_channel : in natural;
+ -- error field
+ constant c_error : in natural;
+ -- when '1' issue sync pulse during this block
+ constant c_sync : in std_logic;
+ -- bsn field
+ constant c_bsn : in std_logic_vector;
signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ -- when '0' then no valid output even when src_in is ready
+ signal in_en : in std_logic;
signal src_in : in t_dp_siso;
signal src_out : out t_dp_sosi);
-- Increment only sosi.re, im, keep data = 0
- procedure proc_dp_gen_block_complex(constant c_data_w : in natural; -- data width for the re, im field
- constant c_symbol_re_init : in natural; -- init counter for symbols in re field
- constant c_symbol_im_init : in natural; -- init counter for symbols in im field
- constant c_nof_symbols : in natural; -- nof symbols = nof data per frame for the data fields
- constant c_channel : in natural; -- channel field
- constant c_error : in natural; -- error field
- constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
- constant c_bsn : in std_logic_vector; -- bsn field
+ -- data width for the re, im field
+ procedure proc_dp_gen_block_complex(constant c_data_w : in natural;
+ -- init counter for symbols in re field
+ constant c_symbol_re_init : in natural;
+ -- init counter for symbols in im field
+ constant c_symbol_im_init : in natural;
+ -- nof symbols = nof data per frame for the data fields
+ constant c_nof_symbols : in natural;
+ -- channel field
+ constant c_channel : in natural;
+ -- error field
+ constant c_error : in natural;
+ -- when '1' issue sync pulse during this block
+ constant c_sync : in std_logic;
+ -- bsn field
+ constant c_bsn : in std_logic_vector;
signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ -- when '0' then no valid output even when src_in is ready
+ signal in_en : in std_logic;
signal src_in : in t_dp_siso;
signal src_out : out t_dp_sosi);
@@ -174,7 +210,8 @@ package tb_dp_pkg is
procedure proc_dp_stream_ready_latency(constant c_latency : in natural;
signal clk : in std_logic;
signal ready : in std_logic;
- signal in_en : in std_logic; -- when '1' then active output when ready
+ -- when '1' then active output when ready
+ signal in_en : in std_logic;
constant c_sync : in std_logic;
constant c_valid : in std_logic;
constant c_sop : in std_logic;
@@ -191,12 +228,14 @@ package tb_dp_pkg is
function func_dp_data_incr(c_data_w, c_symbol_w : natural; data : std_logic_vector) return std_logic_vector;
-- Generate a counter data with valid
- procedure proc_dp_gen_data(constant c_ready_latency : in natural; -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ procedure proc_dp_gen_data(constant c_ready_latency : in natural;
constant c_data_w : in natural;
constant c_data_init : in natural;
signal rst : in std_logic;
signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ -- when '0' then no valid output even when src_in is ready
+ signal in_en : in std_logic;
signal src_in : in t_dp_siso;
signal src_out : out t_dp_sosi);
@@ -212,15 +251,18 @@ package tb_dp_pkg is
signal src_out : out t_dp_sosi);
-- Generate a frame with symbols counter
- procedure proc_dp_gen_frame(constant c_ready_latency : in natural; -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ procedure proc_dp_gen_frame(constant c_ready_latency : in natural;
constant c_data_w : in natural;
- constant c_symbol_w : in natural; -- c_data_w/c_symbol_w must be an integer
+ -- c_data_w/c_symbol_w must be an integer
+ constant c_symbol_w : in natural;
constant c_symbol_init : in natural;
constant c_nof_symbols : in natural;
constant c_bsn : in natural;
constant c_sync : in std_logic;
signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ -- when '0' then no valid output even when src_in is ready
+ signal in_en : in std_logic;
signal src_in : in t_dp_siso;
signal src_out : out t_dp_sosi);
@@ -323,15 +365,20 @@ package tb_dp_pkg is
-- Verify output global and local BSN
-- . incrementing or replicated global BSN
-- . incrementing local BSN that starts at 1
- procedure proc_dp_verify_bsn(constant c_use_local_bsn : in boolean; -- use local BSN or only use global BSN
- constant c_global_bsn_increment : in positive; -- increment per global BSN
- constant c_nof_replicated_global_bsn : in positive; -- number of replicated global BSN
- constant c_block_per_sync : in positive; -- of sop/eop blocks per sync interval
+ -- use local BSN or only use global BSN
+ procedure proc_dp_verify_bsn(constant c_use_local_bsn : in boolean;
+ -- increment per global BSN
+ constant c_global_bsn_increment : in positive;
+ -- number of replicated global BSN
+ constant c_nof_replicated_global_bsn : in positive;
+ -- of sop/eop blocks per sync interval
+ constant c_block_per_sync : in positive;
signal clk : in std_logic;
signal out_sync : in std_logic;
signal out_sop : in std_logic;
signal out_bsn : in std_logic_vector;
- signal verify_en : inout std_logic; -- initialize '0', becomes '1' when bsn verification starts
+ -- initialize '0', becomes '1' when bsn verification starts
+ signal verify_en : inout std_logic;
signal cnt_replicated_global_bsn : inout natural;
signal prev_out_bsn_global : inout std_logic_vector;
signal prev_out_bsn_local : inout std_logic_vector);
@@ -367,7 +414,8 @@ package tb_dp_pkg is
signal clk : in std_logic;
signal verify_en : in std_logic;
signal out_ready : in std_logic;
- signal out_val : in std_logic; -- by using sop or eop proc_dp_verify_data() can also be used to verify other SOSI fields like bsn, error, channel, empty
+ -- by using sop or eop proc_dp_verify_data() can also be used to verify other SOSI fields like bsn, error, channel, empty
+ signal out_val : in std_logic;
signal out_data : in std_logic_vector;
signal prev_out_data : inout std_logic_vector);
@@ -445,8 +493,10 @@ package tb_dp_pkg is
procedure proc_dp_verify_sosi_equal(constant c_str : in string;
signal clk : in std_logic;
signal verify_en : in std_logic;
- signal dut_sosi : in t_dp_sosi_integer; -- use func_dp_stream_slv_to_integer for conversion
- signal exp_sosi : in t_dp_sosi_integer); -- use func_dp_stream_slv_to_integer for conversion
+ -- use func_dp_stream_slv_to_integer for conversion
+ signal dut_sosi : in t_dp_sosi_integer;
+ -- use func_dp_stream_slv_to_integer for conversion
+ signal exp_sosi : in t_dp_sosi_integer);
procedure proc_dp_verify_sosi_equal(constant c_use_complex : in boolean;
signal dut_sosi : in t_dp_sosi;
@@ -476,8 +526,10 @@ package tb_dp_pkg is
signal verify_en : in std_logic;
signal sync : in std_logic;
signal sop : in std_logic;
- bsn : in natural; -- for reporting
- expected_bsn : in natural; -- for reporting
+ -- for reporting
+ bsn : in natural;
+ -- for reporting
+ expected_bsn : in natural;
expected_sync : in std_logic);
-- Note: A SIGNAL IN can only connect a SIGNAL. Therefore define IN as
-- default (= CONSTANT) instead of SIGNAL to be able to connect
@@ -507,7 +559,8 @@ package tb_dp_pkg is
procedure proc_dp_verify_sync(constant c_start_bsn : in natural;
constant c_sync_period : in natural;
constant c_block_size : in natural;
- constant c_bsn_is_rsn : in boolean; -- increment BSN by 1 or by c_block_size for RSN
+ -- increment BSN by 1 or by c_block_size for RSN
+ constant c_bsn_is_rsn : in boolean;
signal clk : in std_logic;
signal verify_en : in std_logic;
signal sync : in std_logic;
@@ -543,8 +596,10 @@ package tb_dp_pkg is
signal hold_sop : inout std_logic);
procedure proc_dp_verify_block_size(constant c_ready_latency : in natural;
- signal alt_size : in natural; -- alternative size (eg. use exp_size'last_value)
- signal exp_size : in natural; -- expected size
+ -- alternative size (eg. use exp_size'last_value)
+ signal alt_size : in natural;
+ -- expected size
+ signal exp_size : in natural;
signal clk : in std_logic;
signal out_ready : in std_logic;
signal out_val : in std_logic;
@@ -553,7 +608,8 @@ package tb_dp_pkg is
signal cnt_size : inout natural);
procedure proc_dp_verify_block_size(constant c_ready_latency : in natural;
- signal exp_size : in natural; -- expected size
+ -- expected size
+ signal exp_size : in natural;
signal clk : in std_logic;
signal out_ready : in std_logic;
signal out_val : in std_logic;
@@ -561,15 +617,18 @@ package tb_dp_pkg is
signal out_eop : in std_logic;
signal cnt_size : inout natural);
- procedure proc_dp_verify_block_size(signal alt_size : in natural; -- alternative size (eg. use exp_size'last_value)
- signal exp_size : in natural; -- expected size
+ -- alternative size (eg. use exp_size'last_value)
+ procedure proc_dp_verify_block_size(signal alt_size : in natural;
+ -- expected size
+ signal exp_size : in natural;
signal clk : in std_logic;
signal out_val : in std_logic;
signal out_sop : in std_logic;
signal out_eop : in std_logic;
signal cnt_size : inout natural);
- procedure proc_dp_verify_block_size(signal exp_size : in natural; -- expected size
+ -- expected size
+ procedure proc_dp_verify_block_size(signal exp_size : in natural;
signal clk : in std_logic;
signal out_val : in std_logic;
signal out_sop : in std_logic;
@@ -581,7 +640,8 @@ package tb_dp_pkg is
signal in_val : in std_logic;
signal in_sop : in std_logic;
signal in_eop : in std_logic;
- signal out_gap : inout std_logic); -- declare initial gap signal = '1'
+ -- declare initial gap signal = '1'
+ signal out_gap : inout std_logic);
-- Verify the DUT output control (use for sop, eop)
procedure proc_dp_verify_ctrl(constant c_offset : in natural;
@@ -632,7 +692,8 @@ package body tb_dp_pkg is
cnt_sync <= '0';
cnt_val <= '0';
- cnt_dat <= (cnt_dat'range => '1'); -- -1, so first valid cnt_dat starts at 0
+ -- -1, so first valid cnt_dat starts at 0
+ cnt_dat <= (cnt_dat'range => '1');
-- allow some clock cycles before start after rst release
wait until rst = '0';
@@ -688,20 +749,33 @@ package body tb_dp_pkg is
-- . dependent on in_en and src_in.ready
-- . optional sync pulse at end of frame
------------------------------------------------------------------------------
- procedure proc_dp_gen_block_data(constant c_ready_latency : in natural; -- 0, 1 are supported by proc_dp_stream_ready_latency()
- constant c_use_data : in boolean; -- when TRUE use data field, else use re, im fields, and keep unused fields at 'X'
- constant c_data_w : in natural; -- data width for the data, re and im fields
- constant c_symbol_w : in natural; -- c_data_w/c_symbol_w must be an integer
- constant c_symbol_init : in natural; -- init counter for symbols in data field
- constant c_symbol_re_init : in natural; -- init counter for symbols in re field
- constant c_symbol_im_init : in natural; -- init counter for symbols in im field
- constant c_nof_symbols : in natural; -- nof symbols per frame for the data, re and im fields
- constant c_channel : in natural; -- channel field
- constant c_error : in natural; -- error field
- constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
- constant c_bsn : in std_logic_vector; -- bsn field
+ -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ procedure proc_dp_gen_block_data(constant c_ready_latency : in natural;
+ -- when TRUE use data field, else use re, im fields, and keep unused fields at 'X'
+ constant c_use_data : in boolean;
+ -- data width for the data, re and im fields
+ constant c_data_w : in natural;
+ -- c_data_w/c_symbol_w must be an integer
+ constant c_symbol_w : in natural;
+ -- init counter for symbols in data field
+ constant c_symbol_init : in natural;
+ -- init counter for symbols in re field
+ constant c_symbol_re_init : in natural;
+ -- init counter for symbols in im field
+ constant c_symbol_im_init : in natural;
+ -- nof symbols per frame for the data, re and im fields
+ constant c_nof_symbols : in natural;
+ -- channel field
+ constant c_channel : in natural;
+ -- error field
+ constant c_error : in natural;
+ -- when '1' issue sync pulse during this block
+ constant c_sync : in std_logic;
+ -- bsn field
+ constant c_bsn : in std_logic_vector;
signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ -- when '0' then no valid output even when src_in is ready
+ signal in_en : in std_logic;
signal src_in : in t_dp_siso;
signal src_out : out t_dp_sosi) is
constant c_nof_symbols_per_data : natural := c_data_w / c_symbol_w;
@@ -756,15 +830,23 @@ package body tb_dp_pkg is
end proc_dp_gen_block_data;
-- Increment only sosi.data, keep complex re,im = 0
- procedure proc_dp_gen_block_data(constant c_data_w : in natural; -- data width for the data field
- constant c_symbol_init : in natural; -- init counter for the data in the data field
- constant c_nof_symbols : in natural; -- nof symbols per frame for the data fields
- constant c_channel : in natural; -- channel field
- constant c_error : in natural; -- error field
- constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
- constant c_bsn : in std_logic_vector; -- bsn field
+ -- data width for the data field
+ procedure proc_dp_gen_block_data(constant c_data_w : in natural;
+ -- init counter for the data in the data field
+ constant c_symbol_init : in natural;
+ -- nof symbols per frame for the data fields
+ constant c_nof_symbols : in natural;
+ -- channel field
+ constant c_channel : in natural;
+ -- error field
+ constant c_error : in natural;
+ -- when '1' issue sync pulse during this block
+ constant c_sync : in std_logic;
+ -- bsn field
+ constant c_bsn : in std_logic_vector;
signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ -- when '0' then no valid output even when src_in is ready
+ signal in_en : in std_logic;
signal src_in : in t_dp_siso;
signal src_out : out t_dp_sosi) is
begin
@@ -772,16 +854,25 @@ package body tb_dp_pkg is
end proc_dp_gen_block_data;
-- Increment only sosi.re, im, keep data = 0
- procedure proc_dp_gen_block_complex(constant c_data_w : in natural; -- data width for the re, im field
- constant c_symbol_re_init : in natural; -- init counter for symbols in re field
- constant c_symbol_im_init : in natural; -- init counter for symbols in im field
- constant c_nof_symbols : in natural; -- nof symbols per frame for the data fields
- constant c_channel : in natural; -- channel field
- constant c_error : in natural; -- error field
- constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
- constant c_bsn : in std_logic_vector; -- bsn field
+ -- data width for the re, im field
+ procedure proc_dp_gen_block_complex(constant c_data_w : in natural;
+ -- init counter for symbols in re field
+ constant c_symbol_re_init : in natural;
+ -- init counter for symbols in im field
+ constant c_symbol_im_init : in natural;
+ -- nof symbols per frame for the data fields
+ constant c_nof_symbols : in natural;
+ -- channel field
+ constant c_channel : in natural;
+ -- error field
+ constant c_error : in natural;
+ -- when '1' issue sync pulse during this block
+ constant c_sync : in std_logic;
+ -- bsn field
+ constant c_bsn : in std_logic_vector;
signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ -- when '0' then no valid output even when src_in is ready
+ signal in_en : in std_logic;
signal src_in : in t_dp_siso;
signal src_out : out t_dp_sosi) is
begin
@@ -897,12 +988,14 @@ package body tb_dp_pkg is
-- PROCEDURE: Generate counter data with valid
-- . Output counter data dependent on in_en and src_in.ready
------------------------------------------------------------------------------
- procedure proc_dp_gen_data(constant c_ready_latency : in natural; -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ procedure proc_dp_gen_data(constant c_ready_latency : in natural;
constant c_data_w : in natural;
constant c_data_init : in natural;
signal rst : in std_logic;
signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ -- when '0' then no valid output even when src_in is ready
+ signal in_en : in std_logic;
signal src_in : in t_dp_siso;
signal src_out : out t_dp_sosi) is
variable v_data : std_logic_vector(c_data_w - 1 downto 0) := TO_UVEC(c_data_init, c_data_w);
@@ -930,7 +1023,8 @@ package body tb_dp_pkg is
constant c_data_max : in natural;
signal rst : in std_logic;
signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ -- when '0' then no valid output even when src_in is ready
+ signal in_en : in std_logic;
signal src_in : in t_dp_siso;
signal src_out : out t_dp_sosi) is
variable v_cnt : std_logic_vector(c_data_w - 1 downto 0) := TO_UVEC(c_data_init, c_data_w);
@@ -955,15 +1049,18 @@ package body tb_dp_pkg is
-- PROCEDURE: Generate a frame with symbols counter
-- . dependent on in_en and src_in.ready
------------------------------------------------------------------------------
- procedure proc_dp_gen_frame(constant c_ready_latency : in natural; -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ procedure proc_dp_gen_frame(constant c_ready_latency : in natural;
constant c_data_w : in natural;
- constant c_symbol_w : in natural; -- c_data_w/c_symbol_w must be an integer
+ -- c_data_w/c_symbol_w must be an integer
+ constant c_symbol_w : in natural;
constant c_symbol_init : in natural;
constant c_nof_symbols : in natural;
constant c_bsn : in natural;
constant c_sync : in std_logic;
signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ -- when '0' then no valid output even when src_in is ready
+ signal in_en : in std_logic;
signal src_in : in t_dp_siso;
signal src_out : out t_dp_sosi) is
constant c_nof_symbols_per_data : natural := c_data_w / c_symbol_w;
@@ -1047,7 +1144,8 @@ package body tb_dp_pkg is
signal tx_val : inout std_logic_vector;
signal out_data : out std_logic_vector;
signal out_val : out std_logic) is
- constant c_void : natural := sel_a_b(c_ready_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_ready_latency=0
+ -- used to avoid empty range VHDL warnings when c_ready_latency=0
+ constant c_void : natural := sel_a_b(c_ready_latency, 1, 0);
begin
-- TX data array for output ready latency [c_ready_latency], index [0] for zero latency combinatorial
tx_data(0) <= cnt_dat;
@@ -1808,15 +1906,20 @@ package body tb_dp_pkg is
-- The verify_en should initially be set to '0' and gets enabled when
-- sufficient BSN history is available to do the verification.
--
- procedure proc_dp_verify_bsn(constant c_use_local_bsn : in boolean; -- use local BSN or only use global BSN
- constant c_global_bsn_increment : in positive; -- increment per global BSN
- constant c_nof_replicated_global_bsn : in positive; -- number of replicated global BSN
- constant c_block_per_sync : in positive; -- of sop/eop blocks per sync interval
+ -- use local BSN or only use global BSN
+ procedure proc_dp_verify_bsn(constant c_use_local_bsn : in boolean;
+ -- increment per global BSN
+ constant c_global_bsn_increment : in positive;
+ -- number of replicated global BSN
+ constant c_nof_replicated_global_bsn : in positive;
+ -- of sop/eop blocks per sync interval
+ constant c_block_per_sync : in positive;
signal clk : in std_logic;
signal out_sync : in std_logic;
signal out_sop : in std_logic;
signal out_bsn : in std_logic_vector;
- signal verify_en : inout std_logic; -- initialize '0', becomes '1' when bsn verification starts
+ -- initialize '0', becomes '1' when bsn verification starts
+ signal verify_en : inout std_logic;
signal cnt_replicated_global_bsn : inout natural;
signal prev_out_bsn_global : inout std_logic_vector;
signal prev_out_bsn_local : inout std_logic_vector) is
@@ -1843,7 +1946,8 @@ package body tb_dp_pkg is
if out_sync = '1' then
prev_out_bsn_global <= out_bsn;
if unsigned(out_bsn) /= unsigned(prev_out_bsn_global) then
- verify_en <= '1'; -- wait until after last replicated global bsn
+ -- wait until after last replicated global bsn
+ verify_en <= '1';
cnt_replicated_global_bsn <= 0;
else
cnt_replicated_global_bsn <= cnt_replicated_global_bsn + 1;
@@ -1884,7 +1988,8 @@ package body tb_dp_pkg is
constant c_out_data_gap : in unsigned;
signal clk : in std_logic;
signal verify_en : in std_logic;
- signal out_ready : in std_logic; -- only needed when c_ready_latency = 0
+ -- only needed when c_ready_latency = 0
+ signal out_ready : in std_logic;
signal out_val : in std_logic;
signal out_data : in std_logic_vector;
signal prev_out_data : inout std_logic_vector) is
@@ -1896,16 +2001,22 @@ package body tb_dp_pkg is
-- for ready_latency = 0 out_val only indicates new data when it is confirmed by out_ready
if c_ready_latency /= 0 or (c_ready_latency = 0 and out_ready = '1') then
if c_out_data_max = 0 then
- prev_out_data <= out_data; -- no wrap detection
+ -- no wrap detection
+ prev_out_data <= out_data;
elsif unsigned(out_data) < c_out_data_max then
- prev_out_data <= out_data; -- no wrap
+ -- no wrap
+ prev_out_data <= out_data;
else
- prev_out_data <= TO_SVEC(-1, prev_out_data'length); -- do wrap
+ -- do wrap
+ prev_out_data <= TO_SVEC(-1, prev_out_data'length);
end if;
if verify_en = '1' then
- if unsigned(out_data) /= unsigned(prev_out_data) + 1 and -- check increment +1
- unsigned(out_data) /= unsigned(prev_out_data) + c_out_data_gap and -- increment +c_out_data_gap
- unsigned(out_data) /= unsigned(prev_out_data) + c_out_data_gap - c_out_data_max then -- increment +c_out_data_gap wrapped
+ -- check increment +1
+ if unsigned(out_data) /= unsigned(prev_out_data) + 1 and
+ -- increment +c_out_data_gap
+ unsigned(out_data) /= unsigned(prev_out_data) + c_out_data_gap and
+ -- increment +c_out_data_gap wrapped
+ unsigned(out_data) /= unsigned(prev_out_data) + c_out_data_gap - c_out_data_max then
report "DP : Wrong out_data " & c_str & " count" severity ERROR;
end if;
end if;
@@ -2006,7 +2117,8 @@ package body tb_dp_pkg is
signal out_data : in std_logic_vector;
signal out_empty : in std_logic_vector;
signal prev_out_data : inout std_logic_vector) is
- constant c_nof_symbols_per_data : natural := c_data_w / c_symbol_w; -- must be an integer
+ -- must be an integer
+ constant c_nof_symbols_per_data : natural := c_data_w / c_symbol_w;
constant c_empty_w : natural := ceil_log2(c_nof_symbols_per_data);
variable v_data : std_logic_vector(c_data_w - 1 downto 0);
variable v_symbol : std_logic_vector(c_symbol_w - 1 downto 0);
@@ -2022,7 +2134,8 @@ package body tb_dp_pkg is
if verify_en = '1' then
v_data := prev_out_data(c_data_w - 1 downto 0);
for I in 0 to c_nof_symbols_per_data - 1 loop
- v_data((I + 1) * c_symbol_w - 1 downto I * c_symbol_w) := INCR_UVEC(v_data((I + 1) * c_symbol_w - 1 downto I * c_symbol_w), c_nof_symbols_per_data); -- increment each symbol
+ -- increment each symbol
+ v_data((I + 1) * c_symbol_w - 1 downto I * c_symbol_w) := INCR_UVEC(v_data((I + 1) * c_symbol_w - 1 downto I * c_symbol_w), c_nof_symbols_per_data);
end loop;
if out_eop = '0' then
if unsigned(out_data) /= unsigned(v_data) then
@@ -2035,10 +2148,13 @@ package body tb_dp_pkg is
end if;
if v_empty > 0 then
-- adjust prev_out_data for potentially undefined empty symbols in out_data
- v_symbol := v_data((v_empty + 1) * c_symbol_w - 1 downto v_empty * c_symbol_w); -- last valid symbol
+ -- last valid symbol
+ v_symbol := v_data((v_empty + 1) * c_symbol_w - 1 downto v_empty * c_symbol_w);
for I in 0 to c_nof_symbols_per_data - 1 loop
- v_data((I + 1) * c_symbol_w - 1 downto I * c_symbol_w) := v_symbol; -- put the last valid symbol at the end of the v_data
- v_symbol := INCR_UVEC(v_symbol, -1); -- decrement each symbol towards the beginning of v_data
+ -- put the last valid symbol at the end of the v_data
+ v_data((I + 1) * c_symbol_w - 1 downto I * c_symbol_w) := v_symbol;
+ -- decrement each symbol towards the beginning of v_data
+ v_symbol := INCR_UVEC(v_symbol, -1);
end loop;
prev_out_data <= v_data;
end if;
@@ -2142,7 +2258,8 @@ package body tb_dp_pkg is
-- are treated in the same way in parallel to the SOSI data.
------------------------------------------------------------------------------
procedure proc_dp_verify_other_sosi(constant c_str : in string;
- constant c_exp_data : in std_logic_vector; -- use constant to support assignment via FUNCTION return value
+ -- use constant to support assignment via FUNCTION return value
+ constant c_exp_data : in std_logic_vector;
signal clk : in std_logic;
signal verify_en : in std_logic;
signal res_data : in std_logic_vector) is
@@ -2178,8 +2295,10 @@ package body tb_dp_pkg is
procedure proc_dp_verify_sosi_equal(constant c_str : in string;
signal clk : in std_logic;
signal verify_en : in std_logic;
- signal dut_sosi : in t_dp_sosi_integer; -- use func_dp_stream_slv_to_integer for conversion
- signal exp_sosi : in t_dp_sosi_integer) is -- use func_dp_stream_slv_to_integer for conversion
+ -- use func_dp_stream_slv_to_integer for conversion
+ signal dut_sosi : in t_dp_sosi_integer;
+ -- use func_dp_stream_slv_to_integer for conversion
+ signal exp_sosi : in t_dp_sosi_integer) is
begin
-- Use sosi integers, instead of sosi slv, for easier comparision. This
-- implies that only integer low part of sosi slv fields is checked, so
@@ -2353,8 +2472,10 @@ package body tb_dp_pkg is
signal verify_en : in std_logic;
signal sync : in std_logic;
signal sop : in std_logic;
- bsn : in natural; -- for reporting
- expected_bsn : in natural; -- for reporting
+ -- for reporting
+ bsn : in natural;
+ -- for reporting
+ expected_bsn : in natural;
expected_sync : in std_logic) is
begin
if rising_edge(clk) then
@@ -2380,14 +2501,17 @@ package body tb_dp_pkg is
-- . sync is defined such that it can only be active at sop
-- . assume that the sync occures priodically at bsn MOD c_sync_period = c_sync_offset
------------------------------------------------------------------------------
- procedure proc_dp_verify_sync(constant c_sync_period : in natural; -- BSN sync period
- constant c_sync_offset : in natural; -- BSN sync offset
+ -- BSN sync period
+ procedure proc_dp_verify_sync(constant c_sync_period : in natural;
+ -- BSN sync offset
+ constant c_sync_offset : in natural;
signal clk : in std_logic;
signal verify_en : in std_logic;
signal sync : in std_logic;
signal sop : in std_logic;
signal bsn : in std_logic_vector) is
- constant c_bsn_w : natural := sel_a_b(bsn'length > 31, 31, bsn'length); -- use maximally c_natural_w = 31 bit of BSN slv to allow calculations with integers
+ -- use maximally c_natural_w = 31 bit of BSN slv to allow calculations with integers
+ constant c_bsn_w : natural := sel_a_b(bsn'length > 31, 31, bsn'length);
variable v_bsn : natural := TO_UINT(bsn(c_bsn_w - 1 downto 0));
variable v_expected_sync : boolean;
begin
@@ -2405,9 +2529,12 @@ package body tb_dp_pkg is
-- dp_bsn_source_v2, dp_bsn_sync_scheduler.
-- . Use block sequence number (BSN) in dbg_expected_bsn.
------------------------------------------------------------------------------
- procedure proc_dp_verify_sync(constant c_start_bsn : in natural; -- BSN of first sync, start of fractional periods
- constant c_sync_period : in natural; -- number of sample per sync period
- constant c_block_size : in natural; -- number of sample per block
+ -- BSN of first sync, start of fractional periods
+ procedure proc_dp_verify_sync(constant c_start_bsn : in natural;
+ -- number of sample per sync period
+ constant c_sync_period : in natural;
+ -- number of sample per block
+ constant c_block_size : in natural;
signal clk : in std_logic;
signal verify_en : in std_logic;
signal sync : in std_logic;
@@ -2441,10 +2568,14 @@ package body tb_dp_pkg is
-- . support using block sequence number (BSN) in dbg_expected_bsn or using
-- raw samples sequence number (RSN) in dbg_expected_bsn
------------------------------------------------------------------------------
- procedure proc_dp_verify_sync(constant c_start_bsn : in natural; -- BSN of first sync, start of fractional periods
- constant c_sync_period : in natural; -- number of sample per sync period
- constant c_block_size : in natural; -- number of sample per block
- constant c_bsn_is_rsn : in boolean; -- increment BSN by 1 or by c_block_size for RSN
+ -- BSN of first sync, start of fractional periods
+ procedure proc_dp_verify_sync(constant c_start_bsn : in natural;
+ -- number of sample per sync period
+ constant c_sync_period : in natural;
+ -- number of sample per block
+ constant c_block_size : in natural;
+ -- increment BSN by 1 or by c_block_size for RSN
+ constant c_bsn_is_rsn : in boolean;
signal clk : in std_logic;
signal verify_en : in std_logic;
signal sync : in std_logic;
@@ -2454,14 +2585,21 @@ package body tb_dp_pkg is
signal dbg_nof_blk : out natural;
signal dbg_accumulate : out natural;
signal dbg_expected_bsn : out natural) is
- constant c_bsn_w : natural := sel_a_b(bsn'length > 31, 31, bsn'length); -- use maximally c_natural_w = 31 bit of BSN slv to allow calculations with integers
- constant c_nof_blk_min : natural := c_sync_period / c_block_size; -- minimum number of blocks in sync period
- constant c_extra : natural := c_sync_period mod c_block_size; -- number of extra samples in sync period
+ -- use maximally c_natural_w = 31 bit of BSN slv to allow calculations with integers
+ constant c_bsn_w : natural := sel_a_b(bsn'length > 31, 31, bsn'length);
+ -- minimum number of blocks in sync period
+ constant c_nof_blk_min : natural := c_sync_period / c_block_size;
+ -- number of extra samples in sync period
+ constant c_extra : natural := c_sync_period mod c_block_size;
variable v_bsn : natural := TO_UINT(bsn(c_bsn_w - 1 downto 0));
- variable v_expected_sync : boolean := false; -- default FALSE, e.g. when bsn < c_start_bsn is in the past
- variable v_expected_bsn : natural := c_start_bsn; -- BSN that is expected to have a sync, intialize with start BSN
- variable v_nof_blk : natural := c_nof_blk_min + 1; -- number of blocks in period, first sync period will be 1 block longer to achieve the fraction part
- variable v_accumulate : integer := c_block_size - c_extra; -- number of extra samples in period, first sync period will have v_accumulate more
+ -- default FALSE, e.g. when bsn < c_start_bsn is in the past
+ variable v_expected_sync : boolean := false;
+ -- BSN that is expected to have a sync, intialize with start BSN
+ variable v_expected_bsn : natural := c_start_bsn;
+ -- number of blocks in period, first sync period will be 1 block longer to achieve the fraction part
+ variable v_nof_blk : natural := c_nof_blk_min + 1;
+ -- number of extra samples in period, first sync period will have v_accumulate more
+ variable v_accumulate : integer := c_block_size - c_extra;
begin
-- Determine v_expected_sync
if c_extra = 0 then
@@ -2568,8 +2706,10 @@ package body tb_dp_pkg is
end proc_dp_verify_sop_and_eop;
procedure proc_dp_verify_block_size(constant c_ready_latency : in natural;
- signal alt_size : in natural; -- alternative size
- signal exp_size : in natural; -- expected size
+ -- alternative size
+ signal alt_size : in natural;
+ -- expected size
+ signal exp_size : in natural;
signal clk : in std_logic;
signal out_ready : in std_logic;
signal out_val : in std_logic;
@@ -2609,8 +2749,10 @@ package body tb_dp_pkg is
proc_dp_verify_block_size(c_ready_latency, exp_size, exp_size, clk, out_ready, out_val, out_sop, out_eop, cnt_size);
end proc_dp_verify_block_size;
- procedure proc_dp_verify_block_size(signal alt_size : in natural; -- alternative size
- signal exp_size : in natural; -- expected size
+ -- alternative size
+ procedure proc_dp_verify_block_size(signal alt_size : in natural;
+ -- expected size
+ signal exp_size : in natural;
signal clk : in std_logic;
signal out_val : in std_logic;
signal out_sop : in std_logic;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd b/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd
index f8137c37ce8e2eac48b0f108c61f2b6651f51a2f..1a58451ee6544cf02de96b5159a7a8fdc282ac71 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd
@@ -43,16 +43,20 @@ use work.tb_dp_pkg.all;
entity tb_dp_repack is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse;
+ -- always active, random or pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
g_in_dat_w : natural := 32;
g_in_nof_words : natural := 1;
g_pack_dat_w : natural := 8;
g_pack_nof_words : natural := 4;
g_nof_repeat : natural := 24;
- g_pkt_len : natural := 16; -- must be a multiple of g_in_nof_words
- g_pkt_gap : natural := 4 -- must be >= g_pack_nof_words
+ -- must be a multiple of g_in_nof_words
+ g_pkt_len : natural := 16;
+ -- must be >= g_pack_nof_words
+ g_pkt_gap : natural := 4
);
end tb_dp_repack;
@@ -67,17 +71,21 @@ architecture tb of tb_dp_repack is
constant c_data_max : unsigned(g_in_dat_w - 1 downto 0) := (others => '1');
constant c_data_init : integer := -1;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
- constant c_channel_init : integer := 5; -- fixed
+ -- fixed
+ constant c_channel_init : integer := 5;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal sl1 : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -96,7 +104,8 @@ architecture tb of tb_dp_repack is
signal prev_verify_snk_out : t_dp_siso;
signal verify_snk_out : t_dp_siso := c_dp_siso_rdy;
signal verify_snk_in : t_dp_sosi;
- signal verify_snk_in_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0); -- used to hold valid data for verify at verify_done
+ -- used to hold valid data for verify at verify_done
+ signal verify_snk_in_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0);
signal verify_data : std_logic_vector(g_in_dat_w - 1 downto 0);
signal prev_verify_snk_in : t_dp_sosi;
@@ -151,10 +160,12 @@ begin
for I in 0 to g_nof_repeat - 1 loop
-- Auto increment v_sosi field values for this packet
v_sosi.bsn := INCR_UVEC(v_sosi.bsn, 1);
- v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_sync_period) = c_sync_offset, '1', '0'); -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_sync_period) = c_sync_offset, '1', '0');
v_sosi.channel := INCR_UVEC(v_sosi.channel, 1);
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
v_sosi.err := INCR_UVEC(v_sosi.err, 1);
-- Send packet
@@ -171,11 +182,13 @@ begin
v_sosi.err := TO_DP_ERROR(c_err_init + g_nof_repeat - 1);
-- . account for g_pkt_len
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len - 1);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
expected_verify_snk_in <= v_sosi;
-- Signal end of stimuli
- proc_common_wait_some_cycles(clk, 100); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ proc_common_wait_some_cycles(clk, 100);
proc_common_gen_pulse(clk, verify_done);
proc_common_wait_some_cycles(clk, 50);
tb_end <= '1';
@@ -236,13 +249,15 @@ begin
in_val => stimuli_src_out.valid,
in_sof => stimuli_src_out.sop,
in_eof => stimuli_src_out.eop,
- in_sync => stimuli_src_out.sync, -- DP style sync at sof
+ -- DP style sync at sof
+ in_sync => stimuli_src_out.sync,
out_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
out_val => pack_src_out.valid,
out_sof => pack_src_out.sop,
out_eof => pack_src_out.eop,
- sof_sync => pack_src_out.sync -- DP style sync at sof, passes on in_sync
+ -- DP style sync at sof, passes on in_sync
+ sof_sync => pack_src_out.sync
);
------------------------------------------------------------------------------
@@ -266,13 +281,15 @@ begin
in_val => pack_src_out.valid,
in_sof => pack_src_out.sop,
in_eof => pack_src_out.eop,
- in_sync => pack_src_out.sync, -- DP style sync at sof
+ -- DP style sync at sof
+ in_sync => pack_src_out.sync,
out_dat => unpack_src_out.data(g_in_dat_w - 1 downto 0),
out_val => unpack_src_out.valid,
out_sof => unpack_src_out.sop,
out_eof => unpack_src_out.eop,
- sof_sync => unpack_src_out.sync -- DP style sync at sof, passes on in_sync
+ -- DP style sync at sof, passes on in_sync
+ sof_sync => unpack_src_out.sync
);
unpack_src_in <= verify_snk_out;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd b/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd
index 1fbc042d83c68b5f5e55817d62faab380e2ca0c7..01aba9efb76b4026d39ba6f1b38c8551bbb81d39 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd
@@ -51,19 +51,26 @@ use work.tb_dp_pkg.all;
entity tb_dp_repack_data is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- always e_active, e_random or e_pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ -- always e_active, e_random or e_pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
g_in_dat_w : natural := 8 * 42;
g_in_nof_words : natural := 1;
g_pack_dat_w : natural := 32;
g_pack_nof_words : natural := 11;
- g_in_bypass : boolean := true; -- can use TRUE when g_in_nof_words=1 or g_in_nof_words=g_out_nof_words
- g_pack_bypass : boolean := false; -- can use TRUE when g_out_nof_words=1 or g_in_nof_words=g_out_nof_words
- g_in_symbol_w : natural := 8; -- default 1 for snk_in.empty in nof bits, else use power of 2
- g_pack_symbol_w : natural := 8; -- default 1 for src_out.empty in nof bits, else use power of 2
+ -- can use TRUE when g_in_nof_words=1 or g_in_nof_words=g_out_nof_words
+ g_in_bypass : boolean := true;
+ -- can use TRUE when g_out_nof_words=1 or g_in_nof_words=g_out_nof_words
+ g_pack_bypass : boolean := false;
+ -- default 1 for snk_in.empty in nof bits, else use power of 2
+ g_in_symbol_w : natural := 8;
+ -- default 1 for src_out.empty in nof bits, else use power of 2
+ g_pack_symbol_w : natural := 8;
g_nof_repeat : natural := 10;
- g_pkt_len : natural := 1; -- if not a multiple of g_in_nof_words then the input stage flush creates gap between blocks
+ -- if not a multiple of g_in_nof_words then the input stage flush creates gap between blocks
+ g_pkt_len : natural := 1;
g_pkt_gap : natural := 0
);
end tb_dp_repack_data;
@@ -74,13 +81,16 @@ architecture tb of tb_dp_repack_data is
constant c_enable_repack_out : boolean := true;
-- dp_stream_stimuli
- constant c_stimuli_pulse_active : natural := 3; -- g_in_nof_words;
+ -- g_in_nof_words;
+ constant c_stimuli_pulse_active : natural := 3;
constant c_stimuli_pulse_period : natural := 7;
constant c_data_init : natural := 0;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
- constant c_channel_init : natural := 5; -- fixed
+ -- fixed
+ constant c_channel_init : natural := 5;
-- dp_stream_verify
constant c_verify_pulse_active : natural := 1;
@@ -91,7 +101,8 @@ architecture tb of tb_dp_repack_data is
--CONSTANT c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := c_dp_sosi_unsigned_rst; -- default 0 is no wrap
constant c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := TO_DP_SOSI_UNSIGNED('0', '0', '0', '0', c_data_max, c_dsp_max, c_dsp_max, c_unsigned_0, c_unsigned_0, c_unsigned_0, c_unsigned_0);
- constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones; -- default only accept increment +1
+ -- default only accept increment +1
+ constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones;
constant c_expected_pkt_len : natural := sel_a_b(c_no_unpack, g_pkt_len * g_pack_nof_words / g_in_nof_words, g_pkt_len);
-- both
@@ -133,12 +144,15 @@ begin
u_dp_stream_stimuli : entity work.dp_stream_stimuli
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 15,
g_pulse_active => c_stimuli_pulse_active,
g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_stimuli,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -161,9 +175,12 @@ begin
src_out => stimuli_src_out,
-- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ -- expected verify_snk_in after end of stimuli
+ last_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ last_snk_in_evt => last_snk_in_evt,
+ -- signal end of tb as far as this dp_stream_stimuli is concerned
+ tb_end => tb_end
);
------------------------------------------------------------------------------
@@ -199,12 +216,15 @@ begin
u_dp_stream_verify : entity work.dp_stream_verify
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 14,
g_pulse_active => c_verify_pulse_active,
g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_verify,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -223,11 +243,14 @@ begin
snk_in => verify_snk_in,
-- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+ -- enable verify to verify that the verify_snk_in fields are incrementing
+ verify_snk_in_enable => verify_snk_in_enable,
-- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ -- expected verify_snk_in after end of stimuli
+ expected_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ verify_expected_snk_in_evt => verify_last_snk_in_evt
);
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd b/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd
index 062f9d2deeca01986cb62ec00d32c670005a83fe..885146036abdc635bb84d2429904fc8a6a819650 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd
@@ -43,8 +43,10 @@ use work.tb_dp_pkg.all;
entity tb_dp_repack_legacy is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse;
+ -- always active, random or pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
-- g_in_dat_w : NATURAL := 8;
-- g_in_nof_words : NATURAL := 9;
@@ -58,8 +60,10 @@ entity tb_dp_repack_legacy is
g_pack_dat_w : natural := 16;
g_pack_nof_words : natural := 2;
g_nof_repeat : natural := 24;
- g_pkt_len : natural := 20; -- must be a multiple of g_in_nof_words
- g_pkt_gap : natural := 4 -- must be >= g_pack_nof_words
+ -- must be a multiple of g_in_nof_words
+ g_pkt_len : natural := 20;
+ -- must be >= g_pack_nof_words
+ g_pkt_gap : natural := 4
);
end tb_dp_repack_legacy;
@@ -69,9 +73,11 @@ architecture tb of tb_dp_repack_legacy is
constant c_stimuli_pulse_period : natural := 2;
constant c_data_init : natural := 0;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
- constant c_channel_init : natural := 5; -- fixed
+ -- fixed
+ constant c_channel_init : natural := 5;
-- dp_stream_verify
constant c_verify_pulse_active : natural := g_in_nof_words;
@@ -82,7 +88,8 @@ architecture tb of tb_dp_repack_legacy is
--CONSTANT c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := c_dp_sosi_unsigned_rst; -- default 0 is no wrap
constant c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := TO_DP_SOSI_UNSIGNED('0', '0', '0', '0', c_data_max, c_dsp_max, c_dsp_max, c_unsigned_0, c_unsigned_0, c_unsigned_0, c_unsigned_0);
- constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones; -- default only accept increment +1
+ -- default only accept increment +1
+ constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones;
-- both
constant c_sync_period : natural := 10;
@@ -121,12 +128,15 @@ begin
u_dp_stream_stimuli : entity work.dp_stream_stimuli
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 15,
g_pulse_active => c_stimuli_pulse_active,
g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_stimuli,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -149,9 +159,12 @@ begin
src_out => stimuli_src_out,
-- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ -- expected verify_snk_in after end of stimuli
+ last_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ last_snk_in_evt => last_snk_in_evt,
+ -- signal end of tb as far as this dp_stream_stimuli is concerned
+ tb_end => tb_end
);
------------------------------------------------------------------------------
@@ -187,12 +200,15 @@ begin
u_dp_stream_verify : entity work.dp_stream_verify
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 14,
g_pulse_active => c_verify_pulse_active,
g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_verify,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -211,11 +227,14 @@ begin
snk_in => verify_snk_in,
-- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+ -- enable verify to verify that the verify_snk_in fields are incrementing
+ verify_snk_in_enable => verify_snk_in_enable,
-- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ -- expected verify_snk_in after end of stimuli
+ expected_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ verify_expected_snk_in_evt => verify_last_snk_in_evt
);
------------------------------------------------------------------------------
@@ -239,13 +258,15 @@ begin
in_val => stimuli_src_out.valid,
in_sof => stimuli_src_out.sop,
in_eof => stimuli_src_out.eop,
- in_sync => stimuli_src_out.sync, -- DP style sync at sof
+ -- DP style sync at sof
+ in_sync => stimuli_src_out.sync,
out_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
out_val => pack_src_out.valid,
out_sof => pack_src_out.sop,
out_eof => pack_src_out.eop,
- sof_sync => pack_src_out.sync -- DP style sync at sof, passes on in_sync
+ -- DP style sync at sof, passes on in_sync
+ sof_sync => pack_src_out.sync
);
------------------------------------------------------------------------------
@@ -269,13 +290,15 @@ begin
in_val => pack_src_out.valid,
in_sof => pack_src_out.sop,
in_eof => pack_src_out.eop,
- in_sync => pack_src_out.sync, -- DP style sync at sof
+ -- DP style sync at sof
+ in_sync => pack_src_out.sync,
out_dat => unpack_src_out.data(g_in_dat_w - 1 downto 0),
out_val => unpack_src_out.valid,
out_sof => unpack_src_out.sop,
out_eof => unpack_src_out.eop,
- sof_sync => unpack_src_out.sync -- DP style sync at sof, passes on in_sync
+ -- DP style sync at sof, passes on in_sync
+ sof_sync => unpack_src_out.sync
);
unpack_src_in <= verify_snk_out;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
index 163c4635bf689c8634b5b045fe0a48a7e33d287b..aef20e0dbd23392887f240a03e441eec3a0d3e76 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
@@ -52,7 +52,8 @@ use work.tb_dp_pkg.all;
entity tb_dp_reverse_n_data is
generic (
-- specific
- g_pipeline : natural := 1; -- 0 for combinatorial, > 0 for registers
+ -- 0 for combinatorial, > 0 for registers
+ g_pipeline : natural := 1;
g_nof_repeat : natural := 5;
g_reverse_len : natural := 2;
g_pkt_gap : natural := 10
@@ -70,9 +71,11 @@ architecture tb of tb_dp_reverse_n_data is
constant c_data_init : natural := 0;
constant c_re_init : natural := 7;
constant c_im_init : natural := 17;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
- constant c_channel_init : natural := 5; -- fixed
+ -- fixed
+ constant c_channel_init : natural := 5;
-- dp_stream_verify
constant c_flow_control_latency : natural := c_pkt_len;
@@ -82,7 +85,8 @@ architecture tb of tb_dp_reverse_n_data is
--CONSTANT c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := c_dp_sosi_unsigned_rst; -- default 0 is no wrap
constant c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := TO_DP_SOSI_UNSIGNED('0', '0', '0', '0', c_data_max, c_dsp_max, c_dsp_max, c_unsigned_0, c_unsigned_0, c_unsigned_0, c_unsigned_0);
- constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones; -- default only accept increment +1
+ -- default only accept increment +1
+ constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones;
-- both
constant c_sync_period : natural := 10;
@@ -121,9 +125,11 @@ begin
u_dp_stream_stimuli : entity work.dp_stream_stimuli
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_flow_control => e_active, -- always active, no flow control
+ -- always active, no flow control
+ g_flow_control => e_active,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -139,7 +145,8 @@ begin
g_nof_repeat => g_nof_repeat,
g_pkt_len => c_pkt_len,
g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ g_wait_last_evt => c_flow_control_latency
)
port map (
rst => rst,
@@ -150,9 +157,12 @@ begin
src_out => stimuli_src_out,
-- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ -- expected verify_snk_in after end of stimuli
+ last_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ last_snk_in_evt => last_snk_in_evt,
+ -- signal end of tb as far as this dp_stream_stimuli is concerned
+ tb_end => tb_end
);
------------------------------------------------------------------------------
@@ -161,7 +171,8 @@ begin
-- Select fields that need to be verified
-- . during the test
- verify_snk_in_enable.sync <= '1'; -- or '0'
+ -- or '0'
+ verify_snk_in_enable.sync <= '1';
verify_snk_in_enable.bsn <= '1';
verify_snk_in_enable.data <= '1';
verify_snk_in_enable.valid <= '1';
@@ -184,9 +195,11 @@ begin
u_dp_stream_verify : entity work.dp_stream_verify
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_flow_control => e_active, -- always active, no flow control
+ -- always active, no flow control
+ g_flow_control => e_active,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -205,11 +218,14 @@ begin
snk_in => verify_snk_in,
-- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+ -- enable verify to verify that the verify_snk_in fields are incrementing
+ verify_snk_in_enable => verify_snk_in_enable,
-- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ -- expected verify_snk_in after end of stimuli
+ expected_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ verify_expected_snk_in_evt => verify_last_snk_in_evt
);
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd
index 5d89c3ab55ca9cb41d1e52e3d28925e3bf6393c4..6d1ef2f54d39a733e6abec6994e4d4155a5ea380 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd
@@ -48,10 +48,13 @@ use work.tb_dp_pkg.all;
entity tb_dp_reverse_n_data_fc is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- always e_active, e_random or e_pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ -- always e_active, e_random or e_pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
- g_pipeline : natural := 1; -- 0 for combinatorial, > 0 for registers
+ -- 0 for combinatorial, > 0 for registers
+ g_pipeline : natural := 1;
g_nof_repeat : natural := 5;
g_reverse_len : natural := 7;
g_pkt_gap : natural := 10
@@ -69,9 +72,11 @@ architecture tb of tb_dp_reverse_n_data_fc is
constant c_data_init : natural := 0;
constant c_re_init : natural := 7;
constant c_im_init : natural := 17;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
- constant c_channel_init : natural := 5; -- fixed
+ -- fixed
+ constant c_channel_init : natural := 5;
-- dp_stream_verify
constant c_verify_pulse_active : natural := 1;
@@ -81,14 +86,16 @@ architecture tb of tb_dp_reverse_n_data_fc is
constant c_flow_control_latency_rnd : natural := g_nof_repeat * c_pkt_len;
constant c_flow_control_latency : natural := sel_a_b(g_flow_control_stimuli = e_pulse or g_flow_control_verify = e_pulse,
c_flow_control_latency_pls,
- c_flow_control_latency_rnd); -- worst case value
+ -- worst case value
+ c_flow_control_latency_rnd);
constant c_data_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
constant c_dsp_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
--CONSTANT c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := c_dp_sosi_unsigned_rst; -- default 0 is no wrap
constant c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := TO_DP_SOSI_UNSIGNED('0', '0', '0', '0', c_data_max, c_dsp_max, c_dsp_max, c_unsigned_0, c_unsigned_0, c_unsigned_0, c_unsigned_0);
- constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones; -- default only accept increment +1
+ -- default only accept increment +1
+ constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones;
-- both
constant c_sync_period : natural := 10;
@@ -124,12 +131,15 @@ begin
u_dp_stream_stimuli : entity work.dp_stream_stimuli
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 15,
g_pulse_active => c_stimuli_pulse_active,
g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_stimuli,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -145,7 +155,8 @@ begin
g_nof_repeat => g_nof_repeat,
g_pkt_len => c_pkt_len,
g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ g_wait_last_evt => c_flow_control_latency
)
port map (
rst => rst,
@@ -156,9 +167,12 @@ begin
src_out => stimuli_src_out,
-- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ -- expected verify_snk_in after end of stimuli
+ last_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ last_snk_in_evt => last_snk_in_evt,
+ -- signal end of tb as far as this dp_stream_stimuli is concerned
+ tb_end => tb_end
);
------------------------------------------------------------------------------
@@ -167,7 +181,8 @@ begin
-- Select fields that need to be verified
-- . during the test
- verify_snk_in_enable.sync <= '1'; -- or '0'
+ -- or '0'
+ verify_snk_in_enable.sync <= '1';
verify_snk_in_enable.bsn <= '1';
verify_snk_in_enable.data <= '1';
verify_snk_in_enable.valid <= '1';
@@ -190,12 +205,15 @@ begin
u_dp_stream_verify : entity work.dp_stream_verify
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 14,
g_pulse_active => c_verify_pulse_active,
g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_verify,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -214,11 +232,14 @@ begin
snk_in => verify_snk_in,
-- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+ -- enable verify to verify that the verify_snk_in fields are incrementing
+ verify_snk_in_enable => verify_snk_in_enable,
-- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ -- expected verify_snk_in after end of stimuli
+ expected_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ verify_expected_snk_in_evt => verify_last_snk_in_evt
);
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
index 2079df76274b23a4f88114270dd0461d2037edb4..3e11e05f0666f5562d7e70be1522f51e740d9040 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
@@ -39,9 +39,12 @@ use dp_lib.tb_dp_pkg.all;
entity tb_dp_rsn_source is
generic (
- g_pps_interval : natural := 40; -- 101;
- g_bs_block_size : natural := 10; -- 23, input BSN block size <= g_pps_interval
- g_rs_block_size : natural := 10 -- 23, output RSN block size <= g_pps_interval
+ -- 101;
+ g_pps_interval : natural := 40;
+ -- 23, input BSN block size <= g_pps_interval
+ g_bs_block_size : natural := 10;
+ -- 23, output RSN block size <= g_pps_interval
+ g_rs_block_size : natural := 10
);
end tb_dp_rsn_source;
@@ -86,12 +89,18 @@ architecture tb of tb_dp_rsn_source is
-- Define the PPS (SSN) and BSN grid that both start at 0 according to Figure 3.1 in [1]:
type t_time_grid is record
- pps : std_logic; -- pulse per second, g_pps_interval clk per pps interval
- ssn : natural; -- seconds sequence number
- bsn : natural; -- block sequence number, g_bs_block_size clk per block
- sync : std_logic; -- active at sop when pps is active or was active
- sop : std_logic; -- start of block
- eop : std_logic; -- end of block
+ -- pulse per second, g_pps_interval clk per pps interval
+ pps : std_logic;
+ -- seconds sequence number
+ ssn : natural;
+ -- block sequence number, g_bs_block_size clk per block
+ bsn : natural;
+ -- active at sop when pps is active or was active
+ sync : std_logic;
+ -- start of block
+ sop : std_logic;
+ -- end of block
+ eop : std_logic;
end record;
constant c_time_grid_rst : t_time_grid := ('0', 0, 0, '0', '0', '0');
@@ -118,13 +127,15 @@ architecture tb of tb_dp_rsn_source is
signal bsn_init : std_logic_vector(c_bsn_w - 1 downto 0) := (others => '0');
signal bsn_time_offset : std_logic_vector(c_bsn_time_offset_w - 1 downto 0) := (others => '0');
signal bs_sosi : t_dp_sosi;
- signal exp_grid_bs : t_time_grid; -- to check with bs_sosi.bsn, sync, sop, eop
+ -- to check with bs_sosi.bsn, sync, sop, eop
+ signal exp_grid_bs : t_time_grid;
-- RSN source
signal rs_restart : std_logic;
signal rs_new_interval : std_logic;
signal rs_sosi : t_dp_sosi;
- signal exp_grid_rs : t_time_grid; -- to verify rs_sosi.bsn, sync, sop, eop
+ -- to verify rs_sosi.bsn, sync, sop, eop
+ signal exp_grid_rs : t_time_grid;
-- Verify
signal exp_rs_start_bsn : natural;
@@ -168,15 +179,18 @@ begin
if ref_grid_bs.pps = '1' then
if ref_grid_bs.sop = '1' then
- ref_grid_bs.sync <= '1'; -- immediately issue sync
+ -- immediately issue sync
+ ref_grid_bs.sync <= '1';
else
- nxt_hold_pps <= '1'; -- wait until next block
+ -- wait until next block
+ nxt_hold_pps <= '1';
end if;
end if;
if hold_pps = '1' then
if ref_grid_bs.sop = '1' then
- ref_grid_bs.sync <= '1'; -- issue pending sync
+ -- issue pending sync
+ ref_grid_bs.sync <= '1';
nxt_hold_pps <= '0';
end if;
end if;
@@ -239,9 +253,11 @@ begin
else
exp_rs_sync_cnt <= 0;
if v_sop = '1' then
- exp_grid_rs.sync <= '1'; -- issue sync immediately at this exp_grid_rs.sop
+ -- issue sync immediately at this exp_grid_rs.sop
+ exp_grid_rs.sync <= '1';
else
- hold_exp_rs_sync <= '1'; -- pend sync until next exp_grid_rs.sop
+ -- pend sync until next exp_grid_rs.sop
+ hold_exp_rs_sync <= '1';
end if;
end if;
end if;
@@ -261,7 +277,8 @@ begin
proc_common_wait_some_cycles(clk, 10);
-- Start asynchronously by making dp_on high
- verify_en <= '0'; -- only verify visualy in wave window
+ -- only verify visualy in wave window
+ verify_en <= '0';
tb_state <= s_dp_on;
dp_on_pps <= '0';
dp_on <= '1';
@@ -274,7 +291,8 @@ begin
proc_common_wait_some_cycles(clk, 5 * g_pps_interval);
-- Start synchronously by making dp_on and dp_on_pps high
- verify_en <= '1'; -- verify automatically in test bench
+ -- verify automatically in test bench
+ verify_en <= '1';
for I in 0 to c_nof_repeat - 1 loop
-- Wait some variable time between tests, to enforce testing different
@@ -289,10 +307,14 @@ begin
-- Determine bsn_init and bsn_time_offset for BSN source start
-- . bsn_init = BSN at sync
-- . bsn_time_offset = number of clk that sync occurs after PPS
- v_ssn := ref_grid_bs.ssn + 1; -- +1 to prepare start in next PPS interval
- v_bsn_init := ceil_div(v_SSN * g_pps_interval, g_bs_block_size); -- Equation 3.6 in [1]
- v_bsn_time_offset := v_bsn_init * g_bs_block_size - v_SSN * g_pps_interval; -- Equation 3.7 in [1]
- bsn_init <= TO_UVEC(v_bsn_init, c_bsn_w); --
+ -- +1 to prepare start in next PPS interval
+ v_ssn := ref_grid_bs.ssn + 1;
+ -- Equation 3.6 in [1]
+ v_bsn_init := ceil_div(v_SSN * g_pps_interval, g_bs_block_size);
+ -- Equation 3.7 in [1]
+ v_bsn_time_offset := v_bsn_init * g_bs_block_size - v_SSN * g_pps_interval;
+ --
+ bsn_init <= TO_UVEC(v_bsn_init, c_bsn_w);
bsn_time_offset <= TO_UVEC(v_bsn_time_offset, c_bsn_time_offset_w);
-- Start synchronously by making dp_on and dp_on_pps high
tb_state <= s_dp_on_pps;
@@ -319,14 +341,16 @@ begin
-----------------------------------------------------------------------------
verify_sync <= verify_en and rs_sosi.valid;
- proc_dp_verify_sop_and_eop(clk, rs_sosi.valid, rs_sosi.sop, rs_sosi.eop, hold_rs_sop); -- Verify that sop and eop come in pairs
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(clk, rs_sosi.valid, rs_sosi.sop, rs_sosi.eop, hold_rs_sop);
--proc_dp_verify_sync(clk, verify_sync, rs_sosi.sync, exp_grid_rs.sop, exp_grid_rs.sync); -- Verify sync at sop and at expected_sync
-- Verify sync at sop and at expected_sync
proc_dp_verify_sync(exp_rs_start_bsn,
g_pps_interval,
g_rs_block_size,
- true, -- use BSN as RSN
+ -- use BSN as RSN
+ true,
clk,
verify_en,
rs_sosi.sync,
@@ -404,9 +428,12 @@ begin
dp_on => dp_on,
dp_on_pps => dp_on_pps,
- dp_on_status => dp_on_status, -- = src_out.valid
- bs_restart => bs_restart, -- = src_out.sync for first sync after dp_on went high
- bs_new_interval => bs_new_interval, -- active during first src_out.sync interval
+ -- = src_out.valid
+ dp_on_status => dp_on_status,
+ -- = src_out.sync for first sync after dp_on went high
+ bs_restart => bs_restart,
+ -- active during first src_out.sync interval
+ bs_new_interval => bs_new_interval,
bsn_init => bsn_init,
bsn_time_offset => bsn_time_offset,
@@ -427,11 +454,15 @@ begin
clk => clk,
-- Input stream sosi control using BSN
- bs_sosi => bs_sosi, -- input reference stream using BSN
+ -- input reference stream using BSN
+ bs_sosi => bs_sosi,
-- Output stream sosi control using RSN
- rs_sosi => rs_sosi, -- output stream using RSN and g_rs_block_size, g_nof_clk_per_sync
- rs_restart => rs_restart, -- = rs_sosi.sync for first sync after bs_sosi.valid went high
- rs_new_interval => rs_new_interval -- = active during first rs_sosi.sync interval
+ -- output stream using RSN and g_rs_block_size, g_nof_clk_per_sync
+ rs_sosi => rs_sosi,
+ -- = rs_sosi.sync for first sync after bs_sosi.valid went high
+ rs_restart => rs_restart,
+ -- = active during first rs_sosi.sync interval
+ rs_new_interval => rs_new_interval
);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
index 2801b29fc2bebb169ad5c1663573eecf1a7410e4..4af11b200751dfdc67c043ff3c96332e52e91762 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
@@ -53,7 +53,8 @@ entity tb_dp_selector_arr is
g_in_dat_w : natural := 32;
g_in_nof_words : natural := 1;
g_nof_repeat : natural := 20;
- g_pkt_len : natural := 16; -- must be a multiple of g_in_nof_words
+ -- must be a multiple of g_in_nof_words
+ g_pkt_len : natural := 16;
g_pkt_gap : natural := 4
);
end tb_dp_selector_arr;
@@ -66,9 +67,11 @@ architecture tb of tb_dp_selector_arr is
constant c_data_max : unsigned(g_in_dat_w - 1 downto 0) := (others => '1');
constant c_data_init : integer := -1;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
- constant c_channel_init : integer := 5; -- fixed
+ -- fixed
+ constant c_channel_init : integer := 5;
constant c_pipe_data_offset : integer := 1000;
@@ -119,10 +122,12 @@ begin
for I in 0 to g_nof_repeat - 1 loop
-- Auto increment v_sosi field values for this packet
v_sosi.bsn := INCR_UVEC(v_sosi.bsn, 1);
- v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_sync_period) = c_sync_offset, '1', '0'); -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_sync_period) = c_sync_offset, '1', '0');
v_sosi.channel := INCR_UVEC(v_sosi.channel, 1);
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
v_sosi.err := INCR_UVEC(v_sosi.err, 1);
-- Send packet
@@ -139,7 +144,8 @@ begin
v_sosi.err := TO_DP_ERROR(c_err_init + g_nof_repeat - 1);
-- . account for g_pkt_len
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len - 1);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
verify_sosi <= v_sosi;
-- Signal end of stimuli
proc_common_wait_some_cycles(clk, 100);
@@ -149,8 +155,10 @@ begin
p_verify : process
begin
- proc_common_wait_some_cycles(clk, g_nof_repeat * (g_pkt_gap + g_pkt_len)); -- Wait until end of simulation.
- proc_common_wait_some_cycles(clk, 50); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ -- Wait until end of simulation.
+ proc_common_wait_some_cycles(clk, g_nof_repeat * (g_pkt_gap + g_pkt_len));
+ -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ proc_common_wait_some_cycles(clk, 50);
for I in 0 to c_nof_streams - 1 loop
assert signed(verify_sosi.channel) = signed(out_ref_sosi_arr(I).channel) report "Unexpected channel from dut_ref output." severity ERROR;
assert signed(verify_sosi.channel) = signed(out_pipe_sosi_arr(I).channel) report "Unexpected channel from dut_pipe output." severity ERROR;
@@ -232,8 +240,10 @@ begin
p_stim: process
begin
wait until rst = '0';
- proc_mem_mm_bus_wr(0, x"0", clk, mm_mosi_ref); -- select ref_sosi_arr on dut_ref
- proc_mem_mm_bus_wr(0, x"1", clk, mm_mosi_pipe); -- select pipe_sosi_arr on dut_pipe
+ -- select ref_sosi_arr on dut_ref
+ proc_mem_mm_bus_wr(0, x"0", clk, mm_mosi_ref);
+ -- select pipe_sosi_arr on dut_pipe
+ proc_mem_mm_bus_wr(0, x"1", clk, mm_mosi_pipe);
wait;
end process;
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd b/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
index 1d249b0aa1e22a96485c7659d14849f8fa0e2bfb..72ed8ae45b0554d908a84d4a1f752669e37217b0 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
@@ -34,21 +34,32 @@ architecture tb of tb_dp_shiftreg is
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT ready latency
- constant c_dut_latency : natural := 1; -- fixed 1 for dp_shiftreg
- constant c_tx_latency : natural := c_dut_latency; -- TX ready latency of TB
- constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ -- fixed 1 for dp_shiftreg
+ constant c_dut_latency : natural := 1;
+ -- TX ready latency of TB
+ constant c_tx_latency : natural := c_dut_latency;
+ -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0);
constant c_tx_offset_sop : natural := 3;
- constant c_tx_period_sop : natural := 7; -- sop in data valid cycle 3, 10, 17, ...
- constant c_tx_offset_eop : natural := 5; -- eop in data valid cycle 5, 12, 19, ...
+ -- sop in data valid cycle 3, 10, 17, ...
+ constant c_tx_period_sop : natural := 7;
+ -- eop in data valid cycle 5, 12, 19, ...
+ constant c_tx_offset_eop : natural := 5;
constant c_tx_period_eop : natural := c_tx_period_sop;
- constant c_rx_latency : natural := c_dut_latency; -- RX ready latency from DUT
- constant c_verify_en_wait : natural := 8; -- wait some cycles before asserting verify enable
+ -- RX ready latency from DUT
+ constant c_rx_latency : natural := c_dut_latency;
+ -- wait some cycles before asserting verify enable
+ constant c_verify_en_wait : natural := 8;
- constant c_dut_output_reg : boolean := true; -- when TRUE register the DUT output control signals, else combinatorial output control
- constant c_dut_flush_eop : boolean := true; -- when TRUE then shift register gets flushed if it contains an eop, else only shift when in_val
- constant c_modify_support : boolean := true; -- when TRUE allow modify shift register contents when in_val is active
+ -- when TRUE register the DUT output control signals, else combinatorial output control
+ constant c_dut_output_reg : boolean := true;
+ -- when TRUE then shift register gets flushed if it contains an eop, else only shift when in_val
+ constant c_dut_flush_eop : boolean := true;
+ -- when TRUE allow modify shift register contents when in_val is active
+ constant c_modify_support : boolean := true;
- constant c_dut_nof_words : natural := 1; -- shift register size
+ -- shift register size
+ constant c_dut_nof_words : natural := 1;
constant c_random_w : natural := 19;
@@ -119,7 +130,8 @@ begin
proc_dp_verify_valid(c_rx_latency, clk, verify_en, out_ready, prev_out_ready, out_val);
proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", clk, verify_en, out_data, out_val, out_sop);
proc_dp_verify_ctrl(c_tx_offset_eop, c_tx_period_eop, "eop", clk, verify_en, out_data, out_val, out_eop);
- proc_dp_verify_sop_and_eop(c_rx_latency, false, clk, out_val, out_val, out_sop, out_eop, hold_out_sop); -- Verify that sop and eop come in pairs, no check on valid between eop and sop
+ -- Verify that sop and eop come in pairs, no check on valid between eop and sop
+ proc_dp_verify_sop_and_eop(c_rx_latency, false, clk, out_val, out_val, out_sop, out_eop, hold_out_sop);
-- Check that the test has ran at all
proc_dp_verify_value(e_equal, clk, verify_done, exp_data, out_data);
@@ -132,14 +144,18 @@ begin
new_shiftreg_inputs <= cur_shiftreg_inputs;
-- map sl, slv to record
- in_ready <= in_siso.ready; -- SISO
- in_sosi.data(c_dp_data_w - 1 downto 0) <= in_data; -- SOSI
+ -- SISO
+ in_ready <= in_siso.ready;
+ -- SOSI
+ in_sosi.data(c_dp_data_w - 1 downto 0) <= in_data;
in_sosi.valid <= in_val;
in_sosi.sop <= in_sop;
in_sosi.eop <= in_eop;
- out_siso.ready <= out_ready; -- SISO
- out_data <= out_sosi.data(c_dp_data_w - 1 downto 0); -- SOSI
+ -- SISO
+ out_siso.ready <= out_ready;
+ -- SOSI
+ out_data <= out_sosi.data(c_dp_data_w - 1 downto 0);
out_val <= out_sosi.valid;
out_sop <= out_sosi.sop;
out_eop <= out_sosi.eop;
@@ -155,13 +171,15 @@ begin
rst => rst,
clk => clk,
-- ST sink
- snk_out => in_siso, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out => in_siso,
snk_in => in_sosi,
-- Control shift register contents
cur_shiftreg_inputs => cur_shiftreg_inputs,
new_shiftreg_inputs => new_shiftreg_inputs,
-- ST source
- src_in => out_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => out_siso,
src_out => out_sosi
);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_split.vhd b/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
index 47278fc5b0eb9e6d7962c55ac16503b9f6f01434..3c8f6865ce79372af5ed4fb491f433825a6b97ff 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
@@ -32,11 +32,15 @@ use work.tb_dp_pkg.all;
entity tb_dp_split is
generic (
- g_data_w : natural := 64; -- g_data_w/g_symbol_w must be an integer
- g_symbol_w : natural := 16; -- use sufficient width to avoid wrap in proc_dp_gen_frame()
+ -- g_data_w/g_symbol_w must be an integer
+ g_data_w : natural := 64;
+ -- use sufficient width to avoid wrap in proc_dp_gen_frame()
+ g_symbol_w : natural := 16;
-- use symbols width that contains whole nibbles (4-bit) to easy debugging in HEX
- g_nof_symbols_max : natural := 50; -- maximum supported frame size
- g_random_control : boolean := false -- use TRUE for random snk_in.valid and src_in.ready control
+ -- maximum supported frame size
+ g_nof_symbols_max : natural := 50;
+ -- use TRUE for random snk_in.valid and src_in.ready control
+ g_random_control : boolean := false
);
end tb_dp_split;
@@ -50,13 +54,15 @@ architecture tb of tb_dp_split is
constant c_sync_period : natural := 7;
constant c_sync_offset : natural := 2;
- constant c_verify_mode : boolean := false; -- use mode FALSE to verify per frame
+ -- use mode FALSE to verify per frame
+ constant c_verify_mode : boolean := false;
signal tb_end : std_logic := '0';
signal rst : std_logic;
signal clk : std_logic := '0';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal random_2 : std_logic_vector(17 downto 0) := (others => '0');
@@ -94,7 +100,8 @@ begin
in_en <= random_0(random_0'high);
out_siso(0).ready <= random_1(random_1'high);
out_siso(1).ready <= random_2(random_2'high);
- end generate; -- else the in_en and out_siso lines are always active
+ -- else the in_en and out_siso lines are always active
+ end generate;
p_stimuli : process
variable vINIT : natural := 0;
@@ -146,9 +153,11 @@ begin
rst => rst,
clk => clk,
nof_symbols => nof_symbols,
- snk_out => in_siso, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out => in_siso,
snk_in => in_sosi,
- src_in_arr => out_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in_arr => out_siso,
src_out_arr => out_sosi
);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd b/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
index 55c713be62ff85fb0e9a99f15cd70a6eea1e437f..7a1a94dd94240eeda7e9e9535b234216e39fabd7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
@@ -65,8 +65,10 @@ architecture tb of tb_dp_strobe_total_count is
constant c_clip : boolean := true;
-- dut
- constant c_nof_counts_max : natural := c_dp_strobe_total_count_reg_nof_counts_max; -- fixed by REGMAP
- constant c_nof_counts : natural := 3; -- count stimuli.sync, sop, valid
+ -- fixed by REGMAP
+ constant c_nof_counts_max : natural := c_dp_strobe_total_count_reg_nof_counts_max;
+ -- count stimuli.sync, sop, valid
+ constant c_nof_counts : natural := 3;
constant c_count_max : natural := 2**g_count_w - 1;
constant c_mm_addr_clear : natural := c_dp_strobe_total_count_reg_clear_adr;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd b/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
index 83b91d51143c56abb68679ec11e9689d0dff9d6f..a53d5d10371bb4594859780a15a657098f403b8d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
@@ -44,10 +44,13 @@ architecture tb of tb_dp_switch is
constant c_data_w : natural := 32;
constant c_nof_packets : natural := 30;
constant c_packet_len : natural := 20;
- constant c_packet_gap : natural := 1; -- NOTE: dp_mux requires a minimum gap of 1 to select a new input!
+ -- NOTE: dp_mux requires a minimum gap of 1 to select a new input!
+ constant c_packet_gap : natural := 1;
- constant c_dp_clk_period : time := 5 ns; -- 200 MHz
- constant c_mm_clk_period : time := 20 ns; -- 50 MHz
+ -- 200 MHz
+ constant c_dp_clk_period : time := 5 ns;
+ -- 50 MHz
+ constant c_mm_clk_period : time := 20 ns;
constant c_nof_switch_runs : natural := 2;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
index 22cf16f4c6aa666ad36bd28409e444d227eb641d..3dd3a0ea13ad56d93eafe18d133a18906a84ac19 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
@@ -46,17 +46,22 @@ use work.tb_dp_pkg.all;
entity tb_dp_sync_checker is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
g_in_dat_w : natural := 32;
g_in_nof_words : natural := 1;
g_nof_repeat : natural := 100;
- g_pkt_len : natural := 16; -- must be a multiple of g_in_nof_words
+ -- must be a multiple of g_in_nof_words
+ g_pkt_len : natural := 16;
g_pkt_gap : natural := 0;
- g_sync_period : natural := 15; -- The sync period generated in the stimuli.
+ -- The sync period generated in the stimuli.
+ g_sync_period : natural := 15;
-- DUT
- g_nof_blk_per_sync : positive := 16 -- The sync period as expected by the sync_checker
+ -- The sync period as expected by the sync_checker
+ g_nof_blk_per_sync : positive := 16
);
end tb_dp_sync_checker;
@@ -74,17 +79,21 @@ architecture tb of tb_dp_sync_checker is
constant c_data_max : unsigned(g_in_dat_w - 1 downto 0) := (others => '1');
constant c_data_init : integer := -1;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
- constant c_channel_init : integer := 5; -- fixed
+ -- fixed
+ constant c_channel_init : integer := 5;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal sl1 : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -106,7 +115,8 @@ architecture tb of tb_dp_sync_checker is
signal prev_verify_snk_out : t_dp_siso;
signal verify_snk_out : t_dp_siso := c_dp_siso_rdy;
signal verify_snk_in : t_dp_sosi;
- signal verify_snk_in_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0); -- used to hold valid data for verify at verify_done
+ -- used to hold valid data for verify at verify_done
+ signal verify_snk_in_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0);
signal verify_data : std_logic_vector(g_in_dat_w - 1 downto 0);
signal prev_verify_snk_in : t_dp_sosi;
@@ -161,10 +171,12 @@ begin
for I in 0 to g_nof_repeat - 1 loop
-- Auto increment v_sosi field values for this packet
v_sosi.bsn := INCR_UVEC(v_sosi.bsn, 1);
- v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod g_sync_period) = c_sync_offset, '1', '0'); -- insert sync starting at BSN=c_sync_offset and with period g_sync_period
+ -- insert sync starting at BSN=c_sync_offset and with period g_sync_period
+ v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod g_sync_period) = c_sync_offset, '1', '0');
v_sosi.channel := INCR_UVEC(v_sosi.channel, 1);
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
v_sosi.err := INCR_UVEC(v_sosi.err, 1);
-- Send packet
@@ -181,11 +193,13 @@ begin
v_sosi.err := TO_DP_ERROR(c_err_init + g_nof_repeat - 1);
-- . account for g_pkt_len
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len - 1);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
expected_verify_snk_in <= v_sosi;
-- Signal end of stimuli
- proc_common_wait_some_cycles(clk, 100); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ proc_common_wait_some_cycles(clk, 100);
proc_common_gen_pulse(clk, verify_done);
proc_common_wait_some_cycles(clk, 50);
tb_end <= '1';
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
index 3ec876e8a30820ff6a74d97518b3faa357b26fd7..44223f0f407fab748bf8640b2c8be0fc51243f8e 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
@@ -51,7 +51,8 @@ entity tb_dp_sync_recover is
g_gap_size_during_block : natural := 0;
g_gap_size_between_block : natural := 0;
g_init_bsn : natural := 23;
- g_bsn_at_restart : natural := 40; -- the bsn index at which to restart the dut.
+ -- the bsn index at which to restart the dut.
+ g_bsn_at_restart : natural := 40;
g_dut_latency : natural := 25;
g_nof_repeat : natural := 14
);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd b/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
index f9587df95d1a3e24b149e625b605eda6842bcfea..a9a21d0900b434886597c7b353bfcc3b7cb30d71 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
@@ -43,14 +43,20 @@ use work.tb_dp_pkg.all;
entity tb_dp_throttle_xon is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random flow control
+ -- always active or random flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ -- always active or random flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
- g_restart_at_sync : boolean := false; -- if true restart xon control at each snk_in_sync, else and start at first valid and never restart
- g_block_size : natural := 10; -- number of valid data per block marked by sop and eop
- g_nof_block_on : natural := 13; -- number of blocks that snk_out.xon is active
+ -- if true restart xon control at each snk_in_sync, else and start at first valid and never restart
+ g_restart_at_sync : boolean := false;
+ -- number of valid data per block marked by sop and eop
+ g_block_size : natural := 10;
+ -- number of blocks that snk_out.xon is active
+ g_nof_block_on : natural := 13;
g_nof_block_per_sync : natural := 10;
- g_nof_clk_off : natural := 37 -- must be > g_block_size, number of clock cycles that snk_out.xon is kept inactive
+ -- must be > g_block_size, number of clock cycles that snk_out.xon is kept inactive
+ g_nof_clk_off : natural := 37
);
end tb_dp_throttle_xon;
@@ -63,10 +69,14 @@ architecture tb of tb_dp_throttle_xon is
constant c_data_w : natural := 16;
constant c_nof_repeat : natural := c_nof_sync * g_nof_block_per_sync;
- constant c_init_bsn : natural := 0; -- will increment
- constant c_init_data : integer := 1; -- fixed
- constant c_init_err : natural := 4; -- fixed
- constant c_init_channel : integer := 5; -- fixed
+ -- will increment
+ constant c_init_bsn : natural := 0;
+ -- fixed
+ constant c_init_data : integer := 1;
+ -- fixed
+ constant c_init_err : natural := 4;
+ -- fixed
+ constant c_init_channel : integer := 5;
signal tb_end : std_logic := '0';
signal tb_stimuli_end : std_logic := '0';
@@ -74,8 +84,10 @@ architecture tb of tb_dp_throttle_xon is
signal rst : std_logic := '1';
signal sl1 : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal stimuli_en : std_logic := '1';
signal stimuli_src_in : t_dp_siso;
@@ -88,7 +100,8 @@ architecture tb of tb_dp_throttle_xon is
signal verify_hold_sop : std_logic := '0';
signal verify_en_sop : std_logic := '0';
- signal verify_en_bsn : std_logic := '0'; -- used as inout
+ -- used as inout
+ signal verify_en_bsn : std_logic := '0';
signal verify_done : std_logic := '0';
signal expected_verify_snk_in : t_dp_sosi;
@@ -98,8 +111,10 @@ architecture tb of tb_dp_throttle_xon is
signal prev_out_bsn_global : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
signal prev_out_bsn_local : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
- signal xon_cnt : natural; -- count nof valid='1' cycles
- signal xoff_cnt : natural; -- count nof valid='0' cycles
+ -- count nof valid='1' cycles
+ signal xon_cnt : natural;
+ -- count nof valid='0' cycles
+ signal xoff_cnt : natural;
begin
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -134,10 +149,12 @@ begin
-- Generate c_nof_repeat packets
for I in 0 to c_nof_repeat - 1 loop
-- Auto increment v_sosi field values for this packet
- v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod g_nof_block_per_sync) = 0, '1', '0'); -- insert sync every g_nof_block_per_sync
+ -- insert sync every g_nof_block_per_sync
+ v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod g_nof_block_per_sync) = 0, '1', '0');
-- Send packet
- proc_common_wait_until_high(clk, stimuli_src_in.xon); -- wait for XON to avoid gaps in BSN increment
+ -- wait for XON to avoid gaps in BSN increment
+ proc_common_wait_until_high(clk, stimuli_src_in.xon);
proc_dp_gen_block_data(c_data_w, c_init_data, g_block_size, c_init_channel, c_init_err, v_sosi.sync, v_sosi.bsn, clk, stimuli_en, stimuli_src_in, stimuli_src_out);
v_sosi.bsn := INCR_UVEC(v_sosi.bsn, 1);
@@ -224,7 +241,8 @@ begin
snk_out => stimuli_src_in,
snk_in => stimuli_src_out,
-- Frame out
- src_in => verify_snk_out, -- flush control via out_siso.xon
+ -- flush control via out_siso.xon
+ src_in => verify_snk_out,
src_out => verify_snk_in
);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
index bd86e59c732776f7803aa5721b3e7e1687b344d7..2e2ad598d9b4d15654f38509f10bdc710c4f6983 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
@@ -63,14 +63,17 @@ use work.tb_dp_pkg.all;
entity tb_dp_xonoff is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
g_in_dat_w : natural := 32;
g_in_nof_words : natural := 1;
g_nof_repeat : natural := 100;
g_nof_dut : natural := 1;
- g_pkt_len : natural := 5; -- must be a multiple of g_in_nof_words
+ -- must be a multiple of g_in_nof_words
+ g_pkt_len : natural := 5;
g_pkt_gap : natural := 4
);
end tb_dp_xonoff;
@@ -89,17 +92,21 @@ architecture tb of tb_dp_xonoff is
constant c_data_max : unsigned(g_in_dat_w - 1 downto 0) := (others => '1');
constant c_data_init : integer := -1 + g_pkt_len;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
- constant c_channel_init : integer := 5; -- fixed
+ -- fixed
+ constant c_channel_init : integer := 5;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal sl1 : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -118,7 +125,8 @@ architecture tb of tb_dp_xonoff is
signal prev_verify_snk_out : t_dp_siso;
signal verify_snk_out : t_dp_siso := c_dp_siso_rdy;
signal verify_snk_in : t_dp_sosi;
- signal verify_snk_in_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0); -- used to hold valid data for verify at verify_done
+ -- used to hold valid data for verify at verify_done
+ signal verify_snk_in_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0);
signal verify_data : std_logic_vector(g_in_dat_w - 1 downto 0);
signal prev_verify_snk_in : t_dp_sosi;
@@ -175,10 +183,12 @@ begin
for I in 0 to c_nof_repeat - 1 loop
-- Auto increment v_sosi field values for this packet
v_sosi.bsn := INCR_UVEC(v_sosi.bsn, 1);
- v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_sync_period) = c_sync_offset, '1', '0'); -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_sync_period) = c_sync_offset, '1', '0');
v_sosi.channel := INCR_UVEC(v_sosi.channel, 1);
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
v_sosi.err := INCR_UVEC(v_sosi.err, 1);
-- Send packet
@@ -199,12 +209,14 @@ begin
v_sosi.err := TO_DP_ERROR(c_err_init + c_nof_repeat - 1);
-- . account for g_pkt_len
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len - 1);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
expected_verify_snk_in <= v_sosi;
-- Signal end of stimuli
proc_common_gen_pulse(clk, stimuli_done);
- proc_common_wait_some_cycles(clk, 100); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ proc_common_wait_some_cycles(clk, 100);
proc_common_gen_pulse(clk, verify_done);
proc_common_wait_some_cycles(clk, 50);
tb_end <= '1';
@@ -284,7 +296,8 @@ begin
in_siso => dut_siso_arr(I - 1),
in_sosi => dut_sosi_arr(I - 1),
-- Frame out
- out_siso => dut_siso_arr(I), -- flush control via out_siso.xon
+ -- flush control via out_siso.xon
+ out_siso => dut_siso_arr(I),
out_sosi => dut_sosi_arr(I)
);
end generate;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd b/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
index 46d08b2d87f8d1669af908f897a87551fe2e6365..6c1f314bd8ca75112f62d4de3b388a3384b99e6b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
@@ -36,8 +36,10 @@ entity tb_dp_xonoff_reg_timeout is
end tb_dp_xonoff_reg_timeout;
architecture tb of tb_dp_xonoff_reg_timeout is
- constant clk_period : time := 20 ns; -- 50 MHz
- constant st_clk_period : time := 5000 ps; -- 200 MHz
+ -- 50 MHz
+ constant clk_period : time := 20 ns;
+ -- 200 MHz
+ constant st_clk_period : time := 5000 ps;
-- Minimum nof clk cycles between eop and sop
constant c_500ns_latency : natural := 500 / 20;
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
index 78ff1107922be99fcc03ddd829a454cf448692a1..c05132b60e65c4d8c3456af349e0d15989bd33ef 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
@@ -46,7 +46,8 @@ use work.tb_dp_pkg.all;
entity tb_mmp_dp_bsn_align_v2 is
generic (
- g_lost_input : boolean := true -- when TRUE use c_nof_streams-1 as lost input
+ -- when TRUE use c_nof_streams-1 as lost input
+ g_lost_input : boolean := true
);
end tb_mmp_dp_bsn_align_v2;
@@ -56,14 +57,17 @@ architecture tb of tb_mmp_dp_bsn_align_v2 is
constant c_cross_clock_domain_latency : natural := 20;
constant c_rl : natural := 1;
- constant c_tb_nof_restart : natural := 2; -- number of times to restart the input stimuli
- constant c_tb_nof_blocks : natural := 50; -- number of input blocks per restart
+ -- number of times to restart the input stimuli
+ constant c_tb_nof_restart : natural := 2;
+ -- number of input blocks per restart
+ constant c_tb_nof_blocks : natural := 50;
-- Fixed dut generics
-- . for dp_bsn_align_v2
constant c_nof_streams : natural := 5;
constant c_bsn_latency_max : natural := 1;
- constant c_nof_aligners_max : positive := 1; -- fixed in this tb
+ -- fixed in this tb
+ constant c_nof_aligners_max : positive := 1;
constant c_block_size : natural := 11;
constant c_block_period : natural := 11;
constant c_block_per_sync : natural := 7;
@@ -78,7 +82,8 @@ architecture tb of tb_mmp_dp_bsn_align_v2 is
constant c_nof_clk_per_sync : natural := c_block_per_sync * c_block_period;
constant c_nof_input_bsn_monitors : natural := c_nof_streams;
constant c_use_bsn_output_monitor : boolean := true;
- constant c_mon_sync_latency : natural := 1; -- due to sync_reg2 in dp_bsn_monitor_v2
+ -- due to sync_reg2 in dp_bsn_monitor_v2
+ constant c_mon_sync_latency : natural := 1;
constant c_reg_bsn_monitor_adr_w : natural := ceil_log2(7);
constant c_reg_bsn_monitor_span : natural := 2**c_reg_bsn_monitor_adr_w;
@@ -106,13 +111,17 @@ architecture tb of tb_mmp_dp_bsn_align_v2 is
constant c_mm_to_dp_latency : natural := 1;
constant c_dut_latency : natural := c_pipeline_input + c_rd_latency + c_mm_to_dp_latency + c_pipeline_output;
- constant c_align_latency_nof_blocks : natural := c_bsn_latency_max * c_nof_aligners_max; -- in number blocks
- constant c_align_latency_nof_valid : natural := c_bsn_latency_max * c_nof_aligners_max * c_block_size; -- in number of data samples
- constant c_align_latency_nof_clk : natural := c_bsn_latency_max * c_nof_aligners_max * c_block_period; -- in number clk cycles
+ -- in number blocks
+ constant c_align_latency_nof_blocks : natural := c_bsn_latency_max * c_nof_aligners_max;
+ -- in number of data samples
+ constant c_align_latency_nof_valid : natural := c_bsn_latency_max * c_nof_aligners_max * c_block_size;
+ -- in number clk cycles
+ constant c_align_latency_nof_clk : natural := c_bsn_latency_max * c_nof_aligners_max * c_block_period;
-- Total DUT chain latency
constant c_total_latency : natural := c_dut_latency + c_align_latency_nof_clk;
- constant c_verify_nof_blocks : natural := c_tb_nof_blocks - c_align_latency_nof_blocks; -- skip last blocks that are still in the DUT buffer
+ -- skip last blocks that are still in the DUT buffer
+ constant c_verify_nof_blocks : natural := c_tb_nof_blocks - c_align_latency_nof_blocks;
-- Signal monitoring and verification
type t_data_arr is array (c_nof_streams - 1 downto 0) of std_logic_vector(c_data_w - 1 downto 0);
@@ -149,8 +158,10 @@ architecture tb of tb_mmp_dp_bsn_align_v2 is
signal node_index : natural := 0;
signal ref_siso_arr : t_dp_siso_arr(c_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
- signal ref_sosi_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0); -- generated stimuli
- signal in_sosi_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst); -- input stimuli
+ -- generated stimuli
+ signal ref_sosi_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0);
+ -- input stimuli
+ signal in_sosi_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
signal in_sync_arr : std_logic_vector(c_nof_streams - 1 downto 0);
signal in_sop_arr : std_logic_vector(c_nof_streams - 1 downto 0);
@@ -161,7 +172,8 @@ architecture tb of tb_mmp_dp_bsn_align_v2 is
signal in_channel_arr : t_channel_arr;
signal in_err_arr : t_err_arr;
- signal out_sosi_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst); -- output
+ -- output
+ signal out_sosi_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
signal out_sosi : t_dp_sosi;
signal out_sync_arr : std_logic_vector(c_nof_streams - 1 downto 0);
signal out_sop_arr : std_logic_vector(c_nof_streams - 1 downto 0);
@@ -264,7 +276,8 @@ begin
mon_latency_input_arr(I) <= TO_SINT(reg_input_monitor_cipo.rddata(31 downto 0));
proc_common_wait_some_cycles(mm_clk, 1);
if g_lost_input = true and I = c_nof_streams - 1 then
- v_exp_latency := -1; -- -1 for BSN monitor timeout due to lost input
+ -- -1 for BSN monitor timeout due to lost input
+ v_exp_latency := -1;
assert mon_latency_input_arr(I) = v_exp_latency report
"Wrong input BSN monitor latency timeout for input " & int_to_str(I) &
" (" & int_to_str(mon_latency_input_arr(I)) &
@@ -325,7 +338,8 @@ begin
proc_dp_gen_block_data(c_rl, true, c_data_w, c_data_w, v_data, 0, 0, c_block_size, v_channel, v_err, v_sync, TO_UVEC(v_bsn, c_bsn_w), dp_clk, sl1, ref_siso_arr(I), ref_sosi_arr(I));
v_bsn := v_bsn + 1;
v_data := v_data + c_block_size;
- proc_common_wait_some_cycles(dp_clk, c_gap_size); -- create gap between frames
+ -- create gap between frames
+ proc_common_wait_some_cycles(dp_clk, c_gap_size);
end loop;
-- Create gap between restarts
proc_common_wait_some_cycles(dp_clk, 10);
@@ -404,16 +418,19 @@ begin
out_err_arr(I) <= out_sosi_arr(I).err;
end generate;
- out_sosi <= out_sosi_arr(0); -- take out_sosi control and info from out_sosi_arr(0)
+ -- take out_sosi control and info from out_sosi_arr(0)
+ out_sosi <= out_sosi_arr(0);
- out_bsn <= TO_UINT(out_sosi.bsn); -- = out_bsn_arr().bsn = out_sosi_arr(I).bsn
+ -- = out_bsn_arr().bsn = out_sosi_arr(I).bsn
+ out_bsn <= TO_UINT(out_sosi.bsn);
gen_verify_ctrl : for I in c_nof_streams - 1 downto 0 generate
-- . Verify that sop and eop come in pairs
proc_dp_verify_sop_and_eop(dp_clk, out_val_arr(I), out_sop_arr(I), out_eop_arr(I), hold_out_sop_arr(I));
-- . Verify that the stimuli have been applied at all
- hold_data_arr(I) <= out_data_arr(I) when out_val_arr(I) = '1'; -- hold last valid data
+ -- hold last valid data
+ hold_data_arr(I) <= out_data_arr(I) when out_val_arr(I) = '1';
proc_dp_verify_value("out_data_arr", e_equal, dp_clk, verify_done_arr(I), expected_out_data_arr(I), hold_data_arr(I));
proc_dp_verify_value("out_bsn_arr", e_equal, dp_clk, verify_done_arr(I), expected_out_bsn_arr(I), out_bsn_arr(I));
proc_dp_verify_value("out_channel_arr", e_equal, dp_clk, verify_done_arr(I), expected_out_channel_arr(I), out_channel_arr(I));
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
index 20d75a9e96538e0a879d3c595d753f01ea649bbf..397fca4de1a4551ee607572dbab6025cd0061abd 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
@@ -44,13 +44,15 @@ architecture tb of tb_mmp_dp_bsn_sync_scheduler is
constant c_dp_clk_period : time := 10 ns;
constant c_cross_clock_domain_latency : natural := 20;
- constant c_report_note : boolean := false; -- Use TRUE for tb debugging, else FALSE to keep Transcript window more empty
+ -- Use TRUE for tb debugging, else FALSE to keep Transcript window more empty
+ constant c_report_note : boolean := false;
constant c_nof_input_sync : natural := 10;
constant c_nof_block_per_input_sync : natural := 17;
constant c_nof_block_per_output_sync : natural := 5;
constant c_block_size : natural := 10;
- constant c_ctrl_interval_size_min : natural := 19; -- Minimum interval size to use if MM write interval size is set too small.
+ -- Minimum interval size to use if MM write interval size is set too small.
+ constant c_ctrl_interval_size_min : natural := 19;
constant c_input_gap_size : natural := 3;
constant c_sim_nof_blocks : natural := c_nof_block_per_input_sync * c_nof_input_sync;
@@ -368,9 +370,11 @@ begin
generic map (
g_sync_period => c_nof_block_per_input_sync,
g_err_init => 0,
- g_err_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
+ -- do not increment, to not distract from viewing of BSN in Wave window
+ g_err_incr => 0,
g_channel_init => 0,
- g_channel_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
+ -- do not increment, to not distract from viewing of BSN in Wave window
+ g_channel_incr => 0,
g_nof_repeat => c_sim_nof_blocks,
g_pkt_len => c_block_size,
g_pkt_gap => c_input_gap_size
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
index ad32c921763e7e4f7ca031c48eca53bc3964ff31..1f2baab7297c9f577bb3f2e377e26a26e0d197d4 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
@@ -47,17 +47,23 @@ entity tb_mms_dp_bsn_align is
generic (
g_block_size : natural := 11;
g_diff_delay : natural := 20;
- g_diff_bsn : natural := 3; -- g_diff_bsn = g_bsn_latency can just be aligned
- g_nof_input : natural := 16; -- >= 1
+ -- g_diff_bsn = g_bsn_latency can just be aligned
+ g_diff_bsn : natural := 3;
+ -- >= 1
+ g_nof_input : natural := 16;
g_bsn_latency : natural := 3;
- g_bsn_request_pipeline : natural := 2; -- = 1, 2, ..., c_bsn_nof_stages, requested total pipelining of the BSN max and BSN min operation
- g_out_ready : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
- g_nof_repeat : natural := 100 -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
+ -- = 1, 2, ..., c_bsn_nof_stages, requested total pipelining of the BSN max and BSN min operation
+ g_bsn_request_pipeline : natural := 2;
+ -- always e_active, e_random or e_pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_active;
+ -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
+ g_nof_repeat : natural := 100
);
end tb_mms_dp_bsn_align;
architecture tb of tb_mms_dp_bsn_align is
- constant c_mm_clk_period : time := 20 ns; -- 40 MHz
+ -- 40 MHz
+ constant c_mm_clk_period : time := 20 ns;
constant c_rl : natural := 1;
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 7;
@@ -73,10 +79,13 @@ architecture tb of tb_mms_dp_bsn_align is
constant c_gap_size : natural := 10;
constant c_block_period : natural := g_block_size + c_gap_size;
- constant c_xoff_timeout : natural := c_block_period * g_bsn_latency * 2; -- xoff timeout to recover for next alignment attempt
- constant c_sop_timeout : natural := c_block_period * g_bsn_latency; -- sop timeout to end current aligment attempt
+ -- xoff timeout to recover for next alignment attempt
+ constant c_xoff_timeout : natural := c_block_period * g_bsn_latency * 2;
+ -- sop timeout to end current aligment attempt
+ constant c_sop_timeout : natural := c_block_period * g_bsn_latency;
- constant c_event_input : natural := smallest(1, g_nof_input - 1); -- select special event input at which the event will apply, use >= g_nof_input to disable the special events
+ -- select special event input at which the event will apply, use >= g_nof_input to disable the special events
+ constant c_event_input : natural := smallest(1, g_nof_input - 1);
type t_data_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(c_data_w - 1 downto 0);
type t_bsn_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(c_bsn_w - 1 downto 0);
@@ -93,7 +102,8 @@ architecture tb of tb_mms_dp_bsn_align is
signal mm_clk : std_logic := '1';
signal mm_rst : std_logic := '1';
- signal random : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(15 downto 0) := (others => '0');
signal pulse : std_logic;
signal pulse_en : std_logic := '1';
@@ -141,11 +151,14 @@ architecture tb of tb_mms_dp_bsn_align is
signal verify_extra_end : std_logic := '0';
signal bsn_diff : integer;
signal bsn_offset : integer;
- signal bsn_event : std_logic := '0'; -- pulse '1' triggers a BSN offset for an input
+ -- pulse '1' triggers a BSN offset for an input
+ signal bsn_event : std_logic := '0';
signal bsn_event_ack_arr : std_logic_vector(g_nof_input - 1 downto 0) := (others => '0');
signal bsn_event_ack : std_logic;
- signal in_en_event : std_logic := '0'; -- pulse '1' indicates that the input enables in in_en_arr have been updated
- signal in_en_arr : std_logic_vector(g_nof_input - 1 downto 0) := (others => '1'); -- default all inputs are enabled
+ -- pulse '1' indicates that the input enables in in_en_arr have been updated
+ signal in_en_event : std_logic := '0';
+ -- default all inputs are enabled
+ signal in_en_arr : std_logic_vector(g_nof_input - 1 downto 0) := (others => '1');
signal mm_mosi : t_mem_mosi;
signal mm_miso : t_mem_miso;
@@ -202,14 +215,16 @@ begin
proc_dp_gen_block_data(c_rl, true, c_data_w, c_data_w, v_data, 0, 0, g_block_size, v_channel, v_err, v_sync, v_bsn, clk, in_en_arr(I), in_siso_arr(I), in_sosi_arr(I));
v_bsn := INCR_UVEC(v_bsn, 1);
v_data := v_data + g_block_size;
- proc_common_wait_some_cycles(clk, c_gap_size); -- create gap between frames
+ -- create gap between frames
+ proc_common_wait_some_cycles(clk, c_gap_size);
end loop;
-- End of default stimuli
expected_out_bsn(I) <= INCR_UVEC(v_bsn, -1);
expected_out_data(I) <= TO_UVEC(v_data - 1, c_data_w);
- proc_common_wait_some_cycles(clk, 100); -- depends on stream control
+ -- depends on stream control
+ proc_common_wait_some_cycles(clk, 100);
default_end_arr(I) <= '1';
verify_done_arr(I) <= '1';
proc_common_wait_some_cycles(clk, 1);
@@ -230,7 +245,8 @@ begin
bsn_event_ack_arr(I) <= '1';
end if;
v_data := v_data + g_block_size;
- proc_common_wait_some_cycles(clk, c_gap_size); -- create gap between frames
+ -- create gap between frames
+ proc_common_wait_some_cycles(clk, c_gap_size);
end loop;
-- End of extra stimuli
@@ -327,7 +343,8 @@ begin
verify_dis_arr <= (others => '1');
-- in_en_event <= '1';
- in_en_arr(c_event_input) <= '0'; -- switch an input off
+ -- switch an input off
+ in_en_arr(c_event_input) <= '0';
-- proc_common_wait_some_cycles(clk, 1);
-- in_en_event <= '0';
proc_common_wait_some_cycles(mm_clk, 1);
@@ -335,13 +352,15 @@ begin
proc_common_wait_some_cycles(clk, 100);
verify_dis_arr <= (others => '0');
- proc_common_wait_some_cycles(clk, 2000); -- keep this input off for a while
+ -- keep this input off for a while
+ proc_common_wait_some_cycles(clk, 2000);
tb_state <= s_enable_inputs;
verify_dis_arr <= (others => '1');
-- in_en_event <= '1';
- in_en_arr(c_event_input) <= '1'; -- switch this input on
+ -- switch this input on
+ in_en_arr(c_event_input) <= '1';
-- proc_common_wait_some_cycles(clk, 1);
-- in_en_event <= '0';
proc_common_wait_some_cycles(mm_clk, 1);
@@ -353,7 +372,8 @@ begin
tb_state <= s_restore_bsn;
verify_dis_arr <= (others => '1');
- bsn_offset <= bsn_diff; -- use input 0 to restore original BSN sequence for input c_event_input, that got lost due to input disable
+ -- use input 0 to restore original BSN sequence for input c_event_input, that got lost due to input disable
+ bsn_offset <= bsn_diff;
bsn_event <= '1';
proc_common_wait_until_high(clk, bsn_event_ack);
bsn_event <= '0';
@@ -377,7 +397,8 @@ begin
gen_verify : for I in g_nof_input - 1 downto 0 generate
-- Verification logistics
verify_en_arr(I) <= '1' when rising_edge(clk) and verify_dis_arr(I) = '0' and in_en_arr(I) = '1' and out_sosi_arr(I).sop = '1' else
- '0' when rising_edge(clk) and verify_dis_arr(I) = '1'; -- verify enable after first output sop
+ -- verify enable after first output sop
+ '0' when rising_edge(clk) and verify_dis_arr(I) = '1';
-- Ease in_siso_arr monitoring
in_ready(I) <= in_siso_arr(I).ready;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
index 13cb45b509ea464702b6c627a0a84b91ed24fb89..17d46abb64e5f74c397afb55dbce3df240db8922 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
@@ -58,9 +58,12 @@ architecture tb of tb_mms_dp_bsn_source is
constant c_mm_addr_bsn_lo : natural := 2;
constant c_mm_addr_bsn_hi : natural := 3;
- constant c_mm_dp_off : natural := 0; -- DP off after finishing current block
- constant c_mm_dp_on_immediate : natural := 1; -- DP on immediate by setting bit 0
- constant c_mm_dp_on_at_pps : natural := 3; -- DP on at next PPS by setting bits 1,0
+ -- DP off after finishing current block
+ constant c_mm_dp_off : natural := 0;
+ -- DP on immediate by setting bit 0
+ constant c_mm_dp_on_immediate : natural := 1;
+ -- DP on at next PPS by setting bits 1,0
+ constant c_mm_dp_on_at_pps : natural := 3;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
@@ -88,7 +91,8 @@ begin
-- Write initial BSN and number of block per sync interval
proc_mem_mm_bus_wr(c_mm_addr_bsn_lo, c_init_bsn, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_wr(c_mm_addr_bsn_hi, 0, clk, mm_miso, mm_mosi); -- must also write hi part to trigger transfer accross clock domain
+ -- must also write hi part to trigger transfer accross clock domain
+ proc_mem_mm_bus_wr(c_mm_addr_bsn_hi, 0, clk, mm_miso, mm_mosi);
proc_mem_mm_bus_wr(c_mm_addr_nof_block_per_sync, c_nof_block_per_sync, clk, mm_miso, mm_mosi);
proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
@@ -156,9 +160,11 @@ begin
u_dut : entity work.mms_dp_bsn_source
generic map (
- g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain => true,
g_block_size => c_block_size,
- g_nof_block_per_sync => 1, -- overrule via MM write
+ -- overrule via MM write
+ g_nof_block_per_sync => 1,
g_bsn_w => c_dp_stream_bsn_w
)
port map (
@@ -170,8 +176,10 @@ begin
dp_pps => pps,
-- Memory-mapped clock domain
- reg_mosi => mm_mosi, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
- reg_miso => mm_miso, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
+ -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
+ reg_mosi => mm_mosi,
+ -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
+ reg_miso => mm_miso,
-- Streaming clock domain
bs_sosi => bs_sosi
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
index a17112b675391a6860eea2cd7e987707435a3b99..c9de10ea7975d1cf776d185e66e862fe7fb5bd29 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
@@ -62,9 +62,12 @@ architecture tb of tb_mms_dp_bsn_source_v2 is
constant c_mm_addr_bsn_hi : natural := 3;
constant c_mm_addr_bsn_time_offset : natural := 4;
- constant c_mm_dp_off : natural := 0; -- DP off after finishing current block
- constant c_mm_dp_on_immediate : natural := 1; -- DP on immediate by setting bit 0
- constant c_mm_dp_on_at_pps : natural := 3; -- DP on at next PPS by setting bits 1,0
+ -- DP off after finishing current block
+ constant c_mm_dp_off : natural := 0;
+ -- DP on immediate by setting bit 0
+ constant c_mm_dp_on_immediate : natural := 1;
+ -- DP on at next PPS by setting bits 1,0
+ constant c_mm_dp_on_at_pps : natural := 3;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
@@ -94,7 +97,8 @@ begin
-- Write initial BSN and number of block per sync interval
proc_mem_mm_bus_wr(c_mm_addr_bsn_lo, c_bsn_init, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_wr(c_mm_addr_bsn_hi, 0, clk, mm_miso, mm_mosi); -- must also write hi part to trigger transfer accross clock domain
+ -- must also write hi part to trigger transfer accross clock domain
+ proc_mem_mm_bus_wr(c_mm_addr_bsn_hi, 0, clk, mm_miso, mm_mosi);
proc_mem_mm_bus_wr(c_mm_addr_nof_block_per_sync, c_nof_block_per_sync, clk, mm_miso, mm_mosi);
proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
@@ -181,9 +185,11 @@ begin
u_dut : entity work.mms_dp_bsn_source_v2
generic map (
- g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain => true,
g_block_size => c_block_size,
- g_nof_clk_per_sync => 200 * 10**6, -- overrule via MM write
+ -- overrule via MM write
+ g_nof_clk_per_sync => 200 * 10**6,
g_bsn_w => c_dp_stream_bsn_w
)
port map (
@@ -195,8 +201,10 @@ begin
dp_pps => pps,
-- Memory-mapped clock domain
- reg_mosi => mm_mosi, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
- reg_miso => mm_miso, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
+ -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
+ reg_mosi => mm_mosi,
+ -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
+ reg_miso => mm_miso,
-- Streaming clock domain
bs_sosi => bs_sosi
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd
index f37559d35294d2e80d2fbac675d336b5234596fa..5018c44d55784bdfdbf5290481570253b681a534 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd
@@ -34,13 +34,19 @@ architecture tb of tb_mms_dp_fields is
constant clk_period : time := 10 ns;
constant c_delay_len : natural := 3;
- constant c_field_arr : t_common_field_arr(2 downto 0) := (( field_name_pad("test_field_2"), "RW", 36, field_default(x"BADC0DE56") ), -- 0xCAFEDEADB
- ( field_name_pad("test_field_1"), "RO", 8, field_default(x"AA") ), -- 0xEE
- ( field_name_pad("test_field_0"), "RO", 4, field_default(x"B") )); -- 0xF
-
- constant c_field_arr2: t_common_field_arr(2 downto 0) := (( field_name_pad("test_field_2"), "RO", 4 , field_default(x"B")), -- 0xF
- ( field_name_pad("test_field_1"), "RO", 8 , field_default(x"AA")), -- 0xEE
- ( field_name_pad("test_field_0"), "RW", 36, field_default(x"BADC0DE56"))); -- 0xCAFEDEADB
+ -- 0xCAFEDEADB
+ constant c_field_arr : t_common_field_arr(2 downto 0) := (( field_name_pad("test_field_2"), "RW", 36, field_default(x"BADC0DE56") ),
+ -- 0xEE
+ ( field_name_pad("test_field_1"), "RO", 8, field_default(x"AA") ),
+ -- 0xF
+ ( field_name_pad("test_field_0"), "RO", 4, field_default(x"B") ));
+
+ -- 0xF
+ constant c_field_arr2: t_common_field_arr(2 downto 0) := (( field_name_pad("test_field_2"), "RO", 4 , field_default(x"B")),
+ -- 0xEE
+ ( field_name_pad("test_field_1"), "RO", 8 , field_default(x"AA")),
+ -- 0xCAFEDEADB
+ ( field_name_pad("test_field_0"), "RW", 36, field_default(x"BADC0DE56")));
signal clk : std_logic := '0';
signal rst : std_logic := '1';
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd
index 006cf2502a0dd7604329f506e1cebcf9c53d239a..0e1f83649ae6b8e87c932a624234811387b66c97 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd
@@ -54,9 +54,11 @@ entity tb_mms_dp_fifo_fill is
g_dut_use_empty : boolean := false;
g_dut_use_channel : boolean := false;
g_dut_use_sync : boolean := false;
- g_dut_fifo_rl : natural := 1; -- internal RL, use 0 for look ahead FIFO, default 1 for normal FIFO
+ -- internal RL, use 0 for look ahead FIFO, default 1 for normal FIFO
+ g_dut_fifo_rl : natural := 1;
g_dut_fifo_size : natural := 64;
- g_dut_fifo_fill : natural := 40 -- selectable >= 0 for dp_fifo_fill
+ -- selectable >= 0 for dp_fifo_fill
+ g_dut_fifo_fill : natural := 40
);
end tb_mms_dp_fifo_fill;
@@ -124,7 +126,8 @@ begin
proc_common_wait_some_cycles(dp_clk, 1);
end loop;
end loop;
- wait; -- add void WAIT statement to avoid (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+ -- add void WAIT statement to avoid (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+ wait;
end process;
gen_connect : for I in 0 to g_nof_streams - 1 generate
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd
index 3ec6d1732919742453554344f93c588e96728474..112a2499c66c1e83f11b92287a3025a80687faf1 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd
@@ -42,20 +42,28 @@ use technology_lib.technology_select_pkg.all;
entity tb_mms_dp_force_data_parallel_arr is
generic (
- g_flow_control_stimuli : t_dp_flow_control_enum := e_random; -- always active or random stimuli valid flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random verify ready flow control
- g_nof_streams : natural := 1; -- >= 1
- g_dat_w : natural := 5; -- must be <= 32 to fit INTEGER range
- g_force_stream : integer := 0; -- must be < g_nof_streams, force data on this stream
+ -- always active or random stimuli valid flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_random;
+ -- always active or random verify ready flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
+ -- >= 1
+ g_nof_streams : natural := 1;
+ -- must be <= 32 to fit INTEGER range
+ g_dat_w : natural := 5;
+ -- must be < g_nof_streams, force data on this stream
+ g_force_stream : integer := 0;
g_force_data : integer := -7;
g_force_re : integer := 3;
g_force_im : integer := -5;
g_increment_data : integer := 1;
g_increment_re : integer := 0;
g_increment_im : integer := 0;
- g_increment_on_sop : boolean := false; -- in this tb use same generic for data, re, im
- g_restart_on_sync : boolean := false; -- in this tb use same generic for data, re, im
- g_restart_on_sop : boolean := false -- in this tb use same generic for data, re, im
+ -- in this tb use same generic for data, re, im
+ g_increment_on_sop : boolean := false;
+ -- in this tb use same generic for data, re, im
+ g_restart_on_sync : boolean := false;
+ -- in this tb use same generic for data, re, im
+ g_restart_on_sop : boolean := false
);
end tb_mms_dp_force_data_parallel_arr;
@@ -65,13 +73,16 @@ architecture tb of tb_mms_dp_force_data_parallel_arr is
constant c_cross_clock_domain_latency : natural := 20;
constant c_init_data : integer := 0;
- constant c_init_channel : integer := 11; -- use recognizable value, will not change
- constant c_init_error : integer := 12; -- use recognizable value, will not change
+ -- use recognizable value, will not change
+ constant c_init_channel : integer := 11;
+ -- use recognizable value, will not change
+ constant c_init_error : integer := 12;
constant c_nof_data_per_block : integer := 17;
constant c_nof_block_per_sync : integer := 10;
constant c_nof_blocks_per_test : integer := c_nof_block_per_sync * 3;
- constant c_mm_reg_span : natural := 4; -- = 2**c_mm_reg.adr_w, span per stream
+ -- = 2**c_mm_reg.adr_w, span per stream
+ constant c_mm_reg_span : natural := 4;
constant c_force_en : natural := 1;
constant c_force_dis : natural := 0;
@@ -81,8 +92,10 @@ architecture tb of tb_mms_dp_force_data_parallel_arr is
signal dp_clk : std_logic := '1';
signal dp_rst : std_logic := '1';
- signal random_valid : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_ready : std_logic_vector(16 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_valid : std_logic_vector(15 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_ready : std_logic_vector(16 downto 0) := (others => '0');
signal stimuli_en : std_logic := '0';
signal verify_en : std_logic := '0';
signal force_en : std_logic := '0';
@@ -133,8 +146,10 @@ begin
-- Generate packets
while tb_end = '0' loop
- v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_nof_block_per_sync) = 0, '1', '0'); -- insert sync starting at BSN=0 and with period g_sync_period
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_dat_w - 1 downto 0)); -- wrap when >= 2**g_dat_w
+ -- insert sync starting at BSN=0 and with period g_sync_period
+ v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_nof_block_per_sync) = 0, '1', '0');
+ -- wrap when >= 2**g_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_dat_w - 1 downto 0));
-- Send block
proc_dp_gen_block_data(g_dat_w, c_init_data, c_nof_data_per_block, c_init_channel, c_init_error, v_sosi.sync, v_sosi.bsn, dp_clk, stimuli_en, snk_out, snk_in);
-- Prepare for next block
@@ -145,12 +160,15 @@ begin
wait;
end process;
- snk_in_re <= func_dp_stream_set_data(snk_in, INCR_UVEC(snk_in.data, 1), "RE"); -- apply re = data+1
- snk_in_complex <= func_dp_stream_set_data(snk_in_re, INCR_UVEC(snk_in.data, 2), "IM"); -- apply im = data+2
+ -- apply re = data+1
+ snk_in_re <= func_dp_stream_set_data(snk_in, INCR_UVEC(snk_in.data, 1), "RE");
+ -- apply im = data+2
+ snk_in_complex <= func_dp_stream_set_data(snk_in_re, INCR_UVEC(snk_in.data, 2), "IM");
u_snk_in_complex_dly : entity work.dp_pipeline
generic map (
- g_pipeline => 1 -- latency of DUT
+ -- latency of DUT
+ g_pipeline => 1
)
port map (
rst => dp_rst,
@@ -161,8 +179,10 @@ begin
src_out => snk_in_complex_dly
);
- snk_out <= snk_out_arr(0); -- use stream 0 for flow control, all tb streams have same flow control
- snk_in_arr <= (others => snk_in_complex); -- apply same default tb data to all streams
+ -- use stream 0 for flow control, all tb streams have same flow control
+ snk_out <= snk_out_arr(0);
+ -- apply same default tb data to all streams
+ snk_in_arr <= (others => snk_in_complex);
p_stimuli_mm : process
variable v_force_data : integer := g_force_data;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd
index 4b9c1555db8bd952e4309078712723405c2ee357..3d697f74eef0486f92beff09a379c897352fb50b 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd
@@ -42,18 +42,27 @@ use technology_lib.technology_select_pkg.all;
entity tb_mms_dp_force_data_serial_arr is
generic (
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random verify ready flow control
- g_nof_streams : natural := 3; -- >= 1
- g_dat_w : natural := 16; -- must be <= 32 to fit INTEGER range
- g_force_stream : integer := 1; -- must be < g_nof_streams, force data on this stream
- g_force_value : boolean := true; -- when TRUE force value at index, else pass on snk_in at index
- g_force_index : natural := 7; -- sample index or block index in time dependent on g_index_sample_block_n
+ -- always active or random stimuli valid flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ -- always active or random verify ready flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
+ -- >= 1
+ g_nof_streams : natural := 3;
+ -- must be <= 32 to fit INTEGER range
+ g_dat_w : natural := 16;
+ -- must be < g_nof_streams, force data on this stream
+ g_force_stream : integer := 1;
+ -- when TRUE force value at index, else pass on snk_in at index
+ g_force_value : boolean := true;
+ -- sample index or block index in time dependent on g_index_sample_block_n
+ g_force_index : natural := 7;
g_force_data : integer := -1;
g_force_re : integer := 2;
g_force_im : integer := -3;
- g_index_period : natural := 17; -- number of indices in time, must be <= 2*31 to fit in NATURAL range
- g_index_sample_block_n : boolean := false -- when TRUE sample index in block, else block index in sync interval
+ -- number of indices in time, must be <= 2*31 to fit in NATURAL range
+ g_index_period : natural := 17;
+ -- when TRUE sample index in block, else block index in sync interval
+ g_index_sample_block_n : boolean := false
);
end tb_mms_dp_force_data_serial_arr;
@@ -63,13 +72,16 @@ architecture tb of tb_mms_dp_force_data_serial_arr is
constant c_cross_clock_domain_latency : natural := 20;
constant c_init_data : integer := 0;
- constant c_init_channel : integer := 11; -- use recognizable value, will not change
- constant c_init_error : integer := 12; -- use recognizable value, will not change
+ -- use recognizable value, will not change
+ constant c_init_channel : integer := 11;
+ -- use recognizable value, will not change
+ constant c_init_error : integer := 12;
constant c_nof_data_per_block : integer := g_index_period;
constant c_nof_block_per_sync : integer := g_index_period;
constant c_nof_blocks_per_test : integer := c_nof_block_per_sync * 3;
- constant c_mm_reg_span : natural := 8; -- = 2**c_mm_reg.adr_w, span per stream
+ -- = 2**c_mm_reg.adr_w, span per stream
+ constant c_mm_reg_span : natural := 8;
signal tb_end : std_logic := '0';
signal mm_clk : std_logic := '1';
@@ -77,8 +89,10 @@ architecture tb of tb_mms_dp_force_data_serial_arr is
signal dp_clk : std_logic := '1';
signal dp_rst : std_logic := '1';
- signal random_valid : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_ready : std_logic_vector(16 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_valid : std_logic_vector(15 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_ready : std_logic_vector(16 downto 0) := (others => '0');
signal stimuli_en : std_logic := '0';
signal verify_en : std_logic := '0';
signal force_en : std_logic := '0';
@@ -131,8 +145,10 @@ begin
-- Generate packets
while tb_end = '0' loop
- v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_nof_block_per_sync) = 0, '1', '0'); -- insert sync starting at BSN=0 and with period g_sync_period
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_dat_w - 1 downto 0)); -- wrap when >= 2**g_dat_w
+ -- insert sync starting at BSN=0 and with period g_sync_period
+ v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_nof_block_per_sync) = 0, '1', '0');
+ -- wrap when >= 2**g_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_dat_w - 1 downto 0));
-- Send block
proc_dp_gen_block_data(g_dat_w, c_init_data, c_nof_data_per_block, c_init_channel, c_init_error, v_sosi.sync, v_sosi.bsn, dp_clk, stimuli_en, snk_out, snk_in);
-- Prepare for next block
@@ -143,12 +159,15 @@ begin
wait;
end process;
- snk_in_re <= func_dp_stream_set_data(snk_in, INCR_UVEC(snk_in.data, 1), "RE"); -- apply re = data+1
- snk_in_complex <= func_dp_stream_set_data(snk_in_re, INCR_UVEC(snk_in.data, 2), "IM"); -- apply im = data+2
+ -- apply re = data+1
+ snk_in_re <= func_dp_stream_set_data(snk_in, INCR_UVEC(snk_in.data, 1), "RE");
+ -- apply im = data+2
+ snk_in_complex <= func_dp_stream_set_data(snk_in_re, INCR_UVEC(snk_in.data, 2), "IM");
u_snk_in_complex_dly : entity work.dp_pipeline
generic map (
- g_pipeline => 1 -- latency of DUT
+ -- latency of DUT
+ g_pipeline => 1
)
port map (
rst => dp_rst,
@@ -159,8 +178,10 @@ begin
src_out => snk_in_complex_dly
);
- snk_out <= snk_out_arr(0); -- use stream 0 for flow control, all tb streams have same flow control
- snk_in_arr <= (others => snk_in_complex); -- apply same default tb data to all streams
+ -- use stream 0 for flow control, all tb streams have same flow control
+ snk_out <= snk_out_arr(0);
+ -- apply same default tb data to all streams
+ snk_in_arr <= (others => snk_in_complex);
p_stimuli_mm : process
variable v_force_data : integer := g_force_data;
@@ -222,7 +243,8 @@ begin
variable v_index : natural;
begin
if rising_edge(dp_clk) then
- dbg_index <= v_index; -- signal dbg_index is one clk cycle off
+ -- signal dbg_index is one clk cycle off
+ dbg_index <= v_index;
-- Start block
if g_index_sample_block_n = true then
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
index 17f42645099e64f6308b8cf4ada29af437ac11ac..80c6800170cbdb1efa2813a0eb6593efb1fed223 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
@@ -42,8 +42,10 @@ use technology_lib.technology_select_pkg.all;
entity tb_mms_dp_gain_arr is
generic (
g_technology : natural := c_tech_select_default;
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
- g_nof_streams : natural := 1; -- >= 1
+ -- always active or random stimuli valid flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ -- >= 1
+ g_nof_streams : natural := 1;
g_complex_data : boolean := true;
g_complex_gain : boolean := false
);
@@ -55,16 +57,22 @@ architecture tb of tb_mms_dp_gain_arr is
constant c_cross_clock_domain_latency : natural := 20;
constant c_real_multiply : boolean := g_complex_data = false and g_complex_gain = false;
- constant c_gain_w : natural := 8; -- from MM
+ -- from MM
+ constant c_gain_w : natural := 8;
constant c_gain_max : integer := 2**(c_gain_w - 1) - 1;
- constant c_gain_min : integer := -2**(c_gain_w - 1) + 1; -- do not use most negative value to allow skipping double sign in gain*in_dat product
- constant c_gain_re_sequence_arr : t_integer_arr(0 to 3) := (c_gain_max, c_gain_max - 3, c_gain_min, c_gain_min + 3); -- some complex/real test gains
- constant c_gain_im_sequence_arr : t_integer_arr(0 to 3) := ( 0, 3, 0, -3); -- some complex test gains
- constant c_in_dat_w : natural := 9; -- streaming data
+ -- do not use most negative value to allow skipping double sign in gain*in_dat product
+ constant c_gain_min : integer := -2**(c_gain_w - 1) + 1;
+ -- some complex/real test gains
+ constant c_gain_re_sequence_arr : t_integer_arr(0 to 3) := (c_gain_max, c_gain_max - 3, c_gain_min, c_gain_min + 3);
+ -- some complex test gains
+ constant c_gain_im_sequence_arr : t_integer_arr(0 to 3) := ( 0, 3, 0, -3);
+ -- streaming data
+ constant c_in_dat_w : natural := 9;
constant c_in_length : integer := 2**c_in_dat_w;
constant c_in_max : integer := 2**(c_in_dat_w - 1) - 1;
constant c_in_min : integer := -2**(c_in_dat_w - 1);
- constant c_out_dat_w : natural := c_gain_w + c_in_dat_w - 1; -- skip double sign bit and assume complex gain amplitude <= 1
+ -- skip double sign bit and assume complex gain amplitude <= 1
+ constant c_out_dat_w : natural := c_gain_w + c_in_dat_w - 1;
signal dbg_nof_streams : natural := g_nof_streams;
signal dbg_complex_data : boolean := g_complex_data;
@@ -76,7 +84,8 @@ architecture tb of tb_mms_dp_gain_arr is
signal dp_clk : std_logic := '1';
signal dp_rst : std_logic := '1';
- signal random : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(15 downto 0) := (others => '0');
signal stimuli_en : std_logic := '0';
signal verify_en : std_logic := '0';
@@ -120,11 +129,13 @@ begin
in_sosi.im <= RESIZE_DP_DSP_DATA(cnt_im);
in_sosi.valid <= cnt_val;
- in_sosi_arr <= (others => in_sosi); -- use same data on all input streams
+ -- use same data on all input streams
+ in_sosi_arr <= (others => in_sosi);
u_in_sosi_dly : entity work.dp_pipeline
generic map (
- g_pipeline => 3 -- latency of DUT
+ -- latency of DUT
+ g_pipeline => 3
)
port map (
rst => dp_rst,
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
index 5c3eb335710ae69024aace5541034dd4cbbeed2a..225b075a54d90614109d2be1363d24900525fb6b 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
@@ -41,9 +41,12 @@ use technology_lib.technology_select_pkg.all;
entity tb_mms_dp_gain_serial_arr is
generic (
g_technology : natural := c_tech_select_default;
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
- g_nof_streams : natural := 3; -- >= 1
- g_nof_gains : natural := 117; -- number of gains in series per stream
+ -- always active or random stimuli valid flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ -- >= 1
+ g_nof_streams : natural := 3;
+ -- number of gains in series per stream
+ g_nof_gains : natural := 117;
g_complex_data : boolean := false;
g_complex_gain : boolean := false
);
@@ -53,20 +56,25 @@ architecture tb of tb_mms_dp_gain_serial_arr is
constant c_mm_clk_period : time := 20 ns;
constant c_dp_clk_period : time := 10 ns;
constant c_cross_clock_domain_latency : natural := 20;
- constant c_dut_latency : natural := 5; -- = 3 for the real or complex multiplier + 2 for the RAM read latency
+ -- = 3 for the real or complex multiplier + 2 for the RAM read latency
+ constant c_dut_latency : natural := 5;
constant c_real_multiply : boolean := g_complex_data = false and g_complex_gain = false;
constant c_nof_gains_w : natural := ceil_log2(g_nof_gains);
constant c_nof_gains_span : natural := 2**c_nof_gains_w;
- constant c_gain_w : natural := 8; -- from MM : <= 32 for real, <= 16 for complex to fit 32b MM data
+ -- from MM : <= 32 for real, <= 16 for complex to fit 32b MM data
+ constant c_gain_w : natural := 8;
constant c_gain_max : integer := 2**(c_gain_w - 1) - 1;
- constant c_gain_min : integer := -2**(c_gain_w - 1) + 1; -- do not use most negative value to allow skipping double sign in gain*in_dat product
+ -- do not use most negative value to allow skipping double sign in gain*in_dat product
+ constant c_gain_min : integer := -2**(c_gain_w - 1) + 1;
- constant c_in_dat_w : natural := 9; -- streaming data
+ -- streaming data
+ constant c_in_dat_w : natural := 9;
constant c_in_length : integer := 2**c_in_dat_w;
constant c_in_max : integer := 2**(c_in_dat_w - 1) - 1;
constant c_in_min : integer := -2**(c_in_dat_w - 1);
- constant c_out_dat_w : natural := c_gain_w + c_in_dat_w - 1; -- skip double sign bit and assume complex gain amplitude <= 1
+ -- skip double sign bit and assume complex gain amplitude <= 1
+ constant c_out_dat_w : natural := c_gain_w + c_in_dat_w - 1;
constant c_int_gain_re : integer := c_gain_max - 1;
constant c_int_gain_im : integer := -1;
@@ -85,7 +93,8 @@ architecture tb of tb_mms_dp_gain_serial_arr is
signal dp_clk : std_logic := '1';
signal dp_rst : std_logic := '1';
- signal random : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(15 downto 0) := (others => '0');
signal stimuli_en : std_logic := '0';
signal in_en : std_logic := '0';
signal verify_en : std_logic := '0';
@@ -99,12 +108,16 @@ architecture tb of tb_mms_dp_gain_serial_arr is
signal in_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal out_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal exp_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal gains_re_arr : t_integer_arr(g_nof_streams - 1 downto 0) := (others => c_int_gain_re); -- default gain for all parallel streams and serial addresses
- signal gains_im_arr : t_integer_arr(g_nof_streams - 1 downto 0) := (others => c_int_gain_im); -- default gain for all parallel streams and serial addresses
+ -- default gain for all parallel streams and serial addresses
+ signal gains_re_arr : t_integer_arr(g_nof_streams - 1 downto 0) := (others => c_int_gain_re);
+ -- default gain for all parallel streams and serial addresses
+ signal gains_im_arr : t_integer_arr(g_nof_streams - 1 downto 0) := (others => c_int_gain_im);
- signal ram_gains_mosi : t_mem_mosi := c_mem_mosi_rst; -- MM write side, im&re
+ -- MM write side, im&re
+ signal ram_gains_mosi : t_mem_mosi := c_mem_mosi_rst;
signal ram_gains_miso : t_mem_miso;
- signal gains_rd_address : std_logic_vector(c_nof_gains_w - 1 downto 0) := TO_UVEC(0, c_nof_gains_w); -- DP read side, same read address for all streams
+ -- DP read side, same read address for all streams
+ signal gains_rd_address : std_logic_vector(c_nof_gains_w - 1 downto 0) := TO_UVEC(0, c_nof_gains_w);
signal gains_rd_address_dly : std_logic_vector(c_nof_gains_w - 1 downto 0);
begin
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
@@ -130,7 +143,8 @@ begin
in_sosi.im <= RESIZE_DP_DSP_DATA(cnt_im);
in_sosi.valid <= cnt_val;
- in_sosi_arr <= (others => in_sosi); -- use same data on all input streams
+ -- use same data on all input streams
+ in_sosi_arr <= (others => in_sosi);
p_clk : process(dp_clk)
begin
@@ -257,14 +271,17 @@ begin
u_dut_one : entity work.mms_dp_gain_serial
generic map (
g_technology => c_tech_select_default,
- g_nof_gains => g_nof_gains, -- number of gains in series per stream
+ -- number of gains in series per stream
+ g_nof_gains => g_nof_gains,
g_complex_data => g_complex_data,
g_complex_gain => g_complex_gain,
g_gain_w => c_gain_w,
g_in_dat_w => c_in_dat_w,
g_out_dat_w => c_out_dat_w,
- g_gains_file_name => "UNUSED", -- "UNUSED" or relative path to some "gains_#.hex" file, where # is the stream index
- g_gains_write_only => false -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode to save memory. When FALSE it is True Dual Port.
+ -- "UNUSED" or relative path to some "gains_#.hex" file, where # is the stream index
+ g_gains_file_name => "UNUSED",
+ -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode to save memory. When FALSE it is True Dual Port.
+ g_gains_write_only => false
)
port map (
-- System
@@ -274,11 +291,13 @@ begin
dp_clk => dp_clk,
-- MM interface
- ram_gains_mosi => ram_gains_mosi, -- write side
+ -- write side
+ ram_gains_mosi => ram_gains_mosi,
ram_gains_miso => ram_gains_miso,
-- ST interface
- gains_rd_address => gains_rd_address, -- read side, same read address for all streams
+ -- read side, same read address for all streams
+ gains_rd_address => gains_rd_address,
in_sosi => in_sosi_arr(0),
out_sosi => out_sosi_arr(0)
@@ -290,14 +309,17 @@ begin
generic map (
g_technology => c_tech_select_default,
g_nof_streams => g_nof_streams,
- g_nof_gains => g_nof_gains, -- number of gains in series per stream
+ -- number of gains in series per stream
+ g_nof_gains => g_nof_gains,
g_complex_data => g_complex_data,
g_complex_gain => g_complex_gain,
g_gain_w => c_gain_w,
g_in_dat_w => c_in_dat_w,
g_out_dat_w => c_out_dat_w,
- g_gains_file_name => "UNUSED", -- "UNUSED" or relative path to some "gains_#.hex" file, where # is the stream index
- g_gains_write_only => false -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode to save memory. When FALSE it is True Dual Port.
+ -- "UNUSED" or relative path to some "gains_#.hex" file, where # is the stream index
+ g_gains_file_name => "UNUSED",
+ -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode to save memory. When FALSE it is True Dual Port.
+ g_gains_write_only => false
)
port map (
-- System
@@ -307,11 +329,13 @@ begin
dp_clk => dp_clk,
-- MM interface
- ram_gains_mosi => ram_gains_mosi, -- write side
+ -- write side
+ ram_gains_mosi => ram_gains_mosi,
ram_gains_miso => ram_gains_miso,
-- ST interface
- gains_rd_address => gains_rd_address, -- read side, same read address for all streams
+ -- read side, same read address for all streams
+ gains_rd_address => gains_rd_address,
in_sosi_arr => in_sosi_arr,
out_sosi_arr => out_sosi_arr
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd
index 869118a7093356714846a9b1b875edcf20b6b106..c764c17cfd0d7cdf32f9b5832fc3a4a4fc29fa64 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd
@@ -52,7 +52,8 @@ architecture tb of tb_mms_dp_scale is
constant c_complex_gain : boolean := false;
constant c_gain_w : natural := 8;
constant c_in_dat_w : natural := 9;
- constant c_in_length : integer := 2**(c_in_dat_w - 3) - 1; -- Expected sosi does not take clipping into account
+ -- Expected sosi does not take clipping into account
+ constant c_in_length : integer := 2**(c_in_dat_w - 3) - 1;
constant c_in_max : integer := 2**(c_in_dat_w - 3) - 1;
constant c_in_min : integer := -2**(c_in_dat_w - 3);
constant c_out_dat_w : natural := c_in_dat_w;
@@ -108,7 +109,8 @@ begin
u_in_sosi_dly : entity work.dp_pipeline
generic map (
- g_pipeline => 3 -- latency of DUT
+ -- latency of DUT
+ g_pipeline => 3
)
port map (
rst => dp_rst,
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
index 16982fd0cd2d2d5cb093db045f5c484db15be653..861877ae40106d79e4f8faea4d0e4d25efb8741e 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
@@ -48,22 +48,28 @@ use work.tb_dp_pkg.all;
entity tb_mms_dp_sync_checker is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
g_in_dat_w : natural := 32;
g_in_nof_words : natural := 1;
g_nof_repeat : natural := 100;
- g_pkt_len : natural := 16; -- must be a multiple of g_in_nof_words
+ -- must be a multiple of g_in_nof_words
+ g_pkt_len : natural := 16;
g_pkt_gap : natural := 0;
- g_sync_period : natural := 17; -- 15 for early syncs. 17 for late syncs. The sync period generated in the stimuli.
+ -- 15 for early syncs. 17 for late syncs. The sync period generated in the stimuli.
+ g_sync_period : natural := 17;
-- DUT
- g_nof_blk_per_sync : positive := 16 -- The sync period as expected by the sync_checker
+ -- The sync period as expected by the sync_checker
+ g_nof_blk_per_sync : positive := 16
);
end tb_mms_dp_sync_checker;
architecture tb of tb_mms_dp_sync_checker is
- constant c_mm_clk_period : time := 30 ns; -- 40 MHz
+ -- 40 MHz
+ constant c_mm_clk_period : time := 30 ns;
constant c_rl : natural := 1;
constant c_no_dut : boolean := true;
@@ -75,11 +81,14 @@ architecture tb of tb_mms_dp_sync_checker is
constant c_gap : natural := sel_a_b(g_sync_period >= g_nof_blk_per_sync, g_sync_period - g_nof_blk_per_sync, 2 * g_sync_period - g_nof_blk_per_sync);
constant c_gapsize : positive := c_gap * g_pkt_len + 1;
- constant c_data_max : unsigned(g_in_dat_w - 1 downto 0) := to_unsigned(0, g_in_dat_w); -- no wrap detection
+ -- no wrap detection
+ constant c_data_max : unsigned(g_in_dat_w - 1 downto 0) := to_unsigned(0, g_in_dat_w);
constant c_data_init : integer := -1;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
- constant c_channel_init : integer := 5; -- fixed
+ -- fixed
+ constant c_channel_init : integer := 5;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
@@ -89,8 +98,10 @@ architecture tb of tb_mms_dp_sync_checker is
signal sl1 : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -109,7 +120,8 @@ architecture tb of tb_mms_dp_sync_checker is
signal prev_verify_snk_out : t_dp_siso;
signal verify_snk_out : t_dp_siso := c_dp_siso_rdy;
signal verify_snk_in : t_dp_sosi;
- signal verify_snk_in_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0); -- used to hold valid data for verify at verify_done
+ -- used to hold valid data for verify at verify_done
+ signal verify_snk_in_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0);
signal verify_data : std_logic_vector(g_in_dat_w - 1 downto 0);
signal prev_verify_snk_in : t_dp_sosi;
@@ -170,10 +182,12 @@ begin
for I in 0 to g_nof_repeat - 1 loop
-- Auto increment v_sosi field values for this packet
v_sosi.bsn := INCR_UVEC(v_sosi.bsn, 1);
- v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod g_sync_period) = c_sync_offset, '1', '0'); -- insert sync starting at BSN=c_sync_offset and with period g_sync_period
+ -- insert sync starting at BSN=c_sync_offset and with period g_sync_period
+ v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod g_sync_period) = c_sync_offset, '1', '0');
v_sosi.channel := INCR_UVEC(v_sosi.channel, 1);
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
v_sosi.err := INCR_UVEC(v_sosi.err, 1);
-- Send packet
@@ -190,11 +204,13 @@ begin
v_sosi.err := TO_DP_ERROR(c_err_init + g_nof_repeat - 1);
-- . account for g_pkt_len
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len - 1);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
expected_verify_snk_in <= v_sosi;
-- Signal end of stimuli
- proc_common_wait_some_cycles(clk, 100); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ proc_common_wait_some_cycles(clk, 100);
proc_common_gen_pulse(clk, verify_done);
proc_common_wait_some_cycles(clk, 50);
tb_end <= '1';
@@ -233,10 +249,12 @@ begin
proc_common_wait_some_cycles(mm_clk, 290);
-- read to verify nof syncs
- proc_mem_mm_bus_rd(0, mm_clk, mm_mosi); -- Read nof_early_syncs
+ -- Read nof_early_syncs
+ proc_mem_mm_bus_rd(0, mm_clk, mm_mosi);
proc_common_wait_some_cycles(mm_clk, 1);
mm_nof_early_syncs <= mm_miso.rddata(c_word_w - 1 downto 0);
- proc_mem_mm_bus_rd(1, mm_clk, mm_mosi); -- Read nof_late_syncs
+ -- Read nof_late_syncs
+ proc_mem_mm_bus_rd(1, mm_clk, mm_mosi);
proc_common_wait_some_cycles(mm_clk, 1);
mm_nof_late_syncs <= mm_miso.rddata(c_word_w - 1 downto 0);
proc_common_wait_some_cycles(mm_clk, 1);
@@ -245,10 +263,12 @@ begin
assert TO_UINT(mm_nof_late_syncs) > 0 report "Unexpected mm_nof_late_syncs" severity ERROR;
-- read again to verify clear after rd
- proc_mem_mm_bus_rd(0, mm_clk, mm_mosi); -- Read nof_early_syncs
+ -- Read nof_early_syncs
+ proc_mem_mm_bus_rd(0, mm_clk, mm_mosi);
proc_common_wait_some_cycles(mm_clk, 1);
mm_nof_early_syncs <= mm_miso.rddata(c_word_w - 1 downto 0);
- proc_mem_mm_bus_rd(1, mm_clk, mm_mosi); -- Read nof_late_syncs
+ -- Read nof_late_syncs
+ proc_mem_mm_bus_rd(1, mm_clk, mm_mosi);
proc_common_wait_some_cycles(mm_clk, 1);
mm_nof_late_syncs <= mm_miso.rddata(c_word_w - 1 downto 0);
proc_common_wait_some_cycles(mm_clk, 1);
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd
index 25c9376f2c966daf026e5145b91bff0f0b88cdda..ba2e190027b6dbd7a245cb972ff64bac8fbbad87 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd
@@ -48,14 +48,17 @@ use work.tb_dp_pkg.all;
entity tb_mms_dp_xonoff is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse;
+ -- always active, random or pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
g_combine_streams : boolean := false;
g_in_dat_w : natural := 32;
g_in_nof_words : natural := 1;
g_nof_repeat : natural := 60;
- g_pkt_len : natural := 16; -- must be a multiple of g_in_nof_words
+ -- must be a multiple of g_in_nof_words
+ g_pkt_len : natural := 16;
g_pkt_gap : natural := 4
);
end tb_mms_dp_xonoff;
@@ -71,9 +74,11 @@ architecture tb of tb_mms_dp_xonoff is
constant c_data_max : unsigned(g_in_dat_w - 1 downto 0) := (others => '1');
constant c_data_init : integer := -1;
- constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000"; -- X"0877665544332211"
+ -- X"0877665544332211"
+ constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
constant c_err_init : natural := 247;
- constant c_channel_init : integer := 5; -- fixed
+ -- fixed
+ constant c_channel_init : integer := 5;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
@@ -121,10 +126,12 @@ begin
for I in 0 to g_nof_repeat - 1 loop
-- Auto increment v_sosi field values for this packet
v_sosi.bsn := INCR_UVEC(v_sosi.bsn, 1);
- v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_sync_period) = c_sync_offset, '1', '0'); -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+ v_sosi.sync := sel_a_b((unsigned(v_sosi.bsn) mod c_sync_period) = c_sync_offset, '1', '0');
v_sosi.channel := INCR_UVEC(v_sosi.channel, 1);
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
v_sosi.err := INCR_UVEC(v_sosi.err, 1);
-- Send packet
@@ -141,10 +148,12 @@ begin
v_sosi.err := TO_DP_ERROR(c_err_init + g_nof_repeat - 1);
-- . account for g_pkt_len
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len - 1);
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
+ -- wrap when >= 2**g_in_dat_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w - 1 downto 0));
-- Signal end of stimuli
- proc_common_wait_some_cycles(clk, 100); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+ proc_common_wait_some_cycles(clk, 100);
proc_common_wait_some_cycles(clk, 50);
tb_end <= '1';
wait;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd
index 85eb2eafed9aa8456f06fddad6a6f9d1d65e8802..76635cf089ee959aa7e26e7a2b1c03aaf7183f44 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd
@@ -31,7 +31,8 @@ entity tb_tb2_dp_demux is
end tb_tb2_dp_demux;
architecture tb of tb_tb2_dp_demux is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- in_en, src_in.ready, in_channel, nof_repeat, nof_streams, mode_demux, mode_mux, use_channel_lo, combined_demux
-- Framed mode 0
diff --git a/libraries/base/dp/tb/vhdl/tb_tb2_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb_tb2_dp_mux.vhd
index a82257f8883763a4693ac6d6b4d3bb5d02c8c525..e705cf0f62b1f8754936912548fc6fd3b0e983e9 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb2_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb2_dp_mux.vhd
@@ -32,7 +32,8 @@ end tb_tb2_dp_mux;
architecture tb of tb_tb2_dp_mux is
constant c_nof_repeat : natural := 10;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Select next input when eop has occurred or when this input has had an active ready (so it has had a fair chance)
-- in_en, src_in.ready, g_mux_mode, g_mux_use_fifo, g_mux_fifo_fill, g_combined_demux, nof repeat
diff --git a/libraries/base/dp/tb/vhdl/tb_tb3_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_tb3_dp_demux.vhd
index 5d6bee41f597727283dbd2d0cd40b85c27762993..d8bc7c86f9e31468afd65176b635deaa0a87e452 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb3_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb3_dp_demux.vhd
@@ -33,7 +33,8 @@ end tb_tb3_dp_demux;
architecture tb of tb_tb3_dp_demux is
constant c_nof_outputs : natural := 3;
constant c_nof_repeat : natural := c_nof_outputs * 10;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Select input via sel_ctrl (g_mode=2)
-- in_en, src_in.ready, nof repeat, nof_outputs
diff --git a/libraries/base/dp/tb/vhdl/tb_tb3_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb_tb3_dp_mux.vhd
index 140f3d8ff14c0a758aed373ec818844eee635f48..52fe949cffe9c95ddd51a2c223b22daa71c10cc4 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb3_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb3_dp_mux.vhd
@@ -33,7 +33,8 @@ end tb_tb3_dp_mux;
architecture tb of tb_tb3_dp_mux is
constant c_nof_inputs : natural := 3;
constant c_nof_repeat : natural := c_nof_inputs * 10;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Select input via sel_ctrl (g_mode=2)
-- in_en, src_in.ready, nof repeat, nof_inputs
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd
index fcca299fdb1e63e1da649b0038fdff3f89b5b834..0b8f4629109cec2470e62f97191fa98b7fb766d2 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd
@@ -37,7 +37,8 @@ entity tb_tb_dp_block_from_mm is
end tb_tb_dp_block_from_mm;
architecture tb of tb_tb_dp_block_from_mm is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- used generics for tb_dp_block_from_mm (g_data_size, g_step_size, g_nof_data)
u0_tst_1_1_1 : entity work.tb_dp_block_from_mm generic map (1, 1, 1);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen.vhd
index ccb522b9b6a5de66e60b7e9f1e4914b8d2103602..79863727a16963da342ffd95ea6c564439fcf9da 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen.vhd
@@ -27,7 +27,8 @@ entity tb_tb_dp_block_gen is
end tb_tb_dp_block_gen;
architecture tb of tb_tb_dp_block_gen is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 3
-- > run -all --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
index a48141d0301224f1073f152e8d493d2a85aff955..b88de90cd23c2b826b6622e94bfc0d8a365d464a 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
@@ -32,7 +32,8 @@ entity tb_tb_dp_block_gen_valid_arr is
end tb_tb_dp_block_gen_valid_arr;
architecture tb of tb_tb_dp_block_gen_valid_arr is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_nof_streams : POSITIVE := 1;
-- g_nof_data_per_block : POSITIVE := 11;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape.vhd
index c9853ef71bf936d8a8e6d1fd46c29ac9ae52d945..f30a53984ca1fd00d8a12633db77e0566856b686 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape.vhd
@@ -30,7 +30,8 @@ entity tb_tb_dp_block_reshape is
end tb_tb_dp_block_reshape;
architecture tb of tb_tb_dp_block_reshape is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 5
-- > run -all --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape_sync.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape_sync.vhd
index d137defec7fea84cf0b0b760bbe2f292aa741fb6..b1d11f8c7e0fc4e47ca4cd0c539e26107e722f44 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape_sync.vhd
@@ -30,7 +30,8 @@ entity tb_tb_dp_block_reshape_sync is
end tb_tb_dp_block_reshape_sync;
architecture tb of tb_tb_dp_block_reshape_sync is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 5
-- > run -all --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_select.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_select.vhd
index e4ea053afe14cfa5de819d77d04b17a3fa2400fe..850fbd08fb3b7daa202112b9c6e69c65c858971f 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_select.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_select.vhd
@@ -34,7 +34,8 @@ entity tb_tb_dp_block_select is
end tb_tb_dp_block_select;
architecture tb of tb_tb_dp_block_select is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
constant c_length : natural := 5;
constant c_end : natural := c_length - 1;
@@ -44,14 +45,24 @@ begin
-- g_index_lo : NATURAL := 0;
-- g_index_hi : NATURAL := c_length-1 = c_end
- u_0_end_comb : entity work.tb_dp_block_select generic map(0, c_length, 0, c_end); -- pass on unchanged without pipeline so combinatorially
- u_0_end : entity work.tb_dp_block_select generic map(1, c_length, 0, c_end); -- pass on unchanged with pipeline
- u_0_skip : entity work.tb_dp_block_select generic map(1, c_length, 0, c_end - 1); -- skip last block in sync interval
- u_skip_end : entity work.tb_dp_block_select generic map(1, c_length, 1, c_end); -- skip first block in sync interval
- u_skip_skip : entity work.tb_dp_block_select generic map(1, c_length, 1, c_end - 1); -- skip first and last block in sync interval
- u_0 : entity work.tb_dp_block_select generic map(1, c_length, 0, 0); -- pass only block at first index
- u_2 : entity work.tb_dp_block_select generic map(1, c_length, 2, 2); -- pass only block at hi index = lo index = 2
- u_end : entity work.tb_dp_block_select generic map(1, c_length, c_end - 1, c_end - 1); -- pass only block at last index
- u_none : entity work.tb_dp_block_select generic map(1, c_length, 3, 2); -- pass no block because hi index < lo index
- u_none_end : entity work.tb_dp_block_select generic map(1, c_length, c_end + 1, c_end + 1); -- pass no block because lo index >= c_length
+ -- pass on unchanged without pipeline so combinatorially
+ u_0_end_comb : entity work.tb_dp_block_select generic map(0, c_length, 0, c_end);
+ -- pass on unchanged with pipeline
+ u_0_end : entity work.tb_dp_block_select generic map(1, c_length, 0, c_end);
+ -- skip last block in sync interval
+ u_0_skip : entity work.tb_dp_block_select generic map(1, c_length, 0, c_end - 1);
+ -- skip first block in sync interval
+ u_skip_end : entity work.tb_dp_block_select generic map(1, c_length, 1, c_end);
+ -- skip first and last block in sync interval
+ u_skip_skip : entity work.tb_dp_block_select generic map(1, c_length, 1, c_end - 1);
+ -- pass only block at first index
+ u_0 : entity work.tb_dp_block_select generic map(1, c_length, 0, 0);
+ -- pass only block at hi index = lo index = 2
+ u_2 : entity work.tb_dp_block_select generic map(1, c_length, 2, 2);
+ -- pass only block at last index
+ u_end : entity work.tb_dp_block_select generic map(1, c_length, c_end - 1, c_end - 1);
+ -- pass no block because hi index < lo index
+ u_none : entity work.tb_dp_block_select generic map(1, c_length, 3, 2);
+ -- pass no block because lo index >= c_length
+ u_none_end : entity work.tb_dp_block_select generic map(1, c_length, c_end + 1, c_end + 1);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_bsn_at_sync.vhd
index 5b129050dabd583f802ade516aed9641d4e96596..2367ce69112d51809e7a39f25c9b613be488ea42 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_bsn_at_sync.vhd
@@ -33,7 +33,8 @@ entity tb_tb_dp_block_validate_bsn_at_sync is
end tb_tb_dp_block_validate_bsn_at_sync;
architecture tb of tb_tb_dp_block_validate_bsn_at_sync is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
constant c_blk_per_sync : natural := 5;
constant c_data_per_blk : natural := 9;
@@ -42,7 +43,10 @@ begin
-- g_nof_data_per_blk : NATURAL := 6;
-- g_bsn_init : NATURAL := 7 -- >= g_nof_blocks_per_sync for discarded sync, < g_nof_blocks_per_sync for no discarded sync.
- u_smaller : entity work.tb_dp_block_validate_bsn_at_sync generic map(c_blk_per_sync, c_data_per_blk, c_blk_per_sync - 4); -- g_bsn_init < g_nof_blocks_per_sync
- u_equal : entity work.tb_dp_block_validate_bsn_at_sync generic map(c_blk_per_sync, c_data_per_blk, c_blk_per_sync); -- g_bsn_init = g_nof_blocks_per_sync
- u_larger : entity work.tb_dp_block_validate_bsn_at_sync generic map(c_blk_per_sync, c_data_per_blk, c_blk_per_sync + 4); -- g_bsn_init > g_nof_blocks_per_sync
+ -- g_bsn_init < g_nof_blocks_per_sync
+ u_smaller : entity work.tb_dp_block_validate_bsn_at_sync generic map(c_blk_per_sync, c_data_per_blk, c_blk_per_sync - 4);
+ -- g_bsn_init = g_nof_blocks_per_sync
+ u_equal : entity work.tb_dp_block_validate_bsn_at_sync generic map(c_blk_per_sync, c_data_per_blk, c_blk_per_sync);
+ -- g_bsn_init > g_nof_blocks_per_sync
+ u_larger : entity work.tb_dp_block_validate_bsn_at_sync generic map(c_blk_per_sync, c_data_per_blk, c_blk_per_sync + 4);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_channel.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_channel.vhd
index b88c0ada78e20629293e9c54078a918100d1a28d..fa4fbc5e99dd5f840cf234c6c1881ca753adb2b9 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_channel.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_channel.vhd
@@ -33,7 +33,8 @@ entity tb_tb_dp_block_validate_channel is
end tb_tb_dp_block_validate_channel;
architecture tb of tb_tb_dp_block_validate_channel is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
constant c_blk_per_sync : natural := 5;
constant c_data_per_blk : natural := 9;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_err.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_err.vhd
index da1be4d735b6b2a9794649f363e63801b82558f9..4468c748675ac6011ecc167faa26d4f8878989ed 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_err.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_err.vhd
@@ -33,7 +33,8 @@ entity tb_tb_dp_block_validate_err is
end tb_tb_dp_block_validate_err;
architecture tb of tb_tb_dp_block_validate_err is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
constant c_blk_per_sync : natural := 5;
constant c_data_per_blk : natural := 9;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_length.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_length.vhd
index c5ec1d291f3a17a60ba6e59ffa5ac9921cabd9db..d20049dc5df8a6b9b2d87123d998e539590fd369 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_length.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_length.vhd
@@ -33,7 +33,8 @@ entity tb_tb_dp_block_validate_length is
end tb_tb_dp_block_validate_length;
architecture tb of tb_tb_dp_block_validate_length is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
constant c_blk_per_sync : natural := 5;
constant c_data_per_blk : natural := 9;
@@ -45,7 +46,10 @@ begin
-- g_expected_length : NATURAL := 3;
-- g_err_bi : NATURAL := 3
- u_equal : entity work.tb_dp_block_validate_length generic map(c_blk_per_sync, c_data_per_blk, c_exp_length, c_err_bi); -- g_expected_length = g_nof_data_per_blk
- u_smaller : entity work.tb_dp_block_validate_length generic map(c_blk_per_sync, c_data_per_blk, c_exp_length - 3, c_err_bi); -- g_expected_length < g_nof_data_per_blk
- u_larger : entity work.tb_dp_block_validate_length generic map(c_blk_per_sync, c_data_per_blk, c_exp_length + 3, c_err_bi); -- g_expected_length > g_nof_data_per_blk
+ -- g_expected_length = g_nof_data_per_blk
+ u_equal : entity work.tb_dp_block_validate_length generic map(c_blk_per_sync, c_data_per_blk, c_exp_length, c_err_bi);
+ -- g_expected_length < g_nof_data_per_blk
+ u_smaller : entity work.tb_dp_block_validate_length generic map(c_blk_per_sync, c_data_per_blk, c_exp_length - 3, c_err_bi);
+ -- g_expected_length > g_nof_data_per_blk
+ u_larger : entity work.tb_dp_block_validate_length generic map(c_blk_per_sync, c_data_per_blk, c_exp_length + 3, c_err_bi);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd
index 98e4893c43033657c41f21a070536c99fb1eda66..3f8f84b7026bcc7144204c5f37343fc5edbc6cac 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd
@@ -29,11 +29,14 @@ end tb_tb_dp_bsn_align;
architecture tb of tb_tb_dp_bsn_align is
constant c_block_size : natural := 11;
constant c_diff_delay : natural := 20;
- constant c_diff_bsn : natural := 3; -- g_diff_bsn = g_bsn_latency can just be aligned
+ -- g_diff_bsn = g_bsn_latency can just be aligned
+ constant c_diff_bsn : natural := 3;
constant c_bsn_latency : natural := 3;
- constant c_nof_repeat : natural := 100; -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
+ -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
+ constant c_nof_repeat : natural := 100;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 2
-- > run -all --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
index d1ac6698b74d433a03b75d037ee651dafc42690b..e20a9357b92a2ea616710482ff03a4ee97fcbc7f 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
@@ -35,7 +35,8 @@ architecture tb of tb_tb_dp_bsn_align_v2 is
constant c_period : natural := 20;
constant c_nof_blk : natural := 30;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- DUT
-- g_nof_streams : NATURAL := 2; -- number of input and output streams
@@ -62,12 +63,16 @@ begin
-- g_tb_nof_blocks : NATURAL := 10 -- number of input blocks per restart
u_mm_output : entity work.tb_dp_bsn_align_v2 generic map (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, 3, true, 0, 0, 1, 0, 2, c_nof_blk);
- u_mm_output_pow2 : entity work.tb_dp_bsn_align_v2 generic map (2, 1, 1, 16, c_period, 32, 16, 17, 0, 0, 0, 3, true, 0, 0, 1, 0, 2, c_nof_blk); -- g_block_size = 2**4 = 16
- u_mm_output_large_bsn : entity work.tb_dp_bsn_align_v2 generic map (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, 3000, true, 0, 0, 1, 0, 2, c_nof_blk); -- test where bsn * g_block_size > 2^10 to test address resizing
+ -- g_block_size = 2**4 = 16
+ u_mm_output_pow2 : entity work.tb_dp_bsn_align_v2 generic map (2, 1, 1, 16, c_period, 32, 16, 17, 0, 0, 0, 3, true, 0, 0, 1, 0, 2, c_nof_blk);
+ -- test where bsn * g_block_size > 2^10 to test address resizing
+ u_mm_output_large_bsn : entity work.tb_dp_bsn_align_v2 generic map (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, 3000, true, 0, 0, 1, 0, 2, c_nof_blk);
u_mm_output_single : entity work.tb_dp_bsn_align_v2 generic map (1, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, 3, true, 0, 0, 1, 0, 2, c_nof_blk);
u_dp_output : entity work.tb_dp_bsn_align_v2 generic map (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, 3, false, 0, 0, 1, 0, 2, c_nof_blk);
- u_dp_output_pow2 : entity work.tb_dp_bsn_align_v2 generic map (2, 1, 1, 16, c_period, 32, 16, 17, 0, 0, 0, 3, false, 0, 0, 1, 0, 2, c_nof_blk); -- g_block_size = 2**4 = 16
- u_dp_output_large_bsn : entity work.tb_dp_bsn_align_v2 generic map (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, 3000, false, 0, 0, 1, 0, 2, c_nof_blk); -- test where bsn * g_block_size > 2^10 to test address resizing
+ -- g_block_size = 2**4 = 16
+ u_dp_output_pow2 : entity work.tb_dp_bsn_align_v2 generic map (2, 1, 1, 16, c_period, 32, 16, 17, 0, 0, 0, 3, false, 0, 0, 1, 0, 2, c_nof_blk);
+ -- test where bsn * g_block_size > 2^10 to test address resizing
+ u_dp_output_large_bsn : entity work.tb_dp_bsn_align_v2 generic map (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, 3000, false, 0, 0, 1, 0, 2, c_nof_blk);
u_dp_output_single : entity work.tb_dp_bsn_align_v2 generic map (1, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, 3, false, 0, 0, 1, 0, 2, c_nof_blk);
u_dp_output_p1 : entity work.tb_dp_bsn_align_v2 generic map (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, 3, false, 1, 1, 1, 0, 2, c_nof_blk);
u_bsn_lat_max_2 : entity work.tb_dp_bsn_align_v2 generic map (2, 2, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, 3, false, 0, 0, 1, 0, 2, c_nof_blk);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
index cf58ac3979680f51c4e2c4490e2a15a0b650884c..f8aaa00ed3e5cba0264aa8329349fb9a5718741f 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
@@ -31,7 +31,8 @@ entity tb_tb_dp_bsn_source_v2 is
end tb_tb_dp_bsn_source_v2;
architecture tb of tb_tb_dp_bsn_source_v2 is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- from tb_dp_bsn_source_v2.vhd
--
@@ -39,32 +40,50 @@ begin
-- g_block_size : NATURAL := 32
-- test integer case
- u_20_10 : entity work.tb_dp_bsn_source_v2 generic map (20, 10); -- 20 // 10 = 2, 20 MOD 10 = 0, 20/10 = 2 block/sync
- u_22_11 : entity work.tb_dp_bsn_source_v2 generic map (22, 11); -- 22 // 11 = 2, 22 MOD 11 = 0, 22/11 = 2 block/sync
- u_39_13 : entity work.tb_dp_bsn_source_v2 generic map (39, 13); -- 39 // 13 = 3, 39 MOD 13 = 0, 39/13 = 3 block/sync
+ -- 20 // 10 = 2, 20 MOD 10 = 0, 20/10 = 2 block/sync
+ u_20_10 : entity work.tb_dp_bsn_source_v2 generic map (20, 10);
+ -- 22 // 11 = 2, 22 MOD 11 = 0, 22/11 = 2 block/sync
+ u_22_11 : entity work.tb_dp_bsn_source_v2 generic map (22, 11);
+ -- 39 // 13 = 3, 39 MOD 13 = 0, 39/13 = 3 block/sync
+ u_39_13 : entity work.tb_dp_bsn_source_v2 generic map (39, 13);
-- test smallest nof block per sync
- u_10_10 : entity work.tb_dp_bsn_source_v2 generic map (10, 10); -- 1 block/sync
- u_5_5 : entity work.tb_dp_bsn_source_v2 generic map (5, 5); -- 1 block/sync
+ -- 1 block/sync
+ u_10_10 : entity work.tb_dp_bsn_source_v2 generic map (10, 10);
+ -- 1 block/sync
+ u_5_5 : entity work.tb_dp_bsn_source_v2 generic map (5, 5);
-- test smallest g_block_size case
- u_3_3 : entity work.tb_dp_bsn_source_v2 generic map (3, 3); -- 3 // 3 = 1, 3 MOD 3 = 0, 3/3 = 1 block/sync
- u_6_3 : entity work.tb_dp_bsn_source_v2 generic map (6, 3); -- 6 // 3 = 2, 6 MOD 3 = 0, 6/3 = 2 block/sync
- u_7_3 : entity work.tb_dp_bsn_source_v2 generic map (7, 3); -- 7 // 3 = 2, 7 MOD 3 = 1, 7/3 = 2.33 block/sync
+ -- 3 // 3 = 1, 3 MOD 3 = 0, 3/3 = 1 block/sync
+ u_3_3 : entity work.tb_dp_bsn_source_v2 generic map (3, 3);
+ -- 6 // 3 = 2, 6 MOD 3 = 0, 6/3 = 2 block/sync
+ u_6_3 : entity work.tb_dp_bsn_source_v2 generic map (6, 3);
+ -- 7 // 3 = 2, 7 MOD 3 = 1, 7/3 = 2.33 block/sync
+ u_7_3 : entity work.tb_dp_bsn_source_v2 generic map (7, 3);
-- test lofar case with 0.5 fraction in average nof block/sync
- u_20_8 : entity work.tb_dp_bsn_source_v2 generic map (20, 8); -- 20 // 8 = 2, 20 MOD 8 = 4, 20/8 = 2.5 block/sync
+ -- 20 // 8 = 2, 20 MOD 8 = 4, 20/8 = 2.5 block/sync
+ u_20_8 : entity work.tb_dp_bsn_source_v2 generic map (20, 8);
-- test fractional (corner) cases
- u_18_9 : entity work.tb_dp_bsn_source_v2 generic map (18, 9); -- 18 MOD 9 = 0
- u_17_9 : entity work.tb_dp_bsn_source_v2 generic map (17, 9); -- 17 MOD 9 = 8 = g_block_size - 1
- u_19_9 : entity work.tb_dp_bsn_source_v2 generic map (19, 9); -- 19 MOD 9 = 1
- u_20_9 : entity work.tb_dp_bsn_source_v2 generic map (20, 9); -- 20 MOD 9 = 2
- u_25_9 : entity work.tb_dp_bsn_source_v2 generic map (25, 9); -- 25 MOD 9 = 7
- u_26_9 : entity work.tb_dp_bsn_source_v2 generic map (26, 9); -- 26 MOD 9 = 8 = g_block_size - 1
- u_27_9 : entity work.tb_dp_bsn_source_v2 generic map (27, 9); -- 27 MOD 9 = 0
+ -- 18 MOD 9 = 0
+ u_18_9 : entity work.tb_dp_bsn_source_v2 generic map (18, 9);
+ -- 17 MOD 9 = 8 = g_block_size - 1
+ u_17_9 : entity work.tb_dp_bsn_source_v2 generic map (17, 9);
+ -- 19 MOD 9 = 1
+ u_19_9 : entity work.tb_dp_bsn_source_v2 generic map (19, 9);
+ -- 20 MOD 9 = 2
+ u_20_9 : entity work.tb_dp_bsn_source_v2 generic map (20, 9);
+ -- 25 MOD 9 = 7
+ u_25_9 : entity work.tb_dp_bsn_source_v2 generic map (25, 9);
+ -- 26 MOD 9 = 8 = g_block_size - 1
+ u_26_9 : entity work.tb_dp_bsn_source_v2 generic map (26, 9);
+ -- 27 MOD 9 = 0
+ u_27_9 : entity work.tb_dp_bsn_source_v2 generic map (27, 9);
-- test some prime values
- u_17_3 : entity work.tb_dp_bsn_source_v2 generic map (17, 3); -- 17 // 3 = 5, 17 MOD 3 = 2, 17/3 = 5.66 block/sync
- u_101_17 : entity work.tb_dp_bsn_source_v2 generic map (101, 17); -- 101 // 17 = 5, 101 MOD 17 = 16, 101/17 = 5.9411 block/sync
+ -- 17 // 3 = 5, 17 MOD 3 = 2, 17/3 = 5.66 block/sync
+ u_17_3 : entity work.tb_dp_bsn_source_v2 generic map (17, 3);
+ -- 101 // 17 = 5, 101 MOD 17 = 16, 101/17 = 5.9411 block/sync
+ u_101_17 : entity work.tb_dp_bsn_source_v2 generic map (101, 17);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
index 23ff128bc48cb46e2d63ba907fd44af18251c189..9d1fe3018385745942470b9bfbb46abc965819dd 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
@@ -33,7 +33,8 @@ entity tb_tb_dp_bsn_sync_scheduler is
end tb_tb_dp_bsn_sync_scheduler;
architecture tb of tb_tb_dp_bsn_sync_scheduler is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
-- Use g_block_size < c_nof_input_sync, because the fractional sync pattern
-- will repeat within g_block_size number of output sync intervals. The
@@ -55,26 +56,41 @@ begin
-- g_pipeline : NATURAL := 0
gen_tb : for P in 0 to c_pipeline generate
- u_output_is_input : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 10, 3, 170, P); -- 170/10 = 17 block/out_sync, = in_sosi
- u_output_is_input_no_gaps : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 5, 0, 85, P); -- 85/5 = 17 block/out_sync, = in_sosi
+ -- 170/10 = 17 block/out_sync, = in_sosi
+ u_output_is_input : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 10, 3, 170, P);
+ -- 85/5 = 17 block/out_sync, = in_sosi
+ u_output_is_input_no_gaps : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 5, 0, 85, P);
- u_sync_interval_0_5x : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 10, 3, 85, P); -- 85/10 = 8.5 block/out_sync, factor 85/170 = 0.5,
- u_sync_interval_1_5x : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 10, 3, 255, P); -- 255/10 = 25.5 block/out_sync, factor 255/170 = 1.5,
- u_sync_interval_prime_251 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 10, 3, 251, P); -- 251/10 = 25.1 block/out_sync, 251 is a prime
+ -- 85/10 = 8.5 block/out_sync, factor 85/170 = 0.5,
+ u_sync_interval_0_5x : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 10, 3, 85, P);
+ -- 255/10 = 25.5 block/out_sync, factor 255/170 = 1.5,
+ u_sync_interval_1_5x : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 10, 3, 255, P);
+ -- 251/10 = 25.1 block/out_sync, 251 is a prime
+ u_sync_interval_prime_251 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 10, 3, 251, P);
- u_short_block_4_3_15 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 4, 3, 3, 15, P); -- 15/3 = 5 block/out_sync,
- u_short_block_5_3_16 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 5, 3, 3, 16, P); -- 16/3 = 5.33 block/out_sync,
- u_short_block_6_3_17 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 6, 3, 3, 17, P); -- 17/3 = 5.66 block/out_sync,
+ -- 15/3 = 5 block/out_sync,
+ u_short_block_4_3_15 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 4, 3, 3, 15, P);
+ -- 16/3 = 5.33 block/out_sync,
+ u_short_block_5_3_16 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 5, 3, 3, 16, P);
+ -- 17/3 = 5.66 block/out_sync,
+ u_short_block_6_3_17 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 6, 3, 3, 17, P);
- u_short_block_no_gaps_4_3_15 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 4, 3, 0, 15, P); -- 15/3 = 5 block/out_sync,
- u_short_block_no_gaps_5_3_16 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 5, 3, 0, 16, P); -- 16/3 = 5.33 block/out_sync,
- u_short_block_no_gaps_6_3_17 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 6, 3, 0, 17, P); -- 17/3 = 5.66 block/out_sync,
+ -- 15/3 = 5 block/out_sync,
+ u_short_block_no_gaps_4_3_15 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 4, 3, 0, 15, P);
+ -- 16/3 = 5.33 block/out_sync,
+ u_short_block_no_gaps_5_3_16 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 5, 3, 0, 16, P);
+ -- 17/3 = 5.66 block/out_sync,
+ u_short_block_no_gaps_6_3_17 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 6, 3, 0, 17, P);
- u_short_block_size_2 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 7, 2, 3, 16, P); -- 16/2 = 8 block/out_sync,
- u_short_block_size_2_no_gaps : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 7, 2, 0, 16, P); -- 16/2 = 8 block/out_sync,
+ -- 16/2 = 8 block/out_sync,
+ u_short_block_size_2 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 7, 2, 3, 16, P);
+ -- 16/2 = 8 block/out_sync,
+ u_short_block_size_2_no_gaps : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 7, 2, 0, 16, P);
- u_fraction_half : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 10, 3, 45, P); -- 45/10 = 4.5 block/out_sync
- u_fraction_0 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 10, 3, 50, P); -- 50/10 = 5 block/out_sync
+ -- 45/10 = 4.5 block/out_sync
+ u_fraction_half : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 10, 3, 45, P);
+ -- 50/10 = 5 block/out_sync
+ u_fraction_0 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 10, 3, 50, P);
end generate;
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_calculate_crc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_calculate_crc.vhd
index b3bf5be97e85af7f05328d5db14e210e0b0d1605..8a37b3e56bf9acc5aea00b941a023be09f5213cd 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_calculate_crc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_calculate_crc.vhd
@@ -41,7 +41,8 @@ entity tb_tb_dp_calculate_crc is
end tb_tb_dp_calculate_crc;
architecture tb of tb_tb_dp_calculate_crc is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_data_w : NATURAL := 28;
-- g_crc_w : NATURAL := 28;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_concat.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_concat.vhd
index 502254befc42e5c4685ef3211b90e0354dacfb09..be7a131ce7a9a6b38af2a1dcb1d414464b61ced7 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_concat.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_concat.vhd
@@ -27,7 +27,8 @@ entity tb_tb_dp_concat is
end tb_tb_dp_concat;
architecture tb of tb_tb_dp_concat is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 10
-- > run 300 us --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_concat_field_blk.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_concat_field_blk.vhd
index 69e2c6d1f757a4890e9e79ce2f47ffe4d8f9cf46..888d00305766d877ba15c1484f260eabf89ec8b2 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_concat_field_blk.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_concat_field_blk.vhd
@@ -33,7 +33,8 @@ entity tb_tb_dp_concat_field_blk is
end tb_tb_dp_concat_field_blk;
architecture tb of tb_tb_dp_concat_field_blk is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
@@ -44,6 +45,7 @@ begin
-- g_pkt_len : NATURAL := 100;
-- g_pkt_gap : NATURAL := 0
- u_large_gap : entity work.tb_dp_concat_field_blk generic map (e_active, e_active, 64, 13, 100, 10); -- g_pkt_gap > header length
+ -- g_pkt_gap > header length
+ u_large_gap : entity work.tb_dp_concat_field_blk generic map (e_active, e_active, 64, 13, 100, 10);
u_zero_gap : entity work.tb_dp_concat_field_blk generic map (e_active, e_active, 64, 13, 100, 0);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_counter.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_counter.vhd
index d97d8f4ae2c8c23306ebc94389ea08aa1aafde4a..85e50952d8e0cac462336090c12ab28b332236c9 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_counter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_counter.vhd
@@ -35,7 +35,8 @@ entity tb_tb_dp_counter is
end tb_tb_dp_counter;
architecture tb of tb_tb_dp_counter is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_interleave_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_interleave_to_one.vhd
index 4f1ab4f582d5d132b46e3c6f3f5617525155be2a..37c2481311c13946c8d86af8050bdb929cd44112 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_interleave_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_interleave_to_one.vhd
@@ -35,7 +35,8 @@ entity tb_tb_dp_deinterleave_interleave_to_one is
end tb_tb_dp_deinterleave_interleave_to_one;
architecture tb of tb_tb_dp_deinterleave_interleave_to_one is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
constant c_rep_act : natural := 5;
constant c_rep_rnd : natural := 100;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_one_to_n_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_one_to_n_to_one.vhd
index 45d727f2a60c181bd25a5cda2d6718b0479b57e4..334011f826f2613ef31f0d20286eed4264c973c4 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_one_to_n_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_one_to_n_to_one.vhd
@@ -35,7 +35,8 @@ entity tb_tb_dp_deinterleave_one_to_n_to_one is
end tb_tb_dp_deinterleave_one_to_n_to_one;
architecture tb of tb_tb_dp_deinterleave_one_to_n_to_one is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
constant c_rep_act : natural := 5;
constant c_rep_rnd : natural := 100;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_demux.vhd
index a027706fbe9969188326b4320cd5c321f05d7311..7d8e6133d3072cd6cff73100c2c4b53a4ef9264c 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_demux.vhd
@@ -29,7 +29,8 @@ entity tb_tb_dp_demux is
end tb_tb_dp_demux;
architecture tb of tb_tb_dp_demux is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 10
-- > run 300 us --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_distribute.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_distribute.vhd
index 50a0a330ecdc3ef19cf46a2a4022ef31955d5f1e..82738af91a44a0768a7a497173d713d14fe4a6f7 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_distribute.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_distribute.vhd
@@ -29,7 +29,8 @@ entity tb_tb_dp_distribute is
end tb_tb_dp_distribute;
architecture tb of tb_tb_dp_distribute is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 10
-- > run -all --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_example_dut.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_example_dut.vhd
index df13417b871fcfd880f7d23d81ba3ffa01da6551..a1468b47dc6b677c17ee8e1eb82c5b600b9cb708 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_example_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_example_dut.vhd
@@ -40,7 +40,8 @@ architecture tb of tb_tb_dp_example_dut is
constant c_flow : t_dp_flow_control_enum_arr := c_dp_flow_control_enum_arr;
constant c_bool : t_nat_boolean_arr := c_nat_boolean_arr;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
@@ -52,9 +53,12 @@ begin
-- g_pkt_len : NATURAL := 16;
-- g_pkt_gap : NATURAL := 4
- g_flow_control_stimuli : for I in 0 to 2 generate -- 0 = e_active, 1 = e_random, 2 = e_pulse
- g_flow_control_verify : for J in 0 to 2 generate -- 0 = e_active, 1 = e_random, 2 = e_pulse
- gen_bool_dut : for K in 0 to 1 generate -- 0 = TRUE, 1= FALSE
+ -- 0 = e_active, 1 = e_random, 2 = e_pulse
+ g_flow_control_stimuli : for I in 0 to 2 generate
+ -- 0 = e_active, 1 = e_random, 2 = e_pulse
+ g_flow_control_verify : for J in 0 to 2 generate
+ -- 0 = TRUE, 1= FALSE
+ gen_bool_dut : for K in 0 to 1 generate
u_dut : entity work.tb_dp_example_dut generic map (c_flow(I), c_flow(J), c_bool(K), 16, c_nof_repeat, 17, 4);
end generate;
end generate;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd
index 3da7df71cedbf8d9729d0d41e7a28ce362afd875..9a5eaf07fa9dbaa922df16a67e4e2e8bec59d528 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd
@@ -35,7 +35,8 @@ end tb_tb_dp_example_no_dut;
architecture tb of tb_tb_dp_example_no_dut is
constant c_nof_repeat : natural := 10;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc.vhd
index 46f94d01c39dd7ac977436eed19e994b2f8f7703..9834783cbcba07b817ec5a4d20f81ca67052581b 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc.vhd
@@ -27,7 +27,8 @@ entity tb_tb_dp_fifo_dc is
end tb_tb_dp_fifo_dc;
architecture tb of tb_tb_dp_fifo_dc is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 10
-- > run g_dut_rd_clk_freq * 330 us --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
index 2df85ef7d265b365d55a06ab03511763ad89f841..d4581754fa6a8cf600b0b8100d275ce4d2af4862 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
@@ -30,7 +30,8 @@ entity tb_tb_dp_fifo_dc_arr is
end tb_tb_dp_fifo_dc_arr;
architecture tb of tb_tb_dp_fifo_dc_arr is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 10
-- > run g_dut_rd_clk_freq * 330 us --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd
index 71f4afcd3252c3ef0a4757064aca5bd870f76417..3e412f0e690220274f0c7cf9501bd12bc95e2dcd 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd
@@ -26,7 +26,8 @@ entity tb_tb_dp_fifo_dc_mixed_widths is
end tb_tb_dp_fifo_dc_mixed_widths;
architecture tb of tb_tb_dp_fifo_dc_mixed_widths is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 5
-- > run 100 us --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill.vhd
index 8bed5bd9378792527c7d55c1c1ab2f388db1c237..242d2208ee6f515276cb292dbe97f0278c9dff96 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill.vhd
@@ -27,14 +27,16 @@ entity tb_tb_dp_fifo_fill is
end tb_tb_dp_fifo_fill;
architecture tb of tb_tb_dp_fifo_fill is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 10
-- > run 300 us --> OK
-- Try FIFO settings : GENERIC MAP (g_dut_use_bsn, g_dut_use_empty, g_dut_use_channel, g_dut_use_sync, g_dut_fifo_rl, g_dut_fifo_size, g_dut_fifo_fill)
- u_rl_1_fill_0 : entity work.tb_dp_fifo_fill generic map (false, false, false, false, 1, 64, 0); -- no fill ==> dp_fifo_sc
+ -- no fill ==> dp_fifo_sc
+ u_rl_1_fill_0 : entity work.tb_dp_fifo_fill generic map (false, false, false, false, 1, 64, 0);
u_rl_1_fill_1 : entity work.tb_dp_fifo_fill generic map (false, false, false, false, 1, 64, 1);
u_rl_1_fill_3 : entity work.tb_dp_fifo_fill generic map (false, false, false, false, 1, 64, 3);
u_rl_1_fill_30 : entity work.tb_dp_fifo_fill generic map (false, false, false, false, 1, 64, 30);
@@ -45,6 +47,7 @@ begin
u_rl_1_fill_30_sync : entity work.tb_dp_fifo_fill generic map (false, false, false, true, 1, 64, 30);
u_rl_1_fill_30_all : entity work.tb_dp_fifo_fill generic map (true, true, true, true, 1, 64, 30);
- u_rl_0_fill_0 : entity work.tb_dp_fifo_fill generic map (false, false, false, false, 0, 64, 0); -- no fill ==> dp_fifo_sc
+ -- no fill ==> dp_fifo_sc
+ u_rl_0_fill_0 : entity work.tb_dp_fifo_fill generic map (false, false, false, false, 0, 64, 0);
u_rl_0_fill_1 : entity work.tb_dp_fifo_fill generic map (false, false, false, false, 0, 64, 1);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
index 4c793ad5223d74a6977a46f7e99016fa72cea803..de06aafb75d73774d62f995e46786c7db44411fd 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
@@ -41,7 +41,8 @@ entity tb_tb_dp_fifo_fill_eop is
end tb_tb_dp_fifo_fill_eop;
architecture tb of tb_tb_dp_fifo_fill_eop is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Try FIFO settings
-- g_dut_use_dual_clock : boolean := true;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd
index c6711c48e2362da593b3cfdbd8694d5e58eacb3e..1780f7344760429f4759e8b6d47c3daa1a41fc28 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd
@@ -27,14 +27,16 @@ entity tb_tb_dp_fifo_fill_sc is
end tb_tb_dp_fifo_fill_sc;
architecture tb of tb_tb_dp_fifo_fill_sc is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 10
-- > run 300 us --> OK
-- Try FIFO settings : GENERIC MAP (g_dut_use_bsn, g_dut_use_empty, g_dut_use_channel, g_dut_use_sync, g_dut_fifo_rl, g_dut_fifo_size, g_dut_fifo_fill)
- u_rl_1_fill_0 : entity work.tb_dp_fifo_fill_sc generic map (false, false, false, false, 1, 64, 0); -- no fill ==> dp_fifo_sc
+ -- no fill ==> dp_fifo_sc
+ u_rl_1_fill_0 : entity work.tb_dp_fifo_fill_sc generic map (false, false, false, false, 1, 64, 0);
u_rl_1_fill_1 : entity work.tb_dp_fifo_fill_sc generic map (false, false, false, false, 1, 64, 1);
u_rl_1_fill_3 : entity work.tb_dp_fifo_fill_sc generic map (false, false, false, false, 1, 64, 3);
u_rl_1_fill_30 : entity work.tb_dp_fifo_fill_sc generic map (false, false, false, false, 1, 64, 30);
@@ -45,7 +47,8 @@ begin
u_rl_1_fill_30_sync : entity work.tb_dp_fifo_fill_sc generic map (false, false, false, true, 1, 64, 30);
u_rl_1_fill_30_all : entity work.tb_dp_fifo_fill_sc generic map (true, true, true, true, 1, 64, 30);
- u_rl_0_fill_0 : entity work.tb_dp_fifo_fill_sc generic map (false, false, false, false, 0, 64, 0); -- no fill ==> dp_fifo_sc
+ -- no fill ==> dp_fifo_sc
+ u_rl_0_fill_0 : entity work.tb_dp_fifo_fill_sc generic map (false, false, false, false, 0, 64, 0);
u_rl_0_fill_1 : entity work.tb_dp_fifo_fill_sc generic map (false, false, false, false, 0, 64, 1);
u_rl_0_fill_control : entity work.tb_dp_fifo_fill_sc generic map (false, false, false, false, 0, 64, 64, true);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_info.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_info.vhd
index 3a1e772519e1c3fb9866d188ef631c5a27071d1d..186a49e018dbfb3b4494fddccf86889ef705870b 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_info.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_info.vhd
@@ -35,7 +35,8 @@ end tb_tb_dp_fifo_info;
architecture tb of tb_tb_dp_fifo_info is
constant c_nof_repeat : natural := 100;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_sc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_sc.vhd
index fbfee6063762a22ea32e758847fdef6f10a6a791..b534258abc850e6873c58ed80d96adecb9f003d8 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_sc.vhd
@@ -27,7 +27,8 @@ entity tb_tb_dp_fifo_sc is
end tb_tb_dp_fifo_sc;
architecture tb of tb_tb_dp_fifo_sc is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 5
-- > run -a --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd
index 1a43d7cf5794393865fd8288cdda7fb8ee705ca5..64d7337c455c67829e8e21b0b362b07758667962 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd
@@ -31,7 +31,8 @@ use dp_lib.tb_dp_pkg.all;
-- > run -all
entity tb_tb_dp_flush is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
end tb_tb_dp_flush;
architecture tb of tb_tb_dp_flush is
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_frame_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_frame_scheduler.vhd
index 7b3a6d811204091a3d6857fea5893ae6e71305d1..bb725eff2511018177e4dd75c4c77ecd89ec52f1 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_frame_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_frame_scheduler.vhd
@@ -27,7 +27,8 @@ entity tb_tb_dp_frame_scheduler is
end tb_tb_dp_frame_scheduler;
architecture tb of tb_tb_dp_frame_scheduler is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 10
-- > run 12 ms --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd
index b2d70fca28db910b965d2bfb4589c10a6449a95b..a57462c8ba65a1e1aab6d1656f6250a879ea6d0b 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd
@@ -28,7 +28,8 @@ entity tb_tb_dp_latency_fifo is
end tb_tb_dp_latency_fifo;
architecture tb of tb_tb_dp_latency_fifo is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 2
-- > run -all --> OK
@@ -43,7 +44,8 @@ begin
-- g_out_ready : t_dp_flow_control_enum := e_active, e_random or e_pulse flow control
u_fifo_bypass : entity work.tb_dp_latency_fifo generic map (true, 1, 1, 1, 51, 4, e_active, e_active);
- u_fifo_0 : entity work.tb_dp_latency_fifo generic map (false, 1, 1, 0, 51, 4, e_active, e_active); -- try bypass via g_fifo_size=0
+ -- try bypass via g_fifo_size=0
+ u_fifo_0 : entity work.tb_dp_latency_fifo generic map (false, 1, 1, 0, 51, 4, e_active, e_active);
u_fifo_1_act_act : entity work.tb_dp_latency_fifo generic map (false, 1, 1, 1, 51, 4, e_active, e_active);
u_fifo_1_rnd_act : entity work.tb_dp_latency_fifo generic map (false, 1, 1, 1, 51, 4, e_random, e_active);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_mux.vhd
index 582a55eaed04b964f3aea217ac0d904819473425..5f1e4187fa70fd305720d4d59eb1a5b5e29d6196 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_mux.vhd
@@ -36,7 +36,8 @@ architecture tb of tb_tb_dp_mux is
-- CONSTANT c_natural_arr_init : t_natural_arr := t_natural_arr(1024);
-- does not work, and we do not want to constrain the array generic in the entity.
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 10
-- > run 300 us --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_offload_tx_v3.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_offload_tx_v3.vhd
index 615f42cfd52b8db909b618d93dd0380ef1bafbb2..1a73efc2d8b58af407772da0c47f40eaf2b522a4 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_offload_tx_v3.vhd
@@ -25,13 +25,15 @@
library IEEE;
use IEEE.std_logic_1164.all;
-use work.tb_dp_pkg.all; -- for t_dp_flow_control_enum
+-- for t_dp_flow_control_enum
+use work.tb_dp_pkg.all;
entity tb_tb_dp_offload_tx_v3 is
end tb_tb_dp_offload_tx_v3;
architecture tb of tb_tb_dp_offload_tx_v3 is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always e_active, e_random or e_pulse flow control
@@ -45,7 +47,8 @@ begin
-- g_pkt_gap : NATURAL := 16
u_pls_act_data_w_64 : entity work.tb_dp_offload_tx_v3 generic map (e_pulse, e_active, false, 64, 64, 0, 240, 16);
- u_act_act_data_w_64_no_gap : entity work.tb_dp_offload_tx_v3 generic map (e_active, e_active, false, 64, 64, 0, 240, 0); -- u_dp_fifo_sc does run almost full
+ -- u_dp_fifo_sc does run almost full
+ u_act_act_data_w_64_no_gap : entity work.tb_dp_offload_tx_v3 generic map (e_active, e_active, false, 64, 64, 0, 240, 0);
u_pls_act_data_w_64_no_gap : entity work.tb_dp_offload_tx_v3 generic map (e_pulse, e_active, false, 64, 64, 0, 240, 0);
u_rnd_act_data_w_64 : entity work.tb_dp_offload_tx_v3 generic map (e_random, e_active, false, 64, 64, 0, 240, 16);
u_rnd_act_data_w_32 : entity work.tb_dp_offload_tx_v3 generic map (e_random, e_active, false, 32, 32, 0, 240, 16);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet.vhd
index ed199b8dbb0827a34988bb2e68a79cb3ce773416..c073e601d612c8a8a87d64a9c64ef218c3e1e3f4 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet.vhd
@@ -35,7 +35,8 @@ end tb_tb_dp_packet;
architecture tb of tb_tb_dp_packet is
constant c_nof_repeat : natural := 10;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_data_w, in_en, src_in.ready, nof repeat
u_16_act_act : entity work.tb_dp_packet generic map (16, e_active, e_active, c_nof_repeat);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd
index 46fbd725ba93af2716dab57266cc4a6f73bb8af1..ffa9e33a08aa966909a789d6e8c3ffad93cf6a3c 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd
@@ -35,7 +35,8 @@ end tb_tb_dp_packet_merge;
architecture tb of tb_tb_dp_packet_merge is
constant c_nof_repeat : natural := 100;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_packetizing.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_packetizing.vhd
index f7df2030e1ec4abd9035d6b32c8f80bc33a495a0..5f6d941f9ee99036e10a81a03a0c6c778d3659d5 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_packetizing.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_packetizing.vhd
@@ -27,22 +27,32 @@ entity tb_tb_dp_packetizing is
end tb_tb_dp_packetizing;
architecture tb of tb_tb_dp_packetizing is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 10
-- > run 30 us --> OK
-- Try different packing : GENERIC MAP (g_usr_nof_words => , g_phy_nof_words => , g_usr_dat_w => , g_phy_dat_w => )
- u_1_1_10_10 : entity work.tb_dp_packetizing generic map (1, 1, 10, 10); -- 1/1 and try different c_phy_dat_w
+ -- 1/1 and try different c_phy_dat_w
+ u_1_1_10_10 : entity work.tb_dp_packetizing generic map (1, 1, 10, 10);
u_1_1_10_16 : entity work.tb_dp_packetizing generic map (1, 1, 10, 16);
u_1_1_10_24 : entity work.tb_dp_packetizing generic map (1, 1, 10, 24);
- u_2_1_8_16 : entity work.tb_dp_packetizing generic map (2, 1, 8, 16); -- 2/1
- u_1_2_16_8 : entity work.tb_dp_packetizing generic map (1, 2, 16, 8); -- 1/2
- u_3_1_8_24 : entity work.tb_dp_packetizing generic map (3, 1, 8, 24); -- 3/1
- u_1_3_24_8 : entity work.tb_dp_packetizing generic map (1, 3, 24, 8); -- 1/3
- u_3_2_16_24 : entity work.tb_dp_packetizing generic map (3, 2, 16, 24); -- 3/2
- u_2_3_24_16 : entity work.tb_dp_packetizing generic map (2, 3, 24, 16); -- 2/3
- u_4_1_8_32 : entity work.tb_dp_packetizing generic map (4, 1, 8, 32); -- 4/1
- u_1_4_32_8 : entity work.tb_dp_packetizing generic map (1, 4, 32, 8); -- 1/4
+ -- 2/1
+ u_2_1_8_16 : entity work.tb_dp_packetizing generic map (2, 1, 8, 16);
+ -- 1/2
+ u_1_2_16_8 : entity work.tb_dp_packetizing generic map (1, 2, 16, 8);
+ -- 3/1
+ u_3_1_8_24 : entity work.tb_dp_packetizing generic map (3, 1, 8, 24);
+ -- 1/3
+ u_1_3_24_8 : entity work.tb_dp_packetizing generic map (1, 3, 24, 8);
+ -- 3/2
+ u_3_2_16_24 : entity work.tb_dp_packetizing generic map (3, 2, 16, 24);
+ -- 2/3
+ u_2_3_24_16 : entity work.tb_dp_packetizing generic map (2, 3, 24, 16);
+ -- 4/1
+ u_4_1_8_32 : entity work.tb_dp_packetizing generic map (4, 1, 8, 32);
+ -- 1/4
+ u_1_4_32_8 : entity work.tb_dp_packetizing generic map (1, 4, 32, 8);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_pad_insert_remove.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_pad_insert_remove.vhd
index b44aa851f661d49fd6f3d03517108f5e499f494b..ebb6128969397e3760e05d9bdc85bbb7d4071a24 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_pad_insert_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_pad_insert_remove.vhd
@@ -29,7 +29,8 @@ entity tb_tb_dp_pad_insert_remove is
end tb_tb_dp_pad_insert_remove;
architecture tb of tb_tb_dp_pad_insert_remove is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 2
-- > run -all --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline.vhd
index bf7764dd7a38062c4f298dd0c17e44a83b74cbfc..e5038652053f63247bbee66012131f3af69735b3 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline.vhd
@@ -30,7 +30,8 @@ entity tb_tb_dp_pipeline is
end tb_tb_dp_pipeline;
architecture tb of tb_tb_dp_pipeline is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
u_p0 : entity work.tb_dp_pipeline generic map (0);
u_p1 : entity work.tb_dp_pipeline generic map (1);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline_ready.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline_ready.vhd
index 78c897f85426a3a6cf0c223c8a036690bc44af16..66cc1aee92a8940e9fcf01b0c793e6d5490d62c8 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline_ready.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline_ready.vhd
@@ -32,7 +32,8 @@ end tb_tb_dp_pipeline_ready;
architecture tb of tb_tb_dp_pipeline_ready is
constant c_nof_repeat : natural := 50;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- in_en, src_in.ready, in_latency, out_latency, nof repeat,
-- Random flow control for different RL
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd
index f61ac825829346b955479db5f27696346389f5df..1bbaba447883a8145d1fd0cf7e886d41f5b5bae9 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd
@@ -40,7 +40,8 @@ architecture tb of tb_tb_dp_repack_data is
constant c_flow : t_dp_flow_control_enum_arr := c_dp_flow_control_enum_arr;
constant c_bool : t_nat_boolean_arr := c_nat_boolean_arr;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
@@ -58,8 +59,10 @@ begin
-- g_pkt_len : NATURAL := 11; -- if not a multiple of g_in_nof_words then the input stage flush creates gap between blocks
-- g_pkt_gap : NATURAL := 0
- g_flow_control_stimuli : for I in 0 to 2 generate -- 0 = e_active, 1 = e_random, 2 = e_pulse
- g_flow_control_verify : for J in 0 to 2 generate -- 0 = e_active, 1 = e_random, 2 = e_pulse
+ -- 0 = e_active, 1 = e_random, 2 = e_pulse
+ g_flow_control_stimuli : for I in 0 to 2 generate
+ -- 0 = e_active, 1 = e_random, 2 = e_pulse
+ g_flow_control_verify : for J in 0 to 2 generate
-------------------------------------------------------------------------
-- Tests that can use bypass
@@ -71,59 +74,88 @@ begin
gen_bool_bypass : for K in 0 to 1 generate
gen_bool_bypass : for L in 0 to 1 generate
-- no repack, g_in_nof_words = g_out_nof_words = 1
- u_16_1_16_1_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 16, 1, 16, 1, c_bool(K), c_bool(L), 1, 1, c_nof_repeat, 10, 0); -- g_pkt_len > g_in_nof_words
- u_16_1_16_1_len_3_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 16, 1, 16, 1, c_bool(K), c_bool(L), 1, 1, c_nof_repeat, 3, 0); -- g_pkt_len > g_in_nof_words, odd
- u_16_1_16_1_len_2_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 16, 1, 16, 1, c_bool(K), c_bool(L), 1, 1, c_nof_repeat, 2, 0); -- g_pkt_len > g_in_nof_words, even
- u_16_1_16_1_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 16, 1, 16, 1, c_bool(K), c_bool(L), 1, 1, c_nof_repeat, 1, 0); -- g_pkt_len = g_in_nof_words
-
- u_16_1_16_1_len_1_gap_1 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 16, 1, 16, 1, c_bool(K), c_bool(L), 1, 1, c_nof_repeat, 1, 1); -- g_pkt_gap > 0
+ -- g_pkt_len > g_in_nof_words
+ u_16_1_16_1_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 16, 1, 16, 1, c_bool(K), c_bool(L), 1, 1, c_nof_repeat, 10, 0);
+ -- g_pkt_len > g_in_nof_words, odd
+ u_16_1_16_1_len_3_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 16, 1, 16, 1, c_bool(K), c_bool(L), 1, 1, c_nof_repeat, 3, 0);
+ -- g_pkt_len > g_in_nof_words, even
+ u_16_1_16_1_len_2_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 16, 1, 16, 1, c_bool(K), c_bool(L), 1, 1, c_nof_repeat, 2, 0);
+ -- g_pkt_len = g_in_nof_words
+ u_16_1_16_1_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 16, 1, 16, 1, c_bool(K), c_bool(L), 1, 1, c_nof_repeat, 1, 0);
+
+ -- g_pkt_gap > 0
+ u_16_1_16_1_len_1_gap_1 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 16, 1, 16, 1, c_bool(K), c_bool(L), 1, 1, c_nof_repeat, 1, 1);
end generate;
-- no repack, g_in_nof_words = g_out_nof_words > 1
u_16_3_16_3_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 16, 3, 16, 3, c_bool(K), c_bool(K), 1, 1, c_nof_repeat, 10, 0);
-- g_in_nof_words > g_pack_nof_words can use always active stimuli except when g_pkt_len MOD g_in_nof_words /= 0, because then the input stage needs to flush
- u_8_4_32_1_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 4, 32, 1, false, c_bool(K), 1, 1, c_nof_repeat, 1, 0); -- g_pkt_len < g_in_nof_words
- u_8_4_32_1_len_2_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 4, 32, 1, false, c_bool(K), 1, 1, c_nof_repeat, 2, 0); -- g_pkt_len = g_in_nof_words
- u_8_4_32_1_len_3_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 4, 32, 1, false, c_bool(K), 1, 1, c_nof_repeat, 3, 0); -- g_pkt_len > g_in_nof_words, MOD /= 0
- u_8_4_32_1_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 4, 32, 1, false, c_bool(K), 1, 1, c_nof_repeat, 10, 0); -- g_pkt_len > g_in_nof_words, MOD /= 0
- u_8_4_32_1_len_11_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 4, 32, 1, false, c_bool(K), 1, 1, c_nof_repeat, 11, 0); -- g_pkt_len > g_in_nof_words, MOD /= 0
- u_8_4_32_1_len_12_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 4, 32, 1, false, c_bool(K), 1, 1, c_nof_repeat, 12, 0); -- g_pkt_len > g_in_nof_words, MOD = 0
-
- u_8_4_32_1_len_12_gap_2 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 4, 32, 1, false, c_bool(K), 1, 1, c_nof_repeat, 12, 2); -- g_pkt_gap > 0
+ -- g_pkt_len < g_in_nof_words
+ u_8_4_32_1_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 4, 32, 1, false, c_bool(K), 1, 1, c_nof_repeat, 1, 0);
+ -- g_pkt_len = g_in_nof_words
+ u_8_4_32_1_len_2_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 4, 32, 1, false, c_bool(K), 1, 1, c_nof_repeat, 2, 0);
+ -- g_pkt_len > g_in_nof_words, MOD /= 0
+ u_8_4_32_1_len_3_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 4, 32, 1, false, c_bool(K), 1, 1, c_nof_repeat, 3, 0);
+ -- g_pkt_len > g_in_nof_words, MOD /= 0
+ u_8_4_32_1_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 4, 32, 1, false, c_bool(K), 1, 1, c_nof_repeat, 10, 0);
+ -- g_pkt_len > g_in_nof_words, MOD /= 0
+ u_8_4_32_1_len_11_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 4, 32, 1, false, c_bool(K), 1, 1, c_nof_repeat, 11, 0);
+ -- g_pkt_len > g_in_nof_words, MOD = 0
+ u_8_4_32_1_len_12_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 4, 32, 1, false, c_bool(K), 1, 1, c_nof_repeat, 12, 0);
+
+ -- g_pkt_gap > 0
+ u_8_4_32_1_len_12_gap_2 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 4, 32, 1, false, c_bool(K), 1, 1, c_nof_repeat, 12, 2);
-- g_in_nof_words < g_pack_nof_words will apply backpressure, because the output stage needs to output more
- u_32_1_8_4_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 32, 1, 8, 4, c_bool(K), false, 1, 1, c_nof_repeat, 1, 0); -- g_pkt_len = g_in_nof_words
- u_32_1_8_4_len_2_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 32, 1, 8, 4, c_bool(K), false, 1, 1, c_nof_repeat, 2, 0); -- g_pkt_len > g_in_nof_words
- u_32_1_8_4_len_3_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 32, 1, 8, 4, c_bool(K), false, 1, 1, c_nof_repeat, 3, 0); -- g_pkt_len > g_in_nof_words
- u_32_1_8_4_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 32, 1, 8, 4, c_bool(K), false, 1, 1, c_nof_repeat, 10, 0); -- g_pkt_len > g_in_nof_words
-
- u_32_1_8_4_len_11_gap_1 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 32, 1, 8, 4, c_bool(K), false, 1, 1, c_nof_repeat, 11, 1); -- g_pkt_gap > 0
+ -- g_pkt_len = g_in_nof_words
+ u_32_1_8_4_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 32, 1, 8, 4, c_bool(K), false, 1, 1, c_nof_repeat, 1, 0);
+ -- g_pkt_len > g_in_nof_words
+ u_32_1_8_4_len_2_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 32, 1, 8, 4, c_bool(K), false, 1, 1, c_nof_repeat, 2, 0);
+ -- g_pkt_len > g_in_nof_words
+ u_32_1_8_4_len_3_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 32, 1, 8, 4, c_bool(K), false, 1, 1, c_nof_repeat, 3, 0);
+ -- g_pkt_len > g_in_nof_words
+ u_32_1_8_4_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 32, 1, 8, 4, c_bool(K), false, 1, 1, c_nof_repeat, 10, 0);
+
+ -- g_pkt_gap > 0
+ u_32_1_8_4_len_11_gap_1 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 32, 1, 8, 4, c_bool(K), false, 1, 1, c_nof_repeat, 11, 1);
-- g_in_dat_w MOD 8 /= 0, g_in_nof_words=1
- u_14_1_8_2_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 14, 1, 8, 2, c_bool(K), false, 1, 1, c_nof_repeat, 10, 0); -- repack with subsection padding, even multiple of g_in_nof_words
- u_14_1_8_2_len_11_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 14, 1, 8, 2, c_bool(K), false, 1, 1, c_nof_repeat, 11, 0); -- repack with subsection padding, odd multiple of g_in_nof_words
+ -- repack with subsection padding, even multiple of g_in_nof_words
+ u_14_1_8_2_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 14, 1, 8, 2, c_bool(K), false, 1, 1, c_nof_repeat, 10, 0);
+ -- repack with subsection padding, odd multiple of g_in_nof_words
+ u_14_1_8_2_len_11_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 14, 1, 8, 2, c_bool(K), false, 1, 1, c_nof_repeat, 11, 0);
-- g_in_dat_w MOD 8 /= 0, g_out_nof_words=1
- u_5_2_16_1_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 5, 2, 16, 1, false, c_bool(K), 1, 1, c_nof_repeat, 10, 0); -- repack with subsection padding, integer multiple of g_in_nof_words
- u_5_2_16_1_len_11_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 5, 2, 16, 1, false, c_bool(K), 1, 1, c_nof_repeat, 11, 0); -- repack with subsection padding, fractional multiple of g_in_nof_words
+ -- repack with subsection padding, integer multiple of g_in_nof_words
+ u_5_2_16_1_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 5, 2, 16, 1, false, c_bool(K), 1, 1, c_nof_repeat, 10, 0);
+ -- repack with subsection padding, fractional multiple of g_in_nof_words
+ u_5_2_16_1_len_11_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 5, 2, 16, 1, false, c_bool(K), 1, 1, c_nof_repeat, 11, 0);
-- g_in_nof_words=1, g_pack_nof_words>1
u_8_1_4_2_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 1, 4, 2, c_bool(K), false, 1, 1, c_nof_repeat, 10, 0);
- u_512_1_32_16_len_1_gap_20 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 512, 1, 32, 16, c_bool(K), false, 1, 1, c_nof_repeat, 1, 20); -- pack a larger header slv into g_pack_dat_w words
+ -- pack a larger header slv into g_pack_dat_w words
+ u_512_1_32_16_len_1_gap_20 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 512, 1, 32, 16, c_bool(K), false, 1, 1, c_nof_repeat, 1, 20);
-- serialize to and deserialize from g_pack_dat_w=1 bit
- u_8_1_1_8_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 1, 1, 8, c_bool(K), false, 1, 1, c_nof_repeat, 10, 0); -- g_pack_dat_w=1
- u_32_1_1_32_len_10_gap_7 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 32, 1, 1, 32, c_bool(K), false, 1, 1, c_nof_repeat, 10, 7); -- g_pack_dat_w=1
+ -- g_pack_dat_w=1
+ u_8_1_1_8_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 8, 1, 1, 8, c_bool(K), false, 1, 1, c_nof_repeat, 10, 0);
+ -- g_pack_dat_w=1
+ u_32_1_1_32_len_10_gap_7 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 32, 1, 1, 32, c_bool(K), false, 1, 1, c_nof_repeat, 10, 7);
-- g_in_symbol_w /= 1, g_out_symbol_w /= 1
- u_20_1_8_3_symbol_1_4_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 20, 1, 8, 3, c_bool(K), false, 1, 4, c_nof_repeat, 10, 0); -- no repack
- u_20_1_8_3_symbol_4_1_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 20, 1, 8, 3, c_bool(K), false, 4, 1, c_nof_repeat, 10, 0); -- no repack
- u_20_1_8_3_symbol_4_4_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 20, 1, 8, 3, c_bool(K), false, 4, 4, c_nof_repeat, 10, 0); -- no repack
+ -- no repack
+ u_20_1_8_3_symbol_1_4_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 20, 1, 8, 3, c_bool(K), false, 1, 4, c_nof_repeat, 10, 0);
+ -- no repack
+ u_20_1_8_3_symbol_4_1_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 20, 1, 8, 3, c_bool(K), false, 4, 1, c_nof_repeat, 10, 0);
+ -- no repack
+ u_20_1_8_3_symbol_4_4_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 20, 1, 8, 3, c_bool(K), false, 4, 4, c_nof_repeat, 10, 0);
-- pack ETH/IP/UDP header, g_in_symbol_w = 8, g_out_symbol_w = 8
- u_336_1_32_11_symbol_8_8_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 336, 1, 32, 11, c_bool(K), false, 8, 8, c_nof_repeat, 1, 0); -- pack to 32 bit --> empty = 2
- u_336_1_64_6_symbol_8_8_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 336, 1, 64, 6, c_bool(K), false, 8, 8, c_nof_repeat, 1, 0); -- pack to 64 bit --> empty = 6
+ -- pack to 32 bit --> empty = 2
+ u_336_1_32_11_symbol_8_8_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 336, 1, 32, 11, c_bool(K), false, 8, 8, c_nof_repeat, 1, 0);
+ -- pack to 64 bit --> empty = 6
+ u_336_1_64_6_symbol_8_8_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 336, 1, 64, 6, c_bool(K), false, 8, 8, c_nof_repeat, 1, 0);
end generate;
-------------------------------------------------------------------------
@@ -131,30 +163,48 @@ begin
-------------------------------------------------------------------------
-- g_in_nof_words > 1 and g_pack_nof_words > 1
- u_24_2_16_3_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 24, 2, 16, 3, false, false, 1, 1, c_nof_repeat, 1, 0); -- g_pkt_len < g_in_nof_words
- u_24_2_16_3_len_2_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 24, 2, 16, 3, false, false, 1, 1, c_nof_repeat, 2, 0); -- g_pkt_len = g_in_nof_words
- u_24_2_16_3_len_3_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 24, 2, 16, 3, false, false, 1, 1, c_nof_repeat, 3, 0); -- g_pkt_len = fractional multiple of g_in_nof_words
- u_24_2_16_3_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 24, 2, 16, 3, false, false, 1, 1, c_nof_repeat, 10, 0); -- g_pkt_len = integer multiple of g_in_nof_words
- u_24_2_16_3_len_11_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 24, 2, 16, 3, false, false, 1, 1, c_nof_repeat, 11, 0); -- g_pkt_len = fractional multiple of g_in_nof_words
-
- u_24_2_16_3_len_11_gap_3 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 24, 2, 16, 3, false, false, 1, 1, c_nof_repeat, 11, 3); -- g_pkt_gap > 0
+ -- g_pkt_len < g_in_nof_words
+ u_24_2_16_3_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 24, 2, 16, 3, false, false, 1, 1, c_nof_repeat, 1, 0);
+ -- g_pkt_len = g_in_nof_words
+ u_24_2_16_3_len_2_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 24, 2, 16, 3, false, false, 1, 1, c_nof_repeat, 2, 0);
+ -- g_pkt_len = fractional multiple of g_in_nof_words
+ u_24_2_16_3_len_3_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 24, 2, 16, 3, false, false, 1, 1, c_nof_repeat, 3, 0);
+ -- g_pkt_len = integer multiple of g_in_nof_words
+ u_24_2_16_3_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 24, 2, 16, 3, false, false, 1, 1, c_nof_repeat, 10, 0);
+ -- g_pkt_len = fractional multiple of g_in_nof_words
+ u_24_2_16_3_len_11_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 24, 2, 16, 3, false, false, 1, 1, c_nof_repeat, 11, 0);
+
+ -- g_pkt_gap > 0
+ u_24_2_16_3_len_11_gap_3 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 24, 2, 16, 3, false, false, 1, 1, c_nof_repeat, 11, 3);
-- g_in_dat_w MOD 8 /= 0
- u_6_5_10_3_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 1, 0); -- g_pkt_len < g_in_nof_words
- u_6_5_10_3_len_2_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 2, 0); -- g_pkt_len < g_in_nof_words
- u_6_5_10_3_len_3_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 3, 0); -- g_pkt_len < g_in_nof_words
- u_6_5_10_3_len_4_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 4, 0); -- g_pkt_len < g_in_nof_words
- u_6_5_10_3_len_5_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 5, 0); -- g_pkt_len = g_in_nof_words
- u_6_5_10_3_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 10, 0); -- g_pkt_len = integer multiple of g_in_nof_words
- u_6_5_10_3_len_11_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 11, 0); -- g_pkt_len = fractional multiple of g_in_nof_words
-
- u_6_5_10_3_len_21_gap_3 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 21, 3); -- g_pkt_gap > 0
+ -- g_pkt_len < g_in_nof_words
+ u_6_5_10_3_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 1, 0);
+ -- g_pkt_len < g_in_nof_words
+ u_6_5_10_3_len_2_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 2, 0);
+ -- g_pkt_len < g_in_nof_words
+ u_6_5_10_3_len_3_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 3, 0);
+ -- g_pkt_len < g_in_nof_words
+ u_6_5_10_3_len_4_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 4, 0);
+ -- g_pkt_len = g_in_nof_words
+ u_6_5_10_3_len_5_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 5, 0);
+ -- g_pkt_len = integer multiple of g_in_nof_words
+ u_6_5_10_3_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 10, 0);
+ -- g_pkt_len = fractional multiple of g_in_nof_words
+ u_6_5_10_3_len_11_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 11, 0);
+
+ -- g_pkt_gap > 0
+ u_6_5_10_3_len_21_gap_3 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 6, 5, 10, 3, false, false, 1, 1, c_nof_repeat, 21, 3);
-- subsection padding, g_in_dat_w * g_in_nof_words < g_pack_dat_w * g_pack_nof_words
- u_18_2_8_5_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 18, 2, 8, 5, false, false, 1, 1, c_nof_repeat, 1, 0); -- g_pkt_len < g_in_nof_words
- u_18_2_8_5_len_2_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 18, 2, 8, 5, false, false, 1, 1, c_nof_repeat, 2, 0); -- g_pkt_len = g_in_nof_words
- u_18_2_8_5_len_3_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 18, 2, 8, 5, false, false, 1, 1, c_nof_repeat, 3, 0); -- g_pkt_len = fractional multiple of g_in_nof_words
- u_18_2_8_5_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 18, 2, 8, 5, false, false, 1, 1, c_nof_repeat, 10, 0); -- g_pkt_len = integer multiple of g_in_nof_words
+ -- g_pkt_len < g_in_nof_words
+ u_18_2_8_5_len_1_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 18, 2, 8, 5, false, false, 1, 1, c_nof_repeat, 1, 0);
+ -- g_pkt_len = g_in_nof_words
+ u_18_2_8_5_len_2_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 18, 2, 8, 5, false, false, 1, 1, c_nof_repeat, 2, 0);
+ -- g_pkt_len = fractional multiple of g_in_nof_words
+ u_18_2_8_5_len_3_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 18, 2, 8, 5, false, false, 1, 1, c_nof_repeat, 3, 0);
+ -- g_pkt_len = integer multiple of g_in_nof_words
+ u_18_2_8_5_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 18, 2, 8, 5, false, false, 1, 1, c_nof_repeat, 10, 0);
end generate;
end generate;
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data.vhd
index 5ac3ae84d277764295373be3050d1a32e3ca59c3..8246ef2c7d7f1af332c643ed55164040598fc55d 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data.vhd
@@ -33,7 +33,8 @@ entity tb_tb_dp_reverse_n_data is
end tb_tb_dp_reverse_n_data;
architecture tb of tb_tb_dp_reverse_n_data is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
constant c_rep_act : natural := 3;
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data_fc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data_fc.vhd
index 85ad8c0022642198169b9b41fa3ab6c06d8e99cd..aafec6c718d956b91bdd41d0e916a9681977b37e 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data_fc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data_fc.vhd
@@ -33,7 +33,8 @@ entity tb_tb_dp_reverse_n_data_fc is
end tb_tb_dp_reverse_n_data_fc;
architecture tb of tb_tb_dp_reverse_n_data_fc is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
constant c_rep_act : natural := 3;
constant c_rep_rnd : natural := 100;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd
index 484aa4dba3ca0575a2ddcace7a82e2e403ab5bd0..4ea9830c0a766517c114ec7c24ef539be83397c6 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd
@@ -35,7 +35,8 @@ entity tb_tb_dp_rsn_source is
end tb_tb_dp_rsn_source;
architecture tb of tb_tb_dp_rsn_source is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- from tb_dp_rsn_source.vhd
--
@@ -46,46 +47,71 @@ begin
-----------------------------------------------------------------------------
-- Tests with g_rs_block_size /= g_bs_block_size
-----------------------------------------------------------------------------
- u_12_3_3 : entity work.tb_dp_rsn_source generic map (12, 3, 3); -- smallest block size
- u_16_8_4 : entity work.tb_dp_rsn_source generic map (16, 8, 4); -- integer number of blocks per g_pps_interval
+ -- smallest block size
+ u_12_3_3 : entity work.tb_dp_rsn_source generic map (12, 3, 3);
+ -- integer number of blocks per g_pps_interval
+ u_16_8_4 : entity work.tb_dp_rsn_source generic map (16, 8, 4);
u_25_5 : entity work.tb_dp_rsn_source generic map (25, 5, 5);
- u_29_17_23 : entity work.tb_dp_rsn_source generic map (29, 17, 23); -- fractional number of blocks per g_pps_interval
+ -- fractional number of blocks per g_pps_interval
+ u_29_17_23 : entity work.tb_dp_rsn_source generic map (29, 17, 23);
- u_9_4_5 : entity work.tb_dp_rsn_source generic map (9, 4, 5); -- 2 g_bs_block_size < g_pps_interval < 2 g_rs_block_size
- u_9_5_4 : entity work.tb_dp_rsn_source generic map (9, 5, 4); -- 2 g_bs_block_size > g_pps_interval > 2 g_rs_block_size
- u_9_5_9 : entity work.tb_dp_rsn_source generic map (9, 5, 9); -- 1 g_rs_block_size/g_pps_interval
- u_9_9_5 : entity work.tb_dp_rsn_source generic map (9, 9, 5); -- 1 g_bs_block_size/g_pps_interval
+ -- 2 g_bs_block_size < g_pps_interval < 2 g_rs_block_size
+ u_9_4_5 : entity work.tb_dp_rsn_source generic map (9, 4, 5);
+ -- 2 g_bs_block_size > g_pps_interval > 2 g_rs_block_size
+ u_9_5_4 : entity work.tb_dp_rsn_source generic map (9, 5, 4);
+ -- 1 g_rs_block_size/g_pps_interval
+ u_9_5_9 : entity work.tb_dp_rsn_source generic map (9, 5, 9);
+ -- 1 g_bs_block_size/g_pps_interval
+ u_9_9_5 : entity work.tb_dp_rsn_source generic map (9, 9, 5);
-----------------------------------------------------------------------------
-- Same tests as with tb_dp_bsn_source_v2 with g_rs_block_size = g_bs_block_size
-----------------------------------------------------------------------------
-- test integer case
- u_20_10 : entity work.tb_dp_rsn_source generic map (20, 10, 10); -- 20 // 10 = 2, 20 MOD 10 = 0, 20/10 = 2 block/sync
- u_22_11 : entity work.tb_dp_rsn_source generic map (22, 11, 11); -- 22 // 11 = 2, 22 MOD 11 = 0, 22/11 = 2 block/sync
- u_39_13 : entity work.tb_dp_rsn_source generic map (39, 13, 13); -- 39 // 13 = 3, 39 MOD 13 = 0, 39/13 = 3 block/sync
+ -- 20 // 10 = 2, 20 MOD 10 = 0, 20/10 = 2 block/sync
+ u_20_10 : entity work.tb_dp_rsn_source generic map (20, 10, 10);
+ -- 22 // 11 = 2, 22 MOD 11 = 0, 22/11 = 2 block/sync
+ u_22_11 : entity work.tb_dp_rsn_source generic map (22, 11, 11);
+ -- 39 // 13 = 3, 39 MOD 13 = 0, 39/13 = 3 block/sync
+ u_39_13 : entity work.tb_dp_rsn_source generic map (39, 13, 13);
-- test smallest nof block per sync
- u_10_10 : entity work.tb_dp_rsn_source generic map (10, 10, 10); -- 1 block/sync
- u_5_5 : entity work.tb_dp_rsn_source generic map (5, 5, 5); -- 1 block/sync
+ -- 1 block/sync
+ u_10_10 : entity work.tb_dp_rsn_source generic map (10, 10, 10);
+ -- 1 block/sync
+ u_5_5 : entity work.tb_dp_rsn_source generic map (5, 5, 5);
-- test smallest g_block_size case
- u_3_3 : entity work.tb_dp_rsn_source generic map (3, 3, 3); -- 3 // 3 = 1, 3 MOD 3 = 0, 3/3 = 1 block/sync
- u_6_3 : entity work.tb_dp_rsn_source generic map (6, 3, 3); -- 6 // 3 = 2, 6 MOD 3 = 0, 6/3 = 2 block/sync
- u_7_3 : entity work.tb_dp_rsn_source generic map (7, 3, 3); -- 7 // 3 = 2, 7 MOD 3 = 1, 7/3 = 2.33 block/sync
+ -- 3 // 3 = 1, 3 MOD 3 = 0, 3/3 = 1 block/sync
+ u_3_3 : entity work.tb_dp_rsn_source generic map (3, 3, 3);
+ -- 6 // 3 = 2, 6 MOD 3 = 0, 6/3 = 2 block/sync
+ u_6_3 : entity work.tb_dp_rsn_source generic map (6, 3, 3);
+ -- 7 // 3 = 2, 7 MOD 3 = 1, 7/3 = 2.33 block/sync
+ u_7_3 : entity work.tb_dp_rsn_source generic map (7, 3, 3);
-- test lofar case with 0.5 fraction in average nof block/sync
- u_20_8 : entity work.tb_dp_rsn_source generic map (20, 8, 8); -- 20 // 8 = 2, 20 MOD 8 = 4, 20/8 = 2.5 block/sync
+ -- 20 // 8 = 2, 20 MOD 8 = 4, 20/8 = 2.5 block/sync
+ u_20_8 : entity work.tb_dp_rsn_source generic map (20, 8, 8);
-- test fractional (corner) cases
- u_18_9 : entity work.tb_dp_rsn_source generic map (18, 9, 9); -- 18 MOD 9 = 0
- u_17_9 : entity work.tb_dp_rsn_source generic map (17, 9, 9); -- 17 MOD 9 = 8 = g_block_size - 1
- u_19_9 : entity work.tb_dp_rsn_source generic map (19, 9, 9); -- 19 MOD 9 = 1
- u_20_9 : entity work.tb_dp_rsn_source generic map (20, 9, 9); -- 20 MOD 9 = 2
- u_25_9 : entity work.tb_dp_rsn_source generic map (25, 9, 9); -- 25 MOD 9 = 7
- u_26_9 : entity work.tb_dp_rsn_source generic map (26, 9, 9); -- 26 MOD 9 = 8 = g_block_size - 1
- u_27_9 : entity work.tb_dp_rsn_source generic map (27, 9, 9); -- 27 MOD 9 = 0
+ -- 18 MOD 9 = 0
+ u_18_9 : entity work.tb_dp_rsn_source generic map (18, 9, 9);
+ -- 17 MOD 9 = 8 = g_block_size - 1
+ u_17_9 : entity work.tb_dp_rsn_source generic map (17, 9, 9);
+ -- 19 MOD 9 = 1
+ u_19_9 : entity work.tb_dp_rsn_source generic map (19, 9, 9);
+ -- 20 MOD 9 = 2
+ u_20_9 : entity work.tb_dp_rsn_source generic map (20, 9, 9);
+ -- 25 MOD 9 = 7
+ u_25_9 : entity work.tb_dp_rsn_source generic map (25, 9, 9);
+ -- 26 MOD 9 = 8 = g_block_size - 1
+ u_26_9 : entity work.tb_dp_rsn_source generic map (26, 9, 9);
+ -- 27 MOD 9 = 0
+ u_27_9 : entity work.tb_dp_rsn_source generic map (27, 9, 9);
-- test some prime values
- u_17_3 : entity work.tb_dp_rsn_source generic map (17, 3, 3); -- 17 // 3 = 5, 17 MOD 3 = 2, 17/3 = 5.66 block/sync
- u_101_17 : entity work.tb_dp_rsn_source generic map (101, 17, 17); -- 101 // 17 = 5, 101 MOD 17 = 16, 101/17 = 5.9411 block/sync
+ -- 17 // 3 = 5, 17 MOD 3 = 2, 17/3 = 5.66 block/sync
+ u_17_3 : entity work.tb_dp_rsn_source generic map (17, 3, 3);
+ -- 101 // 17 = 5, 101 MOD 17 = 16, 101/17 = 5.9411 block/sync
+ u_101_17 : entity work.tb_dp_rsn_source generic map (101, 17, 17);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_split.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_split.vhd
index c57e02ba186424772f3462cc185007e31cb97a4d..d81955c6fee4eb26e20276cb99122e7cbac61d40 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_split.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_split.vhd
@@ -27,7 +27,8 @@ entity tb_tb_dp_split is
end tb_tb_dp_split;
architecture tb of tb_tb_dp_split is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 10
-- > run 300 us --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd
index c7195a0344274b49ae9067bc68c868505763a535..e7261acc1dd6df5aa8942fb0c0e41079ac8dacd6 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd
@@ -32,7 +32,8 @@ entity tb_tb_dp_strobe_total_count is
end tb_tb_dp_strobe_total_count;
architecture tb of tb_tb_dp_strobe_total_count is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
--g_mm_w : NATURAL := c_word_w;
--g_count_w : NATURAL := 16;
@@ -51,7 +52,10 @@ begin
u_mm32b_cnt16b_gap : entity work.tb_dp_strobe_total_count generic map(32, 16, 10,10, 10, 3);
-- Check MM high word and counter overflow (clipping)
- u_mm8b_cnt16b_high : entity work.tb_dp_strobe_total_count generic map(8, 16, 10,10, 10, 3); -- use high part
- u_mm8b_cnt9b_overflow : entity work.tb_dp_strobe_total_count generic map(8, 9, 10,10, 10, 3); -- cause overflow to clip count high part
- u_mm8b_cnt7b_overflow : entity work.tb_dp_strobe_total_count generic map(8, 7, 10,10, 10, 3); -- cause overflow to clip count low part
+ -- use high part
+ u_mm8b_cnt16b_high : entity work.tb_dp_strobe_total_count generic map(8, 16, 10,10, 10, 3);
+ -- cause overflow to clip count high part
+ u_mm8b_cnt9b_overflow : entity work.tb_dp_strobe_total_count generic map(8, 9, 10,10, 10, 3);
+ -- cause overflow to clip count low part
+ u_mm8b_cnt7b_overflow : entity work.tb_dp_strobe_total_count generic map(8, 7, 10,10, 10, 3);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_checker.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_checker.vhd
index 155a8c4c9d455a2434f1aa3a073d870511c37a83..2ebc8b39f1d75b86bedba25c000ba41e41f2da03 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_checker.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_checker.vhd
@@ -35,7 +35,8 @@ end tb_tb_dp_sync_checker;
architecture tb of tb_tb_dp_sync_checker is
constant c_nof_repeat : natural := 100;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert.vhd
index bb53bc054a6eb68f951bb45d3d8e1340d773acea..3f22b50fbcd4a27f95d2526b2c98fb2d4e56eab9 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert.vhd
@@ -34,7 +34,8 @@ end tb_tb_dp_sync_insert;
architecture tb of tb_tb_dp_sync_insert is
constant c_nof_repeat : natural := 100;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_block_size_input : NATURAL := 16;
-- g_nof_blk_per_sync_input : NATURAL := 32;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
index 78b416f87b68f92273d9b69d7376aa41a55acb29..fc2a571816c427aa02b5dfc33307d357deb51517 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
@@ -34,7 +34,8 @@ entity tb_tb_dp_sync_insert_v2 is
end tb_tb_dp_sync_insert_v2;
architecture tb of tb_tb_dp_sync_insert_v2 is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_nof_streams : NATURAL := 2;
-- g_block_size_input : NATURAL := 16;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd
index 31fedc8eb476bcdf4c6a817413676e867f7ceba2..6a64cbe896ec3f0a9990c095260c60dfbf032e6a 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd
@@ -34,7 +34,8 @@ entity tb_tb_dp_sync_recover is
end tb_tb_dp_sync_recover;
architecture tb of tb_tb_dp_sync_recover is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_nof_data_per_block : NATURAL := 16;
-- g_nof_blk_per_sync : NATURAL := 8;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_throttle_xon.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_throttle_xon.vhd
index 6b9190e1527520d0303ed79ae476a4502beaf4f4..48affb69305a4b006e96cbd58ddfd3ce71e5ad99 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_throttle_xon.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_throttle_xon.vhd
@@ -36,7 +36,8 @@ entity tb_tb_dp_throttle_xon is
end tb_tb_dp_throttle_xon;
architecture tb of tb_tb_dp_throttle_xon is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 3
-- > run -all --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_xonoff.vhd
index cfa9826d635bfd139f8fd59aa71ac3bbfd5b1c66..0efdf1f249a48fc13cdca99d4830d9cef90805f9 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_xonoff.vhd
@@ -38,7 +38,8 @@ end tb_tb_dp_xonoff;
architecture tb of tb_tb_dp_xonoff is
constant c_rep : natural := 1000;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 3
-- > run -all --> OK
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
index 9d057991883e12585a9ae236b4ef926f9bc2c579..83459fafc029f8e1521400dfcba8385b29b8ea1b 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
@@ -31,7 +31,8 @@ entity tb_tb_mmp_dp_bsn_align_v2 is
end tb_tb_mmp_dp_bsn_align_v2;
architecture tb of tb_tb_mmp_dp_bsn_align_v2 is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_lost_input : BOOLEAN := FALSE
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
index bdde22c2c0a0004de9b8a367feebd254d87fd282..f932c14ebe84b8b7e9a39f53be3cb32da9a6e053 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
@@ -35,7 +35,8 @@ entity tb_tb_mms_dp_force_data_parallel_arr is
end tb_tb_mms_dp_force_data_parallel_arr;
architecture tb of tb_tb_mms_dp_force_data_parallel_arr is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random verify ready flow control
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd
index b406e3c7e6c46c2f56e7b8f8abc196130dedc223..f838d21f0c099c6742181fdfe7e58e837a377083 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd
@@ -35,7 +35,8 @@ entity tb_tb_mms_dp_force_data_serial_arr is
end tb_tb_mms_dp_force_data_serial_arr;
architecture tb of tb_tb_mms_dp_force_data_serial_arr is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random verify ready flow control
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_arr.vhd
index 0902c69d976cdf7a166b45eeac0ff21228b459e1..b983bfab4da4f6d59205d019070ebb23bfd885f1 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_arr.vhd
@@ -36,7 +36,8 @@ entity tb_tb_mms_dp_gain_arr is
end tb_tb_mms_dp_gain_arr;
architecture tb of tb_tb_mms_dp_gain_arr is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_technology : NATURAL := c_tech_select_default;
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_serial_arr.vhd
index 96e76fd8d6549cfc1a3e7a710f9a1631b13c1ee8..b1e17517e3978807de946b79d1729cd1275ffc1a 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_serial_arr.vhd
@@ -35,7 +35,8 @@ entity tb_tb_mms_dp_gain_serial_arr is
end tb_tb_mms_dp_gain_serial_arr;
architecture tb of tb_tb_mms_dp_gain_serial_arr is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_technology : NATURAL := c_tech_select_default;
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
diff --git a/libraries/base/mm/src/vhdl/mm_arbiter.vhd b/libraries/base/mm/src/vhdl/mm_arbiter.vhd
index 0fe99f1a06ba5314bed8123b974efe0fe2caa505..3c534dc29b0637989da134eb2e137068f90eb1b3 100644
--- a/libraries/base/mm/src/vhdl/mm_arbiter.vhd
+++ b/libraries/base/mm/src/vhdl/mm_arbiter.vhd
@@ -45,8 +45,10 @@ entity mm_arbiter is
end mm_arbiter;
architecture str of mm_arbiter is
- constant c_slave_base : std_logic_vector(g_nof_slaves * 32 - 1 downto 0) := nat_arr_to_concat_slv(g_slave_base_arr, g_nof_slaves); -- Concatenated addresses; one for each slave
- constant c_slave_high : std_logic_vector(g_nof_slaves * 32 - 1 downto 0) := nat_arr_to_concat_slv(g_slave_high_arr, g_nof_slaves); -- Concatenated addresess; one for each slave
+ -- Concatenated addresses; one for each slave
+ constant c_slave_base : std_logic_vector(g_nof_slaves * 32 - 1 downto 0) := nat_arr_to_concat_slv(g_slave_base_arr, g_nof_slaves);
+ -- Concatenated addresess; one for each slave
+ constant c_slave_high : std_logic_vector(g_nof_slaves * 32 - 1 downto 0) := nat_arr_to_concat_slv(g_slave_high_arr, g_nof_slaves);
----------------------------------------------------------------------------
-- Wishbone Arbiter
@@ -54,8 +56,10 @@ architecture str of mm_arbiter is
component wbs_arbiter
generic(
NUM_SLAVES : natural;
- SLAVE_ADDR : std_logic_vector; -- NUM_SLAVES concatenated 32b integers
- SLAVE_HIGH : std_logic_vector; -- NUM_SLAVES concatenated 32b integers
+ -- NUM_SLAVES concatenated 32b integers
+ SLAVE_ADDR : std_logic_vector;
+ -- NUM_SLAVES concatenated 32b integers
+ SLAVE_HIGH : std_logic_vector;
TIMEOUT : natural
);
port (
@@ -144,7 +148,8 @@ architecture str of mm_arbiter is
----------------------------------------------------------------------------
-- Arrayed bus versions of the wbs_arbiter slave side i/o signals
----------------------------------------------------------------------------
- type t_wb_mosi is record -- Master Out Slave In
+ -- Master Out Slave In
+ type t_wb_mosi is record
cyc : std_logic;
stb : std_logic;
we : std_logic;
@@ -153,7 +158,8 @@ architecture str of mm_arbiter is
dat : std_logic_vector(c_word_w - 1 downto 0);
end record;
- type t_wb_miso is record -- Master In Slave Out
+ -- Master In Slave Out
+ type t_wb_miso is record
dat : std_logic_vector(c_word_w - 1 downto 0);
ack : std_logic;
-- err : STD_LOGIC;
@@ -199,7 +205,8 @@ begin
----------------------------------------------------------------------------
wbm_cyc_i <= master_mosi.wr or master_mosi.rd;
wbm_stb_i <= master_mosi.wr or master_mosi.rd;
- wbm_we_i <= master_mosi.wr; -- Low = implicit read
+ -- Low = implicit read
+ wbm_we_i <= master_mosi.wr;
wbm_sel_i <= (others => '1');
wbm_adr_i <= master_mosi.address(c_word_w - 1 downto 0);
wbm_dat_i <= master_mosi.wrdata(c_word_w - 1 downto 0);
diff --git a/libraries/base/mm/src/vhdl/mm_bus.vhd b/libraries/base/mm/src/vhdl/mm_bus.vhd
index 6c6bf43ccbc803bc2bad7dfdaac0f246898cf1a0..a742eed14055b9f16dc45d0c9187eb331a10ec26 100644
--- a/libraries/base/mm/src/vhdl/mm_bus.vhd
+++ b/libraries/base/mm/src/vhdl/mm_bus.vhd
@@ -110,15 +110,24 @@ use common_lib.common_mem_pkg.all;
entity mm_bus is
generic (
- g_nof_slaves : positive; -- Number of MM slave interfaces on the bus
- g_base_arr : t_nat_natural_arr; -- Address base per slave
- g_width_arr : t_nat_natural_arr; -- Address width per slave
- g_rd_latency_arr : t_nat_natural_arr; -- Read latency per slave
- g_slave_enable_arr : t_nat_boolean_arr; -- Use FALSE for not connected slaves, else TRUE
- g_waitrequest_arr : t_nat_boolean_arr; -- Enable waitrequest flow control per slave, else fixed '0'
- g_pipeline_mosi : boolean := false; -- Pipeline MM access (wr, rd)
- g_pipeline_miso_rdval : boolean := false; -- Pipeline MM read (rdval)
- g_pipeline_miso_wait : boolean := false -- Pipeline MM access flow control (waitrequest)
+ -- Number of MM slave interfaces on the bus
+ g_nof_slaves : positive;
+ -- Address base per slave
+ g_base_arr : t_nat_natural_arr;
+ -- Address width per slave
+ g_width_arr : t_nat_natural_arr;
+ -- Read latency per slave
+ g_rd_latency_arr : t_nat_natural_arr;
+ -- Use FALSE for not connected slaves, else TRUE
+ g_slave_enable_arr : t_nat_boolean_arr;
+ -- Enable waitrequest flow control per slave, else fixed '0'
+ g_waitrequest_arr : t_nat_boolean_arr;
+ -- Pipeline MM access (wr, rd)
+ g_pipeline_mosi : boolean := false;
+ -- Pipeline MM read (rdval)
+ g_pipeline_miso_rdval : boolean := false;
+ -- Pipeline MM access flow control (waitrequest)
+ g_pipeline_miso_wait : boolean := false
);
port (
mm_rst : in std_logic := '0';
diff --git a/libraries/base/mm/src/vhdl/mm_bus_comb.vhd b/libraries/base/mm/src/vhdl/mm_bus_comb.vhd
index eb27973b62cefe53239d23991a0fbcc59b29c92f..36b74d3fc5b9e17ef271196581921a16fc6099e4 100644
--- a/libraries/base/mm/src/vhdl/mm_bus_comb.vhd
+++ b/libraries/base/mm/src/vhdl/mm_bus_comb.vhd
@@ -109,10 +109,14 @@ use common_lib.common_mem_pkg.all;
entity mm_bus_comb is
generic (
- g_nof_slaves : positive; -- Number of MM slave interfaces on the bus
- g_base_arr : t_nat_natural_arr; -- Address base per slave
- g_width_arr : t_nat_natural_arr; -- Address width per slave
- g_rd_latency_arr : t_nat_natural_arr -- Read latency per slave
+ -- Number of MM slave interfaces on the bus
+ g_nof_slaves : positive;
+ -- Address base per slave
+ g_base_arr : t_nat_natural_arr;
+ -- Address width per slave
+ g_width_arr : t_nat_natural_arr;
+ -- Read latency per slave
+ g_rd_latency_arr : t_nat_natural_arr
);
port (
mm_clk : in std_logic := '0';
@@ -159,13 +163,16 @@ begin
p_index : process(master_mosi)
variable v_base : natural;
begin
- slave_index_arr(0) <= g_nof_slaves; -- default index of none existing slave
+ -- default index of none existing slave
+ slave_index_arr(0) <= g_nof_slaves;
for I in 0 to g_nof_slaves - 1 loop
v_base := TO_UINT(master_mosi.address(c_mm_bus_addr_w - 1 downto g_width_arr(I)));
assert g_base_arr(I) mod 2**g_width_arr(I) = 0 report "Slave base address must be a multiple of the slave width." severity FAILURE;
if v_base = g_base_arr(I) / 2**g_width_arr(I) then
- slave_index_arr(0) <= I; -- return index of addressed slave
- exit; -- Found addressed slave, no need to loop further. EXIT is
+ -- return index of addressed slave
+ slave_index_arr(0) <= I;
+ -- Found addressed slave, no need to loop further. EXIT is
+ exit;
-- not realy needed, because there can only be one
-- addressed slave so loop further will not change the index.
end if;
@@ -177,11 +184,13 @@ begin
-- Master access, can be write or read
p_slave_mosi_arr : process(master_mosi, slave_index_arr)
begin
- slave_mosi_arr <= (others => master_mosi); -- default assign to all, to avoid latches
+ -- default assign to all, to avoid latches
+ slave_mosi_arr <= (others => master_mosi);
for I in 0 to g_nof_slaves - 1 loop
slave_mosi_arr(I).rd <= '0';
slave_mosi_arr(I).wr <= '0';
- if I = slave_index_arr(0) then -- check index for read or write access
+ -- check index for read or write access
+ if I = slave_index_arr(0) then
slave_mosi_arr(I).rd <= master_mosi.rd;
slave_mosi_arr(I).wr <= master_mosi.wr;
end if;
@@ -192,15 +201,18 @@ begin
p_master_miso : process(slave_miso_arr, slave_index_arr)
variable v_rd_latency : natural;
begin
- master_miso <= c_mem_miso_rst; -- default clear, to avoid latches
+ -- default clear, to avoid latches
+ master_miso <= c_mem_miso_rst;
for I in 0 to g_nof_slaves - 1 loop
v_rd_latency := g_rd_latency_arr(I);
- if I = slave_index_arr(v_rd_latency) then -- check index for read response
+ -- check index for read response
+ if I = slave_index_arr(v_rd_latency) then
master_miso <= slave_miso_arr(I);
end if;
end loop;
for I in 0 to g_nof_slaves - 1 loop
- if I = slave_index_arr(0) then -- check index for waitrequest
+ -- check index for waitrequest
+ if I = slave_index_arr(0) then
master_miso.waitrequest <= slave_miso_arr(I).waitrequest;
end if;
end loop;
diff --git a/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd b/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd
index 67bcb3211ca473285534d4dd1a68583017727ba9..91987f2dd6ce9e5b063709b1cc646df6300310eb 100644
--- a/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd
+++ b/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd
@@ -106,14 +106,22 @@ use common_lib.common_mem_pkg.all;
entity mm_bus_pipe is
generic (
- g_nof_slaves : positive; -- Number of MM slave interfaces on the bus
- g_base_arr : t_nat_natural_arr; -- Address base per slave
- g_width_arr : t_nat_natural_arr; -- Address width per slave
- g_rd_latency_arr : t_nat_natural_arr; -- Read latency per slave
- g_waitrequest_arr : t_nat_boolean_arr; -- Enable waitrequest flow control per slave, else fixed '0'
- g_pipeline_mosi : boolean := false; -- Pipeline MM access (wr, rd)
- g_pipeline_miso_rdval : boolean := false; -- Pipeline MM read (rdval)
- g_pipeline_miso_wait : boolean := false -- Pipeline MM access flow control (waitrequest)
+ -- Number of MM slave interfaces on the bus
+ g_nof_slaves : positive;
+ -- Address base per slave
+ g_base_arr : t_nat_natural_arr;
+ -- Address width per slave
+ g_width_arr : t_nat_natural_arr;
+ -- Read latency per slave
+ g_rd_latency_arr : t_nat_natural_arr;
+ -- Enable waitrequest flow control per slave, else fixed '0'
+ g_waitrequest_arr : t_nat_boolean_arr;
+ -- Pipeline MM access (wr, rd)
+ g_pipeline_mosi : boolean := false;
+ -- Pipeline MM read (rdval)
+ g_pipeline_miso_rdval : boolean := false;
+ -- Pipeline MM access flow control (waitrequest)
+ g_pipeline_miso_wait : boolean := false
);
port (
mm_rst : in std_logic;
diff --git a/libraries/base/mm/src/vhdl/mm_fields.vhd b/libraries/base/mm/src/vhdl/mm_fields.vhd
index 6538f9f9122acabc1ae2ab647fe8af06779bbbde..c279dc6b3fe8dc2f98779605674374a1e73c8bd4 100644
--- a/libraries/base/mm/src/vhdl/mm_fields.vhd
+++ b/libraries/base/mm/src/vhdl/mm_fields.vhd
@@ -74,7 +74,8 @@ use common_lib.common_field_pkg.all;
entity mm_fields is
generic (
g_cross_clock_domain : boolean := true;
- g_use_slv_in_val : boolean := true; -- use TRUE when slv_in_val is used, use FALSE to save logic when always slv_in_val='1'
+ -- use TRUE when slv_in_val is used, use FALSE to save logic when always slv_in_val='1'
+ g_use_slv_in_val : boolean := true;
g_field_arr : t_common_field_arr
);
port (
@@ -88,10 +89,13 @@ entity mm_fields is
slv_clk : in std_logic;
--fields in these SLVs are defined by g_field_arr
- slv_in : in std_logic_vector(field_slv_in_len( g_field_arr) - 1 downto 0) := (others => '0'); -- slv of all "RO" fields in g_field_arr
- slv_in_val : in std_logic := '0'; -- strobe to signal that slv_in is valid and needs to be captured
+ -- slv of all "RO" fields in g_field_arr
+ slv_in : in std_logic_vector(field_slv_in_len( g_field_arr) - 1 downto 0) := (others => '0');
+ -- strobe to signal that slv_in is valid and needs to be captured
+ slv_in_val : in std_logic := '0';
- slv_out : out std_logic_vector(field_slv_out_len(g_field_arr) - 1 downto 0) -- slv of all "RW" fields in g_field_arr
+ -- slv of all "RW" fields in g_field_arr
+ slv_out : out std_logic_vector(field_slv_out_len(g_field_arr) - 1 downto 0)
);
end mm_fields;
diff --git a/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd b/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd
index 558c4202196059480b0f632175661bc7d10ceffe..e97b111d81c62a5362ee17d32f932e587fe58339 100644
--- a/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd
+++ b/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd
@@ -39,7 +39,8 @@ use common_lib.common_mem_pkg.all;
entity mm_latency_adapter is
generic (
- g_adapt : boolean := true -- default when TRUE then decrease sink RL 1 to source RL 0, else then implement wires
+ -- default when TRUE then decrease sink RL 1 to source RL 0, else then implement wires
+ g_adapt : boolean := true
);
port (
mm_rst : in std_logic;
@@ -55,7 +56,8 @@ end mm_latency_adapter;
architecture str of mm_latency_adapter is
-- Sum of all t_mem_mosi fields widths (synthesis will optimize away unused address and data bits)
- constant c_data_w : natural := c_mem_address_w + c_mem_data_w + 2; -- 32 + 72 + 1 (wr) + 1 (rd) = 106
+ -- 32 + 72 + 1 (wr) + 1 (rd) = 106
+ constant c_data_w : natural := c_mem_address_w + c_mem_data_w + 2;
signal in_waitrequest : std_logic;
signal in_data : std_logic_vector(c_data_w - 1 downto 0);
diff --git a/libraries/base/mm/src/vhdl/mm_master_mux.vhd b/libraries/base/mm/src/vhdl/mm_master_mux.vhd
index 0eb66110d923d0a6903c1a12df28762a26adc1db..7fc12919faa986f5b024824ecca5910213da31a6 100644
--- a/libraries/base/mm/src/vhdl/mm_master_mux.vhd
+++ b/libraries/base/mm/src/vhdl/mm_master_mux.vhd
@@ -63,8 +63,10 @@ use common_lib.common_mem_pkg.all;
entity mm_master_mux is
generic (
- g_nof_masters : positive; -- Number of MM masters
- g_rd_latency_min : natural -- Minimum read latency
+ -- Number of MM masters
+ g_nof_masters : positive;
+ -- Minimum read latency
+ g_rd_latency_min : natural
);
port (
mm_clk : in std_logic;
@@ -98,11 +100,14 @@ begin
-- the index value in wave window.
p_index : process(master_mosi_arr, index_hold)
begin
- index <= index_hold; -- default hold index of last active master
+ -- default hold index of last active master
+ index <= index_hold;
for I in 0 to g_nof_masters - 1 loop
if master_mosi_arr(I).wr = '1' or master_mosi_arr(I).rd = '1' then
- index <= I; -- index of active master
- exit; -- Found active master, no need to loop further. EXIT is not
+ -- index of active master
+ index <= I;
+ -- Found active master, no need to loop further. EXIT is not
+ exit;
-- realy needed, because there should be only one active
-- master, and if there are more active masters, then it
-- does not matter whether the first or the last is selected.
@@ -110,7 +115,8 @@ begin
end loop;
end process;
- index_hold <= index when rising_edge(mm_clk); -- hold index of last active master
+ -- hold index of last active master
+ index_hold <= index when rising_edge(mm_clk);
-- Multiplex master access, can be write or read
mux_mosi <= master_mosi_arr(index);
@@ -118,7 +124,8 @@ begin
-- Multiplex slave read response
p_miso : process(mux_miso, index, index_hold)
begin
- master_miso_arr <= (others => mux_miso); -- default assign to all, to avoid latches
+ -- default assign to all, to avoid latches
+ master_miso_arr <= (others => mux_miso);
for I in 0 to g_nof_masters - 1 loop
master_miso_arr(I).rdval <= '0';
-- If the minimal read latency is g_rd_latency_min = 0, then the mux
diff --git a/libraries/base/mm/src/vhdl/mm_pipeline.vhd b/libraries/base/mm/src/vhdl/mm_pipeline.vhd
index bef70460dde95a8ed47837445161a6c647e80d13..f637cc13cea7970b3763371c1b54a3778bfa81c0 100644
--- a/libraries/base/mm/src/vhdl/mm_pipeline.vhd
+++ b/libraries/base/mm/src/vhdl/mm_pipeline.vhd
@@ -127,7 +127,8 @@ begin
p_reg : process(mm_rst, mm_clk)
begin
if mm_rst = '1' then
- mosi_reg <= RESET_MEM_MOSI_CTRL(mosi_reg); -- todo: check with synthesis that mosi_reg data fields remain wires
+ -- todo: check with synthesis that mosi_reg data fields remain wires
+ mosi_reg <= RESET_MEM_MOSI_CTRL(mosi_reg);
elsif rising_edge(mm_clk) then
mosi_reg <= nxt_mosi_reg;
end if;
@@ -141,8 +142,10 @@ begin
begin
out_mosi <= mosi_reg;
if ready /= '1' then
- out_mosi.wr <= '0'; -- out_mosi.wr = mosi_reg.wr AND ready
- out_mosi.rd <= '0'; -- out_mosi.rd = mosi_reg.rd AND ready
+ -- out_mosi.wr = mosi_reg.wr AND ready
+ out_mosi.wr <= '0';
+ -- out_mosi.rd = mosi_reg.rd AND ready
+ out_mosi.rd <= '0';
end if;
end process;
end generate;
diff --git a/libraries/base/mm/src/vhdl/mm_slave_enable.vhd b/libraries/base/mm/src/vhdl/mm_slave_enable.vhd
index dad3178dbd6da0915f82035e63c39f1a990a9331..d64c8bd4c2560d0eb99eef6a69e14db13dd6f046 100644
--- a/libraries/base/mm/src/vhdl/mm_slave_enable.vhd
+++ b/libraries/base/mm/src/vhdl/mm_slave_enable.vhd
@@ -93,8 +93,10 @@ begin
p_in_miso : process(rdval)
begin
- in_miso <= c_mem_miso_rst; -- force all miso to 0, so rddata = 0 and no waitrequest
- in_miso.rdval <= rdval; -- support rdval to avoid hanging master that waits for rdval
+ -- force all miso to 0, so rddata = 0 and no waitrequest
+ in_miso <= c_mem_miso_rst;
+ -- support rdval to avoid hanging master that waits for rdval
+ in_miso.rdval <= rdval;
end process;
end generate;
diff --git a/libraries/base/mm/src/vhdl/mm_slave_mux.vhd b/libraries/base/mm/src/vhdl/mm_slave_mux.vhd
index 09459a54a91bfa2baca83a2dd8ec974e634c9413..de0cbdb4e565ec177c0365f270844e0d2b7e821e 100644
--- a/libraries/base/mm/src/vhdl/mm_slave_mux.vhd
+++ b/libraries/base/mm/src/vhdl/mm_slave_mux.vhd
@@ -36,9 +36,12 @@ use common_lib.common_mem_pkg.all;
entity mm_slave_mux is
generic (
- g_broadcast : boolean := false; -- TRUE use port[0] to access all, else use separate ports
- g_nof_mosi : positive := 256; -- Number of slave memory interfaces in the array.
- g_mosi_addr_w : positive := 8 -- Address width per slave
+ -- TRUE use port[0] to access all, else use separate ports
+ g_broadcast : boolean := false;
+ -- Number of slave memory interfaces in the array.
+ g_nof_mosi : positive := 256;
+ -- Address width per slave
+ g_mosi_addr_w : positive := 8
);
port (
mosi : in t_mem_mosi;
@@ -58,7 +61,8 @@ begin
g_rd_latency => 0
)
port map (
- clk => '0', -- only used when g_rd_latency > 0
+ -- only used when g_rd_latency > 0
+ clk => '0',
mosi => mosi,
miso => miso,
mosi_arr => mosi_arr,
diff --git a/libraries/base/mm/tb/vhdl/mm_file.vhd b/libraries/base/mm/tb/vhdl/mm_file.vhd
index f04fb7d4b0b12414ad989f9ff6eaf97d7f09a669..b71f1154af0e540db0e6cea7c67eace54d32f6e4 100644
--- a/libraries/base/mm/tb/vhdl/mm_file.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file.vhd
@@ -90,11 +90,16 @@ use std.textio.all;
entity mm_file is
generic (
- g_file_prefix : string; -- e.g. "ppsh" will create i/o files ppsh_stat.txt and ppsh_ctrl.txt
- g_file_enable : std_logic := '1'; -- default use '1' to enable file IO, use '0' to disable file IO and force mm_master_out to c_mem_mosi_rst
- g_mm_rd_latency : natural := 2; -- default use 2 to fit 0, 1 or 2, must be >= read latency of the MM slave
- g_mm_timeout : time := c_mmf_mm_timeout; -- use 0 ns for full speed MM, use > 0 ns to define time without MM access after which the MM file IO is paused
- g_mm_pause : time := c_mmf_mm_pause -- defines time for which MM file IO is paused to reduce the file IO rate when the MM slave is idle
+ -- e.g. "ppsh" will create i/o files ppsh_stat.txt and ppsh_ctrl.txt
+ g_file_prefix : string;
+ -- default use '1' to enable file IO, use '0' to disable file IO and force mm_master_out to c_mem_mosi_rst
+ g_file_enable : std_logic := '1';
+ -- default use 2 to fit 0, 1 or 2, must be >= read latency of the MM slave
+ g_mm_rd_latency : natural := 2;
+ -- use 0 ns for full speed MM, use > 0 ns to define time without MM access after which the MM file IO is paused
+ g_mm_timeout : time := c_mmf_mm_timeout;
+ -- defines time for which MM file IO is paused to reduce the file IO rate when the MM slave is idle
+ g_mm_pause : time := c_mmf_mm_pause
);
port (
mm_rst : in std_logic;
@@ -114,7 +119,8 @@ architecture str of mm_file is
-- Optional file IO throttle control
signal strobe : std_logic;
signal pause : std_logic;
- signal polling : std_logic := '0'; -- monitor signal to view in Wave window when mmf_mm_from_file() is busy
+ -- monitor signal to view in Wave window when mmf_mm_from_file() is busy
+ signal polling : std_logic := '0';
signal timebegin : time := 0 ns;
signal timeout : time := 0 ns;
begin
@@ -139,9 +145,11 @@ begin
-- Optional file IO throttle control
if g_mm_timeout > 0 ns and pause = '1' then
polling <= '0';
- wait for g_mm_pause; -- Pause the file IO when MM timeout is enabled and no strobes appeared for g_mm_timeout
+ -- Pause the file IO when MM timeout is enabled and no strobes appeared for g_mm_timeout
+ wait for g_mm_pause;
- proc_common_wait_some_cycles(mm_clk, 1); -- Realign to mm_clk, not needed but done to resemble return from mmf_mm_from_file()
+ -- Realign to mm_clk, not needed but done to resemble return from mmf_mm_from_file()
+ proc_common_wait_some_cycles(mm_clk, 1);
polling <= '1';
end if;
end loop;
@@ -151,9 +159,11 @@ begin
-- Optional file IO throttle control
gen_mm_timeout_control : if g_mm_timeout > 0 ns generate
- strobe <= i_mm_master_out.wr or i_mm_master_out.rd; -- detect MM access
+ -- detect MM access
+ strobe <= i_mm_master_out.wr or i_mm_master_out.rd;
- pause <= not strobe when timeout > g_mm_timeout else '0'; -- issue MM file IO pause after strobe timeout
+ -- issue MM file IO pause after strobe timeout
+ pause <= not strobe when timeout > g_mm_timeout else '0';
-- Use mm_clk event to update time based on NOW, without event it does not update
p_mm_now : process(mm_rst, mm_clk)
diff --git a/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd b/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
index c742fee2212f2208e92002aa56db6337d3f19d5f..69f4df7660f86bd722f2bb54f1ce4a8841d80366 100644
--- a/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
@@ -125,13 +125,16 @@ use common_lib.common_str_pkg.all;
package mm_file_pkg is
-- Constants used by mm_file.vhd
- constant c_mmf_mm_clk_period : time := 100 ps; -- Default mm_clk period in simulation. Set much faster than DP clock to speed up
+ -- Default mm_clk period in simulation. Set much faster than DP clock to speed up
+ constant c_mmf_mm_clk_period : time := 100 ps;
-- simulation of MM access. Without file IO throttling 100 ps is a good balance
-- between simulation speed and file IO rate.
- constant c_mmf_mm_timeout : time := 1000 ns; -- Default MM file IO timeout period. Set large enough to account for MM-DP clock
+ -- Default MM file IO timeout period. Set large enough to account for MM-DP clock
+ constant c_mmf_mm_timeout : time := 1000 ns;
-- domain crossing delays. Use 0 ns to disable file IO throttling, to have file IO
-- at the mm_clk rate.
- constant c_mmf_mm_pause : time := 100 ns; -- Default MM file IO pause period after timeout. Balance between file IO rate
+ -- Default MM file IO pause period after timeout. Balance between file IO rate
+ constant c_mmf_mm_pause : time := 100 ns;
-- reduction and responsiveness to new MM access.
-- Procedure to (re)create empty file
@@ -161,25 +164,32 @@ package mm_file_pkg is
-- Procedures that keep reading the file until it has been made empty or not empty by some other program,
-- to ensure the file is ready for a new write access
- procedure mmf_wait_for_file_status(rd_filename : in string; -- file name with extension
+ -- file name with extension
+ procedure mmf_wait_for_file_status(rd_filename : in string;
exit_on_empty : in boolean;
signal mm_clk : in std_logic);
- procedure mmf_wait_for_file_empty(rd_filename : in string; -- file name with extension
+ -- file name with extension
+ procedure mmf_wait_for_file_empty(rd_filename : in string;
signal mm_clk : in std_logic);
- procedure mmf_wait_for_file_not_empty(rd_filename : in string; -- file name with extension
+ -- file name with extension
+ procedure mmf_wait_for_file_not_empty(rd_filename : in string;
signal mm_clk : in std_logic);
-- Procedure to issue a write access via the MM request .ctrl file
- procedure mmf_mm_bus_wr(filename : in string; -- file name without extension
- wr_addr : in integer; -- use integer to support full 32 bit range
+ -- file name without extension
+ procedure mmf_mm_bus_wr(filename : in string;
+ -- use integer to support full 32 bit range
+ wr_addr : in integer;
wr_data : in integer;
signal mm_clk : in std_logic);
-- Procedure to issue a read access via the MM request .ctrl file and get the read data from the MM response file
- procedure mmf_mm_bus_rd(filename : in string; -- file name without extension
+ -- file name without extension
+ procedure mmf_mm_bus_rd(filename : in string;
rd_latency : in natural;
- rd_addr : in integer; -- use integer to support full 32 bit range
+ -- use integer to support full 32 bit range
+ rd_addr : in integer;
signal rd_data : out std_logic_vector(c_word_w - 1 downto 0);
signal mm_clk : in std_logic);
-- . rd_latency = 1
@@ -189,24 +199,31 @@ package mm_file_pkg is
signal mm_clk : in std_logic);
-- Procedure that reads the rd_data every rd_interval until has the specified rd_value, the proc arguments can be understood as a sentence
- procedure mmf_mm_wait_until_value(filename : in string; -- file name without extension
+ -- file name without extension
+ procedure mmf_mm_wait_until_value(filename : in string;
rd_addr : in integer;
- c_representation : in string; -- treat rd_data as "SIGNED" or "UNSIGNED" 32 bit word
+ -- treat rd_data as "SIGNED" or "UNSIGNED" 32 bit word
+ c_representation : in string;
signal rd_data : inout std_logic_vector(c_word_w - 1 downto 0);
- c_condition : in string; -- ">", ">=", "=", "<=", "<", "/="
+ -- ">", ">=", "=", "<=", "<", "/="
+ c_condition : in string;
c_rd_value : in integer;
c_rd_interval : in time;
signal mm_clk : in std_logic);
-- Procedure to get NOW via simulator status
- procedure mmf_sim_get_now(filename : in string; -- file name without extension
+ -- file name without extension
+ procedure mmf_sim_get_now(filename : in string;
signal rd_now : out string;
signal mm_clk : in std_logic);
-- Functions to create prefixes for the mmf file filename
- function mmf_prefix(name : string; index : natural) return string; -- generic prefix name with index to be used for a file IO filename
- function mmf_tb_prefix(tb : integer) return string; -- fixed test bench prefix with index tb to allow file IO with multi tb
- function mmf_subrack_prefix(subrack : integer) return string; -- fixed subrack prefix with index subrack to allow file IO with multi subracks that use same unb numbers
+ -- generic prefix name with index to be used for a file IO filename
+ function mmf_prefix(name : string; index : natural) return string;
+ -- fixed test bench prefix with index tb to allow file IO with multi tb
+ function mmf_tb_prefix(tb : integer) return string;
+ -- fixed subrack prefix with index subrack to allow file IO with multi subracks that use same unb numbers
+ function mmf_subrack_prefix(subrack : integer) return string;
-- Functions to create mmf file prefix that is unique per slave, for increasing number of hierarchy levels:
-- . return "filepath/s0_i0_"
@@ -220,7 +237,8 @@ package mm_file_pkg is
function mmf_slave_prefix(dir_path, s0 : string; i0 : natural; s1 : string; i1 : natural; s2 : string; i2 : natural; s3 : string; i3 : natural) return string;
function mmf_slave_prefix(dir_path, s0 : string; i0 : natural; s1 : string; i1 : natural; s2 : string; i2 : natural; s3 : string; i3 : natural; s4 : string; i4 : natural) return string;
- constant c_mmf_local_dir_path : string := "mmfiles/"; -- local directory in project file build directory
+ -- local directory in project file build directory
+ constant c_mmf_local_dir_path : string := "mmfiles/";
function mmf_slave_prefix(s0 : string; i0 : natural) return string;
function mmf_slave_prefix(s0 : string; i0 : natural; s1 : string; i1 : natural) return string;
function mmf_slave_prefix(s0 : string; i0 : natural; s1 : string; i1 : natural; s2 : string; i2 : natural) return string;
@@ -281,7 +299,8 @@ package body mm_file_pkg is
variable v_addr_slv : std_logic_vector(c_word_w - 1 downto 0);
variable v_data_slv : std_logic_vector(c_word_w - 1 downto 0);
- variable v_rd_wr_str : string(1 to 2); -- Contains 'RD' or 'WR'
+ -- Contains 'RD' or 'WR'
+ variable v_rd_wr_str : string(1 to 2);
begin
@@ -302,12 +321,14 @@ package body mm_file_pkg is
-- The second line represents the address offset:
readline(rd_file, rd_line);
- hread(rd_line, v_addr_slv); -- read the string as HEX and assign to SLV.
+ -- read the string as HEX and assign to SLV.
+ hread(rd_line, v_addr_slv);
-- Write only: The third line contains the data to write:
if v_rd_wr_str = "WR" then
readline(rd_file, rd_line);
- hread(rd_line, v_data_slv); -- read the string as HEX and assign to SLV.
+ -- read the string as HEX and assign to SLV.
+ hread(rd_line, v_data_slv);
end if;
-- We're done reading MM request from the .ctrl file.
@@ -364,7 +385,8 @@ package body mm_file_pkg is
variable rd_line : LINE;
variable wr_line : LINE;
- variable v_rd_wr_str : string(1 to 12); -- "GET_SIM_TIME"
+ -- "GET_SIM_TIME"
+ variable v_rd_wr_str : string(1 to 12);
begin
@@ -434,7 +456,8 @@ package body mm_file_pkg is
end;
- procedure mmf_wait_for_file_status(rd_filename : in string; -- file name with extension
+ -- file name with extension
+ procedure mmf_wait_for_file_status(rd_filename : in string;
exit_on_empty : in boolean;
signal mm_clk : in std_logic) is
file rd_file : TEXT;
@@ -479,20 +502,24 @@ package body mm_file_pkg is
-- The END implicitely close the file, if still necessary.
end;
- procedure mmf_wait_for_file_empty(rd_filename : in string; -- file name with extension
+ -- file name with extension
+ procedure mmf_wait_for_file_empty(rd_filename : in string;
signal mm_clk : in std_logic) is
begin
mmf_wait_for_file_status(rd_filename, true, mm_clk);
end;
- procedure mmf_wait_for_file_not_empty(rd_filename : in string; -- file name with extension
+ -- file name with extension
+ procedure mmf_wait_for_file_not_empty(rd_filename : in string;
signal mm_clk : in std_logic) is
begin
mmf_wait_for_file_status(rd_filename, false, mm_clk);
end;
- procedure mmf_mm_bus_wr(filename : in string; -- file name without extension
- wr_addr : in integer; -- use integer to support full 32 bit range
+ -- file name without extension
+ procedure mmf_mm_bus_wr(filename : in string;
+ -- use integer to support full 32 bit range
+ wr_addr : in integer;
wr_data : in integer;
signal mm_clk : in std_logic) is
constant ctrl_filename : string := filename & ".ctrl";
@@ -525,9 +552,11 @@ package body mm_file_pkg is
-- The END implicitely close the ctrl_file, if still necessary.
end;
- procedure mmf_mm_bus_rd(filename : in string; -- file name without extension
+ -- file name without extension
+ procedure mmf_mm_bus_rd(filename : in string;
rd_latency : in natural;
- rd_addr : in integer; -- use integer to support full 32 bit range
+ -- use integer to support full 32 bit range
+ rd_addr : in integer;
signal rd_data : out std_logic_vector(c_word_w - 1 downto 0);
signal mm_clk : in std_logic) is
constant ctrl_filename : string := filename & ".ctrl";
@@ -593,39 +622,47 @@ package body mm_file_pkg is
mmf_mm_bus_rd(filename, 1, rd_addr, rd_data, mm_clk);
end;
- procedure mmf_mm_wait_until_value(filename : in string; -- file name without extension
+ -- file name without extension
+ procedure mmf_mm_wait_until_value(filename : in string;
rd_addr : in integer;
- c_representation : in string; -- treat rd_data as "SIGNED" or "UNSIGNED" 32 bit word
+ -- treat rd_data as "SIGNED" or "UNSIGNED" 32 bit word
+ c_representation : in string;
signal rd_data : inout std_logic_vector(c_word_w - 1 downto 0);
- c_condition : in string; -- ">", ">=", "=", "<=", "<", "/="
+ -- ">", ">=", "=", "<=", "<", "/="
+ c_condition : in string;
c_rd_value : in integer;
c_rd_interval : in time;
signal mm_clk : in std_logic) is
begin
while true loop
-- Read current
- mmf_mm_bus_rd(filename, rd_addr, rd_data, mm_clk); -- only read low part
+ -- only read low part
+ mmf_mm_bus_rd(filename, rd_addr, rd_data, mm_clk);
if c_representation = "SIGNED" then
if c_condition = ">" then if TO_SINT(rd_data) > c_rd_value then exit; else wait for c_rd_interval; end if;
elsif c_condition = ">=" then if TO_SINT(rd_data) >= c_rd_value then exit; else wait for c_rd_interval; end if;
elsif c_condition = "/=" then if TO_SINT(rd_data) /= c_rd_value then exit; else wait for c_rd_interval; end if;
elsif c_condition = "<=" then if TO_SINT(rd_data) <= c_rd_value then exit; else wait for c_rd_interval; end if;
elsif c_condition = "<" then if TO_SINT(rd_data) < c_rd_value then exit; else wait for c_rd_interval; end if;
- else if TO_SINT(rd_data) = c_rd_value then exit; else wait for c_rd_interval; end if; -- default: "="
+ -- default: "="
+ else if TO_SINT(rd_data) = c_rd_value then exit; else wait for c_rd_interval; end if;
end if;
- else -- default: UNSIGED
+ -- default: UNSIGED
+ else
if c_condition = ">" then if TO_UINT(rd_data) > c_rd_value then exit; else wait for c_rd_interval; end if;
elsif c_condition = ">=" then if TO_UINT(rd_data) >= c_rd_value then exit; else wait for c_rd_interval; end if;
elsif c_condition = "/=" then if TO_UINT(rd_data) /= c_rd_value then exit; else wait for c_rd_interval; end if;
elsif c_condition = "<=" then if TO_UINT(rd_data) <= c_rd_value then exit; else wait for c_rd_interval; end if;
elsif c_condition = "<" then if TO_UINT(rd_data) < c_rd_value then exit; else wait for c_rd_interval; end if;
- else if TO_UINT(rd_data) = c_rd_value then exit; else wait for c_rd_interval; end if; -- default: "="
+ -- default: "="
+ else if TO_UINT(rd_data) = c_rd_value then exit; else wait for c_rd_interval; end if;
end if;
end if;
end loop;
end mmf_mm_wait_until_value;
- procedure mmf_sim_get_now(filename : in string; -- file name without extension
+ -- file name without extension
+ procedure mmf_sim_get_now(filename : in string;
signal rd_now : out string;
signal mm_clk : in std_logic) is
constant ctrl_filename : string := filename & ".ctrl";
diff --git a/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd b/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
index ded649d443f664fa0b687b2155861a762fb658a5..ff02a8e41169796ff62671945040949f6c1632b6 100644
--- a/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
@@ -26,24 +26,32 @@ use work.mm_file_pkg.all;
package mm_file_unb_pkg is
type t_c_mmf_unb_sys is record
- nof_unb : natural; -- Nof used UniBoard in our system [0..nof_unb-1]
- nof_fn : natural; -- Nof used FNs [0..nof_fn-1] per UniBoard
- nof_bn : natural; -- Nof used BNs [0..nof_fn-1] per UniBoard
+ -- Nof used UniBoard in our system [0..nof_unb-1]
+ nof_unb : natural;
+ -- Nof used FNs [0..nof_fn-1] per UniBoard
+ nof_fn : natural;
+ -- Nof used BNs [0..nof_fn-1] per UniBoard
+ nof_bn : natural;
end record;
constant c_mmf_unb_nof_fn : natural := 4;
constant c_mmf_unb_nof_bn : natural := 4;
- constant c_mmf_unb_nof_pn : natural := c_mmf_unb_nof_fn + c_mmf_unb_nof_bn; -- = 8
+ -- = 8
+ constant c_mmf_unb_nof_pn : natural := c_mmf_unb_nof_fn + c_mmf_unb_nof_bn;
-- use fixed central directory to ease use of Python test case with Modelsim
constant c_mmf_unb_file_path : string := "$HDL_IOFILE_SIM_DIR/";
-- create mmf file prefix that is unique per slave
function mmf_unb_file_prefix(sys: t_c_mmf_unb_sys; node: natural) return string;
- function mmf_unb_file_prefix( unb, node: natural; node_type: string) return string; -- unb 0,1,..., node = 0:3 for FN or BN
- function mmf_unb_file_prefix( unb, node: natural) return string; -- unb 0,1,..., node = 0:7, with 0:3 for FN and 4:7 for BN
- function mmf_unb_file_prefix(tb, unb, node: natural) return string; -- idem, with extra index tb = 0,1,... for use with multi testbench
- function mmf_unb_file_prefix(tb, subrack, unb, node: natural) return string; -- idem, with extra index subrack = 0,1,... to support same local unb range per subrack
+ -- unb 0,1,..., node = 0:3 for FN or BN
+ function mmf_unb_file_prefix( unb, node: natural; node_type: string) return string;
+ -- unb 0,1,..., node = 0:7, with 0:3 for FN and 4:7 for BN
+ function mmf_unb_file_prefix( unb, node: natural) return string;
+ -- idem, with extra index tb = 0,1,... for use with multi testbench
+ function mmf_unb_file_prefix(tb, unb, node: natural) return string;
+ -- idem, with extra index subrack = 0,1,... to support same local unb range per subrack
+ function mmf_unb_file_prefix(tb, subrack, unb, node: natural) return string;
end mm_file_unb_pkg;
@@ -71,7 +79,8 @@ package body mm_file_unb_pkg is
function mmf_unb_file_prefix(unb, node: natural) return string is
-- Use this function and pass the UNB and node 0:7 index.
constant c_node_type : string(1 to 2) := sel_a_b(node >= c_mmf_unb_nof_fn, "BN", "FN");
- constant c_node_nr : natural := node mod c_mmf_unb_nof_fn; -- PN 0:3 --> FN 0:3, PN 4:7 --> BN 0:3
+ -- PN 0:3 --> FN 0:3, PN 4:7 --> BN 0:3
+ constant c_node_nr : natural := node mod c_mmf_unb_nof_fn;
begin
return mmf_slave_prefix(c_mmf_unb_file_path, "UNB", unb, c_node_type, c_node_nr);
end;
@@ -79,7 +88,8 @@ package body mm_file_unb_pkg is
function mmf_unb_file_prefix(tb, unb, node: natural) return string is
-- Use this function and pass the UNB and node 0:7 index and a test bench index to allow file IO with multi tb.
constant c_node_type : string(1 to 2) := sel_a_b(node >= c_mmf_unb_nof_fn, "BN", "FN");
- constant c_node_nr : natural := node mod c_mmf_unb_nof_fn; -- PN 0:3 --> FN 0:3, PN 4:7 --> BN 0:3
+ -- PN 0:3 --> FN 0:3, PN 4:7 --> BN 0:3
+ constant c_node_nr : natural := node mod c_mmf_unb_nof_fn;
begin
return mmf_slave_prefix(c_mmf_unb_file_path, "TB", tb, "UNB", unb, c_node_type, c_node_nr);
end;
@@ -87,7 +97,8 @@ package body mm_file_unb_pkg is
function mmf_unb_file_prefix(tb, subrack, unb, node: natural) return string is
-- Use this function and pass the UNB and node 0:7 index and a test bench index to allow file IO with multi subrack and multi tb.
constant c_node_type : string(1 to 2) := sel_a_b(node >= c_mmf_unb_nof_fn, "BN", "FN");
- constant c_node_nr : natural := node mod c_mmf_unb_nof_fn; -- PN 0:3 --> FN 0:3, PN 4:7 --> BN 0:3
+ -- PN 0:3 --> FN 0:3, PN 4:7 --> BN 0:3
+ constant c_node_nr : natural := node mod c_mmf_unb_nof_fn;
begin
return mmf_slave_prefix(c_mmf_unb_file_path, "TB", tb, "SUBRACK", subrack, "UNB", unb, c_node_type, c_node_nr);
end;
diff --git a/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd b/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd
index 7584ee79839bcbafca5a926816cb91d0a16b03ba..7be4e2cdfbf5d5a99aa2c5a981ff5522579a5c18 100644
--- a/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd
@@ -69,7 +69,8 @@ entity mm_waitrequest_model is
end mm_waitrequest_model;
architecture rtl of mm_waitrequest_model is
- constant c_prsg_init : natural := g_seed + 1; -- PRSG init must be > 0
+ -- PRSG init must be > 0
+ constant c_prsg_init : natural := g_seed + 1;
signal prsg : std_logic_vector(g_prsg_w - 1 downto 0) := TO_UVEC(c_prsg_init, g_prsg_w);
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd b/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
index 7c4046568a12ac401061a6446db41fb82def5e45..72de36db2b668fd5a1aedbf8009d6d66a45fa45e 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
@@ -54,11 +54,16 @@ use common_lib.tb_common_mem_pkg.all;
entity tb_mm_bus is
generic (
- g_nof_slaves : positive := 1; -- Number of slave memory interfaces on the MM bus array.
- g_base_offset : natural := 0; -- Address of first slave on the MM bus
- g_width_w : positive := 4; -- Address width of each slave memory in the MM bus array.
- g_rd_latency : natural := 1; -- Read latency of the slaves
- g_waitrequest : boolean := false; -- When TRUE model waitrequest by MM slaves, else fixed '0'
+ -- Number of slave memory interfaces on the MM bus array.
+ g_nof_slaves : positive := 1;
+ -- Address of first slave on the MM bus
+ g_base_offset : natural := 0;
+ -- Address width of each slave memory in the MM bus array.
+ g_width_w : positive := 4;
+ -- Read latency of the slaves
+ g_rd_latency : natural := 1;
+ -- When TRUE model waitrequest by MM slaves, else fixed '0'
+ g_waitrequest : boolean := false;
g_pipeline_mosi : boolean := false;
g_pipeline_miso_rdval : boolean := false;
g_pipeline_miso_wait : boolean := false
@@ -72,13 +77,19 @@ end tb_mm_bus;
architecture tb of tb_mm_bus is
constant mm_clk_period : time := 10 ns;
- constant c_repeat : natural := 10; -- sel_a_b(g_waitrequest, 10, 2); -- repeat 2 for deterministic, more often for random
+ -- sel_a_b(g_waitrequest, 10, 2); -- repeat 2 for deterministic, more often for random
+ constant c_repeat : natural := 10;
constant c_slave_span : natural := 2**g_width_w;
- constant c_base_arr : t_nat_natural_arr := array_init(g_base_offset, g_nof_slaves, c_slave_span); -- Address base per slave
- constant c_width_arr : t_nat_natural_arr := array_init( g_width_w, g_nof_slaves); -- Address width per slave
- constant c_rd_latency_arr : t_nat_natural_arr := array_init( g_rd_latency, g_nof_slaves); -- Read latency per slave
- constant c_slave_enable_arr: t_nat_boolean_arr := array_init( true, g_nof_slaves); -- TRUE for connected slaves
- constant c_waitrequest_arr : t_nat_boolean_arr := array_init(g_waitrequest, g_nof_slaves); -- Flow control per slave
+ -- Address base per slave
+ constant c_base_arr : t_nat_natural_arr := array_init(g_base_offset, g_nof_slaves, c_slave_span);
+ -- Address width per slave
+ constant c_width_arr : t_nat_natural_arr := array_init( g_width_w, g_nof_slaves);
+ -- Read latency per slave
+ constant c_rd_latency_arr : t_nat_natural_arr := array_init( g_rd_latency, g_nof_slaves);
+ -- TRUE for connected slaves
+ constant c_slave_enable_arr: t_nat_boolean_arr := array_init( true, g_nof_slaves);
+ -- Flow control per slave
+ constant c_waitrequest_arr : t_nat_boolean_arr := array_init(g_waitrequest, g_nof_slaves);
constant c_bus_pipelining : boolean := g_pipeline_mosi or g_pipeline_miso_rdval or g_pipeline_miso_wait;
constant c_pipeline_mosi : natural := sel_a_b(g_pipeline_mosi, 1, 0);
@@ -119,7 +130,8 @@ begin
-- Write stimuli and readback to verify
-----------------------------------------------------------------------------
p_stimuli : process
- variable v_wrdata : integer; -- write data
+ -- write data
+ variable v_wrdata : integer;
begin
tb_end <= '0';
master_mosi <= c_mem_mosi_rst;
@@ -154,7 +166,8 @@ begin
proc_common_wait_some_cycles(mm_clk, 10);
-- Verify that test has indeed ran
- wait for 1 ns; -- wait 1 ns to ensure that assert report appears at end of transcript log
+ -- wait 1 ns to ensure that assert report appears at end of transcript log
+ wait for 1 ns;
assert cnt_rdval = cnt_rd and cnt_rdval > 0 report "Wrong number of rdval" severity ERROR;
tb_end <= '1';
@@ -168,8 +181,10 @@ begin
-- c_read_latency and even variable (in case of g_waitrequest = TRUE). The disadvantage is that the MM
-- slave must support rdval, but that is ensured by mm_slave_enable.
p_verify : process
- variable v_expdata : integer := 0; -- expected data
- variable v_rddata : integer; -- read data
+ -- expected data
+ variable v_expdata : integer := 0;
+ -- read data
+ variable v_rddata : integer;
begin
wait until rising_edge(mm_clk);
if master_miso.rdval = '1' then
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_file.vhd b/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
index ce5bfc5ca2a82cfeda78388176b3b3040c6965e9..4df2395eaf4c80235cedb0ddba5a2bd253e17e35 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
@@ -55,23 +55,31 @@ entity tb_mm_file is
generic (
g_tb_index : natural := 0;
g_mm_nof_accesses : natural := 100;
- g_mm_timeout : time := 0 ns; -- 100 ns; -- default 0 ns for full speed MM, use > 0 to define number of mm_clk without MM access after which the MM file IO is paused
- g_mm_pause : time := 1000 ns; -- defines the time for which MM file IO is paused to reduce the file IO rate when the MM slave is idle
- g_timeout_gap : integer := -1; -- 4; -- no gap when < 0, else force MM access gap after g_timeout_gap wr or rd strobes
- g_cross_clock_domain : boolean := false -- TRUE
+ -- 100 ns; -- default 0 ns for full speed MM, use > 0 to define number of mm_clk without MM access after which the MM file IO is paused
+ g_mm_timeout : time := 0 ns;
+ -- defines the time for which MM file IO is paused to reduce the file IO rate when the MM slave is idle
+ g_mm_pause : time := 1000 ns;
+ -- 4; -- no gap when < 0, else force MM access gap after g_timeout_gap wr or rd strobes
+ g_timeout_gap : integer := -1;
+ -- TRUE
+ g_cross_clock_domain : boolean := false
);
end tb_mm_file;
architecture tb of tb_mm_file is
- constant c_mm_clk_period : time := c_mmf_mm_clk_period; -- = 100 ps;
+ -- = 100 ps;
+ constant c_mm_clk_period : time := c_mmf_mm_clk_period;
constant c_mm_nof_dat : natural := smallest(c_mem_reg_init_w / c_32, g_mm_nof_accesses);
constant c_mm_rd_latency : natural := 2;
- constant c_cross_nof_mm_clk : natural := sel_a_b(g_cross_clock_domain, 100, 0); -- > 2*24 see common_reg_cross_domain, factor 2 for W/R
+ -- > 2*24 see common_reg_cross_domain, factor 2 for W/R
+ constant c_cross_nof_mm_clk : natural := sel_a_b(g_cross_clock_domain, 100, 0);
-- Determine node mm_file prefix based on --unb --gn (similar as done in mmf_unb_file_prefix())
- constant c_unb_nr : natural := 3; -- unb
- constant c_pn_nr : natural := 1; -- gn = 0:7
+ -- unb
+ constant c_unb_nr : natural := 3;
+ -- gn = 0:7
+ constant c_pn_nr : natural := 1;
constant c_node_type : string(1 to 2) := sel_a_b(c_pn_nr < 4, "FN", "BN");
constant c_node_nr : natural := sel_a_b(c_node_type = "BN", c_pn_nr - 4, c_pn_nr);
@@ -95,7 +103,8 @@ architecture tb of tb_mm_file is
signal mm_rst : std_logic;
signal get_now : std_logic := '0';
- signal rd_now : string(1 to 16); -- sufficient to fit TIME NOW in ns as a string
+ -- sufficient to fit TIME NOW in ns as a string
+ signal rd_now : string(1 to 16);
signal mm_mosi : t_mem_mosi;
signal mm_miso : t_mem_miso;
@@ -107,7 +116,8 @@ architecture tb of tb_mm_file is
signal in_new : std_logic := '1';
signal in_reg : std_logic_vector(c_32 * c_mem_reg.nof_dat - 1 downto 0);
signal out_reg : std_logic_vector(c_32 * c_mem_reg.nof_dat - 1 downto 0);
- signal out_new : std_logic; -- Pulses '1' when new data has been written.
+ -- Pulses '1' when new data has been written.
+ signal out_new : std_logic;
signal out_reg_arr : t_slv_32_arr(c_mem_reg.nof_dat - 1 downto 0);
begin
@@ -168,7 +178,8 @@ begin
u_mm_file : entity work.mm_file
generic map(
g_file_prefix => c_reg_r_w_dc_file_pathname,
- g_mm_rd_latency => c_mem_reg.latency, -- the mm_file g_mm_rd_latency must be >= the MM slave read latency
+ -- the mm_file g_mm_rd_latency must be >= the MM slave read latency
+ g_mm_rd_latency => c_mem_reg.latency,
g_mm_timeout => g_mm_timeout,
g_mm_pause => g_mm_pause
)
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd b/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
index f939920bf73176a317cdbbce67781f25a51d159c..d35c593474ee21a3b2c3c56ed1784f0fd414f809 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
@@ -52,10 +52,14 @@ use common_lib.tb_common_mem_pkg.all;
entity tb_mm_master_mux is
generic (
- g_nof_masters : positive := 2; -- Number of master memory interfaces on the MM bus array.
- g_base_arr : t_nat_natural_arr := (0, 256); -- Address base per slave port of mm_bus
- g_width_arr : t_nat_natural_arr := (4, 8); -- Address width per slave port of mm_bus
- g_waitrequest : boolean := true; -- When TRUE model waitrequest by the MM RAM slave, else fixed '0'
+ -- Number of master memory interfaces on the MM bus array.
+ g_nof_masters : positive := 2;
+ -- Address base per slave port of mm_bus
+ g_base_arr : t_nat_natural_arr := (0, 256);
+ -- Address width per slave port of mm_bus
+ g_width_arr : t_nat_natural_arr := (4, 8);
+ -- When TRUE model waitrequest by the MM RAM slave, else fixed '0'
+ g_waitrequest : boolean := true;
g_pipeline_bus_mosi : boolean := false;
g_pipeline_bus_miso_rdval : boolean := false;
g_pipeline_bus_miso_wait : boolean := false
@@ -69,7 +73,8 @@ end tb_mm_master_mux;
architecture tb of tb_mm_master_mux is
constant mm_clk_period : time := 10 ns;
- constant c_repeat : natural := sel_a_b(g_waitrequest, 10, 2); -- repeat 2 for deterministic, more often for random
+ -- repeat 2 for deterministic, more often for random
+ constant c_repeat : natural := sel_a_b(g_waitrequest, 10, 2);
constant c_bus_pipeline_mosi : natural := sel_a_b(g_pipeline_bus_mosi, 1, 0);
constant c_bus_pipeline_miso_rdval : natural := sel_a_b(g_pipeline_bus_miso_rdval, 1, 0);
constant c_bus_pipeline_miso_wait : natural := sel_a_b(g_pipeline_bus_miso_wait, 1, 0);
@@ -106,9 +111,12 @@ begin
p_stimuli : process
variable v_base : natural;
variable v_span : natural;
- variable v_wrdata : integer; -- write data
- variable v_rddata : integer; -- read data
- variable v_expdata : integer; -- expected data
+ -- write data
+ variable v_wrdata : integer;
+ -- read data
+ variable v_rddata : integer;
+ -- expected data
+ variable v_expdata : integer;
begin
tb_end <= '0';
stimuli_mosi <= c_mem_mosi_rst;
diff --git a/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd b/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd
index 508a66f587924d84d07affc77fb3c517ceeb9e96..2413fe129aef1670c1a051c4ccacb865787d79bc 100644
--- a/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd
@@ -33,7 +33,8 @@ entity tb_tb_mm_bus is
end tb_tb_mm_bus;
architecture tb of tb_tb_mm_bus is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Usage:
-- > as 4
diff --git a/libraries/base/mm/tb/vhdl/tb_tb_mm_file.vhd b/libraries/base/mm/tb/vhdl/tb_tb_mm_file.vhd
index 469bf972122fecf110462309c1dd6d365b031015..946a340798046355d2df676c4515e48dd891d91f 100644
--- a/libraries/base/mm/tb/vhdl/tb_tb_mm_file.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_tb_mm_file.vhd
@@ -33,7 +33,8 @@ entity tb_tb_mm_file is
end tb_tb_mm_file;
architecture tb of tb_tb_mm_file is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_tb_index : NATURAL := 0;
-- g_mm_nof_accesses : NATURAL := 100;
diff --git a/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd b/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd
index fb6d289c65dc7db3a0353e3baa8f643b80c73dde..c2d4fb17ba10f9cdda507ec9f278407435c473b2 100644
--- a/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd
@@ -33,7 +33,8 @@ entity tb_tb_mm_master_mux is
end tb_tb_mm_master_mux;
architecture tb of tb_tb_mm_master_mux is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Usage:
-- > as 4
diff --git a/libraries/base/reorder/src/vhdl/reorder_col.vhd b/libraries/base/reorder/src/vhdl/reorder_col.vhd
index b169627075b5f4e70dbdc7e1c01fa6b25199d302..8fcd950d7cde359179aca161adc156205626cc61 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col.vhd
@@ -62,9 +62,11 @@ entity reorder_col is
-- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2 which
-- is fine if no flow control is needed.
g_use_output_rl_adapter : boolean := false;
- g_dsp_data_w : natural := 18; -- complex data width, = c_data_w / 2
+ -- complex data width, = c_data_w / 2
+ g_dsp_data_w : natural := 18;
g_nof_ch_in : natural := 512;
- g_nof_ch_sel : natural := 252; -- g_nof_ch_sel < g_nof_ch_in
+ -- g_nof_ch_sel < g_nof_ch_in
+ g_nof_ch_sel : natural := 252;
g_select_file_name : string := "UNUSED";
g_use_complex : boolean := true
);
@@ -75,14 +77,18 @@ entity reorder_col is
dp_clk : in std_logic;
-- Memory Mapped
- ram_ss_ss_mosi : in t_mem_mosi; -- channel select control
+ -- channel select control
+ ram_ss_ss_mosi : in t_mem_mosi;
ram_ss_ss_miso : out t_mem_miso;
-- Streaming
- input_sosi : in t_dp_sosi; -- complex input
- input_siso : out t_dp_siso; -- complex input
+ -- complex input
+ input_sosi : in t_dp_sosi;
+ -- complex input
+ input_siso : out t_dp_siso;
- output_sosi : out t_dp_sosi; -- selected complex output with flow control
+ -- selected complex output with flow control
+ output_sosi : out t_dp_sosi;
output_siso : in t_dp_siso := c_dp_siso_rdy
);
end reorder_col;
@@ -93,7 +99,8 @@ architecture str of reorder_col is
adr_w => ceil_log2(g_nof_ch_in),
dat_w => c_data_w,
nof_dat => g_nof_ch_in,
- init_sl => '0'); -- ST side : stat_mosi
+ -- ST side : stat_mosi
+ init_sl => '0');
constant c_select_buf : t_c_mem := (latency => 1,
adr_w => ceil_log2(g_nof_ch_sel),
@@ -101,10 +108,13 @@ architecture str of reorder_col is
nof_dat => g_nof_ch_sel,
init_sl => '0');
- constant c_data_nof_pages : natural := 2; -- fixed dual page SS
- constant c_info_nof_pages : natural := 2; -- fixed, fits the dual page block latency and logic latency of the SS
+ -- fixed dual page SS
+ constant c_data_nof_pages : natural := 2;
+ -- fixed, fits the dual page block latency and logic latency of the SS
+ constant c_info_nof_pages : natural := 2;
- constant c_retrieve_lat : natural := c_select_buf.latency + c_store_buf.latency; -- = 2
+ -- = 2
+ constant c_retrieve_lat : natural := c_select_buf.latency + c_store_buf.latency;
-- force output ready latency (RL) from 2 -> 1 or leave it at 2
constant c_output_rl : natural := sel_a_b(g_use_output_rl_adapter, 1, c_retrieve_lat);
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
index 2aac2334fc124334a0e7c429ba67e889522bf65d..9603d0bb52811cc7eb51d4ab3534953cc51a2bc9 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
@@ -61,7 +61,8 @@ use dp_lib.dp_stream_pkg.all;
entity reorder_col_select is
generic (
- g_dsp_data_w : natural := 18; -- complex data width, = c_data_w / 2
+ -- complex data width, = c_data_w / 2
+ g_dsp_data_w : natural := 18;
g_nof_ch_in : natural := 1024;
g_nof_ch_sel : natural := 12;
g_use_complex : boolean := true
@@ -81,8 +82,10 @@ entity reorder_col_select is
output_nof_ch_sel : out natural;
-- Memory Mapped
- col_select_mosi : in t_mem_mosi; -- channel select control
- col_select_miso : out t_mem_miso := c_mem_miso_rst; -- only used for waitrequest
+ -- channel select control
+ col_select_mosi : in t_mem_mosi;
+ -- only used for waitrequest
+ col_select_miso : out t_mem_miso := c_mem_miso_rst;
-- Streaming
input_sosi : in t_dp_sosi;
@@ -96,13 +99,18 @@ architecture str of reorder_col_select is
adr_w => ceil_log2(g_nof_ch_in),
dat_w => c_data_w,
nof_dat => g_nof_ch_in,
- init_sl => '0'); -- ST side : stat_mosi
+ -- ST side : stat_mosi
+ init_sl => '0');
- constant c_data_nof_pages : natural := 2; -- fixed dual page SS
- constant c_info_nof_pages : natural := 2; -- fixed, fits the dual page block latency and logic latency of the SS
- constant c_retrieve_lat : natural := c_store_buf.latency + 1; -- = 2 rd_latency from waitrequest + store_buf latency
+ -- fixed dual page SS
+ constant c_data_nof_pages : natural := 2;
+ -- fixed, fits the dual page block latency and logic latency of the SS
+ constant c_info_nof_pages : natural := 2;
+ -- = 2 rd_latency from waitrequest + store_buf latency
+ constant c_retrieve_lat : natural := c_store_buf.latency + 1;
- signal input_sosi_reg : t_dp_sosi := c_dp_sosi_rst; -- register input_sosi to ease timing closure for reorder_busy
+ -- register input_sosi to ease timing closure for reorder_busy
+ signal input_sosi_reg : t_dp_sosi := c_dp_sosi_rst;
signal info_sop_wr_en : std_logic_vector(c_info_nof_pages - 1 downto 0);
signal info_eop_wr_en : std_logic_vector(c_info_nof_pages - 1 downto 0);
@@ -187,7 +195,8 @@ begin
u_retrieve_en : entity common_lib.common_switch
generic map (
g_rst_level => '0',
- g_priority_lo => false, -- store_done has priority over nxt_retrieve_done when they occur simultaneously
+ -- store_done has priority over nxt_retrieve_done when they occur simultaneously
+ g_priority_lo => false,
g_or_high => true,
g_and_low => false
)
@@ -206,7 +215,8 @@ begin
nxt_reorder_busy <= store_busy or retrieve_busy;
- i_reorder_busy <= input_sosi.valid or nxt_reorder_busy or reorder_busy_reg; -- using input_sosi.valid or sop is equivalent here
+ -- using input_sosi.valid or sop is equivalent here
+ i_reorder_busy <= input_sosi.valid or nxt_reorder_busy or reorder_busy_reg;
-- Registers
p_reg : process (dp_clk, dp_rst)
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd b/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
index ce8a2c0bad5a07f1e71dca14bfe1e825c4aa0558..2284d59851758daabfa7fa5a4ef866ad1575c21b 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
@@ -40,9 +40,11 @@ use dp_lib.dp_stream_pkg.all;
entity reorder_col_wide is
generic (
g_wb_factor : natural := 4;
- g_dsp_data_w : natural := 18; -- complex data width, = c_data_w / 2
+ -- complex data width, = c_data_w / 2
+ g_dsp_data_w : natural := 18;
g_nof_ch_in : natural := 256;
- g_nof_ch_sel : natural := 192; -- g_nof_ch_sel < g_nof_ch_in
+ -- g_nof_ch_sel < g_nof_ch_in
+ g_nof_ch_sel : natural := 192;
g_select_file_prefix : string := "UNUSED";
g_use_complex : boolean := true
);
@@ -53,14 +55,16 @@ entity reorder_col_wide is
dp_clk : in std_logic;
-- Memory Mapped
- ram_ss_ss_wide_mosi : in t_mem_mosi; -- channel select control
+ -- channel select control
+ ram_ss_ss_wide_mosi : in t_mem_mosi;
ram_ss_ss_wide_miso : out t_mem_miso;
-- Streaming
input_sosi_arr : in t_dp_sosi_arr(g_wb_factor - 1 downto 0);
input_siso_arr : out t_dp_siso_arr(g_wb_factor - 1 downto 0) := (others => c_dp_siso_rdy);
- output_sosi_arr : out t_dp_sosi_arr(g_wb_factor - 1 downto 0); -- selected output
+ -- selected output
+ output_sosi_arr : out t_dp_sosi_arr(g_wb_factor - 1 downto 0);
output_siso_arr : in t_dp_siso_arr(g_wb_factor - 1 downto 0) := (others => c_dp_siso_rdy)
);
end reorder_col_wide;
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd b/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
index 41916d90e0a366dc27f7eeb1e10aee86d6d85974..a6854d4574404656f449fe3fd4057069da23e3e7 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
@@ -38,9 +38,11 @@ use dp_lib.dp_stream_pkg.all;
entity reorder_col_wide_select is
generic (
g_nof_inputs : natural := 6;
- g_dsp_data_w : natural := 18; -- complex data width, = c_data_w / 2
+ -- complex data width, = c_data_w / 2
+ g_dsp_data_w : natural := 18;
g_nof_ch_in : natural := 1024;
- g_nof_ch_sel : natural := 12; -- g_nof_ch_sel < g_nof_ch_in
+ -- g_nof_ch_sel < g_nof_ch_in
+ g_nof_ch_sel : natural := 12;
g_use_complex : boolean := true
);
port (
@@ -52,8 +54,10 @@ entity reorder_col_wide_select is
nof_ch_sel : in natural range 0 to g_nof_ch_sel := g_nof_ch_sel;
-- Memory Mapped
- col_select_mosi : in t_mem_mosi; -- channel select control
- col_select_miso : out t_mem_miso; -- only used for waitrequest
+ -- channel select control
+ col_select_mosi : in t_mem_mosi;
+ -- only used for waitrequest
+ col_select_miso : out t_mem_miso;
-- Streaming
input_sosi_arr : in t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
@@ -64,7 +68,8 @@ end reorder_col_wide_select;
architecture str of reorder_col_wide_select is
signal col_select_miso_arr : t_mem_miso_arr(g_nof_inputs - 1 downto 0);
begin
- col_select_miso <= col_select_miso_arr(0); -- All inputs have the same mosi/miso
+ -- All inputs have the same mosi/miso
+ col_select_miso <= col_select_miso_arr(0);
-- Instantiate reorder_col_select for multiple streams in parallel, to
-- reorder blocks in each stream in time. The same reordering is applied
diff --git a/libraries/base/reorder/src/vhdl/reorder_matrix.vhd b/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
index 49a71a802576d591ae915689b6163f099409595e..bbfdf09ff0722851450b3ca277495980bb93f9db 100644
--- a/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
@@ -58,12 +58,16 @@ entity reorder_matrix is
g_nof_inputs : natural := 24;
g_nof_internals : natural := 64;
g_nof_outputs : natural := 64;
- g_dsp_data_w : natural := 8; -- complex data width, = c_data_w / 2
+ -- complex data width, = c_data_w / 2
+ g_dsp_data_w : natural := 8;
g_frame_size_in : natural := 64;
g_frame_size_out : natural := 128;
- g_reorder_in_file_name : string := "UNUSED"; -- path_to_file.hex
- g_ss_wide_file_prefix : string := "UNUSED"; -- path_to_file
- g_reorder_out_file_name : string := "UNUSED" -- path_to_file.hex
+ -- path_to_file.hex
+ g_reorder_in_file_name : string := "UNUSED";
+ -- path_to_file
+ g_ss_wide_file_prefix : string := "UNUSED";
+ -- path_to_file.hex
+ g_reorder_out_file_name : string := "UNUSED"
);
port (
mm_rst : in std_logic;
diff --git a/libraries/base/reorder/src/vhdl/reorder_pkg.vhd b/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
index caad085b16c31d06a5e57bd1333a5279dc2f82a4..ffca6cf597b489831810f9768b0e5413333b0cb4 100644
--- a/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
@@ -27,12 +27,18 @@ use common_lib.common_mem_pkg.all;
package reorder_pkg is
type t_reorder_seq is record
- wr_chunksize : positive; -- := 64;
- rd_chunksize : positive; -- := 16;
- rd_nof_chunks : positive; -- := 4;
- rd_interval : positive; -- := 1;
- gapsize : natural; -- := 0;
- nof_blocks : positive; -- := 5;
+ -- := 64;
+ wr_chunksize : positive;
+ -- := 16;
+ rd_chunksize : positive;
+ -- := 4;
+ rd_nof_chunks : positive;
+ -- := 1;
+ rd_interval : positive;
+ -- := 0;
+ gapsize : natural;
+ -- := 5;
+ nof_blocks : positive;
end record;
constant c_reorder_seq : t_reorder_seq := (64, 16, 4, 1, 0, 5);
diff --git a/libraries/base/reorder/src/vhdl/reorder_retreive.vhd b/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
index b8b15f6837762a89bd8ef66349f42a5ab276c958..c678ee231c49423d6cd2ac5a36e053d523a9829b 100644
--- a/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
@@ -45,7 +45,8 @@ use dp_lib.dp_stream_pkg.all;
entity reorder_retrieve is
generic (
- g_dsp_data_w : natural; -- complex data width, = c_data_w / 2
+ -- complex data width, = c_data_w / 2
+ g_dsp_data_w : natural;
g_nof_ch_in : natural;
g_nof_ch_sel : natural
);
@@ -73,7 +74,8 @@ end reorder_retrieve;
architecture rtl of reorder_retrieve is
constant c_data_w : natural := c_nof_complex * g_dsp_data_w;
- constant c_retrieve_lat : natural := 2; -- fixed 1 for select buf read + 1 for store buf read
+ -- fixed 1 for select buf read + 1 for store buf read
+ constant c_retrieve_lat : natural := 2;
signal ch_cnt : integer range 0 to g_nof_ch_sel - 1;
signal nxt_ch_cnt : integer;
@@ -148,7 +150,8 @@ begin
retrieve_eop_dly(0) <= '1' when retrieve_ready = '1' and ch_cnt = g_nof_ch_sel - 1 else '0';
-- First read store buf address from select buf when the output is ready
- select_mosi.rd <= '1'; -- no need to use retrieve_ready here, keep rd active to ease timing closure
+ -- no need to use retrieve_ready here, keep rd active to ease timing closure
+ select_mosi.rd <= '1';
select_mosi.address <= TO_MEM_ADDRESS(ch_cnt);
-- Then use the read select address to read the data from the store buf
diff --git a/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd b/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd
index db85b9f4822be1737f3804342538840138dcbb62..c3a9aa5357268cb6adfcff8064622353b72a24a4 100644
--- a/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd
@@ -48,18 +48,25 @@ entity reorder_rewire_reg is
generic (
g_nof_streams : positive := 8;
g_sel_in_w : positive := 3;
- g_cross_clock_domain : boolean := true -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
sel_reg : out std_logic_vector
@@ -67,13 +74,16 @@ entity reorder_rewire_reg is
end reorder_rewire_reg;
architecture str of reorder_rewire_reg is
- constant c_nof_required_bits : natural := g_nof_streams * g_sel_in_w; -- 24
- constant c_nof_required_registers : natural := 1; -- c_nof_required_bits MOD c_word_w;
+ -- 24
+ constant c_nof_required_bits : natural := g_nof_streams * g_sel_in_w;
+ -- c_nof_required_bits MOD c_word_w;
+ constant c_nof_required_registers : natural := 1;
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_required_registers),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_nof_required_registers,
init_sl => '0');
@@ -89,7 +99,8 @@ begin
g_in_new_latency => 1,
g_readback => true,
g_reg => c_mm_reg,
- g_init_reg => RESIZE_UVEC(c_reg_init, c_mem_reg_init_w) -- RESIZE_UVEC(TO_UVEC(1, c_word_w), c_mem_reg_init_w)
+ -- RESIZE_UVEC(TO_UVEC(1, c_word_w), c_mem_reg_init_w)
+ g_init_reg => RESIZE_UVEC(c_reg_init, c_mem_reg_init_w)
)
port map (
-- Clocks and reset
@@ -106,8 +117,10 @@ begin
reg_wr_arr => OPEN,
reg_rd_arr => OPEN,
in_new => OPEN,
- in_reg => sel_in_reg, -- read
- out_reg => sel_in_reg, -- write
+ -- read
+ in_reg => sel_in_reg,
+ -- write
+ out_reg => sel_in_reg,
out_new => open
);
diff --git a/libraries/base/reorder/src/vhdl/reorder_row.vhd b/libraries/base/reorder/src/vhdl/reorder_row.vhd
index b02b86889fb79b254037a901895f26f6a6c77f0f..3c182375ff0ec4deda21e00949849eb11557d2ab 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row.vhd
@@ -45,10 +45,14 @@ entity reorder_row is
g_nof_inputs : natural := 8;
g_nof_outputs : natural := 16;
g_use_complex : boolean := true;
- g_ram_init_file : string := "../../../src/data/select_buf"; -- or "UNUSED"
- g_pipeline_in : natural := 1; -- pipeline in_data
- g_pipeline_in_m : natural := 1; -- pipeline in_data for M-fold fan out
- g_pipeline_out : natural := 1 -- pipeline out_data
+ -- or "UNUSED"
+ g_ram_init_file : string := "../../../src/data/select_buf";
+ -- pipeline in_data
+ g_pipeline_in : natural := 1;
+ -- pipeline in_data for M-fold fan out
+ g_pipeline_in_m : natural := 1;
+ -- pipeline out_data
+ g_pipeline_out : natural := 1
);
port (
mm_rst : in std_logic;
@@ -68,7 +72,8 @@ entity reorder_row is
end reorder_row;
architecture str of reorder_row is
- constant c_sel_buf_read_lat : natural := 1; -- Latency introduced by the counter.
+ -- Latency introduced by the counter.
+ constant c_sel_buf_read_lat : natural := 1;
constant c_tot_pipeline : natural := g_pipeline_in + g_pipeline_in_m + g_pipeline_out + c_sel_buf_read_lat;
constant c_select_w : natural := ceil_log2(g_nof_inputs);
diff --git a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
index 429639223a48daf2f9a0750c47ebae03e799f697..2c61d380f1258e6547882461062e79c08eceaab4 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
@@ -40,13 +40,17 @@ use dp_lib.dp_stream_pkg.all;
entity reorder_row_select is
generic (
- g_dsp_data_w : natural := 16; -- complex data width, = c_data_w / 2
+ -- complex data width, = c_data_w / 2
+ g_dsp_data_w : natural := 16;
g_nof_inputs : natural := 8;
g_nof_outputs : natural := 16;
g_use_complex : boolean := true;
- g_pipeline_in : natural := 1; -- pipeline in_data
- g_pipeline_in_m : natural := 1; -- pipeline in_data for M-fold fan out
- g_pipeline_out : natural := 1 -- pipeline out_data
+ -- pipeline in_data
+ g_pipeline_in : natural := 1;
+ -- pipeline in_data for M-fold fan out
+ g_pipeline_in_m : natural := 1;
+ -- pipeline out_data
+ g_pipeline_out : natural := 1
);
port (
dp_rst : in std_logic;
diff --git a/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd b/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
index e23186e4399e343bc42e0aa41e36adc56f958412..115dcf166362904ed3ac89c6102dfac272f445e2 100644
--- a/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
@@ -151,12 +151,16 @@ use work.reorder_pkg.all;
entity reorder_sequencer is
generic (
g_reorder_seq : t_reorder_seq := c_reorder_seq;
- g_data_w_ratio : positive := 1 -- (256/256) Ratio between datawidth of the memory controller and SOSI domain
- ); -- Used to determine the width of counters.
+ -- (256/256) Ratio between datawidth of the memory controller and SOSI domain
+ g_data_w_ratio : positive := 1
+ -- Used to determine the width of counters.
+ );
port (
-- Clocks and reset
- dp_rst : in std_logic; -- reset synchronous with st_clk
- dp_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with st_clk
+ dp_rst : in std_logic;
+ -- other clock domain clock
+ dp_clk : in std_logic;
en_evt : out std_logic;
wr_not_rd : out std_logic;
@@ -189,12 +193,15 @@ architecture rtl of reorder_sequencer is
rd_block_offset : natural;
rd_chunks_offset : natural;
wr_block_offset : natural;
- switch_cnt : natural range 0 to g_reorder_seq.rd_nof_chunks; -- Counter that counts the write and read accesses to determine the switch between read and write phase.
- page_cnt : natural range 0 to g_reorder_seq.nof_blocks; -- Counter that counts the number of write accesses to determine the page-swap.
+ -- Counter that counts the write and read accesses to determine the switch between read and write phase.
+ switch_cnt : natural range 0 to g_reorder_seq.rd_nof_chunks;
+ -- Counter that counts the number of write accesses to determine the page-swap.
+ page_cnt : natural range 0 to g_reorder_seq.nof_blocks;
first_write : std_logic;
start_addr : natural range 0 to c_mem_size-1;
burstsize : natural range 0 to largest(c_wr_chunksize, c_rd_chunksize);
- state : state_type; -- The state machine.
+ -- The state machine.
+ state : state_type;
end record;
signal r, rin : reg_type;
diff --git a/libraries/base/reorder/src/vhdl/reorder_store.vhd b/libraries/base/reorder/src/vhdl/reorder_store.vhd
index 75207311ae588a43fdfd2874d4220c8ba0be4b5c..e5f5b2a22b443c4f1a85ea7802c26a46af455705 100644
--- a/libraries/base/reorder/src/vhdl/reorder_store.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_store.vhd
@@ -51,9 +51,12 @@ use dp_lib.dp_stream_pkg.all;
entity reorder_store is
generic (
- g_dsp_data_w : natural; -- complex data width, = c_data_w / 2
- g_nof_ch_in : natural; -- = nof valid per input block (sop to eop)
- g_use_complex : boolean := true -- use input_sosi.re, im when true, else input_sosi.data
+ -- complex data width, = c_data_w / 2
+ g_dsp_data_w : natural;
+ -- = nof valid per input block (sop to eop)
+ g_nof_ch_in : natural;
+ -- use input_sosi.re, im when true, else input_sosi.data
+ g_use_complex : boolean := true
);
port (
rst : in std_logic;
diff --git a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
index e62740d57c941a0665ee8106efb5ff0090f1526c..5c5f1704e52d33e74549ddc58a652923632aa754 100644
--- a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
@@ -85,21 +85,26 @@ use work.reorder_pkg.all;
entity reorder_transpose is
generic(
- g_pipeline_input : natural := 0; -- choose 0 to have orignal version -r < 19416, choose 1 does not seem to help timing closure (erko)
- g_pipeline_output: natural := 0; -- choose 0 to have orignal version -r < 19416, choose 1 does not seem to help timing closure (erko)
+ -- choose 0 to have orignal version -r < 19416, choose 1 does not seem to help timing closure (erko)
+ g_pipeline_input : natural := 0;
+ -- choose 0 to have orignal version -r < 19416, choose 1 does not seem to help timing closure (erko)
+ g_pipeline_output: natural := 0;
g_nof_streams : natural := 4;
g_in_dat_w : natural := 8;
g_frame_size_in : natural := 256;
g_frame_size_out : natural := 256;
g_use_complex : boolean := true;
- g_mem_dat_w : natural := 256; -- The data width to the attached memory.
+ -- The data width to the attached memory.
+ g_mem_dat_w : natural := 256;
g_ena_pre_transp : boolean := true;
g_reorder_seq : t_reorder_seq := c_reorder_seq;
g_select_file : string := "UNUSED"
);
port (
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
dp_clk : in std_logic;
dp_rst : in std_logic;
@@ -111,7 +116,8 @@ entity reorder_transpose is
src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-- Memory Mapped
- ram_ss_ss_transp_mosi : in t_mem_mosi; -- channel select control
+ -- channel select control
+ ram_ss_ss_transp_mosi : in t_mem_mosi;
ram_ss_ss_transp_miso : out t_mem_miso;
reg_dp_sync_checker_mosi : in t_mem_mosi;
reg_dp_sync_checker_miso : out t_mem_miso;
@@ -138,7 +144,8 @@ architecture str of reorder_transpose is
constant c_total_data_w : natural := g_nof_streams * g_in_dat_w;
constant c_complex_data_w : natural := c_total_data_w * c_nof_complex;
constant c_data_w : natural := sel_a_b(g_use_complex, c_complex_data_w, c_total_data_w);
- constant c_data_w_pre : natural := sel_a_b(g_use_complex, c_total_data_w, c_total_data_w / 2); -- Datawidth for pre-transpose defines Re or Im part.
+ -- Datawidth for pre-transpose defines Re or Im part.
+ constant c_data_w_pre : natural := sel_a_b(g_use_complex, c_total_data_w, c_total_data_w / 2);
constant c_sdata_w : natural := c_data_w / g_nof_streams;
constant c_nof_ch_in : natural := g_frame_size_in * g_reorder_seq.rd_chunksize;
@@ -323,7 +330,8 @@ begin
-- Streaming
input_sosi => ss_in_sosi,
- input_siso => OPEN, -- Don't allow backpressure.
+ -- Don't allow backpressure.
+ input_siso => OPEN,
output_sosi => i_to_mem_src_out,
output_siso => to_mem_src_in
@@ -336,9 +344,11 @@ begin
end generate;
-- Map original dvr interface signals to t_mem_ctlr_mosi/miso
- dvr_done <= dvr_miso.done; -- Requested wr or rd sequence is done
+ -- Requested wr or rd sequence is done
+ dvr_done <= dvr_miso.done;
dvr_mosi.burstbegin <= dvr_en;
- dvr_mosi.wr <= dvr_wr_not_rd; -- No need to use dvr_mosi.rd
+ -- No need to use dvr_mosi.rd
+ dvr_mosi.wr <= dvr_wr_not_rd;
dvr_mosi.address <= RESIZE_MEM_CTLR_ADDRESS(dvr_start_address);
dvr_mosi.burstsize <= RESIZE_MEM_CTLR_BURSTSIZE(dvr_nof_data);
dvr_mosi.flush <= dvr_wr_flush_en;
@@ -367,11 +377,13 @@ begin
---------------------------------------------------------------
u_sync_bsn_fifo : entity common_lib.common_fifo_sc
generic map (
- g_use_lut => true, -- Make this FIFO in logic, since it's only 2 words deep.
+ -- Make this FIFO in logic, since it's only 2 words deep.
+ g_use_lut => true,
g_reset => false,
g_init => false,
g_dat_w => c_dp_stream_bsn_w,
- g_nof_words => 4 -- 2 sync intervals should be sufficient, choose 4 to be safe (erko)
+ -- 2 sync intervals should be sufficient, choose 4 to be safe (erko)
+ g_nof_words => 4
)
port map (
rst => dp_rst,
@@ -485,7 +497,8 @@ begin
u_dp_pipeline_arr : entity dp_lib.dp_pipeline_arr
generic map (
g_nof_streams => g_nof_streams,
- g_pipeline => g_pipeline_output -- 0 for wires, > 0 for registers,
+ -- 0 for wires, > 0 for registers,
+ g_pipeline => g_pipeline_output
)
port map (
rst => dp_rst,
diff --git a/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd b/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd
index ee1bdadda1f566d24992d8aa709b924fa878c00a..1b0325146c453d083da17d9cf6bf4ddba133f319 100644
--- a/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd
@@ -55,10 +55,14 @@ entity tb_mmf_reorder_row is
g_nof_outputs : natural := 16;
g_dsp_data_w : natural := 16;
g_frame_size : natural := 16;
- g_ram_init_file : string := "../../../src/data/select_buf"; -- or "UNUSED"
- g_pipeline_in : natural := 1; -- pipeline in_data
- g_pipeline_in_m : natural := 1; -- pipeline in_data for M-fold fan out
- g_pipeline_out : natural := 1; -- pipeline out_data
+ -- or "UNUSED"
+ g_ram_init_file : string := "../../../src/data/select_buf";
+ -- pipeline in_data
+ g_pipeline_in : natural := 1;
+ -- pipeline in_data for M-fold fan out
+ g_pipeline_in_m : natural := 1;
+ -- pipeline out_data
+ g_pipeline_out : natural := 1;
g_nof_frames : natural := 1
);
end tb_mmf_reorder_row;
diff --git a/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd b/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
index 5572720cd77f88818651c29408756de5700f538d..49ffdbd1693c1a774725aea9514649a05fd3a9f1 100644
--- a/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
@@ -91,26 +91,46 @@ architecture tb of tb_mms_reorder_rewire is
constant c_sel_table: t_reorder_table :=
(
--FN0 FN1 FN2 FN3 BN0 BN1 BN2 BN3
- ( 19, 10, 13, 16, 8 , 8 , 8 , 8 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 0
- ( 10, 13, 16, 19, 11, 11, 11, 11, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 1
- ( 13, 16, 19, 10, 14, 14, 14, 14, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 2
- ( 16, 19, 10, 13, 17, 17, 17, 17, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 3
- ( 8 , 8 , 8 , 8 , 10, 19, 16, 13, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 4
- ( 11, 11, 11, 11, 13, 10, 19, 16, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 5
- ( 14, 14, 14, 14, 16, 13, 10, 19, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 6
- ( 17, 17, 17, 17, 19, 16, 13, 10, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 7
- ( 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 0
- ( 2 , 0 , 6 , 4 , 1 , 3 , 5 , 7 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 1
- ( 9 , 12, 15, 18, 12, 15, 18, 9 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 2
- ( 3 , 3 , 3 , 3 , 2 , 2 , 2 , 2 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 3
- ( 4 , 2 , 0 , 6 , 7 , 1 , 3 , 5 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 4
- ( 12, 15, 18, 9 , 9 , 12, 15, 18, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 5
- ( 5 , 5 , 5 , 5 , 4 , 4 , 4 , 4 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 6
- ( 6 , 4 , 2 , 0 , 5 , 7 , 1 , 3 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 7
- ( 15, 18, 9 , 12, 18, 9 , 12, 15, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 8
- ( 7 , 7 , 7 , 7 , 6 , 6 , 6 , 6 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 9
- ( 0 , 6 , 4 , 2 , 3 , 5 , 7 , 1 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 10
- ( 18, 9 , 12, 15, 15, 18, 9 , 12, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 11
+ -- Local processing output 0
+ ( 19, 10, 13, 16, 8 , 8 , 8 , 8 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Local processing output 1
+ ( 10, 13, 16, 19, 11, 11, 11, 11, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Local processing output 2
+ ( 13, 16, 19, 10, 14, 14, 14, 14, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Local processing output 3
+ ( 16, 19, 10, 13, 17, 17, 17, 17, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Local processing output 4
+ ( 8 , 8 , 8 , 8 , 10, 19, 16, 13, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Local processing output 5
+ ( 11, 11, 11, 11, 13, 10, 19, 16, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Local processing output 6
+ ( 14, 14, 14, 14, 16, 13, 10, 19, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Local processing output 7
+ ( 17, 17, 17, 17, 19, 16, 13, 10, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Mesh Transmit output 0
+ ( 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Mesh Transmit output 1
+ ( 2 , 0 , 6 , 4 , 1 , 3 , 5 , 7 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Mesh Transmit output 2
+ ( 9 , 12, 15, 18, 12, 15, 18, 9 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Mesh Transmit output 3
+ ( 3 , 3 , 3 , 3 , 2 , 2 , 2 , 2 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Mesh Transmit output 4
+ ( 4 , 2 , 0 , 6 , 7 , 1 , 3 , 5 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Mesh Transmit output 5
+ ( 12, 15, 18, 9 , 9 , 12, 15, 18, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Mesh Transmit output 6
+ ( 5 , 5 , 5 , 5 , 4 , 4 , 4 , 4 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Mesh Transmit output 7
+ ( 6 , 4 , 2 , 0 , 5 , 7 , 1 , 3 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Mesh Transmit output 8
+ ( 15, 18, 9 , 12, 18, 9 , 12, 15, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Mesh Transmit output 9
+ ( 7 , 7 , 7 , 7 , 6 , 6 , 6 , 6 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Mesh Transmit output 10
+ ( 0 , 6 , 4 , 2 , 3 , 5 , 7 , 1 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ -- Mesh Transmit output 11
+ ( 18, 9 , 12, 15, 15, 18, 9 , 12, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
@@ -136,11 +156,14 @@ architecture tb of tb_mms_reorder_rewire is
constant c_bg_buf_adr_w : positive := ceil_log2(c_bg_block_len);
constant c_bg_nof_blocks_per_sync : positive := 16;
constant c_bg_gapsize : positive := 8;
- constant c_bg_data_file_prefix : string := "UNUSED"; -- "../../../src/hex/tb_bg_dat";
+ -- "../../../src/hex/tb_bg_dat";
+ constant c_bg_data_file_prefix : string := "UNUSED";
constant c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, 128, 1);
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable: On by default in simulation; MM enable required on hardware.
- '0', -- enable_sync
+ -- enable: On by default in simulation; MM enable required on hardware.
+ constant c_bg_ctrl : t_diag_block_gen := ('0',
+ -- enable_sync
+ '0',
TO_UVEC( c_bg_block_len, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
index c0669ea2dfb18f5bffb521bb5de561c7898ccd49..19805fdeb4b3d037a419cd2f24a0d8c8fa74f354 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
@@ -45,16 +45,19 @@ use dp_lib.tb_dp_pkg.all;
entity tb_reorder_col is
generic (
-- Flow control
- g_mode_in_en : natural := 0; -- use 0 for active in_sosi.valid control
+ -- use 0 for active in_sosi.valid control
+ g_mode_in_en : natural := 0;
-- use 1 for random in_sosi.valid control
- g_mode_out_ready : natural := 0; -- use 0 for active out_siso.ready control
+ -- use 0 for active out_siso.ready control
+ g_mode_out_ready : natural := 0;
-- use 1 for toggling out_siso.ready control, requires g_nof_ch_sel <= g_nof_ch_in/2
-- use 2 for inverted toggling out_siso.ready control, requires g_nof_ch_sel <= g_nof_ch_in/2
-- Test duration
g_nof_sync : natural := 10;
-- Functional parameters
- g_reverse_ss_map : boolean := true; -- use true to verify that the last data written can be read immediately after the SS page swap
+ -- use true to verify that the last data written can be read immediately after the SS page swap
+ g_reverse_ss_map : boolean := true;
--g_nof_ch_in : NATURAL := 256;
g_nof_ch_in : natural := 16;
@@ -66,7 +69,8 @@ entity tb_reorder_col is
g_use_complex : boolean := true;
- g_use_output_rl_adapter : boolean := false -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2
+ -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2
+ g_use_output_rl_adapter : boolean := false
);
end tb_reorder_col;
@@ -89,7 +93,8 @@ architecture tb of tb_reorder_col is
signal mm_dut_mosi : t_mem_mosi;
signal mm_done : std_logic;
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
signal toggle : std_logic := '1';
signal verify_en : std_logic := '0';
signal verify_bsn : std_logic := '1';
@@ -127,9 +132,11 @@ begin
for I in 0 to g_nof_ch_sel - 1 loop
if g_reverse_ss_map = false then
- proc_mem_mm_bus_wr(I, I, clk, mm_dut_mosi); -- Write the default SS map: (0, 1, 2, ... g_nof_ch_sel-1) ==> (0, 1, 2, ... g_nof_ch_sel-1)
+ -- Write the default SS map: (0, 1, 2, ... g_nof_ch_sel-1) ==> (0, 1, 2, ... g_nof_ch_sel-1)
+ proc_mem_mm_bus_wr(I, I, clk, mm_dut_mosi);
else
- proc_mem_mm_bus_wr(I, g_nof_ch_sel - 1 - I, clk, mm_dut_mosi); -- Write the reverse SS map: (0, 1, 2, ... g_nof_ch_sel-1) ==> (g_nof_ch_sel-1, ..., 2, 1, 0)
+ -- Write the reverse SS map: (0, 1, 2, ... g_nof_ch_sel-1) ==> (g_nof_ch_sel-1, ..., 2, 1, 0)
+ proc_mem_mm_bus_wr(I, g_nof_ch_sel - 1 - I, clk, mm_dut_mosi);
end if;
end loop;
mm_done <= '1';
@@ -166,20 +173,25 @@ begin
wait until rising_edge(clk);
for I in 0 to g_nof_sync - 1 loop
if g_use_complex then
- proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi);
v_re := v_re + g_nof_ch_in;
v_im := v_im + g_nof_ch_in;
else
- proc_dp_gen_block_data(c_rl, true, c_nof_complex * c_dsp_data_w, c_nof_complex * c_dsp_data_w, v_data, 0, 0, g_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, true, c_nof_complex * c_dsp_data_w, c_nof_complex * c_dsp_data_w, v_data, 0, 0, g_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi);
v_data := v_data + g_nof_ch_in;
end if;
- for J in 0 to c_nof_block_per_sync - 2 loop -- provide sop and eop for block reference
+ -- provide sop and eop for block reference
+ for J in 0 to c_nof_block_per_sync - 2 loop
if g_use_complex then
- proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi); -- no sync
+ -- no sync
+ proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi);
v_re := v_re + g_nof_ch_in;
v_im := v_im + g_nof_ch_in;
else
- proc_dp_gen_block_data(c_rl, true, c_nof_complex * c_dsp_data_w, c_nof_complex * c_dsp_data_w, v_data, 0, 0, g_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, true, c_nof_complex * c_dsp_data_w, c_nof_complex * c_dsp_data_w, v_data, 0, 0, g_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi);
v_data := v_data + g_nof_ch_in;
end if;
end loop;
@@ -211,7 +223,8 @@ begin
proc_common_wait_some_cycles(clk, 10);
for I in 0 to g_nof_ch_in - 1 loop
- proc_mem_mm_bus_wr(I, g_nof_ch_in - 1 - I, clk, mm_reverse_mosi); -- Write the reverse SS map: (0, 1, 2, ... g_nof_ch_in-1) ==> (g_nof_ch_in-1, ..., 2, 1, 0)
+ -- Write the reverse SS map: (0, 1, 2, ... g_nof_ch_in-1) ==> (g_nof_ch_in-1, ..., 2, 1, 0)
+ proc_mem_mm_bus_wr(I, g_nof_ch_in - 1 - I, clk, mm_reverse_mosi);
end loop;
wait;
@@ -279,8 +292,10 @@ begin
p_verify_en : process
begin
verify_en <= '0';
- proc_common_wait_until_high(clk, in_sosi.eop); -- now the SS will start outputing the first block
- proc_common_wait_some_cycles(clk, 10); -- wait a few cycles for the SS latency
+ -- now the SS will start outputing the first block
+ proc_common_wait_until_high(clk, in_sosi.eop);
+ -- wait a few cycles for the SS latency
+ proc_common_wait_some_cycles(clk, 10);
verify_en <= '1';
wait;
end process;
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
index c335260390e6fd8e1ab24f4091fc1df5c36061b9..3621aba2c997b8df7d1a89d2a3e52fe8c92bf4df 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
@@ -76,13 +76,16 @@ use work.reorder_pkg.all;
entity tb_reorder_col_select_all is
generic(
- g_dsp_data_w : natural := 16; -- complex data width, = c_data_w / 2
+ -- complex data width, = c_data_w / 2
+ g_dsp_data_w : natural := 16;
g_nof_sync : natural := 5;
g_nof_packets_per_sync : natural := 3;
g_nof_blocks_per_packet : natural := 5;
g_nof_data_per_block : natural := 3;
- g_inter_valid_gap : natural := 0; -- nof clk gap in in_sosi.valid
- g_inter_packet_gap : natural := 3; -- nof clk gap betweek in_sosi.eop and next in_sosi.sop
+ -- nof clk gap in in_sosi.valid
+ g_inter_valid_gap : natural := 0;
+ -- nof clk gap betweek in_sosi.eop and next in_sosi.sop
+ g_inter_packet_gap : natural := 3;
g_use_complex : boolean := false;
g_use_dynamic_selection : boolean := false
);
@@ -97,15 +100,19 @@ architecture tb of tb_reorder_col_select_all is
-- Match c_nof_sync with p_nof_ch_stimuli
constant c_nof_sync : natural := sel_a_b(g_use_dynamic_selection, 2, g_nof_sync);
- constant c_factor_blk : natural := sel_a_b(g_use_dynamic_selection, 2, 1); -- factor for more blocks per packet
- constant c_factor_dat : natural := sel_a_b(g_use_dynamic_selection, 1, 1); -- factor for more data per block
- constant c_factor_ch : natural := c_factor_blk * c_factor_dat; -- factor for more data per packet
+ -- factor for more blocks per packet
+ constant c_factor_blk : natural := sel_a_b(g_use_dynamic_selection, 2, 1);
+ -- factor for more data per block
+ constant c_factor_dat : natural := sel_a_b(g_use_dynamic_selection, 1, 1);
+ -- factor for more data per packet
+ constant c_factor_ch : natural := c_factor_blk * c_factor_dat;
constant c_nof_ch : natural := g_nof_blocks_per_packet * g_nof_data_per_block;
constant c_nof_ch_long : natural := c_nof_ch * c_factor_ch;
constant c_sel_gap : natural := c_nof_ch_long * 2;
-- Total output latency for transpose and undo transpose
- constant c_retrieve_lat : natural := 2; -- rd latency of reorder_col_select
+ -- rd latency of reorder_col_select
+ constant c_retrieve_lat : natural := 2;
constant c_output_lat : natural := (c_nof_ch + c_retrieve_lat) * 2;
constant c_output_lat_long : natural := (c_nof_ch_long + c_retrieve_lat) * 2;
@@ -120,7 +127,8 @@ architecture tb of tb_reorder_col_select_all is
-- Data
signal in_en : std_logic := '1';
signal in_sosi : t_dp_sosi := c_dp_sosi_rst;
- signal in_siso : t_dp_siso := c_dp_siso_rdy; -- used for proc_dp_gen_block_data
+ -- used for proc_dp_gen_block_data
+ signal in_siso : t_dp_siso := c_dp_siso_rdy;
signal transposed_sosi : t_dp_sosi;
signal out_sosi : t_dp_sosi;
@@ -191,14 +199,21 @@ begin
c_use_data,
g_dsp_data_w,
g_dsp_data_w,
- v_data, -- data
- v_data, -- re
- v_data + 1, -- im
+ -- data
+ v_data,
+ -- re
+ v_data,
+ -- im
+ v_data + 1,
v_nof_ch,
- v_info + 2, -- channel
- v_info + 3, -- error
- '1', -- with sync
- v_bsn, -- bsn
+ -- channel
+ v_info + 2,
+ -- error
+ v_info + 3,
+ -- with sync
+ '1',
+ -- bsn
+ v_bsn,
clk,
in_en,
in_siso,
@@ -214,14 +229,21 @@ begin
c_use_data,
g_dsp_data_w,
g_dsp_data_w,
- v_data, -- data
- v_data, -- re
- v_data + 1, -- im
+ -- data
+ v_data,
+ -- re
+ v_data,
+ -- im
+ v_data + 1,
v_nof_ch,
- v_info + 2, -- channel
- v_info + 3, -- error
- '0', -- no sync
- v_bsn, -- bsn
+ -- channel
+ v_info + 2,
+ -- error
+ v_info + 3,
+ -- no sync
+ '0',
+ -- bsn
+ v_bsn,
clk,
in_en,
in_siso,
@@ -273,8 +295,10 @@ begin
u_verify_out_sosi : entity dp_lib.dp_stream_verify
generic map (
-- initializations
- g_sync_period => g_nof_packets_per_sync, -- BSN increment per sync interval
- g_sync_offset => 0, -- first BSN
+ -- BSN increment per sync interval
+ g_sync_period => g_nof_packets_per_sync,
+ -- first BSN
+ g_sync_offset => 0,
-- specific
g_in_dat_w => c_data_w,
g_pkt_len => c_nof_ch
@@ -409,7 +433,8 @@ begin
-- Memory Mapped
col_select_mosi => r_transpose.select_copi,
- col_select_miso => select_cipo, -- only used for waitrequest
+ -- only used for waitrequest
+ col_select_miso => select_cipo,
-- Streaming
input_sosi => in_sosi,
@@ -439,7 +464,8 @@ begin
-- Memory Mapped
col_select_mosi => r_undo_transpose.select_copi,
- col_select_miso => undo_select_cipo, -- only used for waitrequest
+ -- only used for waitrequest
+ col_select_miso => undo_select_cipo,
-- Streaming
input_sosi => transposed_sosi,
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd
index d6d5d66f9cd1064fdf8f547fe6ad7b88af5ef8d7..80fbe4a5f441c780f94f6922213ec42147261888 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd
@@ -87,7 +87,8 @@ begin
for J in 0 to c_wb_factor - 1 loop
for I in 0 to c_nof_ch_sel / c_wb_factor - 1 loop
- proc_mem_mm_bus_wr(J * c_adr_incr + I, I, clk, mm_mosi); -- Write the default SS map: (0, 1, 2, ... c_nof_ch_sel-1) ==> (0, 1, 2, ... c_nof_ch_sel-1)
+ -- Write the default SS map: (0, 1, 2, ... c_nof_ch_sel-1) ==> (0, 1, 2, ... c_nof_ch_sel-1)
+ proc_mem_mm_bus_wr(J * c_adr_incr + I, I, clk, mm_mosi);
end loop;
end loop;
mm_done <= '1';
@@ -110,11 +111,14 @@ begin
-- Run some sync intervals with DSP counter data for the real and imag fields
wait until rising_edge(clk);
for I in 0 to c_nof_sync - 1 loop
- proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K));
v_re := v_re + c_nof_ch_in;
v_im := v_im + c_nof_ch_in;
- for J in 0 to c_nof_block_per_sync - 2 loop -- provide sop and eop for block reference
- proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- no sync
+ -- provide sop and eop for block reference
+ for J in 0 to c_nof_block_per_sync - 2 loop
+ -- no sync
+ proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K));
v_re := v_re + c_nof_ch_in;
v_im := v_im + c_nof_ch_in;
end loop;
@@ -124,11 +128,14 @@ begin
-- Run some sync intervals more
wait until rising_edge(clk);
for I in 0 to c_nof_sync - 1 loop
- proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K));
v_re := v_re + c_nof_ch_in;
v_im := v_im + c_nof_ch_in;
- for J in 0 to c_nof_block_per_sync - 2 loop -- provide sop and eop for block reference
- proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- no sync
+ -- provide sop and eop for block reference
+ for J in 0 to c_nof_block_per_sync - 2 loop
+ -- no sync
+ proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K));
v_re := v_re + c_nof_ch_in;
v_im := v_im + c_nof_ch_in;
end loop;
@@ -140,7 +147,8 @@ begin
end generate;
-- Time stimuli
- bsn <= bsn + 1 when rising_edge(clk) and (st_sosi_arr(0).eop = '1'); -- OR st_sosi.sync='1');
+ -- OR st_sosi.sync='1');
+ bsn <= bsn + 1 when rising_edge(clk) and (st_sosi_arr(0).eop = '1');
-- Add BSN to the ST data
p_in_sosi : process(st_sosi_arr, bsn)
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
index 126bfc83b1da467a9966ae330fe6f043de34df28..5cb5c68a33402f2c46fe30bced40e6d2a4d27875 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
@@ -72,16 +72,22 @@ use dp_lib.tb_dp_pkg.all;
entity tb_reorder_col_wide_row_select is
generic(
- g_nof_inputs : natural := 6; -- also nof rows
+ -- also nof rows
+ g_nof_inputs : natural := 6;
g_nof_outputs : natural := 2;
- g_dsp_data_w : natural := 16; -- complex data width, = c_data_w / 2
+ -- complex data width, = c_data_w / 2
+ g_dsp_data_w : natural := 16;
g_nof_sync : natural := 5;
g_nof_block_per_sync : natural := 4;
- g_nof_ch_in : natural := 1024; -- nof input words per block, identical for all input streams.
- g_nof_ch_sel_col : natural := 2; -- nof of sequential collums to select per row.
- g_nof_ch_sel_offset : natural := 2; -- nof offsets defined
+ -- nof input words per block, identical for all input streams.
+ g_nof_ch_in : natural := 1024;
+ -- nof of sequential collums to select per row.
+ g_nof_ch_sel_col : natural := 2;
+ -- nof offsets defined
+ g_nof_ch_sel_offset : natural := 2;
g_ch_sel_offsets : t_natural_arr := (0, 16);
- g_ch_sel_step : natural := 3; -- offset step size to increase per sync interval
+ -- offset step size to increase per sync interval
+ g_ch_sel_step : natural := 3;
g_reorder_row_select_pipe_in : natural := 1;
g_reorder_row_select_pipe_in_m : natural := 1;
g_reorder_row_select_pipe_out : natural := 1
@@ -177,11 +183,14 @@ begin
-- Run some sync intervals with DSP counter data for the real and imag fields
wait until rising_edge(clk);
for I in 0 to g_nof_sync - 1 loop
- proc_dp_gen_block_data(c_rl, false, g_dsp_data_w, g_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, false, g_dsp_data_w, g_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K));
v_re := v_re + g_nof_ch_in;
v_im := v_im + g_nof_ch_in;
- for J in 0 to g_nof_block_per_sync - 2 loop -- provide sop and eop for block reference
- proc_dp_gen_block_data(c_rl, false, g_dsp_data_w, g_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- no sync
+ -- provide sop and eop for block reference
+ for J in 0 to g_nof_block_per_sync - 2 loop
+ -- no sync
+ proc_dp_gen_block_data(c_rl, false, g_dsp_data_w, g_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K));
v_re := v_re + g_nof_ch_in;
v_im := v_im + g_nof_ch_in;
end loop;
@@ -195,7 +204,8 @@ begin
end generate;
-- Time stimuli
- bsn <= bsn + 1 when rising_edge(clk) and (st_sosi_arr(0).eop = '1'); -- OR st_sosi.sync='1');
+ -- OR st_sosi.sync='1');
+ bsn <= bsn + 1 when rising_edge(clk) and (st_sosi_arr(0).eop = '1');
-- Add BSN to the ST data
p_in_sosi : process(st_sosi_arr, bsn)
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
index 62d32e038f01d0a8c9d1d0f5b9697e3c3c8686a8..a534075068c9f7b8feceb29057a612eb0e0f7987 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
@@ -65,15 +65,19 @@ use work.reorder_pkg.all;
entity tb_reorder_transpose is
generic (
- g_wr_chunksize : positive := 176; -- 256;
+ -- 256;
+ g_wr_chunksize : positive := 176;
g_rd_chunksize : positive := 16;
- g_rd_nof_chunks : positive := 11; -- 16;
- g_rd_interval : positive := 16; -- When pre-transpose is used equal to g_rd_chunksize.
+ -- 16;
+ g_rd_nof_chunks : positive := 11;
+ -- When pre-transpose is used equal to g_rd_chunksize.
+ g_rd_interval : positive := 16;
g_gapsize : natural := 0;
g_nof_blocks : positive := 64;
g_nof_streams : positive := 4;
g_in_dat_w : positive := 8;
- g_mem_dat_w : natural := 256; -- The data width to the attached memory.
+ -- The data width to the attached memory.
+ g_mem_dat_w : natural := 256;
g_frame_size_in : natural := 256;
g_frame_size_out : natural := 176;
g_ena_pre_transp : boolean := true
@@ -146,8 +150,10 @@ architecture tb of tb_reorder_transpose is
constant c_mem_size : positive := 2 * c_pagesize;
constant c_mem_size_w : positive := ceil_log2(c_mem_size);
- constant c_wr_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size); -- c_blocksize * 2;
- constant c_rd_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size); -- c_blocksize * 2;
+ -- c_blocksize * 2;
+ constant c_wr_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size);
+ -- c_blocksize * 2;
+ constant c_rd_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size);
constant c_use_complex : boolean := true;
constant c_total_data_w : natural := g_nof_streams * g_in_dat_w;
@@ -164,7 +170,8 @@ architecture tb of tb_reorder_transpose is
constant c_bg_nof_output_streams : positive := g_nof_streams;
constant c_bg_buf_dat_w : positive := c_nof_complex * g_in_dat_w;
constant c_bg_buf_adr_w : positive := ceil_log2(c_bg_block_len);
- constant c_bg_data_file_prefix : string := "UNUSED"; -- "../../../src/hex/tb_bg_dat";
+ -- "../../../src/hex/tb_bg_dat";
+ constant c_bg_data_file_prefix : string := "UNUSED";
constant c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, 128, 1);
-- Configuration of the databuffers:
@@ -332,16 +339,26 @@ begin
u_ddr_mem_ctrl : entity io_ddr_lib.io_ddr
generic map(
- g_tech_ddr => c_tech_ddr, -- : t_c_tech_ddr;
- g_cross_domain_dvr_ctlr => false, -- TRUE, -- : BOOLEAN := TRUE;
- g_wr_data_w => c_data_w, -- : NATURAL := 32;
- g_wr_fifo_depth => c_wr_fifo_depth, -- : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
- g_rd_fifo_depth => c_rd_fifo_depth, -- : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
- g_rd_data_w => c_data_w, -- : NATURAL := 32;
- g_wr_flush_mode => "SYN", -- : STRING := "VAL"; -- "VAL", "SOP", "SYN"
- g_wr_flush_use_channel => false, -- : BOOLEAN := FALSE;
- g_wr_flush_start_channel => 0, -- : NATURAL := 0;
- g_wr_flush_nof_channels => 1 -- : POSITIVE := 1
+ -- : t_c_tech_ddr;
+ g_tech_ddr => c_tech_ddr,
+ -- TRUE, -- : BOOLEAN := TRUE;
+ g_cross_domain_dvr_ctlr => false,
+ -- : NATURAL := 32;
+ g_wr_data_w => c_data_w,
+ -- : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
+ g_wr_fifo_depth => c_wr_fifo_depth,
+ -- : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
+ g_rd_fifo_depth => c_rd_fifo_depth,
+ -- : NATURAL := 32;
+ g_rd_data_w => c_data_w,
+ -- : STRING := "VAL"; -- "VAL", "SOP", "SYN"
+ g_wr_flush_mode => "SYN",
+ -- : BOOLEAN := FALSE;
+ g_wr_flush_use_channel => false,
+ -- : NATURAL := 0;
+ g_wr_flush_start_channel => 0,
+ -- : POSITIVE := 1
+ g_wr_flush_nof_channels => 1
)
port map (
-- DDR reference clock
@@ -349,7 +366,8 @@ begin
ctlr_ref_rst => dp_rst_in,
-- DDR controller clock domain
- ctlr_clk_out => dp_clk, -- output clock of the ddr controller is used as DP clk.
+ -- output clock of the ddr controller is used as DP clk.
+ ctlr_clk_out => dp_clk,
ctlr_rst_out => dp_rst,
ctlr_clk_in => dp_clk,
diff --git a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd
index 5e1b814ea4e76669c569afb79911a634561d2384..410dccebffef4070b4f21064ff70c23007eff8c8 100644
--- a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd
@@ -28,7 +28,8 @@ end tb_tb_reorder_col;
architecture tb of tb_tb_reorder_col is
constant c_nof_sync : natural := 20;
constant c_reverse_ss_map : boolean := true;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 2
-- > run -all --> OK
diff --git a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
index 279f2bdb4b547d0112008dda43a17eca6180f443..9991afd35c8be29fedb7703cbc8978d99e35bc73 100644
--- a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
@@ -34,7 +34,8 @@ entity tb_tb_reorder_col_select_all is
end tb_tb_reorder_col_select_all;
architecture tb of tb_tb_reorder_col_select_all is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_dsp_data_w : natural := 16; -- complex data width, = c_data_w / 2
-- g_nof_sync : natural := 2;
diff --git a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
index 1306c592df15126d11c403bd19903ed5e80fbde5..d6ce0ecd17651d79f0d78560de3e8eb977bc2a1f 100644
--- a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
@@ -36,7 +36,8 @@ end tb_tb_reorder_col_wide_row_select;
architecture tb of tb_tb_reorder_col_wide_row_select is
constant c_nof_sync : natural := 3;
constant c_dsp_data_w : natural := 16;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Generics:
-- g_nof_inputs : NATURAL := 6; -- also nof rows
@@ -54,6 +55,7 @@ begin
-- g_reorder_row_select_pipe_out : NATURAL := 1
u_sdp : entity work.tb_reorder_col_wide_row_select generic map (6, 1, c_dsp_data_w, c_nof_sync, 4, 1024, 2, 2, (0, 16), 3, 0, 1, 1);
- u_max_out : entity work.tb_reorder_col_wide_row_select generic map (8, 1, c_dsp_data_w, c_nof_sync, 1, 512, 8, 8, (0 ,64, 128, 192, 256, 320, 384, 448), 0, 0, 1, 1); -- rows * cols * offsets = 8*8*8 = 512
+ -- rows * cols * offsets = 8*8*8 = 512
+ u_max_out : entity work.tb_reorder_col_wide_row_select generic map (8, 1, c_dsp_data_w, c_nof_sync, 1, 512, 8, 8, (0 ,64, 128, 192, 256, 320, 384, 448), 0, 0, 1, 1);
u_multiple_out : entity work.tb_reorder_col_wide_row_select generic map (2, 5, c_dsp_data_w, c_nof_sync, 4, 1024, 2, 2, (0, 16), 3, 0, 1, 1);
end tb;
diff --git a/libraries/base/ring/src/vhdl/ring_info.vhd b/libraries/base/ring/src/vhdl/ring_info.vhd
index f30cde027d9a0d3dc25787676ac624b52498ab97..16e248bb54998f019ea0fd8c714f8c4fbd6d0fc2 100644
--- a/libraries/base/ring/src/vhdl/ring_info.vhd
+++ b/libraries/base/ring/src/vhdl/ring_info.vhd
@@ -40,8 +40,10 @@ use work.ring_pkg.all;
entity ring_info is
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
dp_clk : in std_logic;
dp_rst : in std_logic;
@@ -58,7 +60,8 @@ architecture str of ring_info is
begin
u_mm_fields: entity mm_lib.mm_fields
generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ -- use FALSE to save logic when always slv_in_val='1'
+ g_use_slv_in_val => false,
g_field_arr => c_ring_info_field_arr
)
port map (
diff --git a/libraries/base/ring/src/vhdl/ring_lane.vhd b/libraries/base/ring/src/vhdl/ring_lane.vhd
index aae48c720df85105ba0946c067aa13ce8ab950be..afbd0b591cca1f187c083bd92fb6531720eca132 100644
--- a/libraries/base/ring/src/vhdl/ring_lane.vhd
+++ b/libraries/base/ring/src/vhdl/ring_lane.vhd
@@ -40,16 +40,21 @@ entity ring_lane is
g_lane_direction : natural := 1;
g_lane_data_w : natural := 64;
g_lane_packet_length : natural := 1024;
- g_lane_total_nof_packets_w : natural := c_longword_w; -- <= c_longword_w = 64
+ -- <= c_longword_w = 64
+ g_lane_total_nof_packets_w : natural := c_longword_w;
g_use_dp_layer : boolean := true;
g_nof_rx_monitors : natural := 0;
g_nof_tx_monitors : natural := 1;
- g_err_bi : natural := 0; -- ring_rx bit index in sosi.err field to set for wrongly sized packets
- g_nof_err_counts : natural := 1; -- nof counters to count the set err bits in range sosi.err(g_nof_err_counts-1 DOWNTO 0)
- g_bsn_at_sync_check_channel : natural := 1; -- on which channel should the bsn be checked
+ -- ring_rx bit index in sosi.err field to set for wrongly sized packets
+ g_err_bi : natural := 0;
+ -- nof counters to count the set err bits in range sosi.err(g_nof_err_counts-1 DOWNTO 0)
+ g_nof_err_counts : natural := 1;
+ -- on which channel should the bsn be checked
+ g_bsn_at_sync_check_channel : natural := 1;
g_validate_channel : boolean := true;
g_validate_channel_mode : string := ">";
- g_sync_timeout : natural := 220 * 10**6 -- 10% margin
+ -- 10% margin
+ g_sync_timeout : natural := 220 * 10**6
);
port (
-- Clocks and reset
diff --git a/libraries/base/ring/src/vhdl/ring_lane_info.vhd b/libraries/base/ring/src/vhdl/ring_lane_info.vhd
index 83c2cf4ca307c5408c5e57b1778609abe79defdc..795e405099b38dd0152407c4e9ea835753c788e6 100644
--- a/libraries/base/ring/src/vhdl/ring_lane_info.vhd
+++ b/libraries/base/ring/src/vhdl/ring_lane_info.vhd
@@ -40,8 +40,10 @@ use work.ring_pkg.all;
entity ring_lane_info is
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
dp_clk : in std_logic;
dp_rst : in std_logic;
@@ -58,7 +60,8 @@ entity ring_lane_info is
end ring_lane_info;
architecture str of ring_lane_info is
- signal lane_info_ro: t_ring_lane_info; -- ro = read only
+ -- ro = read only
+ signal lane_info_ro: t_ring_lane_info;
begin
u_mm_fields: entity work.ring_lane_info_reg
port map (
diff --git a/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd b/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd
index d2a145621ad91194d99a45e79f8c3868fd16bbfa..01d09f74e78097197210edfada52f0f8374b6001 100644
--- a/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd
+++ b/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd
@@ -40,8 +40,10 @@ use work.ring_pkg.all;
entity ring_lane_info_reg is
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
dp_clk : in std_logic;
dp_rst : in std_logic;
@@ -50,7 +52,8 @@ entity ring_lane_info_reg is
reg_miso : out t_mem_miso;
-- sdp info
- lane_info_ro : in t_ring_lane_info; -- ro = read only
+ -- ro = read only
+ lane_info_ro : in t_ring_lane_info;
lane_info : out t_ring_lane_info
);
end ring_lane_info_reg;
@@ -75,7 +78,8 @@ begin
u_mm_fields: entity mm_lib.mm_fields
generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ -- use FALSE to save logic when always slv_in_val='1'
+ g_use_slv_in_val => false,
g_field_arr => c_ring_lane_info_field_arr
)
port map (
diff --git a/libraries/base/ring/src/vhdl/ring_mux.vhd b/libraries/base/ring/src/vhdl/ring_mux.vhd
index da34e38528c5ac357e9460875f7c8e416b8216b9..c1743faf7f4ae1855b0360cef0b6bf065d4d160d 100644
--- a/libraries/base/ring/src/vhdl/ring_mux.vhd
+++ b/libraries/base/ring/src/vhdl/ring_mux.vhd
@@ -46,8 +46,10 @@ entity ring_mux is
g_use_empty : boolean := true;
g_use_error : boolean := true;
g_use_sync : boolean := true;
- g_fifo_af_xon : natural := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
- g_fifo_size : t_natural_arr := array_init(1024, 2) -- must match c_nof_input
+ -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
+ g_fifo_af_xon : natural := 0;
+ -- must match c_nof_input
+ g_fifo_size : t_natural_arr := array_init(1024, 2)
);
port (
-- Clocks and reset
@@ -81,7 +83,8 @@ begin
u_dp_mux : entity dp_lib.dp_mux
generic map (
g_nof_input => c_nof_input,
- g_append_channel_lo => false, -- Keep channels the same as the input.
+ -- Keep channels the same as the input.
+ g_append_channel_lo => false,
g_use_fifo => true,
g_bsn_w => g_bsn_w,
g_data_w => g_data_w,
diff --git a/libraries/base/ring/src/vhdl/ring_pkg.vhd b/libraries/base/ring/src/vhdl/ring_pkg.vhd
index 58bb4193ddcc01c9f29e774916019a5318fe426e..6662e9f6c20e82241c20181a33028fb3fb622d33 100644
--- a/libraries/base/ring/src/vhdl/ring_pkg.vhd
+++ b/libraries/base/ring/src/vhdl/ring_pkg.vhd
@@ -78,7 +78,8 @@ package ring_pkg is
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(c_ring_eth_src_mac) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(0) )
);
- constant c_ring_eth_hdr_field_size : natural := ceil_div(field_slv_len(c_ring_eth_hdr_field_arr), c_longword_w); -- = 14/8 = 2 longwords
+ -- = 14/8 = 2 longwords
+ constant c_ring_eth_hdr_field_size : natural := ceil_div(field_slv_len(c_ring_eth_hdr_field_arr), c_longword_w);
constant c_ring_dp_nof_hdr_fields : natural := 6;
constant c_ring_dp_hdr_field_sel : std_logic_vector(c_ring_dp_nof_hdr_fields - 1 downto 0) := "000" & "000";
@@ -90,10 +91,12 @@ package ring_pkg is
( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
( field_name_pad("dp_bsn" ), "RW", 63, field_default(0) )
);
- constant c_ring_dp_hdr_field_size : natural := ceil_div(field_slv_len(c_ring_dp_hdr_field_arr), c_longword_w); -- = 24/8 = 3 longwords
+ -- = 24/8 = 3 longwords
+ constant c_ring_dp_hdr_field_size : natural := ceil_div(field_slv_len(c_ring_dp_hdr_field_arr), c_longword_w);
function func_ring_nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : natural) return natural;
- function func_ring_nof_hops_to_source_rn(hops, this_rn, N_rn : std_logic_vector; lane_dir : natural) return std_logic_vector; -- return vector length is same as hops vector length
+ -- return vector length is same as hops vector length
+ function func_ring_nof_hops_to_source_rn(hops, this_rn, N_rn : std_logic_vector; lane_dir : natural) return std_logic_vector;
end package ring_pkg;
@@ -103,13 +106,16 @@ package body ring_pkg is
variable v_source_rn_nat : natural;
begin
- if lane_dir > 0 then -- transport in positive direction (even lanes)
+ -- transport in positive direction (even lanes)
+ if lane_dir > 0 then
v_source_rn := this_rn - hops;
- else -- transport in negative direction (odd lanes)
+ -- transport in negative direction (odd lanes)
+ else
v_source_rn := this_rn + hops;
end if;
- if v_source_rn < 0 then -- Cannot use MOD as N_rn is not a constant.
+ -- Cannot use MOD as N_rn is not a constant.
+ if v_source_rn < 0 then
v_source_rn := v_source_rn + N_rn;
end if;
diff --git a/libraries/base/ring/src/vhdl/ring_rx.vhd b/libraries/base/ring/src/vhdl/ring_rx.vhd
index 42c1b8d2061d6f5b4f65d94b1865c94526e3bb00..bb0297f24693cf602eb306ba23a343bceb062a98 100644
--- a/libraries/base/ring/src/vhdl/ring_rx.vhd
+++ b/libraries/base/ring/src/vhdl/ring_rx.vhd
@@ -39,19 +39,23 @@ entity ring_rx is
generic (
g_use_dp_layer : boolean := true;
g_lane_direction : natural := 1;
- g_total_nof_packets_w : natural := 48; -- <= c_longword_w = 64
+ -- <= c_longword_w = 64
+ g_total_nof_packets_w : natural := 48;
g_data_w : natural := 64;
g_nof_rx_monitors : natural := 1;
g_err_bi : natural := 0;
g_block_size : natural := 1024;
g_nof_err_counts : natural := 1;
g_check_channel : natural := 1;
- g_sync_timeout : natural := 220 * 10**6 -- 10% margin
+ -- 10% margin
+ g_sync_timeout : natural := 220 * 10**6
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
dp_clk : in std_logic;
dp_rst : in std_logic;
@@ -88,7 +92,8 @@ architecture str of ring_rx is
signal decoded_sosi : t_dp_sosi;
signal monitor_sosi : t_dp_sosi;
signal piped_monitor_sosi : t_dp_sosi;
- signal demux_sosi_arr : t_dp_sosi_arr(0 to g_nof_rx_monitors - 1); -- using 0 TO ... as that is the output of the demux
+ -- using 0 TO ... as that is the output of the demux
+ signal demux_sosi_arr : t_dp_sosi_arr(0 to g_nof_rx_monitors - 1);
signal monitor_sosi_arr : t_dp_sosi_arr(g_nof_rx_monitors - 1 downto 0);
signal hdr_fields_out : std_logic_vector(1023 downto 0);
@@ -118,13 +123,17 @@ begin
-- intervals multiplexed on one lane).
u_dp_block_validate_err : entity dp_lib.dp_block_validate_err
generic map (
- g_cnt_w => c_word_w, -- <= c_word_w = 32
- g_blk_cnt_w => g_total_nof_packets_w, -- <= c_longword_w = 64
+ -- <= c_word_w = 32
+ g_cnt_w => c_word_w,
+ -- <= c_longword_w = 64
+ g_blk_cnt_w => g_total_nof_packets_w,
g_max_block_size => c_packet_size,
g_min_block_size => c_packet_size,
g_nof_err_counts => g_nof_err_counts,
- g_fifo_size => c_packet_size, -- can be same as g_max_block_size as src_in.ready = '1'
- g_use_sync => false, -- no need to pass on ref_sync
+ -- can be same as g_max_block_size as src_in.ready = '1'
+ g_fifo_size => c_packet_size,
+ -- no need to pass on ref_sync
+ g_use_sync => false,
g_data_w => g_data_w
)
port map (
@@ -220,7 +229,8 @@ begin
snk_in => piped_monitor_sosi,
src_out_arr => demux_sosi_arr
);
- monitor_sosi_arr <= func_dp_stream_arr_reverse_range(demux_sosi_arr); -- Fix reversed bus.
+ -- Fix reversed bus.
+ monitor_sosi_arr <= func_dp_stream_arr_reverse_range(demux_sosi_arr);
-- BSN Monitors
u_mms_dp_bsn_monitor_v2 : entity dp_lib.mms_dp_bsn_monitor_v2
diff --git a/libraries/base/ring/src/vhdl/ring_tx.vhd b/libraries/base/ring/src/vhdl/ring_tx.vhd
index 059e6fb0a3cb105549c0b655dcf479ac79468073..a21c6520d1f979917e0470b932b1d95382078496 100644
--- a/libraries/base/ring/src/vhdl/ring_tx.vhd
+++ b/libraries/base/ring/src/vhdl/ring_tx.vhd
@@ -46,12 +46,15 @@ entity ring_tx is
g_validate_channel : boolean := true;
g_mode : string := ">";
g_nof_tx_monitors : natural := 1;
- g_sync_timeout : natural := 220 * 10**6 -- 10% margin
+ -- 10% margin
+ g_sync_timeout : natural := 220 * 10**6
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
dp_clk : in std_logic;
dp_rst : in std_logic;
@@ -77,7 +80,8 @@ architecture str of ring_tx is
constant c_nof_hdr_fields : natural := sel_a_b(g_use_dp_layer, c_ring_dp_nof_hdr_fields, c_ring_eth_nof_hdr_fields);
constant c_hdr_field_sel : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := sel_a_b(g_use_dp_layer, c_ring_dp_hdr_field_sel, c_ring_eth_hdr_field_sel);
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := sel_a_b(g_use_dp_layer, c_ring_dp_hdr_field_arr, c_ring_eth_hdr_field_arr);
- constant c_fifo_size : natural := 64; -- Large enough to fit ETH/DP header + slack (choose power of 2).
+ -- Large enough to fit ETH/DP header + slack (choose power of 2).
+ constant c_fifo_size : natural := 64;
signal validated_sosi : t_dp_sosi;
signal tx_sosi : t_dp_sosi;
@@ -86,7 +90,8 @@ architecture str of ring_tx is
signal lane_tx_sosi : t_dp_sosi;
signal monitor_sosi : t_dp_sosi;
signal piped_monitor_sosi : t_dp_sosi;
- signal demux_sosi_arr : t_dp_sosi_arr(0 to g_nof_tx_monitors - 1); -- using 0 TO ... as that is the output of the demux
+ -- using 0 TO ... as that is the output of the demux
+ signal demux_sosi_arr : t_dp_sosi_arr(0 to g_nof_tx_monitors - 1);
signal monitor_sosi_arr : t_dp_sosi_arr(g_nof_tx_monitors - 1 downto 0);
signal hdr_fields_in : std_logic_vector(1023 downto 0);
@@ -183,10 +188,12 @@ begin
-- Select output based on tx_select
p_sel_out : process(lane_tx_sosi, tx_select)
begin
- if tx_select = '1' then -- transmit via cable
+ -- transmit via cable
+ if tx_select = '1' then
lane_tx_cable_sosi <= lane_tx_sosi;
lane_tx_board_sosi <= c_dp_sosi_rst;
- else -- transmit via board
+ -- transmit via board
+ else
lane_tx_cable_sosi <= c_dp_sosi_rst;
lane_tx_board_sosi <= lane_tx_sosi;
end if;
@@ -219,7 +226,8 @@ begin
snk_in => piped_monitor_sosi,
src_out_arr => demux_sosi_arr
);
- monitor_sosi_arr <= func_dp_stream_arr_reverse_range(demux_sosi_arr); -- Fix reversed bus.
+ -- Fix reversed bus.
+ monitor_sosi_arr <= func_dp_stream_arr_reverse_range(demux_sosi_arr);
u_mms_dp_bsn_monitor_v2 : entity dp_lib.mms_dp_bsn_monitor_v2
generic map (
diff --git a/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd b/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
index 7ce96472307a11181609ce2427f412747b04b4fb..163458c5cab382370ccb27f745a5bc4606d905df 100644
--- a/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
+++ b/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
@@ -42,8 +42,10 @@ entity tb_ring_lane_info is
end tb_ring_lane_info;
architecture tb of tb_ring_lane_info is
- constant c_dp_clk_period : time := 5 ns; -- 200 MHz
- constant c_mm_clk_period : time := 20 ns; -- 50 MHz
+ -- 200 MHz
+ constant c_dp_clk_period : time := 5 ns;
+ -- 50 MHz
+ constant c_mm_clk_period : time := 20 ns;
constant c_cross_clock_domain_latency : natural := 20;
@@ -54,10 +56,12 @@ architecture tb of tb_ring_lane_info is
signal tb_end : std_logic := '0';
signal tb_mm_reg_end : std_logic := '0';
- signal dp_clk : std_logic := '1'; -- digital data path clock = 200 MHz (deser factor 4);
+ -- digital data path clock = 200 MHz (deser factor 4);
+ signal dp_clk : std_logic := '1';
signal dp_rst : std_logic;
- signal mm_clk : std_logic := '1'; -- MM control clock = 50 MHz
+ -- MM control clock = 50 MHz
+ signal mm_clk : std_logic := '1';
signal mm_rst : std_logic;
signal reg_mosi : t_mem_mosi := c_mem_mosi_rst;
@@ -87,7 +91,8 @@ begin
-- default all register hold value 0, try to write 1 in all registers
proc_mem_mm_bus_wr(c_mm_addr_transport_nof_hops ,11 ,mm_clk, reg_miso, reg_mosi);
- proc_mem_mm_bus_wr(c_mm_addr_lane_direction ,1 ,mm_clk, reg_miso, reg_mosi); -- RO
+ -- RO
+ proc_mem_mm_bus_wr(c_mm_addr_lane_direction ,1 ,mm_clk, reg_miso, reg_mosi);
proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency);
proc_mem_mm_bus_rd(c_mm_addr_transport_nof_hops, mm_clk, reg_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
@@ -106,7 +111,8 @@ begin
-- check if values in lane_info match with expected values
p_lane_info_stimuli : process
begin
- proc_common_wait_until_high(mm_clk, tb_mm_reg_end); -- wait for p_mm_reg_stimuli done
+ -- wait for p_mm_reg_stimuli done
+ proc_common_wait_until_high(mm_clk, tb_mm_reg_end);
assert TO_UINT(lane_info.transport_nof_hops) = 11 report "wrong lane_info.transport_nof_hops value" severity ERROR;
assert lane_info.lane_direction = '0' report "wrong lane_info.lane_direction value" severity ERROR;
diff --git a/libraries/base/sens/src/vhdl/sens.vhd b/libraries/base/sens/src/vhdl/sens.vhd
index b6dbc55dabeedc248878e9743907b8b270dbde47..3336268edcf81a295eff7a554beeffb62d109a9e 100644
--- a/libraries/base/sens/src/vhdl/sens.vhd
+++ b/libraries/base/sens/src/vhdl/sens.vhd
@@ -29,7 +29,8 @@ entity sens is
generic (
g_temp_high : natural := 127;
g_bus_dat_w : natural := 8;
- g_sens_temp_volt_sz : natural := 9; -- Should match nof read bytes via I2C in the sens_ctrl SEQUENCE list
+ -- Should match nof read bytes via I2C in the sens_ctrl SEQUENCE list
+ g_sens_temp_volt_sz : natural := 9;
g_sim : natural := 0
);
port (
@@ -48,15 +49,21 @@ architecture str of sens is
constant cs_sim : boolean := is_true(g_sim);
-- SENS read out rate settings
- constant c_sens_update_clk_cnt_w : natural := 27; -- 2^27 @ 160 MHz = 0.84 sec, 2^27 @ 200 MHz = 0.67 sec
- constant c_update_clk_cnt_w : natural := sel_a_b(g_sim, 15, c_sens_update_clk_cnt_w); -- define sens update rate
+ -- 2^27 @ 160 MHz = 0.84 sec, 2^27 @ 200 MHz = 0.67 sec
+ constant c_sens_update_clk_cnt_w : natural := 27;
+ -- define sens update rate
+ constant c_update_clk_cnt_w : natural := sel_a_b(g_sim, 15, c_sens_update_clk_cnt_w);
-- I2C clock rate settings
- constant c_i2c_sens_clk_cnt : natural := 399; -- (200 MHz/ 5 / (399+1)) = 100 kbps
- constant c_i2c_sens_comma_w : natural := 0; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
+ -- (200 MHz/ 5 / (399+1)) = 100 kbps
+ constant c_i2c_sens_clk_cnt : natural := 399;
+ -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
+ constant c_i2c_sens_comma_w : natural := 0;
-- 0 = no comma time
- constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, c_i2c_sens_clk_cnt); -- define I2C clock rate
- constant c_sens_comma_w : natural := sel_a_b(g_sim, 0, c_i2c_sens_comma_w); -- define I2C comma time
+ -- define I2C clock rate
+ constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, c_i2c_sens_clk_cnt);
+ -- define I2C comma time
+ constant c_sens_comma_w : natural := sel_a_b(g_sim, 0, c_i2c_sens_comma_w);
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
diff --git a/libraries/base/sens/src/vhdl/sens_ctrl.vhd b/libraries/base/sens/src/vhdl/sens_ctrl.vhd
index e3a0cc0b377ce888cf5469821964d2fe5732d5a7..f90ee63d1cf1509f03f27c8e76671389b2318615 100644
--- a/libraries/base/sens/src/vhdl/sens_ctrl.vhd
+++ b/libraries/base/sens/src/vhdl/sens_ctrl.vhd
@@ -86,7 +86,8 @@ architecture rtl of sens_ctrl is
SMBUS_C_NOP
);
- signal seq_start : std_logic; -- The I2C sequence to read out the sensors is started when clk_cnt = 0
+ -- The I2C sequence to read out the sensors is started when clk_cnt = 0
+ signal seq_start : std_logic;
signal nxt_seq_start : std_logic;
signal seq_cnt : natural range 0 to SEQ'high;
diff --git a/libraries/base/sens/tb/vhdl/tb_sens.vhd b/libraries/base/sens/tb/vhdl/tb_sens.vhd
index db6ed53a022866225beba988ddaf3b989b9d2702..2da545fc6c701c7b51dad43385942e1d917a60db 100644
--- a/libraries/base/sens/tb/vhdl/tb_sens.vhd
+++ b/libraries/base/sens/tb/vhdl/tb_sens.vhd
@@ -33,24 +33,35 @@ architecture tb of tb_sens is
constant c_rst_period : time := 4 * c_clk_period;
constant c_bus_dat_w : natural := 8;
- constant c_sens_temp_volt_sz : natural := 9; -- Should match nof read bytes via I2C in the sens_ctrl SEQUENCE list
+ -- Should match nof read bytes via I2C in the sens_ctrl SEQUENCE list
+ constant c_sens_temp_volt_sz : natural := 9;
-- Model I2C sensor slaves as on the LOFAR RSP board
- constant c_bp_volt_address : std_logic_vector(6 downto 0) := "0010100"; -- MAX6652 address GND
- constant c_bp_temp_address : std_logic_vector(6 downto 0) := "0101010"; -- MAX1618 address MID MID
- constant c_ap0_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
- constant c_ap1_temp_address : std_logic_vector(6 downto 0) := "0011010"; -- MAX1618 address LOW HIGH
- constant c_ap2_temp_address : std_logic_vector(6 downto 0) := "1001100"; -- MAX1618 address HIGH LOW
- constant c_ap3_temp_address : std_logic_vector(6 downto 0) := "1001110"; -- MAX1618 address HIGH HIGH
+ -- MAX6652 address GND
+ constant c_bp_volt_address : std_logic_vector(6 downto 0) := "0010100";
+ -- MAX1618 address MID MID
+ constant c_bp_temp_address : std_logic_vector(6 downto 0) := "0101010";
+ -- MAX1618 address LOW LOW
+ constant c_ap0_temp_address : std_logic_vector(6 downto 0) := "0011000";
+ -- MAX1618 address LOW HIGH
+ constant c_ap1_temp_address : std_logic_vector(6 downto 0) := "0011010";
+ -- MAX1618 address HIGH LOW
+ constant c_ap2_temp_address : std_logic_vector(6 downto 0) := "1001100";
+ -- MAX1618 address HIGH HIGH
+ constant c_ap3_temp_address : std_logic_vector(6 downto 0) := "1001110";
constant c_bp_temp : integer := 60;
constant c_ap0_temp : integer := 70;
constant c_ap1_temp : integer := 71;
constant c_ap2_temp : integer := 72;
constant c_ap3_temp : integer := 73;
- constant c_volt_1v2 : natural := 92; -- 92 * 2.5/192 = 1.2
- constant c_volt_2v5 : natural := 147; -- 147 * 3.3/192 = 2.5
- constant c_volt_nc : natural := 13; -- 13 * 12 /192 = 0.1
- constant c_volt_3v3 : natural := 127; -- 127 * 5.0/192 = 3.3
+ -- 92 * 2.5/192 = 1.2
+ constant c_volt_1v2 : natural := 92;
+ -- 147 * 3.3/192 = 2.5
+ constant c_volt_2v5 : natural := 147;
+ -- 13 * 12 /192 = 0.1
+ constant c_volt_nc : natural := 13;
+ -- 127 * 5.0/192 = 3.3
+ constant c_volt_3v3 : natural := 127;
constant c_temp_pcb : natural := 40;
type t_sens_data_arr is array (0 to c_sens_temp_volt_sz - 1) of std_logic_vector(c_bus_dat_w - 1 downto 0);
@@ -67,7 +78,8 @@ architecture tb of tb_sens is
signal sens_data : std_logic_vector(c_sens_temp_volt_sz * c_bus_dat_w - 1 downto 0);
signal sens_data_bytes : t_sens_data_arr;
- signal exp_data_bytes : t_nat_natural_arr(0 to c_sens_temp_volt_sz - 1) := (92, 147, 127, 40, 60, 70, 71, 72, 73); -- expected 9 bytes as read by SEQUENCE in sens_ctrl
+ -- expected 9 bytes as read by SEQUENCE in sens_ctrl
+ signal exp_data_bytes : t_nat_natural_arr(0 to c_sens_temp_volt_sz - 1) := (92, 147, 127, 40, 60, 70, 71, 72, 73);
begin
-- run -all
@@ -98,15 +110,18 @@ begin
end process;
-- I2C bus
- scl <= 'H'; -- model I2C pull up
- sda <= 'H'; -- model I2C pull up
+ -- model I2C pull up
+ scl <= 'H';
+ -- model I2C pull up
+ sda <= 'H';
scl <= scl_stretch;
sens_clk_stretch : process (scl)
begin
if falling_edge(scl) then
- scl_stretch <= '0', 'Z' after 50 ns; -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ scl_stretch <= '0', 'Z' after 50 ns;
end if;
end process;
diff --git a/libraries/base/ss/src/vhdl/ss.vhd b/libraries/base/ss/src/vhdl/ss.vhd
index e53037f69f31bcd234a768a464af0b6ab7e1f946..a49a18ca3fb62f92eb015f02a24ee2ded1c664e5 100644
--- a/libraries/base/ss/src/vhdl/ss.vhd
+++ b/libraries/base/ss/src/vhdl/ss.vhd
@@ -61,10 +61,12 @@ use technology_lib.technology_select_pkg.all;
entity ss is
generic (
g_technology : natural := c_tech_select_default;
- g_use_output_rl_adapter : boolean := false; -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2 which is fine if no flow control is needed.
+ -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2 which is fine if no flow control is needed.
+ g_use_output_rl_adapter : boolean := false;
g_dsp_data_w : natural := 18;
g_nof_ch_in : natural := 512;
- g_nof_ch_sel : natural := 252; -- g_nof_ch_sel < g_nof_ch_in
+ -- g_nof_ch_sel < g_nof_ch_in
+ g_nof_ch_sel : natural := 252;
g_select_file_name : string := "UNUSED";
g_use_complex : boolean := true
);
@@ -75,14 +77,18 @@ entity ss is
dp_clk : in std_logic;
-- Memory Mapped
- ram_ss_ss_mosi : in t_mem_mosi; -- channel select control
+ -- channel select control
+ ram_ss_ss_mosi : in t_mem_mosi;
ram_ss_ss_miso : out t_mem_miso;
-- Streaming
- input_sosi : in t_dp_sosi; -- complex input
- input_siso : out t_dp_siso; -- complex input
+ -- complex input
+ input_sosi : in t_dp_sosi;
+ -- complex input
+ input_siso : out t_dp_siso;
- output_sosi : out t_dp_sosi; -- selected complex output with flow control
+ -- selected complex output with flow control
+ output_sosi : out t_dp_sosi;
output_siso : in t_dp_siso := c_dp_siso_rdy
);
end ss;
@@ -92,7 +98,8 @@ architecture str of ss is
adr_w => ceil_log2(g_nof_ch_in),
dat_w => c_nof_complex * g_dsp_data_w,
nof_dat => g_nof_ch_in,
- init_sl => '0'); -- ST side : stat_mosi
+ -- ST side : stat_mosi
+ init_sl => '0');
constant c_select_buf : t_c_mem := (latency => 1,
adr_w => ceil_log2(g_nof_ch_sel),
@@ -100,11 +107,15 @@ architecture str of ss is
nof_dat => g_nof_ch_sel,
init_sl => '0');
- constant c_data_nof_pages : natural := 2; -- fixed dual page SS
- constant c_info_nof_pages : natural := 2; -- fixed, fits the dual page block latency and logic latency of the SS
+ -- fixed dual page SS
+ constant c_data_nof_pages : natural := 2;
+ -- fixed, fits the dual page block latency and logic latency of the SS
+ constant c_info_nof_pages : natural := 2;
- constant c_retrieve_lat : natural := c_select_buf.latency + c_store_buf.latency; -- = 2
- constant c_output_rl : natural := sel_a_b(g_use_output_rl_adapter, 1, c_retrieve_lat); -- force SS RL from 2 -> 1 or leave it at 2
+ -- = 2
+ constant c_retrieve_lat : natural := c_select_buf.latency + c_store_buf.latency;
+ -- force SS RL from 2 -> 1 or leave it at 2
+ constant c_output_rl : natural := sel_a_b(g_use_output_rl_adapter, 1, c_retrieve_lat);
signal info_sop_wr_en : std_logic_vector(c_info_nof_pages - 1 downto 0);
signal info_eop_wr_en : std_logic_vector(c_info_nof_pages - 1 downto 0);
@@ -240,7 +251,8 @@ begin
output_siso => retrieve_siso
);
- u_rl : entity dp_lib.dp_latency_adapter -- defaults to wires when c_output_rl = c_retrieve_lat
+ -- defaults to wires when c_output_rl = c_retrieve_lat
+ u_rl : entity dp_lib.dp_latency_adapter
generic map (
g_in_latency => c_retrieve_lat,
g_out_latency => c_output_rl
diff --git a/libraries/base/ss/src/vhdl/ss_parallel.vhd b/libraries/base/ss/src/vhdl/ss_parallel.vhd
index 4a458c7ed4518b78377488f76ab2e6ca85df9a78..2b746f7f313872a67951e984819cf9dda85b8423 100644
--- a/libraries/base/ss/src/vhdl/ss_parallel.vhd
+++ b/libraries/base/ss/src/vhdl/ss_parallel.vhd
@@ -63,9 +63,12 @@ entity ss_parallel is
g_dsp_data_w : natural := 16;
g_frame_size_in : natural := 256;
g_frame_size_out : natural := 192;
- g_reorder_in_file_name : string := "UNUSED"; -- path_to_file.hex
- g_ss_wide_file_prefix : string := "UNUSED"; -- path_to_file
- g_reorder_out_file_name : string := "UNUSED" -- path_to_file.hex
+ -- path_to_file.hex
+ g_reorder_in_file_name : string := "UNUSED";
+ -- path_to_file
+ g_ss_wide_file_prefix : string := "UNUSED";
+ -- path_to_file.hex
+ g_reorder_out_file_name : string := "UNUSED"
);
port (
mm_rst : in std_logic;
diff --git a/libraries/base/ss/src/vhdl/ss_reorder.vhd b/libraries/base/ss/src/vhdl/ss_reorder.vhd
index 1f00b179dd9a3003a186f10063d4b1ed9f1abe93..1f4d99f1991080f7934a5b88747629e3247ec844 100644
--- a/libraries/base/ss/src/vhdl/ss_reorder.vhd
+++ b/libraries/base/ss/src/vhdl/ss_reorder.vhd
@@ -46,10 +46,14 @@ entity ss_reorder is
g_frame_size : natural := 256;
g_nof_inputs : natural := 8;
g_nof_outputs : natural := 16;
- g_ram_init_file : string := "../../../src/data/select_buf"; -- or "UNUSED"
- g_pipeline_in : natural := 1; -- pipeline in_data
- g_pipeline_in_m : natural := 1; -- pipeline in_data for M-fold fan out
- g_pipeline_out : natural := 1 -- pipeline out_data
+ -- or "UNUSED"
+ g_ram_init_file : string := "../../../src/data/select_buf";
+ -- pipeline in_data
+ g_pipeline_in : natural := 1;
+ -- pipeline in_data for M-fold fan out
+ g_pipeline_in_m : natural := 1;
+ -- pipeline out_data
+ g_pipeline_out : natural := 1
);
port (
mm_rst : in std_logic;
@@ -69,7 +73,8 @@ entity ss_reorder is
end ss_reorder;
architecture str of ss_reorder is
- constant c_sel_buf_read_lat : natural := 1; -- Latency introduced by the counter.
+ -- Latency introduced by the counter.
+ constant c_sel_buf_read_lat : natural := 1;
constant c_tot_pipeline : natural := g_pipeline_in + g_pipeline_in_m + g_pipeline_out + c_sel_buf_read_lat;
constant c_select_w : natural := ceil_log2(g_nof_inputs);
diff --git a/libraries/base/ss/src/vhdl/ss_retrieve.vhd b/libraries/base/ss/src/vhdl/ss_retrieve.vhd
index 2d4c2b3c4bcfe77921cfd4d363960a2a014b9fce..58d4097c8db15cab88bb417aeedb4d32ae68091d 100644
--- a/libraries/base/ss/src/vhdl/ss_retrieve.vhd
+++ b/libraries/base/ss/src/vhdl/ss_retrieve.vhd
@@ -72,7 +72,8 @@ entity ss_retrieve is
end ss_retrieve;
architecture rtl of ss_retrieve is
- constant c_retrieve_lat : natural := 2; -- fixed 1 for select buf read + 1 for store buf read
+ -- fixed 1 for select buf read + 1 for store buf read
+ constant c_retrieve_lat : natural := 2;
signal ch_cnt : integer range 0 to g_nof_ch_sel - 1;
signal nxt_ch_cnt : integer;
@@ -110,7 +111,8 @@ begin
u_retrieve_en : entity common_lib.common_switch
generic map (
g_rst_level => '0',
- g_priority_lo => false, -- store_done has priority over nxt_retrieve_done when they occur simultaneously
+ -- store_done has priority over nxt_retrieve_done when they occur simultaneously
+ g_priority_lo => false,
g_or_high => true,
g_and_low => false
)
@@ -118,7 +120,8 @@ begin
rst => rst,
clk => clk,
switch_high => store_done,
- switch_low => nxt_retrieve_done, -- can not use retrieve_done with g_and_low = TRUE, because if retrieve_done occurs after next store_done then that page gets missed
+ -- can not use retrieve_done with g_and_low = TRUE, because if retrieve_done occurs after next store_done then that page gets missed
+ switch_low => nxt_retrieve_done,
out_level => retrieve_en
);
@@ -144,7 +147,8 @@ begin
retrieve_eop_dly(0) <= '1' when retrieve_ready = '1' and ch_cnt = g_nof_ch_sel - 1 else '0';
-- First read store buf address from select buf when the output is ready
- select_mosi.rd <= '1'; -- no need to use retrieve_ready here, keep rd active to ease timing closure
+ -- no need to use retrieve_ready here, keep rd active to ease timing closure
+ select_mosi.rd <= '1';
select_mosi.address <= TO_MEM_ADDRESS(ch_cnt);
-- Then use the read select address to read the data from the store buf
diff --git a/libraries/base/ss/src/vhdl/ss_store.vhd b/libraries/base/ss/src/vhdl/ss_store.vhd
index b0acf7da04934d4c22104817ab993caeea891c3c..fb02ec7545228bfcc001f12a44dfa29cf9b707db 100644
--- a/libraries/base/ss/src/vhdl/ss_store.vhd
+++ b/libraries/base/ss/src/vhdl/ss_store.vhd
@@ -45,9 +45,12 @@ use dp_lib.dp_stream_pkg.all;
entity ss_store is
generic (
- g_dsp_data_w : natural; -- = width of sosi.im = width of sosi.re
- g_nof_ch_in : natural; -- = nof valid per input block (sop to eop)
- g_use_complex : boolean := true -- = TRUE --> use RE and IM field. FALSE = use DATA field
+ -- = width of sosi.im = width of sosi.re
+ g_dsp_data_w : natural;
+ -- = nof valid per input block (sop to eop)
+ g_nof_ch_in : natural;
+ -- = TRUE --> use RE and IM field. FALSE = use DATA field
+ g_use_complex : boolean := true
);
port (
rst : in std_logic;
diff --git a/libraries/base/ss/src/vhdl/ss_wide.vhd b/libraries/base/ss/src/vhdl/ss_wide.vhd
index 37bb7363ccc4da379d7723f6daf5e13167ad545e..f7383fcf4a8138507251d8d55d145b95cb81d026 100644
--- a/libraries/base/ss/src/vhdl/ss_wide.vhd
+++ b/libraries/base/ss/src/vhdl/ss_wide.vhd
@@ -45,7 +45,8 @@ entity ss_wide is
g_wb_factor : natural := 4;
g_dsp_data_w : natural := 18;
g_nof_ch_in : natural := 256;
- g_nof_ch_sel : natural := 192; -- g_nof_ch_sel < g_nof_ch_in
+ -- g_nof_ch_sel < g_nof_ch_in
+ g_nof_ch_sel : natural := 192;
g_select_file_prefix : string := "UNUSED";
g_use_complex : boolean := true
);
@@ -56,14 +57,18 @@ entity ss_wide is
dp_clk : in std_logic;
-- Memory Mapped
- ram_ss_ss_wide_mosi : in t_mem_mosi; -- channel select control
+ -- channel select control
+ ram_ss_ss_wide_mosi : in t_mem_mosi;
ram_ss_ss_wide_miso : out t_mem_miso;
-- Streaming
- input_sosi_arr : in t_dp_sosi_arr(g_wb_factor - 1 downto 0); -- complex input
- input_siso_arr : out t_dp_siso_arr(g_wb_factor - 1 downto 0) := (others => c_dp_siso_rdy); -- complex input
+ -- complex input
+ input_sosi_arr : in t_dp_sosi_arr(g_wb_factor - 1 downto 0);
+ -- complex input
+ input_siso_arr : out t_dp_siso_arr(g_wb_factor - 1 downto 0) := (others => c_dp_siso_rdy);
- output_sosi_arr : out t_dp_sosi_arr(g_wb_factor - 1 downto 0); -- selected complex output with flow control
+ -- selected complex output with flow control
+ output_sosi_arr : out t_dp_sosi_arr(g_wb_factor - 1 downto 0);
output_siso_arr : in t_dp_siso_arr(g_wb_factor - 1 downto 0) := (others => c_dp_siso_rdy)
);
end ss_wide;
diff --git a/libraries/base/ss/tb/vhdl/tb_mmf_ss_reorder.vhd b/libraries/base/ss/tb/vhdl/tb_mmf_ss_reorder.vhd
index 589296951b02ebc8fc79201ed41eabf07e0ffd15..ad4172a86c8f7f6ef8d8563de89fae7ebf65b45b 100644
--- a/libraries/base/ss/tb/vhdl/tb_mmf_ss_reorder.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_mmf_ss_reorder.vhd
@@ -55,10 +55,14 @@ entity tb_mmf_ss_reorder is
g_nof_outputs : natural := 16;
g_dsp_data_w : natural := 16;
g_frame_size : natural := 16;
- g_ram_init_file : string := "../../../src/data/select_buf"; -- or "UNUSED"
- g_pipeline_in : natural := 1; -- pipeline in_data
- g_pipeline_in_m : natural := 1; -- pipeline in_data for M-fold fan out
- g_pipeline_out : natural := 1; -- pipeline out_data
+ -- or "UNUSED"
+ g_ram_init_file : string := "../../../src/data/select_buf";
+ -- pipeline in_data
+ g_pipeline_in : natural := 1;
+ -- pipeline in_data for M-fold fan out
+ g_pipeline_in_m : natural := 1;
+ -- pipeline out_data
+ g_pipeline_out : natural := 1;
g_nof_frames : natural := 1
);
end tb_mmf_ss_reorder;
diff --git a/libraries/base/ss/tb/vhdl/tb_ss.vhd b/libraries/base/ss/tb/vhdl/tb_ss.vhd
index 35585289e6e8b6bee6ccb558681014c2b88c800c..455f1f4fe863fbda08ed08086477d5bce23ae48f 100644
--- a/libraries/base/ss/tb/vhdl/tb_ss.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_ss.vhd
@@ -45,16 +45,19 @@ use dp_lib.tb_dp_pkg.all;
entity tb_ss is
generic (
-- Flow control
- g_mode_in_en : natural := 0; -- use 0 for active in_sosi.valid control
+ -- use 0 for active in_sosi.valid control
+ g_mode_in_en : natural := 0;
-- use 1 for random in_sosi.valid control
- g_mode_out_ready : natural := 0; -- use 0 for active out_siso.ready control
+ -- use 0 for active out_siso.ready control
+ g_mode_out_ready : natural := 0;
-- use 1 for toggling out_siso.ready control, requires g_nof_ch_sel <= g_nof_ch_in/2
-- use 2 for inverted toggling out_siso.ready control, requires g_nof_ch_sel <= g_nof_ch_in/2
-- Test duration
g_nof_sync : natural := 10;
-- Functional parameters
- g_reverse_ss_map : boolean := true; -- use true to verify that the last data written can be read immediately after the SS page swap
+ -- use true to verify that the last data written can be read immediately after the SS page swap
+ g_reverse_ss_map : boolean := true;
--g_nof_ch_in : NATURAL := 256;
g_nof_ch_in : natural := 16;
@@ -66,7 +69,8 @@ entity tb_ss is
g_use_complex : boolean := true;
- g_use_output_rl_adapter : boolean := false -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2
+ -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2
+ g_use_output_rl_adapter : boolean := false
);
end tb_ss;
@@ -89,7 +93,8 @@ architecture tb of tb_ss is
signal mm_dut_mosi : t_mem_mosi;
signal mm_done : std_logic;
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
signal toggle : std_logic := '1';
signal verify_en : std_logic := '0';
signal verify_bsn : std_logic := '1';
@@ -127,9 +132,11 @@ begin
for I in 0 to g_nof_ch_sel - 1 loop
if g_reverse_ss_map = false then
- proc_mem_mm_bus_wr(I, I, clk, mm_dut_mosi); -- Write the default SS map: (0, 1, 2, ... g_nof_ch_sel-1) ==> (0, 1, 2, ... g_nof_ch_sel-1)
+ -- Write the default SS map: (0, 1, 2, ... g_nof_ch_sel-1) ==> (0, 1, 2, ... g_nof_ch_sel-1)
+ proc_mem_mm_bus_wr(I, I, clk, mm_dut_mosi);
else
- proc_mem_mm_bus_wr(I, g_nof_ch_sel - 1 - I, clk, mm_dut_mosi); -- Write the reverse SS map: (0, 1, 2, ... g_nof_ch_sel-1) ==> (g_nof_ch_sel-1, ..., 2, 1, 0)
+ -- Write the reverse SS map: (0, 1, 2, ... g_nof_ch_sel-1) ==> (g_nof_ch_sel-1, ..., 2, 1, 0)
+ proc_mem_mm_bus_wr(I, g_nof_ch_sel - 1 - I, clk, mm_dut_mosi);
end if;
end loop;
mm_done <= '1';
@@ -166,20 +173,25 @@ begin
wait until rising_edge(clk);
for I in 0 to g_nof_sync - 1 loop
if g_use_complex then
- proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi);
v_re := v_re + g_nof_ch_in;
v_im := v_im + g_nof_ch_in;
else
- proc_dp_gen_block_data(c_rl, true, c_nof_complex * c_dsp_data_w, c_nof_complex * c_dsp_data_w, v_data, 0, 0, g_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, true, c_nof_complex * c_dsp_data_w, c_nof_complex * c_dsp_data_w, v_data, 0, 0, g_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi);
v_data := v_data + g_nof_ch_in;
end if;
- for J in 0 to c_nof_block_per_sync - 2 loop -- provide sop and eop for block reference
+ -- provide sop and eop for block reference
+ for J in 0 to c_nof_block_per_sync - 2 loop
if g_use_complex then
- proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi); -- no sync
+ -- no sync
+ proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi);
v_re := v_re + g_nof_ch_in;
v_im := v_im + g_nof_ch_in;
else
- proc_dp_gen_block_data(c_rl, true, c_nof_complex * c_dsp_data_w, c_nof_complex * c_dsp_data_w, v_data, 0, 0, g_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, true, c_nof_complex * c_dsp_data_w, c_nof_complex * c_dsp_data_w, v_data, 0, 0, g_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi);
v_data := v_data + g_nof_ch_in;
end if;
end loop;
@@ -211,7 +223,8 @@ begin
proc_common_wait_some_cycles(clk, 10);
for I in 0 to g_nof_ch_in - 1 loop
- proc_mem_mm_bus_wr(I, g_nof_ch_in - 1 - I, clk, mm_reverse_mosi); -- Write the reverse SS map: (0, 1, 2, ... g_nof_ch_in-1) ==> (g_nof_ch_in-1, ..., 2, 1, 0)
+ -- Write the reverse SS map: (0, 1, 2, ... g_nof_ch_in-1) ==> (g_nof_ch_in-1, ..., 2, 1, 0)
+ proc_mem_mm_bus_wr(I, g_nof_ch_in - 1 - I, clk, mm_reverse_mosi);
end loop;
wait;
@@ -279,8 +292,10 @@ begin
p_verify_en : process
begin
verify_en <= '0';
- proc_common_wait_until_high(clk, in_sosi.eop); -- now the SS will start outputing the first block
- proc_common_wait_some_cycles(clk, 10); -- wait a few cycles for the SS latency
+ -- now the SS will start outputing the first block
+ proc_common_wait_until_high(clk, in_sosi.eop);
+ -- wait a few cycles for the SS latency
+ proc_common_wait_some_cycles(clk, 10);
verify_en <= '1';
wait;
end process;
diff --git a/libraries/base/ss/tb/vhdl/tb_ss_wide.vhd b/libraries/base/ss/tb/vhdl/tb_ss_wide.vhd
index c4b8e4051dc6dbf08266de759cd7e96cd437d2f2..6ef96638f000189ed022c8ba2cacec9dfc907fd2 100644
--- a/libraries/base/ss/tb/vhdl/tb_ss_wide.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_ss_wide.vhd
@@ -87,7 +87,8 @@ begin
for J in 0 to c_wb_factor - 1 loop
for I in 0 to c_nof_ch_sel / c_wb_factor - 1 loop
- proc_mem_mm_bus_wr(J * c_adr_incr + I, I, clk, mm_mosi); -- Write the default SS map: (0, 1, 2, ... c_nof_ch_sel-1) ==> (0, 1, 2, ... c_nof_ch_sel-1)
+ -- Write the default SS map: (0, 1, 2, ... c_nof_ch_sel-1) ==> (0, 1, 2, ... c_nof_ch_sel-1)
+ proc_mem_mm_bus_wr(J * c_adr_incr + I, I, clk, mm_mosi);
end loop;
end loop;
mm_done <= '1';
@@ -110,11 +111,14 @@ begin
-- Run some sync intervals with DSP counter data for the real and imag fields
wait until rising_edge(clk);
for I in 0 to c_nof_sync - 1 loop
- proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K));
v_re := v_re + c_nof_ch_in;
v_im := v_im + c_nof_ch_in;
- for J in 0 to c_nof_block_per_sync - 2 loop -- provide sop and eop for block reference
- proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- no sync
+ -- provide sop and eop for block reference
+ for J in 0 to c_nof_block_per_sync - 2 loop
+ -- no sync
+ proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K));
v_re := v_re + c_nof_ch_in;
v_im := v_im + c_nof_ch_in;
end loop;
@@ -124,11 +128,14 @@ begin
-- Run some sync intervals more
wait until rising_edge(clk);
for I in 0 to c_nof_sync - 1 loop
- proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K));
v_re := v_re + c_nof_ch_in;
v_im := v_im + c_nof_ch_in;
- for J in 0 to c_nof_block_per_sync - 2 loop -- provide sop and eop for block reference
- proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- no sync
+ -- provide sop and eop for block reference
+ for J in 0 to c_nof_block_per_sync - 2 loop
+ -- no sync
+ proc_dp_gen_block_data(c_rl, false, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in / c_wb_factor, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K));
v_re := v_re + c_nof_ch_in;
v_im := v_im + c_nof_ch_in;
end loop;
@@ -140,7 +147,8 @@ begin
end generate;
-- Time stimuli
- bsn <= bsn + 1 when rising_edge(clk) and (st_sosi_arr(0).eop = '1'); -- OR st_sosi.sync='1');
+ -- OR st_sosi.sync='1');
+ bsn <= bsn + 1 when rising_edge(clk) and (st_sosi_arr(0).eop = '1');
-- Add BSN to the ST data
p_in_sosi : process(st_sosi_arr, bsn)
diff --git a/libraries/base/ss/tb/vhdl/tb_tb_ss.vhd b/libraries/base/ss/tb/vhdl/tb_tb_ss.vhd
index 48c9b93725957bcfbd6cc274e5754c8373e7e9a3..747ab60a2494f1248f7985a54c40175f237ea9d5 100644
--- a/libraries/base/ss/tb/vhdl/tb_tb_ss.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_tb_ss.vhd
@@ -28,7 +28,8 @@ end tb_tb_ss;
architecture tb of tb_tb_ss is
constant c_nof_sync : natural := 20;
constant c_reverse_ss_map : boolean := true;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 2
-- > run -all --> OK
diff --git a/libraries/base/tst/src/vhdl/tst_input.vhd b/libraries/base/tst/src/vhdl/tst_input.vhd
index fbfbf672293e49e9381930590c64268c1acea033..c4c16d6486199a968ada4ee8509ca9050eb7aed2 100644
--- a/libraries/base/tst/src/vhdl/tst_input.vhd
+++ b/libraries/base/tst/src/vhdl/tst_input.vhd
@@ -123,8 +123,10 @@ begin
file in_file : TEXT;
variable in_line : LINE;
variable num : integer;
- variable cycle_lno : integer; -- file line number
- variable cycle_rep : natural; -- read file g_file_repeat times
+ -- file line number
+ variable cycle_lno : integer;
+ -- read file g_file_repeat times
+ variable cycle_rep : natural;
variable cycle_state : STATE_TYPE;
variable nxt_cycle_state : STATE_TYPE;
diff --git a/libraries/base/uth/src/vhdl/uth_pkg.vhd b/libraries/base/uth/src/vhdl/uth_pkg.vhd
index fc4b0c498bee6fe6b7bba517c60bef2cc5f3f67a..ad3dee355abdefb6b025a69e15d312b0c4a738a9 100644
--- a/libraries/base/uth/src/vhdl/uth_pkg.vhd
+++ b/libraries/base/uth/src/vhdl/uth_pkg.vhd
@@ -31,17 +31,25 @@ use easics_lib.PCK_CRC64_D64.all;
package uth_pkg is
--<constants>--
constant c_uth_data_max_w : natural := 256;
- constant c_uth_crc64 : natural := 64; -- internally use CRC-8, 16, 32 or 64, use CRC-64 for data wider than 32 bits
- constant c_uth_nof_overhead : natural := 4; -- header: idle, sfd, tlen and tail: crc, so total 4 words frame overhead
- constant c_uth_gap_min : natural := c_uth_nof_overhead; -- minimal gap between valid data blocks (to be able to insert the frame overhead into the stream)
- constant c_uth_idle : std_logic_vector(c_uth_data_max_w - 1 downto 0) := c_slv1( c_uth_data_max_w - 1 downto 0); -- = 0xF..FFFF
- constant c_uth_preamble : std_logic_vector(c_uth_data_max_w - 1 downto 0) := c_slv10(c_uth_data_max_w - 1 downto 0); -- = 0xA..AAAA
- constant c_uth_sfd : std_logic_vector(c_uth_data_max_w - 1 downto 0) := c_slv10(c_uth_data_max_w - 1 downto 1) & '1'; -- = 0xA..AAAB
- constant c_uth_payload_min : natural := 1; -- an empty payload is not allowed because we need at least one data to signal sop and eop
+ -- internally use CRC-8, 16, 32 or 64, use CRC-64 for data wider than 32 bits
+ constant c_uth_crc64 : natural := 64;
+ -- header: idle, sfd, tlen and tail: crc, so total 4 words frame overhead
+ constant c_uth_nof_overhead : natural := 4;
+ -- minimal gap between valid data blocks (to be able to insert the frame overhead into the stream)
+ constant c_uth_gap_min : natural := c_uth_nof_overhead;
+ -- = 0xF..FFFF
+ constant c_uth_idle : std_logic_vector(c_uth_data_max_w - 1 downto 0) := c_slv1( c_uth_data_max_w - 1 downto 0);
+ -- = 0xA..AAAA
+ constant c_uth_preamble : std_logic_vector(c_uth_data_max_w - 1 downto 0) := c_slv10(c_uth_data_max_w - 1 downto 0);
+ -- = 0xA..AAAB
+ constant c_uth_sfd : std_logic_vector(c_uth_data_max_w - 1 downto 0) := c_slv10(c_uth_data_max_w - 1 downto 1) & '1';
+ -- an empty payload is not allowed because we need at least one data to signal sop and eop
+ constant c_uth_payload_min : natural := 1;
constant c_uth_crc_ok : natural := 0;
constant c_uth_crc_err : natural := 1;
- constant c_uth_crc_err_w : natural := 1; -- one bit CRC status field to fit c_uth_crc_ok=0 or c_uth_crc_err=1
+ -- one bit CRC status field to fit c_uth_crc_ok=0 or c_uth_crc_err=1
+ constant c_uth_crc_err_w : natural := 1;
--<types>--
@@ -82,10 +90,14 @@ package body uth_pkg is
-- Support CRC-8, 16, 32 and 64
case c_data_w is
when 0 => report "UTH data width must be >= 1" severity FAILURE;
- when 1 to 8 => v_crc_w := 8; -- use CRC-8
- when 9 to 16 => v_crc_w := 16; -- use CRC-16
- when 17 to 32 => v_crc_w := 32; -- use CRC-32
- when 33 to 255 => v_crc_w := 64 * c_nof_crc; -- for data wider than 33 use one or more CRC-64 in parallel (c_uth_crc64 = 64)
+ -- use CRC-8
+ when 1 to 8 => v_crc_w := 8;
+ -- use CRC-16
+ when 9 to 16 => v_crc_w := 16;
+ -- use CRC-32
+ when 17 to 32 => v_crc_w := 32;
+ -- for data wider than 33 use one or more CRC-64 in parallel (c_uth_crc64 = 64)
+ when 33 to 255 => v_crc_w := 64 * c_nof_crc;
when others => report "UTH data width must be <= c_uth_data_max_w = 256" severity FAILURE;
end case;
return v_crc_w;
@@ -103,10 +115,14 @@ package body uth_pkg is
begin
case c_data_w is
when 0 => report "UTH data width must be >= 1" severity FAILURE;
- when 1 to 8 => nxt_crc := nextCRC8_D8( RESIZE_UVEC(data, 8), crc); -- CRC-8 = ATM HEC, polynomial x^(0 1 2 8)
- when 9 to 16 => nxt_crc := nextCRC16_D16(RESIZE_UVEC(data, 16), crc); -- CRC-16 = USB DATA, polynomial x^(0 2 15 16)
- when 17 to 32 => nxt_crc := nextCRC32_D32(RESIZE_UVEC(data, 32), crc); -- CRC-32 = Ethernet, polynomial x^(0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
- when 33 to 255 => nxt_crc := func_uth_parallel_crc(data, crc); -- CRC-64 = EMCA-182, polynomial x^(0 1 4 7 9 10 12 13 17 19 21 22 23 24 27 29 31 32 33 35 37 38 39 40 45 46 47 52 53 54 55 57 62 64)
+ -- CRC-8 = ATM HEC, polynomial x^(0 1 2 8)
+ when 1 to 8 => nxt_crc := nextCRC8_D8( RESIZE_UVEC(data, 8), crc);
+ -- CRC-16 = USB DATA, polynomial x^(0 2 15 16)
+ when 9 to 16 => nxt_crc := nextCRC16_D16(RESIZE_UVEC(data, 16), crc);
+ -- CRC-32 = Ethernet, polynomial x^(0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
+ when 17 to 32 => nxt_crc := nextCRC32_D32(RESIZE_UVEC(data, 32), crc);
+ -- CRC-64 = EMCA-182, polynomial x^(0 1 4 7 9 10 12 13 17 19 21 22 23 24 27 29 31 32 33 35 37 38 39 40 45 46 47 52 53 54 55 57 62 64)
+ when 33 to 255 => nxt_crc := func_uth_parallel_crc(data, crc);
when others => report "UTH data width must be <= c_uth_data_max_w = 256" severity FAILURE;
end case;
return nxt_crc;
diff --git a/libraries/base/uth/src/vhdl/uth_rx.vhd b/libraries/base/uth/src/vhdl/uth_rx.vhd
index 6d186c500dcfc1e5d32953eb1f86a1e75de8b0fc..6dc788230ebe14572f3f03d9648ff836b43cbf14 100644
--- a/libraries/base/uth/src/vhdl/uth_rx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_rx.vhd
@@ -137,13 +137,20 @@ use work.uth_pkg.all;
entity uth_rx is
generic (
g_data_w : natural := c_uth_data_max_w;
- g_len_max : natural := 2**15 - 1; -- g_len_max defines the maximum nof data in the payload
- g_nof_ch : natural := 1; -- g_nof_ch, the channels are numbered from 0 TO g_nof_ch-1, each channel represents a type of UTH frame
- g_typ_arr : t_natural_arr := array_init(0, 1); -- g_nof_ch = g_typ_arr'LENGTH
- g_len_arr : t_natural_arr := array_init(1, 1); -- g_nof_ch = g_len_arr'LENGTH
- g_use_this_siso : boolean := true; -- default use TRUE for best throughput performance
- g_use_src_in : boolean := true; -- default use TRUE for src_in.ready flow control else use FALSE to avoid RL adapter when src_in.ready='1' fixed
- g_timeout_w : natural := 0 -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive snk_in.valid
+ -- g_len_max defines the maximum nof data in the payload
+ g_len_max : natural := 2**15 - 1;
+ -- g_nof_ch, the channels are numbered from 0 TO g_nof_ch-1, each channel represents a type of UTH frame
+ g_nof_ch : natural := 1;
+ -- g_nof_ch = g_typ_arr'LENGTH
+ g_typ_arr : t_natural_arr := array_init(0, 1);
+ -- g_nof_ch = g_len_arr'LENGTH
+ g_len_arr : t_natural_arr := array_init(1, 1);
+ -- default use TRUE for best throughput performance
+ g_use_this_siso : boolean := true;
+ -- default use TRUE for src_in.ready flow control else use FALSE to avoid RL adapter when src_in.ready='1' fixed
+ g_use_src_in : boolean := true;
+ -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive snk_in.valid
+ g_timeout_w : natural := 0
);
port (
rst : in std_logic;
@@ -175,14 +182,19 @@ architecture rtl_adapt of uth_rx is
procedure proc_handle_rx_timeout(signal valid : in std_logic;
signal timeout_evt : in std_logic;
signal clr : out std_logic;
- variable v_state : inout t_state) is -- use variable v_state instead of signal to avoid getting latches
+ -- use variable v_state instead of signal to avoid getting latches
+ variable v_state : inout t_state) is
begin
if valid = '1' then
- clr <= '1'; -- restart timeout_cnt during frame rx and remain in current state
+ -- restart timeout_cnt during frame rx and remain in current state
+ clr <= '1';
else
- clr <= '0'; -- let valid inactive timeout count increment
- if timeout_evt = '1' then -- can only occur when g_timeout_w>0
- v_state := s_flush; -- exit to flush state to finish the current rx frame with void data
+ -- let valid inactive timeout count increment
+ clr <= '0';
+ -- can only occur when g_timeout_w>0
+ if timeout_evt = '1' then
+ -- exit to flush state to finish the current rx frame with void data
+ v_state := s_flush;
end if;
end if;
end proc_handle_rx_timeout;
@@ -204,7 +216,8 @@ architecture rtl_adapt of uth_rx is
signal channel_hld : std_logic_vector(c_channel_w - 1 downto 0);
signal nxt_channel_hld : std_logic_vector(c_channel_w - 1 downto 0);
- signal cnt : natural range 0 to g_len_max + 1; -- payload data count
+ -- payload data count
+ signal cnt : natural range 0 to g_len_max + 1;
signal nxt_cnt : natural;
-- declare data field slv signals to ease debugging in wave window
@@ -235,11 +248,14 @@ begin
-- Input flow control
p_snk_out : process(src_in, this_siso)
begin
- snk_out <= src_in; -- default
+ -- default
+ snk_out <= src_in;
if g_use_this_siso = true then
- snk_out <= this_siso; -- better throughput
+ -- better throughput
+ snk_out <= this_siso;
end if;
- snk_out.xon <= '1'; -- force XON to sink, because uth_rx takes care of packet flush
+ -- force XON to sink, because uth_rx takes care of packet flush
+ snk_out.xon <= '1';
end process;
no_src_in : if g_use_src_in = false generate
@@ -249,7 +265,8 @@ begin
use_src_in : if g_use_src_in = true generate
u_rl_adapt : entity dp_lib.dp_latency_adapter
generic map (
- g_in_latency => 2, -- uth_rx does cause one cycle latency, so using dp_latency_adapter to fit current src_in.ready again (using dp_pipeline does not apply here)
+ -- uth_rx does cause one cycle latency, so using dp_latency_adapter to fit current src_in.ready again (using dp_pipeline does not apply here)
+ g_in_latency => 2,
g_out_latency => 1
)
port map (
@@ -306,13 +323,15 @@ begin
count => timeout_cnt
);
- timeout_evt <= timeout_cnt(g_timeout_w); -- check MSbit for timeout of 2**g_timeout_w clk cycles
+ -- check MSbit for timeout of 2**g_timeout_w clk cycles
+ timeout_evt <= timeout_cnt(g_timeout_w);
assert not(rising_edge(clk) and timeout_evt = '1') report "uth_rx(rtl_adapt) timeout occurred!" severity WARNING;
end generate;
-- XON/XOFF packet flow control
- nxt_xon <= src_in.xon; -- register src_in.xon to ease timing closure, because src_in.xon may come from far on the chip
+ -- register src_in.xon to ease timing closure, because src_in.xon may come from far on the chip
+ nxt_xon <= src_in.xon;
-- Hold snk_in
nxt_snk_in_hld <= snk_in when snk_in.valid = '1' else snk_in_hld;
@@ -338,7 +357,8 @@ begin
begin
nxt_crc <= crc;
if crc_init = '1' then
- nxt_crc <= (others => '1'); -- init crc
+ -- init crc
+ nxt_crc <= (others => '1');
elsif snk_in.valid = '1' then
nxt_crc <= func_uth_next_crc(snk_in.data(g_data_w - 1 downto 0), crc);
end if;
@@ -346,9 +366,11 @@ begin
-- State machine
p_state : process(state, timeout_evt, src_in, xon, crc, cnt, snk_in, snk_in_hld, nof_data, nof_data_hld, channel, channel_hld)
- variable v_nxt_state : t_state; -- use variable instead of signal to avoid getting latches with proc_handle_rx_timeout()
+ -- use variable instead of signal to avoid getting latches with proc_handle_rx_timeout()
+ variable v_nxt_state : t_state;
begin
- nxt_timeout_cnt_clr <= '1'; -- default no timeout_cnt
+ -- default no timeout_cnt
+ nxt_timeout_cnt_clr <= '1';
v_nxt_state := state;
this_siso <= src_in;
@@ -358,19 +380,23 @@ begin
nxt_nof_data_hld <= nof_data_hld;
nxt_channel_hld <= channel_hld;
- nxt_blk_sosi <= snk_in; -- default pass on input dat
+ -- default pass on input dat
+ nxt_blk_sosi <= snk_in;
nxt_blk_sosi.valid <= '0';
nxt_blk_sosi.sop <= '0';
nxt_blk_sosi.eop <= '0';
- nxt_blk_sosi.channel <= RESIZE_DP_CHANNEL(channel_hld); -- use channel derived from 'tlen' field
- nxt_blk_sosi.err <= c_crc_ok; -- default assume CRC will be OK
+ -- use channel derived from 'tlen' field
+ nxt_blk_sosi.channel <= RESIZE_DP_CHANNEL(channel_hld);
+ -- default assume CRC will be OK
+ nxt_blk_sosi.err <= c_crc_ok;
case state is
when s_sfd =>
this_siso <= c_dp_siso_rdy;
crc_init <= '1';
nxt_cnt <= 0;
- if snk_in.valid = '1' and xon = '1' then -- flush any input packet if src_in.xon is XOFF
+ -- flush any input packet if src_in.xon is XOFF
+ if snk_in.valid = '1' and xon = '1' then
if snk_in.data(g_data_w - 1 downto 0) = c_sfd and snk_in_hld.data(g_data_w - 1 downto 0) = c_preamble then
v_nxt_state := s_tlen;
end if;
@@ -380,13 +406,18 @@ begin
crc_init <= '1';
nxt_cnt <= 0;
if snk_in.valid = '1' then
- if unsigned(nof_data) = 0 then -- use nof_data derived combinatorially from 'tlen' field
- v_nxt_state := s_sfd; -- flush not supported UTH frame 'tlen'
+ -- use nof_data derived combinatorially from 'tlen' field
+ if unsigned(nof_data) = 0 then
+ -- flush not supported UTH frame 'tlen'
+ v_nxt_state := s_sfd;
else
- nxt_nof_data_hld <= nof_data; -- hold nof_data derived from 'tlen' field
- nxt_channel_hld <= channel; -- hold channel derived from 'tlen' field
+ -- hold nof_data derived from 'tlen' field
+ nxt_nof_data_hld <= nof_data;
+ -- hold channel derived from 'tlen' field
+ nxt_channel_hld <= channel;
this_siso <= src_in;
- if unsigned(nof_data) = 1 then -- use nof_data derived combinatorially from 'tlen' field
+ -- use nof_data derived combinatorially from 'tlen' field
+ if unsigned(nof_data) = 1 then
v_nxt_state := s_crc;
else
v_nxt_state := s_sop;
@@ -399,7 +430,8 @@ begin
if snk_in.valid = '1' then
nxt_blk_sosi.valid <= '1';
nxt_blk_sosi.sop <= '1';
- nxt_cnt <= cnt + 1; -- first payload data
+ -- first payload data
+ nxt_cnt <= cnt + 1;
if unsigned(nof_data_hld) = 2 then
v_nxt_state := s_crc;
else
@@ -411,7 +443,8 @@ begin
when s_data =>
if snk_in.valid = '1' then
nxt_blk_sosi.valid <= '1';
- nxt_cnt <= cnt + 1; -- count payload data
+ -- count payload data
+ nxt_cnt <= cnt + 1;
if cnt = unsigned(nof_data_hld) - 2 then
v_nxt_state := s_crc;
end if;
@@ -419,7 +452,8 @@ begin
-- Exit to s_flush in case of rx timeout
proc_handle_rx_timeout(snk_in.valid, timeout_evt, nxt_timeout_cnt_clr, v_nxt_state);
when s_crc =>
- if snk_in.valid = '1' then -- hold the last payload data and calculate the final crc
+ -- hold the last payload data and calculate the final crc
+ if snk_in.valid = '1' then
v_nxt_state := s_eop;
end if;
-- Exit to s_flush in case of rx timeout
@@ -428,12 +462,15 @@ begin
if snk_in.valid = '1' then
nxt_blk_sosi.data <= snk_in_hld.data;
nxt_blk_sosi.valid <= '1';
- nxt_cnt <= cnt + 1; -- output the last payload data
+ -- output the last payload data
+ nxt_cnt <= cnt + 1;
if unsigned(nof_data_hld) = 1 then
- nxt_blk_sosi.sop <= '1'; -- output sop in case the payload has only one data
+ -- output sop in case the payload has only one data
+ nxt_blk_sosi.sop <= '1';
end if;
nxt_blk_sosi.eop <= '1';
- if c_crc_w > g_data_w then -- set in SOSI error field based on final crc result
+ -- set in SOSI error field based on final crc result
+ if c_crc_w > g_data_w then
if snk_in.data(g_data_w - 1 downto 0) /= crc(g_data_w - 1 downto 0) then
nxt_blk_sosi.err <= c_crc_err;
end if;
@@ -442,18 +479,23 @@ begin
nxt_blk_sosi.err <= c_crc_err;
end if;
end if;
- this_siso <= c_dp_siso_rdy; -- force this_siso.ready='1', thanks to RL 2->1 we do not have to wait for active src_in.ready
+ -- force this_siso.ready='1', thanks to RL 2->1 we do not have to wait for active src_in.ready
+ this_siso <= c_dp_siso_rdy;
v_nxt_state := s_sfd;
end if;
-- Exit to s_flush in case of rx timeout
proc_handle_rx_timeout(snk_in.valid, timeout_evt, nxt_timeout_cnt_clr, v_nxt_state);
- when others => -- s_flush -- this state can only be reached if g_timeout_w>0
+ -- s_flush -- this state can only be reached if g_timeout_w>0
+ when others =>
if src_in.ready = '1' then
- nxt_blk_sosi.valid <= '1'; -- flush rx frame with void data
- nxt_cnt <= cnt + 1; -- count payload data
+ -- flush rx frame with void data
+ nxt_blk_sosi.valid <= '1';
+ -- count payload data
+ nxt_cnt <= cnt + 1;
if cnt >= unsigned(nof_data_hld) - 1 then
nxt_blk_sosi.eop <= '1';
- nxt_blk_sosi.err <= c_crc_err; -- fill in c_crc_err for flushed rx frame
+ -- fill in c_crc_err for flushed rx frame
+ nxt_blk_sosi.err <= c_crc_err;
v_nxt_state := s_sfd;
end if;
end if;
@@ -481,14 +523,19 @@ architecture rtl_hold of uth_rx is
procedure proc_handle_rx_timeout(signal valid : in std_logic;
signal timeout_evt : in std_logic;
signal clr : out std_logic;
- variable v_state : inout t_state) is -- use variable v_state instead of signal to avoid getting latches
+ -- use variable v_state instead of signal to avoid getting latches
+ variable v_state : inout t_state) is
begin
if valid = '1' then
- clr <= '1'; -- restart timeout_cnt during frame rx and remain in current state
+ -- restart timeout_cnt during frame rx and remain in current state
+ clr <= '1';
else
- clr <= '0'; -- let valid inactive timeout count increment
- if timeout_evt = '1' then -- can only occur when g_timeout_w>0
- v_state := s_flush; -- exit to flush state to finish the current rx frame with void data
+ -- let valid inactive timeout count increment
+ clr <= '0';
+ -- can only occur when g_timeout_w>0
+ if timeout_evt = '1' then
+ -- exit to flush state to finish the current rx frame with void data
+ v_state := s_flush;
end if;
end if;
end proc_handle_rx_timeout;
@@ -518,7 +565,8 @@ architecture rtl_hold of uth_rx is
signal channel_hld : std_logic_vector(c_channel_w - 1 downto 0);
signal nxt_channel_hld : std_logic_vector(c_channel_w - 1 downto 0);
- signal cnt : natural range 0 to g_len_max + 1; -- payload data count
+ -- payload data count
+ signal cnt : natural range 0 to g_len_max + 1;
signal nxt_cnt : natural;
signal this_siso : t_dp_siso;
@@ -547,11 +595,14 @@ begin
-- Input flow control
p_snk_out : process(src_in, this_siso)
begin
- snk_out <= src_in; -- default
+ -- default
+ snk_out <= src_in;
if g_use_this_siso = true then
- snk_out <= this_siso; -- better throughput
+ -- better throughput
+ snk_out <= this_siso;
end if;
- snk_out.xon <= '1'; -- force XON to sink, because uth_rx takes care of packet flush
+ -- force XON to sink, because uth_rx takes care of packet flush
+ snk_out.xon <= '1';
end process;
p_clk : process (clk, rst)
@@ -598,13 +649,15 @@ begin
count => timeout_cnt
);
- timeout_evt <= timeout_cnt(g_timeout_w); -- check MSbit for timeout of 2**g_timeout_w clk cycles
+ -- check MSbit for timeout of 2**g_timeout_w clk cycles
+ timeout_evt <= timeout_cnt(g_timeout_w);
assert not(rising_edge(clk) and timeout_evt = '1') report "uth_rx(rtl_hold) timeout occurred!" severity WARNING;
end generate;
-- XON/XOFF packet flow control
- nxt_xon <= src_in.xon; -- register src_in.xon to ease timing closure, because src_in.xon may come from far on the chip
+ -- register src_in.xon to ease timing closure, because src_in.xon may come from far on the chip
+ nxt_xon <= src_in.xon;
-- Hold input stream register
nxt_src_buf <= next_src_buf;
@@ -624,7 +677,8 @@ begin
);
-- Derive nof_data and channel number from tlen
- rx_tlen <= pend_src_buf.data(g_data_w - 1 downto 0); -- can use pend_src_buf instead of next_src_buf because no need to depend on this_siso
+ -- can use pend_src_buf instead of next_src_buf because no need to depend on this_siso
+ rx_tlen <= pend_src_buf.data(g_data_w - 1 downto 0);
u_rx_tlen : entity work.uth_rx_tlen
generic map (
@@ -644,7 +698,8 @@ begin
begin
nxt_crc <= crc;
if crc_init = '1' then
- nxt_crc <= (others => '1'); -- init crc
+ -- init crc
+ nxt_crc <= (others => '1');
elsif next_src_buf.valid = '1' then
nxt_crc <= func_uth_next_crc(next_src_buf.data(g_data_w - 1 downto 0), crc);
end if;
@@ -652,9 +707,11 @@ begin
-- State machine
p_state : process(state, timeout_evt, src_in, xon, i_src_out, crc, cnt, snk_in, next_src_buf, data_hld, nof_data, nof_data_hld, channel, channel_hld)
- variable v_nxt_state : t_state; -- use variable instead of signal to avoid getting latches with proc_handle_rx_timeout()
+ -- use variable instead of signal to avoid getting latches with proc_handle_rx_timeout()
+ variable v_nxt_state : t_state;
begin
- nxt_timeout_cnt_clr <= '1'; -- default no timeout_cnt
+ -- default no timeout_cnt
+ nxt_timeout_cnt_clr <= '1';
v_nxt_state := state;
this_siso <= src_in;
@@ -662,7 +719,8 @@ begin
crc_init <= '0';
nxt_cnt <= cnt;
- nxt_data_hld <= next_src_buf.data(g_data_w - 1 downto 0); -- default data_hld = src_buf
+ -- default data_hld = src_buf
+ nxt_data_hld <= next_src_buf.data(g_data_w - 1 downto 0);
nxt_nof_data_hld <= nof_data_hld;
nxt_channel_hld <= channel_hld;
@@ -670,8 +728,10 @@ begin
nxt_src_out.valid <= '0';
nxt_src_out.sop <= '0';
nxt_src_out.eop <= '0';
- nxt_src_out.channel <= RESIZE_DP_CHANNEL(channel_hld); -- use channel derived from 'tlen' field
- nxt_src_out.err <= c_crc_ok; -- default assume CRC will be OK
+ -- use channel derived from 'tlen' field
+ nxt_src_out.channel <= RESIZE_DP_CHANNEL(channel_hld);
+ -- default assume CRC will be OK
+ nxt_src_out.err <= c_crc_ok;
case state is
when s_sfd =>
@@ -680,7 +740,8 @@ begin
crc_init <= '1';
nxt_cnt <= 0;
-- For both the preamble and the sfd the valid must be active, between the preamble and the sfd there may occur invalid cycles
- if next_src_buf.valid = '1' and xon = '1' then -- flush any input packet if src_in.xon is XOFF
+ -- flush any input packet if src_in.xon is XOFF
+ if next_src_buf.valid = '1' and xon = '1' then
if next_src_buf.data(g_data_w - 1 downto 0) = c_sfd and data_hld(g_data_w - 1 downto 0) = c_preamble then
v_nxt_state := s_tlen;
end if;
@@ -691,13 +752,19 @@ begin
crc_init <= '1';
nxt_cnt <= 0;
if next_src_buf.valid = '1' then
- if unsigned(nof_data) = 0 then -- use nof_data derived combinatorially from 'tlen' field
- v_nxt_state := s_sfd; -- flush not supported UTH frame 'tlen'
+ -- use nof_data derived combinatorially from 'tlen' field
+ if unsigned(nof_data) = 0 then
+ -- flush not supported UTH frame 'tlen'
+ v_nxt_state := s_sfd;
else
- nxt_nof_data_hld <= nof_data; -- hold nof_data derived from 'tlen' field
- nxt_channel_hld <= channel; -- hold channel derived from 'tlen' field
- this_siso <= src_in; -- maintain active hold_src_in and now use the src_in for this_siso
- if unsigned(nof_data) = 1 then -- use nof_data derived combinatorially from 'tlen' field
+ -- hold nof_data derived from 'tlen' field
+ nxt_nof_data_hld <= nof_data;
+ -- hold channel derived from 'tlen' field
+ nxt_channel_hld <= channel;
+ -- maintain active hold_src_in and now use the src_in for this_siso
+ this_siso <= src_in;
+ -- use nof_data derived combinatorially from 'tlen' field
+ if unsigned(nof_data) = 1 then
v_nxt_state := s_crc;
else
v_nxt_state := s_sop;
@@ -711,7 +778,8 @@ begin
nxt_src_out.data <= next_src_buf.data;
nxt_src_out.valid <= '1';
nxt_src_out.sop <= '1';
- nxt_cnt <= cnt + 1; -- first payload data
+ -- first payload data
+ nxt_cnt <= cnt + 1;
if unsigned(nof_data_hld) = 2 then
v_nxt_state := s_crc;
else
@@ -724,7 +792,8 @@ begin
if next_src_buf.valid = '1' then
nxt_src_out.data <= next_src_buf.data;
nxt_src_out.valid <= '1';
- nxt_cnt <= cnt + 1; -- count payload data
+ -- count payload data
+ nxt_cnt <= cnt + 1;
if cnt = unsigned(nof_data_hld) - 2 then
v_nxt_state := s_crc;
end if;
@@ -732,7 +801,8 @@ begin
-- Exit to s_flush in case of rx timeout
proc_handle_rx_timeout(snk_in.valid, timeout_evt, nxt_timeout_cnt_clr, v_nxt_state);
when s_crc =>
- if next_src_buf.valid = '1' then -- last payload data and calculate the final crc
+ -- last payload data and calculate the final crc
+ if next_src_buf.valid = '1' then
v_nxt_state := s_eop;
end if;
-- Exit to s_flush in case of rx timeout
@@ -740,16 +810,21 @@ begin
when s_eop =>
-- We need data_hld to hold the snk_in.data and can not use src_buf for this, because src_buf will get the CRC value.
-- However if after the CRC the src_in.ready goes low then we can not output the data yet.
- nxt_data_hld <= data_hld; -- hold the last payload data
- if next_src_buf.valid = '1' then -- the payload crc
+ -- hold the last payload data
+ nxt_data_hld <= data_hld;
+ -- the payload crc
+ if next_src_buf.valid = '1' then
nxt_src_out.data <= RESIZE_DP_DATA(data_hld);
nxt_src_out.valid <= '1';
- nxt_cnt <= cnt + 1; -- output the last payload data
+ -- output the last payload data
+ nxt_cnt <= cnt + 1;
if unsigned(nof_data_hld) = 1 then
- nxt_src_out.sop <= '1'; -- output sop in case the payload has only one data
+ -- output sop in case the payload has only one data
+ nxt_src_out.sop <= '1';
end if;
nxt_src_out.eop <= '1';
- if c_crc_w > g_data_w then -- set in SOSI error field based on final crc result
+ -- set in SOSI error field based on final crc result
+ if c_crc_w > g_data_w then
if next_src_buf.data(g_data_w - 1 downto 0) /= crc(g_data_w - 1 downto 0) then
nxt_src_out.err <= c_crc_err;
end if;
@@ -758,17 +833,22 @@ begin
nxt_src_out.err <= c_crc_err;
end if;
end if;
- v_nxt_state := s_sfd; -- no need to force this_siso.ready='1', because it is already '1' due to active src_in.ready
+ -- no need to force this_siso.ready='1', because it is already '1' due to active src_in.ready
+ v_nxt_state := s_sfd;
end if;
-- Exit to s_flush in case of rx timeout
proc_handle_rx_timeout(snk_in.valid, timeout_evt, nxt_timeout_cnt_clr, v_nxt_state);
- when others => -- s_flush -- this state can only be reached if g_timeout_w>0
+ -- s_flush -- this state can only be reached if g_timeout_w>0
+ when others =>
if src_in.ready = '1' then
- nxt_src_out.valid <= '1'; -- flush rx frame with void data
- nxt_cnt <= cnt + 1; -- count payload data
+ -- flush rx frame with void data
+ nxt_src_out.valid <= '1';
+ -- count payload data
+ nxt_cnt <= cnt + 1;
if cnt >= unsigned(nof_data_hld) - 1 then
nxt_src_out.eop <= '1';
- nxt_src_out.err <= c_crc_err; -- fill in c_crc_err for flushed rx frame
+ -- fill in c_crc_err for flushed rx frame
+ nxt_src_out.err <= c_crc_err;
v_nxt_state := s_sfd;
end if;
end if;
diff --git a/libraries/base/uth/src/vhdl/uth_rx_tlen.vhd b/libraries/base/uth/src/vhdl/uth_rx_tlen.vhd
index 77a4beeb5a2f6fa2568319d0dd68514be46c2c24..34a488fa6933e2040514e9f688250c2d9a92638f 100644
--- a/libraries/base/uth/src/vhdl/uth_rx_tlen.vhd
+++ b/libraries/base/uth/src/vhdl/uth_rx_tlen.vhd
@@ -56,9 +56,12 @@ use work.uth_pkg.all;
entity uth_rx_tlen is
generic (
g_data_w : natural := c_uth_data_max_w;
- g_nof_ch : natural := 4; -- g_nof_ch, the channels are numbered from 0 TO g_nof_ch-1, each channel represents a type of UTH frame
- g_typ_arr : t_natural_arr := array_init(0, 4); -- g_nof_ch = g_typ_arr'LENGTH, use unconstraint type to allow generic g_nof_ch
- g_len_arr : t_natural_arr := array_init(1, 4) -- g_nof_ch = g_len_arr'LENGTH, use unconstraint type to allow generic g_nof_ch
+ -- g_nof_ch, the channels are numbered from 0 TO g_nof_ch-1, each channel represents a type of UTH frame
+ g_nof_ch : natural := 4;
+ -- g_nof_ch = g_typ_arr'LENGTH, use unconstraint type to allow generic g_nof_ch
+ g_typ_arr : t_natural_arr := array_init(0, 4);
+ -- g_nof_ch = g_len_arr'LENGTH, use unconstraint type to allow generic g_nof_ch
+ g_len_arr : t_natural_arr := array_init(1, 4)
);
port (
tlen : in std_logic_vector;
@@ -77,14 +80,20 @@ begin
begin
v_tlen := tlen(g_data_w - 1 downto 0);
- nof_data <= TO_UVEC(0, g_data_w); -- default use zero payload length to flush UTH frames other than those supported by the g_nof_ch
- channel <= TO_UVEC(0, channel'length); -- default channel value
+ -- default use zero payload length to flush UTH frames other than those supported by the g_nof_ch
+ nof_data <= TO_UVEC(0, g_data_w);
+ -- default channel value
+ channel <= TO_UVEC(0, channel'length);
for I in 0 to g_nof_ch - 1 loop
- if unsigned(v_tlen) = c_typ_arr(I) then -- search tlen in g_typ_arr
- nof_data <= TO_UVEC(c_len_arr(I), g_data_w); -- TLEN type match in g_typ_arr so use corresponding TLEN length from g_len_arr
- channel <= TO_UVEC(I, channel'length); -- and use the index I as channel number
- exit; -- there will be only one match, the first match is the match
+ -- search tlen in g_typ_arr
+ if unsigned(v_tlen) = c_typ_arr(I) then
+ -- TLEN type match in g_typ_arr so use corresponding TLEN length from g_len_arr
+ nof_data <= TO_UVEC(c_len_arr(I), g_data_w);
+ -- and use the index I as channel number
+ channel <= TO_UVEC(I, channel'length);
+ -- there will be only one match, the first match is the match
+ exit;
end if;
end loop;
end process;
diff --git a/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd b/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd
index 4db9301b8b012b64f2b7b03d1a4b2f5957c6129b..05fdb46d0e70520617834066be21a5c0fbd2d1c5 100644
--- a/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd
+++ b/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd
@@ -41,30 +41,43 @@ entity uth_terminal_bidir is
generic (
g_technology : natural := c_tech_select_default;
-- User
- g_usr_nof_streams : natural := 4; -- number of user streams per bus
- g_usr_use_complex : boolean := false; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ -- number of user streams per bus
+ g_usr_nof_streams : natural := 4;
+ -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ g_usr_use_complex : boolean := false;
g_usr_data_w : natural := 32;
g_usr_frame_len : natural := 20;
-- DP/UTH packet
- g_packet_data_w : natural := 32; -- packet data width for DP packet and for UTH packet, must be >= g_usr_data_w
+ -- packet data width for DP packet and for UTH packet, must be >= g_usr_data_w
+ g_packet_data_w : natural := 32;
-- Phy
- g_phy_nof_serial : natural := 4; -- up to 4 serial lanes per bus
+ -- up to 4 serial lanes per bus
+ g_phy_nof_serial : natural := 4;
-- Tx
g_use_tx : boolean := true;
- g_tx_input_use_fifo : boolean := true; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
- g_tx_input_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ g_tx_input_use_fifo : boolean := true;
+ -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ g_tx_input_fifo_size : natural := c_bram_m9k_fifo_depth;
g_tx_input_fifo_fill : natural := 0;
- g_tx_mux_mode : natural := 0; -- can use 0 for non-blocking tx mux in dp_distribute or use 1 to preserve input order for tx
+ -- can use 0 for non-blocking tx mux in dp_distribute or use 1 to preserve input order for tx
+ g_tx_mux_mode : natural := 0;
-- Rx
g_use_rx : boolean := true;
- g_rx_mux_mode : natural := 0; -- must use 0 for non-blocking rx mux in dp_distribute (can not use 1 to preserve input order for rx, because some rx frames may go lost)
- g_rx_output_use_fifo : boolean := true; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_output_fifo_size : natural := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ -- must use 0 for non-blocking rx mux in dp_distribute (can not use 1 to preserve input order for rx, because some rx frames may go lost)
+ g_rx_mux_mode : natural := 0;
+ -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_use_fifo : boolean := true;
+ -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ g_rx_output_fifo_size : natural := c_bram_m9k_fifo_depth;
g_rx_output_fifo_fill : natural := 0;
- g_rx_timeout_w : natural := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ g_rx_timeout_w : natural := 0;
-- UTH
- g_uth_len_max : natural := 255; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
- g_uth_typ_ofs : natural := 256 -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ g_uth_len_max : natural := 255;
+ -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ g_uth_typ_ofs : natural := 256
);
port (
dp_rst : in std_logic;
@@ -95,28 +108,42 @@ architecture str of uth_terminal_bidir is
constant c_dp_packet_len : natural := func_dp_packet_overhead_len(g_packet_data_w) + g_usr_frame_len;
constant c_uth_packet_len : natural := c_dp_packet_len + c_uth_nof_overhead;
- constant c_uth_nof_ch : natural := 1; -- support only one type of UTH frames
- constant c_use_uth_err : boolean := true; -- when TRUE insert the one bit CRC status from uth_rx in the received DP packet err field, else pass on the received DP packet err field unchanged
- constant c_uth_err_bi : natural := 0; -- bit index for where to insert the UTH err bit
+ -- support only one type of UTH frames
+ constant c_uth_nof_ch : natural := 1;
+ -- when TRUE insert the one bit CRC status from uth_rx in the received DP packet err field, else pass on the received DP packet err field unchanged
+ constant c_use_uth_err : boolean := true;
+ -- bit index for where to insert the UTH err bit
+ constant c_uth_err_bi : natural := 0;
-- Tx
- constant c_tx_input_use_empty : boolean := false; -- assume all words are full with symbols, so no need for empty
- constant c_tx_input_use_channel : boolean := false; -- support no multiplexed channels per DP input and only one kind of DP frame length per input, so no need for channel
- constant c_tx_input_use_error : boolean := false; -- No support (yet) for error field from usr input
- constant c_tx_input_empty_w : natural := c_dp_stream_empty_w; -- actual width will be: true_log2(nof symbols per data)
- constant c_tx_input_channel_w : natural := c_dp_stream_channel_w; -- actual width will be: true_log2(nof multiplexed channels per input) + true_log2(c_uth_nof_ch)
- constant c_tx_input_error_w : natural := c_dp_stream_error_w; -- actual width will be: e.g. c_unb_error_w
+ -- assume all words are full with symbols, so no need for empty
+ constant c_tx_input_use_empty : boolean := false;
+ -- support no multiplexed channels per DP input and only one kind of DP frame length per input, so no need for channel
+ constant c_tx_input_use_channel : boolean := false;
+ -- No support (yet) for error field from usr input
+ constant c_tx_input_use_error : boolean := false;
+ -- actual width will be: true_log2(nof symbols per data)
+ constant c_tx_input_empty_w : natural := c_dp_stream_empty_w;
+ -- actual width will be: true_log2(nof multiplexed channels per input) + true_log2(c_uth_nof_ch)
+ constant c_tx_input_channel_w : natural := c_dp_stream_channel_w;
+ -- actual width will be: e.g. c_unb_error_w
+ constant c_tx_input_error_w : natural := c_dp_stream_error_w;
constant c_tx_input_bsn_w : natural := c_dp_stream_bsn_w;
- constant c_tx_output_use_fifo : boolean := false; -- No need for Tx output FIFO because the SOSI and PHY (tr_nonbonded) serial outputs support passing on data valid
- constant c_tx_output_fifo_fill : natural := c_uth_packet_len; -- When used set the FIFO fill level to the size of one UTH packet
- constant c_tx_output_fifo_size : natural := ceil_div(c_tx_output_fifo_fill + c_fifo_afull_margin, c_bram_m9k_fifo_depth); -- Add margin for the FIFO size and fully use the BRAM blocks
+ -- No need for Tx output FIFO because the SOSI and PHY (tr_nonbonded) serial outputs support passing on data valid
+ constant c_tx_output_use_fifo : boolean := false;
+ -- When used set the FIFO fill level to the size of one UTH packet
+ constant c_tx_output_fifo_fill : natural := c_uth_packet_len;
+ -- Add margin for the FIFO size and fully use the BRAM blocks
+ constant c_tx_output_fifo_size : natural := ceil_div(c_tx_output_fifo_fill + c_fifo_afull_margin, c_bram_m9k_fifo_depth);
-- Rx
- constant c_rx_input_use_fifo : boolean := false; -- Note that mms_tr_nonbonded also already contains an clock-domain crossing FIFO for which the size can be set via c_rx_phy_fifo_size.
+ -- Note that mms_tr_nonbonded also already contains an clock-domain crossing FIFO for which the size can be set via c_rx_phy_fifo_size.
+ constant c_rx_input_use_fifo : boolean := false;
-- Furthermore typically Rx does not need slack because frame headers and tails are stripped.
constant c_rx_input_fifo_fill : natural := 0;
- constant c_rx_input_fifo_size : natural := c_bram_m9k_fifo_depth; -- choose to use full BRAM size = 256 for FIFO depth
+ -- choose to use full BRAM size = 256 for FIFO depth
+ constant c_rx_input_fifo_size : natural := c_bram_m9k_fifo_depth;
begin
gen_tx : if g_use_tx = true generate
u_uth_terminal_tx : entity work.uth_terminal_tx
@@ -140,11 +167,13 @@ begin
g_input_empty_w => c_tx_input_empty_w,
g_input_channel_w => c_tx_input_channel_w,
g_input_error_w => c_tx_input_error_w,
- g_input_use_bsn => true, -- support timing
+ -- support timing
+ g_input_use_bsn => true,
g_input_use_empty => c_tx_input_use_empty,
g_input_use_channel => c_tx_input_use_channel,
g_input_use_error => c_tx_input_use_error,
- g_input_use_sync => true, -- support timing
+ -- support timing
+ g_input_use_sync => true,
g_input_fifo_af_margin => c_fifo_afull_margin,
g_input_fifo_fill => g_tx_input_fifo_fill,
g_input_fifo_size => g_tx_input_fifo_size,
diff --git a/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd b/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
index e31b47462351dcb0c20f5fcf3ab81e1edb9012b4..5742c51ceccbf7ef6f43997fc5813d16d7f1506e 100644
--- a/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
@@ -51,30 +51,46 @@ entity uth_terminal_rx is
generic (
g_technology : natural := c_tech_select_default;
-- Terminal IO
- g_nof_input : natural := 4; -- >= 1
- g_nof_output : natural := 3; -- >= 1
- g_mux_mode : natural := 0; -- default use 0 for non-blocking mux in dp_distribute, use 1 to preserve input order
+ -- >= 1
+ g_nof_input : natural := 4;
+ -- >= 1
+ g_nof_output : natural := 3;
+ -- default use 0 for non-blocking mux in dp_distribute, use 1 to preserve input order
+ g_mux_mode : natural := 0;
-- . DP Packet
- g_data_w : natural := 32; -- DP data width
- g_packet_data_w : natural := 32; -- DP packet data width, must be >= g_data_w, same width is also used for the Uthernet packet data (fixed packing ratio 1/1)
+ -- DP data width
+ g_data_w : natural := 32;
+ -- DP packet data width, must be >= g_data_w, same width is also used for the Uthernet packet data (fixed packing ratio 1/1)
+ g_packet_data_w : natural := 32;
-- . Uthernet
- g_uth_nof_ch : natural := 2; -- selects UTH TLEN based on the snk_in channel_lo part that is not in the DP Packet CHAN field
- g_uth_len_max : natural := 255; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
- g_uth_typ_arr : t_natural_arr := array_init(256, 2, 1); -- = (256, 257), array length must match g_uth_nof_ch
- g_uth_len_arr : t_natural_arr := array_init(256, 10); -- = (10, 10), array length must match g_uth_nof_ch
- g_use_uth_err : boolean := true; -- when TRUE insert the one bit CRC status from uth_rx in the received DP packet err field, else pass on the received DP packet err field unchanged
- g_uth_err_bi : natural := 0; -- bit index for where to insert the UTH err bit
- g_uth_timeout_w : natural := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ -- selects UTH TLEN based on the snk_in channel_lo part that is not in the DP Packet CHAN field
+ g_uth_nof_ch : natural := 2;
+ -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ g_uth_len_max : natural := 255;
+ -- = (256, 257), array length must match g_uth_nof_ch
+ g_uth_typ_arr : t_natural_arr := array_init(256, 2, 1);
+ -- = (10, 10), array length must match g_uth_nof_ch
+ g_uth_len_arr : t_natural_arr := array_init(256, 10);
+ -- when TRUE insert the one bit CRC status from uth_rx in the received DP packet err field, else pass on the received DP packet err field unchanged
+ g_use_uth_err : boolean := true;
+ -- bit index for where to insert the UTH err bit
+ g_uth_err_bi : natural := 0;
+ -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ g_uth_timeout_w : natural := 0;
-- Input FIFO passes DP/Uthernet packets
g_input_use_fifo : boolean := false;
- g_input_fifo_af_margin : natural := c_fifo_afull_margin; -- = 4, nof words below max (full) at which fifo is considered almost full
+ -- = 4, nof words below max (full) at which fifo is considered almost full
+ g_input_fifo_af_margin : natural := c_fifo_afull_margin;
g_input_fifo_fill : natural := 0;
- g_input_fifo_size : natural := c_bram_m9k_fifo_depth; -- = 256
+ -- = 256
+ g_input_fifo_size : natural := c_bram_m9k_fifo_depth;
-- Output FIFO passes DP packets (because the dp_packet_dec to get src_out_arr is placed after the output FIFO)
g_output_use_fifo : boolean := false;
- g_output_fifo_af_margin : natural := c_fifo_afull_margin; -- = 4, nof words below max (full) at which fifo is considered almost full
+ -- = 4, nof words below max (full) at which fifo is considered almost full
+ g_output_fifo_af_margin : natural := c_fifo_afull_margin;
g_output_fifo_fill : natural := 0;
- g_output_fifo_size : natural := c_bram_m9k_fifo_depth -- = 256
+ -- = 256
+ g_output_fifo_size : natural := c_bram_m9k_fifo_depth
);
port (
rst : in std_logic;
@@ -94,7 +110,8 @@ end uth_terminal_rx;
architecture str of uth_terminal_rx is
constant c_packet_channel_lo : natural := true_log2(g_uth_nof_ch);
- constant c_complex_w : natural := g_data_w / 2; -- DP complex data width of Im, Re packet as Im & Re in g_data_w
+ -- DP complex data width of Im, Re packet as Im & Re in g_data_w
+ constant c_complex_w : natural := g_data_w / 2;
signal in_siso_arr : t_dp_siso_arr(g_nof_input - 1 downto 0);
signal in_sosi_arr : t_dp_sosi_arr(g_nof_input - 1 downto 0);
@@ -151,15 +168,18 @@ begin
gen_input : for I in g_nof_input - 1 downto 0 generate
--u_uth_rx : ENTITY work.uth_rx(rtl_adapt) -- requires using g_fifo_af_margin >= 10
- u_uth_rx : entity work.uth_rx(rtl_hold) -- can use default g_fifo_af_margin >= 4
+ -- can use default g_fifo_af_margin >= 4
+ u_uth_rx : entity work.uth_rx(rtl_hold)
generic map (
g_data_w => g_packet_data_w,
g_len_max => g_uth_len_max,
g_nof_ch => g_uth_nof_ch,
g_typ_arr => g_uth_typ_arr,
g_len_arr => g_uth_len_arr,
- g_use_this_siso => true, -- default use TRUE for best throughput performance
- g_use_src_in => true, -- default use TRUE for src_in.ready flow control else use FALSE to avoid RL adapter when src_in.ready='1' fixed
+ -- default use TRUE for best throughput performance
+ g_use_this_siso => true,
+ -- default use TRUE for src_in.ready flow control else use FALSE to avoid RL adapter when src_in.ready='1' fixed
+ g_use_src_in => true,
g_timeout_w => g_uth_timeout_w
)
port map (
@@ -189,7 +209,8 @@ begin
g_code_channel_lo => true,
g_data_w => g_packet_data_w,
-- Scheduling
- g_rx_mux_mode => g_mux_mode, -- default 0 for non-blocking mux, but 1 also works in simulation and on hardware provided that the inputs are garantueed to arrive
+ -- default 0 for non-blocking mux, but 1 also works in simulation and on hardware provided that the inputs are garantueed to arrive
+ g_rx_mux_mode => g_mux_mode,
-- Input FIFO
g_use_fifo => false
)
@@ -221,9 +242,11 @@ begin
generic map (
g_technology => g_technology,
g_data_w => g_packet_data_w,
- g_error_w => c_uth_crc_err_w, -- = 1, one bit CRC error status from uth_rx
+ -- = 1, one bit CRC error status from uth_rx
+ g_error_w => c_uth_crc_err_w,
g_use_error => g_use_uth_err,
- g_use_channel => false, -- FALSE because c_packet_channel_lo is coded in the CHAN field of the DP packet data
+ -- FALSE because c_packet_channel_lo is coded in the CHAN field of the DP packet data
+ g_use_channel => false,
g_fifo_fill => g_output_fifo_fill,
g_fifo_af_margin => g_output_fifo_af_margin,
g_fifo_size => g_output_fifo_size,
@@ -253,7 +276,8 @@ begin
g_channel_lo => c_packet_channel_lo,
g_phy_err_bi => g_uth_err_bi,
g_use_phy_err => g_use_uth_err,
- g_use_this_siso => true -- default use TRUE for best throughput performance
+ -- default use TRUE for best throughput performance
+ g_use_this_siso => true
)
port map (
rst => rst,
diff --git a/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd b/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
index 9b177da33e6bae32d68d6417fea65010e75a15b3..f5bb9ac00078f2587ad0b6f5e28599782254f82a 100644
--- a/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
@@ -49,17 +49,26 @@ entity uth_terminal_tx is
generic (
g_technology : natural := c_tech_select_default;
-- Terminal IO
- g_nof_input : natural := 4; -- >= 1
- g_nof_output : natural := 3; -- >= 1
- g_mux_mode : natural := 0; -- default use 0 for non-blocking mux in dp_distribute, use 1 to preserve input order
+ -- >= 1
+ g_nof_input : natural := 4;
+ -- >= 1
+ g_nof_output : natural := 3;
+ -- default use 0 for non-blocking mux in dp_distribute, use 1 to preserve input order
+ g_mux_mode : natural := 0;
-- . DP Packet
- g_use_complex : boolean := false; -- when TRUE transport snk_in_arr im & re via DP data, else transport snk_in_arr data via DP data
- g_data_w : natural := 32; -- DP data width
- g_packet_data_w : natural := 32; -- DP packet data width, must be >= g_data_w, same width is also used for the Uthernet packet data (fixed packing ratio 1/1)
+ -- when TRUE transport snk_in_arr im & re via DP data, else transport snk_in_arr data via DP data
+ g_use_complex : boolean := false;
+ -- DP data width
+ g_data_w : natural := 32;
+ -- DP packet data width, must be >= g_data_w, same width is also used for the Uthernet packet data (fixed packing ratio 1/1)
+ g_packet_data_w : natural := 32;
-- . Uthernet
- g_uth_nof_ch : natural := 2; -- selects UTH TLEN based on the snk_in channel_lo part that is not in the DP Packet CHAN field
- g_uth_typ_ofs : natural := 256; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
- g_uth_typ_arr : t_natural_arr := array_init(256, 2, 1); -- = (256, 257), array length must match g_uth_nof_ch
+ -- selects UTH TLEN based on the snk_in channel_lo part that is not in the DP Packet CHAN field
+ g_uth_nof_ch : natural := 2;
+ -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ g_uth_typ_ofs : natural := 256;
+ -- = (256, 257), array length must match g_uth_nof_ch
+ g_uth_typ_arr : t_natural_arr := array_init(256, 2, 1);
-- Input FIFO passes DP sosi data
g_input_use_fifo : boolean := false;
g_input_bsn_w : natural := 1;
@@ -71,14 +80,18 @@ entity uth_terminal_tx is
g_input_use_channel : boolean := false;
g_input_use_error : boolean := false;
g_input_use_sync : boolean := false;
- g_input_fifo_af_margin : natural := c_fifo_afull_margin; -- = 4, nof words below max (full) at which fifo is considered almost full
+ -- = 4, nof words below max (full) at which fifo is considered almost full
+ g_input_fifo_af_margin : natural := c_fifo_afull_margin;
g_input_fifo_fill : natural := 0;
- g_input_fifo_size : natural := c_bram_m9k_fifo_depth; -- = 256
+ -- = 256
+ g_input_fifo_size : natural := c_bram_m9k_fifo_depth;
-- Output FIFO passes DP/Uthernet packets
g_output_use_fifo : boolean := false;
- g_output_fifo_af_margin : natural := c_fifo_afull_margin; -- = 4, nof words below max (full) at which fifo is considered almost full
+ -- = 4, nof words below max (full) at which fifo is considered almost full
+ g_output_fifo_af_margin : natural := c_fifo_afull_margin;
g_output_fifo_fill : natural := 0;
- g_output_fifo_size : natural := c_bram_m9k_fifo_depth -- = 256
+ -- = 256
+ g_output_fifo_size : natural := c_bram_m9k_fifo_depth
);
port (
rst : in std_logic;
@@ -199,7 +212,8 @@ begin
g_code_channel_lo => true,
g_data_w => g_packet_data_w,
-- Scheduling
- g_tx_mux_mode => g_mux_mode, -- default 0 for non-blocking mux, but 1 also works in simulation and on hardware provided that the inputs are garantueed to arrive
+ -- default 0 for non-blocking mux, but 1 also works in simulation and on hardware provided that the inputs are garantueed to arrive
+ g_tx_mux_mode => g_mux_mode,
-- Input FIFO
g_use_fifo => false
)
@@ -219,11 +233,14 @@ begin
------------------------------------------------------------------------------
gen_output : for I in g_nof_output - 1 downto 0 generate
--u_uth_tx : ENTITY work.uth_tx(rtl_delay) -- requires using g_fifo_af_margin >= 10
- u_uth_tx : entity work.uth_tx(rtl_hold) -- can use default g_fifo_af_margin >= 4
+ -- can use default g_fifo_af_margin >= 4
+ u_uth_tx : entity work.uth_tx(rtl_hold)
generic map (
g_data_w => g_packet_data_w,
- g_nof_ch => g_uth_nof_ch, -- g_nof_ch, the channels are numbered from 0 TO g_nof_ch-1, each channel represents a type of UTH frame
- g_typ_arr => g_uth_typ_arr -- g_nof_ch number of TLEN type values indexed by sink input channel, use unconstraint type to allow generic g_nof_ch
+ -- g_nof_ch, the channels are numbered from 0 TO g_nof_ch-1, each channel represents a type of UTH frame
+ g_nof_ch => g_uth_nof_ch,
+ -- g_nof_ch number of TLEN type values indexed by sink input channel, use unconstraint type to allow generic g_nof_ch
+ g_typ_arr => g_uth_typ_arr
)
port map (
rst => rst,
diff --git a/libraries/base/uth/src/vhdl/uth_tx.vhd b/libraries/base/uth/src/vhdl/uth_tx.vhd
index e06f41ba99b32a6f1b4d865e35133a8c8b2cedd2..867f3327b5f10f8377dd6ffe17de9e7007c1277e 100644
--- a/libraries/base/uth/src/vhdl/uth_tx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_tx.vhd
@@ -125,9 +125,12 @@ use work.uth_pkg.all;
entity uth_tx is
generic (
g_data_w : natural := c_uth_data_max_w;
- g_nof_ch : natural := 1; -- g_nof_ch, the channels are numbered from 0 TO g_nof_ch-1, each channel represents a type of UTH frame
- g_typ_arr : t_natural_arr := array_init(0, 1); -- g_nof_ch number of TLEN type values indexed by sink input channel, use unconstraint type to allow generic g_nof_ch
- g_out_rl : natural := 6 -- maximum output ready latency, not used by rtl_hold, only applies to rtl_delay
+ -- g_nof_ch, the channels are numbered from 0 TO g_nof_ch-1, each channel represents a type of UTH frame
+ g_nof_ch : natural := 1;
+ -- g_nof_ch number of TLEN type values indexed by sink input channel, use unconstraint type to allow generic g_nof_ch
+ g_typ_arr : t_natural_arr := array_init(0, 1);
+ -- maximum output ready latency, not used by rtl_hold, only applies to rtl_delay
+ g_out_rl : natural := 6
);
port (
rst : in std_logic;
@@ -146,12 +149,14 @@ architecture rtl_delay of uth_tx is
constant c_preamble : std_logic_vector := RESIZE_DP_DATA(c_uth_preamble);
constant c_sfd : std_logic_vector := RESIZE_DP_DATA(c_uth_sfd);
- constant c_channel_w : natural := ceil_log2(g_nof_ch); -- could use true_log2, but instead use extra check on g_nof_ch=1 to force channel = 0 then, to avoid null-range (-1 DOWNTO 0) warnings.
+ -- could use true_log2, but instead use extra check on g_nof_ch=1 to force channel = 0 then, to avoid null-range (-1 DOWNTO 0) warnings.
+ constant c_channel_w : natural := ceil_log2(g_nof_ch);
-- Map input t_natural_arr range to range 0 TO g_nof_ch-1
constant c_typ_arr : t_natural_arr(0 to g_nof_ch - 1) := g_typ_arr;
- constant c_latency : natural := 1; -- Extra latency due to that the p_frame outputs when valid='1', ignoring out_ready
+ -- Extra latency due to that the p_frame outputs when valid='1', ignoring out_ready
+ constant c_latency : natural := 1;
-- This 'rtl_delay' does not adhere to out_ready. Assume that the upstream
-- device does adhere to RL = 1, then this 'rtl_delay' causes the output RL
@@ -194,7 +199,8 @@ architecture rtl_delay of uth_tx is
signal frm_sop : std_logic;
signal frm_eop : std_logic;
begin
- snk_in_dly(0) <= snk_in; -- put combinatorial at index [0]
+ -- put combinatorial at index [0]
+ snk_in_dly(0) <= snk_in;
src_out <= adapt_sosi;
@@ -232,9 +238,11 @@ begin
end if;
-- set default nxt_out_dat
- nxt_frm_sosi.data <= snk_in_dly(3).data; -- pass on input data
+ -- pass on input data
+ nxt_frm_sosi.data <= snk_in_dly(3).data;
if data_busy = '0' then
- nxt_frm_sosi.data <= c_idle; -- force idle data output between frames
+ -- force idle data output between frames
+ nxt_frm_sosi.data <= c_idle;
end if;
nxt_frm_sosi.valid <= snk_in_dly(3).valid;
nxt_frm_sosi.sop <= '0';
@@ -245,25 +253,36 @@ begin
-- overrule default nxt_crc, nxt_out_dat
if snk_in_dly(0).sop = '1' then
- nxt_crc <= (others => '1'); -- init crc
- nxt_frm_sosi.data <= c_preamble; -- prepend preamble word
+ -- init crc
+ nxt_crc <= (others => '1');
+ -- prepend preamble word
+ nxt_frm_sosi.data <= c_preamble;
nxt_frm_sosi.valid <= '1';
- nxt_frm_sosi.sop <= '1'; -- output sop
+ -- output sop
+ nxt_frm_sosi.sop <= '1';
elsif snk_in_dly(1).sop = '1' then
- nxt_crc <= (others => '1'); -- init crc
- nxt_frm_sosi.data <= c_sfd; -- prepend sfd word
+ -- init crc
+ nxt_crc <= (others => '1');
+ -- prepend sfd word
+ nxt_frm_sosi.data <= c_sfd;
nxt_frm_sosi.valid <= '1';
elsif snk_in_dly(2).sop = '1' then
- nxt_crc <= (others => '1'); -- init crc
- nxt_frm_sosi.data <= RESIZE_DP_DATA(tx_tlen); -- prepend tlen word
+ -- init crc
+ nxt_crc <= (others => '1');
+ -- prepend tlen word
+ nxt_frm_sosi.data <= RESIZE_DP_DATA(tx_tlen);
nxt_frm_sosi.valid <= '1';
- nxt_data_busy <= '1'; -- next snk_in_dly(3).valid marks first data
+ -- next snk_in_dly(3).valid marks first data
+ nxt_data_busy <= '1';
elsif snk_in_dly(3).eop = '1' then
- nxt_data_busy <= '0'; -- this snk_in_dly(3).valid marks last data
+ -- this snk_in_dly(3).valid marks last data
+ nxt_data_busy <= '0';
elsif snk_in_dly(4).eop = '1' then
- nxt_frm_sosi.data <= RESIZE_DP_DATA(crc); -- append calculated tx crc
+ -- append calculated tx crc
+ nxt_frm_sosi.data <= RESIZE_DP_DATA(crc);
nxt_frm_sosi.valid <= '1';
- nxt_frm_sosi.eop <= '1'; -- output eop
+ -- output eop
+ nxt_frm_sosi.eop <= '1';
end if;
end process;
@@ -278,8 +297,10 @@ begin
generic map (
g_rst_level => '1',
g_priority_lo => false,
- g_or_high => true, -- combinatorially force out_level high
- g_and_low => true -- combinatorially force out_level low
+ -- combinatorially force out_level high
+ g_or_high => true,
+ -- combinatorially force out_level low
+ g_and_low => true
)
port map (
rst => rst,
@@ -311,7 +332,8 @@ architecture rtl_hold of uth_tx is
constant c_preamble : std_logic_vector := RESIZE_DP_DATA(c_uth_preamble);
constant c_sfd : std_logic_vector := RESIZE_DP_DATA(c_uth_sfd);
- constant c_channel_w : natural := ceil_log2(g_nof_ch); -- could use true_log2, but instead use extra check on g_nof_ch=1 to force channel = 0 then, to avoid null-range (-1 DOWNTO 0) warnings.
+ -- could use true_log2, but instead use extra check on g_nof_ch=1 to force channel = 0 then, to avoid null-range (-1 DOWNTO 0) warnings.
+ constant c_channel_w : natural := ceil_log2(g_nof_ch);
-- Map input t_natural_arr range to range 0 TO g_nof_ch-1
constant c_typ_arr : t_natural_arr(0 to g_nof_ch - 1) := g_typ_arr;
@@ -346,7 +368,8 @@ begin
if rst = '1' then
crc <= (others => '1');
src_buf <= c_dp_sosi_rst;
- i_src_out <= c_dp_sosi_rst; -- default output zero data after reset
+ -- default output zero data after reset
+ i_src_out <= c_dp_sosi_rst;
state <= s_idle;
elsif rising_edge(clk) then
crc <= nxt_crc;
@@ -382,7 +405,8 @@ begin
begin
nxt_crc <= crc;
if crc_init = '1' then
- nxt_crc <= (others => '1'); -- init crc
+ -- init crc
+ nxt_crc <= (others => '1');
elsif next_src_buf.valid = '1' then
nxt_crc <= func_uth_next_crc(next_src_buf.data(g_data_w - 1 downto 0), crc);
end if;
@@ -406,9 +430,11 @@ begin
case state is
when s_idle =>
crc_init <= '1';
- snk_out.ready <= not pend_src_buf.sop; -- flush until sop
+ -- flush until sop
+ snk_out.ready <= not pend_src_buf.sop;
hold_src_in.ready <= '0';
- nxt_src_out.data <= c_idle; -- default force idle data output between frames
+ -- default force idle data output between frames
+ nxt_src_out.data <= c_idle;
if src_in.ready = '1' then
if pend_src_buf.sop = '1' then
nxt_src_out.data <= c_preamble;
@@ -443,8 +469,10 @@ begin
nxt_state <= s_crc;
end if;
end if;
- when others => -- s_crc
- snk_out.ready <= not pend_src_buf.sop; -- flush until next sop
+ -- s_crc
+ when others =>
+ -- flush until next sop
+ snk_out.ready <= not pend_src_buf.sop;
hold_src_in.ready <= '0';
if src_in.ready = '1' then
nxt_src_out.data <= RESIZE_DP_DATA(crc);
diff --git a/libraries/base/uth/src/vhdl/uth_tx_tlen.vhd b/libraries/base/uth/src/vhdl/uth_tx_tlen.vhd
index dfdd04816a2dc4c4bfb1e1b42fb6a69eaf1ffc96..3dea12f025b66d99679bcdd043f26537903663dc 100644
--- a/libraries/base/uth/src/vhdl/uth_tx_tlen.vhd
+++ b/libraries/base/uth/src/vhdl/uth_tx_tlen.vhd
@@ -57,10 +57,14 @@ use work.uth_pkg.all;
entity uth_tx_tlen is
generic (
g_data_w : natural := c_uth_data_max_w;
- g_len_max : natural := 2**15 - 1; -- g_len_max must be < 2**(g_data_w-1), because Msbit of tlen indicates type when '1' and length when '0'
- g_nof_ch : natural := 4; -- g_nof_ch, the channels are numbered from 0 TO g_nof_ch-1, each channel represents a type of UTH frame
- g_typ_arr : t_natural_arr := array_init(0, 4); -- g_nof_ch = g_typ_arr'LENGTH, use unconstraint type to allow generic g_nof_ch
- g_len_arr : t_natural_arr := array_init(1, 4) -- g_nof_ch = g_len_arr'LENGTH, use unconstraint type to allow generic g_nof_ch
+ -- g_len_max must be < 2**(g_data_w-1), because Msbit of tlen indicates type when '1' and length when '0'
+ g_len_max : natural := 2**15 - 1;
+ -- g_nof_ch, the channels are numbered from 0 TO g_nof_ch-1, each channel represents a type of UTH frame
+ g_nof_ch : natural := 4;
+ -- g_nof_ch = g_typ_arr'LENGTH, use unconstraint type to allow generic g_nof_ch
+ g_typ_arr : t_natural_arr := array_init(0, 4);
+ -- g_nof_ch = g_len_arr'LENGTH, use unconstraint type to allow generic g_nof_ch
+ g_len_arr : t_natural_arr := array_init(1, 4)
);
port (
channel : in std_logic_vector;
@@ -82,12 +86,14 @@ begin
variable v_ch : natural;
variable v_tlen : std_logic_vector(g_data_w - 1 downto 0);
begin
- v_ch := 0; -- If g_nof_ch=1 then it is not necessary to use the channel input
+ -- If g_nof_ch=1 then it is not necessary to use the channel input
+ v_ch := 0;
if g_nof_ch > 1 then
v_ch := TO_UINT(channel);
end if;
- v_tlen := TO_UVEC(c_len_arr(v_ch), g_data_w); -- values in c_len_arr must be <= g_len_max
+ -- values in c_len_arr must be <= g_len_max
+ v_tlen := TO_UVEC(c_len_arr(v_ch), g_data_w);
if c_typ_arr(v_ch) > g_len_max then
v_tlen := TO_UVEC(c_typ_arr(v_ch), g_data_w);
end if;
diff --git a/libraries/base/uth/tb/vhdl/tb_tb_uth.vhd b/libraries/base/uth/tb/vhdl/tb_tb_uth.vhd
index 587b343f217a35806e986a8f2274273c895e90e6..81459cf9614b3e4e580fe2ff50eca469bfaaf668 100644
--- a/libraries/base/uth/tb/vhdl/tb_tb_uth.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_tb_uth.vhd
@@ -33,7 +33,8 @@ end tb_tb_uth;
architecture tb of tb_tb_uth is
constant c_phy_link_valid_support : boolean := true;
constant c_nof_repeat : natural := 10;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- in_en = active, src_in.ready = active
u_hold_adapt_act_act : entity work.tb_uth generic map ( "HOLD", "ADAPT", c_phy_link_valid_support, e_active, e_active, c_nof_repeat);
@@ -68,6 +69,8 @@ begin
-- in_en = pulse, src_in.ready = pulse
u_hold_adapt_pls_pls : entity work.tb_uth generic map ( "HOLD", "ADAPT", c_phy_link_valid_support, e_pulse, e_pulse, c_nof_repeat);
u_hold_hold_pls_pls : entity work.tb_uth generic map ( "HOLD", "HOLD", c_phy_link_valid_support, e_pulse, e_pulse, c_nof_repeat);
- u_delay_adapt_pls_pls : entity work.tb_uth generic map ("DELAY", "ADAPT", c_phy_link_valid_support, e_pulse, e_pulse, c_nof_repeat); -- much faster than the uth_tx(rtl_hold)
- u_delay_hold_pls_pls : entity work.tb_uth generic map ("DELAY", "HOLD", c_phy_link_valid_support, e_pulse, e_pulse, c_nof_repeat); -- much faster than the uth_tx(rtl_hold)
+ -- much faster than the uth_tx(rtl_hold)
+ u_delay_adapt_pls_pls : entity work.tb_uth generic map ("DELAY", "ADAPT", c_phy_link_valid_support, e_pulse, e_pulse, c_nof_repeat);
+ -- much faster than the uth_tx(rtl_hold)
+ u_delay_hold_pls_pls : entity work.tb_uth generic map ("DELAY", "HOLD", c_phy_link_valid_support, e_pulse, e_pulse, c_nof_repeat);
end tb;
diff --git a/libraries/base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd b/libraries/base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd
index 772792144e127fd9ec05324eff95136da87dd1a7..f56335b35c0bd759e19f6f257ba5299a5c3cf7c1 100644
--- a/libraries/base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd
@@ -33,7 +33,8 @@ end tb_tb_uth_dp_packet;
architecture tb of tb_tb_uth_dp_packet is
constant c_phy_link_valid_support : boolean := true;
constant c_nof_repeat : natural := 10;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_phy_link_valid_support,
-- g_data_w, in_en,
diff --git a/libraries/base/uth/tb/vhdl/tb_tb_uth_terminals.vhd b/libraries/base/uth/tb/vhdl/tb_tb_uth_terminals.vhd
index ee5ed3ed22403c801f7d34e0de30d7dd368190ac..9066f2a9b97fb2feabd11747eaf78b4fdca525ad 100644
--- a/libraries/base/uth/tb/vhdl/tb_tb_uth_terminals.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_tb_uth_terminals.vhd
@@ -33,7 +33,8 @@ end tb_tb_uth_terminals;
architecture tb of tb_tb_uth_terminals is
constant c_phy_link_valid_support : boolean := true;
constant c_nof_repeat : natural := 100;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- in_en, out_ready, nof_repeat, phy_fifo_size, uth_rx_timeout_w, tx_use_fifo, tx_fifo_fill, rx_use_fifo, rx_fifo_fill, fifo_use_sync, fifo_use_bsn, nof_input, nof_serial
u_rnd_rnd_4_3 : entity work.tb_uth_terminals generic map (e_random, e_random, c_nof_repeat, 0, 0, false, 0, false, 0, false, false, 4, 3);
diff --git a/libraries/base/uth/tb/vhdl/tb_uth.vhd b/libraries/base/uth/tb/vhdl/tb_uth.vhd
index 357f71bd7d4266865968f68880642ac7ae4dd35f..ceb54d9ab3faad289fb0c68efda489d033ef1259 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth.vhd
@@ -37,30 +37,39 @@ use dp_lib.tb_dp_pkg.all;
entity tb_uth is
generic (
- g_use_uth_tx_arch : string := "HOLD"; -- "HOLD" = use uth_tx(rtl_hold)
+ -- "HOLD" = use uth_tx(rtl_hold)
+ g_use_uth_tx_arch : string := "HOLD";
-- "DELAY" = use uth_tx(rtl_delay)
- g_use_uth_rx_arch : string := "HOLD"; -- "HOLD" = use uth_rx(rtl_hold)
+ -- "HOLD" = use uth_rx(rtl_hold)
+ g_use_uth_rx_arch : string := "HOLD";
-- "ADAPT" = use uth_rx(rtl_adapt)
- g_phy_link_valid_support : boolean := true; -- when TRUE then the PHY link can pass on valid control, else the valid not transported and implicitely always active
- g_in_en : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_out_ready : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_nof_repeat : natural := 1 -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
+ -- when TRUE then the PHY link can pass on valid control, else the valid not transported and implicitely always active
+ g_phy_link_valid_support : boolean := true;
+ -- always active, random or pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_active;
+ -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
+ g_nof_repeat : natural := 1
);
end tb_uth;
architecture tb of tb_uth is
constant c_rl : natural := 1;
constant c_data_w : natural := 16;
- constant c_typ_ofs : natural := sel_a_b(c_data_w < 16, 2**7, 2**15); -- avoid out of 32 bit INTEGER range for g_data_w > 30
+ -- avoid out of 32 bit INTEGER range for g_data_w > 30
+ constant c_typ_ofs : natural := sel_a_b(c_data_w < 16, 2**7, 2**15);
constant c_max_len : natural := c_typ_ofs - 1;
constant c_data_init : integer := 0;
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 7;
- constant c_tx_nof_ch : natural := 10; -- the channels are numbered from 0 TO c_tx_nof_ch-1, each channel represents a type of UTH frame
+ -- the channels are numbered from 0 TO c_tx_nof_ch-1, each channel represents a type of UTH frame
+ constant c_tx_nof_ch : natural := 10;
constant c_tx_typ_arr : t_natural_arr(0 to c_tx_nof_ch - 1) := (1, 2, 3, 5, c_typ_ofs, c_typ_ofs + 1, c_typ_ofs + 2, c_typ_ofs + 3, 100, 50);
constant c_tx_len_arr : t_natural_arr(0 to c_tx_nof_ch - 1) := (1, 2, 3, 5, 1, 8, 8, 10, 100, 50);
- constant c_rx_nof_ch : natural := c_tx_nof_ch - 1; -- do not support the last tx tlen channel
+ -- do not support the last tx tlen channel
+ constant c_rx_nof_ch : natural := c_tx_nof_ch - 1;
constant c_rx_typ_arr : t_natural_arr(0 to c_rx_nof_ch - 1) := c_tx_typ_arr(0 to c_rx_nof_ch - 1);
constant c_rx_len_arr : t_natural_arr(0 to c_rx_nof_ch - 1) := c_tx_len_arr(0 to c_rx_nof_ch - 1);
constant c_rx_not_supported_ch : natural := c_tx_nof_ch - 1;
@@ -72,8 +81,10 @@ architecture tb of tb_uth is
signal clk : std_logic := '1';
signal rst : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -180,7 +191,8 @@ begin
-- Signal end of stimuli
expected_uth_rx_data <= TO_UVEC(v_data_init - 1, c_data_w);
- proc_common_wait_some_cycles(clk, 100); -- depends on stream control
+ -- depends on stream control
+ proc_common_wait_some_cycles(clk, 100);
verify_done <= '1';
proc_common_wait_some_cycles(clk, 1);
verify_done <= '0';
@@ -201,10 +213,14 @@ begin
verify_en <= '1';
- proc_dp_verify_data("uth_rx_data", c_rl, clk, verify_en, uth_rx_siso.ready, uth_rx_val, uth_rx_data, prev_uth_rx_data); -- Verify that the output is incrementing data, like the input stimuli
- proc_dp_verify_valid(c_rl, clk, verify_en, uth_rx_siso.ready, prev_uth_rx_ready, uth_rx_val); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_sop_and_eop(clk, uth_rx_val, uth_rx_sop, uth_rx_eop, hold_rx_sop); -- Verify that sop and eop come in pairs
- proc_dp_verify_value(e_equal, clk, verify_done, expected_uth_rx_data, prev_uth_rx_data); -- Verify that the stimuli have been applied at all
+ -- Verify that the output is incrementing data, like the input stimuli
+ proc_dp_verify_data("uth_rx_data", c_rl, clk, verify_en, uth_rx_siso.ready, uth_rx_val, uth_rx_data, prev_uth_rx_data);
+ -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_valid(c_rl, clk, verify_en, uth_rx_siso.ready, prev_uth_rx_ready, uth_rx_val);
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(clk, uth_rx_val, uth_rx_sop, uth_rx_eop, hold_rx_sop);
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done, expected_uth_rx_data, prev_uth_rx_data);
------------------------------------------------------------------------------
-- TRANSMITTER
@@ -217,7 +233,8 @@ begin
g_data_w => c_data_w,
g_nof_ch => c_tx_nof_ch,
g_typ_arr => c_tx_typ_arr,
- g_out_rl => 6 -- g_out_rl is ignored by architecture rtl_hold
+ -- g_out_rl is ignored by architecture rtl_hold
+ g_out_rl => 6
)
port map (
rst => rst,
@@ -237,7 +254,8 @@ begin
g_data_w => c_data_w,
g_nof_ch => c_tx_nof_ch,
g_typ_arr => c_tx_typ_arr,
- g_out_rl => 1 -- adapt architecture rtl_delay RL = 6 to output RL = c_rl = 1
+ -- adapt architecture rtl_delay RL = 6 to output RL = c_rl = 1
+ g_out_rl => 1
)
port map (
rst => rst,
diff --git a/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd b/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
index 7ad85b075dfb7e19e94f8272e7c49280cd41bbe4..ca4b9cc78fc655b91325c7275cb7c9c16e7d3da7 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
@@ -40,21 +40,28 @@ use dp_lib.tb_dp_pkg.all;
entity tb_uth_dp_packet is
generic (
- g_phy_link_valid_support : boolean := true; -- when TRUE then the PHY link can pass on valid control, else the valid not transported and implicitely always active
+ -- when TRUE then the PHY link can pass on valid control, else the valid not transported and implicitely always active
+ g_phy_link_valid_support : boolean := true;
g_data_w : natural := 16;
- g_in_en : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_out_ready : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_nof_repeat : natural := 10 -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
+ -- always active, random or pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_active;
+ -- always active, random or pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_active;
+ -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
+ g_nof_repeat : natural := 10
);
end tb_uth_dp_packet;
architecture tb of tb_uth_dp_packet is
constant c_rl : natural := 1;
- constant c_typ_ofs : natural := sel_a_b(g_data_w < 16, 2**7, 2**15); -- avoid out of 32 bit INTEGER range for g_data_w > 30
+ -- avoid out of 32 bit INTEGER range for g_data_w > 30
+ constant c_typ_ofs : natural := sel_a_b(g_data_w < 16, 2**7, 2**15);
constant c_max_len : natural := c_typ_ofs - 1;
constant c_data_init : integer := 0;
- constant c_data_w : integer := sel_a_b(g_data_w < 30, g_data_w, 30); -- used to avoid INTEGER range error for 2**31 and 2**32
- constant c_data_mod : integer := 2**c_data_w; -- used to avoid TO_UVEC warning for smaller g_data_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ -- used to avoid INTEGER range error for 2**31 and 2**32
+ constant c_data_w : integer := sel_a_b(g_data_w < 30, g_data_w, 30);
+ -- used to avoid TO_UVEC warning for smaller g_data_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ constant c_data_mod : integer := 2**c_data_w;
constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0877665544332211";
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 7;
@@ -77,15 +84,18 @@ architecture tb of tb_uth_dp_packet is
c_pkt_overhead_len + 70,
c_pkt_overhead_len + 17);
--CONSTANT c_repeat_arr : t_natural_arr(0 TO c_nof_streams-1) := array_init(g_nof_repeat, c_nof_streams, 1); -- use g_nof_repeat+cK to have different expected_out_data(I,J) per input, to verify that the output demultiplexing works correct
- constant c_repeat_arr : t_natural_arr(0 to c_nof_streams - 1) := array_init(g_nof_repeat, c_nof_streams); -- use g_nof_repeat for all inputs
+ -- use g_nof_repeat for all inputs
+ constant c_repeat_arr : t_natural_arr(0 to c_nof_streams - 1) := array_init(g_nof_repeat, c_nof_streams);
constant c_bsn_w : natural := 48;
constant c_channel_w : natural := ceil_log2(c_nof_tlen) + ceil_log2(c_nof_input);
constant c_err_w : natural := 1;
--- Default connect enc-uth_tx to uth_rx-dec via UTH over PHY link
- constant c_loopback_packet : boolean := false; -- when TRUE loop back enc-dec, to verify throughput without UTH
- constant c_loopback_mux : boolean := false; -- when TRUE loop back mux-demux, to verify throughput at SISO/SOSI single multiplexed stream level, without DP PACKET and without UTH
+ -- when TRUE loop back enc-dec, to verify throughput without UTH
+ constant c_loopback_packet : boolean := false;
+ -- when TRUE loop back mux-demux, to verify throughput at SISO/SOSI single multiplexed stream level, without DP PACKET and without UTH
+ constant c_loopback_mux : boolean := false;
type t_siso_2arr is array (integer range <>) of t_dp_siso_arr(0 to c_nof_input - 1);
type t_sosi_2arr is array (integer range <>) of t_dp_sosi_arr(0 to c_nof_input - 1);
@@ -98,8 +108,10 @@ architecture tb of tb_uth_dp_packet is
signal clk : std_logic := '1';
signal rst : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -293,16 +305,22 @@ begin
gen_verify : for I in 0 to c_nof_tlen - 1 generate
gen_output : for J in 0 to c_nof_input - 1 generate
-- Verification logistics
- verify_en(I,J) <= '1' when rising_edge(clk) and out_sosi_2arr(I)(J).sop = '1'; -- verify enable after first output sop
- count_eop(I,J) <= count_eop(I,J) + 1 when rising_edge(clk) and out_sosi_2arr(I)(J).eop = '1'; -- count number of output eop
+ -- verify enable after first output sop
+ verify_en(I,J) <= '1' when rising_edge(clk) and out_sosi_2arr(I)(J).sop = '1';
+ -- count number of output eop
+ count_eop(I,J) <= count_eop(I,J) + 1 when rising_edge(clk) and out_sosi_2arr(I)(J).eop = '1';
verify_done(I,J) <= '1' when rising_edge(clk) and count_eop(I,J) = c_repeat_arr(I * c_nof_input + J) and count_eop(I,J) /= prev_count_eop(I,J) else '0';
tb_end_vec(I * c_nof_input + J) <= '1' when rising_edge(clk) and count_eop(I,J) = c_repeat_arr(I * c_nof_input + J);
-- Actual verification of the output streams
- proc_dp_verify_data("out_sosi_2arr.data", c_rl, clk, verify_en(I,J), out_siso_2arr(I)(J).ready, out_sosi_2arr(I)(J).valid, out_data(I,J), prev_out_data(I,J)); -- Verify that the output is incrementing data, like the input stimuli
- proc_dp_verify_valid(c_rl, clk, verify_en(I,J), out_siso_2arr(I)(J).ready, prev_out_ready(I,J), out_sosi_2arr(I)(J).valid); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_sop_and_eop(clk, out_sosi_2arr(I)(J).valid, out_sosi_2arr(I)(J).sop, out_sosi_2arr(I)(J).eop, hold_out_sop(I,J)); -- Verify that sop and eop come in pairs
- proc_dp_verify_value(e_equal, clk, verify_done(I,J), expected_out_data(I,J), prev_out_data(I,J)); -- Verify that the stimuli have been applied at all
+ -- Verify that the output is incrementing data, like the input stimuli
+ proc_dp_verify_data("out_sosi_2arr.data", c_rl, clk, verify_en(I,J), out_siso_2arr(I)(J).ready, out_sosi_2arr(I)(J).valid, out_data(I,J), prev_out_data(I,J));
+ -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_valid(c_rl, clk, verify_en(I,J), out_siso_2arr(I)(J).ready, prev_out_ready(I,J), out_sosi_2arr(I)(J).valid);
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(clk, out_sosi_2arr(I)(J).valid, out_sosi_2arr(I)(J).sop, out_sosi_2arr(I)(J).eop, hold_out_sop(I,J));
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done(I,J), expected_out_data(I,J), prev_out_data(I,J));
end generate;
end generate;
@@ -316,8 +334,10 @@ begin
generic map (
g_nof_input => c_nof_input,
g_use_fifo => false,
- g_fifo_size => array_init(1024, c_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, c_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_size => array_init(1024, c_nof_input),
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, c_nof_input)
)
port map (
rst => rst,
@@ -336,8 +356,10 @@ begin
generic map (
g_nof_input => c_nof_tlen,
g_use_fifo => false,
- g_fifo_size => array_init(1024, c_nof_tlen), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, c_nof_tlen) -- must match g_nof_input, even when g_use_fifo=FALSE
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_size => array_init(1024, c_nof_tlen),
+ -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, c_nof_tlen)
)
port map (
rst => rst,
@@ -570,7 +592,8 @@ begin
p_phy_link : process(uth_tx_sosi, phy_link_err)
begin
uth_rx_sosi <= uth_tx_sosi;
- uth_rx_sosi.data <= RESIZE_DP_DATA(uth_tx_sosi.data(g_data_w - 1 downto 0)); -- limit PHY data width to g_data_w
+ -- limit PHY data width to g_data_w
+ uth_rx_sosi.data <= RESIZE_DP_DATA(uth_tx_sosi.data(g_data_w - 1 downto 0));
if g_phy_link_valid_support = false then
uth_rx_sosi.valid <= '1';
end if;
diff --git a/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd b/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
index 3c5cf552cd23b1dbeca2f41a8400059ab3aa0b57..338f12c63dd98ff383e9c3cf8e9f70e8adfb3291 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
@@ -48,13 +48,18 @@ use dp_lib.tb_dp_pkg.all;
entity tb_uth_terminals is
generic (
-- Try flow control
- g_in_en : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
- g_out_ready : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
- g_nof_repeat : natural := 1000; -- >= 1, number of frames
+ -- always active, random or pulse flow control
+ g_in_en : t_dp_flow_control_enum := e_pulse;
+ -- always active, random or pulse flow control
+ g_out_ready : t_dp_flow_control_enum := e_active;
+ -- >= 1, number of frames
+ g_nof_repeat : natural := 1000;
-- Try PHY model
- g_phy_fifo_size : natural := 0; -- when 0 model PHY link as wire, else using a FIFO with that size
+ -- when 0 model PHY link as wire, else using a FIFO with that size
+ g_phy_fifo_size : natural := 0;
-- Try rx timeout to recover from link disconnect by tb_uth_terminals.do
- g_uth_rx_timeout_w : natural := 5; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ g_uth_rx_timeout_w : natural := 5;
-- Try input FIFO for Tx distribute
g_tx_use_fifo : boolean := true;
g_tx_fifo_fill : natural := 15;
@@ -65,16 +70,20 @@ entity tb_uth_terminals is
g_fifo_use_sync : boolean := true;
g_fifo_use_bsn : boolean := true;
-- Try distribute settings
- g_nof_input : natural := 4; -- = n
- g_nof_serial : natural := 3 -- = m
+ -- = n
+ g_nof_input : natural := 4;
+ -- = m
+ g_nof_serial : natural := 3
);
end tb_uth_terminals;
architecture tb of tb_uth_terminals is
constant c_rl : natural := 1;
constant c_data_init : integer := 0;
- constant c_frame_len : integer := 10; -- 96
- constant c_gap_len : integer := 0; -- 256 - c_frame_len;
+ -- 96
+ constant c_frame_len : integer := 10;
+ -- 256 - c_frame_len;
+ constant c_gap_len : integer := 0;
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 3;
constant c_nof_repeat_extra : natural := sel_a_b(g_tx_use_fifo, 1, 0) * (ceil_div(g_tx_fifo_fill, c_frame_len) + 1) + sel_a_b(g_rx_use_fifo, 1, 0) * (ceil_div(g_rx_fifo_fill, c_frame_len) + 1);
@@ -91,24 +100,30 @@ architecture tb of tb_uth_terminals is
constant c_data_w : natural := 16;
constant c_bsn_w : natural := c_data_w;
constant c_channel_w : natural := c_data_w;
- constant c_fifo_size : natural := c_bram_m9k_fifo_depth; -- = 256
- constant c_fifo_af_margin : natural := c_fifo_afull_margin; -- nof words below max (full) at which fifo is considered almost full. For UTH (rtl_hold) default c_fifo_afull_margin = 4 is OK for the other architectures more margin is needed e.g. 10
+ -- = 256
+ constant c_fifo_size : natural := c_bram_m9k_fifo_depth;
+ -- nof words below max (full) at which fifo is considered almost full. For UTH (rtl_hold) default c_fifo_afull_margin = 4 is OK for the other architectures more margin is needed e.g. 10
+ constant c_fifo_af_margin : natural := c_fifo_afull_margin;
constant c_data_init_offset : integer := 13;
-- DP packet
constant c_link_channel_lo : natural := ceil_log2(g_nof_serial);
- constant c_code_channel_lo : boolean := true; -- Code channel_lo in DP packet CHAN field
+ -- Code channel_lo in DP packet CHAN field
+ constant c_code_channel_lo : boolean := true;
-- UTH
constant c_uth_frame_len : natural := func_dp_packet_overhead_len(c_data_w) + c_frame_len;
- constant c_uth_nof_ch : natural := 1; -- selects UTH TLEN based on the snk_in channel_lo part that is not in the DP Packet CHAN field
+ -- selects UTH TLEN based on the snk_in channel_lo part that is not in the DP Packet CHAN field
+ constant c_uth_nof_ch : natural := 1;
constant c_uth_len_max : natural := 255;
- constant c_uth_typ_ofs : natural := c_uth_len_max + 1; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ constant c_uth_typ_ofs : natural := c_uth_len_max + 1;
constant c_uth_typ_arr : t_natural_arr := array_init( c_uth_typ_ofs, c_uth_nof_ch, 1);
constant c_uth_len_arr : t_natural_arr := array_init(c_uth_frame_len, c_uth_nof_ch);
- subtype t_data_arr is t_slv_16_arr(g_nof_input - 1 downto 0); -- width 16 must match c_data_w
+ -- width 16 must match c_data_w
+ subtype t_data_arr is t_slv_16_arr(g_nof_input - 1 downto 0);
type t_rl_vec_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(0 to c_rl);
signal tb_end_vec : std_logic_vector(g_nof_input - 1 downto 0) := (others => '0');
@@ -116,8 +131,10 @@ architecture tb of tb_uth_terminals is
signal clk : std_logic := '1';
signal rst : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -196,8 +213,10 @@ begin
variable v_error : natural;
variable v_sync : std_logic;
begin
- v_data_init := c_data_init + I * c_data_init_offset; -- offset the frame data for each input, so the inputs can be recognized at the output
- v_frame_len := c_frame_len; -- same frame length for each input, so only one UTH TLEN type is needed
+ -- offset the frame data for each input, so the inputs can be recognized at the output
+ v_data_init := c_data_init + I * c_data_init_offset;
+ -- same frame length for each input, so only one UTH TLEN type is needed
+ v_frame_len := c_frame_len;
v_channel := I;
v_error := 0;
in_sosi_arr(I) <= c_dp_sosi_rst;
@@ -219,8 +238,10 @@ begin
end loop;
-- End of stimuli
- proc_common_wait_until_high(clk, verify_end(I)); -- in case of using FIFOs verify_done is issued somewhat before the output will stop due to c_nof_expected
- proc_common_wait_some_cycles(clk, 10 * c_frame_len); -- continue some more after verify_done to see that the output has stopped
+ -- in case of using FIFOs verify_done is issued somewhat before the output will stop due to c_nof_expected
+ proc_common_wait_until_high(clk, verify_end(I));
+ -- continue some more after verify_done to see that the output has stopped
+ proc_common_wait_some_cycles(clk, 10 * c_frame_len);
tb_end_vec(I) <= '1';
wait;
end process;
@@ -232,23 +253,31 @@ begin
gen_verify : for I in g_nof_input - 1 downto 0 generate
-- Verification logistics
- verify_en(I) <= '1' when rising_edge(clk) and out_sosi_arr(I).sop = '1'; -- enable verify after first output sop
- count_eop(I) <= count_eop(I) + 1 when rising_edge(clk) and out_sosi_arr(I).eop = '1'; -- count number of output eop
+ -- enable verify after first output sop
+ verify_en(I) <= '1' when rising_edge(clk) and out_sosi_arr(I).sop = '1';
+ -- count number of output eop
+ count_eop(I) <= count_eop(I) + 1 when rising_edge(clk) and out_sosi_arr(I).eop = '1';
prev_count_eop(I) <= count_eop(I) when rising_edge(clk);
verify_done(I) <= '1' when rising_edge(clk) and count_eop(I) = c_nof_expected and count_eop(I) /= prev_count_eop(I) else
- '0' when rising_edge(clk); -- signal verify done after c_nof_expected frames, use pulse to have only one assert from proc_dp_verify_value()
- verify_end(I) <= '1' when rising_edge(clk) and verify_done(I) = '1'; -- signal verify_end after verify_done pulse, use level to ensure tb_end even if the stimuli are still busy
+ -- signal verify done after c_nof_expected frames, use pulse to have only one assert from proc_dp_verify_value()
+ '0' when rising_edge(clk);
+ -- signal verify_end after verify_done pulse, use level to ensure tb_end even if the stimuli are still busy
+ verify_end(I) <= '1' when rising_edge(clk) and verify_done(I) = '1';
-- Actual verification of the output streams
- proc_dp_verify_data("out_sosi_arr.data", c_rl, clk, verify_en(I), out_siso_arr(I).ready, out_sosi_arr(I).valid, out_data(I), prev_out_data(I)); -- Verify that the output is incrementing data, like the input stimuli
- proc_dp_verify_valid(c_rl, clk, verify_en(I), out_siso_arr(I).ready, prev_out_ready(I), out_sosi_arr(I).valid); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_sop_and_eop(clk, out_sosi_arr(I).valid, out_sosi_arr(I).sop, out_sosi_arr(I).eop, hold_out_sop(I)); -- Verify that sop and eop come in pairs
+ -- Verify that the output is incrementing data, like the input stimuli
+ proc_dp_verify_data("out_sosi_arr.data", c_rl, clk, verify_en(I), out_siso_arr(I).ready, out_sosi_arr(I).valid, out_data(I), prev_out_data(I));
+ -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_valid(c_rl, clk, verify_en(I), out_siso_arr(I).ready, prev_out_ready(I), out_sosi_arr(I).valid);
+ -- Verify that sop and eop come in pairs
+ proc_dp_verify_sop_and_eop(clk, out_sosi_arr(I).valid, out_sosi_arr(I).sop, out_sosi_arr(I).eop, hold_out_sop(I));
gen_verify_sync : if c_use_sync and c_use_bsn generate
proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en(I), out_sosi_arr(I).sync, out_sosi_arr(I).sop, out_sosi_arr(I).bsn);
-- Use at e_equal because at verify done the result is independ of whether there are still frames in the FIFO
- proc_dp_verify_value(e_equal, clk, verify_done(I), expected_out_bsn(I), out_bsn(I)); -- Verify that the stimuli have been applied at all
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done(I), expected_out_bsn(I), out_bsn(I));
end generate;
gen_verify_channel : if c_use_channel generate
@@ -256,7 +285,8 @@ begin
end generate;
-- Use at e_equal because at verify done the result is independ of whether there are still frames in the FIFO
- proc_dp_verify_value(e_equal, clk, verify_done(I), expected_out_data(I), prev_out_data(I)); -- Verify that the stimuli have been applied at all
+ -- Verify that the stimuli have been applied at all
+ proc_dp_verify_value(e_equal, clk, verify_done(I), expected_out_data(I), prev_out_data(I));
-- Monitoring
out_data(I) <= out_sosi_arr(I).data(c_data_w - 1 downto 0);
diff --git a/libraries/base/util/src/vhdl/util_heater.vhd b/libraries/base/util/src/vhdl/util_heater.vhd
index 14ca41286efd16db50f0d613e97bf8184b1e6667..5bc47b9cffd62b702e96962bf1d0fcecf672c169 100644
--- a/libraries/base/util/src/vhdl/util_heater.vhd
+++ b/libraries/base/util/src/vhdl/util_heater.vhd
@@ -55,15 +55,21 @@ use work.util_heater_pkg.all;
entity util_heater is
generic (
g_technology: natural := c_tech_select_default;
- g_nof_mac4 : natural := 1; -- >= 1, number of multiply 18x18 and accumulate 4 elements in the heater <= c_util_heater_nof_mac4_max
- g_pipeline : natural := 1; -- >= 0, number of pipelining register stages after the multiplier
- g_nof_ram : natural := 1; -- >= 0, number of 1k Byte RAM blocks in the FIFO per multiplier
- g_nof_logic : natural := 1 -- >= 0, number of XOR register stages after the FIFO
+ -- >= 1, number of multiply 18x18 and accumulate 4 elements in the heater <= c_util_heater_nof_mac4_max
+ g_nof_mac4 : natural := 1;
+ -- >= 0, number of pipelining register stages after the multiplier
+ g_pipeline : natural := 1;
+ -- >= 0, number of 1k Byte RAM blocks in the FIFO per multiplier
+ g_nof_ram : natural := 1;
+ -- >= 0, number of XOR register stages after the FIFO
+ g_nof_logic : natural := 1
);
port (
- mm_rst : in std_logic; -- MM is the microprocessor control clock domain
+ -- MM is the microprocessor control clock domain
+ mm_rst : in std_logic;
mm_clk : in std_logic;
- st_rst : in std_logic; -- ST is the DSP clock domain
+ -- ST is the DSP clock domain
+ st_rst : in std_logic;
st_clk : in std_logic;
-- Memory Mapped Slave
sla_in : in t_mem_mosi;
@@ -79,29 +85,42 @@ architecture rtl of util_heater is
nof_dat => c_util_heater_reg_nof_words,
init_sl => '0');
- constant c_remote_len : natural := 5; -- >> 0 to ease timing to reach logic throughout the whole chip
- constant c_sync_delay_len : natural := c_meta_delay_len + c_remote_len; -- >= c_meta_delay_len=3
+ -- >> 0 to ease timing to reach logic throughout the whole chip
+ constant c_remote_len : natural := 5;
+ -- >= c_meta_delay_len=3
+ constant c_sync_delay_len : natural := c_meta_delay_len + c_remote_len;
-- Use a MAC with 4 multipliers as basic heater element to be able to use all 18x18 in a Stratix4 DSP block
- constant c_mac4 : natural := 4; -- 4 multipliers per mac4
+ -- 4 multipliers per mac4
+ constant c_mac4 : natural := 4;
constant c_mac_pipeline_input : natural := 1;
constant c_mac_pipeline_product : natural := 0;
constant c_mac_pipeline_adder : natural := 1;
constant c_mac_pipeline_output : natural := 1;
-- Random input generators
- constant c_in_dat_w : natural := 18; -- fixed multiplier input data width
- constant c_prsg_0_w : natural := c_in_dat_w; -- generate sufficiently large random range
- constant c_prsg_1_w : natural := c_in_dat_w + 1; -- generate different range
- constant c_prsg_2_w : natural := c_in_dat_w + 2; -- generate different range
- constant c_prsg_3_w : natural := c_in_dat_w + 3; -- generate different range
-
- constant c_mac_in_dat_w : natural := c_mac4 * c_in_dat_w; -- aggregate mac4 input data width
- constant c_mult_dat_w : natural := c_in_dat_w + c_in_dat_w; -- = 36
- constant c_mac_out_dat_w : natural := c_mult_dat_w + 2; -- + 2 = ceil_log2(c_mac4)
- constant c_fifo_dat_w : natural := c_mult_dat_w; -- = 36
-
- constant c_nof_fifo_dat_in_1kbyte_ram : natural := (1024 * 9) / c_fifo_dat_w; -- = a byte has 8 + 1 = 9 bits
+ -- fixed multiplier input data width
+ constant c_in_dat_w : natural := 18;
+ -- generate sufficiently large random range
+ constant c_prsg_0_w : natural := c_in_dat_w;
+ -- generate different range
+ constant c_prsg_1_w : natural := c_in_dat_w + 1;
+ -- generate different range
+ constant c_prsg_2_w : natural := c_in_dat_w + 2;
+ -- generate different range
+ constant c_prsg_3_w : natural := c_in_dat_w + 3;
+
+ -- aggregate mac4 input data width
+ constant c_mac_in_dat_w : natural := c_mac4 * c_in_dat_w;
+ -- = 36
+ constant c_mult_dat_w : natural := c_in_dat_w + c_in_dat_w;
+ -- + 2 = ceil_log2(c_mac4)
+ constant c_mac_out_dat_w : natural := c_mult_dat_w + 2;
+ -- = 36
+ constant c_fifo_dat_w : natural := c_mult_dat_w;
+
+ -- = a byte has 8 + 1 = 9 bits
+ constant c_nof_fifo_dat_in_1kbyte_ram : natural := (1024 * 9) / c_fifo_dat_w;
type t_prsg_0_arr is array (integer range <>) of std_logic_vector(c_prsg_0_w - 1 downto 0);
type t_prsg_1_arr is array (integer range <>) of std_logic_vector(c_prsg_1_w - 1 downto 0);
@@ -310,7 +329,8 @@ begin
prsg_0_reg(c_in_dat_w - 1 downto 0);
-- Complex multipliers, these should get mapped on DSP elements in the FPGA
- u_dsp : entity common_mult_lib.common_mult_add4 -- (rtl)
+ -- (rtl)
+ u_dsp : entity common_mult_lib.common_mult_add4
generic map (
g_technology => g_technology,
g_in_a_w => c_in_dat_w,
@@ -332,7 +352,8 @@ begin
-- Pipeline, use g_pipeline > 0 to run some more logic resources or to ease achieving timing closure
u_logic : entity common_lib.common_pipeline
generic map (
- g_pipeline => g_pipeline, -- use 0 for no logic, so only wires
+ -- use 0 for no logic, so only wires
+ g_pipeline => g_pipeline,
g_in_dat_w => c_mac_out_dat_w,
g_out_dat_w => c_fifo_dat_w
)
@@ -396,6 +417,7 @@ begin
end generate;
-- Preserve result, to avoid that the synthesis will optimize all heater element away
- nxt_st_element_xor(I) <= vector_xor(logic_dat(I)); -- arbitrary function to group product bits into single output bit
+ -- arbitrary function to group product bits into single output bit
+ nxt_st_element_xor(I) <= vector_xor(logic_dat(I));
end generate;
end rtl;
diff --git a/libraries/base/util/src/vhdl/util_heater_pkg.vhd b/libraries/base/util/src/vhdl/util_heater_pkg.vhd
index dae51ab7abef1797fe8b00786cb70a2ebefde26d..af1b6c9254b46ad9a5ec9b14c4d7965b62b6f311 100644
--- a/libraries/base/util/src/vhdl/util_heater_pkg.vhd
+++ b/libraries/base/util/src/vhdl/util_heater_pkg.vhd
@@ -34,8 +34,10 @@ package util_heater_pkg is
-- The maximum number of 16kbit M144K RAM blocks in the Stratix IV SGX230 = 22
--CONSTANT c_util_heater_nof_mac4_max : NATURAL := 352; --stratix4 -- >= 1288/4 and multiple of c_word_w=32
- constant c_util_heater_nof_mac4_max : natural := 800; -- stratix4 -- >= 1288/4 and multiple of c_word_w=32
- constant c_util_heater_reg_nof_words : natural := c_util_heater_nof_mac4_max / c_word_w; -- note: needs adjustment if not multiple of c_word_w
+ -- stratix4 -- >= 1288/4 and multiple of c_word_w=32
+ constant c_util_heater_nof_mac4_max : natural := 800;
+ -- note: needs adjustment if not multiple of c_word_w
+ constant c_util_heater_reg_nof_words : natural := c_util_heater_nof_mac4_max / c_word_w;
constant c_util_heater_reg_addr_w : natural := ceil_log2(c_util_heater_reg_nof_words);
diff --git a/libraries/base/util/src/vhdl/util_logic.vhd b/libraries/base/util/src/vhdl/util_logic.vhd
index b50cc43071a2662495ddaa632b4dc746eb9b44f6..180e32be51ac1050e320f9eec430dc79302dfa00 100644
--- a/libraries/base/util/src/vhdl/util_logic.vhd
+++ b/libraries/base/util/src/vhdl/util_logic.vhd
@@ -33,7 +33,8 @@ use IEEE.std_logic_1164.all;
entity util_logic is
generic (
- g_nof_reg : natural := 1 -- 0 for wires, > 0 for registers
+ -- 0 for wires, > 0 for registers
+ g_nof_reg : natural := 1
);
port (
clk : in std_logic;
diff --git a/libraries/base/util/tb/vhdl/tb_util_heater.vhd b/libraries/base/util/tb/vhdl/tb_util_heater.vhd
index 6441abf5667c9a925f3d2bd015aa2760448e45d8..c4f9efbe980fee5e2dd3cc3ecdea86346f369243 100644
--- a/libraries/base/util/tb/vhdl/tb_util_heater.vhd
+++ b/libraries/base/util/tb/vhdl/tb_util_heater.vhd
@@ -35,7 +35,8 @@ architecture tb of tb_util_heater is
constant mm_clk_period : time := 8 ns;
constant st_clk_period : time := 5 ns;
- constant c_word_heater_on : integer := -1; -- 16#FFFFFFFF#;
+ -- 16#FFFFFFFF#;
+ constant c_word_heater_on : integer := -1;
constant c_word_heater_off : integer := 0;
constant c_time_heater_on : natural := 100;
@@ -46,7 +47,8 @@ architecture tb of tb_util_heater is
constant c_nof_ram : natural := 2;
constant c_nof_logic : natural := 3;
- constant c_reg_nof_words : natural := 2; -- derived from c_nof_mac4 / c_word_w
+ -- derived from c_nof_mac4 / c_word_w
+ constant c_reg_nof_words : natural := 2;
signal tb_end : std_logic := '0';
signal mm_rst : std_logic;
@@ -81,7 +83,8 @@ begin
end loop;
for I in 0 to c_reg_nof_words - 1 loop
- proc_mem_mm_bus_wr(I, c_word_heater_on, mm_clk, mm_miso, mm_mosi); -- Enable multiplier 31 : 0
+ -- Enable multiplier 31 : 0
+ proc_mem_mm_bus_wr(I, c_word_heater_on, mm_clk, mm_miso, mm_mosi);
end loop;
for I in 0 to c_time_heater_on - 1 loop
@@ -89,7 +92,8 @@ begin
end loop;
for I in 0 to c_reg_nof_words - 1 loop
- proc_mem_mm_bus_wr(I, c_word_heater_off, mm_clk, mm_miso, mm_mosi); -- Disable multiplier 31 : 0
+ -- Disable multiplier 31 : 0
+ proc_mem_mm_bus_wr(I, c_word_heater_off, mm_clk, mm_miso, mm_mosi);
end loop;
for I in 0 to c_time_heater_off - 1 loop
@@ -107,9 +111,11 @@ begin
g_nof_logic => c_nof_logic
)
port map (
- mm_rst => mm_rst, -- MM is the microprocessor control clock domain
+ -- MM is the microprocessor control clock domain
+ mm_rst => mm_rst,
mm_clk => mm_clk,
- st_rst => st_rst, -- ST is the DSP clock domain
+ -- ST is the DSP clock domain
+ st_rst => st_rst,
st_clk => st_clk,
-- Memory Mapped Slave
sla_in => mm_mosi,
diff --git a/libraries/dsp/beamformer/src/vhdl/beamformer.vhd b/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
index 25a30b681c5ccb464828024b2821286d28804b6e..9d47cf58dd85e8f03d0d3efaa6fe6b19a64a3a6f 100644
--- a/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
+++ b/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
@@ -58,11 +58,15 @@ entity beamformer is
g_nof_weights : natural;
g_weights_w : natural := 16;
g_weights_file : string := "hex/beamformer_weights";
- g_weights_ram_dual_port : boolean := true; -- FIXME rename this to readback_weights
+ -- FIXME rename this to readback_weights
+ g_weights_ram_dual_port : boolean := true;
g_mult_variant : string := "IP";
- g_use_weight_ram : boolean := true; -- Use weights RAM (default)
- g_use_weight_reg : boolean := false; -- Use a weights register instead of RAM
- g_use_weight_arr : boolean := false -- Use the input weights array instead of weights RAM of Registers
+ -- Use weights RAM (default)
+ g_use_weight_ram : boolean := true;
+ -- Use a weights register instead of RAM
+ g_use_weight_reg : boolean := false;
+ -- Use the input weights array instead of weights RAM of Registers
+ g_use_weight_arr : boolean := false
);
port (
dp_clk : in std_logic;
@@ -71,13 +75,16 @@ entity beamformer is
mm_clk : in std_logic;
mm_rst : in std_logic;
- ram_mosi : in t_mem_mosi := c_mem_mosi_rst; -- MM interface to upload weights to RAM or REG
+ -- MM interface to upload weights to RAM or REG
+ ram_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_miso : out t_mem_miso;
- weight_addr : in std_logic_vector(ceil_log2(g_nof_weights) - 1 downto 0); -- Weight address
+ -- Weight address
+ weight_addr : in std_logic_vector(ceil_log2(g_nof_weights) - 1 downto 0);
weight_arr : in t_slv_32_arr(g_nof_inputs - 1 downto 0) := (others => (others => '0'));
- snk_in_arr : in t_dp_sosi_arr(g_nof_inputs - 1 downto 0); -- All streams must be synchronous
+ -- All streams must be synchronous
+ snk_in_arr : in t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
src_out : out t_dp_sosi
);
end beamformer;
@@ -257,8 +264,10 @@ begin
-- Multiplier stage
------------------------------------------------------------------------------
gen_mult_inputs: for i in 0 to g_nof_inputs - 1 generate
- dp_complex_mult_snk_in_2arr_2(i)(0) <= dp_pipeline_arr_src_out_arr(i); -- Streaming data
- dp_complex_mult_snk_in_2arr_2(i)(1) <= common_ram_crw_crw_src_out_arr(i); -- Weights RAM
+ -- Streaming data
+ dp_complex_mult_snk_in_2arr_2(i)(0) <= dp_pipeline_arr_src_out_arr(i);
+ -- Weights RAM
+ dp_complex_mult_snk_in_2arr_2(i)(1) <= common_ram_crw_crw_src_out_arr(i);
end generate;
u_dp_complex_mult : entity dp_lib.dp_complex_mult
diff --git a/libraries/dsp/beamformer/tb/vhdl/tb_beamformer.vhd b/libraries/dsp/beamformer/tb/vhdl/tb_beamformer.vhd
index 1b949c26292a4ab4dbaeacb3aa1776a0c7a7be0c..fc94e3975b45cae4aa628a5aefa586f9cc36252c 100644
--- a/libraries/dsp/beamformer/tb/vhdl/tb_beamformer.vhd
+++ b/libraries/dsp/beamformer/tb/vhdl/tb_beamformer.vhd
@@ -42,11 +42,13 @@ use mm_lib.mm_file_pkg.all;
entity tb_beamformer is
generic (
- g_tb_index : natural := 0; -- use different index to avoid MM file conflict in multi tb
+ -- use different index to avoid MM file conflict in multi tb
+ g_tb_index : natural := 0;
--g_technology : NATURAL := c_tech_select_default;
g_nof_inputs : natural := 2;
g_nof_weights : natural := 32;
- g_data_w : natural := 8; -- 8b complex input data
+ -- 8b complex input data
+ g_data_w : natural := 8;
g_use_weight_ram : boolean := false;
g_use_weight_reg : boolean := true
);
@@ -83,7 +85,8 @@ architecture tb of tb_beamformer is
-- MM
constant c_unb_nr : natural := 0;
- constant c_node_nr : natural := 0; -- choose node 0 is FN 0
+ -- choose node 0 is FN 0
+ constant c_node_nr : natural := 0;
constant c_mm_file_ram_beamformer : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_BEAMFORMER_" & int_to_str(g_tb_index);
signal snk_in_enable : std_logic := '0';
@@ -125,7 +128,8 @@ architecture tb of tb_beamformer is
proc_common_gen_duty_pulse(0, 1, c_in_sync_interval, '1', dp_rst, dp_clk, snk_in_enable, snk_in.sync);
proc_common_gen_duty_pulse(0, c_in_block_size, c_in_block_interval, '1', dp_rst, dp_clk, snk_in_enable, snk_in.valid);
proc_common_gen_duty_pulse(0, 1, c_in_block_interval, '1', dp_rst, dp_clk, snk_in_enable, snk_in.sop);
- proc_common_gen_duty_pulse(c_in_block_size-1, 1, c_in_block_interval, '1', dp_rst, dp_clk, snk_in_enable, snk_in.eop); -- DUT uses eop
+ -- DUT uses eop
+ proc_common_gen_duty_pulse(c_in_block_size-1, 1, c_in_block_interval, '1', dp_rst, dp_clk, snk_in_enable, snk_in.eop);
-- bsn
snk_in.bsn <= INCR_UVEC(snk_in.bsn, 1) when rising_edge(dp_clk) and snk_in.eop = '1';
-- re/im data
@@ -193,7 +197,8 @@ architecture tb of tb_beamformer is
end if;
end loop;
end loop;
- verify_addr_en <= '1'; -- enable second check
+ -- enable second check
+ verify_addr_en <= '1';
end if;
wait;
end process;
@@ -229,7 +234,8 @@ architecture tb of tb_beamformer is
end if;
end loop;
end loop;
- verify_data_en <= '1'; -- enable third check
+ -- enable third check
+ verify_data_en <= '1';
wait;
end process;
@@ -243,8 +249,10 @@ architecture tb of tb_beamformer is
-- with weight (1+1j) output: re=0, im=(snk_in.re+snk_in.im)*nof_inputs
-- with weight (1+0j) output: re=snk_in.re*nof_inputs, im=snk_in.im*nof_inputs
for I in 0 to g_nof_inputs loop
- mmf_mm_bus_wr(c_mm_file_ram_beamformer, I * g_nof_weights, 1 * 2**16 + 1, mm_clk); -- (1+1j)
- mmf_mm_bus_wr(c_mm_file_ram_beamformer, I * g_nof_weights + 1, 1, mm_clk); -- (1+0j)
+ -- (1+1j)
+ mmf_mm_bus_wr(c_mm_file_ram_beamformer, I * g_nof_weights, 1 * 2**16 + 1, mm_clk);
+ -- (1+0j)
+ mmf_mm_bus_wr(c_mm_file_ram_beamformer, I * g_nof_weights + 1, 1, mm_clk);
end loop;
proc_common_wait_some_cycles(dp_clk, 1);
@@ -275,8 +283,10 @@ architecture tb of tb_beamformer is
severity ERROR;
data_ok <= '0';
end if;
- end loop; -- input data
- end loop; -- weigth address
+ -- input data
+ end loop;
+ -- weigth address
+ end loop;
proc_common_wait_some_cycles(dp_clk, 1);
if OK = '0' then
@@ -285,7 +295,8 @@ architecture tb of tb_beamformer is
report "Test passed.";
end if;
- tb_end <= '1'; -- end test
+ -- end test
+ tb_end <= '1';
wait;
end process;
diff --git a/libraries/dsp/beamformer/tb/vhdl/tb_tb_beamformer.vhd b/libraries/dsp/beamformer/tb/vhdl/tb_tb_beamformer.vhd
index cea840d0006c2ed21aa83e0628597bd5c721faf9..06dc1e765beaea353a32784fe2eb615ade4f0b53 100644
--- a/libraries/dsp/beamformer/tb/vhdl/tb_tb_beamformer.vhd
+++ b/libraries/dsp/beamformer/tb/vhdl/tb_tb_beamformer.vhd
@@ -33,7 +33,8 @@ entity tb_tb_beamformer is
end tb_tb_beamformer;
architecture tb of tb_tb_beamformer is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Usage
-- > as 8
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
index d9fa0804e75ae2d367ed7790a6c45f2a712c2587..4066e3f3ad9460aade86cb6a933338ffbface542 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
@@ -39,7 +39,8 @@ use bf_lib.bf_pkg.all;
entity mmm_unb1_fn_bf is
generic (
- g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
+ -- FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
g_bf : t_c_bf := c_bf
@@ -123,7 +124,8 @@ architecture str of mmm_unb1_fn_bf is
constant c_ram_diag_bg_addr_w : natural := ceil_log2(c_bg_diag_wave_period) + ceil_log2(g_bf.nof_subbands * g_bf.nof_signal_paths / g_bf.nof_input_streams) + ceil_log2(g_bf.nof_input_streams);
constant c_ram_bf_weights_addr_w : natural := ceil_log2(c_bf_max_nof_bf_units * g_bf.nof_signal_paths * g_bf.nof_weights);
constant c_ram_st_sst_bf_addr_w : natural := ceil_log2(c_bf_max_nof_bf_units * g_bf.stat_data_sz * g_bf.nof_weights * c_nof_complex);
- constant c_reg_st_sst_bf_addr_w : natural := ceil_log2(c_bf_max_nof_bf_units) * 2; -- 2 bits reserved for single reg_st_sst.
+ -- 2 bits reserved for single reg_st_sst.
+ constant c_reg_st_sst_bf_addr_w : natural := ceil_log2(c_bf_max_nof_bf_units) * 2;
constant c_ram_ss_ss_wide_addr_w : natural := ceil_log2(c_bf_max_nof_bf_units * g_bf.nof_weights * g_bf.nof_signal_paths);
-- BF offload
constant c_hdr_nof_words : natural := c_network_total_header_32b_nof_words;
@@ -238,7 +240,8 @@ begin
proc_tech_tse_setup(c_tech_stratixiv, false, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, i_mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, i_mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi);
sim_eth_mm_bus_switch <= '0';
wait;
@@ -270,11 +273,15 @@ begin
u_sopc : entity work.sopc_unb1_fn_bf
port map (
-- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ -- PLL reference = 25 MHz from ETH_clk pin
+ clk_0 => xo_clk,
reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => OPEN, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+ -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ mm_clk => i_mm_clk,
+ -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ cal_clk => OPEN,
+ -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+ tse_clk => i_tse_clk,
-- the_altpll_0
areset_to_the_altpll_0 => '0',
@@ -371,7 +378,8 @@ begin
-- the_pio_pps
coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1),
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
index bcf58a48080b76b2f7eba62a8b04cae942a81b74..dc1d89a54cc7a96479e98ec7886ba4959400f676 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
@@ -36,23 +36,34 @@ use bf_lib.bf_pkg.all;
entity node_unb1_fn_bf is
generic(
g_sim : boolean := false;
- g_use_bf : boolean := true; -- FALSE skips instantiation of the BF
+ -- FALSE skips instantiation of the BF
+ g_use_bf : boolean := true;
g_bf : t_c_bf := c_bf;
- g_bf_weights_file_name : string := "../../../../../dsp/bf/build/data/weights"; -- default file location for synthesis
- g_ss_wide_file_prefix : string := "UNUSED"; -- path_to_file
- g_bf_offload : boolean := false; -- Use DP TX offload to stream BF output towards LCU
- g_use_block_gen : boolean := true; -- FALSE uses external input.
- g_block_gen_file_prefix : string := "../../../../../modules/Lofar/diag/src/data/bf_in_data"; -- default file location for synthesis
- g_bg_diag_wave_period : positive := 4; -- This generic defines the period of the waveform that is generated with the block generator.
- g_weights_write_only : boolean := false -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
+ -- default file location for synthesis
+ g_bf_weights_file_name : string := "../../../../../dsp/bf/build/data/weights";
+ -- path_to_file
+ g_ss_wide_file_prefix : string := "UNUSED";
+ -- Use DP TX offload to stream BF output towards LCU
+ g_bf_offload : boolean := false;
+ -- FALSE uses external input.
+ g_use_block_gen : boolean := true;
+ -- default file location for synthesis
+ g_block_gen_file_prefix : string := "../../../../../modules/Lofar/diag/src/data/bf_in_data";
+ -- This generic defines the period of the waveform that is generated with the block generator.
+ g_bg_diag_wave_period : positive := 4;
+ -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
+ g_weights_write_only : boolean := false
);
port(
-- System
mm_rst : in std_logic;
- mm_clk : in std_logic; -- 125 MHz from xo_clk PLL in SOPC system
+ -- 125 MHz from xo_clk PLL in SOPC system
+ mm_clk : in std_logic;
dp_rst : in std_logic;
- dp_clk : in std_logic; -- 200 MHz from CLK system clock
- dp_pps : in std_logic := '1'; -- Pulse per second
+ -- 200 MHz from CLK system clock
+ dp_clk : in std_logic;
+ -- Pulse per second
+ dp_pps : in std_logic := '1';
-- MM interface
-- . block generator
reg_diag_bg_mosi : in t_mem_mosi;
@@ -82,12 +93,16 @@ entity node_unb1_fn_bf is
ext_in_siso_arr : out t_dp_siso_arr( g_bf.nof_input_streams - 1 downto 0) := (others => c_dp_siso_rst);
-- ST interface, BF beamlets out
- out_raw_sosi_arr : out t_dp_sosi_arr( g_bf.nof_bf_units - 1 downto 0); -- raw beamlets
- out_bst_sosi_arr : out t_dp_sosi_arr( g_bf.nof_bf_units - 1 downto 0); -- 16b beamlets; a selection can be offloaded via bf_out_offload_tx_sosi_arr.
- out_qua_sosi_arr : out t_dp_sosi_arr( g_bf.nof_bf_units - 1 downto 0); -- 8b beamlets
+ -- raw beamlets
+ out_raw_sosi_arr : out t_dp_sosi_arr( g_bf.nof_bf_units - 1 downto 0);
+ -- 16b beamlets; a selection can be offloaded via bf_out_offload_tx_sosi_arr.
+ out_bst_sosi_arr : out t_dp_sosi_arr( g_bf.nof_bf_units - 1 downto 0);
+ -- 8b beamlets
+ out_qua_sosi_arr : out t_dp_sosi_arr( g_bf.nof_bf_units - 1 downto 0);
-- DP offload for 1GbE
- bf_out_offload_tx_sosi_arr : out t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0); -- 16b beamlets
+ -- 16b beamlets
+ bf_out_offload_tx_sosi_arr : out t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0);
bf_out_offload_tx_siso_arr : in t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_siso_rst)
);
end node_unb1_fn_bf;
@@ -96,13 +111,18 @@ architecture str of node_unb1_fn_bf is
-----------------------------------------------------------------------------
-- Block generator
-----------------------------------------------------------------------------
- constant c_bg_block_size : natural := 96; -- 24 subbands * 4 signals
+ -- 24 subbands * 4 signals
+ constant c_bg_block_size : natural := 96;
constant c_bg_mem_high_addr : natural := c_bg_block_size-1;
- constant c_bg_gapsize : natural := 256 - c_bg_block_size; -- 256 = block period used in terminals
- constant c_bg_blocks_per_sync : natural := 32; -- Used for sim
- constant c_bg_ctrl : t_diag_block_gen := (sel_a_b(g_sim, '1', '0'), -- enable
- sel_a_b(g_sim, '0', '0'), -- enable_sync
+ -- 256 = block period used in terminals
+ constant c_bg_gapsize : natural := 256 - c_bg_block_size;
+ -- Used for sim
+ constant c_bg_blocks_per_sync : natural := 32;
+ -- enable
+ constant c_bg_ctrl : t_diag_block_gen := (sel_a_b(g_sim, '1', '0'),
+ -- enable_sync
+ sel_a_b(g_sim, '0', '0'),
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
@@ -124,9 +144,11 @@ begin
generic map(
g_use_usr_input => true,
g_use_bg => g_use_block_gen,
- g_nof_streams => g_bf.nof_input_streams, -- 16
+ -- 16
+ g_nof_streams => g_bf.nof_input_streams,
g_use_bg_buffer_ram => true,
- g_buf_dat_w => c_nof_complex * g_bf.in_dat_w, -- 2*16b=32b
+ -- 2*16b=32b
+ g_buf_dat_w => c_nof_complex * g_bf.in_dat_w,
g_buf_addr_w => ceil_log2(c_bg_block_size),
g_file_name_prefix => g_block_gen_file_prefix,
g_diag_block_gen_rst => c_bg_ctrl,
@@ -189,9 +211,12 @@ begin
in_sosi_arr => bf_in_sosi_arr,
in_siso_arr => ext_in_siso_arr,
- out_raw_sosi_arr => out_raw_sosi_arr, -- raw beamlets
- out_bst_sosi_arr => i_out_bst_sosi_arr, -- 16b beamlets
- out_qua_sosi_arr => out_qua_sosi_arr -- 8b beamlets
+ -- raw beamlets
+ out_raw_sosi_arr => out_raw_sosi_arr,
+ -- 16b beamlets
+ out_bst_sosi_arr => i_out_bst_sosi_arr,
+ -- 8b beamlets
+ out_qua_sosi_arr => out_qua_sosi_arr
);
end generate;
@@ -203,7 +228,8 @@ begin
generic map (
g_nof_streams => g_bf.nof_bf_units,
g_data_w => c_eth_data_w,
- g_block_size => g_bf.nof_weights, -- = 256
+ -- = 256
+ g_block_size => g_bf.nof_weights,
g_block_nof_sel_words => 20,
g_nof_words_per_pkt => 360,
g_hdr_nof_words => c_network_total_header_32b_nof_words,
@@ -226,7 +252,8 @@ begin
reg_dp_pkt_merge_miso => reg_dp_pkt_merge_miso,
dp_sosi_arr => i_out_bst_sosi_arr,
- dp_siso_arr => OPEN, -- No flow control, so we're instantiating an input FIFO.
+ -- No flow control, so we're instantiating an input FIFO.
+ dp_siso_arr => OPEN,
tx_sosi_arr => bf_out_offload_tx_sosi_arr(g_bf.nof_bf_units - 1 downto 0),
tx_siso_arr => bf_out_offload_tx_siso_arr(g_bf.nof_bf_units - 1 downto 0)
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
index 39ea6ff5eab751d7ea13b0e372324c0c5752feea..9df7569b8b45936a9e1aad5326841b4a6c6f1a46 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
@@ -38,21 +38,30 @@ entity unb1_fn_bf is
generic (
g_design_name : string := "unb1_fn_bf";
g_design_note : string := "UNUSED";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0; -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0;
g_bf : t_c_bf := c_bf
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -71,11 +80,14 @@ entity unb1_fn_bf is
end unb1_fn_bf;
architecture str of unb1_fn_bf is
- constant c_bf_offload : boolean := false; -- Offload BF out(0) datapath to 1GbE UDP TX port
+ -- Offload BF out(0) datapath to 1GbE UDP TX port
+ constant c_bf_offload : boolean := false;
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 0, 0, 0, 0, 0, 1);
- constant c_fw_version : t_unb1_board_fw_version := (2, 3); -- firmware version x.y
+ -- firmware version x.y
+ constant c_fw_version : t_unb1_board_fw_version := (2, 3);
constant c_nof_streams : natural := c_eth_nof_udp_ports;
- constant c_weights_write_only : boolean := true; -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
+ -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
+ constant c_weights_write_only : boolean := true;
-- Use default RAM inti files. The RAM init file for simulation lies one ../ level further way then for synthesis
constant c_bf_weights_file_name : string := "UNUSED";
@@ -123,12 +135,16 @@ architecture str of unb1_fn_bf is
-- eth1g
signal eth1g_tse_clk : std_logic;
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst;
signal eth1g_ram_miso : t_mem_miso;
signal eth1g_led : t_tech_tse_led;
@@ -235,7 +251,8 @@ begin
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
@@ -384,8 +401,10 @@ begin
ram_hdr_insert_mosi => ram_dp_ram_from_mm_mosi,
-- ST interface
- out_bst_sosi_arr => OPEN, -- 16b beamlets
- out_qua_sosi_arr => beams_sosi_arr, -- 8b beamlets
+ -- 16b beamlets
+ out_bst_sosi_arr => OPEN,
+ -- 8b beamlets
+ out_qua_sosi_arr => beams_sosi_arr,
-- DP offload of 16b beamlets to 1GbE via ctrl_unb_common
bf_out_offload_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd
index 2ab0d75b8dff6796229f04a989d97f0472f647ff..7524acb9685c9610cc8ccb489525ef864e99f5bf 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd
@@ -57,15 +57,18 @@ end tb_unb1_fn_bf;
architecture tb of tb_unb1_fn_bf is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 3; -- Front node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Front node 3
+ constant c_node_nr : natural := 3;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w ) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb1_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
+ -- 25 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 40 ns;
constant c_clk_period : time := 1 ns;
constant c_pps_period : natural := 1000;
@@ -90,28 +93,41 @@ architecture tb of tb_unb1_fn_bf is
signal sens_sda : std_logic;
-- Model I2C sensor slaves as on the UniBoard
- constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
+ -- MAX1618 address LOW LOW
+ constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000";
constant c_fpga_temp : integer := 60;
- constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001"; -- MAX1618 address MID LOW
+ -- MAX1618 address MID LOW
+ constant c_eth_temp_address : std_logic_vector(6 downto 0) := "0101001";
constant c_eth_temp : integer := 40;
- constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100"; -- LTC4260 address L L L
- constant c_hot_swap_R_sense : real := 0.01; -- = 10 mOhm on UniBoard
-
- constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
- constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
- constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
+ -- LTC4260 address L L L
+ constant c_hot_swap_address : std_logic_vector(6 downto 0) := "1000100";
+ -- = 10 mOhm on UniBoard
+ constant c_hot_swap_R_sense : real := 0.01;
+
+ -- = assume 5.0 A on UniBoard
+ constant c_uniboard_current : real := 5.0;
+ -- = assume 48.0 V on UniBoard
+ constant c_uniboard_supply : real := 48.0;
+ -- = NC on UniBoard
+ constant c_uniboard_adin : real := -1.0;
begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/libraries/dsp/bf/src/vhdl/bf.vhd b/libraries/dsp/bf/src/vhdl/bf.vhd
index ef5b683e186410b65348c3ca2a251c0fb23f9c86..409c7e672b79f7a5320e016d6e732e39a4484d58 100644
--- a/libraries/dsp/bf/src/vhdl/bf.vhd
+++ b/libraries/dsp/bf/src/vhdl/bf.vhd
@@ -37,8 +37,10 @@ entity bf is
generic (
g_bf : t_c_bf := c_bf;
g_bf_weights_file_name : string := "UNUSED";
- g_ss_wide_file_prefix : string := "UNUSED"; -- path_to_file
- g_weights_write_only : boolean := false -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
+ -- path_to_file
+ g_ss_wide_file_prefix : string := "UNUSED";
+ -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
+ g_weights_write_only : boolean := false
);
port (
-- System
@@ -52,24 +54,31 @@ entity bf is
ram_ss_ss_wide_miso : out t_mem_miso := c_mem_miso_rst;
ram_bf_weights_mosi : in t_mem_mosi;
ram_bf_weights_miso : out t_mem_miso := c_mem_miso_rst;
- ram_st_sst_mosi : in t_mem_mosi; -- Power statistics memory
+ -- Power statistics memory
+ ram_st_sst_mosi : in t_mem_mosi;
ram_st_sst_miso : out t_mem_miso := c_mem_miso_rst;
- reg_st_sst_mosi : in t_mem_mosi; -- Power statistics register
+ -- Power statistics register
+ reg_st_sst_mosi : in t_mem_mosi;
reg_st_sst_miso : out t_mem_miso := c_mem_miso_rst;
-- ST interface
- in_sosi_arr : in t_dp_sosi_arr(g_bf.nof_input_streams - 1 downto 0); -- subbands
+ -- subbands
+ in_sosi_arr : in t_dp_sosi_arr(g_bf.nof_input_streams - 1 downto 0);
in_siso_arr : out t_dp_siso_arr(g_bf.nof_input_streams - 1 downto 0);
- out_raw_sosi_arr : out t_dp_sosi_arr(g_bf.nof_bf_units - 1 downto 0); -- raw beamlets
- out_bst_sosi_arr : out t_dp_sosi_arr(g_bf.nof_bf_units - 1 downto 0); -- 16b beamlets
- out_qua_sosi_arr : out t_dp_sosi_arr(g_bf.nof_bf_units - 1 downto 0) -- 8b beamlets
+ -- raw beamlets
+ out_raw_sosi_arr : out t_dp_sosi_arr(g_bf.nof_bf_units - 1 downto 0);
+ -- 16b beamlets
+ out_bst_sosi_arr : out t_dp_sosi_arr(g_bf.nof_bf_units - 1 downto 0);
+ -- 8b beamlets
+ out_qua_sosi_arr : out t_dp_sosi_arr(g_bf.nof_bf_units - 1 downto 0)
);
end bf;
architecture str of bf is
constant c_frame_size_in : positive := g_bf.nof_subbands * g_bf.nof_signal_paths / g_bf.nof_input_streams;
constant c_reg_st_addr_w : positive := ceil_log2(2);
- constant c_ram_st_addr_w : positive := ceil_log2(g_bf.stat_data_sz * g_bf.nof_weights * c_nof_complex); -- The "c_nof_complex" is due to the crosslets capability.
+ -- The "c_nof_complex" is due to the crosslets capability.
+ constant c_ram_st_addr_w : positive := ceil_log2(g_bf.stat_data_sz * g_bf.nof_weights * c_nof_complex);
type t_in_siso_2arr is array (integer range <>) of t_dp_siso_arr(g_bf.nof_input_streams - 1 downto 0);
diff --git a/libraries/dsp/bf/src/vhdl/bf_pkg.vhd b/libraries/dsp/bf/src/vhdl/bf_pkg.vhd
index 380a12f18f61a46bb3ebbef6896d457156ac45b8..52e9ebc17c66e5cca4428021346104311f9c8899 100644
--- a/libraries/dsp/bf/src/vhdl/bf_pkg.vhd
+++ b/libraries/dsp/bf/src/vhdl/bf_pkg.vhd
@@ -26,30 +26,46 @@ use common_lib.common_pkg.all;
package bf_pkg is
constant c_bf_note_fifo_is_ful : boolean := true;
- constant c_bf_burst_nof_blocks : positive := 4; -- Use 1 for no initial burst, use > 1 to support initial blocks arriving in a burst (= c_nof_no_gap+1 in tb_bf.vhd)
- constant c_bf_max_nof_bf_units : natural := 4; -- Setting the maximum number of bf_units in a FPGA.
+ -- Use 1 for no initial burst, use > 1 to support initial blocks arriving in a burst (= c_nof_no_gap+1 in tb_bf.vhd)
+ constant c_bf_burst_nof_blocks : positive := 4;
+ -- Setting the maximum number of bf_units in a FPGA.
+ constant c_bf_max_nof_bf_units : natural := 4;
-- TYPE DECLARATIONS --------------------------------------------------------
-- Record definition that conatins all the generics that are used in the bf_unit
type t_c_bf is record
- nof_signal_paths : positive; -- = 64
- nof_input_streams : positive; -- = 16
- nof_subbands : positive; -- = 24
- nof_weights : positive; -- = 256
- nof_bf_units : positive; -- = 4
- in_dat_w : positive; -- = 16
- in_weight_w : positive; -- = 16
- bst_gain_w : integer; -- = 1
- bst_dat_w : positive; -- = 16
- out_gain_w : integer; -- = -5
- out_dat_w : positive; -- = 8
- stat_data_w : positive; -- = 56
- stat_data_sz : positive; -- = 2
+ -- = 64
+ nof_signal_paths : positive;
+ -- = 16
+ nof_input_streams : positive;
+ -- = 24
+ nof_subbands : positive;
+ -- = 256
+ nof_weights : positive;
+ -- = 4
+ nof_bf_units : positive;
+ -- = 16
+ in_dat_w : positive;
+ -- = 16
+ in_weight_w : positive;
+ -- = 1
+ bst_gain_w : integer;
+ -- = 16
+ bst_dat_w : positive;
+ -- = -5
+ out_gain_w : integer;
+ -- = 8
+ out_dat_w : positive;
+ -- = 56
+ stat_data_w : positive;
+ -- = 2
+ stat_data_sz : positive;
end record;
--CONSTANT c_bf : t_c_bf := (64, 16, 24, 256, 4, 16, 16, 1, 16, -5, 8, 56, 2); -- bst_gain_w= 1 for 16b and out_gain_w=-5 for 8b as in Fig 10 of RP1377 v0.41
- constant c_bf : t_c_bf := (64, 16, 24, 256, 4, 16, 16, 0, 16, -6, 18, 56, 2); -- preserve 1 more LSbits for the bst_dat and out_dat outputs
+ -- preserve 1 more LSbits for the bst_dat and out_dat outputs
+ constant c_bf : t_c_bf := (64, 16, 24, 256, 4, 16, 16, 0, 16, -6, 18, 56, 2);
end bf_pkg;
diff --git a/libraries/dsp/bf/src/vhdl/bf_unit.vhd b/libraries/dsp/bf/src/vhdl/bf_unit.vhd
index 73d202ae11ab5603fe1ddd39df97484d7e05e239..0902b5f17004120a24d579ef294a22d85f772647 100644
--- a/libraries/dsp/bf/src/vhdl/bf_unit.vhd
+++ b/libraries/dsp/bf/src/vhdl/bf_unit.vhd
@@ -58,9 +58,12 @@ entity bf_unit is
generic (
g_technology : natural := c_tech_select_default;
g_bf : t_c_bf := c_bf;
- g_bf_weights_file_name : string := "UNUSED"; -- "UNUSED" or relative path to e.g. the bf/build/data/weights hex file for adr_w=8 and dat_w=32
- g_ss_wide_file_prefix : string := "UNUSED"; -- path_to_file
- g_weights_write_only : boolean := false -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
+ -- "UNUSED" or relative path to e.g. the bf/build/data/weights hex file for adr_w=8 and dat_w=32
+ g_bf_weights_file_name : string := "UNUSED";
+ -- path_to_file
+ g_ss_wide_file_prefix : string := "UNUSED";
+ -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
+ g_weights_write_only : boolean := false
);
port (
-- System
@@ -74,28 +77,38 @@ entity bf_unit is
ram_ss_ss_wide_miso : out t_mem_miso := c_mem_miso_rst;
ram_bf_weights_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_bf_weights_miso : out t_mem_miso := c_mem_miso_rst;
- ram_st_sst_mosi : in t_mem_mosi := c_mem_mosi_rst; -- Power statistics memory
+ -- Power statistics memory
+ ram_st_sst_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_st_sst_miso : out t_mem_miso := c_mem_miso_rst;
- reg_st_sst_mosi : in t_mem_mosi := c_mem_mosi_rst; -- Power statistics register
+ -- Power statistics register
+ reg_st_sst_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_st_sst_miso : out t_mem_miso := c_mem_miso_rst;
-- ST interface
- in_sosi_arr : in t_dp_sosi_arr(g_bf.nof_input_streams - 1 downto 0); -- subbands; one or more signal paths per datapath input stream
+ -- subbands; one or more signal paths per datapath input stream
+ in_sosi_arr : in t_dp_sosi_arr(g_bf.nof_input_streams - 1 downto 0);
in_siso_arr : out t_dp_siso_arr(g_bf.nof_input_streams - 1 downto 0);
- out_raw_sosi : out t_dp_sosi; -- original raw beamlets output with c_sum_w bits.
- out_bst_sosi : out t_dp_sosi; -- requantized 16b beamlets output that is also used for internal BST.
- out_qua_sosi : out t_dp_sosi -- requantized 8b beamlets output.
+ -- original raw beamlets output with c_sum_w bits.
+ out_raw_sosi : out t_dp_sosi;
+ -- requantized 16b beamlets output that is also used for internal BST.
+ out_bst_sosi : out t_dp_sosi;
+ -- requantized 8b beamlets output.
+ out_qua_sosi : out t_dp_sosi
);
end bf_unit;
architecture str of bf_unit is
-- Operational mode:
- constant c_unit_w : positive := g_bf.in_dat_w + g_bf.in_weight_w - c_sign_w; -- skip double sign bit
- constant c_prod_w : positive := c_unit_w + c_sum_of_prod_w; -- keep bit for sum of products in complex multiply
- constant c_gain_w : integer := largest(g_bf.bst_gain_w, g_bf.out_gain_w); -- keep internal c_sum_w as wide as necessary to fit both BST and qua output
+ -- skip double sign bit
+ constant c_unit_w : positive := g_bf.in_dat_w + g_bf.in_weight_w - c_sign_w;
+ -- keep bit for sum of products in complex multiply
+ constant c_prod_w : positive := c_unit_w + c_sum_of_prod_w;
+ -- keep internal c_sum_w as wide as necessary to fit both BST and qua output
+ constant c_gain_w : integer := largest(g_bf.bst_gain_w, g_bf.out_gain_w);
-- no need to account for adder bit growth of ceil_log2(g_bf.nof_signal_paths),
-- because default BF sum should not clip to allow next stage of BF
- constant c_sum_w : positive := c_unit_w + c_gain_w; -- note use c_gain_w >= 1 if complex sum of products bit growth has to be preserved
+ -- note use c_gain_w >= 1 if complex sum of products bit growth has to be preserved
+ constant c_sum_w : positive := c_unit_w + c_gain_w;
constant c_bst_lsb_w : natural := c_unit_w + g_bf.bst_gain_w - g_bf.bst_dat_w;
constant c_out_lsb_w : natural := c_unit_w + g_bf.out_gain_w - g_bf.out_dat_w;
@@ -110,7 +123,8 @@ architecture str of bf_unit is
nof_dat => g_bf.nof_weights,
init_sl => '0');
-- Latencies
- constant c_input_latency : natural := 1; -- due to r
+ -- due to r
+ constant c_input_latency : natural := 1;
constant c_prod_latency : natural := 3;
constant c_adder_stage_latency : natural := 1;
constant c_nof_adder_stages : natural := ceil_log2(g_bf.nof_signal_paths);
@@ -136,25 +150,32 @@ architecture str of bf_unit is
signal dbg_c_bst_lsb_w : natural := c_bst_lsb_w;
signal dbg_c_out_lsb_w : natural := c_out_lsb_w;
- signal mult_miso_arr : t_mem_miso_arr(g_bf.nof_signal_paths - 1 downto 0) := (others => c_mem_miso_rst); -- MM interfaces between weights-memory and complex multipliers.
+ -- MM interfaces between weights-memory and complex multipliers.
+ signal mult_miso_arr : t_mem_miso_arr(g_bf.nof_signal_paths - 1 downto 0) := (others => c_mem_miso_rst);
signal r, rin : reg_type;
- signal ss_wide_in_sosi_arr : t_dp_sosi_arr( g_bf.nof_signal_paths - 1 downto 0); -- for each signal path a datapath stream interface.
- signal ss_wide_in_siso_arr : t_dp_siso_arr( g_bf.nof_signal_paths - 1 downto 0); -- for each signal path a datapath stream interface.
- signal bf_in_sosi_arr : t_dp_sosi_arr( g_bf.nof_signal_paths - 1 downto 0); -- for each signal path a datapath stream interface.
+ -- for each signal path a datapath stream interface.
+ signal ss_wide_in_sosi_arr : t_dp_sosi_arr( g_bf.nof_signal_paths - 1 downto 0);
+ -- for each signal path a datapath stream interface.
+ signal ss_wide_in_siso_arr : t_dp_siso_arr( g_bf.nof_signal_paths - 1 downto 0);
+ -- for each signal path a datapath stream interface.
+ signal bf_in_sosi_arr : t_dp_sosi_arr( g_bf.nof_signal_paths - 1 downto 0);
signal ram_ss_ss_wide_mosi_arr : t_mem_mosi_arr(g_bf.nof_input_streams - 1 downto 0);
signal ram_ss_ss_wide_miso_arr : t_mem_miso_arr(g_bf.nof_input_streams - 1 downto 0);
signal mm_bf_weights_miso : t_mem_miso := c_mem_miso_rst;
- signal mm_weight_mosi_arr : t_mem_mosi_arr(g_bf.nof_signal_paths - 1 downto 0); -- for each input a mm interface for writing the weight factors
- signal mm_weight_miso_arr : t_mem_miso_arr(g_bf.nof_signal_paths - 1 downto 0) := (others => c_mem_miso_rst); -- for each input a mm interface for writing the weight factors
+ -- for each input a mm interface for writing the weight factors
+ signal mm_weight_mosi_arr : t_mem_mosi_arr(g_bf.nof_signal_paths - 1 downto 0);
+ -- for each input a mm interface for writing the weight factors
+ signal mm_weight_miso_arr : t_mem_miso_arr(g_bf.nof_signal_paths - 1 downto 0) := (others => c_mem_miso_rst);
signal data_re_arr : t_slv_data_in_arr( g_bf.nof_signal_paths - 1 downto 0);
signal data_im_arr : t_slv_data_in_arr( g_bf.nof_signal_paths - 1 downto 0);
- signal weight_addr : std_logic_vector(c_weights_buf.adr_w - 1 downto 0); -- Address for the weight factors memory
+ -- Address for the weight factors memory
+ signal weight_addr : std_logic_vector(c_weights_buf.adr_w - 1 downto 0);
signal weight_re_arr : t_slv_weight_in_arr(g_bf.nof_signal_paths - 1 downto 0);
signal weight_im_arr : t_slv_weight_in_arr(g_bf.nof_signal_paths - 1 downto 0);
@@ -430,7 +451,8 @@ begin
g_lsb_w => c_bst_lsb_w,
g_lsb_round => true,
g_lsb_round_clip => false,
- g_msb_clip => false, -- default BF should not clip
+ -- default BF should not clip
+ g_msb_clip => false,
g_msb_clip_symmetric => false,
g_gain_w => 0,
g_pipeline_remove_lsb => 1,
@@ -456,7 +478,8 @@ begin
g_lsb_w => c_out_lsb_w,
g_lsb_round => true,
g_lsb_round_clip => false,
- g_msb_clip => false, -- default BF should not clip
+ -- default BF should not clip
+ g_msb_clip => false,
g_msb_clip_symmetric => false,
g_gain_w => 0,
g_pipeline_remove_lsb => 1,
diff --git a/libraries/dsp/bf/tb/vhdl/tb_bf.vhd b/libraries/dsp/bf/tb/vhdl/tb_bf.vhd
index c8b63bdf6879b3e3a3d4e3374c363a28e08a86bd..606fffb25619f59cc35ef805047d81ef10735158 100644
--- a/libraries/dsp/bf/tb/vhdl/tb_bf.vhd
+++ b/libraries/dsp/bf/tb/vhdl/tb_bf.vhd
@@ -52,21 +52,36 @@ use work.bf_pkg.all;
entity tb_bf is
generic(
- g_nof_signal_paths : positive := 64; -- = 64
- g_nof_input_streams : positive := 16; -- = 16
- g_nof_subbands : positive := 24; -- = 24
- g_nof_weights : positive := 256; -- = 256
- g_nof_bf_units : positive := 4; -- = 4
- g_in_dat_w : positive := 16; -- = 16
- g_in_weight_w : positive := 16; -- = 16
- g_bst_gain_w : integer := 1; -- = 1
- g_bst_dat_w : positive := 16; -- = 16
- g_out_gain_w : integer := -5; -- = -5
- g_out_dat_w : positive := 16; -- = 16
- g_stat_data_w : positive := 56; -- = 56
- g_stat_data_sz : positive := 2; -- = 2
- g_bf_weights_file_name : string := "../../../build/data/weights"; -- "UNUSED" or relative path to e.g. the bf/build/data/weights hex file for adr_w=8 and dat_w=32
- g_ss_wide_file_prefix : string := "../../../src/hex/ss_wide" -- path_to_file
+ -- = 64
+ g_nof_signal_paths : positive := 64;
+ -- = 16
+ g_nof_input_streams : positive := 16;
+ -- = 24
+ g_nof_subbands : positive := 24;
+ -- = 256
+ g_nof_weights : positive := 256;
+ -- = 4
+ g_nof_bf_units : positive := 4;
+ -- = 16
+ g_in_dat_w : positive := 16;
+ -- = 16
+ g_in_weight_w : positive := 16;
+ -- = 1
+ g_bst_gain_w : integer := 1;
+ -- = 16
+ g_bst_dat_w : positive := 16;
+ -- = -5
+ g_out_gain_w : integer := -5;
+ -- = 16
+ g_out_dat_w : positive := 16;
+ -- = 56
+ g_stat_data_w : positive := 56;
+ -- = 2
+ g_stat_data_sz : positive := 2;
+ -- "UNUSED" or relative path to e.g. the bf/build/data/weights hex file for adr_w=8 and dat_w=32
+ g_bf_weights_file_name : string := "../../../build/data/weights";
+ -- path_to_file
+ g_ss_wide_file_prefix : string := "../../../src/hex/ss_wide"
);
end tb_bf;
@@ -269,9 +284,12 @@ begin
-- ST interface
in_sosi_arr => bg_sosi_arr,
- out_raw_sosi_arr => beamlets_sosi_arr, -- raw beamlets
- out_bst_sosi_arr => OPEN, -- 16b beamlets
- out_qua_sosi_arr => open -- 8b beamlets
+ -- raw beamlets
+ out_raw_sosi_arr => beamlets_sosi_arr,
+ -- 16b beamlets
+ out_bst_sosi_arr => OPEN,
+ -- 8b beamlets
+ out_qua_sosi_arr => open
);
----------------------------------------------------------------------------
diff --git a/libraries/dsp/bf/tb/vhdl/tb_bf_unit.vhd b/libraries/dsp/bf/tb/vhdl/tb_bf_unit.vhd
index 185dbec54cd017a0870b0760a69f4a38bed9439a..dbdeaa956adc3afd9dc9ce8e59aae65d42f01c33 100644
--- a/libraries/dsp/bf/tb/vhdl/tb_bf_unit.vhd
+++ b/libraries/dsp/bf/tb/vhdl/tb_bf_unit.vhd
@@ -53,21 +53,36 @@ use work.bf_pkg.all;
entity tb_bf_unit is
generic(
- g_nof_signal_paths : positive := 64; -- = 64
- g_nof_input_streams : positive := 16; -- = 16
- g_nof_subbands : positive := 24; -- = 24
- g_nof_weights : positive := 256; -- = 256
- g_nof_bf_units : positive := 4; -- = 4
- g_in_dat_w : positive := 16; -- = 16
- g_in_weight_w : positive := 16; -- = 16
- g_bst_gain_w : integer := 1; -- = 1
- g_bst_dat_w : positive := 16; -- = 16
- g_out_gain_w : integer := -5; -- = -5
- g_out_dat_w : positive := 8; -- = 8
- g_stat_data_w : positive := 56; -- = 56
- g_stat_data_sz : positive := 2; -- = 2
- g_bf_weights_file_name : string := "data/weights"; -- "../../../src/hex/weights"; -- "UNUSED" or relative path to e.g. the bf/build/data/weights hex file for adr_w=8 and dat_w=32
- g_ss_wide_file_prefix : string := "data/ss_wide" -- "../../../src/hex/ss_wide" -- path_to_file
+ -- = 64
+ g_nof_signal_paths : positive := 64;
+ -- = 16
+ g_nof_input_streams : positive := 16;
+ -- = 24
+ g_nof_subbands : positive := 24;
+ -- = 256
+ g_nof_weights : positive := 256;
+ -- = 4
+ g_nof_bf_units : positive := 4;
+ -- = 16
+ g_in_dat_w : positive := 16;
+ -- = 16
+ g_in_weight_w : positive := 16;
+ -- = 1
+ g_bst_gain_w : integer := 1;
+ -- = 16
+ g_bst_dat_w : positive := 16;
+ -- = -5
+ g_out_gain_w : integer := -5;
+ -- = 8
+ g_out_dat_w : positive := 8;
+ -- = 56
+ g_stat_data_w : positive := 56;
+ -- = 2
+ g_stat_data_sz : positive := 2;
+ -- "../../../src/hex/weights"; -- "UNUSED" or relative path to e.g. the bf/build/data/weights hex file for adr_w=8 and dat_w=32
+ g_bf_weights_file_name : string := "data/weights";
+ -- "../../../src/hex/ss_wide" -- path_to_file
+ g_ss_wide_file_prefix : string := "data/ss_wide"
);
end tb_bf_unit;
@@ -140,7 +155,8 @@ architecture tb of tb_bf_unit is
constant c_bg_nof_output_streams : positive := c_bf.nof_input_streams;
constant c_bg_buf_dat_w : positive := c_nof_complex * c_bf.in_dat_w;
constant c_bg_buf_adr_w : positive := ceil_log2(c_bg_block_len);
- constant c_bg_data_file_prefix : string := "data/tb_bg_dat"; -- "../../../src/hex/tb_bg_dat";
+ -- "../../../src/hex/tb_bg_dat";
+ constant c_bg_data_file_prefix : string := "data/tb_bg_dat";
constant c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, c_bf.nof_input_streams, 1);
-- Configuration of the databuffers:
@@ -270,9 +286,12 @@ begin
-- ST interface
in_sosi_arr => bg_sosi_arr,
- out_raw_sosi => out_sosi_arr(0), -- original raw beamlets output with c_sum_w bits.
- out_bst_sosi => open, -- requantized 16b beamlets output that is also used for internal BST.
- out_qua_sosi => open -- requantized 8b beamlets output.
+ -- original raw beamlets output with c_sum_w bits.
+ out_raw_sosi => out_sosi_arr(0),
+ -- requantized 16b beamlets output that is also used for internal BST.
+ out_bst_sosi => open,
+ -- requantized 8b beamlets output.
+ out_qua_sosi => open
);
----------------------------------------------------------------------------
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
index 89a874799daa5ae35f72af8ba2667e81e4095ce3..48ead0f32db201e5853d8993774b3697354f86d4 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
@@ -31,7 +31,8 @@ use mm_lib.mm_file_unb_pkg.all;
entity mmm_unb1_correlator is
generic (
- g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
+ -- FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0
);
@@ -90,7 +91,8 @@ entity mmm_unb1_correlator is
end mmm_unb1_correlator;
architecture str of mmm_unb1_correlator is
- constant c_mm_clk_period : time := 8 ns; -- 125 MHz
+ -- 125 MHz
+ constant c_mm_clk_period : time := 8 ns;
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr < 4, "FN", "BN");
constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type = "BN", g_sim_node_nr - 4, g_sim_node_nr);
@@ -103,85 +105,164 @@ architecture str of mmm_unb1_correlator is
-----------------------------------------------------------------------------
component qsys_unb1_correlator is
port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- mm_clk : out std_logic; -- clk
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- tse_clk : out std_logic; -- clk
- epcs_clk : out std_logic; -- clk
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0); -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- c3_from_the_altpll_0 : out std_logic; -- export
- ram_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_read_export : out std_logic; -- export
- ram_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_write_export : out std_logic; -- export
- ram_diag_data_buf_address_export : out std_logic_vector(14 downto 0); -- export
- ram_diag_data_buf_clk_export : out std_logic; -- export
- ram_diag_data_buf_reset_export : out std_logic; -- export
- reg_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_read_export : out std_logic; -- export
- reg_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_write_export : out std_logic; -- export
- reg_diag_data_buf_address_export : out std_logic_vector(9 downto 0); -- export
- reg_diag_data_buf_clk_export : out std_logic; -- export
- reg_diag_data_buf_reset_export : out std_logic; -- export
+ -- export
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic;
+ -- clk
+ mm_clk : out std_logic;
+ -- export
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0);
+ -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_reset_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic;
+ -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ coe_read_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0);
+ -- export
+ coe_clk_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0);
+ -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_write_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0);
+ -- export
+ coe_write_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_write_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X';
+ -- export
+ coe_read_export_from_the_rom_system_info : out std_logic;
+ -- export
+ phasedone_from_the_altpll_0 : out std_logic;
+ -- reset_n
+ reset_n : in std_logic := 'X';
+ -- export
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic;
+ -- clk
+ clk_0 : in std_logic := 'X';
+ -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0);
+ -- clk
+ tse_clk : out std_logic;
+ -- clk
+ epcs_clk : out std_logic;
+ -- export
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0);
+ -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_read_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ out_port_from_the_pio_wdi : out std_logic;
+ -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic;
+ -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_write_export_from_the_reg_wdi : out std_logic;
+ -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ coe_read_export_from_the_pio_pps : out std_logic;
+ -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic;
+ -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0);
+ -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic;
+ -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X';
+ -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0);
+ -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0);
+ -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0);
+ -- export
+ areset_to_the_altpll_0 : in std_logic := 'X';
+ -- export
+ locked_from_the_altpll_0 : out std_logic;
+ -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0);
+ -- export
+ c3_from_the_altpll_0 : out std_logic;
+ -- export
+ ram_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ ram_diag_data_buf_read_export : out std_logic;
+ -- export
+ ram_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ ram_diag_data_buf_write_export : out std_logic;
+ -- export
+ ram_diag_data_buf_address_export : out std_logic_vector(14 downto 0);
+ -- export
+ ram_diag_data_buf_clk_export : out std_logic;
+ -- export
+ ram_diag_data_buf_reset_export : out std_logic;
+ -- export
+ reg_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ reg_diag_data_buf_read_export : out std_logic;
+ -- export
+ reg_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0);
+ -- export
+ reg_diag_data_buf_write_export : out std_logic;
+ -- export
+ reg_diag_data_buf_address_export : out std_logic_vector(9 downto 0);
+ -- export
+ reg_diag_data_buf_clk_export : out std_logic;
+ -- export
+ reg_diag_data_buf_reset_export : out std_logic;
clk_clk : in std_logic;
reset_reset_n : in std_logic;
altpll_1_c0_clk : out std_logic;
@@ -278,7 +359,8 @@ begin
-- the_pio_pps
coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1),
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd
index d71467e0f74c26618c366a39b3a6a180744c39c5..eb03e158a5172ca3dc165c3d4bc4466dce66d53c 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd
@@ -32,20 +32,29 @@ use dp_lib.dp_stream_pkg.all;
entity unb1_correlator is
generic (
g_design_name : string := "unb1_correlator";
- g_sim : boolean := false; -- Overridden by TB
+ -- Overridden by TB
+ g_sim : boolean := false;
g_sim_unb_nr : natural := 0;
g_sim_node_nr : natural := 0;
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- System Clock
- PPS : in std_logic; -- System Sync
- WDI : out std_logic; -- Watchdog Clear
- INTA : inout std_logic; -- FPGA interconnect line
- INTB : inout std_logic; -- FPGA interconnect line
+ -- System Clock
+ CLK : in std_logic;
+ -- System Sync
+ PPS : in std_logic;
+ -- Watchdog Clear
+ WDI : out std_logic;
+ -- FPGA interconnect line
+ INTA : inout std_logic;
+ -- FPGA interconnect line
+ INTB : inout std_logic;
-- Others
VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
@@ -105,12 +114,16 @@ architecture str of unb1_correlator is
-- eth1g
signal eth1g_tse_clk : std_logic;
signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal eth1g_tse_mosi : t_mem_mosi;
signal eth1g_tse_miso : t_mem_miso;
- signal eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal eth1g_reg_mosi : t_mem_mosi;
signal eth1g_reg_miso : t_mem_miso;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ signal eth1g_reg_interrupt : std_logic;
+ -- ETH rx frame and tx frame memory
+ signal eth1g_ram_mosi : t_mem_mosi;
signal eth1g_ram_miso : t_mem_miso;
-- Correlator
@@ -126,7 +139,8 @@ architecture str of unb1_correlator is
constant c_nof_visibilities : natural := (c_nof_inputs * (c_nof_inputs + 1)) / 2;
-- Gap size on the correlator input depends on the number of folds
- constant c_block_period : natural := 1; -- pow2(c_nof_pre_mult_folds); -- To do: figure out the block period as function of both folding factors.
+ -- pow2(c_nof_pre_mult_folds); -- To do: figure out the block period as function of both folding factors.
+ constant c_block_period : natural := 1;
-- Block generator
constant c_bg_block_size : natural := c_nof_channels * pow2(c_nof_input_folds);
@@ -139,8 +153,10 @@ architecture str of unb1_correlator is
-- it is not used by the correlator.
constant c_bg_blocks_per_sync : natural := largest(c_integration_period, c_nof_visibilities);
- constant c_bg_ctrl : t_diag_block_gen := ('1', -- enable
- '0', -- enable_sync
+ -- enable
+ constant c_bg_ctrl : t_diag_block_gen := ('1',
+ -- enable_sync
+ '0',
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
@@ -293,7 +309,8 @@ begin
g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
g_use_phy => c_use_phy,
g_aux => c_unb1_board_aux,
- g_dp_clk_use_pll => false -- Use altpll_1 in QSYS
+ -- Use altpll_1 in QSYS
+ g_dp_clk_use_pll => false
)
port map (
-- Clock an reset signals
@@ -309,7 +326,8 @@ begin
epcs_clk => '0',
dp_rst => dp_rst,
- dp_clk => OPEN, -- dp_clk,
+ -- dp_clk,
+ dp_clk => OPEN,
dp_pps => OPEN,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
@@ -337,7 +355,8 @@ begin
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
@@ -385,9 +404,11 @@ begin
mm_clk => mm_clk,
mm_locked => mm_locked,
- clk_clk => CLK, -- altpll_1 ref clk (200MHz)
+ -- altpll_1 ref clk (200MHz)
+ clk_clk => CLK,
clk_clk_in_reset_reset_n => xo_rst_n,
- altpll_1_c0_clk => dp_clk, -- altpll_1 output clock
+ -- altpll_1 output clock
+ altpll_1_c0_clk => dp_clk,
-- PIOs
pout_wdi => pout_wdi,
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd
index 2b9513a51598d494558f57275c15420f27c77d42..f8aa9746447c6eda543d51e0fd23138ad6929b6f 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd
@@ -37,15 +37,18 @@ end tb_unb1_correlator;
architecture tb of tb_unb1_correlator is
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 7; -- Back node 3
+ -- UniBoard 0
+ constant c_unb_nr : natural := 0;
+ -- Back node 3
+ constant c_node_nr : natural := 7;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_fw_version : t_unb1_board_fw_version := (1, 0);
constant c_cable_delay : time := 12 ns;
- constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
+ -- 25 MHz XO on UniBoard
+ constant c_eth_clk_period : time := 40 ns;
constant c_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
@@ -72,14 +75,20 @@ begin
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
+
+ -- pull up
+ INTA <= 'H';
+ -- pull up
+ INTB <= 'H';
+
+ -- pull up
+ sens_scl <= 'H';
+ -- pull up
+ sens_sda <= 'H';
------------------------------------------------------------------------------
-- External PPS
diff --git a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
index 2eb064ad70a2b65b2bbc596981df29897c5f83e9..583482fbc39133ebbad1138b3764cc187667c21d 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
@@ -38,11 +38,16 @@ use dp_lib.dp_stream_pkg.all;
entity corr_accumulator is
generic (
- g_nof_inputs : natural; -- Number of input streams
- g_nof_channels : natural; -- Number of running sums to keep per input stream
- g_nof_channel_accs : natural; -- Maximum number of timesamples to accumulate (per channel)
- g_data_w : natural; -- Complex input data width
- g_note_is_ful : boolean := false -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ -- Number of input streams
+ g_nof_inputs : natural;
+ -- Number of running sums to keep per input stream
+ g_nof_channels : natural;
+ -- Maximum number of timesamples to accumulate (per channel)
+ g_nof_channel_accs : natural;
+ -- Complex input data width
+ g_data_w : natural;
+ -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_note_is_ful : boolean := false
-- when FALSE no note reports, to speed up simulation and avoid many notes
);
port (
@@ -63,7 +68,8 @@ architecture str of corr_accumulator is
signal acc_cnt : std_logic_vector(ceil_log2(g_nof_channels) downto 0);
signal nxt_acc_cnt : std_logic_vector(ceil_log2(g_nof_channels) downto 0);
- signal corr_adder_snk_in_2arr_2 : t_dp_sosi_2arr_2(g_nof_inputs - 1 downto 0); -- Array of pairs
+ -- Array of pairs
+ signal corr_adder_snk_in_2arr_2 : t_dp_sosi_2arr_2(g_nof_inputs - 1 downto 0);
signal corr_adder_src_out_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
signal dp_fifo_sc_src_in_arr : t_dp_siso_arr(g_nof_inputs - 1 downto 0);
@@ -125,7 +131,8 @@ begin
g_note_is_ful => g_note_is_ful,
g_data_w => 2 * c_acc_data_w,
g_use_ctrl => false,
- g_use_sync => sel_a_b(i = 0, true, false), -- Pass on sync of stream 0.
+ -- Pass on sync of stream 0.
+ g_use_sync => sel_a_b(i = 0, true, false),
g_use_complex => true,
g_fifo_size => g_nof_channels,
g_fifo_af_margin => 1
diff --git a/libraries/dsp/correlator/src/vhdl/corr_carousel.vhd b/libraries/dsp/correlator/src/vhdl/corr_carousel.vhd
index 3664435b342150d9d410d0799427cd069b91b857..cbf3348389308e6202a1b597583595cf3b172251 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_carousel.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_carousel.vhd
@@ -54,7 +54,8 @@ entity corr_carousel is
snk_in_arr : in t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
snk_out_arr : out t_dp_siso_arr(g_nof_inputs - 1 downto 0) := (others => c_dp_siso_rdy);
- src_out_arr : out t_dp_sosi_2arr_2(g_nof_outputs - 1 downto 0) -- Array of pairs
+ -- Array of pairs
+ src_out_arr : out t_dp_sosi_2arr_2(g_nof_outputs - 1 downto 0)
);
end corr_carousel;
@@ -79,12 +80,14 @@ begin
-----------------------------------------------------------------------------
p_carousel: process(snk_in_arr, reg_out_2arr_2)
begin
- if snk_in_arr(0).valid = '1' then -- Take fresh set of input data
+ -- Take fresh set of input data
+ if snk_in_arr(0).valid = '1' then
for i in 0 to g_nof_inputs - 1 loop
nxt_reg_out_2arr_2(i)(0) <= snk_in_arr(i);
nxt_reg_out_2arr_2(i)(1) <= snk_in_arr(i);
end loop;
- else -- Shift around the current data; keep producing new permutations
+ -- Shift around the current data; keep producing new permutations
+ else
-- Top of carousel, shift left
nxt_reg_out_2arr_2(g_nof_inputs - 1)(1) <= reg_out_2arr_2(g_nof_inputs - 1)(0);
-- Left column of carousel, shift down
diff --git a/libraries/dsp/correlator/src/vhdl/corr_folder.vhd b/libraries/dsp/correlator/src/vhdl/corr_folder.vhd
index 99c1a7805c76892e654bf4ac0e501eeedfe24f61..723787e54c7c1e58cad121903a5f2f379860a8ba 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_folder.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_folder.vhd
@@ -38,10 +38,14 @@ use dp_lib.dp_stream_pkg.all;
entity corr_folder is
generic (
- g_nof_inputs : natural; -- Number of inputs
- g_nof_folds : integer := -1 -- >0: Number of folds;
- ); -- 0: Wire out to in;
- port ( -- <0: Fold until one output remains
+ -- Number of inputs
+ g_nof_inputs : natural;
+ -- >0: Number of folds;
+ g_nof_folds : integer := -1
+ -- 0: Wire out to in;
+ );
+ -- <0: Fold until one output remains
+ port (
rst : in std_logic;
clk : in std_logic;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd b/libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd
index 97a02c1aa40a723f2fcdf7ca1263bbdae81114e1..196fe89ef19f7fd5addbe2b171263deb15b8d6b3 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd
@@ -70,7 +70,8 @@ begin
g_variant => "IP",
g_in_a_w => g_data_w,
g_in_b_w => g_data_w,
- g_out_p_w => 2 * g_data_w, -- default use g_out_p_w = g_in_a_w+g_in_b_w
+ -- default use g_out_p_w = g_in_a_w+g_in_b_w
+ g_out_p_w => 2 * g_data_w,
g_conjugate_b => true,
g_pipeline_input => c_pipeline_input,
g_pipeline_product => c_pipeline_product,
diff --git a/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd b/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
index dffbdd2202051d045b196b1435423d0c3f2b2937..38313bf0a0e0c7ebfa627b7203a325f53c692eb3 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
@@ -36,12 +36,18 @@ use dp_lib.dp_stream_pkg.all;
entity corr_output_framer is
generic (
- g_nof_streams : natural; -- Number of input/output streams
- g_nof_folds : natural := 0; -- If >0, channel indices are folded accordingly
- g_nof_channels : natural; -- Number of channels
- g_nof_channel_frames_per_sync : natural; -- Number of channel frames (g_nof_channels long) per sync
- g_generate_sync_and_bsn : boolean; -- FALSE uses sync and BSN from snk_in_arr
- g_fft_channel_index_reorder : boolean -- TRUE if input data is FFT output that needs channel reordering
+ -- Number of input/output streams
+ g_nof_streams : natural;
+ -- If >0, channel indices are folded accordingly
+ g_nof_folds : natural := 0;
+ -- Number of channels
+ g_nof_channels : natural;
+ -- Number of channel frames (g_nof_channels long) per sync
+ g_nof_channel_frames_per_sync : natural;
+ -- FALSE uses sync and BSN from snk_in_arr
+ g_generate_sync_and_bsn : boolean;
+ -- TRUE if input data is FFT output that needs channel reordering
+ g_fft_channel_index_reorder : boolean
);
port (
rst : in std_logic;
@@ -121,11 +127,14 @@ begin
channel_bsn_src_out <= (c_dp_sosi_rst);
reg_dp_block_gen_src_out <= (c_dp_sosi_rst);
for i in 0 to g_nof_streams - 1 loop
- channel_bsn_src_out.channel <= X"FFFFFFFF"; -- Wrap to 0 on first increment
- channel_bsn_src_out.bsn <= X"FFFFFFFF_FFFFFFFF"; -- Wrap to 0 on first increment
+ -- Wrap to 0 on first increment
+ channel_bsn_src_out.channel <= X"FFFFFFFF";
+ -- Wrap to 0 on first increment
+ channel_bsn_src_out.bsn <= X"FFFFFFFF_FFFFFFFF";
-- channel_bsn_src_out.channel <= (OTHERS=>'0');
-- channel_bsn_src_out.bsn <= (OTHERS=>'0');
- folded_word_cnt <= (others => '1'); -- Wrap to 0 on first increment
+ -- Wrap to 0 on first increment
+ folded_word_cnt <= (others => '1');
end loop;
elsif rising_edge(clk) then
channel_bsn_src_out <= nxt_channel_bsn_src_out;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd b/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd
index 376b3babdd50144d0a7d13a230519ad9d3097ba6..fc6d6028d1e6285271e6ab19723833b28832c0a9 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd
@@ -52,7 +52,8 @@ entity corr_permutator is
snk_in_arr : in t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
- src_out_2arr_2 : out t_dp_sosi_2arr_2(g_nof_inputs * (g_nof_inputs + 1) / 2 - 1 downto 0) -- Array of pairs
+ -- Array of pairs
+ src_out_2arr_2 : out t_dp_sosi_2arr_2(g_nof_inputs * (g_nof_inputs + 1) / 2 - 1 downto 0)
);
end corr_permutator;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd b/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
index 9289aa48472f038e9d7e6332b842d12316209c46..213076adc95b0c5b1f312d57859ba81a80685094 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
@@ -35,9 +35,12 @@ use work.corr_permutor_pkg.all;
entity corr_permutor is
generic (
- g_nof_inputs : natural; -- e.g. 24 inputs yield (24*(24+1))/2=300 visibilities
- g_nof_outputs : natural; -- = nof_visibilities/g_nof_cycles
- g_nof_cycles : natural; -- = nof_visibilities/g_nof_outputs
+ -- e.g. 24 inputs yield (24*(24+1))/2=300 visibilities
+ g_nof_inputs : natural;
+ -- = nof_visibilities/g_nof_cycles
+ g_nof_outputs : natural;
+ -- = nof_visibilities/g_nof_outputs
+ g_nof_cycles : natural;
g_data_w : natural
);
port (
@@ -45,15 +48,18 @@ entity corr_permutor is
clk : in std_logic;
snk_in_arr : in t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
- snk_out_arr : out t_dp_siso_arr(g_nof_inputs - 1 downto 0); -- snk_out_arr(i).ready is low during processing when g_nof_cycles>1
+ -- snk_out_arr(i).ready is low during processing when g_nof_cycles>1
+ snk_out_arr : out t_dp_siso_arr(g_nof_inputs - 1 downto 0);
- src_out_2arr_2 : out t_dp_sosi_2arr_2(g_nof_outputs - 1 downto 0) -- Array of pairs
+ -- Array of pairs
+ src_out_2arr_2 : out t_dp_sosi_2arr_2(g_nof_outputs - 1 downto 0)
);
end corr_permutor;
architecture rtl of corr_permutor is
constant c_nof_permutations : natural := g_nof_inputs * (g_nof_inputs + 1) / 2;
- constant c_permutation_table : t_corr_permutation_table := corr_permute(g_nof_inputs, g_nof_cycles); -- Returns 3D array of dimensions nof_folding_cycles*g_nof_outputs*2 input indices
+ -- Returns 3D array of dimensions nof_folding_cycles*g_nof_outputs*2 input indices
+ constant c_permutation_table : t_corr_permutation_table := corr_permute(g_nof_inputs, g_nof_cycles);
type t_common_paged_reg_arr is array(g_nof_inputs - 1 downto 0) of std_logic_vector(g_data_w - 1 downto 0);
@@ -130,7 +136,8 @@ begin
p_permute: process(snk_in_arr, cycle_cnt, common_paged_reg_src_out_arr)
begin
for i in 0 to g_nof_outputs - 1 loop
- if snk_in_arr(0).valid = '1' then -- cycle_cnt=0
+ -- cycle_cnt=0
+ if snk_in_arr(0).valid = '1' then
-- First (or only) (folding) cycle; Take data present on snk_in_arr
nxt_perm_2arr_2(i)(0) <= snk_in_arr(c_permutation_table(0,i)(0));
nxt_perm_2arr_2(i)(1) <= snk_in_arr(c_permutation_table(0,i)(1));
diff --git a/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd b/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
index fe370e1429b7e61865a068a26a64c2f5785a2339..06d2df3ac924bbf25d379744664519d3de4f66a9 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
@@ -43,11 +43,13 @@ package body corr_permutor_pkg is
function corr_permute(nof_inputs : natural; nof_folding_cycles : natural) return t_corr_permutation_table is
constant c_nof_permutations : natural := nof_inputs * (nof_inputs + 1) / 2;
constant c_nof_outputs : natural := c_nof_permutations / nof_folding_cycles;
- constant c_input_index_arr : t_natural_arr(0 to nof_inputs - 1) := array_init(0, nof_inputs, 1); -- array_init resembles Python's range(nof_inputs). We're using a TO range because array_init also uses a TO range.
+ -- array_init resembles Python's range(nof_inputs). We're using a TO range because array_init also uses a TO range.
+ constant c_input_index_arr : t_natural_arr(0 to nof_inputs - 1) := array_init(0, nof_inputs, 1);
variable v_input_index_mat : t_integer_matrix(nof_inputs - 1 downto 0, nof_inputs - 1 downto 0);
variable v_out_index : natural;
variable v_duplicates : natural;
- variable v_output_index_mat : t_integer_matrix(c_nof_permutations - 1 downto 0, 2 - 1 downto 0); -- Array of permutation pairs
+ -- Array of permutation pairs
+ variable v_output_index_mat : t_integer_matrix(c_nof_permutations - 1 downto 0, 2 - 1 downto 0);
variable v_result : t_corr_permutation_table(nof_folding_cycles - 1 downto 0, c_nof_outputs - 1 downto 0);
begin
-----------------------------------------------------------------------------
diff --git a/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd b/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd
index dc3d2e83c14ef0c67fa2ebeb1d622f123cac2ef2..a374ec9299d4cc244268598253485b08b61a4a61 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd
@@ -30,8 +30,10 @@ use dp_lib.dp_stream_pkg.all;
entity corr_unfolder is
generic (
- g_nof_inputs : natural; -- Number of inputs
- g_nof_unfolds : natural := 0 -- Number of times to unfold
+ -- Number of inputs
+ g_nof_inputs : natural;
+ -- Number of times to unfold
+ g_nof_unfolds : natural := 0
);
port (
rst : in std_logic;
@@ -96,7 +98,8 @@ begin
gen_corr_folder: if g_nof_unfolds > 1 generate
u_corr_folder : corr_unfolder
generic map (
- g_nof_inputs => c_nof_demuxes * 2, -- Next stage has all our demux outputs as inputs
+ -- Next stage has all our demux outputs as inputs
+ g_nof_inputs => c_nof_demuxes * 2,
g_nof_unfolds => g_nof_unfolds - 1
)
port map (
diff --git a/libraries/dsp/correlator/src/vhdl/corr_visibility_buffer.vhd b/libraries/dsp/correlator/src/vhdl/corr_visibility_buffer.vhd
index 956bc3934e40d30a632009cd85a76eae0292167e..3b12ade84be820467fffb8d56fd4eb4cb46d23f2 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_visibility_buffer.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_visibility_buffer.vhd
@@ -39,11 +39,16 @@ use dp_lib.dp_stream_pkg.all;
entity corr_visibility_buffer is
generic (
- g_nof_inputs : natural; -- Number of input streams
- g_buffer_depth : natural; -- Number of words to buffer
- g_data_w : natural; -- Complex input data width
- g_nof_pre_mult_folds : natural; -- Nof times the data has been folded
- g_inter_channel_delay : natural -- Nof delay cycles between output channels
+ -- Number of input streams
+ g_nof_inputs : natural;
+ -- Number of words to buffer
+ g_buffer_depth : natural;
+ -- Complex input data width
+ g_data_w : natural;
+ -- Nof times the data has been folded
+ g_nof_pre_mult_folds : natural;
+ -- Nof delay cycles between output channels
+ g_inter_channel_delay : natural
);
port (
rst : in std_logic;
@@ -101,7 +106,8 @@ begin
generic map (
g_data_w => 2 * g_data_w,
g_use_ctrl => false,
- g_use_sync => sel_a_b(i = 0, true, false), -- Pass on sync of stream 0.
+ -- Pass on sync of stream 0.
+ g_use_sync => sel_a_b(i = 0, true, false),
g_use_complex => true,
g_fifo_size => g_buffer_depth,
g_fifo_af_margin => 0
@@ -148,7 +154,8 @@ begin
gen_dp_src_out_timer : for i in 0 to g_nof_inputs - 1 generate
u_dp_src_out_timer : entity dp_lib.dp_src_out_timer
generic map (
- g_init_valid_delay => i * c_vis_block_len, -- relative to dp_fifo_sc_src_out_arr(i).valid
+ -- relative to dp_fifo_sc_src_out_arr(i).valid
+ g_init_valid_delay => i * c_vis_block_len,
g_block_period => c_channel_block_length + g_inter_channel_delay,
g_block_len => c_vis_block_len
)
diff --git a/libraries/dsp/correlator/src/vhdl/correlator.vhd b/libraries/dsp/correlator/src/vhdl/correlator.vhd
index b460ccd574061463916d0d265a8dcdaabbb30199..f0beccfc99eeaf355e65af7c76815cce97a2f881 100644
--- a/libraries/dsp/correlator/src/vhdl/correlator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/correlator.vhd
@@ -34,14 +34,22 @@ use dp_lib.dp_stream_pkg.all;
entity correlator is
generic (
g_nof_input_streams : natural;
- g_input_unfold_factor : natural := 0; -- 2**g_input_unfold_factor = number of inputs carried on one input stream
- g_nof_pre_mult_folds : natural := 0; -- Number of pre-multiplier stage folds.
- g_data_w : natural := 16; -- Complex data width
- g_nof_channels : natural := 64; -- Number of (serial) channels per (parallel) input
- g_integration_period : natural := 0; -- Expressed as the number of samples per channel to accumulate
- g_inter_channel_delay : natural := 0; -- 0: Channels are output back to back. Set to >0 (cycles) for more constant output rate
- g_visibility_buffer_depth : natural := 0; -- 0: internally set to c_nof_accumulators. Use more depth e.g. in sim with shorter integration period.
- g_note_is_ful : boolean := false -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ -- 2**g_input_unfold_factor = number of inputs carried on one input stream
+ g_input_unfold_factor : natural := 0;
+ -- Number of pre-multiplier stage folds.
+ g_nof_pre_mult_folds : natural := 0;
+ -- Complex data width
+ g_data_w : natural := 16;
+ -- Number of (serial) channels per (parallel) input
+ g_nof_channels : natural := 64;
+ -- Expressed as the number of samples per channel to accumulate
+ g_integration_period : natural := 0;
+ -- 0: Channels are output back to back. Set to >0 (cycles) for more constant output rate
+ g_inter_channel_delay : natural := 0;
+ -- 0: internally set to c_nof_accumulators. Use more depth e.g. in sim with shorter integration period.
+ g_visibility_buffer_depth : natural := 0;
+ -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_note_is_ful : boolean := false
-- when FALSE no note reports, to speed up simulation and avoid many notes g_nof_inputs : NATURAL; -- Number of input streams
);
port (
@@ -50,7 +58,8 @@ entity correlator is
snk_in_arr : in t_dp_sosi_arr(g_nof_input_streams - 1 downto 0);
- src_out_arr : out t_dp_sosi_arr(1 - 1 downto 0) -- Single output for now
+ -- Single output for now
+ src_out_arr : out t_dp_sosi_arr(1 - 1 downto 0)
);
end correlator;
@@ -79,8 +88,10 @@ architecture str of correlator is
constant c_acc_data_w : natural := c_mult_output_w + ceil_log2(g_integration_period);
signal corr_unfolder_src_out_arr : t_dp_sosi_arr(c_nof_inputs - 1 downto 0);
- signal corr_permutator_src_out_2arr_2 : t_dp_sosi_2arr_2(c_nof_visibilities - 1 downto 0); -- Array of pairs
- signal corr_folder_src_out_2arr_2 : t_dp_sosi_2arr_2(c_nof_mults - 1 downto 0); -- Array of pairs, folded
+ -- Array of pairs
+ signal corr_permutator_src_out_2arr_2 : t_dp_sosi_2arr_2(c_nof_visibilities - 1 downto 0);
+ -- Array of pairs, folded
+ signal corr_folder_src_out_2arr_2 : t_dp_sosi_2arr_2(c_nof_mults - 1 downto 0);
signal corr_multiplier_src_out_arr : t_dp_sosi_arr(c_nof_mults - 1 downto 0);
signal corr_accumulator_src_out_arr : t_dp_sosi_arr(c_nof_mults - 1 downto 0);
signal corr_visibility_buffer_src_out_arr : t_dp_sosi_arr(c_nof_mults - 1 downto 0);
@@ -184,7 +195,8 @@ begin
g_nof_inputs => c_nof_mults,
g_nof_channels => c_nof_accumulators,
g_nof_channel_accs => g_integration_period,
- g_data_w => 2 * g_data_w, -- Multiplier output data width
+ -- Multiplier output data width
+ g_data_w => 2 * g_data_w,
g_note_is_ful => g_note_is_ful
)
port map (
diff --git a/libraries/dsp/correlator/src/vhdl/correlator_dev.vhd b/libraries/dsp/correlator/src/vhdl/correlator_dev.vhd
index 677ab17f96abeaed302ff12095dea7d5bf62fca3..f4ea0049fe039c25d3cdbd80a2b938401c9e82b8 100644
--- a/libraries/dsp/correlator/src/vhdl/correlator_dev.vhd
+++ b/libraries/dsp/correlator/src/vhdl/correlator_dev.vhd
@@ -56,19 +56,27 @@ use dp_lib.dp_stream_pkg.all;
entity correlator_dev is
generic (
- g_data_w : natural; -- Complex data width (of snk_in(i).re and snk_in(i).im)
- g_nof_inputs : natural; -- Number of inputs
- g_nof_mults : natural; -- Number of complex multipliers
- g_nof_cycles : natural; -- Number of cycles to produce all visibilities
- g_nof_channels : natural; -- Number of (serial) channels per (parallel) input
- g_nof_channel_accs : natural -- The maximum number of samples per channel that can be accumulated (determines accumulator width)
+ -- Complex data width (of snk_in(i).re and snk_in(i).im)
+ g_data_w : natural;
+ -- Number of inputs
+ g_nof_inputs : natural;
+ -- Number of complex multipliers
+ g_nof_mults : natural;
+ -- Number of cycles to produce all visibilities
+ g_nof_cycles : natural;
+ -- Number of (serial) channels per (parallel) input
+ g_nof_channels : natural;
+ -- The maximum number of samples per channel that can be accumulated (determines accumulator width)
+ g_nof_channel_accs : natural
);
port (
rst : in std_logic;
clk : in std_logic;
- snk_in_arr : in t_dp_sosi_arr(g_nof_inputs - 1 downto 0); -- Input data to be correlated must be valid at the same single cycle
- snk_out_arr : out t_dp_siso_arr(g_nof_inputs - 1 downto 0); -- snk_out_arr(i).ready is low during processing when g_nof_cycles>1
+ -- Input data to be correlated must be valid at the same single cycle
+ snk_in_arr : in t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
+ -- snk_out_arr(i).ready is low during processing when g_nof_cycles>1
+ snk_out_arr : out t_dp_siso_arr(g_nof_inputs - 1 downto 0);
src_out_arr : out t_dp_sosi_arr(g_nof_mults - 1 downto 0)
);
@@ -79,7 +87,8 @@ architecture str of correlator_dev is
constant c_mult_output_w : natural := 2 * g_data_w;
constant c_acc_data_w : natural := c_mult_output_w + ceil_log2(g_nof_channel_accs);
- signal corr_permutor_src_out_2arr_2 : t_dp_sosi_2arr_2(g_nof_mults - 1 downto 0); -- Array of (serialized) pairs
+ -- Array of (serialized) pairs
+ signal corr_permutor_src_out_2arr_2 : t_dp_sosi_2arr_2(g_nof_mults - 1 downto 0);
signal corr_multiplier_src_out_arr : t_dp_sosi_arr(g_nof_mults - 1 downto 0);
begin
-----------------------------------------------------------------------------
@@ -127,7 +136,8 @@ begin
g_nof_inputs => g_nof_mults,
g_nof_channels => c_nof_accumulators,
g_nof_channel_accs => g_nof_channel_accs,
- g_data_w => 2 * g_data_w -- = Multiplier output data width
+ -- = Multiplier output data width
+ g_data_w => 2 * g_data_w
)
port map (
clk => clk,
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd
index ddfce89f279cdd5308105a2eda304b5faef76cdf..473afd6cc39bbcab4271134514cf1e6ff86dbfcc 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd
@@ -35,7 +35,8 @@ entity tb_corr_accumulator is
g_nof_channels : natural := 8;
g_nof_channel_accs : natural := 16;
g_data_w : natural := 32;
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active
);
end tb_corr_accumulator;
@@ -57,7 +58,8 @@ architecture tb of tb_corr_accumulator is
signal pulse : std_logic;
signal random : std_logic_vector(14 downto 0) := (others => '0');
signal dp_gen_data_en : std_logic;
- signal dp_gen_data_src_in_arr : t_dp_siso_arr(g_nof_inputs - 1 downto 0) := (others => c_dp_siso_rdy); -- We're using dp_gen_data_en to introduce gaps.
+ -- We're using dp_gen_data_en to introduce gaps.
+ signal dp_gen_data_src_in_arr : t_dp_siso_arr(g_nof_inputs - 1 downto 0) := (others => c_dp_siso_rdy);
signal dp_gen_data_src_out_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
signal in_valid_count : natural;
signal nxt_in_valid_count : natural;
@@ -73,11 +75,15 @@ architecture tb of tb_corr_accumulator is
-----------------------------------------------------------------------------
-- Output verification
-----------------------------------------------------------------------------
- constant c_nof_input_cycles : natural := 12; -- Number of cycles before valid data is produces by adders
- constant c_nof_accumulation_cycles : natural := g_nof_channels * g_nof_channel_accs; -- Number of cycles before valid data is produces by accumulator
- constant c_nof_output_cycles : natural := g_nof_channels; -- Number of valid output cycles per integration period
+ -- Number of cycles before valid data is produces by adders
+ constant c_nof_input_cycles : natural := 12;
+ -- Number of cycles before valid data is produces by accumulator
+ constant c_nof_accumulation_cycles : natural := g_nof_channels * g_nof_channel_accs;
+ -- Number of valid output cycles per integration period
+ constant c_nof_output_cycles : natural := g_nof_channels;
constant c_nof_integration_periods : natural := 5;
- constant c_nof_req_valid_cycles : natural := c_nof_input_cycles + c_nof_accumulation_cycles + c_nof_output_cycles; -- Minimum valid input cycles to verify one integration period
+ -- Minimum valid input cycles to verify one integration period
+ constant c_nof_req_valid_cycles : natural := c_nof_input_cycles + c_nof_accumulation_cycles + c_nof_output_cycles;
constant c_output_data_w : natural := g_data_w + ceil_log2(g_nof_channel_accs);
signal expected_data : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0);
signal nxt_expected_data : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0);
@@ -176,7 +182,8 @@ begin
out_valid_count <= prv_out_valid_count;
for i in 0 to g_nof_inputs - 1 loop
- if corr_accumulator_src_out_arr(i).valid = '1' then -- Compare against expected data
+ -- Compare against expected data
+ if corr_accumulator_src_out_arr(i).valid = '1' then
assert corr_accumulator_src_out_arr(i).re = expected_data report "Expected real: " & slv_to_str(expected_data) & "; " & lf
& " Actual real: " & slv_to_str(corr_accumulator_src_out_arr(i).re) severity ERROR;
assert corr_accumulator_src_out_arr(i).im = expected_data report "Expected imag: " & slv_to_str(expected_data) & "; " & lf
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
index ee589c12ac72860640779d5dcaca91eddc08aad6..6bfc343590a0b711896245e427c9459e4e2bc377 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
@@ -39,8 +39,10 @@ entity tb_correlator is
generic (
g_nof_inputs : natural := 8;
g_nof_channels : natural := 8;
- g_nof_pre_mult_folds : natural := 1; -- Make sure c_nof_visibilities can be folded this many times
- g_nof_input_folds : natural := 1 -- =< g_nof_pre_mult_folds. Use an even g_nof_inputs.
+ -- Make sure c_nof_visibilities can be folded this many times
+ g_nof_pre_mult_folds : natural := 1;
+ -- =< g_nof_pre_mult_folds. Use an even g_nof_inputs.
+ g_nof_input_folds : natural := 1
);
end tb_correlator;
@@ -67,8 +69,10 @@ architecture tb of tb_correlator is
constant c_bg_blocks_per_sync : natural := c_integration_period;
- constant c_bg_ctrl : t_diag_block_gen := ('1', -- enable
- '0', -- enable_sync
+ -- enable
+ constant c_bg_ctrl : t_diag_block_gen := ('1',
+ -- enable_sync
+ '0',
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd b/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
index 2b5d9722394319eb1919df99a2ca358d57f4c41c..342f87b4b0b4433d8845e6bffce427f977169f94 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
@@ -45,7 +45,8 @@ entity tb_correlator_dev is
g_nof_cycles : natural := 2;
g_nof_channels : natural := 8;
g_nof_channel_accs : natural := 1000;
- g_flow_control_stimuli : t_dp_flow_control_enum := e_active -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active
);
end tb_correlator_dev;
@@ -67,7 +68,8 @@ architecture tb of tb_correlator_dev is
signal pulse : std_logic;
signal random : std_logic_vector(14 downto 0) := (others => '0');
signal dp_gen_data_en : std_logic;
- signal dp_gen_data_src_in_arr : t_dp_siso_arr(g_nof_inputs - 1 downto 0) := (others => c_dp_siso_rdy); -- We're using dp_gen_data_en to introduce gaps.
+ -- We're using dp_gen_data_en to introduce gaps.
+ signal dp_gen_data_src_in_arr : t_dp_siso_arr(g_nof_inputs - 1 downto 0) := (others => c_dp_siso_rdy);
signal dp_gen_data_src_out_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
signal in_valid_count : natural;
signal nxt_in_valid_count : natural;
@@ -85,7 +87,8 @@ architecture tb of tb_correlator_dev is
-- Output verification
-----------------------------------------------------------------------------
constant c_nof_permutations : natural := g_nof_inputs * (g_nof_inputs + 1) / 2;
- constant c_permutation_table : t_corr_permutation_table := corr_permute(g_nof_inputs, g_nof_cycles); -- Returns 3D array of dimensions nof_folding_cycles*g_nof_outputs*2 input indices
+ -- Returns 3D array of dimensions nof_folding_cycles*g_nof_outputs*2 input indices
+ constant c_permutation_table : t_corr_permutation_table := corr_permute(g_nof_inputs, g_nof_cycles);
signal out_valid_count : integer := 0;
-- SIGNAL nxt_out_valid_count : NATURAL;
@@ -135,8 +138,10 @@ begin
-----------------------------------------------------------------------------
gen_correlator_snk_in_arr : for i in 0 to g_nof_inputs - 1 generate
correlator_snk_in_arr(i).valid <= dp_gen_data_src_out_arr(i).valid;
- correlator_snk_in_arr(i).re <= TO_DP_DSP_DATA(i); -- Real = Input index
- correlator_snk_in_arr(i).im <= RESIZE_DP_DSP_DATA(dp_gen_data_src_out_arr(i).data); -- Imag = Channel index
+ -- Real = Input index
+ correlator_snk_in_arr(i).re <= TO_DP_DSP_DATA(i);
+ -- Imag = Channel index
+ correlator_snk_in_arr(i).im <= RESIZE_DP_DSP_DATA(dp_gen_data_src_out_arr(i).data);
-- Create a block sync of g_nof_channels wide
correlator_snk_in_arr(0).sync <= '1' when (in_valid_count >= (int_period_cnt + 1) * g_nof_channels * g_nof_channel_accs - g_nof_channels and
in_valid_count < (int_period_cnt + 1) * g_nof_channels * g_nof_channel_accs and
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_tb_corr_accumulator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_tb_corr_accumulator.vhd
index c9b1cb9b507a10d8c11c4d902a813df5a9c497e1..7f9530e94ab2d147555ae7929ddae7e70f00fd5b 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_tb_corr_accumulator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_tb_corr_accumulator.vhd
@@ -28,7 +28,8 @@ entity tb_tb_corr_accumulator is
end tb_tb_corr_accumulator;
architecture tb of tb_tb_corr_accumulator is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_nof_inputs
-- | g_nof_channelss
diff --git a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
index abd88be8522a176d72b78603322584ca6b1586d7..370f47f3a807f7f1828bf2694bc273f3b39e5e59 100644
--- a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
@@ -49,7 +49,8 @@ architecture rtl of fft_lfsr is
-- x^41 + x^20 + 1 and x^41 + x^3 + 1
-- see XAPP217
- constant c_len : natural := c_fft_lfsr_len; -- = 41, same for both trinomials
+ -- = 41, same for both trinomials
+ constant c_len : natural := c_fft_lfsr_len;
constant c1 : natural := 20;
constant c2 : natural := 3;
diff --git a/libraries/dsp/fft/src/vhdl/fft_pkg.vhd b/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
index 8dda8835b58237f265dff80a12a8cf12112d7bbb..d1c28b3dfdc73e619d4d7f58475567b79f6151b8 100644
--- a/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
@@ -43,31 +43,47 @@ package fft_pkg is
-- FFT parameters for pipelined FFT (fft_pipe), parallel FFT (fft_par) and wideband FFT (fft_wide)
type t_fft is record
- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
- use_fft_shift : boolean; -- = false for [0, pos, neg] bin frequencies order, true for [neg, 0, pos] bin frequencies order in case of complex input
- use_separate : boolean; -- = false for complex input, true for two real inputs
- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
- wb_factor : natural; -- = default 1, wideband factor
- twiddle_offset : natural; -- = default 0, twiddle offset for PFT sections in a wideband FFT
- nof_points : natural; -- = 1024, N point FFT
- in_dat_w : natural; -- = 8, number of input bits
- out_dat_w : natural; -- = 13, number of output bits
- out_gain_w : natural; -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
- stage_dat_w : natural; -- = 18, data width used between the stages(= DSP multiplier-width)
- guard_w : natural; -- = 2, guard used to avoid overflow in first FFT stage, compensated in last guard_w nof FFT stages.
+ -- = false for bit-reversed output, true for normal output
+ use_reorder : boolean;
+ -- = false for [0, pos, neg] bin frequencies order, true for [neg, 0, pos] bin frequencies order in case of complex input
+ use_fft_shift : boolean;
+ -- = false for complex input, true for two real inputs
+ use_separate : boolean;
+ -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
+ nof_chan : natural;
+ -- = default 1, wideband factor
+ wb_factor : natural;
+ -- = default 0, twiddle offset for PFT sections in a wideband FFT
+ twiddle_offset : natural;
+ -- = 1024, N point FFT
+ nof_points : natural;
+ -- = 8, number of input bits
+ in_dat_w : natural;
+ -- = 13, number of output bits
+ out_dat_w : natural;
+ -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
+ out_gain_w : natural;
+ -- = 18, data width used between the stages(= DSP multiplier-width)
+ stage_dat_w : natural;
+ -- = 2, guard used to avoid overflow in first FFT stage, compensated in last guard_w nof FFT stages.
+ guard_w : natural;
-- on average the gain per stage is 2 so guard_w = 1, but the gain can be 1+sqrt(2) [Lyons section
-- 12.3.2], therefore use input guard_w = 2.
- guard_enable : boolean; -- = true when input needs guarding, false when input requires no guarding but scaling must be
+ -- = true when input needs guarding, false when input requires no guarding but scaling must be
+ guard_enable : boolean;
-- skipped at the last stage(s) compensate for input guard (used in wb fft with pipe fft section
-- doing the input guard and par fft section doing the output compensation)
- stat_data_w : positive; -- = 56
- stat_data_sz : positive; -- = 2
+ -- = 56
+ stat_data_w : positive;
+ -- = 2
+ stat_data_sz : positive;
end record;
constant c_fft : t_fft := (true, false, true, 0, 4, 0, 1024, 8, 14, 0, c_dsp_mult_w, 2, true, 56, 2);
-- Check consistancy of the FFT parameters
- function fft_r2_parameter_asserts(g_fft : t_fft) return boolean; -- the return value is void, because always true or abort due to failure
+ -- the return value is void, because always true or abort due to failure
+ function fft_r2_parameter_asserts(g_fft : t_fft) return boolean;
-- FFT input width
function func_fft_in_scale_w(g_fft : t_fft) return natural;
@@ -79,11 +95,16 @@ package fft_pkg is
function func_fft_raw_fraction_w(g_fft : t_fft) return natural;
-- Definitions for fft slv array (an array can not have unconstraint elements, so choose sufficiently wide 32 bit slv elements)
- subtype t_fft_slv_arr is t_slv_32_arr; -- use subtype to ease interfacing to existing types and to have central definition for rtwo components
- constant c_fft_slv_w : natural := 32; -- match slv width of t_fft_slv_arr
- function to_fft_svec(n : integer) return std_logic_vector; -- map to c_fft_slv_w wide slv, no need for to_rtwo_uvec, because natural is subtype of integer
- function resize_fft_uvec(vec : std_logic_vector) return std_logic_vector; -- map to c_fft_slv_w wide slv
- function resize_fft_svec(vec : std_logic_vector) return std_logic_vector; -- map to c_fft_slv_w wide slv
+ -- use subtype to ease interfacing to existing types and to have central definition for rtwo components
+ subtype t_fft_slv_arr is t_slv_32_arr;
+ -- match slv width of t_fft_slv_arr
+ constant c_fft_slv_w : natural := 32;
+ -- map to c_fft_slv_w wide slv, no need for to_rtwo_uvec, because natural is subtype of integer
+ function to_fft_svec(n : integer) return std_logic_vector;
+ -- map to c_fft_slv_w wide slv
+ function resize_fft_uvec(vec : std_logic_vector) return std_logic_vector;
+ -- map to c_fft_slv_w wide slv
+ function resize_fft_svec(vec : std_logic_vector) return std_logic_vector;
-- FFT shift swaps right and left half of bin axis to shift zero-frequency component to center of spectrum
function fft_shift(bin : std_logic_vector) return std_logic_vector;
@@ -94,7 +115,8 @@ end package fft_pkg;
package body fft_pkg is
function fft_switch_new_seed(seed : std_logic_vector; offset : natural) return std_logic_vector is
begin
- return INCR_UVEC(seed, offset); -- make new unique seed
+ -- make new unique seed
+ return INCR_UVEC(seed, offset);
end;
function fft_r2_parameter_asserts(g_fft : t_fft) return boolean is
@@ -124,7 +146,8 @@ package body fft_pkg is
-- Raw output data width is equal to the internal data width of the FFT
function func_fft_raw_dat_w(g_fft : t_fft) return natural is
- constant c_sepa_growth_w : natural := sel_a_b(g_fft.use_separate, 1, 0); -- add one bit for add sub growth in separate
+ -- add one bit for add sub growth in separate
+ constant c_sepa_growth_w : natural := sel_a_b(g_fft.use_separate, 1, 0);
constant c_raw_dat_w : natural := g_fft.stage_dat_w + c_sepa_growth_w;
begin
return c_raw_dat_w;
@@ -157,7 +180,8 @@ package body fft_pkg is
constant c_w : natural := bin'length;
variable v_bin : std_logic_vector(c_w - 1 downto 0) := bin;
begin
- return not v_bin(c_w - 1) & v_bin(c_w - 2 downto 0); -- invert MSbit for fft_shift
+ -- invert MSbit for fft_shift
+ return not v_bin(c_w - 1) & v_bin(c_w - 2 downto 0);
end;
function fft_shift(bin, w : natural) return natural is
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_bf_par.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_bf_par.vhd
index a18e851babfef605c0eb1aac7ec1aca04e2c9923..c1941c087a2f1c8bb82bcece81f033da148518a6 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_bf_par.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_bf_par.vhd
@@ -42,7 +42,8 @@ entity fft_r2_bf_par is
g_element : natural := 1;
g_scale_enable : boolean := true;
-- internal pipeline settings
- g_pipeline : t_fft_pipeline := c_fft_pipeline -- defined in rTwoSDF_lib.rTwoSDFPkg
+ -- defined in rTwoSDF_lib.rTwoSDFPkg
+ g_pipeline : t_fft_pipeline := c_fft_pipeline
);
port (
clk : in std_logic;
@@ -65,10 +66,13 @@ architecture str of fft_r2_bf_par is
-- Scale enable is defined by generic.
constant c_stage_bit_growth : natural := sel_a_b(g_scale_enable, 1, 0);
- constant c_out_dat_w : natural := x_out_re'length; -- re and im have same width
+ -- re and im have same width
+ constant c_out_dat_w : natural := x_out_re'length;
- constant c_bf_in_a_zdly : natural := 0; -- No delays in bf_stage, since they only apply to one in- or output
- constant c_bf_out_b_zdly : natural := 0; -- No delays in bf_stage, since they only apply to one in- or output
+ -- No delays in bf_stage, since they only apply to one in- or output
+ constant c_bf_in_a_zdly : natural := 0;
+ -- No delays in bf_stage, since they only apply to one in- or output
+ constant c_bf_out_b_zdly : natural := 0;
signal sum_re : std_logic_vector(x_out_re'range);
signal sum_im : std_logic_vector(x_out_im'range);
@@ -252,7 +256,8 @@ begin
in_re => dif_out_re,
in_im => dif_out_im,
in_val => mul_in_val,
- in_sel => '1', -- Always select the multiplier output
+ -- Always select the multiplier output
+ in_sel => '1',
out_re => mul_out_re,
out_im => mul_out_im,
out_val => mul_out_val
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
index 622cd822b86b148e231af3346b28585b8521339b..9bb97ad964c28d2f89b921c6b2f122f04b9d6c0e 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
@@ -45,8 +45,10 @@ use work.fft_pkg.all;
entity fft_r2_par is
generic (
- g_fft : t_fft := c_fft; -- generics for the FFT
- g_pipeline : t_fft_pipeline := c_fft_pipeline -- generics for pipelining, defined in rTwoSDF_lib.rTwoSDFPkg
+ -- generics for the FFT
+ g_fft : t_fft := c_fft;
+ -- generics for pipelining, defined in rTwoSDF_lib.rTwoSDFPkg
+ g_pipeline : t_fft_pipeline := c_fft_pipeline
);
port (
clk : in std_logic;
@@ -98,24 +100,34 @@ architecture str of fft_r2_par is
-- input element odd => output = element.
function func_butterfly_connect(array_index, stage, nr_of_points : natural) return natural is
- variable v_nr_of_domains : natural; -- Variable that represents the number of "even" areas.
- variable v_return : natural; -- Holds the return value
- variable v_offset : natural; -- Offset
+ -- Variable that represents the number of "even" areas.
+ variable v_nr_of_domains : natural;
+ -- Holds the return value
+ variable v_return : natural;
+ -- Offset
+ variable v_offset : natural;
begin
v_nr_of_domains := nr_of_points / 2**(stage+1);
v_offset := 2**stage;
for I in 0 to v_nr_of_domains loop
- if array_index >= (2 * I) * 2**stage and array_index < (2 * I + 1) * 2**stage then -- Detect if output is an even section
- if (array_index mod 2) = 0 then -- Check if input value is odd or even
- v_return := array_index; -- When even: value of element
+ -- Detect if output is an even section
+ if array_index >= (2 * I) * 2**stage and array_index < (2 * I + 1) * 2**stage then
+ -- Check if input value is odd or even
+ if (array_index mod 2) = 0 then
+ -- When even: value of element
+ v_return := array_index;
else
- v_return := array_index + v_offset - 1; -- When odd: value of element + offset
+ -- When odd: value of element + offset
+ v_return := array_index + v_offset - 1;
end if;
elsif array_index >= (2 * I + 1) * 2**stage and array_index < (2 * I + 2) * 2**stage then
- if (array_index mod 2) = 0 then -- Check if input value is odd or even
- v_return := array_index - v_offset + 1; -- When even: offset is subtracted from the element
+ -- Check if input value is odd or even
+ if (array_index mod 2) = 0 then
+ -- When even: offset is subtracted from the element
+ v_return := array_index - v_offset + 1;
else
- v_return := array_index; -- When odd: element stays the the same.
+ -- When odd: element stays the the same.
+ v_return := array_index;
end if;
end if;
end loop;
@@ -300,10 +312,14 @@ begin
result => sub_arr(2 * I + 1)
);
- fft_re_arr(2 * I ) <= add_arr(2 * I )(c_raw_dat_w - 1 downto 0); -- A real
- fft_re_arr(2 * I + 1) <= add_arr(2 * I + 1)(c_raw_dat_w - 1 downto 0); -- B real
- fft_im_arr(2 * I ) <= sub_arr(2 * I )(c_raw_dat_w - 1 downto 0); -- A imag
- fft_im_arr(2 * I + 1) <= sub_arr(2 * I + 1)(c_raw_dat_w - 1 downto 0); -- B imag
+ -- A real
+ fft_re_arr(2 * I ) <= add_arr(2 * I )(c_raw_dat_w - 1 downto 0);
+ -- B real
+ fft_re_arr(2 * I + 1) <= add_arr(2 * I + 1)(c_raw_dat_w - 1 downto 0);
+ -- A imag
+ fft_im_arr(2 * I ) <= sub_arr(2 * I )(c_raw_dat_w - 1 downto 0);
+ -- B imag
+ fft_im_arr(2 * I + 1) <= sub_arr(2 * I + 1)(c_raw_dat_w - 1 downto 0);
end generate;
---------------------------------------------------------------------------
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
index 1df364ce44b5bc1b01a6bbc1834ef07e3020a856..5f8590b0604c3d4ef6544d1c2e2771c3bbf8c6d5 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
@@ -78,10 +78,14 @@ use work.fft_pkg.all;
entity fft_r2_pipe is
generic (
- g_instance_index : natural := 0; -- used for FFT switch seed
- g_fft : t_fft := c_fft; -- generics for the FFT
- g_pipeline : t_fft_pipeline := c_fft_pipeline; -- generics for pipelining in each stage, defined in rTwoSDF_lib.rTwoSDFPkg
- g_dont_flip_channels : boolean := false -- generic to prevent re-ordering of the channels
+ -- used for FFT switch seed
+ g_instance_index : natural := 0;
+ -- generics for the FFT
+ g_fft : t_fft := c_fft;
+ -- generics for pipelining in each stage, defined in rTwoSDF_lib.rTwoSDFPkg
+ g_pipeline : t_fft_pipeline := c_fft_pipeline;
+ -- generic to prevent re-ordering of the channels
+ g_dont_flip_channels : boolean := false
);
port (
clk : in std_logic;
@@ -99,21 +103,26 @@ entity fft_r2_pipe is
end entity fft_r2_pipe;
architecture str of fft_r2_pipe is
- constant c_pipeline_remove_lsb : natural := 1; -- to easy timing closure
+ -- to easy timing closure
+ constant c_pipeline_remove_lsb : natural := 1;
- constant c_switch_en : boolean := g_fft.use_separate; -- default do apply switch/unswitch per real input to mitigate quantization crosstalk
+ -- default do apply switch/unswitch per real input to mitigate quantization crosstalk
+ constant c_switch_en : boolean := g_fft.use_separate;
constant c_switch_sz_w : natural := ceil_log2(g_fft.nof_points) + g_fft.nof_chan;
- constant c_switch_dat_w : natural := g_fft.in_dat_w + 1; -- add 1 extra bit to fit negation of most negative value per real input switch function
+ -- add 1 extra bit to fit negation of most negative value per real input switch function
+ constant c_switch_dat_w : natural := g_fft.in_dat_w + 1;
constant c_switch_seed1 : std_logic_vector(c_fft_lfsr_len - 1 downto 0) := fft_switch_new_seed(c_fft_switch_seed1, g_instance_index);
constant c_switch_seed2 : std_logic_vector(c_fft_lfsr_len - 1 downto 0) := fft_switch_new_seed(c_fft_switch_seed2, g_instance_index);
constant c_nof_stages : natural := ceil_log2(g_fft.nof_points);
- constant c_stage_offset : natural := true_log2(g_fft.wb_factor); -- Stage offset is required for twiddle generation in wideband fft
+ -- Stage offset is required for twiddle generation in wideband fft
+ constant c_stage_offset : natural := true_log2(g_fft.wb_factor);
constant c_in_scale_w : natural := func_fft_in_scale_w(g_fft);
constant c_raw_fraction_w : natural := func_fft_raw_fraction_w(g_fft);
constant c_raw_dat_w : natural := func_fft_raw_dat_w(g_fft);
- constant c_unswitch_dat_w : natural := c_raw_dat_w; -- no need for extra bit, because most negative value cannot occur in FFT output
+ -- no need for extra bit, because most negative value cannot occur in FFT output
+ constant c_unswitch_dat_w : natural := c_raw_dat_w;
-- number the stage instances from c_nof_stages:1
-- . the data input for the first stage has index c_nof_stages
@@ -246,9 +255,11 @@ begin
port map (
clk => clk,
rst => rst,
- in_dat => in_cplx, -- c_nof_complex * g_fft.stage_dat_w
+ -- c_nof_complex * g_fft.stage_dat_w
+ in_dat => in_cplx,
in_val => data_val(0),
- out_dat => out_cplx, -- c_nof_complex * c_raw_dat_w
+ -- c_nof_complex * c_raw_dat_w
+ out_dat => out_cplx,
out_val => fft_out_val
);
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd
index d2401d7cf4e0459e3702e84689f29cbbd1e263e2..853cd9a22519553acde621c6d66bc7a54cfc5142 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd
@@ -75,14 +75,18 @@ use work.fft_pkg.all;
entity fft_r2_wide is
generic (
- g_fft : t_fft := c_fft; -- generics for the FFT
- g_pft_pipeline : t_fft_pipeline := c_fft_pipeline; -- For the pipelined part, from rTwoSDF_lib.rTwoSDFPkg
- g_fft_pipeline : t_fft_pipeline := c_fft_pipeline -- For the parallel part, from rTwoSDF_lib.rTwoSDFPkg
+ -- generics for the FFT
+ g_fft : t_fft := c_fft;
+ -- For the pipelined part, from rTwoSDF_lib.rTwoSDFPkg
+ g_pft_pipeline : t_fft_pipeline := c_fft_pipeline;
+ -- For the parallel part, from rTwoSDF_lib.rTwoSDFPkg
+ g_fft_pipeline : t_fft_pipeline := c_fft_pipeline
);
port (
clk : in std_logic;
rst : in std_logic := '0';
- in_re_arr : in t_fft_slv_arr(g_fft.wb_factor - 1 downto 0); -- = time samples t3, t2, t1, t0
+ -- = time samples t3, t2, t1, t0
+ in_re_arr : in t_fft_slv_arr(g_fft.wb_factor - 1 downto 0);
in_im_arr : in t_fft_slv_arr(g_fft.wb_factor - 1 downto 0);
in_val : in std_logic := '1';
out_re_arr : out t_fft_slv_arr(g_fft.wb_factor - 1 downto 0);
@@ -92,7 +96,8 @@ entity fft_r2_wide is
end entity fft_r2_wide;
architecture rtl of fft_r2_wide is
- type t_fft_arr is array(integer range <> ) of t_fft; -- An array of t_fft's generics.
+ -- An array of t_fft's generics.
+ type t_fft_arr is array(integer range <> ) of t_fft;
----------------------------------------------------------
-- This function creates an array of t_fft generics
@@ -103,20 +108,32 @@ architecture rtl of fft_r2_wide is
-- the nof_points.
----------------------------------------------------------
function func_create_generic_for_pipe_fft(input : t_fft) return t_fft_arr is
- variable v_nof_points : natural := input.nof_points / input.wb_factor; -- The nof_points for the pipelined fft stages
- variable v_return : t_fft_arr(input.wb_factor - 1 downto 0) := (others => input); -- Variable that holds the return values
+ -- The nof_points for the pipelined fft stages
+ variable v_nof_points : natural := input.nof_points / input.wb_factor;
+ -- Variable that holds the return values
+ variable v_return : t_fft_arr(input.wb_factor - 1 downto 0) := (others => input);
begin
for I in 0 to input.wb_factor - 1 loop
- v_return(I).use_reorder := input.use_reorder; -- Pass on use_reorder
- v_return(I).use_fft_shift := false; -- FFT shift function is forced to false
- v_return(I).use_separate := false; -- Separate function is forced to false.
- v_return(I).twiddle_offset := I; -- Twiddle offset is set to the order number of the pipelined fft.
- v_return(I).nof_points := v_nof_points; -- Set the nof points
- v_return(I).in_dat_w := input.stage_dat_w; -- Set the input width
- v_return(I).out_dat_w := input.stage_dat_w; -- Set the output width.
- v_return(I).out_gain_w := 0; -- Output gain is forced to 0
- v_return(I).guard_w := 0; -- Set the guard_w to 0 to enable scaling at every stage.
- v_return(I).guard_enable := false; -- No input guard.
+ -- Pass on use_reorder
+ v_return(I).use_reorder := input.use_reorder;
+ -- FFT shift function is forced to false
+ v_return(I).use_fft_shift := false;
+ -- Separate function is forced to false.
+ v_return(I).use_separate := false;
+ -- Twiddle offset is set to the order number of the pipelined fft.
+ v_return(I).twiddle_offset := I;
+ -- Set the nof points
+ v_return(I).nof_points := v_nof_points;
+ -- Set the input width
+ v_return(I).in_dat_w := input.stage_dat_w;
+ -- Set the output width.
+ v_return(I).out_dat_w := input.stage_dat_w;
+ -- Output gain is forced to 0
+ v_return(I).out_gain_w := 0;
+ -- Set the guard_w to 0 to enable scaling at every stage.
+ v_return(I).guard_w := 0;
+ -- No input guard.
+ v_return(I).guard_enable := false;
end loop;
return v_return;
end;
@@ -127,18 +144,29 @@ architecture rtl of fft_r2_wide is
-- belongs to the fft_r2_wide entity.
----------------------------------------------------------
function func_create_generic_for_par_fft(input : t_fft) return t_fft is
- variable v_return : t_fft := input; -- Variable that holds the return value
+ -- Variable that holds the return value
+ variable v_return : t_fft := input;
begin
- v_return.use_reorder := input.use_reorder; -- Pass on use_reorder
- v_return.use_fft_shift := input.use_fft_shift; -- Pass on use_fft_shift
- v_return.use_separate := false; -- Separate function is forced to false, because it is handled outside the parallel fft
- v_return.twiddle_offset := 0; -- Twiddle offset is forced to 0, which is also the input.twiddle_offset default
- v_return.nof_points := input.wb_factor; -- Set the number of points to wb_factor
- v_return.in_dat_w := input.stage_dat_w; -- Specify the input width
- v_return.out_dat_w := input.stage_dat_w; -- Output width
- v_return.out_gain_w := 0; -- Output gain is forced to 0, because it is handled outside the parallel fft
- v_return.guard_w := input.guard_w; -- Set the guard_w here to skip the scaling on the last stages
- v_return.guard_enable := false; -- No input guard.
+ -- Pass on use_reorder
+ v_return.use_reorder := input.use_reorder;
+ -- Pass on use_fft_shift
+ v_return.use_fft_shift := input.use_fft_shift;
+ -- Separate function is forced to false, because it is handled outside the parallel fft
+ v_return.use_separate := false;
+ -- Twiddle offset is forced to 0, which is also the input.twiddle_offset default
+ v_return.twiddle_offset := 0;
+ -- Set the number of points to wb_factor
+ v_return.nof_points := input.wb_factor;
+ -- Specify the input width
+ v_return.in_dat_w := input.stage_dat_w;
+ -- Output width
+ v_return.out_dat_w := input.stage_dat_w;
+ -- Output gain is forced to 0, because it is handled outside the parallel fft
+ v_return.out_gain_w := 0;
+ -- Set the guard_w here to skip the scaling on the last stages
+ v_return.guard_w := input.guard_w;
+ -- No input guard.
+ v_return.guard_enable := false;
return v_return;
end;
@@ -163,7 +191,8 @@ architecture rtl of fft_r2_wide is
signal out_fft_pipe_im_arr : t_fft_slv_arr(g_fft.wb_factor - 1 downto 0);
signal out_fft_pipe_val : std_logic_vector(g_fft.wb_factor - 1 downto 0);
- signal in_fft_par : std_logic; -- = out_fft_pipe_val(0)
+ -- = out_fft_pipe_val(0)
+ signal in_fft_par : std_logic;
signal in_fft_par_re_arr : t_fft_slv_arr(g_fft.wb_factor - 1 downto 0);
signal in_fft_par_im_arr : t_fft_slv_arr(g_fft.wb_factor - 1 downto 0);
@@ -239,8 +268,10 @@ begin
gen_pipelined_ffts : for I in g_fft.wb_factor - 1 downto 0 generate
u_pft : entity work.fft_r2_pipe
generic map (
- g_fft => c_fft_r2_pipe_arr(I), -- generics for the pipelined FFTs
- g_pipeline => g_pft_pipeline -- pipeline generics for the pipelined FFTs
+ -- generics for the pipelined FFTs
+ g_fft => c_fft_r2_pipe_arr(I),
+ -- pipeline generics for the pipelined FFTs
+ g_pipeline => g_pft_pipeline
)
port map (
clk => clk,
@@ -270,8 +301,10 @@ begin
-- to the input of a single parallel FFT.
u_fft : entity work.fft_r2_par
generic map (
- g_fft => c_fft_r2_par, -- generics for the FFT
- g_pipeline => g_fft_pipeline -- pipeline generics for the parallel FFT
+ -- generics for the FFT
+ g_fft => c_fft_r2_par,
+ -- pipeline generics for the parallel FFT
+ g_pipeline => g_fft_pipeline
)
port map (
clk => clk,
diff --git a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
index 36d0e53f0d279d8a5c60b57a5345f9e9dc68d65d..77aabbbf603245aafcfb761b94776bd924f173c7 100644
--- a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
@@ -42,18 +42,25 @@ use work.fft_pkg.all;
entity fft_reorder_sepa_pipe is
generic (
g_nof_points : natural := 8;
- g_bit_flip : boolean := true; -- apply index flip to have bins in incrementing frequency order
- g_fft_shift : boolean := false; -- apply fft_shift to have negative bin frequencies first for complex input
- g_dont_flip_channels : boolean := false; -- set true to preserve the channel interleaving when g_bit_flip is true, otherwise the channels get separated in time when g_bit_flip is true
- g_separate : boolean := true; -- apply separation bins for two real inputs
- g_nof_chan : natural := 0 -- Exponent of nr of subbands (0 means 1 subband, 1 => 2 sb, 2 => 4 sb, etc )
+ -- apply index flip to have bins in incrementing frequency order
+ g_bit_flip : boolean := true;
+ -- apply fft_shift to have negative bin frequencies first for complex input
+ g_fft_shift : boolean := false;
+ -- set true to preserve the channel interleaving when g_bit_flip is true, otherwise the channels get separated in time when g_bit_flip is true
+ g_dont_flip_channels : boolean := false;
+ -- apply separation bins for two real inputs
+ g_separate : boolean := true;
+ -- Exponent of nr of subbands (0 means 1 subband, 1 => 2 sb, 2 => 4 sb, etc )
+ g_nof_chan : natural := 0
);
port (
clk : in std_logic;
rst : in std_logic;
- in_dat : in std_logic_vector; -- c_dat_w (Im & Re)
+ -- c_dat_w (Im & Re)
+ in_dat : in std_logic_vector;
in_val : in std_logic;
- out_dat : out std_logic_vector; -- c_dat_w when g_separate = false, else c_dat_w + 2 (Im & Re, with 1 extra bit for both)
+ -- c_dat_w when g_separate = false, else c_dat_w + 2 (Im & Re, with 1 extra bit for both)
+ out_dat : out std_logic_vector;
out_val : out std_logic
);
end entity fft_reorder_sepa_pipe;
@@ -83,7 +90,8 @@ architecture rtl of fft_reorder_sepa_pipe is
signal rd_en : std_logic;
signal rd_adr_up : std_logic_vector(c_adr_points_w downto 0);
- signal rd_adr_down : std_logic_vector(c_adr_points_w downto 0); -- use intermediate rd_adr_down that has 1 bit extra to avoid truncation warning with TO_UVEC()
+ -- use intermediate rd_adr_down that has 1 bit extra to avoid truncation warning with TO_UVEC()
+ signal rd_adr_down : std_logic_vector(c_adr_points_w downto 0);
signal rd_adr : std_logic_vector(c_adr_tot_w - 1 downto 0);
signal rd_dat : std_logic_vector(c_dat_w - 1 downto 0);
signal rd_val : std_logic;
@@ -94,12 +102,18 @@ architecture rtl of fft_reorder_sepa_pipe is
type state_type is (s_idle, s_run_separate, s_run_normal);
type reg_type is record
- rd_en : std_logic; -- The read enable signal to read out the data from the dp memory
- switch : std_logic; -- Toggel register used for separate functionalilty
- count_up : natural; -- An upwards counter for read addressing
- count_down : natural; -- A downwards counter for read addressing
- count_chan : natural; -- Counter that holds the number of channels for reading.
- state : state_type; -- The state machine.
+ -- The read enable signal to read out the data from the dp memory
+ rd_en : std_logic;
+ -- Toggel register used for separate functionalilty
+ switch : std_logic;
+ -- An upwards counter for read addressing
+ count_up : natural;
+ -- A downwards counter for read addressing
+ count_down : natural;
+ -- Counter that holds the number of channels for reading.
+ count_chan : natural;
+ -- The state machine.
+ state : state_type;
end record;
signal r, rin : reg_type;
@@ -122,15 +136,18 @@ begin
adr_tot_cnt <= adr_chan_cnt & adr_points_cnt;
- adr_fft_flip <= flip(adr_points_cnt); -- flip the addresses to perform the bit-reversed reorder
- adr_fft_shift <= fft_shift(adr_fft_flip); -- invert MSbit for fft_shift
+ -- flip the addresses to perform the bit-reversed reorder
+ adr_fft_flip <= flip(adr_points_cnt);
+ -- invert MSbit for fft_shift
+ adr_fft_shift <= fft_shift(adr_fft_flip);
gen_complex : if g_separate = false generate
no_bit_flip : if g_bit_flip = false generate
wr_adr <= adr_tot_cnt;
end generate;
- gen_bit_flip_spectrum_and_channels : if g_bit_flip = true and g_dont_flip_channels = false generate -- the channels get separated in time
+ -- the channels get separated in time
+ gen_bit_flip_spectrum_and_channels : if g_bit_flip = true and g_dont_flip_channels = false generate
gen_no_fft_shift_sac : if g_fft_shift = false generate
wr_adr <= adr_chan_cnt & adr_fft_flip;
@@ -140,7 +157,8 @@ begin
wr_adr <= adr_chan_cnt & adr_fft_shift;
end generate;
end generate;
- gen_bit_flip_spectrum_only : if g_bit_flip = true and g_dont_flip_channels = true generate -- the channel interleaving in time is preserved
+ -- the channel interleaving in time is preserved
+ gen_bit_flip_spectrum_only : if g_bit_flip = true and g_dont_flip_channels = true generate
gen_no_fft_shift_so : if g_fft_shift = false generate
wr_adr <= adr_fft_flip & adr_chan_cnt;
@@ -153,11 +171,13 @@ begin
end generate;
gen_two_real : if g_separate = true generate
- gen_bit_flip_spectrum_and_channels : if g_dont_flip_channels = false generate -- the channels get separated in time
+ -- the channels get separated in time
+ gen_bit_flip_spectrum_and_channels : if g_dont_flip_channels = false generate
wr_adr <= adr_chan_cnt & adr_fft_flip;
end generate;
- gen_bit_flip_spectrum_only : if g_dont_flip_channels = true generate -- the channel interleaving in time is preserved
+ -- the channel interleaving in time is preserved
+ gen_bit_flip_spectrum_only : if g_dont_flip_channels = true generate
wr_adr <= adr_fft_flip & adr_chan_cnt;
end generate;
end generate;
@@ -244,11 +264,13 @@ begin
case r.state is
when s_idle =>
- if(next_page = '1') then -- Both counters are reset on page turn.
+ -- Both counters are reset on page turn.
+ if(next_page = '1') then
v.rd_en := '1';
v.switch := '0';
v.count_up := 0;
- if(g_separate = true) then -- Choose the appropriate run state
+ -- Choose the appropriate run state
+ if(g_separate = true) then
v.count_chan := 0;
v.count_down := g_nof_points;
v.state := s_run_separate;
@@ -269,24 +291,29 @@ begin
v.count_down := r.count_down - 1;
end if;
- if(next_page = '1') then -- Both counters are reset on page turn.
+ -- Both counters are reset on page turn.
+ if(next_page = '1') then
v.count_up := 0;
v.count_down := g_nof_points;
v.count_chan := 0;
- elsif(r.count_up = g_nof_points / 2 and r.count_chan < c_nof_channels - 1) then --
+ --
+ elsif(r.count_up = g_nof_points / 2 and r.count_chan < c_nof_channels - 1) then
v.count_up := 0;
v.count_down := g_nof_points;
v.count_chan := r.count_chan + 1;
- elsif(r.count_up = g_nof_points / 2) then -- Pagereading is done, but there is not yet new data available
+ -- Pagereading is done, but there is not yet new data available
+ elsif(r.count_up = g_nof_points / 2) then
v.rd_en := '0';
v.state := s_idle;
end if;
when s_run_normal =>
v.rd_en := '1';
- if(next_page = '1') then -- Counters is reset on page turn.
+ -- Counters is reset on page turn.
+ if(next_page = '1') then
v.count_up := 0;
- elsif(r.count_up = c_page_size-1) then -- Pagereading is done, but there is not yet new data available
+ -- Pagereading is done, but there is not yet new data available
+ elsif(r.count_up = c_page_size-1) then
v.rd_en := '0';
v.state := s_idle;
else
@@ -321,8 +348,10 @@ begin
gen_separate : if g_separate = true generate
-- The read address toggles between the upcounter and the downcounter.
-- Modulo N addressing is done with the TO_UVEC function.
- rd_adr_up <= TO_UVEC(r.count_up, c_adr_points_w + 1); -- eg. 0 .. 512
- rd_adr_down <= TO_UVEC(r.count_down, c_adr_points_w + 1); -- eg. 1024 .. 513, use 1 bit more to avoid truncation warning on 1024 ^= 0
+ -- eg. 0 .. 512
+ rd_adr_up <= TO_UVEC(r.count_up, c_adr_points_w + 1);
+ -- eg. 1024 .. 513, use 1 bit more to avoid truncation warning on 1024 ^= 0
+ rd_adr_down <= TO_UVEC(r.count_down, c_adr_points_w + 1);
rd_adr <= TO_UVEC(r.count_chan, c_adr_chan_w) & rd_adr_up( c_adr_points_w - 1 downto 0) when r.switch = '0' else
TO_UVEC(r.count_chan, c_adr_chan_w) & rd_adr_down(c_adr_points_w - 1 downto 0);
-- The data that is read from the memory is fed to the separate block
@@ -333,9 +362,11 @@ begin
port map (
clk => clk,
rst => rst,
- in_dat => out_dat_i, -- c_dat_w
+ -- c_dat_w
+ in_dat => out_dat_i,
in_val => out_val_i,
- out_dat => out_dat, -- c_dat_w + 2
+ -- c_dat_w + 2
+ out_dat => out_dat,
out_val => out_val
);
end generate;
@@ -345,7 +376,8 @@ begin
-- the output signals are directly driven.
gen_no_separate : if g_separate = false generate
rd_adr <= TO_UVEC(r.count_up, c_adr_tot_w);
- out_dat <= out_dat_i; -- c_dat_w
+ -- c_dat_w
+ out_dat <= out_dat_i;
out_val <= out_val_i;
end generate;
diff --git a/libraries/dsp/fft/src/vhdl/fft_sepa.vhd b/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
index f9b660aaaeb668de28134b314eda21686b5e3494..b9ea54da8afe1270bcf9cc210fbdce1fa2106faa 100644
--- a/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
@@ -54,9 +54,11 @@ entity fft_sepa is
port (
clk : in std_logic;
rst : in std_logic;
- in_dat : in std_logic_vector; -- c_nof_complex * c_in_data_w
+ -- c_nof_complex * c_in_data_w
+ in_dat : in std_logic_vector;
in_val : in std_logic;
- out_dat : out std_logic_vector; -- c_nof_complex * c_out_data_w = c_nof_complex * (c_in_data_w + 1)
+ -- c_nof_complex * c_out_data_w = c_nof_complex * (c_in_data_w + 1)
+ out_dat : out std_logic_vector;
out_val : out std_logic
);
end entity fft_sepa;
@@ -69,24 +71,36 @@ architecture rtl of fft_sepa is
constant c_pipeline : natural := 3;
type t_reg is record
- switch : std_logic; -- Register used to toggle between A & B definitionn
- val_dly : std_logic_vector(c_pipeline-1 downto 0); -- Register that delays the incoming valid signal
- xn_m_reg : std_logic_vector(c_in_complex_w - 1 downto 0); -- Register to hold the X(N-m) value for one cycle
- xm_reg : std_logic_vector(c_in_complex_w - 1 downto 0); -- Register to hold the X(m) value for one cycle
- add_reg_a : std_logic_vector(c_in_data_w - 1 downto 0); -- Input register A for the adder
- add_reg_b : std_logic_vector(c_in_data_w - 1 downto 0); -- Input register B for the adder
- sub_reg_a : std_logic_vector(c_in_data_w - 1 downto 0); -- Input register A for the subtractor
- sub_reg_b : std_logic_vector(c_in_data_w - 1 downto 0); -- Input register B for the subtractor
- out_dat : std_logic_vector(c_out_complex_w - 1 downto 0); -- Registered output value
- out_val : std_logic; -- Registered data valid signal
+ -- Register used to toggle between A & B definitionn
+ switch : std_logic;
+ -- Register that delays the incoming valid signal
+ val_dly : std_logic_vector(c_pipeline-1 downto 0);
+ -- Register to hold the X(N-m) value for one cycle
+ xn_m_reg : std_logic_vector(c_in_complex_w - 1 downto 0);
+ -- Register to hold the X(m) value for one cycle
+ xm_reg : std_logic_vector(c_in_complex_w - 1 downto 0);
+ -- Input register A for the adder
+ add_reg_a : std_logic_vector(c_in_data_w - 1 downto 0);
+ -- Input register B for the adder
+ add_reg_b : std_logic_vector(c_in_data_w - 1 downto 0);
+ -- Input register A for the subtractor
+ sub_reg_a : std_logic_vector(c_in_data_w - 1 downto 0);
+ -- Input register B for the subtractor
+ sub_reg_b : std_logic_vector(c_in_data_w - 1 downto 0);
+ -- Registered output value
+ out_dat : std_logic_vector(c_out_complex_w - 1 downto 0);
+ -- Registered data valid signal
+ out_val : std_logic;
end record;
constant c_reg_init : t_reg := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0');
signal r : t_reg := c_reg_init;
signal rin : t_reg;
- signal sub_result : std_logic_vector(c_out_data_w - 1 downto 0); -- Result of the subtractor
- signal add_result : std_logic_vector(c_out_data_w - 1 downto 0); -- Result of the adder
+ -- Result of the subtractor
+ signal sub_result : std_logic_vector(c_out_data_w - 1 downto 0);
+ -- Result of the adder
+ signal add_result : std_logic_vector(c_out_data_w - 1 downto 0);
begin
---------------------------------------------------------------
-- ADDER AND SUBTRACTOR
@@ -98,7 +112,8 @@ begin
g_pipeline_input => 0,
g_pipeline_output => 1,
g_in_dat_w => c_in_data_w,
- g_out_dat_w => c_out_data_w -- = c_in_data_w + 1
+ -- = c_in_data_w + 1
+ g_out_dat_w => c_out_data_w
)
port map (
clk => clk,
@@ -114,7 +129,8 @@ begin
g_pipeline_input => 0,
g_pipeline_output => 1,
g_in_dat_w => c_in_data_w,
- g_out_dat_w => c_out_data_w -- = c_in_data_w + 1
+ -- = c_in_data_w + 1
+ g_out_dat_w => c_out_data_w
)
port map (
clk => clk,
@@ -144,16 +160,24 @@ begin
if in_val = '1' or r.val_dly(0) = '1' then
if r.switch = '0' then
v.xm_reg := in_dat;
- v.add_reg_a := r.xm_reg(c_in_complex_w - 1 downto c_in_data_w); -- Xm imag
- v.add_reg_b := r.xn_m_reg(c_in_complex_w - 1 downto c_in_data_w); -- Xn-m imag
- v.sub_reg_a := r.xn_m_reg(c_in_data_w - 1 downto 0); -- Xn-m real
- v.sub_reg_b := r.xm_reg(c_in_data_w - 1 downto 0); -- Xm real
+ -- Xm imag
+ v.add_reg_a := r.xm_reg(c_in_complex_w - 1 downto c_in_data_w);
+ -- Xn-m imag
+ v.add_reg_b := r.xn_m_reg(c_in_complex_w - 1 downto c_in_data_w);
+ -- Xn-m real
+ v.sub_reg_a := r.xn_m_reg(c_in_data_w - 1 downto 0);
+ -- Xm real
+ v.sub_reg_b := r.xm_reg(c_in_data_w - 1 downto 0);
else
v.xn_m_reg := in_dat;
- v.add_reg_a := r.xm_reg(c_in_data_w - 1 downto 0); -- Xm real
- v.add_reg_b := in_dat(c_in_data_w - 1 downto 0); -- Xn-m real
- v.sub_reg_a := r.xm_reg(c_in_complex_w - 1 downto c_in_data_w); -- Xm imag
- v.sub_reg_b := in_dat(c_in_complex_w - 1 downto c_in_data_w); -- Xn-m imag
+ -- Xm real
+ v.add_reg_a := r.xm_reg(c_in_data_w - 1 downto 0);
+ -- Xn-m real
+ v.add_reg_b := in_dat(c_in_data_w - 1 downto 0);
+ -- Xm imag
+ v.sub_reg_a := r.xm_reg(c_in_complex_w - 1 downto c_in_data_w);
+ -- Xn-m imag
+ v.sub_reg_b := in_dat(c_in_complex_w - 1 downto c_in_data_w);
end if;
end if;
diff --git a/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd b/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
index 720653a425aff14402dee71b8f337d2ef8815154..5b2b641ea6ec109661363c376e73542b9a426a50 100644
--- a/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
@@ -46,7 +46,8 @@ use work.fft_pkg.all;
entity fft_sepa_wide is
generic (
- g_fft : t_fft := c_fft -- generics for the FFT
+ -- generics for the FFT
+ g_fft : t_fft := c_fft
);
port (
clk : in std_logic;
@@ -61,49 +62,77 @@ entity fft_sepa_wide is
end entity fft_sepa_wide;
architecture rtl of fft_sepa_wide is
- constant c_pipeline_output : natural := 0; -- no need for extra pipeline output, because output is already registered
+ -- no need for extra pipeline output, because output is already registered
+ constant c_pipeline_output : natural := 0;
- constant c_page_size : natural := g_fft.nof_points / g_fft.wb_factor; -- Size of the memories
- constant c_nof_pages : natural := 2; -- The number of pages in each ram.
+ -- Size of the memories
+ constant c_page_size : natural := g_fft.nof_points / g_fft.wb_factor;
+ -- The number of pages in each ram.
+ constant c_nof_pages : natural := 2;
constant c_in_w : natural := g_fft.stage_dat_w;
- constant c_dat_w : natural := c_nof_complex * c_in_w; -- Data width for the internal vectors where real and imag are combined.
- constant c_adr_w : natural := ceil_log2(c_page_size); -- Address width of the rams
- constant c_nof_streams : natural := 2; -- Number of inputstreams for the zip units
-
- constant c_sepa_growth_w : natural := sel_a_b(g_fft.use_separate, 1, 0); -- add one bit for add sub growth in separate
+ -- Data width for the internal vectors where real and imag are combined.
+ constant c_dat_w : natural := c_nof_complex * c_in_w;
+ -- Address width of the rams
+ constant c_adr_w : natural := ceil_log2(c_page_size);
+ -- Number of inputstreams for the zip units
+ constant c_nof_streams : natural := 2;
+
+ -- add one bit for add sub growth in separate
+ constant c_sepa_growth_w : natural := sel_a_b(g_fft.use_separate, 1, 0);
constant c_out_w : natural := c_in_w + c_sepa_growth_w;
- constant c_raw_dat_w : natural := c_nof_complex * c_out_w; -- = c_dat_w or c_dat_w + 2
+ -- = c_dat_w or c_dat_w + 2
+ constant c_raw_dat_w : natural := c_nof_complex * c_out_w;
type t_dat_arr is array(integer range <> ) of std_logic_vector(c_dat_w - 1 downto 0);
type t_raw_dat_arr is array(integer range <> ) of std_logic_vector(c_raw_dat_w - 1 downto 0);
type t_rd_adr_arr is array(integer range <> ) of std_logic_vector(c_adr_w - 1 downto 0);
- type t_zip_in_matrix is array(integer range <> ) of t_slv_64_arr(1 downto 0); -- Every Zip unit has two inputs.
-
- signal next_page : std_logic; -- Active high signal to force a page-swap in the memories
- signal wr_en : std_logic; -- The write enable signal for the memories
- signal wr_adr : std_logic_vector(c_adr_w - 1 downto 0); -- The write address
- signal wr_dat : t_dat_arr(g_fft.wb_factor - 1 downto 0); -- Array of data to be written to memory
-
- signal rd_dat_arr : t_dat_arr(g_fft.wb_factor - 1 downto 0); -- Array of data that is read from memory
- signal rd_adr_arr : t_rd_adr_arr(1 downto 0); -- There are two different read addresses.
-
- signal zip_in_matrix : t_zip_in_matrix(g_fft.wb_factor - 1 downto 0); -- Matrix that contains the inputs for zip units
- signal zip_in_val : std_logic_vector(g_fft.wb_factor - 1 downto 0); -- Vector that holds the data input valids for the zip units
- signal zip_out_dat_arr : t_dat_arr(g_fft.wb_factor - 1 downto 0); -- Array that holds the outputs of all zip units.
- signal zip_out_val : std_logic_vector(g_fft.wb_factor - 1 downto 0); -- Vector that holds the output valids of the zip units
-
- signal sep_out_dat_arr : t_raw_dat_arr(g_fft.wb_factor - 1 downto 0); -- Array that holds the outputs of the separation blocks
- signal sep_out_val_vec : std_logic_vector(g_fft.wb_factor - 1 downto 0); -- Vector containing the datavalids from the separation blocks
- signal out_dat_arr : t_raw_dat_arr(g_fft.wb_factor - 1 downto 0); -- Array that holds the ouput values, where real and imag are concatenated
+ -- Every Zip unit has two inputs.
+ type t_zip_in_matrix is array(integer range <> ) of t_slv_64_arr(1 downto 0);
+
+ -- Active high signal to force a page-swap in the memories
+ signal next_page : std_logic;
+ -- The write enable signal for the memories
+ signal wr_en : std_logic;
+ -- The write address
+ signal wr_adr : std_logic_vector(c_adr_w - 1 downto 0);
+ -- Array of data to be written to memory
+ signal wr_dat : t_dat_arr(g_fft.wb_factor - 1 downto 0);
+
+ -- Array of data that is read from memory
+ signal rd_dat_arr : t_dat_arr(g_fft.wb_factor - 1 downto 0);
+ -- There are two different read addresses.
+ signal rd_adr_arr : t_rd_adr_arr(1 downto 0);
+
+ -- Matrix that contains the inputs for zip units
+ signal zip_in_matrix : t_zip_in_matrix(g_fft.wb_factor - 1 downto 0);
+ -- Vector that holds the data input valids for the zip units
+ signal zip_in_val : std_logic_vector(g_fft.wb_factor - 1 downto 0);
+ -- Array that holds the outputs of all zip units.
+ signal zip_out_dat_arr : t_dat_arr(g_fft.wb_factor - 1 downto 0);
+ -- Vector that holds the output valids of the zip units
+ signal zip_out_val : std_logic_vector(g_fft.wb_factor - 1 downto 0);
+
+ -- Array that holds the outputs of the separation blocks
+ signal sep_out_dat_arr : t_raw_dat_arr(g_fft.wb_factor - 1 downto 0);
+ -- Vector containing the datavalids from the separation blocks
+ signal sep_out_val_vec : std_logic_vector(g_fft.wb_factor - 1 downto 0);
+ -- Array that holds the ouput values, where real and imag are concatenated
+ signal out_dat_arr : t_raw_dat_arr(g_fft.wb_factor - 1 downto 0);
type t_state is (s_idle, s_read);
type t_reg is record
- switch : std_logic; -- Toggle register used for separate functionalilty
- count_up : natural range 0 to c_page_size; -- An upwards counter for read addressing
- count_down : natural range 0 to c_page_size; -- A downwards counter for read addressing
- val_odd : std_logic; -- Register that drives the in_valid of the odd zip units
- val_even : std_logic; -- Register that drives the in_valid of the even zip units
- state : t_state; -- The state machine.
+ -- Toggle register used for separate functionalilty
+ switch : std_logic;
+ -- An upwards counter for read addressing
+ count_up : natural range 0 to c_page_size;
+ -- A downwards counter for read addressing
+ count_down : natural range 0 to c_page_size;
+ -- Register that drives the in_valid of the odd zip units
+ val_odd : std_logic;
+ -- Register that drives the in_valid of the even zip units
+ val_even : std_logic;
+ -- The state machine.
+ state : t_state;
end record;
constant c_reg_init : t_reg := ('0', 0, 0, '0', '0', s_idle);
@@ -209,9 +238,11 @@ begin
port map (
clk => clk,
rst => rst,
- in_dat => zip_out_dat_arr(I), -- c_dat_w
+ -- c_dat_w
+ in_dat => zip_out_dat_arr(I),
in_val => zip_out_val(I),
- out_dat => sep_out_dat_arr(I), -- c_dat_w + 2
+ -- c_dat_w + 2
+ out_dat => sep_out_dat_arr(I),
out_val => sep_out_val_vec(I)
);
end generate;
@@ -234,29 +265,38 @@ begin
v.val_even := '0';
v.count_up := 0;
v.count_down := c_page_size;
- if(next_page = '1') then -- Check if next page is asserted, meaning first page is written)
+ -- Check if next page is asserted, meaning first page is written)
+ if(next_page = '1') then
v.state := s_read;
end if;
when s_read =>
- if(r.switch = '0') then -- Toggle the switch register from 0 to 1
+ -- Toggle the switch register from 0 to 1
+ if(r.switch = '0') then
v.switch := '1';
end if;
- if(r.switch = '1') then -- Toggle the switch register from 1 to 0
+ -- Toggle the switch register from 1 to 0
+ if(r.switch = '1') then
v.switch := '0';
- v.count_up := r.count_up + 1; -- Increment the upwards counter
- v.count_down := r.count_down - 1; -- Decrease the downwards counter
+ -- Increment the upwards counter
+ v.count_up := r.count_up + 1;
+ -- Decrease the downwards counter
+ v.count_down := r.count_down - 1;
end if;
- if(next_page = '1') then -- Both counters are reset on page turn.
+ -- Both counters are reset on page turn.
+ if(next_page = '1') then
v.count_up := 0;
v.count_down := c_page_size;
- elsif(v.count_up = c_page_size / 2) then -- Pagereading is done, but there is not yet new data available (Note that the value of variable v is checked here)
- v.state := s_idle; -- then go back to idle.
+ -- Pagereading is done, but there is not yet new data available (Note that the value of variable v is checked here)
+ elsif(v.count_up = c_page_size / 2) then
+ -- then go back to idle.
+ v.state := s_idle;
end if;
- v.val_odd := r.switch; -- Assignment of the odd and even markers
+ -- Assignment of the odd and even markers
+ v.val_odd := r.switch;
v.val_even := not(r.switch);
when others =>
@@ -283,7 +323,8 @@ begin
gen_align_and_pipeline_stages : for I in g_fft.wb_factor / 2 - 1 downto 0 generate
u_output_pipeline_align : entity common_lib.common_pipeline
generic map (
- g_pipeline => c_pipeline_output + 1, -- Pipeline + one stage for allignment
+ -- Pipeline + one stage for allignment
+ g_pipeline => c_pipeline_output + 1,
g_in_dat_w => c_raw_dat_w,
g_out_dat_w => c_raw_dat_w
)
@@ -295,7 +336,8 @@ begin
u_output_pipeline : entity common_lib.common_pipeline
generic map (
- g_pipeline => c_pipeline_output, -- Only pipeline stage
+ -- Only pipeline stage
+ g_pipeline => c_pipeline_output,
g_in_dat_w => c_raw_dat_w,
g_out_dat_w => c_raw_dat_w
)
diff --git a/libraries/dsp/fft/src/vhdl/fft_switch.vhd b/libraries/dsp/fft/src/vhdl/fft_switch.vhd
index e1732d2a8153084a92c65a57f58d3f86ec81144f..b1bb8082fd32dee8213fafffb31b55d1a847a93b 100644
--- a/libraries/dsp/fft/src/vhdl/fft_switch.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_switch.vhd
@@ -57,8 +57,10 @@ entity fft_switch is
g_dat_w : natural
);
port (
- in_re : in std_logic_vector(g_dat_w - 1 downto 0); -- real input A
- in_im : in std_logic_vector(g_dat_w - 1 downto 0); -- real input B
+ -- real input A
+ in_re : in std_logic_vector(g_dat_w - 1 downto 0);
+ -- real input B
+ in_im : in std_logic_vector(g_dat_w - 1 downto 0);
in_val : in std_logic;
out_re : out std_logic_vector(g_dat_w - 1 downto 0);
out_im : out std_logic_vector(g_dat_w - 1 downto 0);
@@ -88,14 +90,16 @@ begin
u_in_strobes : entity common_lib.common_create_strobes_from_valid
generic map (
g_pipeline => false,
- g_nof_clk_per_sync => c_nof_clk_per_block * 16, -- void value, sync is not used
+ -- void value, sync is not used
+ g_nof_clk_per_sync => c_nof_clk_per_block * 16,
g_nof_clk_per_block => c_nof_clk_per_block
)
port map (
rst => rst,
clk => clk,
in_val => in_val,
- out_val => OPEN, -- out_val = in_val, because g_pipeline = FALSE
+ -- out_val = in_val, because g_pipeline = FALSE
+ out_val => OPEN,
out_sop => in_sop,
out_eop => in_eop,
out_sync => open
@@ -147,10 +151,12 @@ begin
nxt_out_im <= in_im;
if lfsr_bit1 = cnt(cnt'high) then
- nxt_out_re <= NEGATE_SVEC(in_re, g_dat_w); -- negate block of input A samples
+ -- negate block of input A samples
+ nxt_out_re <= NEGATE_SVEC(in_re, g_dat_w);
end if;
if lfsr_bit2 = cnt(cnt'high) then
- nxt_out_im <= NEGATE_SVEC(in_im, g_dat_w); -- negate block of input B samples
+ -- negate block of input B samples
+ nxt_out_im <= NEGATE_SVEC(in_im, g_dat_w);
end if;
end process;
diff --git a/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd b/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
index 9d1ad5ef00b3fb3a60bbcb5e7c313c45f63b13fa..2f7545ca642a3eba272e11b93d10010bf700bacb 100644
--- a/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
@@ -74,14 +74,16 @@ begin
u_in_strobes : entity common_lib.common_create_strobes_from_valid
generic map (
g_pipeline => false,
- g_nof_clk_per_sync => c_nof_clk_per_block * 16, -- void value, sync is not used
+ -- void value, sync is not used
+ g_nof_clk_per_sync => c_nof_clk_per_block * 16,
g_nof_clk_per_block => c_nof_clk_per_block
)
port map (
rst => rst,
clk => clk,
in_val => in_val,
- out_val => OPEN, -- out_val = in_val, because g_pipeline = FALSE
+ -- out_val = in_val, because g_pipeline = FALSE
+ out_val => OPEN,
out_sop => in_sop,
out_eop => in_eop,
out_sync => open
@@ -134,12 +136,14 @@ begin
-- multiplexed spectrum for input A at index 0, B at index 1
if cnt(0) = '0' then
- if cnt(cnt'high) = lfsr_bit1 then -- negate spectrum to undo negate of block of real input A
+ -- negate spectrum to undo negate of block of real input A
+ if cnt(cnt'high) = lfsr_bit1 then
nxt_out_re <= NEGATE_SVEC(in_re, g_dat_w);
nxt_out_im <= NEGATE_SVEC(in_im, g_dat_w);
end if;
else
- if cnt(cnt'high) = lfsr_bit2 then -- negate spectrum to undo negate of block of real input B
+ -- negate spectrum to undo negate of block of real input B
+ if cnt(cnt'high) = lfsr_bit2 then
nxt_out_re <= NEGATE_SVEC(in_re, g_dat_w);
nxt_out_im <= NEGATE_SVEC(in_im, g_dat_w);
end if;
diff --git a/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd b/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd
index 3134ef587f4b2d7013c81bf27b70bc34e5b13344..2ad9aced75ea4fa84506c66b61cbcb4f67280912 100644
--- a/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd
@@ -44,16 +44,20 @@ use work.fft_pkg.all;
entity fft_wide_unit is
generic (
- g_fft : t_fft := c_fft; -- generics for the FFT
- g_pft_pipeline : t_fft_pipeline := c_fft_pipeline; -- For the pipelined part, defined in rTwoSDF_lib.rTwoSDFPkg
- g_fft_pipeline : t_fft_pipeline := c_fft_pipeline -- For the parallel part, defined in rTwoSDF_lib.rTwoSDFPkg
+ -- generics for the FFT
+ g_fft : t_fft := c_fft;
+ -- For the pipelined part, defined in rTwoSDF_lib.rTwoSDFPkg
+ g_pft_pipeline : t_fft_pipeline := c_fft_pipeline;
+ -- For the parallel part, defined in rTwoSDF_lib.rTwoSDFPkg
+ g_fft_pipeline : t_fft_pipeline := c_fft_pipeline
);
port (
dp_rst : in std_logic := '0';
dp_clk : in std_logic;
mm_rst : in std_logic;
mm_clk : in std_logic;
- ram_st_sst_mosi : in t_mem_mosi; -- Subband statistics registers
+ -- Subband statistics registers
+ ram_st_sst_mosi : in t_mem_mosi;
ram_st_sst_miso : out t_mem_miso := c_mem_miso_rst;
in_sosi_arr : in t_dp_sosi_arr(g_fft.wb_factor - 1 downto 0);
out_sosi_arr : out t_dp_sosi_arr(g_fft.wb_factor - 1 downto 0)
@@ -136,7 +140,8 @@ begin
---------------------------------------------------------------
u_fft_wide : entity work.fft_r2_wide
generic map(
- g_fft => g_fft, -- generics for the WFFT
+ -- generics for the WFFT
+ g_fft => g_fft,
g_pft_pipeline => g_pft_pipeline,
g_fft_pipeline => g_fft_pipeline
)
diff --git a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
index c31e4c188132f18303c3fd9219c07a213af1e46d..6b6033d4b7239ca4e536a88af5dd14678cc351f4 100644
--- a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
@@ -55,30 +55,45 @@ entity fft_wide_unit_control is
in_re_arr : in t_fft_slv_arr(g_nof_ffts * g_fft.wb_factor - 1 downto 0);
in_im_arr : in t_fft_slv_arr(g_nof_ffts * g_fft.wb_factor - 1 downto 0);
in_val : in std_logic;
- ctrl_sosi : in t_dp_sosi; -- Inputrecord for tapping off the sync, bsn and err.
- out_sosi_arr : out t_dp_sosi_arr(g_nof_ffts * g_fft.wb_factor - 1 downto 0) -- Streaming output interface
+ -- Inputrecord for tapping off the sync, bsn and err.
+ ctrl_sosi : in t_dp_sosi;
+ -- Streaming output interface
+ out_sosi_arr : out t_dp_sosi_arr(g_nof_ffts * g_fft.wb_factor - 1 downto 0)
);
end fft_wide_unit_control;
architecture rtl of fft_wide_unit_control is
- constant c_pipe_data : natural := 3; -- Delay depth for the data
- constant c_pipe_ctrl : natural := c_pipe_data - 1; -- Delay depth for the control signals
- constant c_packet_size : natural := (2**g_fft.nof_chan) * g_fft.nof_points / g_fft.wb_factor; -- Definition of the packet size
- constant c_ctrl_fifo_depth : natural := 16; -- Depth of the bsn and err fifo.
+ -- Delay depth for the data
+ constant c_pipe_data : natural := 3;
+ -- Delay depth for the control signals
+ constant c_pipe_ctrl : natural := c_pipe_data - 1;
+ -- Definition of the packet size
+ constant c_packet_size : natural := (2**g_fft.nof_chan) * g_fft.nof_points / g_fft.wb_factor;
+ -- Depth of the bsn and err fifo.
+ constant c_ctrl_fifo_depth : natural := 16;
type t_fft_slv_arr2 is array (integer range <>) of t_fft_slv_arr(g_nof_ffts * g_fft.wb_factor - 1 downto 0);
type state_type is (s_idle, s_run, s_hold);
type reg_type is record
- out_sosi_arr : t_dp_sosi_arr(g_nof_ffts * g_fft.wb_factor - 1 downto 0); -- Register that holds the streaming interface
- in_re_arr2_dly : t_fft_slv_arr2(c_pipe_data - 1 downto 0); -- Input registers for the real data
- in_im_arr2_dly : t_fft_slv_arr2(c_pipe_data - 1 downto 0); -- Input registers for the imag data
- val_dly : std_logic_vector(c_pipe_ctrl - 1 downto 0); -- Delay-register for the valid signal
- sop_dly : std_logic_vector(c_pipe_ctrl - 1 downto 0); -- Delay-register for the sop signal
- eop_dly : std_logic_vector(c_pipe_ctrl - 1 downto 0); -- Delay-register for the eop signal
- sync_detected : std_logic; -- Register used to detect and pass the sync pulse.
- packet_cnt : integer; -- Counter to create the packets.
- state : state_type; -- The state machine.
+ -- Register that holds the streaming interface
+ out_sosi_arr : t_dp_sosi_arr(g_nof_ffts * g_fft.wb_factor - 1 downto 0);
+ -- Input registers for the real data
+ in_re_arr2_dly : t_fft_slv_arr2(c_pipe_data - 1 downto 0);
+ -- Input registers for the imag data
+ in_im_arr2_dly : t_fft_slv_arr2(c_pipe_data - 1 downto 0);
+ -- Delay-register for the valid signal
+ val_dly : std_logic_vector(c_pipe_ctrl - 1 downto 0);
+ -- Delay-register for the sop signal
+ sop_dly : std_logic_vector(c_pipe_ctrl - 1 downto 0);
+ -- Delay-register for the eop signal
+ eop_dly : std_logic_vector(c_pipe_ctrl - 1 downto 0);
+ -- Register used to detect and pass the sync pulse.
+ sync_detected : std_logic;
+ -- Counter to create the packets.
+ packet_cnt : integer;
+ -- The state machine.
+ state : state_type;
end record;
signal r, rin : reg_type;
@@ -95,7 +110,8 @@ begin
---------------------------------------------------------------
u_bsn_fifo : entity common_lib.common_fifo_sc
generic map (
- g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep.
+ -- Make this FIFO in logic, since it's only 4 words deep.
+ g_use_lut => true,
g_reset => false,
g_init => false,
g_dat_w => c_dp_stream_bsn_w,
@@ -119,7 +135,8 @@ begin
---------------------------------------------------------------
u_error_fifo : entity common_lib.common_fifo_sc
generic map (
- g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep.
+ -- Make this FIFO in logic, since it's only 4 words deep.
+ g_use_lut => true,
g_reset => false,
g_init => false,
g_dat_w => c_dp_stream_error_w,
@@ -143,7 +160,8 @@ begin
---------------------------------------------------------------
u_sync_bsn_fifo : entity common_lib.common_fifo_sc
generic map (
- g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep.
+ -- Make this FIFO in logic, since it's only 4 words deep.
+ g_use_lut => true,
g_reset => false,
g_init => false,
g_dat_w => c_dp_stream_bsn_w,
@@ -182,7 +200,8 @@ begin
rd_val => open
);
- rd_req <= r.out_sosi_arr(0).sync; -- (r.sync_detected and not(rd_emp)) or r.rd_first;
+ -- (r.sync_detected and not(rd_emp)) or r.rd_first;
+ rd_req <= r.out_sosi_arr(0).sync;
---------------------------------------------------------------
-- PROCESS THAT COMPOSES THE SOSI OUTPUT ARRAYS
@@ -192,7 +211,8 @@ begin
begin
v := r;
- v.val_dly(0) := '0'; -- Some defaults, before entering the state machine.
+ -- Some defaults, before entering the state machine.
+ v.val_dly(0) := '0';
v.sop_dly(0) := '0';
v.eop_dly(0) := '0';
@@ -200,60 +220,90 @@ begin
v.out_sosi_arr(I).sync := '0';
end loop;
- v.in_re_arr2_dly(0) := in_re_arr; -- Latch the data into the input registers.
- v.in_im_arr2_dly(0) := in_im_arr; -- Latch the data into the input registers.
+ -- Latch the data into the input registers.
+ v.in_re_arr2_dly(0) := in_re_arr;
+ -- Latch the data into the input registers.
+ v.in_im_arr2_dly(0) := in_im_arr;
- v.in_re_arr2_dly(c_pipe_data - 1 downto 1) := r.in_re_arr2_dly(c_pipe_data - 2 downto 0); -- Shift the delay registers
- v.in_im_arr2_dly(c_pipe_data - 1 downto 1) := r.in_im_arr2_dly(c_pipe_data - 2 downto 0); -- Shift the delay registers
- v.val_dly(c_pipe_ctrl - 1 downto 1) := r.val_dly(c_pipe_ctrl - 2 downto 0); -- Shift the delay registers
- v.sop_dly(c_pipe_ctrl - 1 downto 1) := r.sop_dly(c_pipe_ctrl - 2 downto 0); -- Shift the delay registers
- v.eop_dly(c_pipe_ctrl - 1 downto 1) := r.eop_dly(c_pipe_ctrl - 2 downto 0); -- Shift the delay registers
+ -- Shift the delay registers
+ v.in_re_arr2_dly(c_pipe_data - 1 downto 1) := r.in_re_arr2_dly(c_pipe_data - 2 downto 0);
+ -- Shift the delay registers
+ v.in_im_arr2_dly(c_pipe_data - 1 downto 1) := r.in_im_arr2_dly(c_pipe_data - 2 downto 0);
+ -- Shift the delay registers
+ v.val_dly(c_pipe_ctrl - 1 downto 1) := r.val_dly(c_pipe_ctrl - 2 downto 0);
+ -- Shift the delay registers
+ v.sop_dly(c_pipe_ctrl - 1 downto 1) := r.sop_dly(c_pipe_ctrl - 2 downto 0);
+ -- Shift the delay registers
+ v.eop_dly(c_pipe_ctrl - 1 downto 1) := r.eop_dly(c_pipe_ctrl - 2 downto 0);
for I in g_nof_ffts * g_fft.wb_factor - 1 downto 0 loop
- v.out_sosi_arr(I).sop := r.sop_dly(c_pipe_ctrl - 1); -- Assign the output of the shiftregisters to the "real" signals
- v.out_sosi_arr(I).eop := r.eop_dly(c_pipe_ctrl - 1); -- Assign the output of the shiftregisters to the "real" signals
- v.out_sosi_arr(I).valid := r.val_dly(c_pipe_ctrl - 1); -- Assign the output of the shiftregisters to the "real" signals
- v.out_sosi_arr(I).bsn := bsn; -- The bsn is read from the FIFO
- v.out_sosi_arr(I).err := err; -- The err is read from the FIFO
- v.out_sosi_arr(I).re := RESIZE_SVEC(r.in_re_arr2_dly(c_pipe_data - 1)(I), c_dp_stream_dsp_data_w); -- Data input is latched-in
- v.out_sosi_arr(I).im := RESIZE_SVEC(r.in_im_arr2_dly(c_pipe_data - 1)(I), c_dp_stream_dsp_data_w); -- Data input is latched-in
+ -- Assign the output of the shiftregisters to the "real" signals
+ v.out_sosi_arr(I).sop := r.sop_dly(c_pipe_ctrl - 1);
+ -- Assign the output of the shiftregisters to the "real" signals
+ v.out_sosi_arr(I).eop := r.eop_dly(c_pipe_ctrl - 1);
+ -- Assign the output of the shiftregisters to the "real" signals
+ v.out_sosi_arr(I).valid := r.val_dly(c_pipe_ctrl - 1);
+ -- The bsn is read from the FIFO
+ v.out_sosi_arr(I).bsn := bsn;
+ -- The err is read from the FIFO
+ v.out_sosi_arr(I).err := err;
+ -- Data input is latched-in
+ v.out_sosi_arr(I).re := RESIZE_SVEC(r.in_re_arr2_dly(c_pipe_data - 1)(I), c_dp_stream_dsp_data_w);
+ -- Data input is latched-in
+ v.out_sosi_arr(I).im := RESIZE_SVEC(r.in_im_arr2_dly(c_pipe_data - 1)(I), c_dp_stream_dsp_data_w);
end loop;
- if(ctrl_sosi.sync = '1') then -- Check which bsn accompanies the sync
+ -- Check which bsn accompanies the sync
+ if(ctrl_sosi.sync = '1') then
v.sync_detected := '1';
end if;
- if(sync_bsn = bsn and r.sop_dly(1) = '1' and r.sync_detected = '1') then -- When the next bsn equals the stored bsn
- for I in g_fft.wb_factor - 1 downto 0 loop -- a sync pulse will be generated that
- v.out_sosi_arr(I).sync := '1'; -- preceeds the sop
+ -- When the next bsn equals the stored bsn
+ if(sync_bsn = bsn and r.sop_dly(1) = '1' and r.sync_detected = '1') then
+ -- a sync pulse will be generated that
+ for I in g_fft.wb_factor - 1 downto 0 loop
+ -- preceeds the sop
+ v.out_sosi_arr(I).sync := '1';
end loop;
v.sync_detected := '0';
end if;
case r.state is
when s_idle =>
- if(in_val = '1') then -- Wait for the first data to arrive
- v.packet_cnt := 0; -- Reset the packet counter
+ -- Wait for the first data to arrive
+ if(in_val = '1') then
+ -- Reset the packet counter
+ v.packet_cnt := 0;
v.state := s_run;
end if;
when s_run =>
- v.val_dly(0) := '1'; -- Assert the valid signal (Stream starts)
- v.packet_cnt := r.packet_cnt + 1; -- Increment the packet-counter when in s_run-state
+ -- Assert the valid signal (Stream starts)
+ v.val_dly(0) := '1';
+ -- Increment the packet-counter when in s_run-state
+ v.packet_cnt := r.packet_cnt + 1;
- if(r.packet_cnt = 0) then -- First sample marks
- v.sop_dly(0) := '1'; -- the start of a packet
- elsif(r.packet_cnt = c_packet_size-1) then -- Last address marks
- v.eop_dly(0) := '1'; -- the end of a packet
- v.packet_cnt := 0; -- Reset the counter
+ -- First sample marks
+ if(r.packet_cnt = 0) then
+ -- the start of a packet
+ v.sop_dly(0) := '1';
+ -- Last address marks
+ elsif(r.packet_cnt = c_packet_size-1) then
+ -- the end of a packet
+ v.eop_dly(0) := '1';
+ -- Reset the counter
+ v.packet_cnt := 0;
end if;
- if(in_val = '0') then -- If there is no more data:
- v.state := s_hold; -- go wait in the s_hold state
+ -- If there is no more data:
+ if(in_val = '0') then
+ -- go wait in the s_hold state
+ v.state := s_hold;
end if;
when s_hold =>
- if(in_val = '1') then -- Wait until new valid data arrives
+ -- Wait until new valid data arrives
+ if(in_val = '1') then
v.state := s_run;
end if;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd
index 739b0cba34abd49e147c90654cf84d98417ba38b..3b8546bdc74c1bd7ff3b0e69c73a8b7ff7e9bd8d 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd
@@ -62,11 +62,14 @@ architecture tb of tb_fft_functions is
signal index_flip_shift_arr : t_natural_arr(0 to c_nof_points - 1);
signal index_shift_flip_arr : t_natural_arr(0 to c_nof_points - 1);
signal bin_complex_arr : t_natural_arr(0 to c_nof_points - 1);
- signal bin_complex_flip_arr : t_natural_arr(0 to c_nof_points - 1); -- flip()
+ -- flip()
+ signal bin_complex_flip_arr : t_natural_arr(0 to c_nof_points - 1);
signal bin_complex_flip_transpose_arr : t_natural_arr(0 to c_nof_points - 1);
- signal bin_complex_reorder_arr : t_natural_arr(0 to c_nof_points - 1); -- fft_shift(flip())
+ -- fft_shift(flip())
+ signal bin_complex_reorder_arr : t_natural_arr(0 to c_nof_points - 1);
signal bin_complex_reorder_transpose_arr : t_natural_arr(0 to c_nof_points - 1);
- signal bin_two_real_reorder_arr : t_natural_arr(0 to c_nof_points - 1); -- separate(flip())
+ -- separate(flip())
+ signal bin_two_real_reorder_arr : t_natural_arr(0 to c_nof_points - 1);
signal bin_two_real_reorder_transpose_arr : t_natural_arr(0 to c_nof_points - 1);
begin
p_bin : process
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
index b566285a2932ee150bab7812781ad122b7aa8ee1..d2c1386cd2ac3c9d9384df90f5a009f883fea19f 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
@@ -34,8 +34,10 @@ use work.fft_pkg.all;
package tb_fft_pkg is
constant c_fft_nof_subbands_max : natural := 256;
- subtype t_fft_sst_arr is t_slv_64_arr(c_fft_nof_subbands_max - 1 downto 0); -- use subtype to allow using assignments via t_slv_64_arr as well
- type t_fft_sst_arr2 is array (integer range <>) of t_fft_sst_arr; -- Private procedures
+ -- use subtype to allow using assignments via t_slv_64_arr as well
+ subtype t_fft_sst_arr is t_slv_64_arr(c_fft_nof_subbands_max - 1 downto 0);
+ -- Private procedures
+ type t_fft_sst_arr2 is array (integer range <>) of t_fft_sst_arr;
-- map fft output index to bin frequency
function fft_index_to_bin_frequency(wb_factor, nof_points, index : natural; use_reorder, use_fft_shift, use_separate : boolean) return natural;
@@ -47,7 +49,8 @@ package tb_fft_pkg is
use_reorder : boolean;
use_fft_shift : boolean;
use_separate : boolean;
- signal out_val_cnt : in natural; -- count at sclk sample rate
+ -- count at sclk sample rate
+ signal out_val_cnt : in natural;
signal out_val : in std_logic;
signal out_val_a : out std_logic;
signal out_val_b : out std_logic;
@@ -61,7 +64,8 @@ package tb_fft_pkg is
signal in_file_val : out std_logic_vector;
file_name : in string);
- procedure proc_read_input_file(signal clk : in std_logic; -- Same read procedure for data files that do not contain a valid and sync column
+ -- Same read procedure for data files that do not contain a valid and sync column
+ procedure proc_read_input_file(signal clk : in std_logic;
signal in_file_data : out t_integer_matrix;
file_name : in string);
@@ -293,7 +297,8 @@ package body tb_fft_pkg is
--
constant c_addr_w : natural := ceil_log2(nof_points);
- variable v_addr : std_logic_vector(c_addr_w - 1 downto 0); -- used to convert index integer into slv
+ -- used to convert index integer into slv
+ variable v_addr : std_logic_vector(c_addr_w - 1 downto 0);
variable v_index : natural;
variable v_bin : natural;
begin
@@ -306,23 +311,27 @@ package body tb_fft_pkg is
-- No HDL index flip
v_addr := to_uvec(index, c_addr_w);
v_addr := flip(v_addr);
- v_addr := fft_shift(v_addr); -- b = fft_shift(flip(i))
+ -- b = fft_shift(flip(i))
+ v_addr := fft_shift(v_addr);
else
-- With HDL index flip
if use_fft_shift = false then
-- No HDL fft_shift
v_addr := to_uvec(index, c_addr_w);
- v_addr := fft_shift(v_addr); -- b = fft_shift(i)
+ -- b = fft_shift(i)
+ v_addr := fft_shift(v_addr);
else
-- With HDL fft_shift
- v_addr := to_uvec(index, c_addr_w); -- b = i
+ -- b = i
+ v_addr := to_uvec(index, c_addr_w);
end if;
end if;
v_bin := to_uint(v_addr);
else
-- Two real input data
- v_bin := index / 2; -- b = i/2
+ -- b = i/2
+ v_bin := index / 2;
end if;
else
-- Wideband parallel data
@@ -332,25 +341,32 @@ package body tb_fft_pkg is
-- No HDL pipelined and parallel index flips
v_addr := to_uvec(index, c_addr_w);
v_addr := flip(v_addr);
- v_addr := fft_shift(v_addr); -- b = fft_shift(flip(i))
+ -- b = fft_shift(flip(i))
+ v_addr := fft_shift(v_addr);
else
-- With HDL pipelined and parallel index flips
if use_fft_shift = false then
-- No HDL fft_shift
- v_index := transpose(index, wb_factor, nof_points / wb_factor); -- t = transpose(i, 4, 8)
+ -- t = transpose(i, 4, 8)
+ v_index := transpose(index, wb_factor, nof_points / wb_factor);
v_addr := to_uvec(v_index, c_addr_w);
- v_addr := fft_shift(v_addr); -- b = fft_shift(t)
+ -- b = fft_shift(t)
+ v_addr := fft_shift(v_addr);
else
-- With HDL fft_shift
- v_index := transpose(index, wb_factor, nof_points / wb_factor); -- t = transpose(i, 4, 8)
- v_addr := to_uvec(v_index, c_addr_w); -- b = t
+ -- t = transpose(i, 4, 8)
+ v_index := transpose(index, wb_factor, nof_points / wb_factor);
+ -- b = t
+ v_addr := to_uvec(v_index, c_addr_w);
end if;
end if;
v_bin := to_uint(v_addr);
else
-- Wideband two real input data
- v_index := transpose(index, wb_factor, nof_points / wb_factor); -- t = transpose(i, 4, 8)
- v_bin := v_index / 2; -- b = t/2
+ -- t = transpose(i, 4, 8)
+ v_index := transpose(index, wb_factor, nof_points / wb_factor);
+ -- b = t/2
+ v_bin := v_index / 2;
end if;
end if;
return v_bin;
@@ -362,7 +378,8 @@ package body tb_fft_pkg is
use_reorder : boolean;
use_fft_shift : boolean;
use_separate : boolean;
- signal out_val_cnt : in natural; -- count at sclk sample rate
+ -- count at sclk sample rate
+ signal out_val_cnt : in natural;
signal out_val : in std_logic;
signal out_val_a : out std_logic;
signal out_val_b : out std_logic;
@@ -404,33 +421,44 @@ package body tb_fft_pkg is
end if;
if use_reorder = true then
- v_blk_index := out_val_cnt / nof_points; -- each block has nof_points
- out_channel <= v_blk_index mod nof_channels; -- the nof_channels are interleaved per block
+ -- each block has nof_points
+ v_blk_index := out_val_cnt / nof_points;
+ -- the nof_channels are interleaved per block
+ out_channel <= v_blk_index mod nof_channels;
- v_index := out_val_cnt mod nof_points; -- index within a block independent of nof_channels
+ -- index within a block independent of nof_channels
+ v_index := out_val_cnt mod nof_points;
v_bin := fft_index_to_bin_frequency(wb_factor, nof_points, v_index, use_reorder, use_fft_shift, use_separate);
- out_bin <= v_bin; -- bin frequency in a block
+ -- bin frequency in a block
+ out_bin <= v_bin;
if use_separate = true then
-- Two real input data
- out_bin_cnt <= v_bin + (v_blk_index / nof_channels) * (nof_points / c_nof_complex); -- bin index in the half spectrum reference data stream of blocks
+ -- bin index in the half spectrum reference data stream of blocks
+ out_bin_cnt <= v_bin + (v_blk_index / nof_channels) * (nof_points / c_nof_complex);
else
-- Complex input data
- out_bin_cnt <= v_bin + (v_blk_index / nof_channels) * nof_points; -- bin index in the full spectrum reference data stream of blocks
+ -- bin index in the full spectrum reference data stream of blocks
+ out_bin_cnt <= v_bin + (v_blk_index / nof_channels) * nof_points;
end if;
else
-- Complex input data
- v_blk_index := out_val_cnt / nof_points / nof_channels; -- each block has nof_channels*nof_points
- out_channel <= (out_val_cnt / wb_factor) mod nof_channels; -- the nof_channels are interleaved per wb_factor number of samples
+ -- each block has nof_channels*nof_points
+ v_blk_index := out_val_cnt / nof_points / nof_channels;
+ -- the nof_channels are interleaved per wb_factor number of samples
+ out_channel <= (out_val_cnt / wb_factor) mod nof_channels;
v_index := ((out_val_cnt / wb_factor / nof_channels) * wb_factor +
- (out_val_cnt mod wb_factor)) mod nof_points; -- index within a block independent of nof_channels
+ -- index within a block independent of nof_channels
+ (out_val_cnt mod wb_factor)) mod nof_points;
v_bin := fft_index_to_bin_frequency(wb_factor, nof_points, v_index, use_reorder, use_fft_shift, use_separate);
- out_bin <= v_bin; -- bin frequency in a block
- out_bin_cnt <= v_bin + v_blk_index * nof_points; -- bin index in the full spectrum reference data stream of blocks
+ -- bin frequency in a block
+ out_bin <= v_bin;
+ -- bin index in the full spectrum reference data stream of blocks
+ out_bin_cnt <= v_bin + v_blk_index * nof_points;
end if;
end proc_fft_out_control;
@@ -461,24 +489,30 @@ package body tb_fft_pkg is
write(v_log_line, string'("reading file : "));
write(v_log_line, file_name);
writeline(output, v_log_line);
- proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE); -- Open the file with data values for reading
+ -- Open the file with data values for reading
+ proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE);
loop
exit when endfile(v_in_file);
readline(v_in_file, v_input_line);
- read(v_input_line, v_sync(v_index)); -- sync
+ -- sync
+ read(v_input_line, v_sync(v_index));
read(v_input_line, v_comma);
- read(v_input_line, v_val(v_index)); -- valid
+ -- valid
+ read(v_input_line, v_val(v_index));
read(v_input_line, v_comma);
- read(v_input_line, v_data(v_index,1)); -- real
+ -- real
+ read(v_input_line, v_data(v_index,1));
read(v_input_line, v_comma);
- read(v_input_line, v_data(v_index,2)); -- imag
+ -- imag
+ read(v_input_line, v_data(v_index,2));
v_index := v_index + 1;
end loop;
- proc_common_close_file(v_file_status, v_in_file); -- Close the file
+ -- Close the file
+ proc_common_close_file(v_file_status, v_in_file);
write(v_log_line, string'("finished reading file : "));
write(v_log_line, file_name);
writeline(output, v_log_line);
@@ -512,18 +546,22 @@ package body tb_fft_pkg is
write(v_log_line, string'("reading file : "));
write(v_log_line, file_name);
writeline(output, v_log_line);
- proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE); -- Open the file with data values for reading
+ -- Open the file with data values for reading
+ proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE);
loop
exit when v_index = in_file_data'high + 1;
readline(v_in_file, v_input_line);
- read(v_input_line, v_data(v_index,1)); -- real
+ -- real
+ read(v_input_line, v_data(v_index,1));
read(v_input_line, v_comma);
- read(v_input_line, v_data(v_index,2)); -- imag
+ -- imag
+ read(v_input_line, v_data(v_index,2));
v_index := v_index + 1;
end loop;
- proc_common_close_file(v_file_status, v_in_file); -- Close the file
+ -- Close the file
+ proc_common_close_file(v_file_status, v_in_file);
write(v_log_line, string'("finished reading file : "));
write(v_log_line, file_name);
writeline(output, v_log_line);
@@ -549,7 +587,8 @@ package body tb_fft_pkg is
v_offset := c_fft_lane * c_fft.stat_data_sz * v_nof_stats;
proc_read_subband_stats(v_nof_stats, v_offset, clk, mm_mosi, mm_miso, v_statistics_arr);
statistics_arr <= v_statistics_arr;
- proc_common_wait_some_cycles(clk, 1); -- ensure that the last statistics_arr value gets assigned too
+ -- ensure that the last statistics_arr value gets assigned too
+ proc_common_wait_some_cycles(clk, 1);
end proc_fft_read_subband_statistics_memory;
------------------------------------------------------------------------------
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd
index 18b7abe7eb2b8ed4cbcc1109a96878bc9005bf2b..94c3ab641d32f41516b13fae393a7a8862f42a36 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd
@@ -49,10 +49,12 @@ entity tb_fft_r2_bf_par is
end tb_fft_r2_bf_par;
architecture tb of tb_fft_r2_bf_par is
- constant c_pipeline : t_fft_pipeline := c_fft_pipeline; -- defined in rTwoSDF_lib.rTwoSDFPkg
+ -- defined in rTwoSDF_lib.rTwoSDFPkg
+ constant c_pipeline : t_fft_pipeline := c_fft_pipeline;
constant c_clk_period : time := 10 ns;
- constant c_nof_points : natural := 1024; -- Number of points should be a power of 2
+ -- Number of points should be a power of 2
+ constant c_nof_points : natural := 1024;
constant c_conjugate : boolean := false;
constant c_in_dat_w : natural := 16;
@@ -60,14 +62,16 @@ architecture tb of tb_fft_r2_bf_par is
constant c_prod_w : natural := c_in_dat_w + c_weight_w;
constant c_complex_prod_w : natural := c_prod_w + 1;
constant c_bit_growth : natural := 1;
- constant c_round_w : natural := c_weight_w - c_bit_growth; -- the weights are normalized
+ -- the weights are normalized
+ constant c_round_w : natural := c_weight_w - c_bit_growth;
-- BG derived constants
constant c_nof_streams : natural := 2;
constant c_bg_mem_size : natural := 1024;
constant c_bg_addr_w : natural := ceil_log2(c_bg_mem_size);
constant c_nof_samples_in_packet : natural := c_nof_points;
- constant c_gap : natural := 0; -- Gapsize is set to 0 in order to generate a continuous stream of packets.
+ -- Gapsize is set to 0 in order to generate a continuous stream of packets.
+ constant c_gap : natural := 0;
constant c_bst_skip_nof_sync : natural := 3;
constant c_nof_accum_per_sync : natural := 10;
constant c_bsn_init : natural := 32;
@@ -119,18 +123,27 @@ begin
proc_common_wait_some_cycles(clk, 10);
-- Set and enable the waveform generators. All generators are controlled by the same registers
- proc_mem_mm_bus_wr(1, c_nof_samples_in_packet, clk, reg_bg_ctrl_mosi); -- Set the number of samples per block
- proc_mem_mm_bus_wr(2, c_nof_accum_per_sync, clk, reg_bg_ctrl_mosi); -- Set the number of blocks per sync
- proc_mem_mm_bus_wr(3, c_gap, clk, reg_bg_ctrl_mosi); -- Set the gapsize
- proc_mem_mm_bus_wr(4, 0, clk, reg_bg_ctrl_mosi); -- Set the start address of the memory
- proc_mem_mm_bus_wr(5, c_nof_samples_in_packet - 1, clk, reg_bg_ctrl_mosi); -- Set the end address of the memory
- proc_mem_mm_bus_wr(6, c_bsn_init, clk, reg_bg_ctrl_mosi); -- Set the BSNInit low value
- proc_mem_mm_bus_wr(7, 0, clk, reg_bg_ctrl_mosi); -- Set the BSNInit high value
- proc_mem_mm_bus_wr(0, 1, clk, reg_bg_ctrl_mosi); -- Enable the BG
+ -- Set the number of samples per block
+ proc_mem_mm_bus_wr(1, c_nof_samples_in_packet, clk, reg_bg_ctrl_mosi);
+ -- Set the number of blocks per sync
+ proc_mem_mm_bus_wr(2, c_nof_accum_per_sync, clk, reg_bg_ctrl_mosi);
+ -- Set the gapsize
+ proc_mem_mm_bus_wr(3, c_gap, clk, reg_bg_ctrl_mosi);
+ -- Set the start address of the memory
+ proc_mem_mm_bus_wr(4, 0, clk, reg_bg_ctrl_mosi);
+ -- Set the end address of the memory
+ proc_mem_mm_bus_wr(5, c_nof_samples_in_packet - 1, clk, reg_bg_ctrl_mosi);
+ -- Set the BSNInit low value
+ proc_mem_mm_bus_wr(6, c_bsn_init, clk, reg_bg_ctrl_mosi);
+ -- Set the BSNInit high value
+ proc_mem_mm_bus_wr(7, 0, clk, reg_bg_ctrl_mosi);
+ -- Enable the BG
+ proc_mem_mm_bus_wr(0, 1, clk, reg_bg_ctrl_mosi);
-- Run time
proc_common_wait_some_cycles(clk, c_nof_points);
- proc_mem_mm_bus_wr(0, 0, clk, reg_bg_ctrl_mosi); -- Disable the BG
+ -- Disable the BG
+ proc_mem_mm_bus_wr(0, 0, clk, reg_bg_ctrl_mosi);
-- The end
proc_common_wait_some_cycles(clk, c_nof_points + 20);
@@ -142,7 +155,8 @@ begin
generic map(
g_nof_streams => c_nof_streams,
g_buf_dat_w => c_nof_complex * c_in_dat_w,
- g_buf_addr_w => c_bg_addr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_buf_addr_w => c_bg_addr_w,
g_file_name_prefix => c_bg_prefix
)
port map(
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd
index b1a979ee6a3b8d646bd43c2b1cf4a7d3d8c7dc0b..b81b8c928f1b87b95a0cb28e1c760a2cf7987692 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd
@@ -73,7 +73,8 @@ entity tb_fft_r2_par is
generic(
-- DUT generics
--g_fft : t_fft := ( true, false, true, 0, 1, 0, 128, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- two real inputs A and B
- g_fft : t_fft := ( true, false, true, 0, 1, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- two real inputs A and B
+ -- two real inputs A and B
+ g_fft : t_fft := ( true, false, true, 0, 1, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
--g_fft : t_fft := ( true, false, false, 0, 1, 0, 64, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- complex input reordered
--g_fft : t_fft := (false, false, false, 0, 1, 0, 64, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- complex input flipped
-- type t_rtwo_fft is record
@@ -95,7 +96,8 @@ entity tb_fft_r2_par is
-- end record;
--
-- TB generics
- g_diff_margin : integer := 2; -- maximum difference between HDL output and expected output (> 0 to allow minor rounding differences)
+ -- maximum difference between HDL output and expected output (> 0 to allow minor rounding differences)
+ g_diff_margin : integer := 2;
-- Two real input data files A and B used when g_fft.use_separate = true
--g_data_file_a : string := "data/run_pfft_m_sinusoid_chirp_8b_128points_16b.dat";
@@ -115,7 +117,8 @@ entity tb_fft_r2_par is
g_data_file_c_nof_lines : natural := 320;
g_data_file_nof_lines : natural := 160;
- g_enable_in_val_gaps : boolean := false -- when false then in_val flow control active continuously, else with random inactive gaps
+ -- when false then in_val flow control active continuously, else with random inactive gaps
+ g_enable_in_val_gaps : boolean := false
);
end entity tb_fft_r2_par;
@@ -125,11 +128,13 @@ architecture tb of tb_fft_r2_par is
constant c_in_complex : boolean := not g_fft.use_separate;
constant c_fft_r2_check : boolean := fft_r2_parameter_asserts(g_fft);
- constant c_nof_channels : natural := 1; -- fixed g_fft.nof_chan=0, because the concept of channels is void for the parallel FFT
+ -- fixed g_fft.nof_chan=0, because the concept of channels is void for the parallel FFT
+ constant c_nof_channels : natural := 1;
constant c_rnd_factor : natural := sel_a_b(g_enable_in_val_gaps, 3, 1);
constant c_dut_block_latency : natural := 3;
- constant c_dut_clk_latency : natural := g_fft.nof_points * c_dut_block_latency * c_rnd_factor; -- worst case
+ -- worst case
+ constant c_dut_clk_latency : natural := g_fft.nof_points * c_dut_block_latency * c_rnd_factor;
-- need to account for g_fft.nof_points, because tb verifies on serialized output
-- input/output data width
@@ -138,14 +143,20 @@ architecture tb of tb_fft_r2_par is
-- Data file access
constant c_nof_lines_header : natural := 2;
- constant c_nof_lines_a_wg_dat : natural := g_data_file_a_nof_lines; -- Real input A via in_re, one value per line
- constant c_nof_lines_a_pfft_dat : natural := g_data_file_a_nof_lines / c_nof_complex; -- Half spectrum, two values per line (re, im)
+ -- Real input A via in_re, one value per line
+ constant c_nof_lines_a_wg_dat : natural := g_data_file_a_nof_lines;
+ -- Half spectrum, two values per line (re, im)
+ constant c_nof_lines_a_pfft_dat : natural := g_data_file_a_nof_lines / c_nof_complex;
constant c_nof_lines_a_pfft_header : natural := c_nof_lines_header + c_nof_lines_a_wg_dat;
- constant c_nof_lines_b_wg_dat : natural := g_data_file_b_nof_lines; -- Real input B via in_im, one value per line
- constant c_nof_lines_b_pfft_dat : natural := g_data_file_b_nof_lines / c_nof_complex; -- Half spectrum, two values per line (re, im)
+ -- Real input B via in_im, one value per line
+ constant c_nof_lines_b_wg_dat : natural := g_data_file_b_nof_lines;
+ -- Half spectrum, two values per line (re, im)
+ constant c_nof_lines_b_pfft_dat : natural := g_data_file_b_nof_lines / c_nof_complex;
constant c_nof_lines_b_pfft_header : natural := c_nof_lines_header + c_nof_lines_b_wg_dat;
- constant c_nof_lines_c_wg_dat : natural := g_data_file_c_nof_lines; -- Complex input, two values per line (re, im)
- constant c_nof_lines_c_pfft_dat : natural := g_data_file_c_nof_lines; -- Full spectrum, two values per line (re, im)
+ -- Complex input, two values per line (re, im)
+ constant c_nof_lines_c_wg_dat : natural := g_data_file_c_nof_lines;
+ -- Full spectrum, two values per line (re, im)
+ constant c_nof_lines_c_pfft_dat : natural := g_data_file_c_nof_lines;
constant c_nof_lines_c_pfft_header : natural := c_nof_lines_header + c_nof_lines_c_wg_dat;
constant c_gap_factor : natural := sel_a_b(g_enable_in_val_gaps, 3, 1);
@@ -157,30 +168,50 @@ architecture tb of tb_fft_r2_par is
signal dut_clk : std_logic := '0';
signal tb_clk : std_logic := '0';
signal rst : std_logic := '0';
- signal random : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
-
- signal input_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- one value per line (A via re input)
- signal input_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- one value per line (B via im input)
- signal input_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0); -- two values per line (re, im)
-
- signal output_data_a_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, re
- signal output_data_a_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, im
- signal output_data_b_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, re
- signal output_data_b_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, im
- signal output_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- full spectrum, re
- signal output_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- full spectrum, im
-
- signal expected_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- half spectrum, two values per line (re, im)
- signal expected_data_a_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, re
- signal expected_data_a_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, im
- signal expected_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- half spectrum, two values per line (re, im)
- signal expected_data_b_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, re
- signal expected_data_b_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, im
- signal expected_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0); -- full spectrum, two values per line (re, im)
- signal expected_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- full spectrum, re
- signal expected_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- full spectrum, im
-
- signal t_blk : integer := 0; -- block time counter
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(15 downto 0) := (others => '0');
+
+ -- one value per line (A via re input)
+ signal input_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- one value per line (B via im input)
+ signal input_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- two values per line (re, im)
+ signal input_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0);
+
+ -- half spectrum, re
+ signal output_data_a_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, im
+ signal output_data_a_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, re
+ signal output_data_b_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, im
+ signal output_data_b_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- full spectrum, re
+ signal output_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- full spectrum, im
+ signal output_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+
+ -- half spectrum, two values per line (re, im)
+ signal expected_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- half spectrum, re
+ signal expected_data_a_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, im
+ signal expected_data_a_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, two values per line (re, im)
+ signal expected_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- half spectrum, re
+ signal expected_data_b_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, im
+ signal expected_data_b_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- full spectrum, two values per line (re, im)
+ signal expected_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0);
+ -- full spectrum, re
+ signal expected_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- full spectrum, im
+ signal expected_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+
+ -- block time counter
+ signal t_blk : integer := 0;
-- Input
signal in_dat_a : std_logic_vector(c_in_dat_w - 1 downto 0);
@@ -198,12 +229,17 @@ architecture tb of tb_fft_r2_par is
signal out_re_arr : t_fft_slv_arr(g_fft.nof_points - 1 downto 0);
signal out_im_arr : t_fft_slv_arr(g_fft.nof_points - 1 downto 0);
- signal out_val : std_logic := '0'; -- for parallel output
+ -- for parallel output
+ signal out_val : std_logic := '0';
signal out_val_cnt : natural := 0;
- signal out_channel : natural := 0; -- not used for parallel FFT, set at default 0
- signal out_val_a : std_logic := '0'; -- for real A
- signal out_val_b : std_logic := '0'; -- for real B
- signal out_val_c : std_logic := '0'; -- for complex(A,B)
+ -- not used for parallel FFT, set at default 0
+ signal out_channel : natural := 0;
+ -- for real A
+ signal out_val_a : std_logic := '0';
+ -- for real B
+ signal out_val_b : std_logic := '0';
+ -- for complex(A,B)
+ signal out_val_c : std_logic := '0';
signal out_cnt : natural := 0;
signal out_bin_cnt : natural := 0;
signal out_bin : natural;
@@ -268,12 +304,16 @@ begin
in_re_arr <= (others => (others => '0'));
in_im_arr <= (others => (others => '0'));
in_val <= '0';
- proc_common_wait_until_low(dut_clk, rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(dut_clk, 10); -- Wait an additional amount of cycles
+ -- Wait until reset has finished
+ proc_common_wait_until_low(dut_clk, rst);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(dut_clk, 10);
-- apply stimuli
- for B in 0 to g_data_file_nof_lines / g_fft.nof_points - 1 loop -- serial
- for I in 0 to g_fft.nof_points - 1 loop -- parallel
+ -- serial
+ for B in 0 to g_data_file_nof_lines / g_fft.nof_points - 1 loop
+ -- parallel
+ for I in 0 to g_fft.nof_points - 1 loop
if c_in_complex then
in_re_arr(I) <= to_fft_svec(input_data_c_arr(2 * (B * g_fft.nof_points + I)));
in_im_arr(I) <= to_fft_svec(input_data_c_arr(2 * (B * g_fft.nof_points + I) + 1));
@@ -292,7 +332,8 @@ begin
-- Wait until done
in_val <= '0';
- proc_common_wait_some_cycles(dut_clk, c_dut_clk_latency); -- wait for DUT latency
+ -- wait for DUT latency
+ proc_common_wait_some_cycles(dut_clk, c_dut_clk_latency);
tb_end_dut <= '1';
wait;
end process;
@@ -354,8 +395,10 @@ begin
proc_common_wait_until_high(tb_clk, tb_end_dut);
-- Show the input serially
- for B in 0 to g_data_file_nof_lines / g_fft.nof_points - 1 loop -- serial
- for I in 0 to g_fft.nof_points - 1 loop -- serial
+ -- serial
+ for B in 0 to g_data_file_nof_lines / g_fft.nof_points - 1 loop
+ -- serial
+ for I in 0 to g_fft.nof_points - 1 loop
if c_in_complex then
in_dat_a <= TO_SVEC(input_data_c_arr(2 * (B * g_fft.nof_points + I)), c_in_dat_w);
in_dat_b <= TO_SVEC(input_data_c_arr(2 * (B * g_fft.nof_points + I) + 1), c_in_dat_w);
@@ -378,13 +421,16 @@ begin
proc_common_wait_until_high(tb_clk, tb_end_dut);
-- Show the output serially
- for B in 0 to g_data_file_nof_lines / g_fft.nof_points - 1 loop -- serial
- for I in 0 to g_fft.nof_points - 1 loop -- serial
+ -- serial
+ for B in 0 to g_data_file_nof_lines / g_fft.nof_points - 1 loop
+ -- serial
+ for I in 0 to g_fft.nof_points - 1 loop
if c_in_complex then
out_re <= TO_SVEC(output_data_c_re_arr(B * g_fft.nof_points + I), c_out_dat_w);
out_im <= TO_SVEC(output_data_c_im_arr(B * g_fft.nof_points + I), c_out_dat_w);
else
- if I mod c_nof_complex = 0 then -- must use I here, cannot use out_cnt because then for the first two out_val_c mod will yield 0
+ -- must use I here, cannot use out_cnt because then for the first two out_val_c mod will yield 0
+ if I mod c_nof_complex = 0 then
out_re <= TO_SVEC(output_data_a_re_arr((B * g_fft.nof_points + I) / c_nof_complex), c_out_dat_w);
out_im <= TO_SVEC(output_data_a_im_arr((B * g_fft.nof_points + I) / c_nof_complex), c_out_dat_w);
else
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
index 93d3ba3dd3281658f41de6415881056cc097ec19..428293c0b4f5d777764b5bb87a232d43af688e9e 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
@@ -100,7 +100,8 @@ entity tb_fft_r2_pipe is
generic(
-- DUT generics
--g_fft : t_fft := ( true, false, true, 0, 1, 0, 128, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- two real inputs A and B
- g_fft : t_fft := ( true, false, true, 0, 1, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- two real inputs A and B
+ -- two real inputs A and B
+ g_fft : t_fft := ( true, false, true, 0, 1, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
--g_fft : t_fft := ( true, false, false, 0, 1, 0, 64, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- complex input reordered
--g_fft : t_fft := (false, false, false, 0, 1, 0, 64, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- complex input flipped
-- type t_rtwo_fft is record
@@ -122,7 +123,8 @@ entity tb_fft_r2_pipe is
-- end record;
--
-- TB generics
- g_diff_margin : integer := 2; -- maximum difference between HDL output and expected output (> 0 to allow minor rounding differences)
+ -- maximum difference between HDL output and expected output (> 0 to allow minor rounding differences)
+ g_diff_margin : integer := 2;
-- Two real input data files A and B used when g_fft.use_separate = true
-- * 128 points = 64 subbands
@@ -149,7 +151,8 @@ entity tb_fft_r2_pipe is
g_data_file_c_nof_lines : natural := 320;
g_data_file_nof_lines : natural := 6400;
- g_enable_in_val_gaps : boolean := false -- when false then in_val flow control active continuously, else with random inactive gaps
+ -- when false then in_val flow control active continuously, else with random inactive gaps
+ g_enable_in_val_gaps : boolean := false
);
end entity tb_fft_r2_pipe;
@@ -161,11 +164,13 @@ architecture tb of tb_fft_r2_pipe is
constant c_nof_channels : natural := 2**g_fft.nof_chan;
constant c_nof_data_per_block : natural := g_fft.nof_points * c_nof_channels;
- constant c_nof_valid_per_block : natural := c_nof_data_per_block; -- wb_factor=1
+ -- wb_factor=1
+ constant c_nof_valid_per_block : natural := c_nof_data_per_block;
constant c_rnd_factor : natural := sel_a_b(g_enable_in_val_gaps, 3, 1);
constant c_dut_block_latency : natural := 3;
- constant c_dut_clk_latency : natural := c_nof_valid_per_block * c_dut_block_latency * c_rnd_factor; -- worst case
+ -- worst case
+ constant c_dut_clk_latency : natural := c_nof_valid_per_block * c_dut_block_latency * c_rnd_factor;
-- input/output data width
constant c_in_dat_w : natural := g_fft.in_dat_w;
@@ -173,14 +178,20 @@ architecture tb of tb_fft_r2_pipe is
-- Data file access
constant c_nof_lines_header : natural := 2;
- constant c_nof_lines_a_wg_dat : natural := g_data_file_a_nof_lines; -- Real input A via in_re, one value per line
- constant c_nof_lines_a_pfft_dat : natural := g_data_file_a_nof_lines / c_nof_complex; -- Half spectrum, two values per line (re, im)
+ -- Real input A via in_re, one value per line
+ constant c_nof_lines_a_wg_dat : natural := g_data_file_a_nof_lines;
+ -- Half spectrum, two values per line (re, im)
+ constant c_nof_lines_a_pfft_dat : natural := g_data_file_a_nof_lines / c_nof_complex;
constant c_nof_lines_a_pfft_header : natural := c_nof_lines_header + c_nof_lines_a_wg_dat;
- constant c_nof_lines_b_wg_dat : natural := g_data_file_b_nof_lines; -- Real input B via in_im, one value per line
- constant c_nof_lines_b_pfft_dat : natural := g_data_file_b_nof_lines / c_nof_complex; -- Half spectrum, two values per line (re, im)
+ -- Real input B via in_im, one value per line
+ constant c_nof_lines_b_wg_dat : natural := g_data_file_b_nof_lines;
+ -- Half spectrum, two values per line (re, im)
+ constant c_nof_lines_b_pfft_dat : natural := g_data_file_b_nof_lines / c_nof_complex;
constant c_nof_lines_b_pfft_header : natural := c_nof_lines_header + c_nof_lines_b_wg_dat;
- constant c_nof_lines_c_wg_dat : natural := g_data_file_c_nof_lines; -- Complex input, two values per line (re, im)
- constant c_nof_lines_c_pfft_dat : natural := g_data_file_c_nof_lines; -- Full spectrum, two values per line (re, im)
+ -- Complex input, two values per line (re, im)
+ constant c_nof_lines_c_wg_dat : natural := g_data_file_c_nof_lines;
+ -- Full spectrum, two values per line (re, im)
+ constant c_nof_lines_c_pfft_dat : natural := g_data_file_c_nof_lines;
constant c_nof_lines_c_pfft_header : natural := c_nof_lines_header + c_nof_lines_c_wg_dat;
-- signal definitions
@@ -188,23 +199,37 @@ architecture tb of tb_fft_r2_pipe is
signal tb_end_almost : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic := '0';
- signal random : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
-
- signal input_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- one value per line (A via re input)
- signal input_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- one value per line (B via im input)
- signal input_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0); -- two values per line (re, im)
-
- signal expected_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- half spectrum, two values per line (re, im)
- signal expected_data_a_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, re
- signal expected_data_a_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, im
- signal expected_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- half spectrum, two values per line (re, im)
- signal expected_data_b_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, re
- signal expected_data_b_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, im
- signal expected_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0); -- full spectrum, two values per line (re, im)
- signal expected_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- full spectrum, re
- signal expected_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- full spectrum, im
-
- signal t_blk : integer := 0; -- block time counter
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(15 downto 0) := (others => '0');
+
+ -- one value per line (A via re input)
+ signal input_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- one value per line (B via im input)
+ signal input_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- two values per line (re, im)
+ signal input_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0);
+
+ -- half spectrum, two values per line (re, im)
+ signal expected_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- half spectrum, re
+ signal expected_data_a_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, im
+ signal expected_data_a_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, two values per line (re, im)
+ signal expected_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- half spectrum, re
+ signal expected_data_b_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, im
+ signal expected_data_b_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- full spectrum, two values per line (re, im)
+ signal expected_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0);
+ -- full spectrum, re
+ signal expected_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- full spectrum, im
+ signal expected_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+
+ -- block time counter
+ signal t_blk : integer := 0;
-- Input
signal in_dat_a : std_logic_vector(c_in_dat_w - 1 downto 0);
@@ -220,9 +245,12 @@ architecture tb of tb_fft_r2_pipe is
-- Output control
signal out_val_cnt : natural := 0;
- signal out_val : std_logic := '0'; -- for complex(A,B)
- signal out_val_a : std_logic := '0'; -- for real A
- signal out_val_b : std_logic := '0'; -- for real B
+ -- for complex(A,B)
+ signal out_val : std_logic := '0';
+ -- for real A
+ signal out_val_a : std_logic := '0';
+ -- for real B
+ signal out_val_b : std_logic := '0';
signal out_bin_cnt : natural := 0;
signal out_bin : natural;
signal out_channel : natural;
@@ -288,12 +316,16 @@ begin
in_dat_a <= (others => '0');
in_dat_b <= (others => '0');
in_val <= '0';
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
+ -- Wait until reset has finished
+ proc_common_wait_until_low(clk, rst);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(clk, 10);
-- apply stimuli
- for I in 0 to g_data_file_nof_lines - 1 loop -- serial
- for K in 0 to c_nof_channels - 1 loop -- serial
+ -- serial
+ for I in 0 to g_data_file_nof_lines - 1 loop
+ -- serial
+ for K in 0 to c_nof_channels - 1 loop
if c_in_complex then
in_dat_a <= TO_SVEC(input_data_c_arr(2 * I), c_in_dat_w);
in_dat_b <= TO_SVEC(input_data_c_arr(2 * I + 1), c_in_dat_w);
@@ -313,7 +345,8 @@ begin
-- Wait until done
in_val <= '0';
- proc_common_wait_some_cycles(clk, c_dut_clk_latency); -- wait for at least latency of 2 FFT block
+ -- wait for at least latency of 2 FFT block
+ proc_common_wait_some_cycles(clk, c_dut_clk_latency);
tb_end_almost <= '1';
proc_common_wait_some_cycles(clk, 100);
tb_end <= '1';
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd
index 89835d3eeb2f52f46d50d40326b2dc9247ef70e6..8e4a39385824dda87e3bd1328b67bdaa9ff16533 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd
@@ -60,7 +60,8 @@ entity tb_fft_r2_wide is
generic(
-- DUT generics
--g_fft : t_fft := ( true, false, true, 0, 4, 0, 128, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- two real inputs A and B
- g_fft : t_fft := ( true, false, true, 0, 4, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- two real inputs A and B
+ -- two real inputs A and B
+ g_fft : t_fft := ( true, false, true, 0, 4, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
--g_fft : t_fft := ( true, false, false, 0, 4, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- complex input reordered
--g_fft : t_fft := (false, false, false, 0, 4, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- complex input flipped
-- type t_rtwo_fft is record
@@ -82,7 +83,8 @@ entity tb_fft_r2_wide is
-- end record;
--
-- TB generics
- g_diff_margin : integer := 2; -- maximum difference between HDL output and expected output (> 0 to allow minor rounding differences)
+ -- maximum difference between HDL output and expected output (> 0 to allow minor rounding differences)
+ g_diff_margin : integer := 2;
-- Two real input data files A and B used when g_fft.use_separate = true
-- * 128 points = 64 subbands
@@ -119,8 +121,10 @@ entity tb_fft_r2_wide is
--g_data_file_c : string := "data/run_pfft_complex_m_noise_8b_32points_16b.dat";
--g_data_file_c_nof_lines : natural := 320;
- g_data_file_nof_lines : natural := 6400; -- actual number of lines with input data to simulate from the data files, must be <= g_data_file_*_nof_lines
- g_enable_in_val_gaps : boolean := true -- when false then in_val flow control active continuously, else with random inactive gaps
+ -- actual number of lines with input data to simulate from the data files, must be <= g_data_file_*_nof_lines
+ g_data_file_nof_lines : natural := 6400;
+ -- when false then in_val flow control active continuously, else with random inactive gaps
+ g_enable_in_val_gaps : boolean := true
);
end entity tb_fft_r2_wide;
@@ -131,13 +135,15 @@ architecture tb of tb_fft_r2_wide is
constant c_in_complex : boolean := not g_fft.use_separate;
constant c_fft_r2_check : boolean := fft_r2_parameter_asserts(g_fft);
- constant c_nof_channels : natural := 1; -- fixed g_fft.nof_chan=0, because the concept of channels is void when wb_factor > 1
+ -- fixed g_fft.nof_chan=0, because the concept of channels is void when wb_factor > 1
+ constant c_nof_channels : natural := 1;
constant c_nof_data_per_block : natural := g_fft.nof_points * c_nof_channels;
constant c_nof_valid_per_block : natural := c_nof_data_per_block / g_fft.wb_factor;
constant c_rnd_factor : natural := sel_a_b(g_enable_in_val_gaps, 3, 1);
constant c_dut_block_latency : natural := 4;
- constant c_dut_clk_latency : natural := c_nof_valid_per_block * c_dut_block_latency * c_rnd_factor + 50; -- worst case
+ -- worst case
+ constant c_dut_clk_latency : natural := c_nof_valid_per_block * c_dut_block_latency * c_rnd_factor + 50;
-- input/output data width
constant c_in_dat_w : natural := g_fft.in_dat_w;
@@ -145,17 +151,23 @@ architecture tb of tb_fft_r2_wide is
-- Data file access (Header + WG data + PFFT data)
constant c_nof_lines_header : natural := 2;
- constant c_nof_lines_a_wg_dat : natural := g_data_file_a_nof_lines; -- Real input A via in_re, one value per line
+ -- Real input A via in_re, one value per line
+ constant c_nof_lines_a_wg_dat : natural := g_data_file_a_nof_lines;
constant c_nof_lines_a_wg_header : natural := c_nof_lines_header;
- constant c_nof_lines_a_pfft_dat : natural := g_data_file_a_nof_lines / c_nof_complex; -- Half spectrum, two values per line (re, im)
+ -- Half spectrum, two values per line (re, im)
+ constant c_nof_lines_a_pfft_dat : natural := g_data_file_a_nof_lines / c_nof_complex;
constant c_nof_lines_a_pfft_header : natural := c_nof_lines_header + c_nof_lines_a_wg_dat;
- constant c_nof_lines_b_wg_dat : natural := g_data_file_b_nof_lines; -- Real input B via in_im, one value per line
+ -- Real input B via in_im, one value per line
+ constant c_nof_lines_b_wg_dat : natural := g_data_file_b_nof_lines;
constant c_nof_lines_b_wg_header : natural := c_nof_lines_header;
- constant c_nof_lines_b_pfft_dat : natural := g_data_file_b_nof_lines / c_nof_complex; -- Half spectrum, two values per line (re, im)
+ -- Half spectrum, two values per line (re, im)
+ constant c_nof_lines_b_pfft_dat : natural := g_data_file_b_nof_lines / c_nof_complex;
constant c_nof_lines_b_pfft_header : natural := c_nof_lines_header + c_nof_lines_b_wg_dat;
- constant c_nof_lines_c_wg_dat : natural := g_data_file_c_nof_lines; -- Complex input, two values per line (re, im)
+ -- Complex input, two values per line (re, im)
+ constant c_nof_lines_c_wg_dat : natural := g_data_file_c_nof_lines;
constant c_nof_lines_c_wg_header : natural := c_nof_lines_header;
- constant c_nof_lines_c_pfft_dat : natural := g_data_file_c_nof_lines; -- Full spectrum, two values per line (re, im)
+ -- Full spectrum, two values per line (re, im)
+ constant c_nof_lines_c_pfft_dat : natural := g_data_file_c_nof_lines;
constant c_nof_lines_c_pfft_header : natural := c_nof_lines_header + c_nof_lines_c_wg_dat;
-- signal definitions
@@ -164,30 +176,50 @@ architecture tb of tb_fft_r2_wide is
signal clk : std_logic := '0';
signal sclk : std_logic := '0';
signal rst : std_logic := '0';
- signal random : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
-
- signal input_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- one value per line (A via re input)
- signal input_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- one value per line (B via im input)
- signal input_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0); -- two values per line (re, im)
-
- signal output_data_a_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, re
- signal output_data_a_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, im
- signal output_data_b_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, re
- signal output_data_b_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, im
- signal output_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- full spectrum, re
- signal output_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- full spectrum, im
-
- signal expected_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- half spectrum, two values per line (re, im)
- signal expected_data_a_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, re
- signal expected_data_a_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, im
- signal expected_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- half spectrum, two values per line (re, im)
- signal expected_data_b_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, re
- signal expected_data_b_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, im
- signal expected_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0); -- full spectrum, two values per line (re, im)
- signal expected_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- full spectrum, re
- signal expected_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- full spectrum, im
-
- signal t_blk : integer := 0; -- block time counter
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(15 downto 0) := (others => '0');
+
+ -- one value per line (A via re input)
+ signal input_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- one value per line (B via im input)
+ signal input_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- two values per line (re, im)
+ signal input_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0);
+
+ -- half spectrum, re
+ signal output_data_a_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, im
+ signal output_data_a_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, re
+ signal output_data_b_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, im
+ signal output_data_b_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- full spectrum, re
+ signal output_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- full spectrum, im
+ signal output_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+
+ -- half spectrum, two values per line (re, im)
+ signal expected_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- half spectrum, re
+ signal expected_data_a_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, im
+ signal expected_data_a_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, two values per line (re, im)
+ signal expected_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- half spectrum, re
+ signal expected_data_b_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, im
+ signal expected_data_b_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- full spectrum, two values per line (re, im)
+ signal expected_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0);
+ -- full spectrum, re
+ signal expected_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- full spectrum, im
+ signal expected_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+
+ -- block time counter
+ signal t_blk : integer := 0;
-- Input
signal in_re_arr : t_fft_slv_arr(g_fft.wb_factor - 1 downto 0);
@@ -208,15 +240,19 @@ architecture tb of tb_fft_r2_wide is
signal out_im_arr : t_fft_slv_arr(g_fft.wb_factor - 1 downto 0);
signal out_re_data : std_logic_vector(g_fft.wb_factor * c_out_dat_w - 1 downto 0);
signal out_im_data : std_logic_vector(g_fft.wb_factor * c_out_dat_w - 1 downto 0);
- signal out_val : std_logic := '0'; -- for parallel output
+ -- for parallel output
+ signal out_val : std_logic := '0';
signal out_val_cnt : natural := 0;
-- Output in sclk domain
signal out_re_scope : integer := 0;
signal out_im_scope : integer := 0;
- signal out_val_a : std_logic := '0'; -- for real A
- signal out_val_b : std_logic := '0'; -- for real B
- signal out_val_c : std_logic := '0'; -- for complex(A,B)
+ -- for real A
+ signal out_val_a : std_logic := '0';
+ -- for real B
+ signal out_val_b : std_logic := '0';
+ -- for complex(A,B)
+ signal out_val_c : std_logic := '0';
signal out_channel : natural := 0;
signal out_cnt : natural := 0;
signal out_bin_cnt : natural := 0;
@@ -275,12 +311,16 @@ begin
in_re_arr <= (others => (others => '0'));
in_im_arr <= (others => (others => '0'));
in_val <= '0';
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
+ -- Wait until reset has finished
+ proc_common_wait_until_low(clk, rst);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(clk, 10);
-- apply stimuli
- for J in 0 to g_data_file_nof_lines / g_fft.wb_factor - 1 loop -- serial
- for I in 0 to g_fft.wb_factor - 1 loop -- parallel
+ -- serial
+ for J in 0 to g_data_file_nof_lines / g_fft.wb_factor - 1 loop
+ -- parallel
+ for I in 0 to g_fft.wb_factor - 1 loop
if c_in_complex then
in_re_arr(I) <= to_fft_svec(input_data_c_arr(2 * (J * g_fft.wb_factor + I)));
in_im_arr(I) <= to_fft_svec(input_data_c_arr(2 * (J * g_fft.wb_factor + I) + 1));
@@ -299,7 +339,8 @@ begin
-- Wait until done
in_val <= '0';
- proc_common_wait_some_cycles(clk, c_dut_clk_latency); -- wait for DUT latency
+ -- wait for DUT latency
+ proc_common_wait_some_cycles(clk, c_dut_clk_latency);
tb_end_almost <= '1';
proc_common_wait_some_cycles(clk, 100);
tb_end <= '1';
@@ -451,13 +492,17 @@ begin
u_in_re_scope : entity common_lib.common_wideband_data_scope
generic map (
g_sim => true,
- g_wideband_factor => g_fft.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => false, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_in_dat_w -- Actual width of the data samples
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor => g_fft.wb_factor,
+ -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian => false,
+ -- Actual width of the data samples
+ g_dat_w => c_in_dat_w
)
port map (
-- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
+ -- sample clk, use only for simulation purposes
+ SCLK => sclk,
-- Streaming input data
in_data => in_re_data,
@@ -472,13 +517,17 @@ begin
u_in_im_scope : entity common_lib.common_wideband_data_scope
generic map (
g_sim => true,
- g_wideband_factor => g_fft.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => false, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_in_dat_w -- Actual width of the data samples
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor => g_fft.wb_factor,
+ -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian => false,
+ -- Actual width of the data samples
+ g_dat_w => c_in_dat_w
)
port map (
-- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
+ -- sample clk, use only for simulation purposes
+ SCLK => sclk,
-- Streaming input data
in_data => in_im_data,
@@ -493,13 +542,17 @@ begin
u_out_re_scope : entity common_lib.common_wideband_data_scope
generic map (
g_sim => true,
- g_wideband_factor => g_fft.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => false, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_out_dat_w -- Actual width of the data samples
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor => g_fft.wb_factor,
+ -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian => false,
+ -- Actual width of the data samples
+ g_dat_w => c_out_dat_w
)
port map (
-- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
+ -- sample clk, use only for simulation purposes
+ SCLK => sclk,
-- Streaming input data
in_data => out_re_data,
@@ -514,13 +567,17 @@ begin
u_out_im_scope : entity common_lib.common_wideband_data_scope
generic map (
g_sim => true,
- g_wideband_factor => g_fft.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => false, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_out_dat_w -- Actual width of the data samples
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor => g_fft.wb_factor,
+ -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian => false,
+ -- Actual width of the data samples
+ g_dat_w => c_out_dat_w
)
port map (
-- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
+ -- sample clk, use only for simulation purposes
+ SCLK => sclk,
-- Streaming input data
in_data => out_im_data,
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
index 77204376033fcbdc6d96ffc57de7246e51f1c2c7..300b39c45264afdfdc0207102d4ccf0f2cc4e2eb 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
@@ -45,10 +45,13 @@ end tb_fft_reorder_sepa_pipe;
architecture tb of tb_fft_reorder_sepa_pipe is
constant c_clk_period : time := 10 ns;
- constant c_nof_points : natural := 16; -- Number of points should be a power of 2
+ -- Number of points should be a power of 2
+ constant c_nof_points : natural := 16;
constant c_in_dat_w : natural := 16;
- constant c_separate : boolean := true; -- When true the seperate function is enabled
- constant c_reorder : boolean := true; -- When enabled the reordering is performed
+ -- When true the seperate function is enabled
+ constant c_separate : boolean := true;
+ -- When enabled the reordering is performed
+ constant c_reorder : boolean := true;
constant c_nof_chan : natural := 1;
constant c_nof_channels : natural := 2**c_nof_chan;
@@ -58,7 +61,8 @@ architecture tb of tb_fft_reorder_sepa_pipe is
constant c_bg_mem_size : natural := 1024;
constant c_bg_addr_w : natural := ceil_log2(c_bg_mem_size);
constant c_nof_samples_in_packet : natural := c_nof_channels * c_nof_points;
- constant c_gap : natural := 0; -- Gapsize is set to 0 in order to generate a continuous stream of packets.
+ -- Gapsize is set to 0 in order to generate a continuous stream of packets.
+ constant c_gap : natural := 0;
constant c_bst_skip_nof_sync : natural := 3;
constant c_nof_accum_per_sync : natural := 10;
constant c_bsn_init : natural := 32;
@@ -101,18 +105,27 @@ begin
proc_common_wait_some_cycles(clk, 10);
-- Set and enable the waveform generators. All generators are controlled by the same registers
- proc_mem_mm_bus_wr(1, c_nof_samples_in_packet, clk, reg_bg_ctrl_mosi); -- Set the number of samples per block
- proc_mem_mm_bus_wr(2, c_nof_accum_per_sync, clk, reg_bg_ctrl_mosi); -- Set the number of blocks per sync
- proc_mem_mm_bus_wr(3, c_gap, clk, reg_bg_ctrl_mosi); -- Set the gapsize
- proc_mem_mm_bus_wr(4, 0, clk, reg_bg_ctrl_mosi); -- Set the start address of the memory
- proc_mem_mm_bus_wr(5, c_nof_samples_in_packet - 1, clk, reg_bg_ctrl_mosi); -- Set the end address of the memory
- proc_mem_mm_bus_wr(6, c_bsn_init, clk, reg_bg_ctrl_mosi); -- Set the BSNInit low value
- proc_mem_mm_bus_wr(7, 0, clk, reg_bg_ctrl_mosi); -- Set the BSNInit high value
- proc_mem_mm_bus_wr(0, 1, clk, reg_bg_ctrl_mosi); -- Enable the BG
+ -- Set the number of samples per block
+ proc_mem_mm_bus_wr(1, c_nof_samples_in_packet, clk, reg_bg_ctrl_mosi);
+ -- Set the number of blocks per sync
+ proc_mem_mm_bus_wr(2, c_nof_accum_per_sync, clk, reg_bg_ctrl_mosi);
+ -- Set the gapsize
+ proc_mem_mm_bus_wr(3, c_gap, clk, reg_bg_ctrl_mosi);
+ -- Set the start address of the memory
+ proc_mem_mm_bus_wr(4, 0, clk, reg_bg_ctrl_mosi);
+ -- Set the end address of the memory
+ proc_mem_mm_bus_wr(5, c_nof_samples_in_packet - 1, clk, reg_bg_ctrl_mosi);
+ -- Set the BSNInit low value
+ proc_mem_mm_bus_wr(6, c_bsn_init, clk, reg_bg_ctrl_mosi);
+ -- Set the BSNInit high value
+ proc_mem_mm_bus_wr(7, 0, clk, reg_bg_ctrl_mosi);
+ -- Enable the BG
+ proc_mem_mm_bus_wr(0, 1, clk, reg_bg_ctrl_mosi);
-- Run time
proc_common_wait_some_cycles(clk, 10 * c_nof_points);
- proc_mem_mm_bus_wr(0, 0, clk, reg_bg_ctrl_mosi); -- Disable the BG
+ -- Disable the BG
+ proc_mem_mm_bus_wr(0, 0, clk, reg_bg_ctrl_mosi);
-- The end
proc_common_wait_some_cycles(clk, c_nof_points + 20);
@@ -124,7 +137,8 @@ begin
generic map(
g_nof_streams => 1,
g_buf_dat_w => c_nof_complex * c_in_dat_w,
- g_buf_addr_w => c_bg_addr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_buf_addr_w => c_bg_addr_w,
g_file_name_prefix => c_bg_prefix
)
port map(
@@ -178,7 +192,8 @@ begin
wait until in_sosi_arr(0).sync = '1';
while I < c_nof_channels * c_nof_points loop
wait until (rising_edge(clk) and in_sosi_arr(0).valid = '1');
- buf_input_re(I) <= in_sosi_arr(0).re(c_in_dat_w - 1 downto 0); -- The first dataframe is latched in and used as reference
+ -- The first dataframe is latched in and used as reference
+ buf_input_re(I) <= in_sosi_arr(0).re(c_in_dat_w - 1 downto 0);
buf_input_im(I) <= in_sosi_arr(0).im(c_in_dat_w - 1 downto 0);
I := I + 1;
end loop;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
index a38cdfba6556c8596a39677d85fe580010c95cf2..a08ba08cf6cdd16bed3f7c6975b9af6c1ae3cba6 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
@@ -97,19 +97,28 @@ begin
proc_common_wait_some_cycles(clk, 10);
-- Set and enable the waveform generators. All generators are controlled by the same registers
- proc_mem_mm_bus_wr(1, c_nof_samples_in_packet, clk, reg_bg_ctrl_mosi); -- Set the number of samples per block
- proc_mem_mm_bus_wr(2, c_nof_accum_per_sync, clk, reg_bg_ctrl_mosi); -- Set the number of blocks per sync
- proc_mem_mm_bus_wr(3, c_gap, clk, reg_bg_ctrl_mosi); -- Set the gapsize
- proc_mem_mm_bus_wr(4, 0, clk, reg_bg_ctrl_mosi); -- Set the start address of the memory
- proc_mem_mm_bus_wr(5, c_nof_samples_in_packet - 1, clk, reg_bg_ctrl_mosi); -- Set the end address of the memory
- proc_mem_mm_bus_wr(6, c_bsn_init, clk, reg_bg_ctrl_mosi); -- Set the BSNInit low value
- proc_mem_mm_bus_wr(7, 0, clk, reg_bg_ctrl_mosi); -- Set the BSNInit high value
- proc_mem_mm_bus_wr(0, 1, clk, reg_bg_ctrl_mosi); -- Enable the BG
+ -- Set the number of samples per block
+ proc_mem_mm_bus_wr(1, c_nof_samples_in_packet, clk, reg_bg_ctrl_mosi);
+ -- Set the number of blocks per sync
+ proc_mem_mm_bus_wr(2, c_nof_accum_per_sync, clk, reg_bg_ctrl_mosi);
+ -- Set the gapsize
+ proc_mem_mm_bus_wr(3, c_gap, clk, reg_bg_ctrl_mosi);
+ -- Set the start address of the memory
+ proc_mem_mm_bus_wr(4, 0, clk, reg_bg_ctrl_mosi);
+ -- Set the end address of the memory
+ proc_mem_mm_bus_wr(5, c_nof_samples_in_packet - 1, clk, reg_bg_ctrl_mosi);
+ -- Set the BSNInit low value
+ proc_mem_mm_bus_wr(6, c_bsn_init, clk, reg_bg_ctrl_mosi);
+ -- Set the BSNInit high value
+ proc_mem_mm_bus_wr(7, 0, clk, reg_bg_ctrl_mosi);
+ -- Enable the BG
+ proc_mem_mm_bus_wr(0, 1, clk, reg_bg_ctrl_mosi);
-- Run time
proc_common_wait_some_cycles(clk, 300);
- proc_mem_mm_bus_wr(0, 0, clk, reg_bg_ctrl_mosi); -- Disable the BG
+ -- Disable the BG
+ proc_mem_mm_bus_wr(0, 0, clk, reg_bg_ctrl_mosi);
-- The end
proc_common_wait_some_cycles(clk, c_nof_points + 20);
@@ -121,7 +130,8 @@ begin
generic map(
g_nof_streams => 1,
g_buf_dat_w => c_nof_complex * c_in_dat_w,
- g_buf_addr_w => c_bg_addr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_buf_addr_w => c_bg_addr_w,
g_file_name_prefix => c_bg_prefix
)
port map(
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
index 26a50b4369cffd9be145d4d26a69eca61b22ff7d..6e4668bb5d67751ddca406550e93ebc54370cc5e 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
@@ -75,7 +75,8 @@ architecture tb of tb_fft_switch is
constant c_nof_block_per_sync_max : natural := ceil_div(g_nof_clk_per_sync, c_nof_clk_per_block);
constant c_nof_block_per_sync_min : natural := g_nof_clk_per_sync / c_nof_clk_per_block;
- constant c_dly : natural := 4; -- pipeling in fft_switch, mux, fft_unswitch and demux
+ -- pipeling in fft_switch, mux, fft_unswitch and demux
+ constant c_dly : natural := 4;
constant c_switch_seed1 : std_logic_vector(c_fft_lfsr_len - 1 downto 0) := fft_switch_new_seed(c_fft_switch_seed1, g_instance_index);
constant c_switch_seed2 : std_logic_vector(c_fft_lfsr_len - 1 downto 0) := fft_switch_new_seed(c_fft_switch_seed2, g_instance_index);
@@ -143,7 +144,8 @@ begin
for J in 0 to c_nof_block_per_sync_max - 1 loop
for K in 0 to c_nof_clk_per_block - 1 loop
if g_in_val_gaps and K = 0 then
- in_val <= '0'; -- insert a one cycle gap
+ -- insert a one cycle gap
+ in_val <= '0';
proc_common_wait_some_cycles(clk, 1);
end if;
in_val <= '1';
@@ -167,7 +169,8 @@ begin
rst => rst,
clk => clk,
in_val => in_val,
- out_val => OPEN, -- out_val = in_val, because g_pipeline = FALSE
+ -- out_val = in_val, because g_pipeline = FALSE
+ out_val => OPEN,
out_sop => in_sop,
out_eop => in_eop,
out_sync => in_sync
@@ -222,8 +225,10 @@ begin
mux_toggle <= not mux_toggle when rising_edge(clk) and switch_val = '1';
- mux_re <= prev1_switch_a when mux_toggle = '1' else prev2_switch_b; -- a0, b0, ..
- mux_im <= switch_a when mux_toggle = '1' else prev1_switch_b; -- a1, b1, ..
+ -- a0, b0, ..
+ mux_re <= prev1_switch_a when mux_toggle = '1' else prev2_switch_b;
+ -- a1, b1, ..
+ mux_im <= switch_a when mux_toggle = '1' else prev1_switch_b;
mux_val <= switch_val when rising_edge(clk);
u_fft_unswitch : entity work.fft_unswitch
@@ -265,8 +270,10 @@ begin
out_toggle <= not out_toggle when rising_edge(clk) and unswitch_val = '1';
- out_a <= prev1_unswitch_re when out_toggle = '1' else prev2_unswitch_im; -- a0, a1, ..
- out_b <= unswitch_re when out_toggle = '1' else prev1_unswitch_im; -- b0, b1, ..
+ -- a0, a1, ..
+ out_a <= prev1_unswitch_re when out_toggle = '1' else prev2_unswitch_im;
+ -- b0, b1, ..
+ out_b <= unswitch_re when out_toggle = '1' else prev1_unswitch_im;
out_val <= unswitch_val when rising_edge(clk);
-- Create out strobes for debugging
@@ -280,7 +287,8 @@ begin
rst => rst,
clk => clk,
in_val => out_val,
- out_val => OPEN, -- out_val = in_val, because g_pipeline = FALSE
+ -- out_val = in_val, because g_pipeline = FALSE
+ out_val => OPEN,
out_sop => out_sop,
out_eop => out_eop,
out_sync => out_sync
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
index c021f0cdfbcd402afcd91b46d856622e8ee0571b..726c7562685145141c6dc0eae9b04be42dbcf5a1 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
@@ -52,7 +52,8 @@ entity tb_fft_wide_unit is
g_use_sinus_file : boolean := false;
g_use_sinNoise_file : boolean := false;
g_use_impulse_file : boolean := false;
- g_use_2xreal_inputs : boolean := false; -- Set to true for running the two-real input variants
+ -- Set to true for running the two-real input variants
+ g_use_2xreal_inputs : boolean := false;
g_fft : t_fft := (true, false, false, 0, 4, 0, 1024, 16, 18, 0, 18, 2, true, 56, 2)
-- type t_rtwo_fft is record
-- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
@@ -80,7 +81,8 @@ architecture tb of tb_fft_wide_unit is
-- input/output data width
constant c_in_dat_w : natural := g_fft.in_dat_w;
constant c_twiddle_w : natural := 16;
- constant c_out_dat_w : natural := g_fft.out_dat_w; -- g_rtwo_fft.in_dat_w + natural((ceil_log2(g_rtwo_fft.nof_points))/2 + 2); -- bit growth
+ -- g_rtwo_fft.in_dat_w + natural((ceil_log2(g_rtwo_fft.nof_points))/2 + 2); -- bit growth
+ constant c_out_dat_w : natural := g_fft.out_dat_w;
-- input/output files
constant c_nof_spectra_in_file : natural := 4;
@@ -90,7 +92,8 @@ architecture tb of tb_fft_wide_unit is
constant c_bg_mem_size : natural := c_nof_spectra_in_file * g_fft.nof_points / g_fft.wb_factor;
constant c_bg_addr_w : natural := ceil_log2(c_bg_mem_size);
constant c_nof_samples_in_packet : natural := c_bg_mem_size / c_nof_spectra_in_file;
- constant c_gap : natural := 3; -- Gapsize is set to 0 in order to generate a continuous stream of packets.
+ -- Gapsize is set to 0 in order to generate a continuous stream of packets.
+ constant c_gap : natural := 3;
constant c_nof_accum_per_sync : natural := 8;
constant c_bsn_init : natural := 32;
constant c_bg_prefix : string := "UNUSED";
@@ -158,11 +161,13 @@ architecture tb of tb_fft_wide_unit is
signal out_re_arr : t_fft_slv_arr(g_fft.wb_factor - 1 downto 0);
signal out_im_arr : t_fft_slv_arr(g_fft.wb_factor - 1 downto 0);
- signal in_file_data : t_integer_matrix(0 to c_file_len - 1, 1 to 2) := (others => (others => 0)); -- [re, im]
+ -- [re, im]
+ signal in_file_data : t_integer_matrix(0 to c_file_len - 1, 1 to 2) := (others => (others => 0));
signal in_file_sync : std_logic_vector(0 to c_file_len - 1) := (others => '0');
signal in_file_val : std_logic_vector(0 to c_file_len - 1) := (others => '0');
- signal gold_file_data : t_integer_matrix(0 to c_file_len - 1, 1 to 2) := (others => (others => 0)); -- [re, im]
+ -- [re, im]
+ signal gold_file_data : t_integer_matrix(0 to c_file_len - 1, 1 to 2) := (others => (others => 0));
signal gold_file_sync : std_logic_vector(0 to c_file_len - 1) := (others => '0');
signal gold_file_val : std_logic_vector(0 to c_file_len - 1) := (others => '0');
@@ -213,12 +218,15 @@ begin
begin
init_waveforms_done <= '0';
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
+ -- Wait until reset has finished
+ proc_common_wait_until_low(clk, rst);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(clk, 10);
for J in 0 to c_bg_mem_size-1 loop
v_mem_data := (others => '0');
- v_mem_data := TO_SVEC(in_file_data(I + J * g_fft.wb_factor, 2), g_fft.in_dat_w) & TO_SVEC(in_file_data(I + J * g_fft.wb_factor, 1), g_fft.in_dat_w); -- two k_bf.in_dat_w = 16 fits in c_word_w = 32 bit
+ -- two k_bf.in_dat_w = 16 fits in c_word_w = 32 bit
+ v_mem_data := TO_SVEC(in_file_data(I + J * g_fft.wb_factor, 2), g_fft.in_dat_w) & TO_SVEC(in_file_data(I + J * g_fft.wb_factor, 1), g_fft.in_dat_w);
proc_mem_mm_bus_wr(J, v_mem_data, clk, ram_bg_data_mosi_arr(I));
end loop;
@@ -237,17 +245,26 @@ begin
-- Wait until reset is done
proc_common_wait_until_high(clk, rst);
proc_common_wait_some_cycles(clk, 10);
- wait until init_waveforms_done = '1'; -- Wait until the waveform data is written.
+ -- Wait until the waveform data is written.
+ wait until init_waveforms_done = '1';
-- Set and enable the waveform generators. All generators are controlled by the same registers
- proc_mem_mm_bus_wr(1, c_nof_samples_in_packet, clk, reg_bg_ctrl_mosi); -- Set the number of samples per block
- proc_mem_mm_bus_wr(2, c_nof_accum_per_sync, clk, reg_bg_ctrl_mosi); -- Set the number of blocks per sync
- proc_mem_mm_bus_wr(3, c_gap, clk, reg_bg_ctrl_mosi); -- Set the gapsize
- proc_mem_mm_bus_wr(4, 0, clk, reg_bg_ctrl_mosi); -- Set the start address of the memory
- proc_mem_mm_bus_wr(5, c_bg_mem_size-1, clk, reg_bg_ctrl_mosi); -- Set the end address of the memory
- proc_mem_mm_bus_wr(6, c_bsn_init, clk, reg_bg_ctrl_mosi); -- Set the BSNInit low value
- proc_mem_mm_bus_wr(7, 0, clk, reg_bg_ctrl_mosi); -- Set the BSNInit high value
- proc_mem_mm_bus_wr(0, 1, clk, reg_bg_ctrl_mosi); -- Enable the BG
+ -- Set the number of samples per block
+ proc_mem_mm_bus_wr(1, c_nof_samples_in_packet, clk, reg_bg_ctrl_mosi);
+ -- Set the number of blocks per sync
+ proc_mem_mm_bus_wr(2, c_nof_accum_per_sync, clk, reg_bg_ctrl_mosi);
+ -- Set the gapsize
+ proc_mem_mm_bus_wr(3, c_gap, clk, reg_bg_ctrl_mosi);
+ -- Set the start address of the memory
+ proc_mem_mm_bus_wr(4, 0, clk, reg_bg_ctrl_mosi);
+ -- Set the end address of the memory
+ proc_mem_mm_bus_wr(5, c_bg_mem_size-1, clk, reg_bg_ctrl_mosi);
+ -- Set the BSNInit low value
+ proc_mem_mm_bus_wr(6, c_bsn_init, clk, reg_bg_ctrl_mosi);
+ -- Set the BSNInit high value
+ proc_mem_mm_bus_wr(7, 0, clk, reg_bg_ctrl_mosi);
+ -- Enable the BG
+ proc_mem_mm_bus_wr(0, 1, clk, reg_bg_ctrl_mosi);
-- Run time is defined by:
-- * the number of sync periods
@@ -302,7 +319,8 @@ begin
p_read_sst_memory : process
variable c_sync_cnt : natural;
begin
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
+ -- Wait until reset has finished
+ proc_common_wait_until_low(clk, rst);
-- Skip reading for the initial syncs to save simulation time
for J in 0 to c_bst_skip_nof_sync - 2 loop
@@ -316,7 +334,8 @@ begin
for I in 0 to g_fft.wb_factor - 1 loop
proc_fft_read_subband_statistics_memory(I, g_fft, clk, ram_sst_mosi, ram_sst_miso, result_sst_arr_temp);
- result_sst_arr((I + 1) * c_nof_samples_in_packet - 1 downto I * c_nof_samples_in_packet) <= result_sst_arr_temp; -- can not use result_bst_arr2(I) directly as argument in proc_bf_read_beamlet_statistics_memory()
+ -- can not use result_bst_arr2(I) directly as argument in proc_bf_read_beamlet_statistics_memory()
+ result_sst_arr((I + 1) * c_nof_samples_in_packet - 1 downto I * c_nof_samples_in_packet) <= result_sst_arr_temp;
end loop;
end loop;
end process;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2.vhd b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2.vhd
index 3551d700653c7f3a813d3007d3efcb0bf0ec9fed..3d78898541c838aaa4a09a8496f61b8e5bd6d183 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2.vhd
@@ -60,14 +60,22 @@ use work.fft_pkg.all;
entity tb_mmf_fft_r2 is
generic(
- g_fft_type : string := "wide"; -- = default "wide", 3 fft types possible: pipe, wide or par
- g_nof_chan : natural := 0; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
- g_wb_factor : natural := 4; -- = default 1, wideband factor
- g_nof_points : natural := 1024; -- = 1024, N point FFT
- g_nof_blocks : natural := 4; -- = 4, the number of blocks of g_nof_points each in the BG waveform (must be power of 2 due to that BG c_bg_block_len must be power of 2)
- g_in_dat_w : natural := 8; -- = 8, number of input bits
- g_out_dat_w : natural := 16; -- = 14, number of output bits: in_dat_w + natural((ceil_log2(nof_points))/2)
- g_use_separate : boolean := false -- = false for complex input, true for two real inputs
+ -- = default "wide", 3 fft types possible: pipe, wide or par
+ g_fft_type : string := "wide";
+ -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
+ g_nof_chan : natural := 0;
+ -- = default 1, wideband factor
+ g_wb_factor : natural := 4;
+ -- = 1024, N point FFT
+ g_nof_points : natural := 1024;
+ -- = 4, the number of blocks of g_nof_points each in the BG waveform (must be power of 2 due to that BG c_bg_block_len must be power of 2)
+ g_nof_blocks : natural := 4;
+ -- = 8, number of input bits
+ g_in_dat_w : natural := 8;
+ -- = 14, number of output bits: in_dat_w + natural((ceil_log2(nof_points))/2)
+ g_out_dat_w : natural := 16;
+ -- = false for complex input, true for two real inputs
+ g_use_separate : boolean := false
);
end tb_mmf_fft_r2;
@@ -206,7 +214,8 @@ begin
generic map(
g_nof_streams => c_nof_streams,
g_buf_dat_w => c_nof_complex * c_fft.in_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => c_bg_data_file_index_arr,
g_file_name_prefix => c_bg_data_file_prefix
)
@@ -253,7 +262,8 @@ begin
gen_wideband_fft : if g_fft_type = "wide" generate
u_dut : entity work.fft_r2_wide
generic map(
- g_fft => c_fft -- generics for the FFT
+ -- generics for the FFT
+ g_fft => c_fft
)
port map(
clk => dp_clk,
diff --git a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_par.vhd
index 2a417eabe34d99cb906490978017b3db3a1804b6..90a02cfa8844665fce0d93f921a53899dbf54488 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_par.vhd
@@ -182,7 +182,8 @@ begin
generic map(
g_nof_output_streams => c_nof_streams,
g_buf_dat_w => c_nof_complex * g_fft.in_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => c_bg_data_file_index_arr,
g_file_name_prefix => c_bg_data_file_prefix
)
@@ -213,7 +214,8 @@ begin
-- DUT = Device Under Test
u_dut : entity work.fft_r2_par
generic map(
- g_fft => g_fft -- generics for the FFT
+ -- generics for the FFT
+ g_fft => g_fft
)
port map(
clk => dp_clk,
diff --git a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_pipe.vhd
index 39505893a1e74df511195a6126dec3c0b7e51b8c..f456aa44ce0a959c4c14e583e66402c557af3fd6 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_pipe.vhd
@@ -184,7 +184,8 @@ begin
generic map(
g_nof_output_streams => c_nof_streams,
g_buf_dat_w => c_nof_complex * g_fft.in_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => c_bg_data_file_index_arr,
g_file_name_prefix => c_bg_data_file_prefix
)
@@ -212,7 +213,8 @@ begin
-- DUT = Device Under Test
u_dut : entity work.fft_r2_pipe
generic map(
- g_fft => g_fft -- generics for the FFT
+ -- generics for the FFT
+ g_fft => g_fft
)
port map(
clk => dp_clk,
diff --git a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_wide_unit.vhd b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_wide_unit.vhd
index acc5adb12335c174634fa5519fb76d6cd1c8ba4b..8c2779693aa349f3bab24b5a75f4a6f27717417b 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_wide_unit.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_wide_unit.vhd
@@ -58,14 +58,22 @@ use work.fft_pkg.all;
entity tb_mmf_fft_wide_unit is
generic(
- g_fft_type : string := "wide"; -- = default "wide", 3 fft types possible: pipe, wide or par
- g_nof_chan : natural := 0; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
- g_wb_factor : natural := 4; -- = default 1, wideband factor
- g_nof_points : natural := 64; -- = 1024, N point FFT
- g_nof_integrations : natural := 4; -- = 4, the number of accumulations.
- g_in_dat_w : natural := 8; -- = 8, number of input bits
- g_out_dat_w : natural := 14; -- = 14, number of output bits: in_dat_w + natural((ceil_log2(nof_points))/2)
- g_use_separate : boolean := false -- = false for complex input, true for two real inputs
+ -- = default "wide", 3 fft types possible: pipe, wide or par
+ g_fft_type : string := "wide";
+ -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
+ g_nof_chan : natural := 0;
+ -- = default 1, wideband factor
+ g_wb_factor : natural := 4;
+ -- = 1024, N point FFT
+ g_nof_points : natural := 64;
+ -- = 4, the number of accumulations.
+ g_nof_integrations : natural := 4;
+ -- = 8, number of input bits
+ g_in_dat_w : natural := 8;
+ -- = 14, number of output bits: in_dat_w + natural((ceil_log2(nof_points))/2)
+ g_out_dat_w : natural := 14;
+ -- = false for complex input, true for two real inputs
+ g_use_separate : boolean := false
);
end tb_mmf_fft_wide_unit;
@@ -202,7 +210,8 @@ begin
generic map(
g_nof_streams => c_nof_streams,
g_buf_dat_w => c_nof_complex * c_fft.in_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => c_bg_data_file_index_arr,
g_file_name_prefix => c_bg_data_file_prefix
)
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
index 090afe6549ebe2b22a30c126786824e7431d5818..5f4d52dbf436b348e3bcf0406f09852bdd490453 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
@@ -46,19 +46,27 @@ architecture tb of tb_tb_fft_r2_par is
constant c_diff_margin : natural := 2;
-- Real input
- constant c_impulse_chirp : string := "data/run_pfft_m_impulse_chirp_8b_128points_16b.dat"; -- 25600 lines
- constant c_sinusoid_chirp : string := "data/run_pfft_m_sinusoid_chirp_8b_128points_16b.dat"; -- 25600 lines
- constant c_noise : string := "data/run_pfft_m_noise_8b_128points_16b.dat"; -- 1280 lines
- constant c_dc_agwn : string := "data/run_pfft_m_dc_agwn_8b_128points_16b.dat"; -- 1280 lines
+ -- 25600 lines
+ constant c_impulse_chirp : string := "data/run_pfft_m_impulse_chirp_8b_128points_16b.dat";
+ -- 25600 lines
+ constant c_sinusoid_chirp : string := "data/run_pfft_m_sinusoid_chirp_8b_128points_16b.dat";
+ -- 1280 lines
+ constant c_noise : string := "data/run_pfft_m_noise_8b_128points_16b.dat";
+ -- 1280 lines
+ constant c_dc_agwn : string := "data/run_pfft_m_dc_agwn_8b_128points_16b.dat";
-- Complex input
- constant c_phasor_chirp : string := "data/run_pfft_complex_m_phasor_chirp_8b_64points_16b.dat"; -- 12800 lines
- constant c_phasor : string := "data/run_pfft_complex_m_phasor_8b_64points_16b.dat"; -- 320 lines
- constant c_noise_complex : string := "data/run_pfft_complex_m_noise_complex_8b_64points_16b.dat"; -- 620 lines
+ -- 12800 lines
+ constant c_phasor_chirp : string := "data/run_pfft_complex_m_phasor_chirp_8b_64points_16b.dat";
+ -- 320 lines
+ constant c_phasor : string := "data/run_pfft_complex_m_phasor_8b_64points_16b.dat";
+ -- 620 lines
+ constant c_noise_complex : string := "data/run_pfft_complex_m_noise_complex_8b_64points_16b.dat";
-- Zero input
constant c_zero : string := "UNUSED";
constant c_unused : string := "UNUSED";
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- DUT generics
-- g_fft : t_fft := (true, false, true, 0, 1, 0, 128, 9, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
index 2a72e3c1debfd1911644188ff18c1a0115b6653b..46d02e59df3d256dc3bcb2418ee4928d03190bbb 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
@@ -50,20 +50,29 @@ architecture tb of tb_tb_fft_r2_pipe is
constant c_diff_margin : natural := 2;
-- Real input
- constant c_impulse_chirp : string := "data/run_pfft_m_impulse_chirp_8b_128points_16b.dat"; -- 25600 lines
- constant c_sinusoid_chirp : string := "data/run_pfft_m_sinusoid_chirp_8b_128points_16b.dat"; -- 25600 lines
- constant c_sinusoid : string := "data/run_pfft_m_sinusoid_8b_128points_16b.dat"; -- 640 lines
- constant c_noise : string := "data/run_pfft_m_noise_8b_128points_16b.dat"; -- 1280 lines
- constant c_dc_agwn : string := "data/run_pfft_m_dc_agwn_8b_128points_16b.dat"; -- 1280 lines
+ -- 25600 lines
+ constant c_impulse_chirp : string := "data/run_pfft_m_impulse_chirp_8b_128points_16b.dat";
+ -- 25600 lines
+ constant c_sinusoid_chirp : string := "data/run_pfft_m_sinusoid_chirp_8b_128points_16b.dat";
+ -- 640 lines
+ constant c_sinusoid : string := "data/run_pfft_m_sinusoid_8b_128points_16b.dat";
+ -- 1280 lines
+ constant c_noise : string := "data/run_pfft_m_noise_8b_128points_16b.dat";
+ -- 1280 lines
+ constant c_dc_agwn : string := "data/run_pfft_m_dc_agwn_8b_128points_16b.dat";
-- Complex input
- constant c_phasor_chirp : string := "data/run_pfft_complex_m_phasor_chirp_8b_64points_16b.dat"; -- 12800 lines
- constant c_phasor : string := "data/run_pfft_complex_m_phasor_8b_64points_16b.dat"; -- 320 lines
- constant c_noise_complex : string := "data/run_pfft_complex_m_noise_complex_8b_64points_16b.dat"; -- 620 lines
+ -- 12800 lines
+ constant c_phasor_chirp : string := "data/run_pfft_complex_m_phasor_chirp_8b_64points_16b.dat";
+ -- 320 lines
+ constant c_phasor : string := "data/run_pfft_complex_m_phasor_8b_64points_16b.dat";
+ -- 620 lines
+ constant c_noise_complex : string := "data/run_pfft_complex_m_noise_complex_8b_64points_16b.dat";
-- Zero input
constant c_zero : string := "UNUSED";
constant c_unused : string := "UNUSED";
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- DUT generics
-- g_fft : t_fft := (true, false, true, 0, 1, 0, 128, 9, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
index e48519e06488aa21fd264b6990cbbb25c3c8c8de..f10a7cdeec84824a419201d20d73c478be11f332 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
@@ -51,19 +51,27 @@ architecture tb of tb_tb_fft_r2_wide is
constant c_diff_margin : natural := 2;
-- Real input
- constant c_impulse_chirp : string := "data/run_pfft_m_impulse_chirp_8b_128points_16b.dat"; -- 25600 lines
- constant c_sinusoid_chirp : string := "data/run_pfft_m_sinusoid_chirp_8b_128points_16b.dat"; -- 25600 lines
- constant c_noise : string := "data/run_pfft_m_noise_8b_128points_16b.dat"; -- 1280 lines
- constant c_dc_agwn : string := "data/run_pfft_m_dc_agwn_8b_128points_16b.dat"; -- 1280 lines
+ -- 25600 lines
+ constant c_impulse_chirp : string := "data/run_pfft_m_impulse_chirp_8b_128points_16b.dat";
+ -- 25600 lines
+ constant c_sinusoid_chirp : string := "data/run_pfft_m_sinusoid_chirp_8b_128points_16b.dat";
+ -- 1280 lines
+ constant c_noise : string := "data/run_pfft_m_noise_8b_128points_16b.dat";
+ -- 1280 lines
+ constant c_dc_agwn : string := "data/run_pfft_m_dc_agwn_8b_128points_16b.dat";
-- Complex input
- constant c_phasor_chirp : string := "data/run_pfft_complex_m_phasor_chirp_8b_64points_16b.dat"; -- 12800 lines
- constant c_phasor : string := "data/run_pfft_complex_m_phasor_8b_64points_16b.dat"; -- 320 lines
- constant c_noise_complex : string := "data/run_pfft_complex_m_noise_complex_8b_64points_16b.dat"; -- 620 lines
+ -- 12800 lines
+ constant c_phasor_chirp : string := "data/run_pfft_complex_m_phasor_chirp_8b_64points_16b.dat";
+ -- 320 lines
+ constant c_phasor : string := "data/run_pfft_complex_m_phasor_8b_64points_16b.dat";
+ -- 620 lines
+ constant c_noise_complex : string := "data/run_pfft_complex_m_noise_complex_8b_64points_16b.dat";
-- Zero input
constant c_zero : string := "UNUSED";
constant c_unused : string := "UNUSED";
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- DUT generics
-- --g_fft : t_fft := ( true, false, true, 0, 4, 0, 128, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- two real inputs A and B
diff --git a/libraries/dsp/filter/src/vhdl/fil_pkg.vhd b/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
index 0526a3ce5ecbaa98eec8d26bc75235c70956880a..d093a4d548d9a6381392afe6c279118c252f56fd 100644
--- a/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
@@ -26,36 +26,54 @@ use common_lib.common_pkg.all;
package fil_pkg is
-- Parameters for the (wideband) poly phase filter.
type t_fil_ppf is record
- wb_factor : natural; -- = 1, the wideband factor
- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
- nof_bands : natural; -- = 1024, the number of polyphase channels (= number of points of the FFT)
- nof_taps : natural; -- = 16, the number of FIR taps per subband
- nof_streams : natural; -- = 1, the number of streams that are served by the same coefficients.
- backoff_w : natural; -- = 0, number of bits for input backoff to avoid output overflow
- in_dat_w : natural; -- = 8, number of input bits per stream
- out_dat_w : natural; -- = 16, number of output bits per stream
- coef_dat_w : natural; -- = 16, data width of the FIR coefficients
+ -- = 1, the wideband factor
+ wb_factor : natural;
+ -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
+ nof_chan : natural;
+ -- = 1024, the number of polyphase channels (= number of points of the FFT)
+ nof_bands : natural;
+ -- = 16, the number of FIR taps per subband
+ nof_taps : natural;
+ -- = 1, the number of streams that are served by the same coefficients.
+ nof_streams : natural;
+ -- = 0, number of bits for input backoff to avoid output overflow
+ backoff_w : natural;
+ -- = 8, number of input bits per stream
+ in_dat_w : natural;
+ -- = 16, number of output bits per stream
+ out_dat_w : natural;
+ -- = 16, data width of the FIR coefficients
+ coef_dat_w : natural;
end record;
constant c_fil_ppf : t_fil_ppf := (1, 0, 1024, 16, 1, 0, 8, 16, 16);
-- Definitions for fil slv array (an array can not have unconstraint elements, so choose sufficiently wide 32 bit slv elements)
- subtype t_fil_slv_arr is t_slv_32_arr; -- use subtype to ease interfacing to existing types and to have central definition for filter components
- constant c_fil_slv_w : natural := 32; -- match slv width of t_fil_slv_arr
+ -- use subtype to ease interfacing to existing types and to have central definition for filter components
+ subtype t_fil_slv_arr is t_slv_32_arr;
+ -- match slv width of t_fil_slv_arr
+ constant c_fil_slv_w : natural := 32;
-- Record with the pipeline settings for the filter units.
type t_fil_ppf_pipeline is record
-- generic for the taps and coefficients memory
- mem_delay : natural; -- = 1
+ -- = 1
+ mem_delay : natural;
-- generics for the multiplier in in the filter unit
- mult_input : natural; -- = 1
- mult_product : natural; -- = 1
- mult_output : natural; -- = 1
+ -- = 1
+ mult_input : natural;
+ -- = 1
+ mult_product : natural;
+ -- = 1
+ mult_output : natural;
-- generics for the adder tree in in the filter unit
- adder_stage : natural; -- = 1
+ -- = 1
+ adder_stage : natural;
-- generics for the requantizer in the filter unit
- requant_remove_lsb : natural; -- = 1
- requant_remove_msb : natural; -- = 0
+ -- = 1
+ requant_remove_lsb : natural;
+ -- = 0
+ requant_remove_msb : natural;
end record;
constant c_fil_ppf_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd
index b77dcee842f9d7d1b8b0c4e95ab2215fccf8ea44..1819c9d6f0a1da18bd3a65839d539318a2aae2f2 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd
@@ -60,7 +60,8 @@ architecture rtl of fil_ppf_ctrl is
type t_in_dat_delay is array (g_fil_ppf_pipeline.mem_delay downto 0) of std_logic_vector(g_fil_ppf.in_dat_w * g_fil_ppf.nof_streams - 1 downto 0);
constant c_addr_w : natural := ceil_log2(g_fil_ppf.nof_bands * (2**g_fil_ppf.nof_chan));
- constant c_ctrl_latency : natural := 1; -- due to taps_out_vec register
+ -- due to taps_out_vec register
+ constant c_ctrl_latency : natural := 1;
constant c_mult_latency : natural := g_fil_ppf_pipeline.mult_input + g_fil_ppf_pipeline.mult_product + g_fil_ppf_pipeline.mult_output;
constant c_adder_latency : natural := ceil_log2(g_fil_ppf.nof_taps) * g_fil_ppf_pipeline.adder_stage;
constant c_filter_zdly : natural := g_fil_ppf.nof_bands * (2**g_fil_ppf.nof_chan);
@@ -73,14 +74,22 @@ architecture rtl of fil_ppf_ctrl is
constant c_taps_vec_w : natural := c_single_taps_vec_w * g_fil_ppf.nof_streams;
type reg_type is record
- in_dat_arr : t_in_dat_delay; -- Input register for the data
- init_dly_cnt : integer range 0 to c_filter_zdly; -- Counter used to overcome the settling time of the filter.
- val_dly : std_logic_vector(c_tot_latency - 1 downto 0); -- Delay register for the valid signal
- rd_addr : std_logic_vector(c_addr_w - 1 downto 0); -- The read address
- wr_addr : std_logic_vector(c_addr_w - 1 downto 0); -- The write address
- wr_en : std_logic; -- Write enable signal for the taps memory
- taps_out_vec : std_logic_vector(c_taps_vec_w - 1 downto 0); -- Output register containing the next taps data
- out_val_ena : std_logic; -- Output enable
+ -- Input register for the data
+ in_dat_arr : t_in_dat_delay;
+ -- Counter used to overcome the settling time of the filter.
+ init_dly_cnt : integer range 0 to c_filter_zdly;
+ -- Delay register for the valid signal
+ val_dly : std_logic_vector(c_tot_latency - 1 downto 0);
+ -- The read address
+ rd_addr : std_logic_vector(c_addr_w - 1 downto 0);
+ -- The write address
+ wr_addr : std_logic_vector(c_addr_w - 1 downto 0);
+ -- Write enable signal for the taps memory
+ wr_en : std_logic;
+ -- Output register containing the next taps data
+ taps_out_vec : std_logic_vector(c_taps_vec_w - 1 downto 0);
+ -- Output enable
+ out_val_ena : std_logic;
end record;
signal r, rin : reg_type;
@@ -100,11 +109,13 @@ begin
v.in_dat_arr(0) := RESIZE_SVEC(in_dat, r.in_dat_arr(0)'length);
v.in_dat_arr(g_fil_ppf_pipeline.mem_delay downto 1) := r.in_dat_arr(g_fil_ppf_pipeline.mem_delay - 1 downto 0);
- if(r.val_dly(0) = '1') then -- Wait for incoming data
+ -- Wait for incoming data
+ if(r.val_dly(0) = '1') then
v.rd_addr := INCR_UVEC(r.rd_addr, 1);
end if;
- if(r.val_dly(c_tot_latency - 2) = '1') then -- Wait for incoming data
+ -- Wait for incoming data
+ if(r.val_dly(c_tot_latency - 2) = '1') then
if(r.init_dly_cnt < c_filter_zdly) then
v.init_dly_cnt := r.init_dly_cnt + 1;
v.out_val_ena := '0';
diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd
index d1e6c814ba9153ee28976ceb44f0fe90bb6a7503..628dd41ab0198fb75582525cd5f7a4a2bf470717 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd
@@ -51,9 +51,12 @@ entity fil_ppf_filter is
end fil_ppf_filter;
architecture rtl of fil_ppf_filter is
- constant c_in_dat_w : natural := g_fil_ppf.backoff_w + g_fil_ppf.in_dat_w; -- add optional input backoff to fit output overshoot
- constant c_prod_w : natural := c_in_dat_w + g_fil_ppf.coef_dat_w - c_sign_w; -- skip double sign bit
- constant c_gain_w : natural := 0; -- no need for adder bit growth so fixed 0, because filter coefficients should have DC gain <= 1.
+ -- add optional input backoff to fit output overshoot
+ constant c_in_dat_w : natural := g_fil_ppf.backoff_w + g_fil_ppf.in_dat_w;
+ -- skip double sign bit
+ constant c_prod_w : natural := c_in_dat_w + g_fil_ppf.coef_dat_w - c_sign_w;
+ -- no need for adder bit growth so fixed 0, because filter coefficients should have DC gain <= 1.
+ constant c_gain_w : natural := 0;
-- The adder tree bit growth depends on DC gain of FIR coefficients, not on ceil_log2(g_fil_ppf.nof_taps).
constant c_sum_w : natural := c_prod_w + c_gain_w;
constant c_ppf_lsb_w : natural := c_sum_w - g_fil_ppf.out_dat_w;
@@ -62,10 +65,13 @@ architecture rtl of fil_ppf_filter is
signal adder_out : std_logic_vector(c_sum_w - 1 downto 0) := (others => '0');
signal requant_out : std_logic_vector(g_fil_ppf.out_dat_w - 1 downto 0);
- signal in_taps : std_logic_vector(g_fil_ppf.in_dat_w * g_fil_ppf.nof_taps - 1 downto 0); -- taps input data as stored in RAM
- signal in_taps_backoff : std_logic_vector( c_in_dat_w * g_fil_ppf.nof_taps - 1 downto 0); -- taps input data with backoff as use in FIR
+ -- taps input data as stored in RAM
+ signal in_taps : std_logic_vector(g_fil_ppf.in_dat_w * g_fil_ppf.nof_taps - 1 downto 0);
+ -- taps input data with backoff as use in FIR
+ signal in_taps_backoff : std_logic_vector( c_in_dat_w * g_fil_ppf.nof_taps - 1 downto 0);
begin
- in_taps <= taps; -- Use this help signal to create a 'HIGH downto 0 vector again.
+ -- Use this help signal to create a 'HIGH downto 0 vector again.
+ in_taps <= taps;
---------------------------------------------------------------
-- GENERATE THE MUTIPLIERS
---------------------------------------------------------------
diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_single.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_single.vhd
index 57baa9b3d81173fd21aed4064e85f68dd5160027..e5dc10aecba10472756a892209919f8307c44ae1 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_single.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_single.vhd
@@ -75,9 +75,12 @@ entity fil_ppf_single is
g_fil_ppf : t_fil_ppf := c_fil_ppf;
g_fil_ppf_pipeline : t_fil_ppf_pipeline := c_fil_ppf_pipeline;
g_round_even : boolean := true;
- g_file_index_arr : t_nat_natural_arr := array_init(0, 128, 1); -- default use the instance index as file index 0, 1, 2, 3, 4 ...
- g_coefs_file_prefix : string := "hex/coef" -- Relative path to the mif files that contain the initial data for the coefficients memories
- ); -- The sequence number and ".mif"-extension are added within the entity.
+ -- default use the instance index as file index 0, 1, 2, 3, 4 ...
+ g_file_index_arr : t_nat_natural_arr := array_init(0, 128, 1);
+ -- Relative path to the mif files that contain the initial data for the coefficients memories
+ g_coefs_file_prefix : string := "hex/coef"
+ -- The sequence number and ".mif"-extension are added within the entity.
+ );
port (
dp_clk : in std_logic;
dp_rst : in std_logic;
@@ -105,13 +108,15 @@ architecture rtl of fil_ppf_single is
adr_w => c_taps_mem_addr_w,
dat_w => c_taps_mem_data_w,
nof_dat => g_fil_ppf.nof_bands * (2**g_fil_ppf.nof_chan),
- init_sl => '0'); -- use '0' instead of 'X' to avoid RTL RAM simulation warnings due to read before write
+ -- use '0' instead of 'X' to avoid RTL RAM simulation warnings due to read before write
+ init_sl => '0');
constant c_coef_mem : t_c_mem := (latency => c_coef_mem_delay,
adr_w => c_coef_mem_addr_w,
dat_w => c_coef_mem_data_w,
nof_dat => g_fil_ppf.nof_bands,
- init_sl => '0'); -- use '0' instead of 'X' to avoid RTL RAM simulation warnings due to read before write
+ -- use '0' instead of 'X' to avoid RTL RAM simulation warnings due to read before write
+ init_sl => '0');
signal ram_coefs_mosi_arr : t_mem_mosi_arr(g_fil_ppf.nof_taps - 1 downto 0);
signal ram_coefs_miso_arr : t_mem_miso_arr(g_fil_ppf.nof_taps - 1 downto 0) := (others => c_mem_miso_rst);
@@ -130,7 +135,8 @@ begin
u_taps_mem : entity common_lib.common_ram_r_w
generic map (
g_ram => c_taps_mem,
- g_init_file => "UNUSED" -- assume block RAM gets initialized to '0' by default in simulation
+ -- assume block RAM gets initialized to '0' by default in simulation
+ g_init_file => "UNUSED"
)
port map (
rst => dp_rst,
diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd
index fa57b10ec687002f24b5ce222d5b89a86a2f3e30..e9521a71ffa4cf8b24661cdcbe8289542e24a823 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd
@@ -122,7 +122,8 @@ entity fil_ppf_wide is
g_fil_ppf : t_fil_ppf := c_fil_ppf;
g_fil_ppf_pipeline : t_fil_ppf_pipeline := c_fil_ppf_pipeline;
g_round_even : boolean := true;
- g_coefs_file_prefix : string := "../../data/coef" -- Relative path to the mif files that contain the FIR the coefficients
+ -- Relative path to the mif files that contain the FIR the coefficients
+ g_coefs_file_prefix : string := "../../data/coef"
-- The sequence number and ".mif"-extension are added within the entity.
);
port (
@@ -132,19 +133,24 @@ entity fil_ppf_wide is
mm_rst : in std_logic;
ram_coefs_mosi : in t_mem_mosi;
ram_coefs_miso : out t_mem_miso := c_mem_miso_rst;
- in_dat_arr : in t_fil_slv_arr(g_fil_ppf.wb_factor * g_fil_ppf.nof_streams - 1 downto 0); -- = t_slv_32_arr fits g_fil_ppf.in_dat_w <= 32
+ -- = t_slv_32_arr fits g_fil_ppf.in_dat_w <= 32
+ in_dat_arr : in t_fil_slv_arr(g_fil_ppf.wb_factor * g_fil_ppf.nof_streams - 1 downto 0);
in_val : in std_logic;
- out_dat_arr : out t_fil_slv_arr(g_fil_ppf.wb_factor * g_fil_ppf.nof_streams - 1 downto 0); -- = t_slv_32_arr fits g_fil_ppf.out_dat_w <= 32
+ -- = t_slv_32_arr fits g_fil_ppf.out_dat_w <= 32
+ out_dat_arr : out t_fil_slv_arr(g_fil_ppf.wb_factor * g_fil_ppf.nof_streams - 1 downto 0);
out_val : out std_logic
);
end fil_ppf_wide;
architecture rtl of fil_ppf_wide is
constant c_nof_mif_files : natural := g_fil_ppf.wb_factor * g_fil_ppf.nof_taps;
- constant c_file_index_arr : t_nat_natural_arr := array_init(0, c_nof_mif_files, 1); -- use the instance index as file index 0, 1, 2, 3, 4 ...
+ -- use the instance index as file index 0, 1, 2, 3, 4 ...
+ constant c_file_index_arr : t_nat_natural_arr := array_init(0, c_nof_mif_files, 1);
- type t_fil_ppf_arr is array(integer range <> ) of t_fil_ppf; -- An array of t_fil_ppf's generics.
- type t_nat_natural_arr2 is array(integer range <> ) of t_nat_natural_arr(g_fil_ppf.nof_taps - 1 downto 0); -- An array of arrays, used to point to the right .mif files for the coefficients
+ -- An array of t_fil_ppf's generics.
+ type t_fil_ppf_arr is array(integer range <> ) of t_fil_ppf;
+ -- An array of arrays, used to point to the right .mif files for the coefficients
+ type t_nat_natural_arr2 is array(integer range <> ) of t_nat_natural_arr(g_fil_ppf.nof_taps - 1 downto 0);
type t_streams_in_arr is array(integer range <> ) of std_logic_vector(g_fil_ppf.nof_streams * g_fil_ppf.in_dat_w - 1 downto 0);
type t_streams_out_arr is array(integer range <> ) of std_logic_vector(g_fil_ppf.nof_streams * g_fil_ppf.out_dat_w - 1 downto 0);
@@ -158,11 +164,14 @@ architecture rtl of fil_ppf_wide is
-- Only the nof_bands is modified.
----------------------------------------------------------
function func_create_generics_for_ppfs(input: t_fil_ppf) return t_fil_ppf_arr is
- variable v_nof_bands : natural := input.nof_bands / input.wb_factor; -- The nof_bands for the single channel poly phase filters
- variable v_return : t_fil_ppf_arr(input.wb_factor - 1 downto 0) := (others => input); -- Variable that holds the return values
+ -- The nof_bands for the single channel poly phase filters
+ variable v_nof_bands : natural := input.nof_bands / input.wb_factor;
+ -- Variable that holds the return values
+ variable v_return : t_fil_ppf_arr(input.wb_factor - 1 downto 0) := (others => input);
begin
for P in 0 to input.wb_factor - 1 loop
- v_return(P).nof_bands := v_nof_bands; -- The new number of bands
+ -- The new number of bands
+ v_return(P).nof_bands := v_nof_bands;
end loop;
return v_return;
end;
@@ -172,7 +181,8 @@ architecture rtl of fil_ppf_wide is
-- "wb_factor" new file index arrays.
----------------------------------------------------------
function func_create_file_index_array(input: t_nat_natural_arr; wb_factor: natural; nof_taps: natural) return t_nat_natural_arr2 is
- variable v_return : t_nat_natural_arr2(wb_factor - 1 downto 0); -- Variable that holds the return values
+ -- Variable that holds the return values
+ variable v_return : t_nat_natural_arr2(wb_factor - 1 downto 0);
begin
for P in 0 to wb_factor - 1 loop
for T in 0 to nof_taps - 1 loop
@@ -216,9 +226,11 @@ begin
begin
for P in 0 to g_fil_ppf.wb_factor - 1 loop
if g_big_endian_wb_in = true then
- vP := g_fil_ppf.wb_factor - 1 - P; -- convert input big endian time [0,1,2,3] to P [3,2,1,0] index mapping to internal little endian
+ -- convert input big endian time [0,1,2,3] to P [3,2,1,0] index mapping to internal little endian
+ vP := g_fil_ppf.wb_factor - 1 - P;
else
- vP := P; -- keep input little endian time [0,1,2,3] to P [0,1,2,3] index mapping
+ -- keep input little endian time [0,1,2,3] to P [0,1,2,3] index mapping
+ vP := P;
end if;
for S in 0 to g_fil_ppf.nof_streams - 1 loop
streams_in_arr(vP)((S + 1) * g_fil_ppf.in_dat_w - 1 downto S * g_fil_ppf.in_dat_w) <= in_dat_arr(P * g_fil_ppf.nof_streams + S)(g_fil_ppf.in_dat_w - 1 downto 0);
@@ -235,7 +247,8 @@ begin
g_fil_ppf => c_fil_ppf_arr(P),
g_fil_ppf_pipeline => g_fil_ppf_pipeline,
g_round_even => g_round_even,
- g_file_index_arr => c_file_index_arr2(P), -- use (g_fil_ppf.wb_factor-1 - P) to try impact of reversed WB FIR coefficients
+ -- use (g_fil_ppf.wb_factor-1 - P) to try impact of reversed WB FIR coefficients
+ g_file_index_arr => c_file_index_arr2(P),
g_coefs_file_prefix => g_coefs_file_prefix
)
port map (
@@ -257,9 +270,11 @@ begin
begin
for P in 0 to g_fil_ppf.wb_factor - 1 loop
if g_big_endian_wb_out = true then
- vP := g_fil_ppf.wb_factor - 1 - P; -- convert internal little endian to output big endian time [0,1,2,3] to P [3,2,1,0] index mapping
+ -- convert internal little endian to output big endian time [0,1,2,3] to P [3,2,1,0] index mapping
+ vP := g_fil_ppf.wb_factor - 1 - P;
else
- vP := P; -- keep internal little endian for output little endian time [0,1,2,3] to P [0,1,2,3] index mapping
+ -- keep internal little endian for output little endian time [0,1,2,3] to P [0,1,2,3] index mapping
+ vP := P;
end if;
for S in 0 to g_fil_ppf.nof_streams - 1 loop
out_dat_arr(vP * g_fil_ppf.nof_streams + S) <= RESIZE_SVEC_32(streams_out_arr(P)((S + 1) * g_fil_ppf.out_dat_w - 1 downto S * g_fil_ppf.out_dat_w));
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
index a46728b9cf67359b74bdee7e2b11c1828fe0054b..27b7c1ad053f5047f437bf9e4de95fc9c0db229b 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
@@ -180,29 +180,37 @@ architecture tb of tb_fil_ppf_single is
constant c_clk_period : time := 10 ns;
constant c_nof_channels : natural := 2**g_fil_ppf.nof_chan;
- constant c_nof_coefs : natural := g_fil_ppf.nof_taps * g_fil_ppf.nof_bands; -- nof PFIR coef
- constant c_nof_data_in_filter : natural := c_nof_coefs * c_nof_channels; -- nof PFIR coef expanded for all channels
+ -- nof PFIR coef
+ constant c_nof_coefs : natural := g_fil_ppf.nof_taps * g_fil_ppf.nof_bands;
+ -- nof PFIR coef expanded for all channels
+ constant c_nof_data_in_filter : natural := c_nof_coefs * c_nof_channels;
constant c_nof_data_per_tap : natural := g_fil_ppf.nof_bands * c_nof_channels;
constant c_nof_bands_per_mif : natural := g_fil_ppf.nof_bands;
constant c_nof_mif_files : natural := g_fil_ppf.nof_taps;
constant c_mif_coef_mem_addr_w : natural := ceil_log2(g_fil_ppf.nof_bands);
- constant c_mif_coef_mem_span : natural := 2**c_mif_coef_mem_addr_w; -- mif coef mem span for one tap
+ -- mif coef mem span for one tap
+ constant c_mif_coef_mem_span : natural := 2**c_mif_coef_mem_addr_w;
constant c_coefs_file_prefix : string := g_coefs_file_prefix & "_" & integer'image(g_fil_ppf.nof_taps) & "taps" &
"_" & integer'image(g_fil_ppf.nof_bands) & "points" &
"_" & integer'image(g_fil_ppf.coef_dat_w) & "b";
constant c_mif_file_prefix : string := c_coefs_file_prefix & "_" & "1wb";
constant c_mif_file_index_arr : t_nat_natural_arr := array_init(0, c_nof_mif_files, 1);
- constant c_fil_prod_w : natural := g_fil_ppf.in_dat_w + g_fil_ppf.coef_dat_w - 1; -- skip double sign bit
- constant c_fil_sum_w : natural := c_fil_prod_w; -- DC gain = 1
- constant c_fil_lsb_w : natural := c_fil_sum_w - g_fil_ppf.out_dat_w; -- nof LSbits that get rounded for out_dat
- constant c_in_ampl : natural := 2**c_fil_lsb_w; -- scale in_dat to compensate for rounding
+ -- skip double sign bit
+ constant c_fil_prod_w : natural := g_fil_ppf.in_dat_w + g_fil_ppf.coef_dat_w - 1;
+ -- DC gain = 1
+ constant c_fil_sum_w : natural := c_fil_prod_w;
+ -- nof LSbits that get rounded for out_dat
+ constant c_fil_lsb_w : natural := c_fil_sum_w - g_fil_ppf.out_dat_w;
+ -- scale in_dat to compensate for rounding
+ constant c_in_ampl : natural := 2**c_fil_lsb_w;
constant c_gap_factor : natural := sel_a_b(g_enable_in_val_gaps, 3, 1);
-- input/output data width
constant c_in_dat_w : natural := g_fil_ppf.in_dat_w;
- constant c_out_dat_w : natural := g_fil_ppf.out_dat_w; -- must be >= coef_dat_w to be able to show the coeff in out_dat
+ -- must be >= coef_dat_w to be able to show the coeff in out_dat
+ constant c_out_dat_w : natural := g_fil_ppf.out_dat_w;
-- signal definitions
signal tb_end : std_logic := '0';
@@ -210,7 +218,8 @@ architecture tb of tb_fil_ppf_single is
signal tb_end_almost : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic := '0';
- signal random : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(15 downto 0) := (others => '0');
signal ram_coefs_mosi : t_mem_mosi := c_mem_mosi_rst;
signal ram_coefs_miso : t_mem_miso;
@@ -224,14 +233,19 @@ architecture tb of tb_fil_ppf_single is
signal out_val : std_logic;
signal out_val_cnt : natural := 0;
- signal mif_coefs_arr : t_integer_arr(g_fil_ppf.nof_bands - 1 downto 0) := (others => 0); -- = PFIR coef for 1 tap as read from 1 MIF file
- signal mif_dat_arr : t_integer_arr(c_nof_data_in_filter - 1 downto 0) := (others => 0); -- = PFIR coef for all taps as read from all MIF files and expanded for all channels
+ -- = PFIR coef for 1 tap as read from 1 MIF file
+ signal mif_coefs_arr : t_integer_arr(g_fil_ppf.nof_bands - 1 downto 0) := (others => 0);
+ -- = PFIR coef for all taps as read from all MIF files and expanded for all channels
+ signal mif_dat_arr : t_integer_arr(c_nof_data_in_filter - 1 downto 0) := (others => 0);
- signal ref_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef for all taps as read from the coefs file
- signal ref_dat_arr : t_integer_arr(c_nof_data_in_filter - 1 downto 0) := (others => 0); -- = PFIR coef for all taps as read from the coefs file expanded for all channels
+ -- = PFIR coef for all taps as read from the coefs file
+ signal ref_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0);
+ -- = PFIR coef for all taps as read from the coefs file expanded for all channels
+ signal ref_dat_arr : t_integer_arr(c_nof_data_in_filter - 1 downto 0) := (others => 0);
signal ref_dat : integer := 0;
- signal read_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef for all taps as read via MM from the coefs memories
+ -- = PFIR coef for all taps as read via MM from the coefs memories
+ signal read_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0);
begin
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
@@ -246,8 +260,10 @@ begin
tb_end <= '0';
in_dat <= (others => '0');
in_val <= '0';
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
+ -- Wait until reset has finished
+ proc_common_wait_until_low(clk, rst);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(clk, 10);
-- Pulse during first tap of all channels
for I in 0 to c_nof_data_per_tap - 1 loop
@@ -277,8 +293,10 @@ begin
in_val <= '0';
-- Wait until done
- proc_common_wait_some_cycles(clk, c_gap_factor * c_nof_data_per_tap); -- PPF latency of 1 tap
- proc_common_wait_until_high(clk, tb_end_mm); -- MM read done
+ -- PPF latency of 1 tap
+ proc_common_wait_some_cycles(clk, c_gap_factor * c_nof_data_per_tap);
+ -- MM read done
+ proc_common_wait_until_high(clk, tb_end_mm);
tb_end_almost <= '1';
proc_common_wait_some_cycles(clk, 10);
tb_end <= '1';
@@ -418,9 +436,11 @@ begin
if out_val = '1' then
if g_fil_ppf.out_dat_w >= g_fil_ppf.coef_dat_w then
if g_fil_ppf.out_dat_w > g_fil_ppf.coef_dat_w then
- v_coeff := ref_dat; -- positive input pulse
+ -- positive input pulse
+ v_coeff := ref_dat;
else
- v_coeff := -ref_dat; -- compensate for full scale negative input pulse
+ -- compensate for full scale negative input pulse
+ v_coeff := -ref_dat;
end if;
for S in 0 to g_fil_ppf.nof_streams - 1 loop
-- all streams carry the same data
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd
index 0e166466f4fb589b36c1da95435862a0d78883c3..82cd50444e74f3285a52cf80fb52ad614555d7ab 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd
@@ -86,25 +86,32 @@ architecture tb of tb_fil_ppf_wide is
constant c_clk_period : time := 10 ns;
constant c_nof_channels : natural := 2**g_fil_ppf.nof_chan;
- constant c_nof_coefs : natural := g_fil_ppf.nof_taps * g_fil_ppf.nof_bands; -- nof PFIR coef
+ -- nof PFIR coef
+ constant c_nof_coefs : natural := g_fil_ppf.nof_taps * g_fil_ppf.nof_bands;
constant c_nof_coefs_per_wb : natural := c_nof_coefs / g_fil_ppf.wb_factor;
- constant c_nof_data_in_filter : natural := c_nof_coefs * c_nof_channels; -- nof PFIR coef expanded for all channels
+ -- nof PFIR coef expanded for all channels
+ constant c_nof_data_in_filter : natural := c_nof_coefs * c_nof_channels;
constant c_nof_data_per_tap : natural := c_nof_data_in_filter / g_fil_ppf.nof_taps;
constant c_nof_valid_in_filter : natural := c_nof_data_in_filter / g_fil_ppf.wb_factor;
constant c_nof_valid_per_tap : natural := c_nof_data_per_tap / g_fil_ppf.wb_factor;
constant c_nof_bands_per_mif : natural := g_fil_ppf.nof_bands / g_fil_ppf.wb_factor;
constant c_mif_coef_mem_addr_w : natural := ceil_log2(g_fil_ppf.nof_bands);
- constant c_mif_coef_mem_span : natural := 2**c_mif_coef_mem_addr_w; -- mif coef mem span for one tap
+ -- mif coef mem span for one tap
+ constant c_mif_coef_mem_span : natural := 2**c_mif_coef_mem_addr_w;
constant c_coefs_file_prefix : string := g_coefs_file_prefix & "_" & integer'image(g_fil_ppf.nof_taps) & "taps" &
"_" & integer'image(g_fil_ppf.nof_bands) & "points" &
"_" & integer'image(g_fil_ppf.coef_dat_w) & "b";
constant c_mif_file_prefix : string := c_coefs_file_prefix & "_" & integer'image(g_fil_ppf.wb_factor) & "wb";
- constant c_fil_prod_w : natural := g_fil_ppf.in_dat_w + g_fil_ppf.coef_dat_w - 1; -- skip double sign bit
- constant c_fil_sum_w : natural := c_fil_prod_w; -- DC gain = 1
- constant c_fil_lsb_w : natural := c_fil_sum_w - g_fil_ppf.out_dat_w; -- nof LSbits that get rounded for out_dat
- constant c_in_ampl : natural := 2**c_fil_lsb_w; -- scale in_dat to compensate for rounding
+ -- skip double sign bit
+ constant c_fil_prod_w : natural := g_fil_ppf.in_dat_w + g_fil_ppf.coef_dat_w - 1;
+ -- DC gain = 1
+ constant c_fil_sum_w : natural := c_fil_prod_w;
+ -- nof LSbits that get rounded for out_dat
+ constant c_fil_lsb_w : natural := c_fil_sum_w - g_fil_ppf.out_dat_w;
+ -- scale in_dat to compensate for rounding
+ constant c_in_ampl : natural := 2**c_fil_lsb_w;
constant c_gap_factor : natural := sel_a_b(g_enable_in_val_gaps, 3, 1);
@@ -120,28 +127,36 @@ architecture tb of tb_fil_ppf_wide is
signal tb_end_almost : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic := '0';
- signal random : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(15 downto 0) := (others => '0');
signal ram_coefs_mosi : t_mem_mosi := c_mem_mosi_rst;
signal ram_coefs_miso : t_mem_miso;
- signal in_dat_arr : t_fil_slv_arr(g_fil_ppf.wb_factor * g_fil_ppf.nof_streams - 1 downto 0); -- = t_slv_32_arr fits g_fil_ppf.in_dat_w <= 32
+ -- = t_slv_32_arr fits g_fil_ppf.in_dat_w <= 32
+ signal in_dat_arr : t_fil_slv_arr(g_fil_ppf.wb_factor * g_fil_ppf.nof_streams - 1 downto 0);
signal in_val : std_logic;
signal in_val_cnt : natural := 0;
signal in_gap : std_logic := '0';
- signal out_dat_arr : t_fil_slv_arr(g_fil_ppf.wb_factor * g_fil_ppf.nof_streams - 1 downto 0); -- = t_slv_32_arr fits g_fil_ppf.out_dat_w <= 32
+ -- = t_slv_32_arr fits g_fil_ppf.out_dat_w <= 32
+ signal out_dat_arr : t_fil_slv_arr(g_fil_ppf.wb_factor * g_fil_ppf.nof_streams - 1 downto 0);
signal out_val : std_logic;
signal out_val_cnt : natural := 0;
- signal mif_coefs_arr : t_integer_arr(c_nof_bands_per_mif - 1 downto 0) := (others => 0); -- = PFIR coef for 1 wb, 1 tap as read from 1 MIF file
- signal mif_dat_arr2 : t_wb_integer_arr2(0 to g_fil_ppf.wb_factor - 1) := (others => (others => 0)); -- = PFIR coef for all taps as read from all MIF files and expanded for all channels
+ -- = PFIR coef for 1 wb, 1 tap as read from 1 MIF file
+ signal mif_coefs_arr : t_integer_arr(c_nof_bands_per_mif - 1 downto 0) := (others => 0);
+ -- = PFIR coef for all taps as read from all MIF files and expanded for all channels
+ signal mif_dat_arr2 : t_wb_integer_arr2(0 to g_fil_ppf.wb_factor - 1) := (others => (others => 0));
- signal ref_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef for all taps as read from the coefs file
- signal ref_dat_arr2 : t_wb_integer_arr2(0 to g_fil_ppf.wb_factor - 1) := (others => (others => 0)); -- = PFIR coef for all taps as read from the coefs file expanded for all channels
+ -- = PFIR coef for all taps as read from the coefs file
+ signal ref_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0);
+ -- = PFIR coef for all taps as read from the coefs file expanded for all channels
+ signal ref_dat_arr2 : t_wb_integer_arr2(0 to g_fil_ppf.wb_factor - 1) := (others => (others => 0));
signal ref_dat_arr : t_integer_arr(0 to g_fil_ppf.wb_factor - 1) := (others => 0);
- signal read_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef for all taps as read via MM from the coefs memories
+ -- = PFIR coef for all taps as read via MM from the coefs memories
+ signal read_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0);
begin
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
@@ -156,8 +171,10 @@ begin
tb_end <= '0';
in_dat_arr <= (others => (others => '0'));
in_val <= '0';
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
+ -- Wait until reset has finished
+ proc_common_wait_until_low(clk, rst);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(clk, 10);
-- The impulse is high during the entire tap, so g_big_endian_wb_in has no impact on the wideband input order of index P
@@ -192,8 +209,10 @@ begin
in_val <= '0';
-- Wait until done
- proc_common_wait_some_cycles(clk, c_gap_factor * c_nof_valid_per_tap); -- PPF latency of 1 tap
- proc_common_wait_until_high(clk, tb_end_mm); -- MM read done
+ -- PPF latency of 1 tap
+ proc_common_wait_some_cycles(clk, c_gap_factor * c_nof_valid_per_tap);
+ -- MM read done
+ proc_common_wait_until_high(clk, tb_end_mm);
tb_end_almost <= '1';
proc_common_wait_some_cycles(clk, 10);
tb_end <= '1';
@@ -255,7 +274,8 @@ begin
for J in 0 to g_fil_ppf.nof_taps - 1 loop
v_mif_index := P * g_fil_ppf.nof_taps + J;
v_mif_base := v_mif_index * c_mif_coef_mem_span;
- v_coef_offset := g_fil_ppf.nof_bands * (J + 1) - 1 - P; -- coeff in MIF are in flipped order, unflip this in v_coef_index
+ -- coeff in MIF are in flipped order, unflip this in v_coef_index
+ v_coef_offset := g_fil_ppf.nof_bands * (J + 1) - 1 - P;
for I in 0 to c_nof_bands_per_mif - 1 loop
proc_mem_mm_bus_rd(v_mif_base + I, clk, ram_coefs_miso, ram_coefs_mosi);
proc_mem_mm_bus_rd_latency(1, clk);
@@ -338,9 +358,11 @@ begin
-- If g_fil_ppf.out_dat_w = g_fil_ppf.coef_dat_w then full scale input is simulated as negative due to that +2**(w-1)
-- wraps to -2**(w-1), so then compensate for that here.
if g_fil_ppf.out_dat_w > g_fil_ppf.coef_dat_w then
- v_coeff := ref_dat_arr(vP); -- positive input pulse
+ -- positive input pulse
+ v_coeff := ref_dat_arr(vP);
else
- v_coeff := -ref_dat_arr(vP); -- compensate for full scale negative input pulse
+ -- compensate for full scale negative input pulse
+ v_coeff := -ref_dat_arr(vP);
end if;
for S in 0 to g_fil_ppf.nof_streams - 1 loop
-- all streams carry the same data
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
index 1e2c17cee976309b626feea49a95359b1765a953..ae10c6b160cee3b1b95c029811d839bce572dfce 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
@@ -118,10 +118,13 @@ entity tb_fil_ppf_wide_file_data is
-- coef_dat_w : natural; -- = 16, data width of the FIR coefficients
-- end record;
g_coefs_file_prefix : string := "hex/run_pfir_m_pfir_coeff_fircls1";
- g_data_file : string := "data/run_pfir_m_sinusoid_chirp_8b_16taps_128points_16b_16b.dat"; -- coefs, input and output data for 1 stream
- g_data_file_nof_lines : natural := 25600; -- number of lines with input data that is available in the g_data_file
+ -- coefs, input and output data for 1 stream
+ g_data_file : string := "data/run_pfir_m_sinusoid_chirp_8b_16taps_128points_16b_16b.dat";
+ -- number of lines with input data that is available in the g_data_file
+ g_data_file_nof_lines : natural := 25600;
- g_data_file_nof_read : natural := 5000; -- number of lines with input data to read and simulate, must be <= g_data_file_nof_lines
+ -- number of lines with input data to read and simulate, must be <= g_data_file_nof_lines
+ g_data_file_nof_read : natural := 5000;
g_enable_in_val_gaps : boolean := false
);
end entity tb_fil_ppf_wide_file_data;
@@ -130,17 +133,22 @@ architecture tb of tb_fil_ppf_wide_file_data is
constant c_clk_period : time := 10 ns;
constant c_sclk_period : time := c_clk_period / g_fil_ppf.wb_factor;
- constant c_round_even : boolean := false; -- golden reference data is for round half away from zero
- constant c_diff_margin : integer := 0; -- maximum difference between PFIR HDL output and expected output (> 0 to allow minor rounding differences)
+ -- golden reference data is for round half away from zero
+ constant c_round_even : boolean := false;
+ -- maximum difference between PFIR HDL output and expected output (> 0 to allow minor rounding differences)
+ constant c_diff_margin : integer := 0;
constant c_nof_channels : natural := 2**g_fil_ppf.nof_chan;
- constant c_nof_coefs : natural := g_fil_ppf.nof_taps * g_fil_ppf.nof_bands; -- nof PFIR coef
- constant c_nof_data_per_block : natural := g_fil_ppf.nof_bands * c_nof_channels; -- 1 block corresponds to 1 tap
+ -- nof PFIR coef
+ constant c_nof_coefs : natural := g_fil_ppf.nof_taps * g_fil_ppf.nof_bands;
+ -- 1 block corresponds to 1 tap
+ constant c_nof_data_per_block : natural := g_fil_ppf.nof_bands * c_nof_channels;
constant c_nof_valid_per_block : natural := c_nof_data_per_block / g_fil_ppf.wb_factor;
constant c_rnd_factor : natural := sel_a_b(g_enable_in_val_gaps, 3, 1);
constant c_dut_block_latency : natural := 2;
- constant c_dut_clk_latency : natural := c_nof_valid_per_block * c_dut_block_latency * c_rnd_factor; -- worst case
+ -- worst case
+ constant c_dut_clk_latency : natural := c_nof_valid_per_block * c_dut_block_latency * c_rnd_factor;
-- input/output data width
constant c_in_dat_w : natural := g_fil_ppf.in_dat_w;
@@ -166,30 +174,36 @@ architecture tb of tb_fil_ppf_wide_file_data is
signal clk : std_logic := '0';
signal sclk : std_logic := '1';
signal rst : std_logic := '0';
- signal random : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(15 downto 0) := (others => '0');
- signal coefs_dat_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef for all taps as read from via c_coefs_dat_file_prefix
- signal coefs_ref_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef for all taps as read from via g_data_file
+ -- = PFIR coef for all taps as read from via c_coefs_dat_file_prefix
+ signal coefs_dat_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0);
+ -- = PFIR coef for all taps as read from via g_data_file
+ signal coefs_ref_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0);
signal expected_data_arr : t_integer_arr(0 to g_data_file_nof_read - 1) := (others => 0);
signal input_data_arr : t_integer_arr(0 to g_data_file_nof_read - 1) := (others => 0);
signal input_data : std_logic_vector(g_fil_ppf.wb_factor * c_in_dat_w - 1 downto 0);
signal input_data_scope : integer;
- signal in_dat_arr : t_fil_slv_arr(g_fil_ppf.wb_factor * g_fil_ppf.nof_streams - 1 downto 0); -- = t_slv_32_arr fits g_fil_ppf.in_dat_w <= 32
+ -- = t_slv_32_arr fits g_fil_ppf.in_dat_w <= 32
+ signal in_dat_arr : t_fil_slv_arr(g_fil_ppf.wb_factor * g_fil_ppf.nof_streams - 1 downto 0);
signal in_val : std_logic;
signal in_val_cnt : natural := 0;
signal in_sub_val : std_logic;
signal in_sub_val_cnt : natural := 0;
signal in_gap : std_logic := '0';
- signal tsub : integer := 0; -- subband time counter
+ -- subband time counter
+ signal tsub : integer := 0;
signal exp_data : std_logic_vector(g_fil_ppf.wb_factor * c_out_dat_w - 1 downto 0);
signal exp_data_scope : integer;
signal diff_data_scope : integer;
signal output_data_scope : integer;
signal output_data : std_logic_vector(g_fil_ppf.wb_factor * c_out_dat_w - 1 downto 0);
- signal out_dat_arr : t_fil_slv_arr(g_fil_ppf.wb_factor * g_fil_ppf.nof_streams - 1 downto 0); -- = t_slv_32_arr fits g_fil_ppf.out_dat_w <= 32
+ -- = t_slv_32_arr fits g_fil_ppf.out_dat_w <= 32
+ signal out_dat_arr : t_fil_slv_arr(g_fil_ppf.wb_factor * g_fil_ppf.nof_streams - 1 downto 0);
signal out_val : std_logic;
signal out_val_cnt : natural := 0;
signal out_sub_val : std_logic;
@@ -233,19 +247,27 @@ begin
tb_end <= '0';
in_dat_arr <= (others => (others => '0'));
in_val <= '0';
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
+ -- Wait until reset has finished
+ proc_common_wait_until_low(clk, rst);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(clk, 10);
-- apply stimuli
- for I in 0 to g_data_file_nof_read / g_fil_ppf.wb_factor - 1 loop -- serial
- for K in 0 to c_nof_channels - 1 loop -- serial
- for P in 0 to g_fil_ppf.wb_factor - 1 loop -- parallel
+ -- serial
+ for I in 0 to g_data_file_nof_read / g_fil_ppf.wb_factor - 1 loop
+ -- serial
+ for K in 0 to c_nof_channels - 1 loop
+ -- parallel
+ for P in 0 to g_fil_ppf.wb_factor - 1 loop
if g_big_endian_wb_in = true then
- vP := g_fil_ppf.wb_factor - 1 - P; -- time to wideband big endian
+ -- time to wideband big endian
+ vP := g_fil_ppf.wb_factor - 1 - P;
else
- vP := P; -- time to wideband little endian
+ -- time to wideband little endian
+ vP := P;
end if;
- for S in 0 to g_fil_ppf.nof_streams - 1 loop -- parallel
+ -- parallel
+ for S in 0 to g_fil_ppf.nof_streams - 1 loop
if S = 1 then
-- if present then stream 1 carries zero data to be able to recognize the stream order in the wave window
in_dat_arr(vP * g_fil_ppf.nof_streams + S) <= (others => '0');
@@ -267,7 +289,8 @@ begin
-- Wait until done
in_val <= '0';
- proc_common_wait_some_cycles(clk, c_dut_clk_latency); -- wait for at least PPF latency of 1 tap
+ -- wait for at least PPF latency of 1 tap
+ proc_common_wait_some_cycles(clk, c_dut_clk_latency);
tb_end_almost <= '1';
proc_common_wait_some_cycles(clk, 100);
tb_end <= '1';
@@ -355,13 +378,17 @@ begin
begin
if rising_edge(clk) then
if out_val = '1' then
- for P in 0 to g_fil_ppf.wb_factor - 1 loop -- parallel
+ -- parallel
+ for P in 0 to g_fil_ppf.wb_factor - 1 loop
if g_big_endian_wb_out = true then
- vP := g_fil_ppf.wb_factor - 1 - P; -- time to wideband big endian
+ -- time to wideband big endian
+ vP := g_fil_ppf.wb_factor - 1 - P;
else
- vP := P; -- time to wideband little endian
+ -- time to wideband little endian
+ vP := P;
end if;
- for S in 0 to g_fil_ppf.nof_streams - 1 loop -- parallel
+ -- parallel
+ for S in 0 to g_fil_ppf.nof_streams - 1 loop
v_out_dat := TO_SINT(out_dat_arr(vP * g_fil_ppf.nof_streams + S));
if S = 1 then
-- stream 1 carries zero data
@@ -375,7 +402,8 @@ begin
end if;
end loop;
end loop;
- if vK < c_nof_channels - 1 then -- serial
+ -- serial
+ if vK < c_nof_channels - 1 then
vK := vK + 1;
else
vK := 0;
@@ -389,7 +417,8 @@ begin
-- DATA SCOPES
---------------------------------------------------------------
p_input_data : process(in_dat_arr)
- constant cS : natural := 0; -- tap the input_data from stream 0
+ -- tap the input_data from stream 0
+ constant cS : natural := 0;
begin
for P in 0 to g_fil_ppf.wb_factor - 1 loop
input_data((P + 1) * c_in_dat_w - 1 downto P * c_in_dat_w) <= in_dat_arr(P * g_fil_ppf.nof_streams + cS)(c_in_dat_w - 1 downto 0);
@@ -397,7 +426,8 @@ begin
end process;
p_output_data : process(out_dat_arr)
- variable cS : natural; -- tap the output_data from stream 0
+ -- tap the output_data from stream 0
+ variable cS : natural;
begin
for P in 0 to g_fil_ppf.wb_factor - 1 loop
output_data((P + 1) * c_out_dat_w - 1 downto P * c_out_dat_w) <= out_dat_arr(P * g_fil_ppf.nof_streams + cS)(c_out_dat_w - 1 downto 0);
@@ -420,13 +450,17 @@ begin
u_input_data_scope : entity common_lib.common_wideband_data_scope
generic map (
g_sim => true,
- g_wideband_factor => g_fil_ppf.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => g_big_endian_wb_in, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_in_dat_w -- Actual width of the data samples
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor => g_fil_ppf.wb_factor,
+ -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian => g_big_endian_wb_in,
+ -- Actual width of the data samples
+ g_dat_w => c_in_dat_w
)
port map (
-- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
+ -- sample clk, use only for simulation purposes
+ SCLK => sclk,
-- Streaming input data
in_data => input_data,
@@ -440,13 +474,17 @@ begin
u_exp_data_scope : entity common_lib.common_wideband_data_scope
generic map (
g_sim => true,
- g_wideband_factor => g_fil_ppf.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => g_big_endian_wb_out, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_out_dat_w -- Actual width of the data samples
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor => g_fil_ppf.wb_factor,
+ -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian => g_big_endian_wb_out,
+ -- Actual width of the data samples
+ g_dat_w => c_out_dat_w
)
port map (
-- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
+ -- sample clk, use only for simulation purposes
+ SCLK => sclk,
-- Streaming input data
in_data => exp_data,
@@ -460,13 +498,17 @@ begin
u_output_data_scope : entity common_lib.common_wideband_data_scope
generic map (
g_sim => true,
- g_wideband_factor => g_fil_ppf.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => g_big_endian_wb_out, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_out_dat_w -- Actual width of the data samples
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor => g_fil_ppf.wb_factor,
+ -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian => g_big_endian_wb_out,
+ -- Actual width of the data samples
+ g_dat_w => c_out_dat_w
)
port map (
-- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
+ -- sample clk, use only for simulation purposes
+ SCLK => sclk,
-- Streaming input data
in_data => output_data,
diff --git a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_single.vhd b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_single.vhd
index 246318460d1d8dd3c3bf94b0e8a9dc939a5554a2..8701f7383fec715865d6068043acfbe924988b85 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_single.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_single.vhd
@@ -38,7 +38,8 @@ architecture tb of tb_tb_fil_ppf_single is
constant c_fil_ppf_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
constant c_prefix : string := "hex/run_pfir_coeff_m_incrementing";
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
--g_fil_ppf_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
-- -- type t_fil_pipeline is record
diff --git a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide.vhd b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide.vhd
index fd5ce1f498b0c3cab27f2bb0839468c7f78de714..516292191167dc93f7fa64b324ff2bed7d575568 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide.vhd
@@ -38,7 +38,8 @@ architecture tb of tb_tb_fil_ppf_wide is
constant c_fil_ppf_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
constant c_prefix : string := "hex/run_pfir_coeff_m_incrementing";
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
--g_big_endian_wb_in : boolean := true;
--g_big_endian_wb_out : boolean := true;
diff --git a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
index 2aaff2311589c1c1bae5a91f6203b62b4d9abc99..7ae1a80691d09f7960e0551b58411dcf17f8aded 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
@@ -40,10 +40,13 @@ architecture tb of tb_tb_fil_ppf_wide_file_data is
constant c_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
constant c_coeff_prefix : string := "hex/run_pfir_m_pfir_coeff_fircls1";
- constant c_data : string := "data/run_pfir_m_sinusoid_chirp_8b_16taps_128points_16b_16b.dat"; -- coefs, input and output data for 1 stream
- constant c_data15 : string := "data/run_pfir_m_sinusoid_chirp_8b_15taps_128points_16b_16b.dat"; -- coefs, input and output data for 1 stream
+ -- coefs, input and output data for 1 stream
+ constant c_data : string := "data/run_pfir_m_sinusoid_chirp_8b_16taps_128points_16b_16b.dat";
+ -- coefs, input and output data for 1 stream
+ constant c_data15 : string := "data/run_pfir_m_sinusoid_chirp_8b_15taps_128points_16b_16b.dat";
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
--g_big_endian_wb_in : boolean := true;
--g_big_endian_wb_out : boolean := true;
diff --git a/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
index 65f193f20a9016327936b9688527f53dba485f16..6f3e845734e006bd0413c49cabb0a8c35d844456 100644
--- a/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
@@ -37,13 +37,20 @@ use dp_lib.dp_stream_pkg.all;
entity fringe_stop_unit is
generic (
g_technology : natural := c_tech_select_default;
- g_in_dat_w : positive := 8; -- Width of the incoming data
- g_fs_offset_w : positive := 10; -- Width of the offset of the linear coefficient
- g_fs_step_w : positive := 17; -- Width of the step of the linear coefficient
- g_accu_w : positive := 31; -- Width of the accumulation register
- g_phi_minus_sign : boolean := true; -- Apply exp(j*phi) or exp(-j*phi) based on phasor lookup table address phi
- g_phasor_w : positive := 9; -- Width of the phasor values in the lookup table
- g_nof_channels : positive := 256 -- Number of serial channels for which the fringe stopping must be applied uniquely
+ -- Width of the incoming data
+ g_in_dat_w : positive := 8;
+ -- Width of the offset of the linear coefficient
+ g_fs_offset_w : positive := 10;
+ -- Width of the step of the linear coefficient
+ g_fs_step_w : positive := 17;
+ -- Width of the accumulation register
+ g_accu_w : positive := 31;
+ -- Apply exp(j*phi) or exp(-j*phi) based on phasor lookup table address phi
+ g_phi_minus_sign : boolean := true;
+ -- Width of the phasor values in the lookup table
+ g_phasor_w : positive := 9;
+ -- Number of serial channels for which the fringe stopping must be applied uniquely
+ g_nof_channels : positive := 256
);
port (
-- System
@@ -75,7 +82,8 @@ architecture str of fringe_stop_unit is
constant c_fs_ram_w : positive := ceil_log2(g_nof_channels);
- constant c_input_latency : natural := 2; -- It is 2 because we use the in_sosi.sync to swap the page of dual page memory.
+ -- It is 2 because we use the in_sosi.sync to swap the page of dual page memory.
+ constant c_input_latency : natural := 2;
constant c_step_adder_stage_latency : natural := 1;
constant c_sum_adder_stage_latency : natural := 1;
constant c_look_up_latency : natural := 0;
@@ -83,7 +91,8 @@ architecture str of fringe_stop_unit is
constant c_total_latency : natural := c_input_latency + c_step_adder_stage_latency + c_sum_adder_stage_latency +
c_look_up_latency + c_cmult_latency;
- constant c_product_w : positive := g_in_dat_w + g_phasor_w; -- no need for + c_sum_of_prod_w, because phasor amplitude is 1
+ -- no need for + c_sum_of_prod_w, because phasor amplitude is 1
+ constant c_product_w : positive := g_in_dat_w + g_phasor_w;
type reg_type is record
in_sosi_arr : t_dp_sosi_arr(c_total_latency - 1 downto 0);
@@ -145,10 +154,14 @@ begin
v.page_turn_arr(0) := page_turn;
v.page_turn_arr(c_total_latency - 1 downto 1) := r.page_turn_arr(c_total_latency - 2 downto 0);
- v.fs_step_accu_valid := fs_step_data_valid; -- Valid signals only used as reference in simulation
- v.fs_sum_valid := r.fs_step_accu_valid; -- Valid signals only used as reference in simulation
- v.fs_offset_data_valid := fs_offset_data_valid; -- Valid signals only used as reference in simulation
- v.fs_index_valid := r.in_sosi_arr(5).valid; -- Valid signals only used as reference in simulation
+ -- Valid signals only used as reference in simulation
+ v.fs_step_accu_valid := fs_step_data_valid;
+ -- Valid signals only used as reference in simulation
+ v.fs_sum_valid := r.fs_step_accu_valid;
+ -- Valid signals only used as reference in simulation
+ v.fs_offset_data_valid := fs_offset_data_valid;
+ -- Valid signals only used as reference in simulation
+ v.fs_index_valid := r.in_sosi_arr(5).valid;
-- Create the flush_accu register for flushing the accumulation register.
-- Only flush accu at page_turn, to keep on stepping if there is no MM control
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
index d2225c2df6b4b7af24e4316dfaabc98dc952020b..60a27b74680ae080845d53e96b9f620dd709a8b6 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
@@ -43,14 +43,22 @@ use diag_lib.diag_pkg.all;
entity tb_fringe_stop_unit is
generic(
- g_sim_type : natural := 2; -- 0 = Increment, 1 = Increment over the maximum, 2 = Decrease, 3 = Decrease over the minimum
- g_in_dat_w : positive := 8; -- Width of the incoming data.
- g_fs_offset_w : positive := 10; -- Width of the offset of the linear coefficient
- g_accu_w : positive := 31; -- Width of the accumulation register
- g_fs_step_w : positive := 17; -- Width of the step of the linear coefficient
- g_nof_channels : positive := 4; -- Number of serial channels for which the fringe stopping must be applied uniquely
- g_phasor_w : positive := 9; -- Width of the phasor values in the lookup table
- g_phi_minus_sign : boolean := true -- Apply exp(j*phi) or exp(-j*phi) based on phasor lookup table address phi
+ -- 0 = Increment, 1 = Increment over the maximum, 2 = Decrease, 3 = Decrease over the minimum
+ g_sim_type : natural := 2;
+ -- Width of the incoming data.
+ g_in_dat_w : positive := 8;
+ -- Width of the offset of the linear coefficient
+ g_fs_offset_w : positive := 10;
+ -- Width of the accumulation register
+ g_accu_w : positive := 31;
+ -- Width of the step of the linear coefficient
+ g_fs_step_w : positive := 17;
+ -- Number of serial channels for which the fringe stopping must be applied uniquely
+ g_nof_channels : positive := 4;
+ -- Width of the phasor values in the lookup table
+ g_phasor_w : positive := 9;
+ -- Apply exp(j*phi) or exp(-j*phi) based on phasor lookup table address phi
+ g_phi_minus_sign : boolean := true
);
end tb_fringe_stop_unit;
@@ -95,7 +103,8 @@ architecture tb of tb_fringe_stop_unit is
constant c_bg_nof_output_streams : positive := 1;
constant c_bg_buf_dat_w : positive := c_nof_complex * g_in_dat_w;
constant c_bg_buf_adr_w : positive := ceil_log2(g_nof_channels);
- constant c_bg_data_file_prefix : string := "UNUSED"; -- "/tb_bg_dat";
+ -- "/tb_bg_dat";
+ constant c_bg_data_file_prefix : string := "UNUSED";
constant c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, c_bg_nof_output_streams, 1);
constant c_block_size : natural := g_nof_channels;
@@ -103,8 +112,10 @@ architecture tb of tb_fringe_stop_unit is
constant c_bg_nof_blocks_per_sync : natural := 128;
constant c_bg_mem_high_addr : natural := g_nof_channels - 1;
- constant c_bg_ctrl : t_diag_block_gen := ( '0', -- enable: On by default in simulation; MM enable required on hardware.
- '0', -- enable_sync
+ -- enable: On by default in simulation; MM enable required on hardware.
+ constant c_bg_ctrl : t_diag_block_gen := ( '0',
+ -- enable_sync
+ '0',
TO_UVEC( c_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
@@ -117,7 +128,8 @@ architecture tb of tb_fringe_stop_unit is
signal out_sosi_arr : t_dp_sosi_arr(1 - 1 downto 0) := (others => c_dp_sosi_rst);
- constant c_lookup_len : positive := 2**g_fs_offset_w; -- corresponds to 2*pi
+ -- corresponds to 2*pi
+ constant c_lookup_len : positive := 2**g_fs_offset_w;
constant c_lookup_real : t_nat_integer_arr := common_math_create_look_up_table_cos(c_lookup_len, g_phasor_w, false);
constant c_lookup_imag : t_nat_integer_arr := common_math_create_look_up_table_sin(c_lookup_len, g_phasor_w, g_phi_minus_sign);
constant c_nof_sync_periods : positive := 8;
@@ -246,8 +258,10 @@ begin
end loop;
-- wait until the next sync interval
proc_common_wait_some_pulses(dp_clk, bg_sosi_arr(0).sync, 1);
- proc_common_wait_some_cycles(dp_clk, 20); -- account for clock domain crossing latency
- proc_common_wait_some_cycles(mm_clk, 20); -- account for clock domain crossing latency
+ -- account for clock domain crossing latency
+ proc_common_wait_some_cycles(dp_clk, 20);
+ -- account for clock domain crossing latency
+ proc_common_wait_some_cycles(mm_clk, 20);
end loop;
end loop;
proc_common_wait_some_cycles(mm_clk, 80);
@@ -270,8 +284,10 @@ begin
end loop;
-- wait until the next sync interval
proc_common_wait_some_pulses(dp_clk, bg_sosi_arr(0).sync, 1);
- proc_common_wait_some_cycles(dp_clk, 20); -- account for clock domain crossing latency
- proc_common_wait_some_cycles(mm_clk, 20); -- account for clock domain crossing latency
+ -- account for clock domain crossing latency
+ proc_common_wait_some_cycles(dp_clk, 20);
+ -- account for clock domain crossing latency
+ proc_common_wait_some_cycles(mm_clk, 20);
end loop;
end loop;
proc_common_wait_some_cycles(mm_clk, 80);
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
index 7fd9d4c2a183e94c5b67c3f526cecf016b5455cf..015f9c64bf59d78f229329c29a0878f7dc7a5a74 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
@@ -70,10 +70,12 @@ use dp_lib.dp_stream_pkg.all;
entity tb_mmf_fringe_stop_unit is
generic(
- g_tb_index : natural := 0; -- use different index to avoid MM file conflict in multi tb
+ -- use different index to avoid MM file conflict in multi tb
+ g_tb_index : natural := 0;
g_mm_stimuli_enable : boolean := true;
--g_mm_stimuli_enable : BOOLEAN := FALSE; -- use TRUE to activate p_mm_stimuli, else FALSE to apply mm_file IO via Python
- g_mm_clk_faster_than_dp_clk : boolean := true; -- when TRUE than mm_clk > dp_clk.
+ -- when TRUE than mm_clk > dp_clk.
+ g_mm_clk_faster_than_dp_clk : boolean := true;
g_in_valid_gapsize : natural := 0
);
end tb_mmf_fringe_stop_unit;
@@ -83,20 +85,29 @@ architecture tb of tb_mmf_fringe_stop_unit is
-- Clocks and resets
----------------------------------------------------------------------------
constant c_dp_clk_period : time := 5 ns;
- constant c_mm_clk_period : time := sel_a_b(g_mm_clk_faster_than_dp_clk, 1 ns, 10 ns); -- 100 ps makes simulation slow
+ -- 100 ps makes simulation slow
+ constant c_mm_clk_period : time := sel_a_b(g_mm_clk_faster_than_dp_clk, 1 ns, 10 ns);
-- Fringe stop settings
- constant c_in_dat_w : positive := 8; -- Width of the incoming data.
- constant c_fs_offset_w : positive := 10; -- Width of the offset of the linear coefficient
- constant c_fs_step_w : positive := 17; -- Width of the step of the linear coefficient
- constant c_accu_w : positive := 31; -- Width of the accumulation register
- constant c_phi_minus_sign : boolean := true; -- Apply exp(j*phi) or exp(-j*phi) based on phasor lookup table address phi
+ -- Width of the incoming data.
+ constant c_in_dat_w : positive := 8;
+ -- Width of the offset of the linear coefficient
+ constant c_fs_offset_w : positive := 10;
+ -- Width of the step of the linear coefficient
+ constant c_fs_step_w : positive := 17;
+ -- Width of the accumulation register
+ constant c_accu_w : positive := 31;
+ -- Apply exp(j*phi) or exp(-j*phi) based on phasor lookup table address phi
+ constant c_phi_minus_sign : boolean := true;
--CONSTANT c_phi_minus_sign : BOOLEAN := FALSE;
- constant c_phasor_w : positive := 9; -- Width of the phasor values in the lookup table
- constant c_nof_channels : positive := 4; -- Number of serial channels for which the fringe stopping must be applied uniquely
+ -- Width of the phasor values in the lookup table
+ constant c_phasor_w : positive := 9;
+ -- Number of serial channels for which the fringe stopping must be applied uniquely
+ constant c_nof_channels : positive := 4;
constant c_nof_pages : natural := 2;
- constant c_in_offset : natural := 0; -- range 0:1023 = 0:2**c_fs_offset_w-1
+ -- range 0:1023 = 0:2**c_fs_offset_w-1
+ constant c_in_offset : natural := 0;
--CONSTANT c_in_step : INTEGER := 65431; -- range -65536:65535 = -2**(c_fs_step-1):+2**(c_fs_step-1)-1
constant c_in_step : integer := 2**15;
constant c_in_step2 : integer := 17;
@@ -114,8 +125,10 @@ architecture tb of tb_mmf_fringe_stop_unit is
-- MM
constant c_unb_nr : natural := 0;
- constant c_node_nr : natural := 0; -- choose node 0 is FN 0
- constant c_cross_clock_domain_delay : natural := 50; -- apply in both dp_clk and mm_clk domain, to be independent of which one is fastest
+ -- choose node 0 is FN 0
+ constant c_node_nr : natural := 0;
+ -- apply in both dp_clk and mm_clk domain, to be independent of which one is fastest
+ constant c_cross_clock_domain_delay : natural := 50;
constant c_mm_file_ram_fringe_stop_offset : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_FRINGE_STOP_OFFSET_" & int_to_str(g_tb_index);
constant c_mm_file_ram_fringe_stop_step : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_FRINGE_STOP_STEP_" & int_to_str(g_tb_index);
@@ -172,7 +185,8 @@ begin
proc_common_gen_duty_pulse(0, 1, c_in_sync_interval, '1', dp_rst, dp_clk, in_enable, in_sosi.sync);
proc_common_gen_duty_pulse(0, c_in_block_size, c_in_block_interval, '1', dp_rst, dp_clk, in_enable, in_sosi.valid);
proc_common_gen_duty_pulse(0, 1, c_in_block_interval, '1', dp_rst, dp_clk, in_enable, in_sosi.sop);
- proc_common_gen_duty_pulse(c_in_block_size-1, 1, c_in_block_interval, '1', dp_rst, dp_clk, in_enable, in_sosi.eop); -- DUT uses eop
+ -- DUT uses eop
+ proc_common_gen_duty_pulse(c_in_block_size-1, 1, c_in_block_interval, '1', dp_rst, dp_clk, in_enable, in_sosi.eop);
-- bsn
in_sosi.bsn <= INCR_UVEC(in_sosi.bsn, 1) when rising_edge(dp_clk) and in_sosi.eop = '1';
@@ -257,12 +271,16 @@ begin
-------------------------------------------------------------------------
-- Wait for at least one fringe stop phase period
v_data := out_re;
- proc_common_wait_until_value(v_data + 1, dp_clk, out_re); -- wait until out_re+1, initial (out_re, out_im) = (-c_in_amplitude, 0)
+ -- wait until out_re+1, initial (out_re, out_im) = (-c_in_amplitude, 0)
+ proc_common_wait_until_value(v_data + 1, dp_clk, out_re);
report "Phasor start " & integer'image(g_tb_index) severity NOTE;
tb_state <= "Phasor start ";
- proc_common_wait_until_evt(dp_clk, out_re); -- wait until out_re+1 changes
- proc_common_wait_until_value(v_data, dp_clk, out_re); -- wait until out_re again
- proc_common_wait_until_value(v_data + 1, dp_clk, out_re); -- wait until out_re+1 again
+ -- wait until out_re+1 changes
+ proc_common_wait_until_evt(dp_clk, out_re);
+ -- wait until out_re again
+ proc_common_wait_until_value(v_data, dp_clk, out_re);
+ -- wait until out_re+1 again
+ proc_common_wait_until_value(v_data + 1, dp_clk, out_re);
report "Phasor end " & integer'image(g_tb_index) severity NOTE;
tb_state <= "Phasor end ";
@@ -365,14 +383,20 @@ begin
-- Measure
verify_sum_en <= '0';
-- Initial (out_re, out_im) = (-c_in_amplitude, 0)
- proc_common_wait_until_value(-c_in_amplitude, dp_clk, out_re); -- wait until out_re=-c_in_amplitude
- proc_common_wait_until_value(-c_in_amplitude+1, dp_clk, out_re); -- wait until out_re=-c_in_amplitude+1
- proc_common_wait_until_evt(dp_clk, out_re); -- wait until out_re changes
+ -- wait until out_re=-c_in_amplitude
+ proc_common_wait_until_value(-c_in_amplitude, dp_clk, out_re);
+ -- wait until out_re=-c_in_amplitude+1
+ proc_common_wait_until_value(-c_in_amplitude+1, dp_clk, out_re);
+ -- wait until out_re changes
+ proc_common_wait_until_evt(dp_clk, out_re);
vBegin := NOW / c_dp_clk_period;
verify_sum_en <= '1';
- proc_common_wait_until_value(-c_in_amplitude, dp_clk, out_re); -- wait until out_re=-c_in_amplitude again
- proc_common_wait_until_value(-c_in_amplitude+1, dp_clk, out_re); -- wait until out_re=-c_in_amplitude+1 again
- proc_common_wait_until_evt(dp_clk, out_re); -- wait until out_re changes
+ -- wait until out_re=-c_in_amplitude again
+ proc_common_wait_until_value(-c_in_amplitude, dp_clk, out_re);
+ -- wait until out_re=-c_in_amplitude+1 again
+ proc_common_wait_until_value(-c_in_amplitude+1, dp_clk, out_re);
+ -- wait until out_re changes
+ proc_common_wait_until_evt(dp_clk, out_re);
vEnd := NOW / c_dp_clk_period;
vPeriod := vEnd - vBegin;
verify_sum_en <= '0';
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_fringe_stop_unit.vhd
index 9a49efb0b76468711202bece508568c89eb56185..a9f5979d6c815b153dae617d94f4527cb167a0a2 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_fringe_stop_unit.vhd
@@ -35,7 +35,8 @@ entity tb_tb_fringe_stop_unit is
end tb_tb_fringe_stop_unit;
architecture tb of tb_tb_fringe_stop_unit is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Usage
-- > as 8
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_mmf_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_mmf_fringe_stop_unit.vhd
index 776e1d86b76b3a5b9e0a8d3fd5d57ec2c7de74e5..ae70c5e8c4af7c4dd67bc4c2774b1ed846f36705 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_mmf_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_mmf_fringe_stop_unit.vhd
@@ -32,13 +32,16 @@ entity tb_tb_mmf_fringe_stop_unit is
end tb_tb_mmf_fringe_stop_unit;
architecture tb of tb_tb_mmf_fringe_stop_unit is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_tb_index : NATURAL := 0; -- use different index to avoid MM file conflict in multi tb
-- g_mm_stimuli_enable : BOOLEAN := FALSE; -- use TRUE to activate p_mm_stimuli, else FALSE to apply mm_file IO via Python
-- g_mm_clk_faster_than_dp_clk : BOOLEAN := TRUE; -- when TRUE than mm_clk > dp_clk.
-- g_in_valid_gapsize : NATURAL := 0
- u_mm_slower_no_gap : entity work.tb_mmf_fringe_stop_unit generic map (0, true, false, 0); -- use no gap to enable verification of phasor period
- u_mm_faster_with_gap : entity work.tb_mmf_fringe_stop_unit generic map (1, true, true, 1); -- use gap to verify valid gaps
+ -- use no gap to enable verification of phasor period
+ u_mm_slower_no_gap : entity work.tb_mmf_fringe_stop_unit generic map (0, true, false, 0);
+ -- use gap to verify valid gaps
+ u_mm_faster_with_gap : entity work.tb_mmf_fringe_stop_unit generic map (1, true, true, 1);
end tb;
diff --git a/libraries/dsp/iquv/src/vhdl/iquv.vhd b/libraries/dsp/iquv/src/vhdl/iquv.vhd
index e2f245afddb259829d76dd72834892261f820f74..dda6b36455d0a206b5ca48399b3df3cef4f84817 100644
--- a/libraries/dsp/iquv/src/vhdl/iquv.vhd
+++ b/libraries/dsp/iquv/src/vhdl/iquv.vhd
@@ -45,23 +45,33 @@ entity iquv is
generic (
g_sim : boolean := false;
g_technology : natural := c_tech_select_default;
- g_variant : string := "IP"; -- overide with "RTL" for sc3
+ -- overide with "RTL" for sc3
+ g_variant : string := "IP";
g_use_accum : boolean := true;
- g_nof_int : natural := 8; -- number of successive subbands to integrate
- g_in_data_w : natural := 12; -- width of the incoming complex data
- g_out_data_w : natural := 18; -- width to round the output to
- g_lsb_adj_w : natural := 0 -- number of bit to shift the output down
+ -- number of successive subbands to integrate
+ g_nof_int : natural := 8;
+ -- width of the incoming complex data
+ g_in_data_w : natural := 12;
+ -- width to round the output to
+ g_out_data_w : natural := 18;
+ -- number of bit to shift the output down
+ g_lsb_adj_w : natural := 0
);
port (
dp_rst : in std_logic;
dp_clk : in std_logic;
-- Streaming
- in_complex : in t_dp_sosi; -- Complex input data
- i_out : out t_dp_sosi; -- Complex output data I
- q_out : out t_dp_sosi; -- Complex output data Q
- u_out : out t_dp_sosi; -- Complex output data U
- v_out : out t_dp_sosi -- Complex output data V
+ -- Complex input data
+ in_complex : in t_dp_sosi;
+ -- Complex output data I
+ i_out : out t_dp_sosi;
+ -- Complex output data Q
+ q_out : out t_dp_sosi;
+ -- Complex output data U
+ u_out : out t_dp_sosi;
+ -- Complex output data V
+ v_out : out t_dp_sosi
);
end iquv;
@@ -69,7 +79,8 @@ end iquv;
architecture str of iquv is
constant c_multprod_w : natural := g_in_data_w * 2;
constant c_iquv_w : natural := c_multprod_w + 1;
- constant c_nof_int : natural := sel_a_b(g_use_accum, g_nof_int, 1); -- force nof_int to 1 if accum is not used
+ -- force nof_int to 1 if accum is not used
+ constant c_nof_int : natural := sel_a_b(g_use_accum, g_nof_int, 1);
constant c_accumcount_w : natural := true_log2(c_nof_int);
constant c_iquv_accum_w : natural := c_iquv_w + c_accumcount_w;
constant c_lsb_w : natural := c_iquv_accum_w - g_out_data_w - g_lsb_adj_w;
diff --git a/libraries/dsp/iquv/src/vhdl/iquv_accum.vhd b/libraries/dsp/iquv/src/vhdl/iquv_accum.vhd
index 3a348a2e60fbde316d64766dd299b954efff7624..4600ee6c071f83bab762c84eb17c4a1266b2e644 100644
--- a/libraries/dsp/iquv/src/vhdl/iquv_accum.vhd
+++ b/libraries/dsp/iquv/src/vhdl/iquv_accum.vhd
@@ -38,8 +38,10 @@ use dp_lib.dp_stream_pkg.all;
entity iquv_accum is
generic (
- g_accumcount_w : natural := 3; -- log2 of the number of samples to integrate
- g_in_data_w : natural := 12 -- width of the incoming data
+ -- log2 of the number of samples to integrate
+ g_accumcount_w : natural := 3;
+ -- width of the incoming data
+ g_in_data_w : natural := 12
);
port (
dp_rst : in std_logic;
diff --git a/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd b/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd
index 5c60653c136df0a522cff0cf5c6b7fc5b2c05ab8..c0cec291ef9566aef4c31c505003737b8258475b 100644
--- a/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd
+++ b/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd
@@ -45,11 +45,16 @@ entity iquv_iab is
g_sim : boolean := false;
g_technology : natural := c_tech_select_default;
g_use_accum : boolean := false;
- g_use_gain_ctrl : boolean := false; -- set TRUE to ignore accumulator bit growth and enable fine gain control
- g_nof_streams : natural := 12; -- number of imput streams
- g_nof_int : natural := 8; -- number of successive subbands to integrate
- g_in_data_w : natural := 12; -- width of the incoming complex data
- g_out_data_w : natural := 18 -- width of the final summed output
+ -- set TRUE to ignore accumulator bit growth and enable fine gain control
+ g_use_gain_ctrl : boolean := false;
+ -- number of imput streams
+ g_nof_streams : natural := 12;
+ -- number of successive subbands to integrate
+ g_nof_int : natural := 8;
+ -- width of the incoming complex data
+ g_in_data_w : natural := 12;
+ -- width of the final summed output
+ g_out_data_w : natural := 18
);
port (
dp_rst : in std_logic;
@@ -68,11 +73,16 @@ entity iquv_iab is
reg_dp_gain_v_miso : out t_mem_miso;
-- Streaming
- in_complex_arr : in t_dp_sosi_arr(0 to g_nof_streams - 1); -- Complex input data
- i_out : out t_dp_sosi; -- Output data I
- q_out : out t_dp_sosi; -- Output data Q
- u_out : out t_dp_sosi; -- Output data U
- v_out : out t_dp_sosi -- Output data V
+ -- Complex input data
+ in_complex_arr : in t_dp_sosi_arr(0 to g_nof_streams - 1);
+ -- Output data I
+ i_out : out t_dp_sosi;
+ -- Output data Q
+ q_out : out t_dp_sosi;
+ -- Output data U
+ u_out : out t_dp_sosi;
+ -- Output data V
+ v_out : out t_dp_sosi
);
end iquv_iab;
@@ -87,7 +97,8 @@ architecture str of iquv_iab is
constant c_accum_out_w : natural := sel_a_b(g_use_accum, c_adder_out_w + c_accumcount_w, c_adder_out_w);
-- bitwidths for the optional gain section
- constant c_gain_requantize_in_w : natural := c_adder_out_w; -- ignore the accumulator bitgrowth when using gain
+ -- ignore the accumulator bitgrowth when using gain
+ constant c_gain_requantize_in_w : natural := c_adder_out_w;
constant c_mm_gain_ctrl_w : natural := 16;
constant c_gain_in_w : natural := 18;
constant c_gain_out_w : natural := 18;
@@ -321,7 +332,8 @@ begin
g_gain_init_re => 1,
g_gain_w => c_mm_gain_ctrl_w,
g_in_dat_w => c_gain_in_w,
- g_out_dat_w => c_gain_out_w -- Todo: Check that the MSBs get truncated correctly
+ -- Todo: Check that the MSBs get truncated correctly
+ g_out_dat_w => c_gain_out_w
)
port map
(
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
index 51e20a0fa1ab482958301b4cd0ced1fa3fd39d5d..bf15ddbae56206b8008f9e37364d4afd8129a513 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
@@ -40,18 +40,25 @@ use technology_lib.technology_select_pkg.all;
entity tb_iquv is
generic (
- g_nof_int : natural := 16; -- number of successive subbands to integrate
- g_random_valid : boolean := true; -- Put gaps in the valid signal
- g_in_data_w : natural := 12; -- width of the incoming complex data
- g_out_data_w : natural := 18 -- width of the output data
+ -- number of successive subbands to integrate
+ g_nof_int : natural := 16;
+ -- Put gaps in the valid signal
+ g_random_valid : boolean := true;
+ -- width of the incoming complex data
+ g_in_data_w : natural := 12;
+ -- width of the output data
+ g_out_data_w : natural := 18
);
end tb_iquv;
architecture tb of tb_iquv is
constant clk_period : time := 10 ns;
- constant c_npoints : natural := 4 * g_nof_int; -- number of subbands (size of block) at present only used to generate test vectors
- constant c_fsd_w : natural := g_in_data_w * 2 + 1 + ceil_log2(g_nof_int); -- The number of bits used for the accumulated result inside the DUT
- constant c_lsb_w : natural := c_fsd_w - g_out_data_w; -- number of lsbs to remove from the expected result
+ -- number of subbands (size of block) at present only used to generate test vectors
+ constant c_npoints : natural := 4 * g_nof_int;
+ -- The number of bits used for the accumulated result inside the DUT
+ constant c_fsd_w : natural := g_in_data_w * 2 + 1 + ceil_log2(g_nof_int);
+ -- number of lsbs to remove from the expected result
+ constant c_lsb_w : natural := c_fsd_w - g_out_data_w;
signal tb_end : std_logic := '0';
signal dp_rst : std_logic := '1';
@@ -180,75 +187,113 @@ begin
wait until rising_edge(dp_clk);
for I in 0 to 19 loop wait until rising_edge(dp_clk); end loop;
- for BLOCKCOUNT in 0 to 0 loop -- Repeat as needed
+ -- Repeat as needed
+ for BLOCKCOUNT in 0 to 0 loop
- in_complex.im <= TO_DP_DSP_DATA(0); -- Keep the imaginary part 0
- for FBIN in 0 to c_npoints - 1 loop -- BLOCK cycle one
- in_complex.re <= TO_DP_DSP_DATA(FBIN); -- The real part of the X pol counts up
+ -- Keep the imaginary part 0
+ in_complex.im <= TO_DP_DSP_DATA(0);
+ -- BLOCK cycle one
+ for FBIN in 0 to c_npoints - 1 loop
+ -- The real part of the X pol counts up
+ in_complex.re <= TO_DP_DSP_DATA(FBIN);
wait until rising_edge(dp_clk) and valid_enable = '1';
- in_complex.re <= TO_DP_DSP_DATA(0); -- The real part of the Y pol stays 0
+ -- The real part of the Y pol stays 0
+ in_complex.re <= TO_DP_DSP_DATA(0);
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- for FBIN in 0 to c_npoints - 1 loop -- BLOCK cycle two
- in_complex.re <= TO_DP_DSP_DATA(0); -- The real part of the X pol stays 0
+ -- BLOCK cycle two
+ for FBIN in 0 to c_npoints - 1 loop
+ -- The real part of the X pol stays 0
+ in_complex.re <= TO_DP_DSP_DATA(0);
wait until rising_edge(dp_clk) and valid_enable = '1';
- in_complex.re <= TO_DP_DSP_DATA(FBIN); -- The real part of the Y pol counts up
+ -- The real part of the Y pol counts up
+ in_complex.re <= TO_DP_DSP_DATA(FBIN);
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- in_complex.re <= TO_DP_DSP_DATA(0); -- Keep the real part 0
- for FBIN in 0 to c_npoints - 1 loop -- BLOCK cycle three
- in_complex.im <= TO_DP_DSP_DATA(FBIN); -- The im part of the X pol counts up
+ -- Keep the real part 0
+ in_complex.re <= TO_DP_DSP_DATA(0);
+ -- BLOCK cycle three
+ for FBIN in 0 to c_npoints - 1 loop
+ -- The im part of the X pol counts up
+ in_complex.im <= TO_DP_DSP_DATA(FBIN);
wait until rising_edge(dp_clk) and valid_enable = '1';
- in_complex.im <= TO_DP_DSP_DATA(0); -- The im part of the Y pol stays 0
+ -- The im part of the Y pol stays 0
+ in_complex.im <= TO_DP_DSP_DATA(0);
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- for FBIN in 0 to c_npoints - 1 loop -- BLOCK cycle four
- in_complex.im <= TO_DP_DSP_DATA(0); -- The im part of the X pol stays 0
+ -- BLOCK cycle four
+ for FBIN in 0 to c_npoints - 1 loop
+ -- The im part of the X pol stays 0
+ in_complex.im <= TO_DP_DSP_DATA(0);
wait until rising_edge(dp_clk) and valid_enable = '1';
- in_complex.im <= TO_DP_DSP_DATA(FBIN); -- The im part of the Y pol counts up
+ -- The im part of the Y pol counts up
+ in_complex.im <= TO_DP_DSP_DATA(FBIN);
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- in_complex.im <= TO_DP_DSP_DATA(0); -- Keep the imaginary part 0
- for FBIN in 0 to c_npoints - 1 loop -- BLOCK cycle five
- in_complex.re <= TO_DP_DSP_DATA(FBIN); -- The real part of the X pol counts up
+ -- Keep the imaginary part 0
+ in_complex.im <= TO_DP_DSP_DATA(0);
+ -- BLOCK cycle five
+ for FBIN in 0 to c_npoints - 1 loop
+ -- The real part of the X pol counts up
+ in_complex.re <= TO_DP_DSP_DATA(FBIN);
wait until rising_edge(dp_clk) and valid_enable = '1';
- in_complex.re <= TO_DP_DSP_DATA(FBIN); -- The real part of the Y pol counts up
+ -- The real part of the Y pol counts up
+ in_complex.re <= TO_DP_DSP_DATA(FBIN);
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- in_complex.re <= TO_DP_DSP_DATA(0); -- Keep the real part 0
- for FBIN in 0 to c_npoints - 1 loop -- BLOCK cycle six
- in_complex.im <= TO_DP_DSP_DATA(FBIN); -- The im part of the X pol counts up
+ -- Keep the real part 0
+ in_complex.re <= TO_DP_DSP_DATA(0);
+ -- BLOCK cycle six
+ for FBIN in 0 to c_npoints - 1 loop
+ -- The im part of the X pol counts up
+ in_complex.im <= TO_DP_DSP_DATA(FBIN);
wait until rising_edge(dp_clk) and valid_enable = '1';
- in_complex.im <= TO_DP_DSP_DATA(FBIN); -- The im part of the Y pol counts up
+ -- The im part of the Y pol counts up
+ in_complex.im <= TO_DP_DSP_DATA(FBIN);
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- for FBIN in 0 to c_npoints - 1 loop -- BLOCK cycle seven
- in_complex.re <= TO_DP_DSP_DATA(FBIN); -- The real part of the X pol counts up
- in_complex.im <= TO_DP_DSP_DATA(FBIN); -- The im part of the X pol counts up
+ -- BLOCK cycle seven
+ for FBIN in 0 to c_npoints - 1 loop
+ -- The real part of the X pol counts up
+ in_complex.re <= TO_DP_DSP_DATA(FBIN);
+ -- The im part of the X pol counts up
+ in_complex.im <= TO_DP_DSP_DATA(FBIN);
wait until rising_edge(dp_clk) and valid_enable = '1';
- in_complex.re <= TO_DP_DSP_DATA(FBIN); -- The real part of the Y pol counts up
- in_complex.im <= TO_DP_DSP_DATA(FBIN); -- The im part of the Y pol counts up
+ -- The real part of the Y pol counts up
+ in_complex.re <= TO_DP_DSP_DATA(FBIN);
+ -- The im part of the Y pol counts up
+ in_complex.im <= TO_DP_DSP_DATA(FBIN);
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- for FBIN in 0 to c_npoints - 1 loop -- BLOCK cycle eight
- in_complex.re <= TO_DP_DSP_DATA(-8); -- The real part of the X pol is fixed
- in_complex.im <= TO_DP_DSP_DATA(20); -- The im part of the X pol is fixed
+ -- BLOCK cycle eight
+ for FBIN in 0 to c_npoints - 1 loop
+ -- The real part of the X pol is fixed
+ in_complex.re <= TO_DP_DSP_DATA(-8);
+ -- The im part of the X pol is fixed
+ in_complex.im <= TO_DP_DSP_DATA(20);
wait until rising_edge(dp_clk) and valid_enable = '1';
- in_complex.re <= TO_DP_DSP_DATA(100); -- The real part of the Y pol is fixed
- in_complex.im <= TO_DP_DSP_DATA(-12); -- The im part of the Y pol is fixed
+ -- The real part of the Y pol is fixed
+ in_complex.re <= TO_DP_DSP_DATA(100);
+ -- The im part of the Y pol is fixed
+ in_complex.im <= TO_DP_DSP_DATA(-12);
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- for FBIN in 0 to c_npoints - 1 loop -- BLOCK cycle nine
- in_complex.re <= TO_DP_DSP_DATA(2047); -- The real part of the X pol is fixed
- in_complex.im <= TO_DP_DSP_DATA(2047); -- The im part of the X pol is fixed
+ -- BLOCK cycle nine
+ for FBIN in 0 to c_npoints - 1 loop
+ -- The real part of the X pol is fixed
+ in_complex.re <= TO_DP_DSP_DATA(2047);
+ -- The im part of the X pol is fixed
+ in_complex.im <= TO_DP_DSP_DATA(2047);
wait until rising_edge(dp_clk) and valid_enable = '1';
- in_complex.re <= TO_DP_DSP_DATA(-2047); -- The real part of the Y pol is fixed
- in_complex.im <= TO_DP_DSP_DATA(-2047); -- The im part of the Y pol is fixed
+ -- The real part of the Y pol is fixed
+ in_complex.re <= TO_DP_DSP_DATA(-2047);
+ -- The im part of the Y pol is fixed
+ in_complex.im <= TO_DP_DSP_DATA(-2047);
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
end loop;
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd
index 1060e8f869e95eeff71bbfe4a1e311650fb74d39..b7b5faef54192998238140620471044a684bc721 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd
@@ -41,19 +41,26 @@ use technology_lib.technology_select_pkg.all;
entity tb_iquv_file_data is
generic (
- g_random_valid : boolean := true; -- Put gaps in the valid signal
+ -- Put gaps in the valid signal
+ g_random_valid : boolean := true;
g_data_file : string := "iquv_stimuli_1.dat";
- g_use_accum : boolean := true; -- Use the accumulator stage
- g_nof_int : natural := 16; -- Number of samples to integrate when accumulator is used
- g_in_data_w : natural := 12; -- width of the incoming complex data
- g_out_data_w : natural := 18 -- width of the output data
+ -- Use the accumulator stage
+ g_use_accum : boolean := true;
+ -- Number of samples to integrate when accumulator is used
+ g_nof_int : natural := 16;
+ -- width of the incoming complex data
+ g_in_data_w : natural := 12;
+ -- width of the output data
+ g_out_data_w : natural := 18
);
end tb_iquv_file_data;
architecture tb of tb_iquv_file_data is
constant clk_period : time := 10 ns;
- constant c_fsd_w : natural := g_in_data_w * 2 + 1 + true_log2(g_nof_int); -- The number of bits used for the accumulated result inside the DUT
- constant c_lsb_w : natural := c_fsd_w - g_out_data_w; -- number of lsbs to remove from the expected result
+ -- The number of bits used for the accumulated result inside the DUT
+ constant c_fsd_w : natural := g_in_data_w * 2 + 1 + true_log2(g_nof_int);
+ -- number of lsbs to remove from the expected result
+ constant c_lsb_w : natural := c_fsd_w - g_out_data_w;
signal tb_end : std_logic := '0';
signal dp_rst : std_logic := '1';
@@ -76,9 +83,11 @@ architecture tb of tb_iquv_file_data is
-- Data file access
constant c_nof_nof_int_cases : natural := 3;
- constant c_nof_int_arr : t_integer_arr(0 to c_nof_nof_int_cases - 1) := (8, 16, 1); -- The nof_int cases to test. 1 means no accumulator
+ -- The nof_int cases to test. 1 means no accumulator
+ constant c_nof_int_arr : t_integer_arr(0 to c_nof_nof_int_cases - 1) := (8, 16, 1);
constant c_nof_cols : natural := 4 + 4 * c_nof_nof_int_cases;
- constant c_nof_lines : natural := 14641; -- 11 ** 4
+ -- 11 ** 4
+ constant c_nof_lines : natural := 14641;
signal file_data_arr : t_integer_arr(0 to (c_nof_lines * c_nof_cols) - 1) := (others => 0);
signal xreal_stimuli_arr : t_integer_arr(0 to c_nof_lines - 1) := (others => 0);
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
index 6b3e8f6cd12ab7b8c7e643ba398e4fac7d7b481f..2be08ba2cc598badf7f2b14261bc395920a8de69 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
@@ -40,20 +40,29 @@ use technology_lib.technology_select_pkg.all;
entity tb_iquv_iab is
generic (
- g_nof_int : natural := 16; -- number of successive subbands to integrate
- g_random_valid : boolean := false; -- Put gaps in the valid signal
- g_nof_streams : natural := 12; -- number of imput streams
- g_in_data_w : natural := 12; -- width of the incoming complex data
- g_out_data_w : natural := 18 -- width of the output data
+ -- number of successive subbands to integrate
+ g_nof_int : natural := 16;
+ -- Put gaps in the valid signal
+ g_random_valid : boolean := false;
+ -- number of imput streams
+ g_nof_streams : natural := 12;
+ -- width of the incoming complex data
+ g_in_data_w : natural := 12;
+ -- width of the output data
+ g_out_data_w : natural := 18
);
end tb_iquv_iab;
architecture tb of tb_iquv_iab is
constant clk_period : time := 10 ns;
- constant c_npoints : natural := 4 * g_nof_int; -- number of subbands (size of block) at present only used to generate test vectors
- constant c_iquv_out_w : natural := 18; -- number of bits the IQUV module truncates to
- constant c_fsd_w : natural := c_iquv_out_w + ceil_log2(g_nof_streams); -- The number of bits fsd after the adder tree
- constant c_lsb_w : natural := c_fsd_w - g_out_data_w; -- number of lsbs to remove from the expected result
+ -- number of subbands (size of block) at present only used to generate test vectors
+ constant c_npoints : natural := 4 * g_nof_int;
+ -- number of bits the IQUV module truncates to
+ constant c_iquv_out_w : natural := 18;
+ -- The number of bits fsd after the adder tree
+ constant c_fsd_w : natural := c_iquv_out_w + ceil_log2(g_nof_streams);
+ -- number of lsbs to remove from the expected result
+ constant c_lsb_w : natural := c_fsd_w - g_out_data_w;
constant c_clip : boolean := true;
constant c_wrap : boolean := not c_clip;
@@ -135,23 +144,34 @@ begin
wait until rising_edge(dp_clk);
for I in 0 to 19 loop wait until rising_edge(dp_clk); end loop;
- for BLOCKCOUNT in 0 to 0 loop -- Repeat as needed
+ -- Repeat as needed
+ for BLOCKCOUNT in 0 to 0 loop
- for FBIN in 0 to c_npoints - 1 loop -- BLOCK cycle one
- in_complex.re <= TO_DP_DSP_DATA(10 * FBIN); -- Set the real part of the X pol
- in_complex.im <= TO_DP_DSP_DATA(50 - 10 * FBIN ); -- Set the imag part of the X pol
+ -- BLOCK cycle one
+ for FBIN in 0 to c_npoints - 1 loop
+ -- Set the real part of the X pol
+ in_complex.re <= TO_DP_DSP_DATA(10 * FBIN);
+ -- Set the imag part of the X pol
+ in_complex.im <= TO_DP_DSP_DATA(50 - 10 * FBIN );
wait until rising_edge(dp_clk) and valid_enable = '1';
- in_complex.re <= TO_DP_DSP_DATA(-20 * FBIN); -- Set the real part of the Y pol
- in_complex.im <= TO_DP_DSP_DATA(1000 - 20 * FBIN ); -- Set the imag part of the Y pol
+ -- Set the real part of the Y pol
+ in_complex.re <= TO_DP_DSP_DATA(-20 * FBIN);
+ -- Set the imag part of the Y pol
+ in_complex.im <= TO_DP_DSP_DATA(1000 - 20 * FBIN );
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- for FBIN in 0 to c_npoints - 1 loop -- BLOCK cycle one
- in_complex.re <= TO_DP_DSP_DATA(2047); -- Set the real part of the X pol
- in_complex.im <= TO_DP_DSP_DATA(2047); -- Set the imag part of the X pol
+ -- BLOCK cycle one
+ for FBIN in 0 to c_npoints - 1 loop
+ -- Set the real part of the X pol
+ in_complex.re <= TO_DP_DSP_DATA(2047);
+ -- Set the imag part of the X pol
+ in_complex.im <= TO_DP_DSP_DATA(2047);
wait until rising_edge(dp_clk) and valid_enable = '1';
- in_complex.re <= TO_DP_DSP_DATA(-2047); -- Set the real part of the Y pol
- in_complex.im <= TO_DP_DSP_DATA(-2047); -- Set the imag part of the Y pol
+ -- Set the real part of the Y pol
+ in_complex.re <= TO_DP_DSP_DATA(-2047);
+ -- Set the imag part of the Y pol
+ in_complex.im <= TO_DP_DSP_DATA(-2047);
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
end loop;
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd
index 981d9fb509aea364b8f53ba877a25ef0d56c2650..8f2ffb8b9a1715130c5b217a19e005edcac2c9e2 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd
@@ -41,30 +41,44 @@ use technology_lib.technology_select_pkg.all;
entity tb_iquv_iab_file_data is
generic (
- g_random_valid : boolean := true; -- Put gaps in the valid signal
+ -- Put gaps in the valid signal
+ g_random_valid : boolean := true;
g_data_file : string := "iquv_stimuli_1.dat";
- g_use_accum : boolean := true; -- Use the accumulator stage after the IAB
- g_nof_streams : natural := 12; -- number of imput streams
- g_nof_int : natural := 16; -- Number of samples to integrate when accumulator is used
- g_in_data_w : natural := 12; -- width of the incoming complex data
- g_out_data_w : natural := 18 -- width of the output data
+ -- Use the accumulator stage after the IAB
+ g_use_accum : boolean := true;
+ -- number of imput streams
+ g_nof_streams : natural := 12;
+ -- Number of samples to integrate when accumulator is used
+ g_nof_int : natural := 16;
+ -- width of the incoming complex data
+ g_in_data_w : natural := 12;
+ -- width of the output data
+ g_out_data_w : natural := 18
);
end tb_iquv_iab_file_data;
architecture tb of tb_iquv_iab_file_data is
constant clk_period : time := 10 ns;
- constant c_out_iquv_w : natural := 18; -- number of bits the IQUV module truncates to
- constant c_iquv_accum_w: natural := sel_a_b(g_use_accum, 0, true_log2(g_nof_int)); -- Bitgrowth of the IQUV accumulator
- constant c_iab_accum_w : natural := sel_a_b(g_use_accum, true_log2(g_nof_int), 0); -- Bitgrowth of the IAB accumulator
- constant c_fsd_iquv_w : natural := g_in_data_w * 2 + 1 + c_iquv_accum_w; -- The number of bits used for the result inside the IQUV
- constant c_lsb_iquv_w : natural := c_fsd_iquv_w - c_out_iquv_w; -- number of lsbs to remove from the expected IQUV result
- constant c_fsd_w : natural := c_out_iquv_w + ceil_log2(g_nof_streams) + c_iab_accum_w; -- The number of bits fsd after the IAB adder tree
+ -- number of bits the IQUV module truncates to
+ constant c_out_iquv_w : natural := 18;
+ -- Bitgrowth of the IQUV accumulator
+ constant c_iquv_accum_w: natural := sel_a_b(g_use_accum, 0, true_log2(g_nof_int));
+ -- Bitgrowth of the IAB accumulator
+ constant c_iab_accum_w : natural := sel_a_b(g_use_accum, true_log2(g_nof_int), 0);
+ -- The number of bits used for the result inside the IQUV
+ constant c_fsd_iquv_w : natural := g_in_data_w * 2 + 1 + c_iquv_accum_w;
+ -- number of lsbs to remove from the expected IQUV result
+ constant c_lsb_iquv_w : natural := c_fsd_iquv_w - c_out_iquv_w;
+ -- The number of bits fsd after the IAB adder tree
+ constant c_fsd_w : natural := c_out_iquv_w + ceil_log2(g_nof_streams) + c_iab_accum_w;
-- and IAB accumulator if used
- constant c_lsb_w : natural := c_fsd_w - g_out_data_w; -- number of lsbs to remove from the expected IAB result
+ -- number of lsbs to remove from the expected IAB result
+ constant c_lsb_w : natural := c_fsd_w - g_out_data_w;
constant c_allstreams : natural := g_nof_streams;
constant latency : time := 100 ns;
- constant c_nof_iab_int : natural := sel_a_b(g_use_accum, g_nof_int, 1); -- Used to simulate the IAB accumulator
+ -- Used to simulate the IAB accumulator
+ constant c_nof_iab_int : natural := sel_a_b(g_use_accum, g_nof_int, 1);
signal tb_end : std_logic := '0';
signal dp_rst : std_logic := '1';
@@ -89,9 +103,11 @@ architecture tb of tb_iquv_iab_file_data is
-- Data file access
constant c_nof_nof_int_cases : natural := 3;
- constant c_nof_int_arr : t_integer_arr(0 to c_nof_nof_int_cases - 1) := (8, 16, 1); -- The nof_int cases to test. 1 means no accumulator
+ -- The nof_int cases to test. 1 means no accumulator
+ constant c_nof_int_arr : t_integer_arr(0 to c_nof_nof_int_cases - 1) := (8, 16, 1);
constant c_nof_cols : natural := 4 + 4 * c_nof_nof_int_cases;
- constant c_nof_lines : natural := 14641; -- 11 ** 4
+ -- 11 ** 4
+ constant c_nof_lines : natural := 14641;
signal file_data_arr : t_integer_arr(0 to (c_nof_lines * c_nof_cols) - 1) := (others => 0);
signal xreal_stimuli_arr : t_integer_arr(0 to c_nof_lines - 1) := (others => 0);
@@ -251,7 +267,8 @@ begin
begin
if rising_edge(dp_clk) then
if diag_out_valid = '1' then
- activestream_dly <= activestream; -- make sure we capture the last output valid of each cycle
+ -- make sure we capture the last output valid of each cycle
+ activestream_dly <= activestream;
-- Integration is done in the IQUV
if g_use_accum = false and g_nof_int = 8 then
i_expected_iquv := u_round(TO_UVEC(i_nint8_exp_arr(v_index),c_fsd_iquv_w - 1), c_lsb_iquv_w - 1, true);
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_file_data.vhd b/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_file_data.vhd
index 1dc8c856761c16a0919d57bb39f75f0282dae1b4..9e17ff8aa2bf76a72e69f9c40fe9ed9756776887 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_file_data.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_file_data.vhd
@@ -36,7 +36,8 @@ end tb_tb_iquv_file_data;
architecture tb of tb_tb_iquv_file_data is
constant c_file_name : string := "iquv_stimuli_1.dat";
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Parameter list (random valid, stimuli file, enable accumulator, samples to integrate, input data width, output data width);
u_tc0 : entity work.tb_iquv_file_data generic map (true, c_file_name, true, 8, 12, 18);
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_iab_file_data.vhd b/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_iab_file_data.vhd
index c39a01cde195e3ee7c2dabbb3bb82796b573b54f..bc7a60c7bd8a81e1038bb08e9ba268e7dc6f5870 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_iab_file_data.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_iab_file_data.vhd
@@ -36,7 +36,8 @@ end tb_tb_iquv_iab_file_data;
architecture tb of tb_tb_iquv_iab_file_data is
constant c_file_name : string := "iquv_stimuli_1.dat";
constant c_nof_streams : natural := 3;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- Parameter list (random valid, stimuli file, enable IAB accumulator, number of streams samples to integrate, in data width, out data width);
u_tc0 : entity work.tb_iquv_iab_file_data generic map (true, c_file_name, false, c_nof_streams, 8, 12, 18);
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoBF.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoBF.vhd
index b69305190699438f9e368ae991a02416c52b76d2..18ac16e8b85e3f1e1b57a7cdc2a1837ea9da5212 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoBF.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoBF.vhd
@@ -47,8 +47,10 @@ use common_lib.common_pkg.all;
entity rTwoBF is
generic (
- g_in_a_zdly : natural := 0; -- default 0, 1
- g_out_d_zdly : natural := 0 -- default 0, optionally use 1
+ -- default 0, 1
+ g_in_a_zdly : natural := 0;
+ -- default 0, optionally use 1
+ g_out_d_zdly : natural := 0
);
port (
clk : in std_logic := '0';
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoBFStage.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoBFStage.vhd
index 73302be0901e1a2c82d25d7c1fa8f047510ddc52..e9efb12cdb01022b21a852024c37a94459f31d08 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoBFStage.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoBFStage.vhd
@@ -26,13 +26,19 @@ use common_lib.common_pkg.all;
entity rTwoBFStage is
generic (
-- generics for this stage
- g_nof_chan : natural := 0; -- Exponent of nr of subbands (0 means 1 subband)
- g_stage : natural; -- The stage indices are ..., 3, 2, 1. The input stage has the highest index, the output stage has index 1.
- g_bf_lat : natural := 1; -- Digital pipelining latency
+ -- Exponent of nr of subbands (0 means 1 subband)
+ g_nof_chan : natural := 0;
+ -- The stage indices are ..., 3, 2, 1. The input stage has the highest index, the output stage has index 1.
+ g_stage : natural;
+ -- Digital pipelining latency
+ g_bf_lat : natural := 1;
-- generics for rTwoBF
- g_bf_use_zdly : natural := 1; -- >= 1. Stage high downto g_bf_use_zdly will will use g_bf_in_a_zdly and g_bf_out_zdly
- g_bf_in_a_zdly : natural := 0; -- g_bf_in_a_zdly+g_bf_out_d_zdly must be <= the stage z^(-1) delay, note that stage 1 has only one z^(-1) delay
- g_bf_out_d_zdly : natural := 0 -- The stage z^(-1) delays are ..., 4, 2, 1.
+ -- >= 1. Stage high downto g_bf_use_zdly will will use g_bf_in_a_zdly and g_bf_out_zdly
+ g_bf_use_zdly : natural := 1;
+ -- g_bf_in_a_zdly+g_bf_out_d_zdly must be <= the stage z^(-1) delay, note that stage 1 has only one z^(-1) delay
+ g_bf_in_a_zdly : natural := 0;
+ -- The stage z^(-1) delays are ..., 4, 2, 1.
+ g_bf_out_d_zdly : natural := 0
);
port (
clk : in std_logic;
@@ -57,8 +63,10 @@ architecture str of rTwoBFStage is
constant c_feedback_zdly : natural := pow2(g_stage-1);
-- The BF adds, subtracts or passes the data on, so typically c_out_dat_w = c_in_dat_w + 1
- constant c_in_dat_w : natural := in_re'length; -- re and im have same width
- constant c_out_dat_w : natural := out_re'length; -- re and im have same width
+ -- re and im have same width
+ constant c_in_dat_w : natural := in_re'length;
+ -- re and im have same width
+ constant c_out_dat_w : natural := out_re'length;
-- Concatenate im & re into complex data to potentially ease synthesis to make more efficient use of block RAM memory for z-1 data feedback line
signal bf_complex : std_logic_vector(c_nof_complex * c_in_dat_w - 1 downto 0);
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoOrder.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoOrder.vhd
index 2119f5395f665b651829d856a7332890c150e322..2421a70a29f2f6cda93357ab473bf243dd53e812 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoOrder.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoOrder.vhd
@@ -82,9 +82,11 @@ begin
end if;
end process;
- nxt_in_init <= '0' when next_page = '1' else in_init; -- keep in_init active until the first block has been written
+ -- keep in_init active until the first block has been written
+ nxt_in_init <= '0' when next_page = '1' else in_init;
- in_en <= not in_init; -- disable reading of the first block for convenience in verification, because it contains undefined values
+ -- disable reading of the first block for convenience in verification, because it contains undefined values
+ in_en <= not in_init;
wr_dat <= in_dat;
wr_en <= in_val;
@@ -95,11 +97,13 @@ begin
adr_tot_cnt <= adr_chan_cnt & adr_points_cnt;
gen_bit_flip : if g_bit_flip = true generate
- wr_adr <= adr_chan_cnt & flip(adr_points_cnt); -- flip the addresses to perform the reorder
+ -- flip the addresses to perform the reorder
+ wr_adr <= adr_chan_cnt & flip(adr_points_cnt);
end generate;
no_bit_flip : if g_bit_flip = false generate
- wr_adr <= adr_tot_cnt; -- do not flip the addresses for easier debugging with tb_rTwoOrder
+ -- do not flip the addresses for easier debugging with tb_rTwoOrder
+ wr_adr <= adr_tot_cnt;
end generate;
rd_adr <= adr_tot_cnt;
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDF.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDF.vhd
index 73a859198ecdbbf9335841c5364f5cbd65e07551..ff8a7b971cb431dcdfa3d10ffcf3bb7e25c9070f 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDF.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDF.vhd
@@ -35,13 +35,19 @@ use work.rTwoSDFPkg.all;
entity rTwoSDF is
generic (
-- generics for the FFT
- g_nof_chan : natural := 0; -- Exponent of nr of subbands (0 means 1 subband)
+ -- Exponent of nr of subbands (0 means 1 subband)
+ g_nof_chan : natural := 0;
g_use_reorder : boolean := true;
- g_in_dat_w : natural := 8; -- number of input bits
- g_out_dat_w : natural := 14; -- number of output bits
- g_stage_dat_w : natural := 18; -- number of bits used between the stages
- g_guard_w : natural := 2; -- guard bits are used to avoid overflow in single FFT stage.
- g_nof_points : natural := 1024; -- N point FFT
+ -- number of input bits
+ g_in_dat_w : natural := 8;
+ -- number of output bits
+ g_out_dat_w : natural := 14;
+ -- number of bits used between the stages
+ g_stage_dat_w : natural := 18;
+ -- guard bits are used to avoid overflow in single FFT stage.
+ g_guard_w : natural := 2;
+ -- N point FFT
+ g_nof_points : natural := 1024;
g_round_even : boolean := true;
-- generics for rTwoSDFStage
g_pipeline : t_fft_pipeline := c_fft_pipeline
@@ -60,14 +66,18 @@ end entity rTwoSDF;
architecture str of rTwoSDF is
constant c_nof_stages : natural := ceil_log2(g_nof_points);
- constant c_stage_offset : natural := 0; -- In "normal" pipelined fft operation the stage offset is 0
- constant c_twiddle_offset : natural := 0; -- In "normal" pipelined fft operation the twiddle offset is 0
+ -- In "normal" pipelined fft operation the stage offset is 0
+ constant c_stage_offset : natural := 0;
+ -- In "normal" pipelined fft operation the twiddle offset is 0
+ constant c_twiddle_offset : natural := 0;
-- Round last stage output to g_out_dat_w if g_out_dat_w < g_stage_dat_w else resize to g_out_dat_w
- constant c_out_scale_w : integer := g_stage_dat_w - g_out_dat_w; -- Estimate number of LSBs to round throw away when > 0 or insert when < 0
+ -- Estimate number of LSBs to round throw away when > 0 or insert when < 0
+ constant c_out_scale_w : integer := g_stage_dat_w - g_out_dat_w;
-- Scale the input to make optimal use of the g_stage_dat_w of the stages, using a margin of g_guard_w to account for factor > 2 gain of the first stage
- constant c_in_scale_w : natural := g_stage_dat_w - g_guard_w - g_in_dat_w; -- use type natural instead of integer to implicitly ensure that the g_stage_dat_w >= g_input_dat_w
+ -- use type natural instead of integer to implicitly ensure that the g_stage_dat_w >= g_input_dat_w
+ constant c_in_scale_w : natural := g_stage_dat_w - g_guard_w - g_in_dat_w;
-- number the stage instances from c_nof_stages:1
-- . the data input for the first stage has index c_nof_stages
@@ -100,7 +110,8 @@ begin
g_stage => stage,
g_stage_offset => c_stage_offset,
g_twiddle_offset => c_twiddle_offset,
- g_scale_enable => sel_a_b(stage <= g_guard_w, false, true), -- On average all stages have a gain factor of 2 therefore each stage needs to round 1 bit except for the last g_guard_w nof stages due to the input c_in_scale_w
+ -- On average all stages have a gain factor of 2 therefore each stage needs to round 1 bit except for the last g_guard_w nof stages due to the input c_in_scale_w
+ g_scale_enable => sel_a_b(stage <= g_guard_w, false, true),
g_round_even => g_round_even,
g_pipeline => g_pipeline
)
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFPkg.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFPkg.vhd
index a21087320728da102867c6656a7802ad1222e838..eed1527c2349a222748cf72dc76d899fd7b30ad7 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFPkg.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFPkg.vhd
@@ -27,15 +27,22 @@ package rTwoSDFPkg is
-- Also used for other preallele and wideband FFT implementations (fft_lib)
type t_fft_pipeline is record
-- generics for rTwoSDFStage
- stage_lat : natural; -- = 1
- weight_lat : natural; -- = 1
- mul_lat : natural; -- = 3+1
+ -- = 1
+ stage_lat : natural;
+ -- = 1
+ weight_lat : natural;
+ -- = 3+1
+ mul_lat : natural;
-- generics for rTwoBFStage
- bf_lat : natural; -- = 1
+ -- = 1
+ bf_lat : natural;
-- generics for rTwoBF
- bf_use_zdly : natural; -- = 1
- bf_in_a_zdly : natural; -- = 0
- bf_out_d_zdly : natural; -- = 0
+ -- = 1
+ bf_use_zdly : natural;
+ -- = 0
+ bf_in_a_zdly : natural;
+ -- = 0
+ bf_out_d_zdly : natural;
end record;
constant c_fft_pipeline : t_fft_pipeline := (1, 1, 4, 1, 1, 0, 0);
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd
index 82605e715170a7559056d8839fafbfd892822867..a59124a4255dc9eb4c96ffed24b846080bc2c86a 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd
@@ -27,13 +27,17 @@ use work.rTwoSDFPkg.all;
entity rTwoSDFStage is
generic (
- g_nof_chan : natural := 0; -- Exponent of nr of subbands (0 means 1 subband)
+ -- Exponent of nr of subbands (0 means 1 subband)
+ g_nof_chan : natural := 0;
g_stage : natural := 8;
- g_stage_offset : natural := 0; -- The Stage offset: 0 for normal FFT. Other than 0 in wideband FFT
- g_twiddle_offset : natural := 0; -- The twiddle offset: 0 for normal FFT. Other than 0 in wideband FFT
+ -- The Stage offset: 0 for normal FFT. Other than 0 in wideband FFT
+ g_stage_offset : natural := 0;
+ -- The twiddle offset: 0 for normal FFT. Other than 0 in wideband FFT
+ g_twiddle_offset : natural := 0;
g_scale_enable : boolean := true;
g_round_even : boolean := true;
- g_pipeline : t_fft_pipeline := c_fft_pipeline -- internal pipeline settings
+ -- internal pipeline settings
+ g_pipeline : t_fft_pipeline := c_fft_pipeline
);
port (
clk : in std_logic;
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
index 875f9a660826c83d0e0f58be0e9daea6e46462ce..7d8e5e3c88e981f83935ba9724cc830539f8b069 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
@@ -30,7 +30,8 @@ entity rTwoWMul is
g_technology : natural := c_tech_select_default;
g_stage : natural := 1;
g_round_even : boolean := true;
- g_lat : natural := 3 + 1 -- 3 for mult, 1 for round
+ -- 3 for mult, 1 for round
+ g_lat : natural := 3 + 1
);
port (
clk : in std_logic;
@@ -52,7 +53,8 @@ architecture str of rTwoWMul is
-- Apertif and using the WG at various frequencies at subband or between subbands it appears that
-- using truncate or sround does not make a noticable difference in the SST. Still choose to use
-- signed rounding to preserve zero DC.
- constant c_use_truncate : boolean := true; -- false;
+ -- false;
+ constant c_use_truncate : boolean := true;
-- Derive the common_complex_mult g_pipeline_* values from g_lat. The sum c_total_lat = g_lat, so that g_lat defines
-- the total latency from in_* to out_*.
@@ -61,14 +63,20 @@ architecture str of rTwoWMul is
constant c_dsp_mult_lat : natural := 3;
-- Pipeline multiplier product rounding from c_prod_w via c_round_w to c_out_dat_w
- constant c_round_lat : natural := sel_a_b(g_lat > c_dsp_mult_lat, 1, 0); -- allocate 1 pipeline for round
- constant c_lat : natural := g_lat - c_round_lat; -- allocate remaining pipeline to multiplier
+ -- allocate 1 pipeline for round
+ constant c_round_lat : natural := sel_a_b(g_lat > c_dsp_mult_lat, 1, 0);
+ -- allocate remaining pipeline to multiplier
+ constant c_lat : natural := g_lat - c_round_lat;
- constant c_mult_input_lat : natural := sel_a_b(c_lat > 1, 1, 0); -- second priority use DSP pipeline input
+ -- second priority use DSP pipeline input
+ constant c_mult_input_lat : natural := sel_a_b(c_lat > 1, 1, 0);
constant c_mult_product_lat : natural := 0;
- constant c_mult_adder_lat : natural := sel_a_b(c_lat > 2, 1, 0); -- third priority use DSP internal product-sum pipeline
- constant c_mult_extra_lat : natural := sel_a_b(c_lat > 3, c_lat - 3, 0); -- remaining extra pipelining in logic
- constant c_mult_output_lat : natural := sel_a_b(c_lat > 0, 1, 0) + c_mult_extra_lat; -- first priority use DSP pipeline output
+ -- third priority use DSP internal product-sum pipeline
+ constant c_mult_adder_lat : natural := sel_a_b(c_lat > 2, 1, 0);
+ -- remaining extra pipelining in logic
+ constant c_mult_extra_lat : natural := sel_a_b(c_lat > 3, c_lat - 3, 0);
+ -- first priority use DSP pipeline output
+ constant c_mult_output_lat : natural := sel_a_b(c_lat > 0, 1, 0) + c_mult_extra_lat;
constant c_mult_lat : natural := c_mult_input_lat + c_mult_product_lat + c_mult_adder_lat + c_mult_output_lat;
constant c_max_dsp_mult_w : natural := sel_a_b(g_technology = c_tech_stratixiv, c_dsp_mult_18_w, c_dsp_mult_27_w);
@@ -81,7 +89,8 @@ architecture str of rTwoWMul is
constant c_prod_w : natural := c_in_dat_w + c_weight_w + 1;
constant c_out_dat_w : natural := out_re'length;
constant c_out_extra_w : natural := c_out_dat_w - c_in_dat_w;
- constant c_round_w : natural := c_weight_w - c_sign_w - c_out_extra_w; -- the weights are normalized, c_out_extra_w will be rounded externally at stage output
+ -- the weights are normalized, c_out_extra_w will be rounded externally at stage output
+ constant c_round_w : natural := c_weight_w - c_sign_w - c_out_extra_w;
signal in_re_dly : std_logic_vector(in_re'range);
signal in_im_dly : std_logic_vector(in_re'range);
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd
index 5f7b31c5ce915cab37dc04cdf5cd045396441157..b842a2ac68ba5d40d13adcda64ddeb3ee9101450 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd
@@ -37,10 +37,14 @@ use work.twiddlesPkg.all;
entity rTwoWeights is
generic (
- g_stage : natural := 4; -- The stage number of the pft
- g_lat : natural := 1; -- latency 0 or 1
- g_twiddle_offset : natural := 0; -- The twiddle offset: 0 for normal FFT. Other than 0 in wideband FFT
- g_stage_offset : natural := 0 -- The Stage offset: 0 for normal FFT. Other than 0 in wideband FFT
+ -- The stage number of the pft
+ g_stage : natural := 4;
+ -- latency 0 or 1
+ g_lat : natural := 1;
+ -- The twiddle offset: 0 for normal FFT. Other than 0 in wideband FFT
+ g_twiddle_offset : natural := 0;
+ -- The Stage offset: 0 for normal FFT. Other than 0 in wideband FFT
+ g_stage_offset : natural := 0
);
port (
clk : in std_logic;
@@ -51,8 +55,10 @@ entity rTwoWeights is
end;
architecture rtl of rTwoWeights is
- constant c_virtual_stage : integer := g_stage + g_stage_offset; -- Virtual stage based on the real stage and the stage_offset.
- constant c_nof_shifts : integer := -1 * g_stage_offset; -- Shift factor when fft is used in wfft configuration
+ -- Virtual stage based on the real stage and the stage_offset.
+ constant c_virtual_stage : integer := g_stage + g_stage_offset;
+ -- Shift factor when fft is used in wfft configuration
+ constant c_nof_shifts : integer := -1 * g_stage_offset;
signal nxt_weight_re : wTyp;
signal nxt_weight_im : wTyp;
diff --git a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoOrder.vhd b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoOrder.vhd
index 2781ff5e6ea7226f6a474d9925e0ee59fc1e5c60..a7058c57723f6fd3f5ad11db9b290b1ec153f1b8 100644
--- a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoOrder.vhd
+++ b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoOrder.vhd
@@ -48,7 +48,8 @@ architecture tb of tb_rTwoOrder is
signal rst : std_logic;
signal clk : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
signal in_dat : std_logic_vector(c_dat_w - 1 downto 0) := TO_UVEC(1, c_dat_w);
signal in_val : std_logic;
@@ -76,7 +77,8 @@ begin
-- FOR I IN 0 TO 1 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
-- one block
- in_val <= not in_val; -- toggling
+ -- toggling
+ in_val <= not in_val;
for I in 0 to c_nof_points - 1 loop
--in_val <= NOT in_val; -- toggling
--in_val <= random_0(random_0'HIGH); -- random
diff --git a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
index 1dac5bc00bd01bffeca324bec34d6ee80ef24a4c..b264ed5d3c4b10822c1b1420186bb258ced7c74f 100644
--- a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
+++ b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
@@ -87,14 +87,19 @@ use work.twiddlesPkg.all;
entity tb_rTwoSDF is
generic(
-- generics for tb
- g_use_uniNoise_file : boolean := true; -- golden results currently only available for false (noise data)
- g_in_en : natural := 1; -- 1 = always active, others = random control
+ -- golden results currently only available for false (noise data)
+ g_use_uniNoise_file : boolean := true;
+ -- 1 = always active, others = random control
+ g_in_en : natural := 1;
-- generics for rTwoSDF
- g_use_reorder : boolean := true; -- tb supports both true and false, use true to create golden output file
+ -- tb supports both true and false, use true to create golden output file
+ g_use_reorder : boolean := true;
g_nof_points : natural := 1024;
- g_in_dat_w : natural := 8; -- use g_in_dat_w = 8 when g_use_uniNoise_file = true
+ -- use g_in_dat_w = 8 when g_use_uniNoise_file = true
+ g_in_dat_w : natural := 8;
g_out_dat_w : natural := 14;
- g_guard_w : natural := 2 -- guard bits are used to avoid overflow in single FFT stage.
+ -- guard bits are used to avoid overflow in single FFT stage.
+ g_guard_w : natural := 2
);
end entity tb_rTwoSDF;
@@ -105,11 +110,13 @@ architecture tb of tb_rTwoSDF is
-- input/output data width
constant c_twiddle_w : natural := wTyp'length;
- constant c_stage_dat_w : natural := sel_a_b(g_out_dat_w > c_dsp_mult_w, g_out_dat_w, c_dsp_mult_w); -- number of bits used between the stages
+ -- number of bits used between the stages
+ constant c_stage_dat_w : natural := sel_a_b(g_out_dat_w > c_dsp_mult_w, g_out_dat_w, c_dsp_mult_w);
-- input/output files
constant c_file_len : natural := 8 * g_nof_points;
- constant c_repeat : natural := 2; -- >= 2 to have sufficent frames for c_outputFile evaluation by testFFT_output.m
+ -- >= 2 to have sufficent frames for c_outputFile evaluation by testFFT_output.m
+ constant c_repeat : natural := 2;
-- input from uniform noise file created automatically by MATLAB testFFT_input.m
constant c_noiseInputFile : string := "data/test/in/uniNoise_p" & natural'image(g_nof_points) & "_b" & natural'image(g_in_dat_w) & "_in.txt";
@@ -133,7 +140,8 @@ architecture tb of tb_rTwoSDF is
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enable : std_logic := '1';
- signal random : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(15 downto 0) := (others => '0');
signal in_en : std_logic := '0';
signal in_re : std_logic_vector(g_in_dat_w - 1 downto 0);
@@ -146,14 +154,16 @@ architecture tb of tb_rTwoSDF is
signal out_sync : std_logic := '0';
signal out_val : std_logic := '0';
- signal in_file_data : t_integer_matrix(0 to c_file_len - 1, 1 to 2) := (others => (others => 0)); -- [re, im]
+ -- [re, im]
+ signal in_file_data : t_integer_matrix(0 to c_file_len - 1, 1 to 2) := (others => (others => 0));
signal in_file_sync : std_logic_vector(0 to c_file_len - 1) := (others => '0');
signal in_file_val : std_logic_vector(0 to c_file_len - 1) := (others => '0');
signal in_index : natural := 0;
signal in_repeat : natural := 0;
- signal gold_file_data : t_integer_matrix(0 to c_file_len - 1, 1 to 2) := (others => (others => 0)); -- [re, im]
+ -- [re, im]
+ signal gold_file_data : t_integer_matrix(0 to c_file_len - 1, 1 to 2) := (others => (others => 0));
signal gold_file_sync : std_logic_vector(0 to c_file_len - 1) := (others => '0');
signal gold_file_val : std_logic_vector(0 to c_file_len - 1) := (others => '0');
@@ -171,7 +181,8 @@ begin
in_en <= '1' when g_in_en = 1 else random(random'high);
p_read_input_file : process
- file v_input : TEXT open READ_MODE is c_inputFile; -- this is LRM 1076-1987 style and implies that only simulator start and quit can open and close the file
+ -- this is LRM 1076-1987 style and implies that only simulator start and quit can open and close the file
+ file v_input : TEXT open READ_MODE is c_inputFile;
variable v_log_line : LINE;
variable v_input_line : LINE;
variable v_index : integer := 0;
@@ -190,16 +201,20 @@ begin
exit when endfile(v_input);
readline(v_input, v_input_line);
- read(v_input_line, v_sync(v_index)); -- sync
+ -- sync
+ read(v_input_line, v_sync(v_index));
read(v_input_line, v_comma);
- read(v_input_line, v_val(v_index)); -- valid
+ -- valid
+ read(v_input_line, v_val(v_index));
read(v_input_line, v_comma);
- read(v_input_line, v_data(v_index,1)); -- real
+ -- real
+ read(v_input_line, v_data(v_index,1));
read(v_input_line, v_comma);
- read(v_input_line, v_data(v_index,2)); -- imag
+ -- imag
+ read(v_input_line, v_data(v_index,2));
v_index := v_index + 1;
end loop;
write(v_log_line, string'("finished reading stimuli file"));
@@ -262,7 +277,8 @@ begin
g_stage_dat_w => c_stage_dat_w,
g_guard_w => g_guard_w,
g_nof_points => g_nof_points,
- g_round_even => false -- golden results use round half away instead of round half even
+ -- golden results use round half away instead of round half even
+ g_round_even => false
)
port map(
clk => clk,
@@ -277,7 +293,8 @@ begin
-- Read golden file with the expected DUT output
p_read_golden_file : process
- file v_golden : TEXT open READ_MODE is c_goldenFile; -- this is LRM 1076-1987 style and implies that only simulator start and quit can open and close the file
+ -- this is LRM 1076-1987 style and implies that only simulator start and quit can open and close the file
+ file v_golden : TEXT open READ_MODE is c_goldenFile;
variable v_log_line : LINE;
variable v_golden_line : LINE;
variable v_index : integer := 0;
@@ -296,16 +313,20 @@ begin
exit when endfile(v_golden);
readline(v_golden, v_golden_line);
- read(v_golden_line, v_sync(v_index)); -- sync
+ -- sync
+ read(v_golden_line, v_sync(v_index));
read(v_golden_line, v_comma);
- read(v_golden_line, v_val(v_index)); -- valid
+ -- valid
+ read(v_golden_line, v_val(v_index));
read(v_golden_line, v_comma);
- read(v_golden_line, v_data(v_index,1)); -- real
+ -- real
+ read(v_golden_line, v_data(v_index,1));
read(v_golden_line, v_comma);
- read(v_golden_line, v_data(v_index,2)); -- imag
+ -- imag
+ read(v_golden_line, v_data(v_index,2));
v_index := v_index + 1;
end loop;
write(v_log_line, string'("finished reading golden file"));
@@ -340,7 +361,8 @@ begin
-- Write to default output file, this allows using command line diff or graphical diff viewer to compare it with the golden result file
p_write_output_file : process(clk)
- file v_output : TEXT open WRITE_MODE is c_outputFile; -- this is LRM 1076-1987 style and implies that only simulator start and quit can open and close the file
+ -- this is LRM 1076-1987 style and implies that only simulator start and quit can open and close the file
+ file v_output : TEXT open WRITE_MODE is c_outputFile;
variable v_line : LINE;
begin
if rising_edge(clk) then
diff --git a/libraries/dsp/rTwoSDF/tb/vhdl/tb_tb_rTwoSDF.vhd b/libraries/dsp/rTwoSDF/tb/vhdl/tb_tb_rTwoSDF.vhd
index eaaaa888480aaf53d446291076428305ab790e16..7511e4b0c93bf843104452a9573c7d08da7760d9 100644
--- a/libraries/dsp/rTwoSDF/tb/vhdl/tb_tb_rTwoSDF.vhd
+++ b/libraries/dsp/rTwoSDF/tb/vhdl/tb_tb_rTwoSDF.vhd
@@ -38,7 +38,8 @@ entity tb_tb_rTwoSDF is
end entity tb_tb_rTwoSDF;
architecture tb of tb_tb_rTwoSDF is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- generics for tb
-- g_use_uniNoise_file : boolean := true;
diff --git a/libraries/dsp/si/src/vhdl/si.vhd b/libraries/dsp/si/src/vhdl/si.vhd
index 6e5a85aff3e9b328c85538f97a9ff5205fae8b60..da66ba5a33a3e95d324a6611e44e9ede2a1596b4 100755
--- a/libraries/dsp/si/src/vhdl/si.vhd
+++ b/libraries/dsp/si/src/vhdl/si.vhd
@@ -41,7 +41,8 @@ use dp_lib.dp_stream_pkg.all;
entity si is
generic (
- g_pipeline : natural := 1; -- 0 for wires, 1 for output pipeline
+ -- 0 for wires, 1 for output pipeline
+ g_pipeline : natural := 1;
g_dat_w : natural := 18
);
port (
diff --git a/libraries/dsp/si/src/vhdl/si_arr.vhd b/libraries/dsp/si/src/vhdl/si_arr.vhd
index 2ef041cda1e33cd0e84d0fa2f09a5fb4a8d76f9d..d713c38f1dbf02685e391e0d1eb7092827d99e82 100755
--- a/libraries/dsp/si/src/vhdl/si_arr.vhd
+++ b/libraries/dsp/si/src/vhdl/si_arr.vhd
@@ -37,7 +37,8 @@ use dp_lib.dp_stream_pkg.all;
entity si_arr is
generic (
g_nof_streams : natural := 1;
- g_pipeline : natural := 1; -- 0 for wires, 1 for output pipeline
+ -- 0 for wires, 1 for output pipeline
+ g_pipeline : natural := 1;
g_dat_w : natural := 18
);
port (
diff --git a/libraries/dsp/si/tb/vhdl/tb_si.vhd b/libraries/dsp/si/tb/vhdl/tb_si.vhd
index 98cc1d9762ef1c18df3e60e9f1f8702a32392934..311a42444a0774537979ba76523c3dbd2f74b6fb 100755
--- a/libraries/dsp/si/tb/vhdl/tb_si.vhd
+++ b/libraries/dsp/si/tb/vhdl/tb_si.vhd
@@ -220,8 +220,10 @@ begin
-- identify clip wrap of -c_min to +c_max
if v_even = c_max and v_odd = c_min then v_clip_even := '1'; else v_clip_even := '0'; end if;
if v_even = c_min and v_odd = c_max then v_clip_odd := '1'; else v_clip_odd := '0'; end if;
- clip_even <= v_clip_even; -- show in wave window (only cycle late)
- clip_odd <= v_clip_odd; -- show in wave window (only cycle late)
+ -- show in wave window (only cycle late)
+ clip_even <= v_clip_even;
+ -- show in wave window (only cycle late)
+ clip_odd <= v_clip_odd;
-- compare pair
if tb_end = '0' then
if verify_en = '1' then
diff --git a/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd b/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
index 011a1479fc07a0d07cc0f5706f3346ee20876662..54a7a328d247fe05210152c4dced4506fb1e0d37 100644
--- a/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
@@ -165,7 +165,8 @@ begin
port map (
clk => dp_clk,
rst => dp_rst,
- in_dat => snk_in_arr(0).sync, -- Use only the status signal of st_histogram instance 0
+ -- Use only the status signal of st_histogram instance 0
+ in_dat => snk_in_arr(0).sync,
out_dat => ram_fill
);
diff --git a/libraries/dsp/st/src/vhdl/st_acc.vhd b/libraries/dsp/st/src/vhdl/st_acc.vhd
index 62ffc2e0963c77ee7fcc83a914e9f2ab91101956..8526736dd460dbd82ed7201c1968bac6dcf5f09a 100644
--- a/libraries/dsp/st/src/vhdl/st_acc.vhd
+++ b/libraries/dsp/st/src/vhdl/st_acc.vhd
@@ -43,10 +43,13 @@ use common_lib.common_pkg.all;
entity st_acc is
generic (
g_dat_w : natural;
- g_acc_w : natural; -- g_acc_w >= g_dat_w
+ -- g_acc_w >= g_dat_w
+ g_acc_w : natural;
g_hold_load : boolean := true;
- g_pipeline_input : natural; -- 0 no input registers, else register input after in_load
- g_pipeline_output : natural -- pipeline for the adder
+ -- 0 no input registers, else register input after in_load
+ g_pipeline_input : natural;
+ -- pipeline for the adder
+ g_pipeline_output : natural
);
port (
clk : in std_logic;
@@ -100,7 +103,8 @@ begin
-- . For g_pipeline_input>0 this is fine
-- . For g_pipeline_input=0 this may cause difficulty in achieving timing closure for synthesis
use_in_load : if g_hold_load = false generate
- acc_clr <= in_load; -- the in_load may already be extended during in_val
+ -- the in_load may already be extended during in_val
+ acc_clr <= in_load;
end generate;
use_hld_load : if g_hold_load = true generate
@@ -135,7 +139,8 @@ begin
u_adder : entity common_lib.common_add_sub
generic map (
g_direction => "ADD",
- g_representation => "SIGNED", -- not relevant because g_out_dat_w = g_in_dat_w
+ -- not relevant because g_out_dat_w = g_in_dat_w
+ g_representation => "SIGNED",
g_pipeline_input => 0,
g_pipeline_output => g_pipeline_output,
g_in_dat_w => g_acc_w,
diff --git a/libraries/dsp/st/src/vhdl/st_calc.vhd b/libraries/dsp/st/src/vhdl/st_calc.vhd
index 5e895907bdf2e33662392f70e0bf21c92c8547e2..88d7fd23c903141abd40309c76c3b41961e06a72 100644
--- a/libraries/dsp/st/src/vhdl/st_calc.vhd
+++ b/libraries/dsp/st/src/vhdl/st_calc.vhd
@@ -56,9 +56,12 @@ entity st_calc is
g_technology : natural := c_tech_select_default;
g_nof_mux : natural := 1;
g_nof_stat : natural := 512;
- g_in_dat_w : natural := 18; -- = input data width
- g_out_dat_w : natural := 54; -- = accumulator width for the input data products, so >> 2*g_in_dat_w
- g_out_adr_w : natural := 9; -- = ceil_log2(g_nof_stat)
+ -- = input data width
+ g_in_dat_w : natural := 18;
+ -- = accumulator width for the input data products, so >> 2*g_in_dat_w
+ g_out_dat_w : natural := 54;
+ -- = ceil_log2(g_nof_stat)
+ g_out_adr_w : natural := 9;
g_complex : boolean := false
);
port (
@@ -74,8 +77,10 @@ entity st_calc is
out_adr : out std_logic_vector(g_out_adr_w - 1 downto 0);
out_re : out std_logic_vector(g_out_dat_w - 1 downto 0);
out_im : out std_logic_vector(g_out_dat_w - 1 downto 0);
- out_val : out std_logic; -- Use when g_nof_mux = 1, else leave OPEN
- out_val_m : out std_logic_vector(g_nof_mux - 1 downto 0) -- Use when g_nof_mux > 1, else leave OPEN
+ -- Use when g_nof_mux = 1, else leave OPEN
+ out_val : out std_logic;
+ -- Use when g_nof_mux > 1, else leave OPEN
+ out_val_m : out std_logic_vector(g_nof_mux - 1 downto 0)
);
end;
@@ -83,7 +88,8 @@ architecture str of st_calc is
constant c_complex_mult_variant : string := sel_a_b(g_in_dat_w <= c_dsp_mult_w, "IP", "RTL");
constant c_mux_w : natural := true_log2(g_nof_mux);
- constant c_adr_w : natural := c_mux_w + g_out_adr_w; -- = = ceil_log2(g_nof_mux*g_nof_stat)
+ -- = = ceil_log2(g_nof_mux*g_nof_stat)
+ constant c_adr_w : natural := c_mux_w + g_out_adr_w;
constant c_dly_rd : natural := 2;
constant c_dly_mul : natural := 3;
@@ -96,7 +102,8 @@ architecture str of st_calc is
constant c_acc_hold_load : boolean := true;
constant c_rd_latency : natural := 2;
- constant c_mem_acc : t_c_mem := (c_rd_latency, c_adr_w, c_acc_w, g_nof_mux * g_nof_stat, 'X'); -- 1 M9K
+ -- 1 M9K
+ constant c_mem_acc : t_c_mem := (c_rd_latency, c_adr_w, c_acc_w, g_nof_mux * g_nof_stat, 'X');
signal mult_re : std_logic_vector(c_mult_w - 1 downto 0);
signal mult_im : std_logic_vector(c_mult_w - 1 downto 0);
@@ -194,11 +201,13 @@ begin
g_in_a_w => in_ar'LENGTH,
g_in_b_w => in_br'LENGTH,
g_out_p_w => mult_re'LENGTH,
- g_conjugate_b => true, -- use conjugate product for cross power
+ -- use conjugate product for cross power
+ g_conjugate_b => true,
g_pipeline_input => 1,
g_pipeline_product => 0,
g_pipeline_adder => 1,
- g_pipeline_output => 1 -- 1+0+1+1 = 3 = c_dly_mul
+ -- 1+0+1+1 = 3 = c_dly_mul
+ g_pipeline_output => 1
)
port map (
clk => clk,
@@ -249,7 +258,8 @@ begin
rd_val => open
);
- out_re <= rd_re; -- c_dly_out = 0
+ -- c_dly_out = 0
+ out_re <= rd_re;
-- imaginary part is optional
no_im: if g_complex = false generate
@@ -295,7 +305,8 @@ begin
rd_val => open
);
- out_im <= rd_im; -- c_dly_out = 0
+ -- c_dly_out = 0
+ out_im <= rd_im;
end generate;
end str;
diff --git a/libraries/dsp/st/src/vhdl/st_ctrl.vhd b/libraries/dsp/st/src/vhdl/st_ctrl.vhd
index ee08d4e8f413fb83a8e23d598407b965c3956775..9853bef19876c2215a13a2fc7eab5c744f4e73d7 100644
--- a/libraries/dsp/st/src/vhdl/st_ctrl.vhd
+++ b/libraries/dsp/st/src/vhdl/st_ctrl.vhd
@@ -28,7 +28,8 @@ entity st_ctrl is
generic (
g_nof_mux : natural := 1;
g_nof_stat : natural := 512;
- g_adr_w : natural := 9; -- ceil_log2(g_nof_mux*g_nof_stat)
+ -- ceil_log2(g_nof_mux*g_nof_stat)
+ g_adr_w : natural := 9;
g_dly_rd : natural := 1;
g_dly_mul : natural := 4;
g_dly_acc : natural := 2;
diff --git a/libraries/dsp/st/src/vhdl/st_histogram.vhd b/libraries/dsp/st/src/vhdl/st_histogram.vhd
index 10e3901f52c22f4ea4d30a2e4185ae5f5fd4233a..1adf888837ce045c3600fc2930f60ff195ca4649 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram.vhd
@@ -102,18 +102,23 @@ use technology_lib.technology_select_pkg.all;
entity st_histogram is
generic (
g_data_w : natural := 8;
- g_nof_bins : natural := 256; -- <= 2^g_data_w (having more bins than possible values is not useful)
+ -- <= 2^g_data_w (having more bins than possible values is not useful)
+ g_nof_bins : natural := 256;
g_nof_data_per_sync : natural := 1024;
- g_nof_data_per_sync_diff : natural := 0; -- Allow +- g_nof_data_per_sync_diff samples per sync interval
- g_data_type : string := "unsigned" -- unsigned or signed
+ -- Allow +- g_nof_data_per_sync_diff samples per sync interval
+ g_nof_data_per_sync_diff : natural := 0;
+ -- unsigned or signed
+ g_data_type : string := "unsigned"
);
port (
dp_clk : in std_logic;
dp_rst : in std_logic;
- snk_in : in t_dp_sosi; -- Active RAM page swaps on snk_in.sync
+ -- Active RAM page swaps on snk_in.sync
+ snk_in : in t_dp_sosi;
- ram_mosi : in t_mem_mosi; -- MM access to the inactive RAM page
+ -- MM access to the inactive RAM page
+ ram_mosi : in t_mem_mosi;
ram_miso : out t_mem_miso
);
end st_histogram;
@@ -134,7 +139,8 @@ architecture rtl of st_histogram is
-------------------------------------------------------------------------------
-- snk_in_reg_arr
-------------------------------------------------------------------------------
- constant c_ram_rd_wr_latency : natural := 3; -- RAM read,incr,write cycle latency
+ -- RAM read,incr,write cycle latency
+ constant c_ram_rd_wr_latency : natural := 3;
constant c_shiftreg_depth : natural := c_ram_rd_wr_latency + 1;
signal snk_in_reg_arr : t_dp_sosi_arr(c_shiftreg_depth - 1 downto 0);
@@ -190,7 +196,8 @@ architecture rtl of st_histogram is
-- ram_clear
-------------------------------------------------------------------------------
constant c_data_cnt_w : natural := ceil_log2(g_nof_data_per_sync + g_nof_data_per_sync_diff);
- constant c_clear_sample_cnt : natural := g_nof_data_per_sync - g_nof_data_per_sync_diff; -- Clear sooner (-g_nof_data_per_sync_diff) rather than later
+ -- Clear sooner (-g_nof_data_per_sync_diff) rather than later
+ constant c_clear_sample_cnt : natural := g_nof_data_per_sync - g_nof_data_per_sync_diff;
signal data_cnt : std_logic_vector(c_data_cnt_w - 1 downto 0);
signal nxt_data_cnt : std_logic_vector(c_data_cnt_w - 1 downto 0);
@@ -251,7 +258,8 @@ begin
if snk_in.valid = '1' then
-- The base function is a shift register
nxt_snk_in_reg_arr(0) <= snk_in;
- nxt_snk_in_reg_arr(0).data(c_ram_adr_w - 1 downto 0) <= snk_in_data; -- Use the ranged data
+ -- Use the ranged data
+ nxt_snk_in_reg_arr(0).data(c_ram_adr_w - 1 downto 0) <= snk_in_data;
nxt_snk_in_reg_arr(1) <= snk_in_reg_arr(0);
nxt_snk_in_reg_arr(2) <= snk_in_reg_arr(1);
nxt_snk_in_reg_arr(3) <= snk_in_reg_arr(2);
@@ -266,15 +274,18 @@ begin
nxt_snk_in_reg_arr(1).channel <= TO_DP_CHANNEL(0);
nxt_snk_in_reg_arr(2).valid <= '0';
nxt_snk_in_reg_arr(2).channel <= TO_DP_CHANNEL(0);
- nxt_snk_in_reg_arr(3).channel <= TO_DP_CHANNEL(3); -- 0,1,2 match: put count=3 here
+ -- 0,1,2 match: put count=3 here
+ nxt_snk_in_reg_arr(3).channel <= TO_DP_CHANNEL(3);
elsif func_dp_data_match(snk_in_reg_arr(1), snk_in_reg_arr(2), g_data_w) and snk_in_reg_arr(1).sync = '0' then
nxt_snk_in_reg_arr(2).valid <= '0';
nxt_snk_in_reg_arr(2).channel <= TO_DP_CHANNEL(0);
- nxt_snk_in_reg_arr(3).channel <= TO_DP_CHANNEL(2); -- 1,2 match: put count=2 here
+ -- 1,2 match: put count=2 here
+ nxt_snk_in_reg_arr(3).channel <= TO_DP_CHANNEL(2);
elsif func_dp_data_match(snk_in_reg_arr(0), snk_in_reg_arr(2), g_data_w) and (snk_in_reg_arr(0).sync = '0' and snk_in_reg_arr(1).sync = '0') then
nxt_snk_in_reg_arr(1).valid <= '0';
nxt_snk_in_reg_arr(1).channel <= TO_DP_CHANNEL(0);
- nxt_snk_in_reg_arr(3).channel <= TO_DP_CHANNEL(2); -- 0,2 match: put count=2 here
+ -- 0,2 match: put count=2 here
+ nxt_snk_in_reg_arr(3).channel <= TO_DP_CHANNEL(2);
end if;
end if;
end process;
@@ -340,7 +351,8 @@ begin
bin_reader_to_writer_mosi.wr <= bin_reader_miso.rdval;
bin_reader_to_writer_mosi.wrdata <= RESIZE_UVEC(bin_reader_miso.rddata(c_ram_dat_w - 1 downto 0), c_mem_data_w);
bin_reader_to_writer_mosi.address <= prv_bin_reader_mosi.address;
- nxt_bin_reader_to_writer_count <= TO_UINT(snk_in_reg.channel); -- Use register (_nxt) to align count with rdval instead of snk_in_reg.valid
+ -- Use register (_nxt) to align count with rdval instead of snk_in_reg.valid
+ nxt_bin_reader_to_writer_count <= TO_UINT(snk_in_reg.channel);
-------------------------------------------------------------------------------
-- bin_writer : Increment the bin, do write request
diff --git a/libraries/dsp/st/src/vhdl/st_sst.vhd b/libraries/dsp/st/src/vhdl/st_sst.vhd
index 97fa6e9e29e6f45280fbb999650e38f901d4a083..133b4a43b0800a566e1e0b6d4b99e3f187f14283 100644
--- a/libraries/dsp/st/src/vhdl/st_sst.vhd
+++ b/libraries/dsp/st/src/vhdl/st_sst.vhd
@@ -21,7 +21,8 @@
library IEEE, common_lib, mm_lib, technology_lib, dp_lib;
use IEEE.std_logic_1164.all;
-use IEEE.math_real.all; -- for sim only
+-- for sim only
+use IEEE.math_real.all;
use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use common_lib.common_field_pkg.all;
@@ -61,12 +62,18 @@ use technology_lib.technology_select_pkg.all;
entity st_sst is
generic (
g_technology : natural := c_tech_select_default;
- g_nof_stat : natural := 512; -- total nof accumulators
- g_xst_enable : boolean := false; -- when set to true, an extra memory is instantiated to hold the imaginary part of the cross-correlation results
- g_in_data_w : natural := 18; -- width o dth edata to be accumulated
- g_stat_data_w : natural := 54; -- statistics accumulator width
- g_stat_data_sz : natural := 2; -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
- g_stat_multiplex: natural := 2 -- number of accumulators per stat_bin, for debug purposes with view in Wave window
+ -- total nof accumulators
+ g_nof_stat : natural := 512;
+ -- when set to true, an extra memory is instantiated to hold the imaginary part of the cross-correlation results
+ g_xst_enable : boolean := false;
+ -- width o dth edata to be accumulated
+ g_in_data_w : natural := 18;
+ -- statistics accumulator width
+ g_stat_data_w : natural := 54;
+ -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ g_stat_data_sz : natural := 2;
+ -- number of accumulators per stat_bin, for debug purposes with view in Wave window
+ g_stat_multiplex: natural := 2
);
port (
mm_rst : in std_logic;
@@ -75,7 +82,8 @@ entity st_sst is
dp_clk : in std_logic;
-- Streaming
- in_complex : in t_dp_sosi; -- Complex input data
+ -- Complex input data
+ in_complex : in t_dp_sosi;
-- Memory Mapped
ram_st_sst_mosi : in t_mem_mosi;
@@ -97,12 +105,14 @@ architecture str of st_sst is
adr_w => c_nof_word_w,
dat_w => c_word_w,
nof_dat => c_nof_word,
- init_sl => '0'); -- MM side : sla_in, sla_out
+ -- MM side : sla_in, sla_out
+ init_sl => '0');
constant c_stat_ram : t_c_mem := (latency => 1,
adr_w => c_nof_stat_w,
dat_w => g_stat_word_w,
nof_dat => g_nof_stat,
- init_sl => '0'); -- ST side : stat_mosi
+ -- ST side : stat_mosi
+ init_sl => '0');
constant c_field_arr : t_common_field_arr(0 downto 0) := (0 => ( field_name_pad("treshold"), "RW", c_nof_stat_w, field_default(0) ));
@@ -262,7 +272,8 @@ begin
rst_b => dp_rst,
clk_b => dp_clk,
- wr_en_a => ram_st_sst_mosi_arr(0).wr, -- only for diagnostic purposes, typically statistics are read only
+ -- only for diagnostic purposes, typically statistics are read only
+ wr_en_a => ram_st_sst_mosi_arr(0).wr,
wr_dat_a => ram_st_sst_mosi_arr(0).wrdata(c_mm_ram.dat_w - 1 downto 0),
adr_a => ram_st_sst_mosi_arr(0).address(c_mm_ram.adr_w - 1 downto 0),
rd_en_a => ram_st_sst_mosi_arr(0).rd,
@@ -315,7 +326,8 @@ begin
rst_b => dp_rst,
clk_b => dp_clk,
- wr_en_a => ram_st_sst_mosi_arr(1).wr, -- only for diagnostic purposes, typically statistics are read only
+ -- only for diagnostic purposes, typically statistics are read only
+ wr_en_a => ram_st_sst_mosi_arr(1).wr,
wr_dat_a => ram_st_sst_mosi_arr(1).wrdata(c_mm_ram.dat_w - 1 downto 0),
adr_a => ram_st_sst_mosi_arr(1).address(c_mm_ram.adr_w - 1 downto 0),
rd_en_a => ram_st_sst_mosi_arr(1).rd,
diff --git a/libraries/dsp/st/src/vhdl/st_xsq.vhd b/libraries/dsp/st/src/vhdl/st_xsq.vhd
index d09aeec6c15c1030957a64d11fcdfad686eddb13..d221771e9270d7ab54097d3e5bf55e7fe78c24dd 100644
--- a/libraries/dsp/st/src/vhdl/st_xsq.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xsq.vhd
@@ -46,7 +46,8 @@
library IEEE, common_lib, mm_lib, technology_lib, dp_lib;
use IEEE.std_logic_1164.all;
-use IEEE.math_real.all; -- for sim only
+-- for sim only
+use IEEE.math_real.all;
use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use common_lib.common_field_pkg.all;
@@ -57,9 +58,12 @@ entity st_xsq is
generic (
g_nof_signal_inputs : natural := 2;
g_nof_crosslets : natural := 1;
- g_in_data_w : natural := 18; -- width of the data to be accumulated
- g_stat_data_w : natural := 54; -- statistics accumulator width
- g_stat_data_sz : natural := 2 -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ -- width of the data to be accumulated
+ g_in_data_w : natural := 18;
+ -- statistics accumulator width
+ g_stat_data_w : natural := 54;
+ -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ g_stat_data_sz : natural := 2
);
port (
mm_rst : in std_logic;
@@ -68,8 +72,10 @@ entity st_xsq is
dp_clk : in std_logic;
-- Streaming
- in_a : in t_dp_sosi; -- Complex input data
- in_b : in t_dp_sosi; -- Complex input data
+ -- Complex input data
+ in_a : in t_dp_sosi;
+ -- Complex input data
+ in_b : in t_dp_sosi;
-- Memory Mapped
ram_st_xsq_mosi : in t_mem_mosi := c_mem_mosi_rst;
@@ -91,12 +97,14 @@ architecture str of st_xsq is
adr_w => c_nof_word_w,
dat_w => c_word_w,
nof_dat => c_nof_word,
- init_sl => '0'); -- MM side : sla_in, sla_out
+ -- MM side : sla_in, sla_out
+ init_sl => '0');
constant c_stat_ram : t_c_mem := (latency => 1,
adr_w => c_nof_stat_w,
dat_w => c_stat_word_w,
nof_dat => c_nof_statistics,
- init_sl => '0'); -- ST side : stat_mosi
+ -- ST side : stat_mosi
+ init_sl => '0');
signal pipe_in_a : t_dp_sosi;
signal pipe_in_b : t_dp_sosi;
@@ -232,7 +240,8 @@ begin
rst_b => dp_rst,
clk_b => dp_clk,
- wr_en_a => ram_st_xsq_mosi_arr(0).wr, -- only for diagnostic purposes, typically statistics are read only
+ -- only for diagnostic purposes, typically statistics are read only
+ wr_en_a => ram_st_xsq_mosi_arr(0).wr,
wr_dat_a => ram_st_xsq_mosi_arr(0).wrdata(c_mm_ram.dat_w - 1 downto 0),
adr_a => ram_st_xsq_mosi_arr(0).address(c_mm_ram.adr_w - 1 downto 0),
rd_en_a => ram_st_xsq_mosi_arr(0).rd,
@@ -261,7 +270,8 @@ begin
rst_b => dp_rst,
clk_b => dp_clk,
- wr_en_a => ram_st_xsq_mosi_arr(1).wr, -- only for diagnostic purposes, typically statistics are read only
+ -- only for diagnostic purposes, typically statistics are read only
+ wr_en_a => ram_st_xsq_mosi_arr(1).wr,
wr_dat_a => ram_st_xsq_mosi_arr(1).wrdata(c_mm_ram.dat_w - 1 downto 0),
adr_a => ram_st_xsq_mosi_arr(1).address(c_mm_ram.adr_w - 1 downto 0),
rd_en_a => ram_st_xsq_mosi_arr(1).rd,
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_arr.vhd b/libraries/dsp/st/src/vhdl/st_xsq_arr.vhd
index 0ab5d69614d34e897a0b9b51f2f4efbcfc19c15d..95cb10f20139b1c5c5ed18a3fd8afb1843df97f8 100644
--- a/libraries/dsp/st/src/vhdl/st_xsq_arr.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xsq_arr.vhd
@@ -37,9 +37,12 @@ entity st_xsq_arr is
g_nof_streams : natural := 1;
g_nof_crosslets : natural := 1;
g_nof_signal_inputs : natural := 2;
- g_in_data_w : natural := 18; -- width of the data to be accumulated
- g_stat_data_w : natural := 54; -- statistics accumulator width
- g_stat_data_sz : natural := 2 -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ -- width of the data to be accumulated
+ g_in_data_w : natural := 18;
+ -- statistics accumulator width
+ g_stat_data_w : natural := 54;
+ -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ g_stat_data_sz : natural := 2
);
port (
mm_rst : in std_logic;
@@ -48,8 +51,10 @@ entity st_xsq_arr is
dp_clk : in std_logic;
-- Streaming
- in_a_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Complex input data
- in_b_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Complex input data
+ -- Complex input data
+ in_a_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ -- Complex input data
+ in_b_arr : in t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-- Memory Mapped
ram_st_xsq_mosi : in t_mem_mosi;
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd b/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
index 8d4fc6a96510274df76bd64cf90481d7ff28a6cb..846a42a48df70ebc99449277b57fc576e1936388 100644
--- a/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
@@ -45,7 +45,8 @@ entity st_xsq_mm_to_dp is
port (
rst : in std_logic;
clk : in std_logic;
- in_sosi : in t_dp_sosi; -- sop used as start signal
+ -- sop used as start signal
+ in_sosi : in t_dp_sosi;
mm_mosi : out t_mem_mosi;
mm_miso_arr : in t_mem_miso_arr(g_nof_streams - 1 downto 0);
out_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0)
@@ -76,7 +77,8 @@ begin
out_sosi_arr(I) <= r.out_sosi_ctrl;
out_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(mm_miso_arr(I).rddata(g_dsp_data_w - 1 downto 0));
out_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(mm_miso_arr(I).rddata(c_nof_complex * g_dsp_data_w - 1 downto g_dsp_data_w));
- out_sosi_arr(I).valid <= mm_miso_arr(I).rdval; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
+ -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
+ out_sosi_arr(I).valid <= mm_miso_arr(I).rdval;
end loop;
end process;
@@ -103,7 +105,8 @@ begin
elsif r.busy = '1' then
-- continue with block
v.mm_mosi.rd := '1';
- v.mm_mosi.address := TO_MEM_ADDRESS(r.crosslets_index * g_nof_signal_inputs + r.in_b_index); -- streams iterate over in_b_index
+ -- streams iterate over in_b_index
+ v.mm_mosi.address := TO_MEM_ADDRESS(r.crosslets_index * g_nof_signal_inputs + r.in_b_index);
-- Indices counters to select data order
if r.in_b_index < g_nof_signal_inputs - 1 then
diff --git a/libraries/dsp/st/src/vhdl/st_xst.vhd b/libraries/dsp/st/src/vhdl/st_xst.vhd
index 33908871418a6a47deb48f6fa55d7110d7ee6de6..19a94803d4a762e300c2979f98ec5af8c26c987a 100644
--- a/libraries/dsp/st/src/vhdl/st_xst.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xst.vhd
@@ -41,9 +41,12 @@ entity st_xst is
g_nof_streams : natural := 1;
g_nof_crosslets : natural := 1;
g_nof_signal_inputs : natural := 2;
- g_in_data_w : natural := 18; -- width of the data to be accumulated
- g_stat_data_w : natural := 54; -- statistics accumulator width
- g_stat_data_sz : natural := 2 -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ -- width of the data to be accumulated
+ g_in_data_w : natural := 18;
+ -- statistics accumulator width
+ g_stat_data_w : natural := 54;
+ -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ g_stat_data_sz : natural := 2
);
port (
mm_rst : in std_logic;
diff --git a/libraries/dsp/st/tb/vhdl/tb_mmf_st_sst.vhd b/libraries/dsp/st/tb/vhdl/tb_mmf_st_sst.vhd
index 5001ac90f810382249f2e755040a27e3a4e2a9bb..1fd42b40074a0aa3590e960b95120d451d806d2f 100644
--- a/libraries/dsp/st/tb/vhdl/tb_mmf_st_sst.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_mmf_st_sst.vhd
@@ -46,12 +46,16 @@ use diag_lib.diag_pkg.all;
entity tb_mmf_st_sst is
generic(
- g_nof_stat : natural := 8; -- nof accumulators
+ -- nof accumulators
+ g_nof_stat : natural := 8;
g_xst_enable : boolean := true;
g_in_data_w : natural := 16;
- g_stat_data_w : natural := 56; -- statistics accumulator width
- g_stat_data_sz : natural := 2; -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
- g_nof_instances : natural := 4; -- The number of st_sst instances in parallel.
+ -- statistics accumulator width
+ g_stat_data_w : natural := 56;
+ -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ g_stat_data_sz : natural := 2;
+ -- The number of st_sst instances in parallel.
+ g_nof_instances : natural := 4;
g_nof_frames : natural := 1
);
end tb_mmf_st_sst;
diff --git a/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
index 72d545e3f59c53698d5e97273d7b6d6b9f714cb1..f865c918a0cef2933b5ba8d025be43cd28b065c3 100644
--- a/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
@@ -52,9 +52,12 @@ entity tb_mmp_st_histogram is
g_nof_instances : natural := 12;
g_data_w : natural := 14;
g_nof_bins : natural := 512;
- g_nof_data_per_sync : natural := 16384; -- g_nof_data_per_sync/g_nof_bins should be integer so counter data yields the same histogram in each bin
- g_nof_data_per_sync_diff : natural := 32 -- Use non-constant g_nof_data_per_sync: longer (+g_nof_data_per_sync_diff), shorter (-g_nof_data_per_sync_diff),
- ); -- longer, shorter, etc. E.g. LOFAR2 uses 200M+-512 samples per sync.
+ -- g_nof_data_per_sync/g_nof_bins should be integer so counter data yields the same histogram in each bin
+ g_nof_data_per_sync : natural := 16384;
+ -- Use non-constant g_nof_data_per_sync: longer (+g_nof_data_per_sync_diff), shorter (-g_nof_data_per_sync_diff),
+ g_nof_data_per_sync_diff : natural := 32
+ -- longer, shorter, etc. E.g. LOFAR2 uses 200M+-512 samples per sync.
+ );
end tb_mmp_st_histogram;
architecture tb of tb_mmp_st_histogram is
@@ -97,9 +100,11 @@ architecture tb of tb_mmp_st_histogram is
-- Automatic verification of RAM readout
----------------------------------------------------------------------------
-- Use these 4 signals to verify histogram by eye in the wave window
- signal histogram_data : natural; -- QuestaSim: Format->Analog
+ -- QuestaSim: Format->Analog
+ signal histogram_data : natural;
signal histogram_bin_unsigned : natural;
- signal histogram_bin_signed : integer; -- QuestaSim: Radix->Decimal
+ -- QuestaSim: Radix->Decimal
+ signal histogram_bin_signed : integer;
signal histogram_valid : std_logic;
signal sum_of_bins : natural;
@@ -138,12 +143,14 @@ begin
v_nof_data_per_sync := g_nof_data_per_sync;
if v_long_sync_interval then
v_nof_data_per_sync := g_nof_data_per_sync + g_nof_data_per_sync_diff;
- else -- Short interval
+ -- Short interval
+ else
v_nof_data_per_sync := g_nof_data_per_sync - g_nof_data_per_sync_diff;
end if;
v_sosi.sync := '1';
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_data_w - 1 downto 0)); -- wrap when >= 2**g_data_w
+ -- wrap when >= 2**g_data_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_data_w - 1 downto 0));
-- Generate a block of counter data
proc_dp_gen_block_data(g_data_w, TO_UINT(v_sosi.data), v_nof_data_per_sync, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn, dp_clk, stimuli_en, stimuli_src_in, stimuli_src_out);
v_long_sync_interval := not v_long_sync_interval;
@@ -237,9 +244,11 @@ begin
proc_common_wait_until_high(dp_clk, stimuli_src_out.sync);
for j in 0 to g_nof_bins - 1 loop
proc_common_wait_until_high(mm_clk, histogram_valid);
- if i = 0 then -- Sync period 0: we expect RAM to contain zeros
+ -- Sync period 0: we expect RAM to contain zeros
+ if i = 0 then
assert histogram_data = 0 report "RAM contains wrong bin count (expected 0, actual " & integer'image(histogram_data) & ")" severity ERROR;
- else -- Sync period 1 onwards
+ -- Sync period 1 onwards
+ else
v_expected_ram_content_counter := c_expected_ram_content_counter;
if ver_long_sync_interval and j = 0 then
-- Long sync interval: more counter values (counter wraps) so lowest bin has double the amount
@@ -251,12 +260,14 @@ begin
-- Check counter data: bin values remain the same every sync
assert histogram_data = v_expected_ram_content_counter report "RAM contains wrong bin count (expected " & integer'image(v_expected_ram_content_counter) & ", actual " & integer'image(histogram_data) & ")" severity ERROR;
end if;
- sum_of_bins <= sum_of_bins + histogram_data; -- Keep the sum of all bins
+ -- Keep the sum of all bins
+ sum_of_bins <= sum_of_bins + histogram_data;
proc_common_wait_some_cycles(mm_clk, 1);
end loop;
-- Check the sum of all bins
- if i > 0 then -- Skip sync 0 (histogram still all zeros)
+ -- Skip sync 0 (histogram still all zeros)
+ if i > 0 then
-- Account for g_nof_data_per_sync_diff
v_sum_of_bins := g_nof_data_per_sync - g_nof_data_per_sync_diff;
if ver_long_sync_interval then
@@ -266,7 +277,8 @@ begin
end if;
ver_long_sync_interval <= not ver_long_sync_interval;
end loop;
- verification_done <= '1'; -- We have blocking proc_common_wait_until_high procedures above so we need to know if we make it here.
+ -- We have blocking proc_common_wait_until_high procedures above so we need to know if we make it here.
+ verification_done <= '1';
wait;
end process;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_acc.vhd b/libraries/dsp/st/tb/vhdl/tb_st_acc.vhd
index 738ce81a41798b7c4b04e56a7fa3dedffaa503d8..5906dec8a1b04a2a526ea1a94425f959162b9d0b 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_acc.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_acc.vhd
@@ -44,11 +44,14 @@ architecture tb of tb_st_acc is
variable v_dat, v_acc, v_result : integer;
begin
-- Calculate expected result
- if in_val = '0' then -- hold: out_acc = in_acc
+ -- hold: out_acc = in_acc
+ if in_val = '0' then
v_result := TO_SINT(in_acc);
- elsif in_load = '1' then -- force: out_acc = 0 + in_dat
+ -- force: out_acc = 0 + in_dat
+ elsif in_load = '1' then
v_result := TO_SINT(in_dat);
- else -- accumulate: out_acc = in_acc + in_dat
+ -- accumulate: out_acc = in_acc + in_dat
+ else
v_result := TO_SINT(in_dat) + TO_SINT(in_acc);
end if;
-- Wrap to avoid warning: NUMERIC_STD.TO_SIGNED: vector truncated
@@ -87,7 +90,8 @@ begin
in_load <= '1';
in_val <= '1';
- for R in 0 to 2 loop -- Repeat some intervals marked by in_load = '1'
+ -- Repeat some intervals marked by in_load = '1'
+ for R in 0 to 2 loop
in_load <= '1';
-- All combinations
for I in - 2**(g_dat_w - 1) to 2**(g_dat_w - 1) - 1 loop
@@ -101,7 +105,8 @@ begin
-- in_val <= '1';
end loop;
end loop;
- in_load <= '1'; -- keep '1' to avoid further toggling of out_acc (in a real design this would safe power)
+ -- keep '1' to avoid further toggling of out_acc (in a real design this would safe power)
+ in_load <= '1';
in_val <= '0';
for I in 0 to 9 loop wait until rising_edge(clk); end loop;
tb_end <= '1';
@@ -123,16 +128,19 @@ begin
port map (
clk => clk,
clken => '1',
- in_load => in_load, -- start of accumulate period
+ -- start of accumulate period
+ in_load => in_load,
in_dat => in_dat,
- in_acc => in_acc, -- use only one accumulator
+ -- use only one accumulator
+ in_acc => in_acc,
in_val => in_val,
out_acc => out_acc,
out_val => out_val
);
in_acc <= out_acc when c_pipeline > 0 else
- out_acc when rising_edge(clk); -- if DUT has no pipeline, then register feedback to avoid combinatorial loop
+ -- if DUT has no pipeline, then register feedback to avoid combinatorial loop
+ out_acc when rising_edge(clk);
------------------------------------------------------------------------------
-- Verify
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_calc.vhd b/libraries/dsp/st/tb/vhdl/tb_st_calc.vhd
index 9442ccec2acbcc4d9e30fbb50184356b1d40ddb9..43504e204aed5e5e14f1bd1b97c32a946b934787 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_calc.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_calc.vhd
@@ -39,7 +39,8 @@ architecture tb of tb_st_calc is
constant c_out_adr_w : natural := ceil_log2(c_nof_stat);
constant c_gap_size : natural := 2**c_out_adr_w - c_nof_stat;
- constant c_nof_accum_per_sync : natural := 5; -- integration time
+ -- integration time
+ constant c_nof_accum_per_sync : natural := 5;
signal tb_end : std_logic := '0';
signal clk : std_logic := '0';
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
index 85a515726d869bd92817c23014cfa4368bd37658..0c05126969b11dd5f71bf4f90bd0e9d31c339583 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
@@ -72,14 +72,22 @@ use dp_lib.tb_dp_pkg.all;
entity tb_st_histogram is
generic(
- g_nof_sync : natural := 4; -- We're simulating at least 4 g_nof_sync so both RAMs are written and cleared twice.
- g_data_w : natural := 3; -- Determines maximum number of bins (2^g_data_w)
- g_nof_bins : natural := 8; -- Lower than or equal to 2^g_data_w. Higher is allowed but makes no sense.
- g_nof_data_per_sync : natural := 20; -- >= g_nof_bins. Determines max required RAM data width. e.g. 11b to store max bin count '1024'.
- g_stimuli_mode : string := "sine"; -- "counter", "dc", "sine" or "random"
- g_data_type : string := "signed"; -- use "signed" if g_stimuli_mode="sine"
- g_lock_sine : boolean := true -- TRUE to lock the sine wave to Sync - produces sparse histogram with low number of non-zero samples (occuring 2*c_sine_nof_periods)
- ); -- FALSE produces a dense histogram as the drifting sine wave hits more levels.
+ -- We're simulating at least 4 g_nof_sync so both RAMs are written and cleared twice.
+ g_nof_sync : natural := 4;
+ -- Determines maximum number of bins (2^g_data_w)
+ g_data_w : natural := 3;
+ -- Lower than or equal to 2^g_data_w. Higher is allowed but makes no sense.
+ g_nof_bins : natural := 8;
+ -- >= g_nof_bins. Determines max required RAM data width. e.g. 11b to store max bin count '1024'.
+ g_nof_data_per_sync : natural := 20;
+ -- "counter", "dc", "sine" or "random"
+ g_stimuli_mode : string := "sine";
+ -- use "signed" if g_stimuli_mode="sine"
+ g_data_type : string := "signed";
+ -- TRUE to lock the sine wave to Sync - produces sparse histogram with low number of non-zero samples (occuring 2*c_sine_nof_periods)
+ g_lock_sine : boolean := true
+ -- FALSE produces a dense histogram as the drifting sine wave hits more levels.
+ );
end tb_st_histogram;
architecture tb of tb_st_histogram is
@@ -87,7 +95,8 @@ architecture tb of tb_st_histogram is
-- Constants derived from generics
---------------------------------------------------------------------------
constant c_expected_ram_content_counter : natural := g_nof_data_per_sync / g_nof_bins;
- constant c_nof_levels_per_bin : natural := (2**g_data_w) / g_nof_bins; -- e.g. 2 values per bin if g_data_w=9 (512 levels) and g_nof_bins=256
+ -- e.g. 2 values per bin if g_data_w=9 (512 levels) and g_nof_bins=256
+ constant c_nof_levels_per_bin : natural := (2**g_data_w) / g_nof_bins;
constant c_ram_dat_w : natural := ceil_log2(g_nof_data_per_sync + 1);
constant c_ram_adr_w : natural := ceil_log2(g_nof_bins);
@@ -107,7 +116,8 @@ architecture tb of tb_st_histogram is
constant c_sine_amplitude : real := real((2**g_data_w) / 2 - 1);
constant c_sine_nof_periods : real := 1.0;
constant c_sine_nof_samples_per_period : real := real(g_nof_data_per_sync) / c_sine_nof_periods;
- constant c_sine_time_step_denom : real := sel_a_b(g_lock_sine, MATH_2_PI, 5.0); -- Use 5 instead of 2 pi to create unlocked, drifting sine wave
+ -- Use 5 instead of 2 pi to create unlocked, drifting sine wave
+ constant c_sine_time_step_denom : real := sel_a_b(g_lock_sine, MATH_2_PI, 5.0);
constant c_sine_time_step : real := c_sine_time_step_denom / c_sine_nof_samples_per_period;
signal stimuli_en : std_logic := '1';
@@ -115,7 +125,8 @@ architecture tb of tb_st_histogram is
signal nxt_stimuli_src_out : t_dp_sosi;
signal stimuli_src_in : t_dp_siso;
signal stimuli_count : real;
- signal stimuli_data : std_logic_vector(g_data_w - 1 downto 0); -- QuestaSim: Format->Analog, Radix->Decimal
+ -- QuestaSim: Format->Analog, Radix->Decimal
+ signal stimuli_data : std_logic_vector(g_data_w - 1 downto 0);
signal random_data : std_logic_vector(g_data_w - 1 downto 0);
signal stimuli_done : std_logic;
@@ -131,9 +142,11 @@ architecture tb of tb_st_histogram is
-- Automatic verification of RAM readout
----------------------------------------------------------------------------
-- Use these 4 signals to verify histogram by eye in the wave window
- signal histogram_data : natural; -- QuestaSim: Format->Analog
+ -- QuestaSim: Format->Analog
+ signal histogram_data : natural;
signal histogram_bin_unsigned : natural;
- signal histogram_bin_signed : integer; -- QuestaSim: Radix->Decimal
+ -- QuestaSim: Radix->Decimal
+ signal histogram_bin_signed : integer;
signal histogram_valid : std_logic;
signal sum_of_bins : natural;
@@ -163,7 +176,8 @@ begin
if g_stimuli_mode = "counter" then
for I in 0 to g_nof_sync - 1 loop
v_sosi.sync := '1';
- v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_data_w - 1 downto 0)); -- wrap when >= 2**g_data_w
+ -- wrap when >= 2**g_data_w
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_data_w - 1 downto 0));
proc_dp_gen_block_data(g_data_w, TO_UINT(v_sosi.data), g_nof_data_per_sync, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn, dp_clk, stimuli_en, stimuli_src_in, nxt_stimuli_src_out);
end loop;
end if;
@@ -172,10 +186,13 @@ begin
if g_stimuli_mode = "dc" then
nxt_stimuli_src_out.valid <= '1';
for I in 0 to g_nof_sync - 1 loop
- nxt_stimuli_src_out.data <= INCR_UVEC(stimuli_src_out.data, 1); -- all g_nof_data_per_sync cycles
- nxt_stimuli_src_out.sync <= '1'; -- cycle 0
+ -- all g_nof_data_per_sync cycles
+ nxt_stimuli_src_out.data <= INCR_UVEC(stimuli_src_out.data, 1);
+ -- cycle 0
+ nxt_stimuli_src_out.sync <= '1';
wait for 5 ns;
- for j in 1 to g_nof_data_per_sync - 1 loop -- cycles 1..g_nof_data_per_sync-1
+ -- cycles 1..g_nof_data_per_sync-1
+ for j in 1 to g_nof_data_per_sync - 1 loop
nxt_stimuli_src_out.sync <= '0';
wait for 5 ns;
end loop;
@@ -188,9 +205,11 @@ begin
nxt_stimuli_src_out.valid <= '1';
stimuli_count <= 0.0;
for I in 0 to g_nof_sync - 1 loop
- nxt_stimuli_src_out.sync <= '1'; -- cycle 0
+ -- cycle 0
+ nxt_stimuli_src_out.sync <= '1';
wait for 5 ns;
- for j in 1 to g_nof_data_per_sync - 1 loop -- cycles 1..g_nof_data_per_sync-1
+ -- cycles 1..g_nof_data_per_sync-1
+ for j in 1 to g_nof_data_per_sync - 1 loop
nxt_stimuli_src_out.sync <= '0';
nxt_stimuli_src_out.data(g_data_w - 1 downto 0) <= TO_SVEC( integer(round( c_sine_amplitude * sin(stimuli_count) )), g_data_w);
stimuli_count <= stimuli_count + c_sine_time_step;
@@ -204,12 +223,14 @@ begin
nxt_stimuli_src_out.valid <= '1';
for I in 0 to g_nof_sync - 1 loop
random_data <= (others => '0');
- nxt_stimuli_src_out.sync <= '1'; -- cycle 0
+ -- cycle 0
+ nxt_stimuli_src_out.sync <= '1';
wait for 5 ns;
for j in 1 to g_nof_data_per_sync - 1 loop
nxt_stimuli_src_out.sync <= '0';
random_data <= func_common_random(random_data);
- nxt_stimuli_src_out.data(g_data_w - 1 downto 0) <= random_data; -- all g_nof_data_per_sync cycles
+ -- all g_nof_data_per_sync cycles
+ nxt_stimuli_src_out.data(g_data_w - 1 downto 0) <= random_data;
wait for 5 ns;
end loop;
end loop;
@@ -309,15 +330,18 @@ begin
proc_common_wait_until_high(dp_clk, stimuli_src_out.sync);
for j in 0 to g_nof_bins - 1 loop
proc_common_wait_until_high(dp_clk, histogram_valid);
- if i = 0 then -- Sync period 0: we expect RAM to contain zeros
+ -- Sync period 0: we expect RAM to contain zeros
+ if i = 0 then
assert histogram_data = 0 report "RAM contains wrong bin count (expected 0, actual " & integer'image(histogram_data) & ")" severity ERROR;
- else -- Sync period 1 onwards
+ -- Sync period 1 onwards
+ else
if g_stimuli_mode = "counter" then
-- Counter data: bin values remain the same every sync
assert histogram_data = c_expected_ram_content_counter report "RAM contains wrong bin count (expected " & integer'image(c_expected_ram_content_counter) & ", actual " & integer'image(histogram_data) & ")" severity ERROR;
elsif g_stimuli_mode = "dc" then
-- DC data: DC level increments every sync
- if j = (i / c_nof_levels_per_bin) then -- Check bin address and account for multiple levels per bin
+ -- Check bin address and account for multiple levels per bin
+ if j = (i / c_nof_levels_per_bin) then
-- this address (j) should contain the DC level total count of this sync period (i)
assert histogram_data = g_nof_data_per_sync report "RAM contains wrong bin count (expected " & integer'image(g_nof_data_per_sync) & ", actual " & integer'image(histogram_data) & ")" severity ERROR;
else
@@ -326,16 +350,19 @@ begin
end if;
end if;
end if;
- sum_of_bins <= sum_of_bins + histogram_data; -- Keep the sum of all bins
+ -- Keep the sum of all bins
+ sum_of_bins <= sum_of_bins + histogram_data;
wait for 5 ns;
end loop;
-- Check the sum of all bins
- if i > 0 then -- Skip sync 0 (histogram still all zeros)
+ -- Skip sync 0 (histogram still all zeros)
+ if i > 0 then
assert sum_of_bins = g_nof_data_per_sync report "Sum of bins not equal to g_nof_data_per_sync (expected " & integer'image(g_nof_data_per_sync) & ", actual " & integer'image(sum_of_bins) & ")" severity ERROR;
end if;
end loop;
- verification_done <= '1'; -- We have blocking proc_common_wait_until_high procedures above so we need to know if we make it here.
+ -- We have blocking proc_common_wait_until_high procedures above so we need to know if we make it here.
+ verification_done <= '1';
wait;
end process;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd b/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd
index d3217150a2e8d5e477f2af44345446d975ded98a..51923e2012214d981388ac3bce90fa33d4e49d32 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd
@@ -55,8 +55,10 @@ entity tb_st_xsq is
g_nof_signal_inputs : natural := 12;
g_in_data_w : natural := 16;
g_nof_sync : natural := 3;
- g_stat_data_w : natural := 64; -- statistics accumulator width
- g_stat_data_sz : natural := 2; -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ -- statistics accumulator width
+ g_stat_data_w : natural := 64;
+ -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ g_stat_data_sz : natural := 2;
g_nof_block_per_sync : natural := 5;
g_nof_clk_per_blk : natural := 1024
);
@@ -145,11 +147,14 @@ begin
wait until rising_edge(dp_clk);
proc_common_wait_some_cycles(dp_clk, 7);
for I in 0 to g_nof_sync - 1 loop
- proc_dp_gen_block_data(c_rl, false, g_in_data_w, g_in_data_w, 0, v_re, v_im, c_nof_statistics, 0, 0, '1', "0", dp_clk, st_en, st_siso, st_sosi); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, false, g_in_data_w, g_in_data_w, 0, v_re, v_im, c_nof_statistics, 0, 0, '1', "0", dp_clk, st_en, st_siso, st_sosi);
st_sosi <= c_dp_sosi_rst;
proc_common_wait_some_cycles(dp_clk, c_gap_size);
- for J in 0 to g_nof_block_per_sync - 2 loop -- provide sop and eop for block reference
- proc_dp_gen_block_data(c_rl, false, g_in_data_w, g_in_data_w, 0, v_re, v_im, c_nof_statistics, 0, 0, '0', "0", dp_clk, st_en, st_siso, st_sosi); -- no sync
+ -- provide sop and eop for block reference
+ for J in 0 to g_nof_block_per_sync - 2 loop
+ -- no sync
+ proc_dp_gen_block_data(c_rl, false, g_in_data_w, g_in_data_w, 0, v_re, v_im, c_nof_statistics, 0, 0, '0', "0", dp_clk, st_en, st_siso, st_sosi);
st_sosi <= c_dp_sosi_rst;
proc_common_wait_some_cycles(dp_clk, c_gap_size);
end loop;
@@ -196,7 +201,8 @@ begin
proc_common_wait_until_high(mm_clk, ram_st_xsq_miso.rdval);
proc_common_wait_some_cycles(mm_clk, 2 * c_nof_statistics * c_nof_complex * g_stat_data_sz + 10);
for I in 0 to c_nof_statistics * c_nof_complex - 1 loop
- assert TO_SINT(st_xsq_out_arr(I * 2)) = c_expected_xsq(I) report "WRONG XSQ DATA" severity ERROR; -- Only read low part of statistic
+ -- Only read low part of statistic
+ assert TO_SINT(st_xsq_out_arr(I * 2)) = c_expected_xsq(I) report "WRONG XSQ DATA" severity ERROR;
end loop;
wait;
end process;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd b/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd
index 51fd62c3f9e3deddf3e3103fbf212f8a5e50b22c..4cd6f5f4b8edcb5828ba2fe4b3d7fc1843825d8a 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd
@@ -56,8 +56,10 @@ entity tb_st_xst is
g_nof_signal_inputs : natural := 12;
g_in_data_w : natural := 16;
g_nof_sync : natural := 3;
- g_stat_data_w : natural := 64; -- statistics accumulator width
- g_stat_data_sz : natural := 2; -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ -- statistics accumulator width
+ g_stat_data_w : natural := 64;
+ -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ g_stat_data_sz : natural := 2;
g_nof_block_per_sync : natural := 5;
g_nof_clk_per_blk : natural := 1024
);
@@ -80,7 +82,8 @@ architecture tb of tb_st_xst is
adr_w => ceil_log2(c_block_size),
dat_w => c_nof_complex * g_in_data_w,
nof_dat => c_block_size,
- init_sl => '0'); -- MM side : sla_in, sla_out
+ -- MM side : sla_in, sla_out
+ init_sl => '0');
type t_random_in_2arr is array (integer range <>) of t_integer_arr(0 to c_block_size-1);
type t_xsq_2arr is array (integer range <>) of t_integer_arr(0 to c_nof_statistics * c_nof_complex - 1);
@@ -191,7 +194,8 @@ begin
proc_common_wait_some_cycles(dp_clk, 1);
in_sosi <= c_dp_sosi_rst;
proc_common_wait_some_cycles(dp_clk, g_nof_clk_per_blk - 1);
- for J in 0 to g_nof_block_per_sync - 2 loop -- provide sop and eop for block reference
+ -- provide sop and eop for block reference
+ for J in 0 to g_nof_block_per_sync - 2 loop
in_sosi.sop <= '1';
in_sosi.eop <= '1';
proc_common_wait_some_cycles(dp_clk, 1);
@@ -214,7 +218,8 @@ begin
proc_common_wait_some_cycles(mm_clk, 2 * c_total_mem_size + 10);
for M in 0 to g_nof_streams - 1 loop
for I in 0 to c_nof_statistics * c_nof_complex - 1 loop
- assert TO_SINT(st_xsq_out_2arr(M)(g_stat_data_sz * I)) = expected_xsq_2arr(M)(I) report "WRONG XSQ DATA" severity ERROR; -- Only read low part of statistic
+ -- Only read low part of statistic
+ assert TO_SINT(st_xsq_out_2arr(M)(g_stat_data_sz * I)) = expected_xsq_2arr(M)(I) report "WRONG XSQ DATA" severity ERROR;
end loop;
end loop;
wait;
diff --git a/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd
index 304a91ab0f34fff97ade1b2d9d03dd07f1284bf5..b638c26748fdc6bc7f8bd46d931a21130f5f9d79 100644
--- a/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd
@@ -36,7 +36,8 @@ entity tb_tb_st_histogram is
end tb_tb_st_histogram;
architecture tb of tb_tb_st_histogram is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_nof_sync : NATURAL := 4;
-- g_data_w : NATURAL := 8;
@@ -47,11 +48,16 @@ begin
-- g_lock_sine : BOOLEAN := TRUE
-- Counter data
-u_tb_st_histogram_0 : entity work.tb_st_histogram generic map ( 7, 8, 256, 1024, "counter", "unsigned"); -- Incoming data repeats 1024/ 256= 4 times: Bin count = 4
-u_tb_st_histogram_1 : entity work.tb_st_histogram generic map ( 6, 10, 256, 4096, "counter", "unsigned"); -- Incoming data repeats 4096/ 256=16 times: Bin count = 16
-u_tb_st_histogram_2 : entity work.tb_st_histogram generic map ( 5, 12, 512, 4096, "counter", "unsigned"); -- Incoming data repeats 4096/ 512= 8 times: Bin count = 8
-u_tb_st_histogram_3 : entity work.tb_st_histogram generic map ( 4, 13, 1024, 8192, "counter", "unsigned"); -- Incoming data repeats 8192/1024= 8 times: Bin count = 8
-u_tb_st_histogram_4 : entity work.tb_st_histogram generic map (20, 6, 64, 128, "counter", "unsigned"); -- Incoming data repeats 128/ 64= 2 times: Bin count = 2
+-- Incoming data repeats 1024/ 256= 4 times: Bin count = 4
+u_tb_st_histogram_0 : entity work.tb_st_histogram generic map ( 7, 8, 256, 1024, "counter", "unsigned");
+-- Incoming data repeats 4096/ 256=16 times: Bin count = 16
+u_tb_st_histogram_1 : entity work.tb_st_histogram generic map ( 6, 10, 256, 4096, "counter", "unsigned");
+-- Incoming data repeats 4096/ 512= 8 times: Bin count = 8
+u_tb_st_histogram_2 : entity work.tb_st_histogram generic map ( 5, 12, 512, 4096, "counter", "unsigned");
+-- Incoming data repeats 8192/1024= 8 times: Bin count = 8
+u_tb_st_histogram_3 : entity work.tb_st_histogram generic map ( 4, 13, 1024, 8192, "counter", "unsigned");
+-- Incoming data repeats 128/ 64= 2 times: Bin count = 2
+u_tb_st_histogram_4 : entity work.tb_st_histogram generic map (20, 6, 64, 128, "counter", "unsigned");
-- DC signal
u_tb_st_histogram_5 : entity work.tb_st_histogram generic map ( 2, 8, 256, 1000, "dc", "unsigned");
diff --git a/libraries/dsp/st/tb/vhdl/tb_tb_st_xsq.vhd b/libraries/dsp/st/tb/vhdl/tb_tb_st_xsq.vhd
index 7317c264fab4a8273c24259c660c429807cea146..6a98da64e9090636b8b07e4ff7ef1b78733446cd 100644
--- a/libraries/dsp/st/tb/vhdl/tb_tb_st_xsq.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_tb_st_xsq.vhd
@@ -36,7 +36,8 @@ end tb_tb_st_xsq;
architecture tb of tb_tb_st_xsq is
constant c_nof_sync : natural := 3;
constant c_dsp_data_w : natural := 16;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- GENERICS:
-- g_nof_crosslets : NATURAL := 2;
@@ -49,5 +50,6 @@ begin
-- g_nof_clk_per_blk : NATURAL := 1024
u_sdp : entity work.tb_st_xsq generic map (1, 12, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024);
- u_max : entity work.tb_st_xsq generic map (16, 8, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024); -- g_nof_crosslets * g_nof_signal_inputs**2 = 16 * 8 * 8 = 1024 = g_nof_clk_per_blk
+ -- g_nof_crosslets * g_nof_signal_inputs**2 = 16 * 8 * 8 = 1024 = g_nof_clk_per_blk
+ u_max : entity work.tb_st_xsq generic map (16, 8, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024);
end tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_tb_st_xst.vhd b/libraries/dsp/st/tb/vhdl/tb_tb_st_xst.vhd
index 956b184c80dd2d336ce12df36408f510b47dd780..86d8b52f7881baf5985f3680b9ba4d9d54d723df 100644
--- a/libraries/dsp/st/tb/vhdl/tb_tb_st_xst.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_tb_st_xst.vhd
@@ -36,7 +36,8 @@ end tb_tb_st_xst;
architecture tb of tb_tb_st_xst is
constant c_nof_sync : natural := 3;
constant c_dsp_data_w : natural := 16;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- GENERICS:
-- g_nof_streams : NATURAL := 9;
@@ -53,5 +54,6 @@ begin
u_sdp_one : entity work.tb_st_xst generic map (1, 1, 12, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024);
u_sdp_mult_crosslets : entity work.tb_st_xst generic map (9, 7, 12, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024);
-- Note: u_max shows that the dut will skip sync periods if nof_statistics is not < g_nof_clk_per_blk
- u_max : entity work.tb_st_xst generic map (2, 16, 8, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024); -- g_nof_crosslets * g_nof_signal_inputs**2 = 16 * 8 * 8 = 1024 = g_nof_clk_per_blk
+ -- g_nof_crosslets * g_nof_signal_inputs**2 = 16 * 8 * 8 = 1024 = g_nof_clk_per_blk
+ u_max : entity work.tb_st_xst generic map (2, 16, 8, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024);
end tb;
diff --git a/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd b/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd
index 0813eb85dc3b7d3baffc5a5ab3718da786f20607..323fecc98aef9dd87c45f31e9b45c78967a9c2a4 100644
--- a/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd
+++ b/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd
@@ -91,7 +91,8 @@ architecture tb of tb_tb_verify_pfb_wg is
constant c_fil_kaiser_18b : string := "data/Coefficient_16KKaiser_18b_1wb";
constant c_fil_kaiser_20b : string := "data/Coefficient_16KKaiser_20b_1wb";
- signal tb_end : std_logic := '0'; -- tb_end is used to end a tb if it cannot end itself, but is not needed for tb_verify_pfb_wg
+ -- tb_end is used to end a tb if it cannot end itself, but is not needed for tb_verify_pfb_wg
+ signal tb_end : std_logic := '0';
-- however, do declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
constant c_gen_ref : boolean := true;
@@ -179,7 +180,8 @@ begin
-- . . . . . . . . . . . . . . . . g_fft_guard_w
-- . . . . . . . . . . . . . . . . . g_switch_en
-- . . . . . . . . . . . . . . . . . .
-gen_ref : if c_gen_ref generate -- . . . . . . . . . . . . . . . . . .
+-- . . . . . . . . . . . . . . . . . .
+gen_ref : if c_gen_ref generate
-- WPFB . . . . . . . . . . . . . . . . . .
--u_apertif : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1001, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 8, 16, 18, 1, 18, 2, '0');
--u_lts_2020_11_23 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1002, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 1, 18, 2, '0');
@@ -195,10 +197,13 @@ gen_ref : if c_gen_ref generate -- . . . . . . . .
--u_wpfb_stage23 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1010, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 23, 1, '0');
--u_wpfb_stage24 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1011, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 24, 1, '0');
-- c_twiddle_w = 18
- u_wpfb_lofar2_subbands_lts_2021 : entity work.tb_verify_pfb_wg generic map (1012, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0'); -- = u_wpfb_stage22
+ -- = u_wpfb_stage22
+ u_wpfb_lofar2_subbands_lts_2021 : entity work.tb_verify_pfb_wg generic map (1012, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0');
-- c_twiddle_w = 20
- u_wpfb_lofar2_subbands_dts_18b : entity work.tb_verify_pfb_wg generic map (1013, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 18, 1, 24, 1, '0'); -- = u_2000
- u_wpfb_lofar2_subbands_dts_19b : entity work.tb_verify_pfb_wg generic map (1014, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 19, 1, 24, 1, '0'); -- = u_2001
+ -- = u_2000
+ u_wpfb_lofar2_subbands_dts_18b : entity work.tb_verify_pfb_wg generic map (1013, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 18, 1, 24, 1, '0');
+ -- = u_2001
+ u_wpfb_lofar2_subbands_dts_19b : entity work.tb_verify_pfb_wg generic map (1014, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 19, 1, 24, 1, '0');
-- Results:
-- Coeffs16384Kaiser-quant
@@ -268,7 +273,8 @@ gen_g_fil_backoff_w_1 : if c_gen_g_fil_backoff_w_1 generate
end generate;
gen_vary_g_fil_backoff_w : if c_gen_vary_g_fil_backoff_w generate
- u_1000 : entity work.tb_verify_pfb_wg generic map (1000, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0'); -- = u_wpfb_stage22
+ -- = u_wpfb_stage22
+ u_1000 : entity work.tb_verify_pfb_wg generic map (1000, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0');
u_1001 : entity work.tb_verify_pfb_wg generic map (1001, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 22, 0, '0');
u_1002 : entity work.tb_verify_pfb_wg generic map (1002, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 18, 19, 0, 22, 0, '0');
u_1003 : entity work.tb_verify_pfb_wg generic map (1003, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 18, 19, 1, 22, 0, '0');
@@ -281,7 +287,8 @@ end generate;
gen_vary_g_fft_out_dat_w : if c_gen_vary_g_fft_out_dat_w generate
-- WPFB
- u_100 : entity work.tb_verify_pfb_wg generic map (100, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0'); -- = u_wpfb_stage22
+ -- = u_wpfb_stage22
+ u_100 : entity work.tb_verify_pfb_wg generic map (100, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0');
u_101 : entity work.tb_verify_pfb_wg generic map (101, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 19, 0, 22, 1, '0');
u_102 : entity work.tb_verify_pfb_wg generic map (102, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 20, 0, 22, 1, '0');
-- PFB2
@@ -301,9 +308,12 @@ gen_vary_g_fft_out_dat_w : if c_gen_vary_g_fft_out_dat_w generate
end generate;
gen_2020_jan_18 : if c_gen_2020_jan_18 generate
- u_200 : entity work.tb_verify_pfb_wg generic map (200, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 1, 18, 2, '0'); -- = u_lts_2020_11_23
- u_201 : entity work.tb_verify_pfb_wg generic map (201, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_204 : entity work.tb_verify_pfb_wg generic map (204, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0'); -- = u_wpfb_stage20
+ -- = u_lts_2020_11_23
+ u_200 : entity work.tb_verify_pfb_wg generic map (200, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 1, 18, 2, '0');
+ -- = u_wpfb_stage18
+ u_201 : entity work.tb_verify_pfb_wg generic map (201, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage20
+ u_204 : entity work.tb_verify_pfb_wg generic map (204, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0');
-- Results:
-- Table C: PFB processing gain for APERTIF WPFB quick improvements
@@ -320,22 +330,38 @@ gen_2020_jan_18 : if c_gen_2020_jan_18 generate
end generate;
gen_vary_wg_integer_freq : if c_gen_vary_wg_integer_freq generate
- u_2001 : entity work.tb_verify_pfb_wg generic map (2001, "WPFB", 1.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2002 : entity work.tb_verify_pfb_wg generic map (2002, "WPFB", 2.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2003 : entity work.tb_verify_pfb_wg generic map (2003, "WPFB", 3.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2004 : entity work.tb_verify_pfb_wg generic map (2004, "WPFB", 4.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2008 : entity work.tb_verify_pfb_wg generic map (2008, "WPFB", 8.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2016 : entity work.tb_verify_pfb_wg generic map (2016, "WPFB", 16.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2032 : entity work.tb_verify_pfb_wg generic map (2032, "WPFB", 32.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2037 : entity work.tb_verify_pfb_wg generic map (2037, "WPFB", 37.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2061 : entity work.tb_verify_pfb_wg generic map (2061, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2064 : entity work.tb_verify_pfb_wg generic map (2064, "WPFB", 64.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2117 : entity work.tb_verify_pfb_wg generic map (2117, "WPFB",117.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2128 : entity work.tb_verify_pfb_wg generic map (2128, "WPFB",128.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2256 : entity work.tb_verify_pfb_wg generic map (2256, "WPFB",256.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2257 : entity work.tb_verify_pfb_wg generic map (2257, "WPFB",257.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2373 : entity work.tb_verify_pfb_wg generic map (2373, "WPFB",373.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2503 : entity work.tb_verify_pfb_wg generic map (2503, "WPFB",503.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ -- = u_wpfb_stage18
+ u_2001 : entity work.tb_verify_pfb_wg generic map (2001, "WPFB", 1.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2002 : entity work.tb_verify_pfb_wg generic map (2002, "WPFB", 2.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2003 : entity work.tb_verify_pfb_wg generic map (2003, "WPFB", 3.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2004 : entity work.tb_verify_pfb_wg generic map (2004, "WPFB", 4.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2008 : entity work.tb_verify_pfb_wg generic map (2008, "WPFB", 8.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2016 : entity work.tb_verify_pfb_wg generic map (2016, "WPFB", 16.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2032 : entity work.tb_verify_pfb_wg generic map (2032, "WPFB", 32.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2037 : entity work.tb_verify_pfb_wg generic map (2037, "WPFB", 37.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2061 : entity work.tb_verify_pfb_wg generic map (2061, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2064 : entity work.tb_verify_pfb_wg generic map (2064, "WPFB", 64.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2117 : entity work.tb_verify_pfb_wg generic map (2117, "WPFB",117.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2128 : entity work.tb_verify_pfb_wg generic map (2128, "WPFB",128.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2256 : entity work.tb_verify_pfb_wg generic map (2256, "WPFB",256.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2257 : entity work.tb_verify_pfb_wg generic map (2257, "WPFB",257.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2373 : entity work.tb_verify_pfb_wg generic map (2373, "WPFB",373.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_2503 : entity work.tb_verify_pfb_wg generic map (2503, "WPFB",503.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
-- Results:
-- g_subband_index_a
@@ -361,29 +387,50 @@ gen_vary_wg_fractional_freq : if c_gen_vary_wg_fractional_freq generate
-- Use fractions that fit integer number of periods in sync interval c_N_blk = c_wpfb.nof_blk_per_sync = 10, so c_N_blk*fraction must be integer, to have stable SST value
-- Need to use g_amplitude_a = 0.9 ~< 0.95 to avoid overflow in PFS output, that occurs for some fractional g_subband_index_a
-- WG freq 60.0
- u_600 : entity work.tb_verify_pfb_wg generic map (600, "WPFB", 60.0, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_601 : entity work.tb_verify_pfb_wg generic map (601, "WPFB", 60.1, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_602 : entity work.tb_verify_pfb_wg generic map (602, "WPFB", 60.2, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_603 : entity work.tb_verify_pfb_wg generic map (603, "WPFB", 60.3, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_604 : entity work.tb_verify_pfb_wg generic map (604, "WPFB", 60.4, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_605 : entity work.tb_verify_pfb_wg generic map (605, "WPFB", 60.5, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_606 : entity work.tb_verify_pfb_wg generic map (606, "WPFB", 60.6, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_607 : entity work.tb_verify_pfb_wg generic map (607, "WPFB", 60.7, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_608 : entity work.tb_verify_pfb_wg generic map (608, "WPFB", 60.8, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_609 : entity work.tb_verify_pfb_wg generic map (609, "WPFB", 60.9, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ -- = u_wpfb_stage18
+ u_600 : entity work.tb_verify_pfb_wg generic map (600, "WPFB", 60.0, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_601 : entity work.tb_verify_pfb_wg generic map (601, "WPFB", 60.1, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_602 : entity work.tb_verify_pfb_wg generic map (602, "WPFB", 60.2, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_603 : entity work.tb_verify_pfb_wg generic map (603, "WPFB", 60.3, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_604 : entity work.tb_verify_pfb_wg generic map (604, "WPFB", 60.4, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_605 : entity work.tb_verify_pfb_wg generic map (605, "WPFB", 60.5, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_606 : entity work.tb_verify_pfb_wg generic map (606, "WPFB", 60.6, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_607 : entity work.tb_verify_pfb_wg generic map (607, "WPFB", 60.7, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_608 : entity work.tb_verify_pfb_wg generic map (608, "WPFB", 60.8, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_609 : entity work.tb_verify_pfb_wg generic map (609, "WPFB", 60.9, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
-- WG freq 61.0
- u_610 : entity work.tb_verify_pfb_wg generic map (610, "WPFB", 61.0, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18 freq 61
- u_611 : entity work.tb_verify_pfb_wg generic map (611, "WPFB", 61.1, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_612 : entity work.tb_verify_pfb_wg generic map (612, "WPFB", 61.2, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_613 : entity work.tb_verify_pfb_wg generic map (613, "WPFB", 61.3, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_614 : entity work.tb_verify_pfb_wg generic map (614, "WPFB", 61.4, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_615 : entity work.tb_verify_pfb_wg generic map (615, "WPFB", 61.5, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_616 : entity work.tb_verify_pfb_wg generic map (616, "WPFB", 61.6, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_617 : entity work.tb_verify_pfb_wg generic map (617, "WPFB", 61.7, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_618 : entity work.tb_verify_pfb_wg generic map (618, "WPFB", 61.8, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_619 : entity work.tb_verify_pfb_wg generic map (619, "WPFB", 61.9, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ -- = u_wpfb_stage18 freq 61
+ u_610 : entity work.tb_verify_pfb_wg generic map (610, "WPFB", 61.0, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_611 : entity work.tb_verify_pfb_wg generic map (611, "WPFB", 61.1, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_612 : entity work.tb_verify_pfb_wg generic map (612, "WPFB", 61.2, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_613 : entity work.tb_verify_pfb_wg generic map (613, "WPFB", 61.3, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_614 : entity work.tb_verify_pfb_wg generic map (614, "WPFB", 61.4, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_615 : entity work.tb_verify_pfb_wg generic map (615, "WPFB", 61.5, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_616 : entity work.tb_verify_pfb_wg generic map (616, "WPFB", 61.6, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_617 : entity work.tb_verify_pfb_wg generic map (617, "WPFB", 61.7, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_618 : entity work.tb_verify_pfb_wg generic map (618, "WPFB", 61.8, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_619 : entity work.tb_verify_pfb_wg generic map (619, "WPFB", 61.9, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
-- WG freq 62.0
- u_620 : entity work.tb_verify_pfb_wg generic map (620, "WPFB", 62.0, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ -- = u_wpfb_stage18
+ u_620 : entity work.tb_verify_pfb_wg generic map (620, "WPFB", 62.0, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
-- Note>:
-- . For fractional subband frequencies the WG can only generate the average frequency, due to limited period accuracy of WG. This causes
@@ -417,19 +464,25 @@ end generate;
gen_vary_g_fft_stage_dat_w : if c_gen_vary_g_fft_stage_dat_w generate
-- g_internal_dat_w = constant
-- WPFB
- u_300 : entity work.tb_verify_pfb_wg generic map (300, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ -- = u_wpfb_stage18
+ u_300 : entity work.tb_verify_pfb_wg generic map (300, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
u_301 : entity work.tb_verify_pfb_wg generic map (301, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 19, 1, '0');
- u_302 : entity work.tb_verify_pfb_wg generic map (302, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0'); -- = u_wpfb_stage20
+ -- = u_wpfb_stage20
+ u_302 : entity work.tb_verify_pfb_wg generic map (302, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0');
u_303 : entity work.tb_verify_pfb_wg generic map (303, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 21, 1, '0');
- u_304 : entity work.tb_verify_pfb_wg generic map (304, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0'); -- = u_wpfb_stage22
- u_305 : entity work.tb_verify_pfb_wg generic map (305, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 23, 1, '0'); -- = u_wpfb_stage23
- u_306 : entity work.tb_verify_pfb_wg generic map (306, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 24, 1, '0'); -- = u_wpfb_stage24
+ -- = u_wpfb_stage22
+ u_304 : entity work.tb_verify_pfb_wg generic map (304, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0');
+ -- = u_wpfb_stage23
+ u_305 : entity work.tb_verify_pfb_wg generic map (305, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 23, 1, '0');
+ -- = u_wpfb_stage24
+ u_306 : entity work.tb_verify_pfb_wg generic map (306, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 24, 1, '0');
u_307 : entity work.tb_verify_pfb_wg generic map (307, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 25, 1, '0');
-- PFB2
u_310 : entity work.tb_verify_pfb_wg generic map (310, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 18, 0, '0');
u_311 : entity work.tb_verify_pfb_wg generic map (311, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 19, 0, '0');
- u_312 : entity work.tb_verify_pfb_wg generic map (312, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 20, 0, '0'); -- = u_lofar1_14b
+ -- = u_lofar1_14b
+ u_312 : entity work.tb_verify_pfb_wg generic map (312, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 20, 0, '0');
u_313 : entity work.tb_verify_pfb_wg generic map (313, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 21, 0, '0');
u_314 : entity work.tb_verify_pfb_wg generic map (314, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 22, 0, '0');
u_315 : entity work.tb_verify_pfb_wg generic map (315, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 23, 0, '0');
@@ -437,7 +490,8 @@ gen_vary_g_fft_stage_dat_w : if c_gen_vary_g_fft_stage_dat_w generate
u_317 : entity work.tb_verify_pfb_wg generic map (317, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 25, 0, '0');
-- WPFB only FFT
- u_320 : entity work.tb_verify_pfb_wg generic map (320, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ -- = u_wpfb_stage18
+ u_320 : entity work.tb_verify_pfb_wg generic map (320, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 18, 1, '0');
u_321 : entity work.tb_verify_pfb_wg generic map (321, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 19, 1, '0');
u_322 : entity work.tb_verify_pfb_wg generic map (322, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 20, 1, '0');
u_323 : entity work.tb_verify_pfb_wg generic map (323, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 21, 1, '0');
@@ -458,7 +512,8 @@ gen_vary_g_fft_stage_dat_w : if c_gen_vary_g_fft_stage_dat_w generate
-- g_internal_dat_w = incrementing with g_fft_stage_dat_w
-- WPFB
- u_340 : entity work.tb_verify_pfb_wg generic map (340, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ -- = u_wpfb_stage18
+ u_340 : entity work.tb_verify_pfb_wg generic map (340, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
u_341 : entity work.tb_verify_pfb_wg generic map (341, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 19, 1, '0');
u_342 : entity work.tb_verify_pfb_wg generic map (342, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 19, 18, 0, 20, 1, '0');
u_343 : entity work.tb_verify_pfb_wg generic map (343, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 20, 18, 0, 21, 1, '0');
@@ -505,7 +560,8 @@ gen_vary_g_fil_in_dat_w : if c_gen_vary_g_fil_in_dat_w generate
u_403 : entity work.tb_verify_pfb_wg generic map (403, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 11, 17, 18, 0, 20, 1, '0');
u_404 : entity work.tb_verify_pfb_wg generic map (404, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 12, 17, 18, 0, 20, 1, '0');
u_405 : entity work.tb_verify_pfb_wg generic map (405, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 13, 17, 18, 0, 20, 1, '0');
- u_406 : entity work.tb_verify_pfb_wg generic map (406, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0'); -- u_wpfb_stage20
+ -- u_wpfb_stage20
+ u_406 : entity work.tb_verify_pfb_wg generic map (406, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0');
u_410 : entity work.tb_verify_pfb_wg generic map (410, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 8, 18, 18, 0, 20, 0, '0');
u_411 : entity work.tb_verify_pfb_wg generic map (411, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 9, 18, 18, 0, 20, 0, '0');
@@ -513,7 +569,8 @@ gen_vary_g_fil_in_dat_w : if c_gen_vary_g_fil_in_dat_w generate
u_413 : entity work.tb_verify_pfb_wg generic map (413, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 11, 18, 18, 0, 20, 0, '0');
u_414 : entity work.tb_verify_pfb_wg generic map (414, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 12, 18, 18, 0, 20, 0, '0');
u_415 : entity work.tb_verify_pfb_wg generic map (415, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 13, 18, 18, 0, 20, 0, '0');
- u_416 : entity work.tb_verify_pfb_wg generic map (416, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 20, 0, '0'); -- u_lofar1_14b
+ -- u_lofar1_14b
+ u_416 : entity work.tb_verify_pfb_wg generic map (416, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 20, 0, '0');
u_420 : entity work.tb_verify_pfb_wg generic map (420, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 8, 17, 18, 0, 20, 1, '0');
u_421 : entity work.tb_verify_pfb_wg generic map (421, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 9, 17, 18, 0, 20, 1, '0');
@@ -550,13 +607,20 @@ end generate;
-- 2021_jan_11
gen_vary_g_amplitude_a : if c_gen_vary_g_amplitude_a generate
- u_760 : entity work.tb_verify_pfb_wg generic map (760, "WPFB", 61.0, 61.0, 1.0 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18, 1.0
- u_761 : entity work.tb_verify_pfb_wg generic map (761, "WPFB", 61.0, 61.0, 0.5 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_762 : entity work.tb_verify_pfb_wg generic map (762, "WPFB", 61.0, 61.0, 0.25 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_763 : entity work.tb_verify_pfb_wg generic map (763, "WPFB", 61.0, 61.0, 0.125 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_764 : entity work.tb_verify_pfb_wg generic map (764, "WPFB", 61.0, 61.0, 0.0625 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_765 : entity work.tb_verify_pfb_wg generic map (765, "WPFB", 61.0, 61.0, 0.03125 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_766 : entity work.tb_verify_pfb_wg generic map (766, "WPFB", 61.0, 61.0, 0.015625, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ -- = u_wpfb_stage18, 1.0
+ u_760 : entity work.tb_verify_pfb_wg generic map (760, "WPFB", 61.0, 61.0, 1.0 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_761 : entity work.tb_verify_pfb_wg generic map (761, "WPFB", 61.0, 61.0, 0.5 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_762 : entity work.tb_verify_pfb_wg generic map (762, "WPFB", 61.0, 61.0, 0.25 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_763 : entity work.tb_verify_pfb_wg generic map (763, "WPFB", 61.0, 61.0, 0.125 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_764 : entity work.tb_verify_pfb_wg generic map (764, "WPFB", 61.0, 61.0, 0.0625 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_765 : entity work.tb_verify_pfb_wg generic map (765, "WPFB", 61.0, 61.0, 0.03125 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ -- = u_wpfb_stage18
+ u_766 : entity work.tb_verify_pfb_wg generic map (766, "WPFB", 61.0, 61.0, 0.015625, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
--Results:
--tb-761 . wpfb_measured_proc_gain_a_dB = 6.11 [dB]
--tb-762 . wpfb_measured_proc_gain_a_dB = 6.15 [dB]
@@ -569,8 +633,10 @@ end generate;
gen_vary_c_twiddle_w : if c_gen_vary_c_twiddle_w generate
-- WPFB only FFT
- u_0 : entity work.tb_verify_pfb_wg generic map (0, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 22, 1, '0'); -- = u_324
- u_1 : entity work.tb_verify_pfb_wg generic map (1, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 24, 1, '0'); -- = u_326
+ -- = u_324
+ u_0 : entity work.tb_verify_pfb_wg generic map (0, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 22, 1, '0');
+ -- = u_326
+ u_1 : entity work.tb_verify_pfb_wg generic map (1, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 24, 1, '0');
-- Rerun the simulation per c_twiddle_w setting ## by first manually doing:
-- > cp libraries/dsp/rTwoSDF/src/vhdl/pkg/twiddlesPkg_w##.vhd libraries/dsp/rTwoSDF/src/vhdl/twiddlesPkg.vhd
diff --git a/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd b/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd
index efc4f67069d6e2ab1d606b109eaf3d2b2a5ea1b0..d6f57a4c060da856f4df002d91c4b28fa9b0d79b 100644
--- a/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd
+++ b/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd
@@ -62,18 +62,22 @@ use pft2_lib.pft_pkg.all;
entity tb_verify_pfb_response is
generic (
- g_tb_index : natural := 0; -- use g_tb_index to identify and separate print_str() loggings from multi tb
+ -- use g_tb_index to identify and separate print_str() loggings from multi tb
+ g_tb_index : natural := 0;
-- PFB
- g_sel_pfb : string := "WPFB"; -- "WPFB" for APERTIF PFB, "PFB2" for LOFAR1 PBF
+ -- "WPFB" for APERTIF PFB, "PFB2" for LOFAR1 PBF
+ g_sel_pfb : string := "WPFB";
--g_sel_pfb : STRING := "PFB2";
-- LOFAR2 WPFB
- g_fil_coefs_file_prefix : string := "data/Coeffs16384Kaiser-quant_1wb"; -- PFIR coefficients file access
+ -- PFIR coefficients file access
+ g_fil_coefs_file_prefix : string := "data/Coeffs16384Kaiser-quant_1wb";
--g_fil_coefs_file_prefix : STRING := "data/run_pfir_coeff_m_bypass_16taps_1024points_16b_1wb"; -- bypass PFIR
--g_fil_coefs_file_prefix : STRING := "data/run_pfir_coeff_m_fircls1_16taps_1024points_16b_1wb"; -- g_fil_coef_dat_w = 16 bit
-- LOFAR1 PFB2
- g_pfir_coefs_file : string := c_pfs_coefs_file -- PFB2 "data/pfs_coefsbuf_1024.hex" = Coeffs16384Kaiser-quant.dat default from pfs_pkg.vhd
+ -- PFB2 "data/pfs_coefsbuf_1024.hex" = Coeffs16384Kaiser-quant.dat default from pfs_pkg.vhd
+ g_pfir_coefs_file : string := c_pfs_coefs_file
);
end entity tb_verify_pfb_response;
@@ -86,7 +90,8 @@ architecture tb of tb_verify_pfb_response is
constant c_nof_blk_per_sync : natural := 20;
constant c_pfs_bypass : boolean := g_fil_coefs_file_prefix = "data/run_pfir_coeff_m_bypass_16taps_1024points_16b_1wb";
- constant c_fil_coefs_dat_file : string := g_fil_coefs_file_prefix(1 to g_fil_coefs_file_prefix'length - 4) & ".dat"; -- strip _1wb
+ -- strip _1wb
+ constant c_fil_coefs_dat_file : string := g_fil_coefs_file_prefix(1 to g_fil_coefs_file_prefix'length - 4) & ".dat";
-- WPFB
-- type t_wpfb is record
@@ -135,11 +140,14 @@ architecture tb of tb_verify_pfb_response is
c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
constant c_N_fft : natural := c_wpfb.nof_points;
- constant c_N_blk : natural := c_wpfb.nof_blk_per_sync; -- nof FFT blocks per sync interval
+ -- nof FFT blocks per sync interval
+ constant c_N_blk : natural := c_wpfb.nof_blk_per_sync;
constant c_N_taps : natural := c_wpfb.nof_taps;
constant c_nof_coefs : natural := c_N_taps * c_N_fft;
- constant c_nof_channels : natural := 2**c_wpfb.nof_chan; -- = 2**0 = 1, so no time multiplexing of inputs
- constant c_nof_sync : natural := 2; -- nof sync intervals to simulate
+ -- = 2**0 = 1, so no time multiplexing of inputs
+ constant c_nof_channels : natural := 2**c_wpfb.nof_chan;
+ -- nof sync intervals to simulate
+ constant c_nof_sync : natural := 2;
-- BSN source
constant c_bsn_w : natural := 64;
@@ -163,17 +171,25 @@ architecture tb of tb_verify_pfb_response is
signal in_sosi_arr : t_dp_sosi_arr(0 downto 0);
signal in_sosi : t_dp_sosi;
- signal in_a_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
- signal in_b_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal in_a_scope : integer := 0;
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal in_b_scope : integer := 0;
signal in_val : std_logic;
- signal in_val_cnt_per_sop : natural := 0; -- count valid samples per block
- signal in_val_cnt_per_sync : natural := 0; -- count valid samples per sync interval
- signal in_blk_cnt : natural := 0; -- count blocks per sync interval
+ -- count valid samples per block
+ signal in_val_cnt_per_sop : natural := 0;
+ -- count valid samples per sync interval
+ signal in_val_cnt_per_sync : natural := 0;
+ -- count blocks per sync interval
+ signal in_blk_cnt : natural := 0;
-- Filter coefficients
- signal ref_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef read from g_fil_coefs_file_prefix file
- signal flip_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef from g_fil_coefs_file_prefix flipped per tap
- signal read_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef read via MM from the coefs memories
+ -- = PFIR coef read from g_fil_coefs_file_prefix file
+ signal ref_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0);
+ -- = PFIR coef from g_fil_coefs_file_prefix flipped per tap
+ signal flip_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0);
+ -- = PFIR coef read via MM from the coefs memories
+ signal read_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0);
signal ram_fil_coefs_mosi : t_mem_mosi := c_mem_mosi_rst;
signal ram_fil_coefs_miso : t_mem_miso;
@@ -181,12 +197,17 @@ architecture tb of tb_verify_pfb_response is
-- Filter output
signal fil_sosi_arr : t_dp_sosi_arr(0 downto 0);
signal fil_sosi : t_dp_sosi;
- signal fil_re_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
- signal fil_im_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal fil_re_scope : integer := 0;
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal fil_im_scope : integer := 0;
signal fil_val : std_logic;
- signal fil_val_cnt_per_sop : natural := 0; -- count valid samples per block
- signal fil_val_cnt_per_sync : natural := 0; -- count valid samples per sync interval
- signal fil_blk_cnt : natural := 0; -- count blocks per sync interval
+ -- count valid samples per block
+ signal fil_val_cnt_per_sop : natural := 0;
+ -- count valid samples per sync interval
+ signal fil_val_cnt_per_sync : natural := 0;
+ -- count blocks per sync interval
+ signal fil_blk_cnt : natural := 0;
-- Output
signal raw_sosi_arr : t_dp_sosi_arr(0 downto 0);
@@ -200,20 +221,26 @@ architecture tb of tb_verify_pfb_response is
signal out_val_cnt : natural := 0;
signal out_blk_cnt : natural := 0;
- signal out_val_a : std_logic; -- for real A
- signal out_val_b : std_logic; -- for real B
+ -- for real A
+ signal out_val_a : std_logic;
+ -- for real B
+ signal out_val_b : std_logic;
signal out_channel : natural := 0;
signal out_cnt : natural := 0;
signal out_bin_cnt : natural := 0;
signal out_bin : natural := 0;
signal reg_out_sosi : t_dp_sosi;
- signal reg_out_re_a_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
- signal reg_out_im_a_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal reg_out_re_a_scope : integer := 0;
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal reg_out_im_a_scope : integer := 0;
signal reg_out_power_a_scope : real := 0.0;
signal reg_out_phase_a_scope : real := 0.0;
- signal reg_out_re_b_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
- signal reg_out_im_b_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal reg_out_re_b_scope : integer := 0;
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal reg_out_im_b_scope : integer := 0;
signal reg_out_power_b_scope : real := 0.0;
signal reg_out_phase_b_scope : real := 0.0;
signal reg_out_val_a : std_logic;
@@ -246,7 +273,8 @@ begin
proc_common_wait_some_cycles(dp_clk, c_N_fft);
-- Start BSN
bs_sosi.valid <= '1';
- for K in 0 to c_nof_sync loop -- simulate one input sync interval extra to have c_nof_sync output sync intervals
+ -- simulate one input sync interval extra to have c_nof_sync output sync intervals
+ for K in 0 to c_nof_sync loop
bs_sosi.sync <= '1';
for J in 0 to c_N_blk - 1 loop
bs_sosi.sop <= '1';
@@ -276,7 +304,8 @@ begin
if bs_sosi.eop = '1' then
-- raise impulse for one block
if impulse_cnt = 0 then
- impulse_data <= TO_SVEC(2**(c_W_adc - 2), c_W_adc); -- 0.5 * full scale impulse that will be active at sop (= after eop)
+ -- 0.5 * full scale impulse that will be active at sop (= after eop)
+ impulse_data <= TO_SVEC(2**(c_W_adc - 2), c_W_adc);
else
impulse_data <= TO_SVEC(0, c_W_adc);
end if;
@@ -324,7 +353,8 @@ begin
p_read_coefs_from_mm : process
constant c_mif_coef_mem_addr_w : natural := ceil_log2(c_N_fft);
- constant c_mif_coef_mem_span : natural := 2**c_mif_coef_mem_addr_w; -- mif coef mem span for one tap
+ -- mif coef mem span for one tap
+ constant c_mif_coef_mem_span : natural := 2**c_mif_coef_mem_addr_w;
variable v_mif_base : natural;
variable v_I : natural := 0;
@@ -379,7 +409,8 @@ begin
dut_pfb2_unit : if g_sel_pfb = "PFB2" generate
u_pfb2_unit : entity pfb2_lib.pfb2_unit
generic map (
- g_nof_streams => 1, -- number of pfb2 instances, 1 pfb2 per stream
+ -- number of pfb2 instances, 1 pfb2 per stream
+ g_nof_streams => 1,
g_nof_points => c_wpfb.nof_points,
-- pfs
diff --git a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
index ee4a173a4ab9271e6aa5c90cdb826516ff7fdec3..263c9f55cdff22bbac3e13cd0fa04e40ed9a43ac 100644
--- a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
+++ b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
@@ -109,17 +109,25 @@ use pft2_lib.pft_pkg.all;
entity tb_verify_pfb_wg is
generic (
- g_tb_index : natural := 0; -- use g_tb_index to identify and separate print_str() loggings from multi tb
- g_sel_pfb : string := "WPFB"; -- "WPFB" for APERTIF PFB, "PFB2" for LOFAR1 PBF
+ -- use g_tb_index to identify and separate print_str() loggings from multi tb
+ g_tb_index : natural := 0;
+ -- "WPFB" for APERTIF PFB, "PFB2" for LOFAR1 PBF
+ g_sel_pfb : string := "WPFB";
--g_sel_pfb : STRING := "PFB2";
-- WG
- g_subband_index_a : real := 61.0; -- 0:511
- g_subband_index_b : real := 61.0; -- 0:511
- g_amplitude_a : real := 1.0; -- 1.0 is full scale
- g_amplitude_b : real := 0.0; -- 1.0 is full scale
- g_phase_a : real := 0.0; -- 0:360 degrees
- g_phase_b : real := 0.0; -- 0:360 degrees
+ -- 0:511
+ g_subband_index_a : real := 61.0;
+ -- 0:511
+ g_subband_index_b : real := 61.0;
+ -- 1.0 is full scale
+ g_amplitude_a : real := 1.0;
+ -- 1.0 is full scale
+ g_amplitude_b : real := 0.0;
+ -- 0:360 degrees
+ g_phase_a : real := 0.0;
+ -- 0:360 degrees
+ g_phase_b : real := 0.0;
-- WPFB fields in c_wpfb
-- . c_sdp_wpfb_subbands from sdp_pkg.vhd:
@@ -140,25 +148,35 @@ entity tb_verify_pfb_wg is
-- . g_fft_guard_w = 2
-- FIR filter
- g_fil_coefs_file_prefix : string := "data/Coeffs16384Kaiser-quant_1wb"; -- PFIR coefficients file access
+ -- PFIR coefficients file access
+ g_fil_coefs_file_prefix : string := "data/Coeffs16384Kaiser-quant_1wb";
--g_fil_coefs_file_prefix : STRING := "data/run_pfir_coeff_m_bypass_16taps_1024points_16b_1wb"; -- bypass PFIR
--g_fil_coefs_file_prefix : STRING := "data/run_pfir_coeff_m_fircls1_16taps_1024points_16b_1wb"; -- g_fil_coef_dat_w = 16 bit
--g_fil_coefs_file_prefix : STRING := "data/run_pfir_coeff_m_fircls1_16taps_1024points_18b_1wb"; -- g_fil_coef_dat_w = 18 bit
- g_fil_coef_dat_w : natural := 16; -- = 16, data width of the FIR coefficients
+ -- = 16, data width of the FIR coefficients
+ g_fil_coef_dat_w : natural := 16;
--g_fil_coef_dat_w : NATURAL := 18; -- = 16, data width of the FIR coefficients
- g_fil_backoff_w : natural := 1; -- = 0, number of bits for input backoff to avoid output overflow
- g_fil_in_dat_w : natural := 14; -- = W_adc, number of input bits
+ -- = 0, number of bits for input backoff to avoid output overflow
+ g_fil_backoff_w : natural := 1;
+ -- = W_adc, number of input bits
+ g_fil_in_dat_w : natural := 14;
- g_internal_dat_w : natural := 0; -- = number of bits between fil and fft, use 0 to use maximum default:
+ -- = number of bits between fil and fft, use 0 to use maximum default:
+ g_internal_dat_w : natural := 0;
-- . WPFB : g_internal_dat_w <= g_fft_stage_dat_w - g_fft_guard_w in fft_r2_pipe
-- . PFB2 : g_internal_dat_w <= g_fft_stage_dat_w
-- FFT
- g_fft_out_dat_w : natural := 18; -- = W_subband, number of output bits
- g_fft_out_gain_w : natural := 1; -- = 1, output gain factor applied after the last stage output, before requantization to out_dat_w
- g_fft_stage_dat_w : natural := 24; -- = c_dsp_mult_w = 18, number of bits that are used inter-stage
- g_fft_guard_w : natural := 1; -- = 2
- g_switch_en : std_logic := '0' -- two real input decorrelation option in PFB2
+ -- = W_subband, number of output bits
+ g_fft_out_dat_w : natural := 18;
+ -- = 1, output gain factor applied after the last stage output, before requantization to out_dat_w
+ g_fft_out_gain_w : natural := 1;
+ -- = c_dsp_mult_w = 18, number of bits that are used inter-stage
+ g_fft_stage_dat_w : natural := 24;
+ -- = 2
+ g_fft_guard_w : natural := 1;
+ -- two real input decorrelation option in PFB2
+ g_switch_en : std_logic := '0'
);
end entity tb_verify_pfb_wg;
@@ -167,7 +185,8 @@ architecture tb of tb_verify_pfb_wg is
constant c_dp_clk_period : time := 10 ns;
-- Define input stimuli WG sinus or impulse
- constant c_view_pfir_impulse_reponse : boolean := false; -- Default FALSE to use WG data input, else use TRUE to view PFIR coefficients via fil_re_scope in Wave Window
+ -- Default FALSE to use WG data input, else use TRUE to view PFIR coefficients via fil_re_scope in Wave Window
+ constant c_view_pfir_impulse_reponse : boolean := false;
--CONSTANT c_view_pfir_impulse_reponse : BOOLEAN := TRUE;
-- Determine bypass PFIR for PFB2, using g_fil_coefs_file_prefix setting for WPFB
@@ -176,7 +195,8 @@ architecture tb of tb_verify_pfb_wg is
-- Determine PFIR coefficient width for WPFB and PFB2
constant c_pfir_coef_w : natural := sel_a_b(g_sel_pfb = "WPFB", g_fil_coef_dat_w, 16);
- constant c_pfir_coefs_file : string := c_pfs_coefs_file; -- PFB2 "data/pfs_coefsbuf_1024.hex" default from pfs_pkg.vhd
+ -- PFB2 "data/pfs_coefsbuf_1024.hex" default from pfs_pkg.vhd
+ constant c_pfir_coefs_file : string := c_pfs_coefs_file;
-- Determine internal data width between PFIR and PFT for WPFB and PFB2, use default if g_internal_dat_w=0
constant c_internal_dat_w : natural := sel_a_b(g_sel_pfb = "WPFB",
@@ -188,7 +208,8 @@ architecture tb of tb_verify_pfb_wg is
-- Determine FFT twiddle factors info
constant c_fft_twiddle : wTyp := (others => '0');
- constant c_fft_twiddle_w : natural := c_fft_twiddle'length; -- from rTwoSDF twiddlesPkg.vhd
+ -- from rTwoSDF twiddlesPkg.vhd
+ constant c_fft_twiddle_w : natural := c_fft_twiddle'length;
constant c_twiddle_w : natural := sel_a_b(g_sel_pfb = "WPFB", c_fft_twiddle_w, c_pft_twiddle_w);
-- WPFB
@@ -234,10 +255,14 @@ architecture tb of tb_verify_pfb_wg is
constant c_N_fft : natural := c_wpfb.nof_points;
constant c_N_sub : natural := c_N_fft / c_nof_complex;
- constant c_N_blk : natural := c_wpfb.nof_blk_per_sync; -- nof FFT blocks per sync interval
- constant c_N_samples : natural := c_N_fft * c_N_blk; -- nof samples per sync interval
- constant c_nof_channels : natural := 2**c_wpfb.nof_chan; -- = 2**0 = 1, so no time multiplexing of inputs
- constant c_nof_sync : natural := 5; -- nof sync intervals to simulate
+ -- nof FFT blocks per sync interval
+ constant c_N_blk : natural := c_wpfb.nof_blk_per_sync;
+ -- nof samples per sync interval
+ constant c_N_samples : natural := c_N_fft * c_N_blk;
+ -- = 2**0 = 1, so no time multiplexing of inputs
+ constant c_nof_channels : natural := 2**c_wpfb.nof_chan;
+ -- nof sync intervals to simulate
+ constant c_nof_sync : natural := 5;
-- Subband at WG frequency
constant c_bin_a : natural := natural(FLOOR(g_subband_index_a));
@@ -250,8 +275,10 @@ architecture tb of tb_verify_pfb_wg is
-- ADC
constant c_W_adc : natural := c_wpfb.fil_in_dat_w;
- constant c_adc_fs : real := real(2**(c_W_adc - 1) - 1); -- ADC full scale
- constant c_adc_quant_power : real := 1.0 / 12.0; -- ADC theoretical quantization noise power
+ -- ADC full scale
+ constant c_adc_fs : real := real(2**(c_W_adc - 1) - 1);
+ -- ADC theoretical quantization noise power
+ constant c_adc_quant_power : real := 1.0 / 12.0;
-- Waveform Generator
constant c_wg_ampl_a : real := g_amplitude_a * c_adc_fs;
@@ -266,11 +293,15 @@ architecture tb of tb_verify_pfb_wg is
constant c_wg_snr_b_dB : real := 10.0 * LOG10(c_wg_snr_b + c_eps);
constant c_wg_buf_directory : string := "data/";
- constant c_wg_buf_dat_w : natural := 18; -- default value of WG that fits 14 bits of ADC data
- constant c_wg_buf_addr_w : natural := 10; -- default value of WG for 1024 samples;
- constant c_wg_calc_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**(c_W_adc-1)>
+ -- default value of WG that fits 14 bits of ADC data
+ constant c_wg_buf_dat_w : natural := 18;
+ -- default value of WG for 1024 samples;
+ constant c_wg_buf_addr_w : natural := 10;
+ -- Normalized range [0 1> maps to fixed point range [0:2**(c_W_adc-1)>
+ constant c_wg_calc_gain_w : natural := 1;
constant c_wg_calc_dat_w : natural := c_W_adc;
- constant c_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_N_fft); -- freq = Fs/16 = 200 MSps/16 = 12.5 MHz sinus,
+ -- freq = Fs/16 = 200 MSps/16 = 12.5 MHz sinus,
+ constant c_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_N_fft);
-- subband index / c_N_fft = 64 / 1024 = 1/16
-- SST
@@ -316,22 +347,32 @@ architecture tb of tb_verify_pfb_wg is
signal in_sosi_arr : t_dp_sosi_arr(0 downto 0);
signal in_sosi : t_dp_sosi;
- signal in_a_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
- signal in_b_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal in_a_scope : integer := 0;
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal in_b_scope : integer := 0;
signal in_val : std_logic;
- signal in_val_cnt_per_sop : natural := 0; -- count valid samples per block
- signal in_val_cnt_per_sync : natural := 0; -- count valid samples per sync interval
- signal in_blk_cnt : natural := 0; -- count blocks per sync interval
+ -- count valid samples per block
+ signal in_val_cnt_per_sop : natural := 0;
+ -- count valid samples per sync interval
+ signal in_val_cnt_per_sync : natural := 0;
+ -- count blocks per sync interval
+ signal in_blk_cnt : natural := 0;
-- Filter output
signal fil_sosi_arr : t_dp_sosi_arr(0 downto 0);
signal fil_sosi : t_dp_sosi;
- signal fil_re_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
- signal fil_im_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal fil_re_scope : integer := 0;
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal fil_im_scope : integer := 0;
signal fil_val : std_logic;
- signal fil_val_cnt_per_sop : natural := 0; -- count valid samples per block
- signal fil_val_cnt_per_sync : natural := 0; -- count valid samples per sync interval
- signal fil_blk_cnt : natural := 0; -- count blocks per sync interval
+ -- count valid samples per block
+ signal fil_val_cnt_per_sop : natural := 0;
+ -- count valid samples per sync interval
+ signal fil_val_cnt_per_sync : natural := 0;
+ -- count blocks per sync interval
+ signal fil_blk_cnt : natural := 0;
signal sub_a_re : integer := 0;
signal sub_a_im : integer := 0;
@@ -349,129 +390,230 @@ architecture tb of tb_verify_pfb_wg is
-- Input power measurement
-- . signal input A
- signal input_track_max_a : real := 0.0; -- track sample max
- signal input_track_min_a : real := 0.0; -- track sample min
- signal input_accum_mean_a : real := 0.0; -- accumulate sample mean (DC)
- signal input_accum_power_a : real := 0.0; -- accumulate sample power
- signal input_max_a : real := 0.0; -- measured sample max
- signal input_min_a : real := 0.0; -- measured sample min
- signal input_mean_a : real := 0.0; -- measured average input sample mean (DC) based on AST
- signal input_power_a : real := 0.0; -- measured average input sample power based on AST
- signal input_ampl_a : real := 0.0; -- measured input amplitude based on AST
+ -- track sample max
+ signal input_track_max_a : real := 0.0;
+ -- track sample min
+ signal input_track_min_a : real := 0.0;
+ -- accumulate sample mean (DC)
+ signal input_accum_mean_a : real := 0.0;
+ -- accumulate sample power
+ signal input_accum_power_a : real := 0.0;
+ -- measured sample max
+ signal input_max_a : real := 0.0;
+ -- measured sample min
+ signal input_min_a : real := 0.0;
+ -- measured average input sample mean (DC) based on AST
+ signal input_mean_a : real := 0.0;
+ -- measured average input sample power based on AST
+ signal input_power_a : real := 0.0;
+ -- measured input amplitude based on AST
+ signal input_ampl_a : real := 0.0;
-- . signal input B
- signal input_track_max_b : real := 0.0; -- track sample max
- signal input_track_min_b : real := 0.0; -- track sample min
- signal input_accum_mean_b : real := 0.0; -- accumulate sample mean (DC)
- signal input_accum_power_b : real := 0.0; -- accumulate sample power
- signal input_max_b : real := 0.0; -- measured sample max
- signal input_min_b : real := 0.0; -- measured sample min
- signal input_mean_b : real := 0.0; -- measured average input sample mean (DC) based on AST
- signal input_power_b : real := 0.0; -- measured average input sample power based on AST
- signal input_ampl_b : real := 0.0; -- measured input amplitude based on AST
+ -- track sample max
+ signal input_track_max_b : real := 0.0;
+ -- track sample min
+ signal input_track_min_b : real := 0.0;
+ -- accumulate sample mean (DC)
+ signal input_accum_mean_b : real := 0.0;
+ -- accumulate sample power
+ signal input_accum_power_b : real := 0.0;
+ -- measured sample max
+ signal input_max_b : real := 0.0;
+ -- measured sample min
+ signal input_min_b : real := 0.0;
+ -- measured average input sample mean (DC) based on AST
+ signal input_mean_b : real := 0.0;
+ -- measured average input sample power based on AST
+ signal input_power_b : real := 0.0;
+ -- measured input amplitude based on AST
+ signal input_ampl_b : real := 0.0;
-- Input CW amplitude and phase estimator
-- . signal input A
- signal cw_ref_I_a : real := 0.0; -- local I in phase reference
- signal cw_ref_Q_a : real := 0.0; -- local Q quadrature reference
- signal cw_accum_I_a : real := 0.0; -- local I accumulator
- signal cw_accum_Q_a : real := 0.0; -- local Q accumulator
- signal cw_ampl_a : real := 0.0; -- estimated CW amplitude
- signal cw_phase_a : real := 0.0; -- estimated CW phase in radials
- signal cw_phase_Ts_a : real := 0.0; -- estimated CW phase in sample periods
- signal cw_dat_a : integer := 0; -- estimated CW = amplitude * SIN(omega*t + phase)
- signal cw_power_a : real := 0.0; -- estimated CW power
- signal cw_noise_a : real := 0.0; -- estimated CW quantization noise
- signal cw_accum_noise_a : real := 0.0; -- local noise power accumulator
- signal cw_noise_power_a : real := 0.0; -- estimated noise power
- signal wg_measured_snr_a : real := 0.0; -- estimated SNR
- signal wg_measured_snr_a_dB : real := 0.0; -- estimated SNR in dB
+ -- local I in phase reference
+ signal cw_ref_I_a : real := 0.0;
+ -- local Q quadrature reference
+ signal cw_ref_Q_a : real := 0.0;
+ -- local I accumulator
+ signal cw_accum_I_a : real := 0.0;
+ -- local Q accumulator
+ signal cw_accum_Q_a : real := 0.0;
+ -- estimated CW amplitude
+ signal cw_ampl_a : real := 0.0;
+ -- estimated CW phase in radials
+ signal cw_phase_a : real := 0.0;
+ -- estimated CW phase in sample periods
+ signal cw_phase_Ts_a : real := 0.0;
+ -- estimated CW = amplitude * SIN(omega*t + phase)
+ signal cw_dat_a : integer := 0;
+ -- estimated CW power
+ signal cw_power_a : real := 0.0;
+ -- estimated CW quantization noise
+ signal cw_noise_a : real := 0.0;
+ -- local noise power accumulator
+ signal cw_accum_noise_a : real := 0.0;
+ -- estimated noise power
+ signal cw_noise_power_a : real := 0.0;
+ -- estimated SNR
+ signal wg_measured_snr_a : real := 0.0;
+ -- estimated SNR in dB
+ signal wg_measured_snr_a_dB : real := 0.0;
-- . signal input B
- signal cw_ref_I_b : real := 0.0; -- local I in phase reference
- signal cw_ref_Q_b : real := 0.0; -- local Q quadrature reference
- signal cw_accum_I_b : real := 0.0; -- local I accumulator
- signal cw_accum_Q_b : real := 0.0; -- local Q accumulator
- signal cw_ampl_b : real := 0.0; -- estimated CW amplitude
- signal cw_phase_b : real := 0.0; -- estimated CW phase in radials
- signal cw_phase_Ts_b : real := 0.0; -- estimated CW phase in sample periods
- signal cw_dat_b : integer := 0; -- estimated CW = amplitude * SIN(omega*t + phase)
- signal cw_power_b : real := 0.0; -- estimated CW power
- signal cw_noise_b : real := 0.0; -- estimated CW quantization noise
- signal cw_accum_noise_b : real := 0.0; -- local noise power accumulator
- signal cw_noise_power_b : real := 0.0; -- estimated noise power
- signal wg_measured_snr_b : real := 0.0; -- estimated SNR
- signal wg_measured_snr_b_dB : real := 0.0; -- estimated SNR in dB
+ -- local I in phase reference
+ signal cw_ref_I_b : real := 0.0;
+ -- local Q quadrature reference
+ signal cw_ref_Q_b : real := 0.0;
+ -- local I accumulator
+ signal cw_accum_I_b : real := 0.0;
+ -- local Q accumulator
+ signal cw_accum_Q_b : real := 0.0;
+ -- estimated CW amplitude
+ signal cw_ampl_b : real := 0.0;
+ -- estimated CW phase in radials
+ signal cw_phase_b : real := 0.0;
+ -- estimated CW phase in sample periods
+ signal cw_phase_Ts_b : real := 0.0;
+ -- estimated CW = amplitude * SIN(omega*t + phase)
+ signal cw_dat_b : integer := 0;
+ -- estimated CW power
+ signal cw_power_b : real := 0.0;
+ -- estimated CW quantization noise
+ signal cw_noise_b : real := 0.0;
+ -- local noise power accumulator
+ signal cw_accum_noise_b : real := 0.0;
+ -- estimated noise power
+ signal cw_noise_power_b : real := 0.0;
+ -- estimated SNR
+ signal wg_measured_snr_b : real := 0.0;
+ -- estimated SNR in dB
+ signal wg_measured_snr_b_dB : real := 0.0;
-- FIR filter output power measurement
-- . signal input A
- signal fir_track_max_a : real := 0.0; -- track sample max
- signal fir_track_min_a : real := 0.0; -- track sample min
- signal fir_accum_mean_a : real := 0.0; -- accumulate sample mean (DC)
- signal fir_accum_power_a : real := 0.0; -- accumulate sample power
- signal fir_max_a : real := 0.0; -- measured sample max
- signal fir_min_a : real := 0.0; -- measured sample min
- signal fir_mean_a : real := 0.0; -- measured average input sample mean (DC) based on AST
- signal fir_power_a : real := 0.0; -- measured average input sample power based on AST
- signal fir_ampl_a : real := 0.0; -- measured input amplitude based on AST
+ -- track sample max
+ signal fir_track_max_a : real := 0.0;
+ -- track sample min
+ signal fir_track_min_a : real := 0.0;
+ -- accumulate sample mean (DC)
+ signal fir_accum_mean_a : real := 0.0;
+ -- accumulate sample power
+ signal fir_accum_power_a : real := 0.0;
+ -- measured sample max
+ signal fir_max_a : real := 0.0;
+ -- measured sample min
+ signal fir_min_a : real := 0.0;
+ -- measured average input sample mean (DC) based on AST
+ signal fir_mean_a : real := 0.0;
+ -- measured average input sample power based on AST
+ signal fir_power_a : real := 0.0;
+ -- measured input amplitude based on AST
+ signal fir_ampl_a : real := 0.0;
-- . signal input B
- signal fir_track_max_b : real := 0.0; -- track sample max
- signal fir_track_min_b : real := 0.0; -- track sample min
- signal fir_accum_mean_b : real := 0.0; -- accumulate sample mean (DC)
- signal fir_accum_power_b : real := 0.0; -- accumulate sample power
- signal fir_max_b : real := 0.0; -- measured sample max
- signal fir_min_b : real := 0.0; -- measured sample min
- signal fir_mean_b : real := 0.0; -- measured average input sample mean (DC) based on AST
- signal fir_power_b : real := 0.0; -- measured average input sample power based on AST
- signal fir_ampl_b : real := 0.0; -- measured input amplitude based on AST
+ -- track sample max
+ signal fir_track_max_b : real := 0.0;
+ -- track sample min
+ signal fir_track_min_b : real := 0.0;
+ -- accumulate sample mean (DC)
+ signal fir_accum_mean_b : real := 0.0;
+ -- accumulate sample power
+ signal fir_accum_power_b : real := 0.0;
+ -- measured sample max
+ signal fir_max_b : real := 0.0;
+ -- measured sample min
+ signal fir_min_b : real := 0.0;
+ -- measured average input sample mean (DC) based on AST
+ signal fir_mean_b : real := 0.0;
+ -- measured average input sample power based on AST
+ signal fir_power_b : real := 0.0;
+ -- measured input amplitude based on AST
+ signal fir_ampl_b : real := 0.0;
-- FIR filter output CW amplitude and phase estimator
-- . signal input A
- signal fil_ref_I_a : real := 0.0; -- local I in phase reference
- signal fil_ref_Q_a : real := 0.0; -- local Q quadrature reference
- signal fil_accum_I_a : real := 0.0; -- local I accumulator
- signal fil_accum_Q_a : real := 0.0; -- local Q accumulator
- signal fil_ampl_a : real := 0.0; -- estimated CW amplitude
- signal fil_phase_a : real := 0.0; -- estimated CW phase in radials
- signal fil_phase_Ts_a : real := 0.0; -- estimated CW phase in sample periods
- signal fil_dat_a : integer := 0; -- estimated CW = amplitude * SIN(omega*t + phase)
- signal fil_power_a : real := 0.0; -- estimated CW power
- signal fil_noise_a : real := 0.0; -- estimated CW quantization noise
- signal fil_accum_noise_a : real := 0.0; -- local noise power accumulator
- signal fil_noise_power_a : real := 0.0; -- estimated noise power
- signal fil_measured_snr_a : real := 0.0; -- estimated SNR
- signal fil_measured_snr_a_dB : real := 0.0; -- estimated SNR in dB
+ -- local I in phase reference
+ signal fil_ref_I_a : real := 0.0;
+ -- local Q quadrature reference
+ signal fil_ref_Q_a : real := 0.0;
+ -- local I accumulator
+ signal fil_accum_I_a : real := 0.0;
+ -- local Q accumulator
+ signal fil_accum_Q_a : real := 0.0;
+ -- estimated CW amplitude
+ signal fil_ampl_a : real := 0.0;
+ -- estimated CW phase in radials
+ signal fil_phase_a : real := 0.0;
+ -- estimated CW phase in sample periods
+ signal fil_phase_Ts_a : real := 0.0;
+ -- estimated CW = amplitude * SIN(omega*t + phase)
+ signal fil_dat_a : integer := 0;
+ -- estimated CW power
+ signal fil_power_a : real := 0.0;
+ -- estimated CW quantization noise
+ signal fil_noise_a : real := 0.0;
+ -- local noise power accumulator
+ signal fil_accum_noise_a : real := 0.0;
+ -- estimated noise power
+ signal fil_noise_power_a : real := 0.0;
+ -- estimated SNR
+ signal fil_measured_snr_a : real := 0.0;
+ -- estimated SNR in dB
+ signal fil_measured_snr_a_dB : real := 0.0;
-- . signal input B
- signal fil_ref_I_b : real := 0.0; -- local I in phase reference
- signal fil_ref_Q_b : real := 0.0; -- local Q quadrature reference
- signal fil_accum_I_b : real := 0.0; -- local I accumulator
- signal fil_accum_Q_b : real := 0.0; -- local Q accumulator
- signal fil_ampl_b : real := 0.0; -- estimated CW amplitude
- signal fil_phase_b : real := 0.0; -- estimated CW phase in radials
- signal fil_phase_Ts_b : real := 0.0; -- estimated CW phase in sample periods
- signal fil_dat_b : integer := 0; -- estimated CW = amplitude * SIN(omega*t + phase)
- signal fil_power_b : real := 0.0; -- estimated CW power
- signal fil_noise_b : real := 0.0; -- estimated CW quantization noise
- signal fil_accum_noise_b : real := 0.0; -- local noise power accumulator
- signal fil_noise_power_b : real := 0.0; -- estimated noise power
- signal fil_measured_snr_b : real := 0.0; -- estimated SNR
- signal fil_measured_snr_b_dB : real := 0.0; -- estimated SNR in dB
+ -- local I in phase reference
+ signal fil_ref_I_b : real := 0.0;
+ -- local Q quadrature reference
+ signal fil_ref_Q_b : real := 0.0;
+ -- local I accumulator
+ signal fil_accum_I_b : real := 0.0;
+ -- local Q accumulator
+ signal fil_accum_Q_b : real := 0.0;
+ -- estimated CW amplitude
+ signal fil_ampl_b : real := 0.0;
+ -- estimated CW phase in radials
+ signal fil_phase_b : real := 0.0;
+ -- estimated CW phase in sample periods
+ signal fil_phase_Ts_b : real := 0.0;
+ -- estimated CW = amplitude * SIN(omega*t + phase)
+ signal fil_dat_b : integer := 0;
+ -- estimated CW power
+ signal fil_power_b : real := 0.0;
+ -- estimated CW quantization noise
+ signal fil_noise_b : real := 0.0;
+ -- local noise power accumulator
+ signal fil_accum_noise_b : real := 0.0;
+ -- estimated noise power
+ signal fil_noise_power_b : real := 0.0;
+ -- estimated SNR
+ signal fil_measured_snr_b : real := 0.0;
+ -- estimated SNR in dB
+ signal fil_measured_snr_b_dB : real := 0.0;
-- SST
type t_slv_64_subbands_arr is array (integer range <>) of t_slv_64_arr(0 to c_N_sub - 1);
- signal sp_subband_powers_arr2 : t_slv_64_subbands_arr(c_nof_complex - 1 downto 0); -- [sp][sub], sp = A,B, sub = 0:c_N_sub-1
+ -- [sp][sub], sp = A,B, sub = 0:c_N_sub-1
+ signal sp_subband_powers_arr2 : t_slv_64_subbands_arr(c_nof_complex - 1 downto 0);
signal sp_subband_powers_a : t_nat_real_arr(0 to c_N_sub - 1) := (others => 0.0);
signal sp_subband_powers_b : t_nat_real_arr(0 to c_N_sub - 1) := (others => 0.0);
- signal sst_wg_power_a : real := 0.0; -- measured WG sine power at WG bin in SST
- signal sst_wg_power_a_dB : real := 0.0; -- measured WG sine power at WG bin in SST in dB
- signal sst_noise_a : real := 0.0; -- measured sum of noise power in all other bins in SST
- signal sst_noise_a_dB : real := 0.0; -- measured sum of noise power in all other bins in SST in dB
- signal sst_wg_power_b : real := 0.0; -- measured WG sine power at WG bin in SST
- signal sst_wg_power_b_dB : real := 0.0; -- measured WG sine power at WG bin in SST in dB
- signal sst_noise_b : real := 0.0; -- measured sum of noise power in all other bins in SST
- signal sst_noise_b_dB : real := 0.0; -- measured sum of noise power in all other bins in SST in dB
+ -- measured WG sine power at WG bin in SST
+ signal sst_wg_power_a : real := 0.0;
+ -- measured WG sine power at WG bin in SST in dB
+ signal sst_wg_power_a_dB : real := 0.0;
+ -- measured sum of noise power in all other bins in SST
+ signal sst_noise_a : real := 0.0;
+ -- measured sum of noise power in all other bins in SST in dB
+ signal sst_noise_a_dB : real := 0.0;
+ -- measured WG sine power at WG bin in SST
+ signal sst_wg_power_b : real := 0.0;
+ -- measured WG sine power at WG bin in SST in dB
+ signal sst_wg_power_b_dB : real := 0.0;
+ -- measured sum of noise power in all other bins in SST
+ signal sst_noise_b : real := 0.0;
+ -- measured sum of noise power in all other bins in SST in dB
+ signal sst_noise_b_dB : real := 0.0;
-- SNR and WPFB processing gain
signal sst_measured_snr_a : real := 0.0;
@@ -494,18 +636,24 @@ architecture tb of tb_verify_pfb_wg is
signal out_val_cnt : natural := 0;
signal out_blk_cnt : natural := 0;
- signal out_val_a : std_logic; -- for real A
- signal out_val_b : std_logic; -- for real B
+ -- for real A
+ signal out_val_a : std_logic;
+ -- for real B
+ signal out_val_b : std_logic;
signal out_channel : natural := 0;
signal out_cnt : natural := 0;
signal out_bin_cnt : natural := 0;
signal out_bin : natural := 0;
signal reg_out_sosi : t_dp_sosi;
- signal reg_out_re_a_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
- signal reg_out_im_a_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
- signal reg_out_re_b_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
- signal reg_out_im_b_scope : integer := 0; -- init at 0 to fit automatic analog scaling in Wave Window
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal reg_out_re_a_scope : integer := 0;
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal reg_out_im_a_scope : integer := 0;
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal reg_out_re_b_scope : integer := 0;
+ -- init at 0 to fit automatic analog scaling in Wave Window
+ signal reg_out_im_b_scope : integer := 0;
signal reg_out_val_a : std_logic;
signal reg_out_val_b : std_logic;
signal reg_out_val : std_logic;
@@ -537,7 +685,8 @@ begin
-- Start BSN when WG have started
proc_common_wait_until_high(dp_clk, bs_start);
bs_sosi.valid <= '1';
- for K in 0 to c_nof_sync loop -- simulate one input sync interval extra to have c_nof_sync output sync intervals
+ -- simulate one input sync interval extra to have c_nof_sync output sync intervals
+ for K in 0 to c_nof_sync loop
bs_sosi.sync <= '1';
for J in 0 to c_N_blk - 1 loop
bs_sosi.sop <= '1';
@@ -579,15 +728,23 @@ begin
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
-- WG-A
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 1, mm_clk, reg_wg_mosi_a); -- mode calc, nof_sample
- proc_mem_mm_bus_wr(1, integer(g_phase_a * c_diag_wg_phase_unit), mm_clk, reg_wg_mosi_a); -- phase offset in degrees
- proc_mem_mm_bus_wr(2, integer(g_subband_index_a * c_wg_subband_freq_unit), mm_clk, reg_wg_mosi_a); -- freq
- proc_mem_mm_bus_wr(3, integer(g_amplitude_a * c_diag_wg_ampl_unit), mm_clk, reg_wg_mosi_a); -- amplitude
+ -- mode calc, nof_sample
+ proc_mem_mm_bus_wr(0, 1024 * 2**16 + 1, mm_clk, reg_wg_mosi_a);
+ -- phase offset in degrees
+ proc_mem_mm_bus_wr(1, integer(g_phase_a * c_diag_wg_phase_unit), mm_clk, reg_wg_mosi_a);
+ -- freq
+ proc_mem_mm_bus_wr(2, integer(g_subband_index_a * c_wg_subband_freq_unit), mm_clk, reg_wg_mosi_a);
+ -- amplitude
+ proc_mem_mm_bus_wr(3, integer(g_amplitude_a * c_diag_wg_ampl_unit), mm_clk, reg_wg_mosi_a);
-- WG-B
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 1, mm_clk, reg_wg_mosi_b); -- mode calc, nof_sample
- proc_mem_mm_bus_wr(1, integer(g_phase_b * c_diag_wg_phase_unit), mm_clk, reg_wg_mosi_b); -- phase offset in degrees
- proc_mem_mm_bus_wr(2, integer(g_subband_index_b * c_wg_subband_freq_unit), mm_clk, reg_wg_mosi_b); -- freq
- proc_mem_mm_bus_wr(3, integer(g_amplitude_b * c_diag_wg_ampl_unit), mm_clk, reg_wg_mosi_b); -- amplitude
+ -- mode calc, nof_sample
+ proc_mem_mm_bus_wr(0, 1024 * 2**16 + 1, mm_clk, reg_wg_mosi_b);
+ -- phase offset in degrees
+ proc_mem_mm_bus_wr(1, integer(g_phase_b * c_diag_wg_phase_unit), mm_clk, reg_wg_mosi_b);
+ -- freq
+ proc_mem_mm_bus_wr(2, integer(g_subband_index_b * c_wg_subband_freq_unit), mm_clk, reg_wg_mosi_b);
+ -- amplitude
+ proc_mem_mm_bus_wr(3, integer(g_amplitude_b * c_diag_wg_ampl_unit), mm_clk, reg_wg_mosi_b);
-- Start WG
proc_common_wait_some_cycles(dp_clk, 10);
@@ -674,7 +831,8 @@ begin
if bs_sosi.eop = '1' then
-- raise impulse for one block
if impulse_cnt = 0 then
- impulse_data <= TO_SVEC(2**(c_W_adc - 2), c_W_adc); -- 0.5 * full scale impulse that will be active at sop (= after eop)
+ -- 0.5 * full scale impulse that will be active at sop (= after eop)
+ impulse_data <= TO_SVEC(2**(c_W_adc - 2), c_W_adc);
else
impulse_data <= TO_SVEC(0, c_W_adc);
end if;
@@ -698,8 +856,10 @@ begin
in_sosi.im <= TO_DP_DSP_DATA(0);
else
-- Use WG data
- in_sosi.re <= RESIZE_DP_DSP_DATA(wg_sosi_a_arr(0).data); -- A via real input
- in_sosi.im <= RESIZE_DP_DSP_DATA(wg_sosi_b_arr(0).data); -- B via imag input
+ -- A via real input
+ in_sosi.re <= RESIZE_DP_DSP_DATA(wg_sosi_a_arr(0).data);
+ -- B via imag input
+ in_sosi.im <= RESIZE_DP_DSP_DATA(wg_sosi_b_arr(0).data);
end if;
end process;
@@ -830,8 +990,10 @@ begin
---------------------------------------------------------------------------
-- Measure FIR filter output mean (DC) and power, and determine sine amplitude
---------------------------------------------------------------------------
- proc_diag_measure_cw_statistics(c_N_samples, dp_clk, fil_sosi.re, fil_sosi.sync, fil_sosi.valid, fir_track_max_a, fir_track_min_a, fir_accum_mean_a, fir_accum_power_a, fir_max_a, fir_min_a, fir_mean_a, fir_power_a, fir_ampl_a); -- use fir_ to distinguish from similar fil_ signal
- proc_diag_measure_cw_statistics(c_N_samples, dp_clk, fil_sosi.im, fil_sosi.sync, fil_sosi.valid, fir_track_max_b, fir_track_min_b, fir_accum_mean_b, fir_accum_power_b, fir_max_b, fir_min_b, fir_mean_b, fir_power_b, fir_ampl_b); -- use fir_ to distinguish from similar fil_ signal
+ -- use fir_ to distinguish from similar fil_ signal
+ proc_diag_measure_cw_statistics(c_N_samples, dp_clk, fil_sosi.re, fil_sosi.sync, fil_sosi.valid, fir_track_max_a, fir_track_min_a, fir_accum_mean_a, fir_accum_power_a, fir_max_a, fir_min_a, fir_mean_a, fir_power_a, fir_ampl_a);
+ -- use fir_ to distinguish from similar fil_ signal
+ proc_diag_measure_cw_statistics(c_N_samples, dp_clk, fil_sosi.im, fil_sosi.sync, fil_sosi.valid, fir_track_max_b, fir_track_min_b, fir_accum_mean_b, fir_accum_power_b, fir_max_b, fir_min_b, fir_mean_b, fir_power_b, fir_ampl_b);
---------------------------------------------------------------------------
-- Measure FIR filter output amplitude and phase using local I = sin and Q = cos
@@ -863,7 +1025,8 @@ begin
-- . copied from tb_lofar2_unb2b_filterbank.vhd
---------------------------------------------------------------------------
p_read_sst : process
- variable v_W, v_T, v_U, v_S, v_B : natural; -- array indicies
+ -- array indicies
+ variable v_W, v_T, v_U, v_S, v_B : natural;
variable v_sst_noise : real;
variable v_gain : real;
begin
@@ -965,7 +1128,8 @@ begin
---------------------------------------------------------------------------
-- Report
---------------------------------------------------------------------------
- proc_common_wait_some_cycles(dp_clk, g_tb_index); -- use g_tb_index to identify and separate logging in case of multiple tb instances finishing in parallel
+ -- use g_tb_index to identify and separate logging in case of multiple tb instances finishing in parallel
+ proc_common_wait_some_cycles(dp_clk, g_tb_index);
if g_sel_pfb = "WPFB" then
print_str(" -- -----------------------------------------------------------");
print_str(" -- WPFB settings of tb-" & int_to_str(g_tb_index) & ":");
@@ -1036,7 +1200,8 @@ begin
print_str(". sst_wg_power_a = " & real_to_str(sst_wg_power_a, 15, 3) & " = " & real_to_str(sst_wg_power_a_dB, 7, 2) & " [dB]");
print_str(". sst_wg_power_a/c_exp_sst_a = " & real_to_str(sst_wg_power_a / c_exp_sst_a, 10, 6));
print_str(". sst_noise_a = " & real_to_str(sst_noise_a, 15, 3) & " = " & real_to_str(sst_noise_a_dB, 7, 2) & " [dB]");
- print_str(". sst_noise_b = " & real_to_str(sst_noise_b, 15, 3) & " = " & real_to_str(sst_noise_b_dB, 7, 2) & " [dB]"); -- FFT cross talk power from a to b (if g_amplitude_b = 0)
+ -- FFT cross talk power from a to b (if g_amplitude_b = 0)
+ print_str(". sst_noise_b = " & real_to_str(sst_noise_b, 15, 3) & " = " & real_to_str(sst_noise_b_dB, 7, 2) & " [dB]");
print_str("");
print_str("SNR and WPFB processing gain:");
print_str(". c_wg_snr_a_dB = " & real_to_str(c_wg_snr_a_dB, 7, 2) & " [dB]");
@@ -1080,7 +1245,8 @@ begin
print_str(". sst_wg_power_b = " & real_to_str(sst_wg_power_b, 15, 3) & " = " & real_to_str(sst_wg_power_b_dB, 7, 2) & " [dB]");
print_str(". sst_wg_power_b/c_exp_sst_b = " & real_to_str(sst_wg_power_b / c_exp_sst_b, 10, 6));
print_str(". sst_noise_b = " & real_to_str(sst_noise_b, 15, 3) & " = " & real_to_str(sst_noise_b_dB, 7, 2) & " [dB]");
- print_str(". sst_noise_a = " & real_to_str(sst_noise_a, 15, 3) & " = " & real_to_str(sst_noise_a_dB, 7, 2) & " [dB]"); -- FFT cross talk power from b to a (if g_amplitude_a = 0)
+ -- FFT cross talk power from b to a (if g_amplitude_a = 0)
+ print_str(". sst_noise_a = " & real_to_str(sst_noise_a, 15, 3) & " = " & real_to_str(sst_noise_a_dB, 7, 2) & " [dB]");
print_str("");
print_str("SNR and WPFB processing gain:");
print_str(". c_wg_snr_b_dB = " & real_to_str(c_wg_snr_b_dB, 7, 2) & " [dB]");
@@ -1142,7 +1308,8 @@ begin
dut_pfb2_unit : if g_sel_pfb = "PFB2" generate
u_pfb2_unit : entity pfb2_lib.pfb2_unit
generic map (
- g_nof_streams => 1, -- number of pfb2 instances, 1 pfb2 per stream
+ -- number of pfb2 instances, 1 pfb2 per stream
+ g_nof_streams => 1,
g_nof_points => c_wpfb.nof_points,
-- pfs
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd
index 0d717d9f4d2487538b533a52ee31fb12acf38d42..f3209a17d79717afd72d1715e56e2be41f3d6b46 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd
@@ -31,42 +31,66 @@ package wpfb_pkg is
-- Parameters for the (wideband) poly phase filter.
type t_wpfb is record
-- General parameters for the wideband poly phase filter
- wb_factor : natural; -- = default 4, wideband factor
- nof_points : natural; -- = 1024, N point FFT (Also the number of subbands for the filter part)
- nof_chan : natural; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
- nof_wb_streams : natural; -- = 1, the number of parallel wideband streams. The filter coefficients are shared on every wb-stream.
+ -- = default 4, wideband factor
+ wb_factor : natural;
+ -- = 1024, N point FFT (Also the number of subbands for the filter part)
+ nof_points : natural;
+ -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
+ nof_chan : natural;
+ -- = 1, the number of parallel wideband streams. The filter coefficients are shared on every wb-stream.
+ nof_wb_streams : natural;
-- Parameters for the poly phase filter
- nof_taps : natural; -- = 16, the number of FIR taps per subband
- fil_backoff_w : natural; -- = 0, number of bits for input backoff to avoid output overflow
- fil_in_dat_w : natural; -- = 8, number of input bits
- fil_out_dat_w : natural; -- = 16, number of output bits
- coef_dat_w : natural; -- = 16, data width of the FIR coefficients
+ -- = 16, the number of FIR taps per subband
+ nof_taps : natural;
+ -- = 0, number of bits for input backoff to avoid output overflow
+ fil_backoff_w : natural;
+ -- = 8, number of input bits
+ fil_in_dat_w : natural;
+ -- = 16, number of output bits
+ fil_out_dat_w : natural;
+ -- = 16, data width of the FIR coefficients
+ coef_dat_w : natural;
-- Parameters for the FFT
- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
- use_fft_shift : boolean; -- = false for [0, pos, neg] bin frequencies order, true for [neg, 0, pos] bin frequencies order in case of complex input
- use_separate : boolean; -- = false for complex input, true for two real inputs
- fft_in_dat_w : natural; -- = 16, number of input bits
- fft_out_dat_w : natural; -- = 16, number of output bits >= (fil_in_dat_w=8) + log2(nof_points=1024)/2 = 13
- fft_out_gain_w : natural; -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
- stage_dat_w : natural; -- = 18, number of bits that are used inter-stage
- guard_w : natural; -- = 2, guard used to avoid overflow in first FFT stage, compensated in last guard_w nof FFT stages.
+ -- = false for bit-reversed output, true for normal output
+ use_reorder : boolean;
+ -- = false for [0, pos, neg] bin frequencies order, true for [neg, 0, pos] bin frequencies order in case of complex input
+ use_fft_shift : boolean;
+ -- = false for complex input, true for two real inputs
+ use_separate : boolean;
+ -- = 16, number of input bits
+ fft_in_dat_w : natural;
+ -- = 16, number of output bits >= (fil_in_dat_w=8) + log2(nof_points=1024)/2 = 13
+ fft_out_dat_w : natural;
+ -- = 0, output gain factor applied after the last stage output, before requantization to out_dat_w
+ fft_out_gain_w : natural;
+ -- = 18, number of bits that are used inter-stage
+ stage_dat_w : natural;
+ -- = 2, guard used to avoid overflow in first FFT stage, compensated in last guard_w nof FFT stages.
+ guard_w : natural;
-- on average the gain per stage is 2 so guard_w = 1, but the gain can be 1+sqrt(2) [Lyons section
-- 12.3.2], therefore use input guard_w = 2.
- guard_enable : boolean; -- = true when input needs guarding, false when input requires no guarding but scaling must be
+ -- = true when input needs guarding, false when input requires no guarding but scaling must be
+ guard_enable : boolean;
-- skipped at the last stage(s) compensate for input guard (used in wb fft with pipe fft section
-- doing the input guard and par fft section doing the output compensation)
-- Parameters for the statistics
- stat_data_w : positive; -- = 56
- stat_data_sz : positive; -- = 2
- nof_blk_per_sync : natural; -- = 800000, number of FFT output blocks per sync interval, used to pass on BSN
+ -- = 56
+ stat_data_w : positive;
+ -- = 2
+ stat_data_sz : positive;
+ -- = 800000, number of FFT output blocks per sync interval, used to pass on BSN
+ nof_blk_per_sync : natural;
-- Pipeline parameters for both poly phase filter and FFT. These are heritaged from the filter and fft libraries.
- pft_pipeline : t_fft_pipeline; -- Pipeline settings for the pipelined FFT
- fft_pipeline : t_fft_pipeline; -- Pipeline settings for the parallel FFT
- fil_pipeline : t_fil_ppf_pipeline; -- Pipeline settings for the filter units
+ -- Pipeline settings for the pipelined FFT
+ pft_pipeline : t_fft_pipeline;
+ -- Pipeline settings for the parallel FFT
+ fft_pipeline : t_fft_pipeline;
+ -- Pipeline settings for the filter units
+ fil_pipeline : t_fil_ppf_pipeline;
end record;
-----------------------------------------------------------------------------
@@ -273,7 +297,8 @@ package body wpfb_pkg is
g_wpfb.nof_chan,
g_wpfb.nof_points,
g_wpfb.nof_taps,
- c_nof_complex * g_wpfb.nof_wb_streams, -- Complex FFT always requires 2 filter streams: real and imaginary
+ -- Complex FFT always requires 2 filter streams: real and imaginary
+ c_nof_complex * g_wpfb.nof_wb_streams,
g_wpfb.fil_backoff_w,
g_wpfb.fil_in_dat_w,
g_wpfb.fil_out_dat_w,
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
index c75f7f8c998e8d62aabd887630cffe9e0e0a1e47..16436f221702a4dda0bf80c5abf565a266e40be5 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
@@ -64,9 +64,11 @@ entity wpfb_unit is
generic (
g_wpfb : t_wpfb;
g_use_prefilter : boolean := true;
- g_stats_ena : boolean := true; -- Enables the statistics unit
+ -- Enables the statistics unit
+ g_stats_ena : boolean := true;
g_use_bg : boolean := false;
- g_coefs_file_prefix : string := "../../../../filter/build/data/coefs_wide" -- File prefix for the coefficients files.
+ -- File prefix for the coefficients files.
+ g_coefs_file_prefix : string := "../../../../filter/build/data/coefs_wide"
);
port (
dp_rst : in std_logic := '0';
@@ -75,7 +77,8 @@ entity wpfb_unit is
mm_clk : in std_logic;
ram_fil_coefs_mosi : in t_mem_mosi;
ram_fil_coefs_miso : out t_mem_miso := c_mem_miso_rst;
- ram_st_sst_mosi : in t_mem_mosi; -- Subband statistics registers
+ -- Subband statistics registers
+ ram_st_sst_mosi : in t_mem_mosi;
ram_st_sst_miso : out t_mem_miso := c_mem_miso_rst;
reg_bg_ctrl_mosi : in t_mem_mosi;
reg_bg_ctrl_miso : out t_mem_miso;
@@ -252,7 +255,8 @@ begin
gen_prep_wide_fft_streams: for I in 0 to g_wpfb.nof_wb_streams - 1 generate
u_fft_wide : entity fft_lib.fft_r2_wide
generic map(
- g_fft => c_fft, -- generics for the WFFT
+ -- generics for the WFFT
+ g_fft => c_fft,
g_pft_pipeline => g_wpfb.pft_pipeline,
g_fft_pipeline => g_wpfb.fft_pipeline
)
@@ -331,7 +335,8 @@ begin
generic map(
g_nof_streams => g_wpfb.nof_wb_streams * g_wpfb.wb_factor,
g_buf_dat_w => c_nof_complex * g_wpfb.fft_out_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => c_bg_data_file_index_arr,
g_file_name_prefix => c_bg_data_file_prefix
)
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
index 3385973b5266d184abde65a7e9c2d86b695ee086..275e82ad02372b47581decae049d8d684fb01fa2 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
@@ -371,11 +371,14 @@ entity wpfb_unit_dev is
generic (
g_big_endian_wb_in : boolean := true;
g_wpfb : t_wpfb;
- g_dont_flip_channels: boolean := false; -- True preserves channel interleaving for pipelined FFT
+ -- True preserves channel interleaving for pipelined FFT
+ g_dont_flip_channels: boolean := false;
g_use_prefilter : boolean := true;
- g_stats_ena : boolean := true; -- Enables the statistics unit
+ -- Enables the statistics unit
+ g_stats_ena : boolean := true;
g_use_bg : boolean := false;
- g_coefs_file_prefix : string := "data/coefs_wide"; -- File prefix for the coefficients files.
+ -- File prefix for the coefficients files.
+ g_coefs_file_prefix : string := "data/coefs_wide";
g_restart_on_valid : boolean := true
);
port (
@@ -385,7 +388,8 @@ entity wpfb_unit_dev is
mm_clk : in std_logic;
ram_fil_coefs_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_fil_coefs_miso : out t_mem_miso;
- ram_st_sst_mosi : in t_mem_mosi := c_mem_mosi_rst; -- Subband statistics registers
+ -- Subband statistics registers
+ ram_st_sst_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_st_sst_miso : out t_mem_miso;
reg_bg_ctrl_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_bg_ctrl_miso : out t_mem_miso;
@@ -533,7 +537,8 @@ begin
u_filter : entity filter_lib.fil_ppf_wide
generic map (
g_big_endian_wb_in => g_big_endian_wb_in,
- g_big_endian_wb_out => false, -- reverse wideband order from big-endian [3:0] = [t0,t1,t2,t3] in fil_ppf_wide to little-endian [3:0] = [t3,t2,t1,t0] in fft_r2_wide
+ -- reverse wideband order from big-endian [3:0] = [t0,t1,t2,t3] in fil_ppf_wide to little-endian [3:0] = [t3,t2,t1,t0] in fft_r2_wide
+ g_big_endian_wb_out => false,
g_fil_ppf => c_fil_ppf,
g_fil_ppf_pipeline => g_wpfb.fil_pipeline,
g_coefs_file_prefix => g_coefs_file_prefix
@@ -567,7 +572,8 @@ begin
gen_fft_r2_wide_streams: for S in 0 to g_wpfb.nof_wb_streams - 1 generate
u_fft_r2_wide : entity fft_lib.fft_r2_wide
generic map(
- g_fft => c_fft, -- generics for the WFFT
+ -- generics for the WFFT
+ g_fft => c_fft,
g_pft_pipeline => g_wpfb.pft_pipeline,
g_fft_pipeline => g_wpfb.fft_pipeline
)
@@ -666,7 +672,8 @@ begin
generic map(
g_nof_streams => g_wpfb.nof_wb_streams * g_wpfb.wb_factor,
g_buf_dat_w => c_nof_complex * g_wpfb.fft_out_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => c_bg_data_file_index_arr,
g_file_name_prefix => c_bg_data_file_prefix
)
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_mmf_wpfb_unit.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_mmf_wpfb_unit.vhd
index 6676271bd0de13aa61cdd46869086ef3a4501560..a64b0a3a2a3a8b033a69917fce29a0d839f45161 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_mmf_wpfb_unit.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_mmf_wpfb_unit.vhd
@@ -69,22 +69,32 @@ use work.wpfb_pkg.all;
entity tb_mmf_wpfb_unit is
generic(
- g_wb_factor : natural := 1; -- = default 1, wideband factor
- g_nof_wb_streams : natural := 1; -- = 1, the number of parallel wideband streams. The filter coefficients are shared on every wb-stream.
- g_nof_chan : natural := 0; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
- g_nof_points : natural := 64; -- = 1024, N point FFT
- g_nof_taps : natural := 16; -- = 8 nof taps n the filter
- g_nof_blocks : natural := 4; -- = 4, the number of blocks of g_nof_points each in the BG waveform (must be power of 2 due to that BG c_bg_block_len must be power of 2)
- g_in_dat_w : natural := 8; -- = 8, number of input bits
- g_out_dat_w : natural := 16; -- = 14, number of output bits: in_dat_w + natural((ceil_log2(nof_points))/2)
- g_use_separate : boolean := false; -- = false for complex input, true for two real inputs
+ -- = default 1, wideband factor
+ g_wb_factor : natural := 1;
+ -- = 1, the number of parallel wideband streams. The filter coefficients are shared on every wb-stream.
+ g_nof_wb_streams : natural := 1;
+ -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
+ g_nof_chan : natural := 0;
+ -- = 1024, N point FFT
+ g_nof_points : natural := 64;
+ -- = 8 nof taps n the filter
+ g_nof_taps : natural := 16;
+ -- = 4, the number of blocks of g_nof_points each in the BG waveform (must be power of 2 due to that BG c_bg_block_len must be power of 2)
+ g_nof_blocks : natural := 4;
+ -- = 8, number of input bits
+ g_in_dat_w : natural := 8;
+ -- = 14, number of output bits: in_dat_w + natural((ceil_log2(nof_points))/2)
+ g_out_dat_w : natural := 16;
+ -- = false for complex input, true for two real inputs
+ g_use_separate : boolean := false;
g_use_bg : boolean := false;
g_coefs_file_prefix : string := "data/coefs_wide"
);
end tb_mmf_wpfb_unit;
architecture tb of tb_mmf_wpfb_unit is
- constant c_in_backoff_w : natural := 0; -- = 0, number of bits for input backoff to avoid FIR output overflow
+ -- = 0, number of bits for input backoff to avoid FIR output overflow
+ constant c_in_backoff_w : natural := 0;
constant c_nof_blk_per_sync : natural := 20;
constant c_wpfb : t_wpfb := (g_wb_factor, g_nof_points, g_nof_chan, g_nof_wb_streams,
@@ -266,7 +276,8 @@ begin
generic map(
g_nof_streams => c_nof_streams,
g_buf_dat_w => c_nof_complex * c_wpfb.fil_in_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => c_bg_data_file_index_arr,
g_file_name_prefix => c_bg_data_file_prefix
)
@@ -332,7 +343,8 @@ begin
);
time_map : process is
- variable sim_time_str_v : string(1 to 30); -- 30 chars should be enough
+ -- 30 chars should be enough
+ variable sim_time_str_v : string(1 to 30);
variable sim_time_len_v : natural;
begin
wait for 1000 ns;
@@ -372,8 +384,10 @@ begin
end if;
end if;
end process;
- scope_out_bin <= fft_index_to_bin_frequency(c_wpfb.wb_factor, c_wpfb.nof_points, scope_out_index, true, false, true); -- complex bin
- scope_out_band <= fft_index_to_bin_frequency(c_wpfb.wb_factor, c_wpfb.nof_points, scope_out_index, true, true, true); -- two real bin
+ -- complex bin
+ scope_out_bin <= fft_index_to_bin_frequency(c_wpfb.wb_factor, c_wpfb.nof_points, scope_out_index, true, false, true);
+ -- two real bin
+ scope_out_band <= fft_index_to_bin_frequency(c_wpfb.wb_factor, c_wpfb.nof_points, scope_out_index, true, true, true);
scope_out_power <= real(scope_out_sosi(0).re)**2 + real(scope_out_sosi(0).im)**2;
scope_out_ampl <= SQRT(scope_out_power);
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
index 94cf0d06208b7ccc50ed2d727a10b2dedbb5b471..4f5ce710b19abcb73d8301af86f9a0684223b138 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
@@ -175,39 +175,65 @@ architecture tb of tb_tb_wpfb_unit_wide is
false, false, false, 16, 16, 0, c_dsp_mult_w, 2, true, 56, 2, c_nof_blk_per_sync,
c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
- constant c_dm_1 : natural := 1; -- diff margin (for stage_dat_w >> c_dsp_mult_w)
- constant c_dm_3 : natural := 3; -- diff margin (for 32 point dm=2 appears sufficient, for 1024 point dm=3 is sufficient)
- constant c_dm_5 : natural := 5; -- diff margin (for 32 point dm=2 appears sufficient, for 1024 point dm=3 is sufficient)
+ -- diff margin (for stage_dat_w >> c_dsp_mult_w)
+ constant c_dm_1 : natural := 1;
+ -- diff margin (for 32 point dm=2 appears sufficient, for 1024 point dm=3 is sufficient)
+ constant c_dm_3 : natural := 3;
+ -- diff margin (for 32 point dm=2 appears sufficient, for 1024 point dm=3 is sufficient)
+ constant c_dm_5 : natural := 5;
- constant c_pre_ab : string := "data/run_pfb_m_pfir_coeff_fircls1"; -- original version
- constant c_pre_ab_v2 : string := "data/run_pfb_m_v2_pfir_coeff_fircls1"; -- next version
+ -- original version
+ constant c_pre_ab : string := "data/run_pfb_m_pfir_coeff_fircls1";
+ -- next version
+ constant c_pre_ab_v2 : string := "data/run_pfb_m_v2_pfir_coeff_fircls1";
constant c_pre_c : string := "data/run_pfb_complex_m_pfir_coeff_fircls1";
-- Real input
- constant c_sinusoid_chirp_1024 : string := "data/run_pfb_m_sinusoid_chirp_8b_16taps_1024points_16b_16b.dat"; -- 204800 lines
- constant c_sinusoid_chirp : string := "data/run_pfb_m_sinusoid_chirp_8b_16taps_32points_16b_16b.dat"; -- 6400 lines
- constant c_sinusoid_1024 : string := "data/run_pfb_m_sinusoid_8b_16taps_1024points_16b_16b.dat"; -- 51200 lines
- constant c_sinusoid_1024_v2 : string := "data/run_pfb_m_v2_sinusoid_8b_16taps_1024points_16b_16b.dat"; -- 51200 lines
- constant c_sinusoid : string := "data/run_pfb_m_sinusoid_8b_16taps_32points_16b_16b.dat"; -- 1600 lines
- constant c_impulse_chirp : string := "data/run_pfb_m_impulse_chirp_8b_16taps_32points_16b_16b.dat"; -- 6400 lines
- constant c_noise_1024 : string := "data/run_pfb_m_noise_8b_16taps_1024points_16b_16b.dat"; -- 51200 lines
- constant c_noise : string := "data/run_pfb_m_noise_8b_16taps_32points_16b_16b.dat"; -- 1600 lines
- constant c_dc_agwn : string := "data/run_pfb_m_dc_agwn_8b_16taps_32points_16b_16b.dat"; -- 1600 lines
+ -- 204800 lines
+ constant c_sinusoid_chirp_1024 : string := "data/run_pfb_m_sinusoid_chirp_8b_16taps_1024points_16b_16b.dat";
+ -- 6400 lines
+ constant c_sinusoid_chirp : string := "data/run_pfb_m_sinusoid_chirp_8b_16taps_32points_16b_16b.dat";
+ -- 51200 lines
+ constant c_sinusoid_1024 : string := "data/run_pfb_m_sinusoid_8b_16taps_1024points_16b_16b.dat";
+ -- 51200 lines
+ constant c_sinusoid_1024_v2 : string := "data/run_pfb_m_v2_sinusoid_8b_16taps_1024points_16b_16b.dat";
+ -- 1600 lines
+ constant c_sinusoid : string := "data/run_pfb_m_sinusoid_8b_16taps_32points_16b_16b.dat";
+ -- 6400 lines
+ constant c_impulse_chirp : string := "data/run_pfb_m_impulse_chirp_8b_16taps_32points_16b_16b.dat";
+ -- 51200 lines
+ constant c_noise_1024 : string := "data/run_pfb_m_noise_8b_16taps_1024points_16b_16b.dat";
+ -- 1600 lines
+ constant c_noise : string := "data/run_pfb_m_noise_8b_16taps_32points_16b_16b.dat";
+ -- 1600 lines
+ constant c_dc_agwn : string := "data/run_pfb_m_dc_agwn_8b_16taps_32points_16b_16b.dat";
-- Complex input
- constant c_phasor_chirp_1024 : string := "data/run_pfb_complex_m_phasor_chirp_8b_16taps_1024points_16b_16b.dat"; -- 204800 lines
- constant c_phasor_chirp_128 : string := "data/run_pfb_complex_m_phasor_chirp_8b_16taps_128points_16b_16b.dat"; -- 25600 lines
- constant c_phasor_chirp_64 : string := "data/run_pfb_complex_m_phasor_chirp_8b_16taps_64points_16b_16b.dat"; -- 12800 lines
- constant c_phasor_chirp : string := "data/run_pfb_complex_m_phasor_chirp_8b_16taps_32points_16b_16b.dat"; -- 6400 lines
- constant c_phasor : string := "data/run_pfb_complex_m_phasor_8b_16taps_32points_16b_16b.dat"; -- 1600 lines
- constant c_noise_complex_1024 : string := "data/run_pfb_complex_m_noise_complex_8b_16taps_1024points_16b_16b.dat"; -- 51200 lines
- constant c_noise_complex_128 : string := "data/run_pfb_complex_m_noise_complex_8b_16taps_128points_16b_16b.dat"; -- 6400 lines
- constant c_noise_complex_64 : string := "data/run_pfb_complex_m_noise_complex_8b_16taps_64points_16b_16b.dat"; -- 3200 lines
- constant c_noise_complex : string := "data/run_pfb_complex_m_noise_complex_8b_16taps_32points_16b_16b.dat"; -- 1600 lines
+ -- 204800 lines
+ constant c_phasor_chirp_1024 : string := "data/run_pfb_complex_m_phasor_chirp_8b_16taps_1024points_16b_16b.dat";
+ -- 25600 lines
+ constant c_phasor_chirp_128 : string := "data/run_pfb_complex_m_phasor_chirp_8b_16taps_128points_16b_16b.dat";
+ -- 12800 lines
+ constant c_phasor_chirp_64 : string := "data/run_pfb_complex_m_phasor_chirp_8b_16taps_64points_16b_16b.dat";
+ -- 6400 lines
+ constant c_phasor_chirp : string := "data/run_pfb_complex_m_phasor_chirp_8b_16taps_32points_16b_16b.dat";
+ -- 1600 lines
+ constant c_phasor : string := "data/run_pfb_complex_m_phasor_8b_16taps_32points_16b_16b.dat";
+ -- 51200 lines
+ constant c_noise_complex_1024 : string := "data/run_pfb_complex_m_noise_complex_8b_16taps_1024points_16b_16b.dat";
+ -- 6400 lines
+ constant c_noise_complex_128 : string := "data/run_pfb_complex_m_noise_complex_8b_16taps_128points_16b_16b.dat";
+ -- 3200 lines
+ constant c_noise_complex_64 : string := "data/run_pfb_complex_m_noise_complex_8b_16taps_64points_16b_16b.dat";
+ -- 1600 lines
+ constant c_noise_complex : string := "data/run_pfb_complex_m_noise_complex_8b_16taps_32points_16b_16b.dat";
-- Zero input
- constant c_zero : string := "UNUSED"; -- zero's data
- constant c_un : string := "UNUSED"; -- zero's data
+ -- zero's data
+ constant c_zero : string := "UNUSED";
+ -- zero's data
+ constant c_un : string := "UNUSED";
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- DUT generics
-- g_wpfb : t_wpfb := (4, 32, 0, 1,
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd
index c8be3118e2f27f0620b78c0b61b8bc9a4027507a..2de0af0a0735d4f4fd9cdabae84cc3266120324b 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd
@@ -137,7 +137,8 @@ architecture tb of tb_wpfb_unit is
-- input/output data width
constant c_in_dat_w : natural := g_wpfb.fil_in_dat_w;
constant c_twiddle_w : natural := 16;
- constant c_out_dat_w : natural := g_wpfb.fft_out_dat_w; -- g_rtwo_fft.in_dat_w + natural((ceil_log2(g_rtwo_fft.nof_points))/2 + 2); -- bit growth
+ -- g_rtwo_fft.in_dat_w + natural((ceil_log2(g_rtwo_fft.nof_points))/2 + 2); -- bit growth
+ constant c_out_dat_w : natural := g_wpfb.fft_out_dat_w;
-- input/output files
constant c_nof_spectra_in_file : natural := 8;
@@ -148,7 +149,8 @@ architecture tb of tb_wpfb_unit is
constant c_bg_mem_size : natural := g_wpfb.nof_points / g_wpfb.wb_factor;
constant c_bg_addr_w : natural := ceil_log2(c_bg_mem_size);
constant c_nof_samples_in_packet : natural := c_bg_mem_size;
- constant c_gap : natural := 0; -- Gapsize is set to 0 in order to generate a continuous stream of packets.
+ -- Gapsize is set to 0 in order to generate a continuous stream of packets.
+ constant c_gap : natural := 0;
constant c_nof_accum_per_sync : natural := g_wpfb.nof_blk_per_sync;
constant c_bsn_init : natural := 32;
constant c_bg_prefix : string := "UNUSED";
@@ -181,11 +183,13 @@ architecture tb of tb_wpfb_unit is
signal out_re_arr : t_fft_slv_arr(g_wpfb.wb_factor - 1 downto 0);
signal out_im_arr : t_fft_slv_arr(g_wpfb.wb_factor - 1 downto 0);
- signal in_file_data : t_integer_matrix(0 to c_file_len - 1, 1 to 2) := (others => (others => 0)); -- [re, im]
+ -- [re, im]
+ signal in_file_data : t_integer_matrix(0 to c_file_len - 1, 1 to 2) := (others => (others => 0));
signal in_file_sync : std_logic_vector(0 to c_file_len - 1) := (others => '0');
signal in_file_val : std_logic_vector(0 to c_file_len - 1) := (others => '0');
- signal gold_file_data : t_integer_matrix(0 to c_file_len - 1, 1 to 2) := (others => (others => 0)); -- [re, im]
+ -- [re, im]
+ signal gold_file_data : t_integer_matrix(0 to c_file_len - 1, 1 to 2) := (others => (others => 0));
signal gold_file_sync : std_logic_vector(0 to c_file_len - 1) := (others => '0');
signal gold_file_val : std_logic_vector(0 to c_file_len - 1) := (others => '0');
@@ -241,27 +245,32 @@ begin
p_coefs_memory_write : process
begin
coefs_mem_write <= false;
- ram_coefs_mosi <= c_mem_mosi_rst; -- Reset the master out interface
+ -- Reset the master out interface
+ ram_coefs_mosi <= c_mem_mosi_rst;
-- Write the coefficients
- for L in 0 to c_nof_complex loop -- There are two filters in the DUT: real and imaginary
+ -- There are two filters in the DUT: real and imaginary
+ for L in 0 to c_nof_complex loop
for K in 0 to g_wpfb.wb_factor - 1 loop
for J in 0 to g_wpfb.nof_taps - 1 loop
proc_common_read_mif_file(c_coefs_file_prefix & "_" & integer'image(k * g_wpfb.nof_taps + J) & ".mif", coefs_arr);
wait for 1 ns;
for I in 0 to c_nof_bands_per_chn - 1 loop
- proc_mem_mm_bus_wr(L * g_wpfb.nof_points * g_wpfb.nof_taps + K * c_nof_bands_per_chn * g_wpfb.nof_taps + J * c_nof_bands_per_chn + I, coefs_arr(I), clk, ram_coefs_mosi); -- Write the coefficient to the memory
+ -- Write the coefficient to the memory
+ proc_mem_mm_bus_wr(L * g_wpfb.nof_points * g_wpfb.nof_taps + K * c_nof_bands_per_chn * g_wpfb.nof_taps + J * c_nof_bands_per_chn + I, coefs_arr(I), clk, ram_coefs_mosi);
end loop;
end loop;
end loop;
end loop;
-- Read the coefficients back and verify
- for L in 0 to c_nof_complex loop -- There are two filters in the DUT: real and imaginary
+ -- There are two filters in the DUT: real and imaginary
+ for L in 0 to c_nof_complex loop
for K in 0 to g_wpfb.wb_factor - 1 loop
for J in 0 to g_wpfb.nof_taps - 1 loop
proc_common_read_mif_file(c_coefs_file_prefix & "_" & integer'image(k * g_wpfb.nof_taps + J) & ".mif", coefs_arr);
wait for 1 ns;
for I in 0 to c_nof_bands_per_chn - 1 loop
- proc_mem_mm_bus_rd(L * g_wpfb.nof_points * g_wpfb.nof_taps + K * c_nof_bands_per_chn * g_wpfb.nof_taps + J * c_nof_bands_per_chn + I, clk, ram_coefs_miso, ram_coefs_mosi); -- Read the coefficient from the memory
+ -- Read the coefficient from the memory
+ proc_mem_mm_bus_rd(L * g_wpfb.nof_points * g_wpfb.nof_taps + K * c_nof_bands_per_chn * g_wpfb.nof_taps + J * c_nof_bands_per_chn + I, clk, ram_coefs_miso, ram_coefs_mosi);
temp_reg <= coefs_arr(I);
if(ram_coefs_miso.rdval = '1') then
assert temp_reg = TO_UINT(ram_coefs_miso.rddata(g_wpfb.coef_dat_w - 1 downto 0)) report "Read data from memory error" severity error;
@@ -290,8 +299,10 @@ begin
begin
init_waveforms_done <= '0';
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
+ -- Wait until reset has finished
+ proc_common_wait_until_low(clk, rst);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(clk, 10);
for J in 0 to c_bg_mem_size-1 loop
v_mem_data := (others => '0');
@@ -314,18 +325,28 @@ begin
-- Wait until reset is done
proc_common_wait_until_high(clk, rst);
proc_common_wait_some_cycles(clk, 10);
- wait until init_waveforms_done = '1'; -- Wait until the waveform data is written.
- wait until coefs_mem_write = true; -- Wait until the coefficients are written.
+ -- Wait until the waveform data is written.
+ wait until init_waveforms_done = '1';
+ -- Wait until the coefficients are written.
+ wait until coefs_mem_write = true;
-- Set and enable the waveform generators. All generators are controlled by the same registers
- proc_mem_mm_bus_wr(1, c_nof_samples_in_packet, clk, reg_bg_ctrl_mosi); -- Set the number of samples per block
- proc_mem_mm_bus_wr(2, c_nof_accum_per_sync, clk, reg_bg_ctrl_mosi); -- Set the number of blocks per sync
- proc_mem_mm_bus_wr(3, c_gap, clk, reg_bg_ctrl_mosi); -- Set the gapsize
- proc_mem_mm_bus_wr(4, 0, clk, reg_bg_ctrl_mosi); -- Set the start address of the memory
- proc_mem_mm_bus_wr(5, c_bg_mem_size-1, clk, reg_bg_ctrl_mosi); -- Set the end address of the memory
- proc_mem_mm_bus_wr(6, c_bsn_init, clk, reg_bg_ctrl_mosi); -- Set the BSNInit low value
- proc_mem_mm_bus_wr(7, 0, clk, reg_bg_ctrl_mosi); -- Set the BSNInit high value
- proc_mem_mm_bus_wr(0, 1, clk, reg_bg_ctrl_mosi); -- Enable the BG
+ -- Set the number of samples per block
+ proc_mem_mm_bus_wr(1, c_nof_samples_in_packet, clk, reg_bg_ctrl_mosi);
+ -- Set the number of blocks per sync
+ proc_mem_mm_bus_wr(2, c_nof_accum_per_sync, clk, reg_bg_ctrl_mosi);
+ -- Set the gapsize
+ proc_mem_mm_bus_wr(3, c_gap, clk, reg_bg_ctrl_mosi);
+ -- Set the start address of the memory
+ proc_mem_mm_bus_wr(4, 0, clk, reg_bg_ctrl_mosi);
+ -- Set the end address of the memory
+ proc_mem_mm_bus_wr(5, c_bg_mem_size-1, clk, reg_bg_ctrl_mosi);
+ -- Set the BSNInit low value
+ proc_mem_mm_bus_wr(6, c_bsn_init, clk, reg_bg_ctrl_mosi);
+ -- Set the BSNInit high value
+ proc_mem_mm_bus_wr(7, 0, clk, reg_bg_ctrl_mosi);
+ -- Enable the BG
+ proc_mem_mm_bus_wr(0, 1, clk, reg_bg_ctrl_mosi);
-- Run time is defined by:
-- * the number of sync periods
@@ -380,7 +401,8 @@ begin
p_read_sst_memory : process
variable c_sync_cnt : natural;
begin
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
+ -- Wait until reset has finished
+ proc_common_wait_until_low(clk, rst);
-- Skip reading for the initial syncs to save simulation time
for J in 0 to c_bst_skip_nof_sync - 2 loop
@@ -394,7 +416,8 @@ begin
for I in 0 to g_wpfb.wb_factor - 1 loop
proc_fft_read_subband_statistics_memory(I, c_fft, clk, ram_sst_mosi, ram_sst_miso, result_sst_arr_temp);
- result_sst_arr((I + 1) * c_nof_samples_in_packet - 1 downto I * c_nof_samples_in_packet) <= result_sst_arr_temp; -- can not use result_bst_arr2(I) directly as argument in proc_bf_read_beamlet_statistics_memory()
+ -- can not use result_bst_arr2(I) directly as argument in proc_bf_read_beamlet_statistics_memory()
+ result_sst_arr((I + 1) * c_nof_samples_in_packet - 1 downto I * c_nof_samples_in_packet) <= result_sst_arr_temp;
end loop;
proc_common_wait_some_cycles(clk, 10);
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd
index bfc0eef5a84346339fd0688ec61a74ddbf48c315..bec4f886c41b532f4ad2bb918d900584715ac789 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd
@@ -69,16 +69,26 @@ use work.wpfb_pkg.all;
entity tb_wpfb_unit_dev is
generic(
- g_wb_factor : natural := 1; -- = default 1, wideband factor
- g_nof_wb_streams : natural := 1; -- = 1, the number of parallel wideband streams. The filter coefficients are shared on every wb-stream.
- g_nof_chan : natural := 0; -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
- g_nof_points : natural := 64; -- = 1024, N point FFT
- g_nof_taps : natural := 8; -- = 8 nof taps n the filter
- g_nof_blocks : natural := 4; -- = 4, the number of blocks of g_nof_points each in the BG waveform (must be power of 2 due to that BG c_bg_block_len must be power of 2)
- g_in_dat_w : natural := 8; -- = 8, number of input bits
- g_out_dat_w : natural := 16; -- = 14, number of output bits: in_dat_w + natural((ceil_log2(nof_points))/2)
- g_use_prefilter : boolean := false; -- TRUE;
- g_use_separate : boolean := false; -- = false for complex input, true for two real inputs
+ -- = default 1, wideband factor
+ g_wb_factor : natural := 1;
+ -- = 1, the number of parallel wideband streams. The filter coefficients are shared on every wb-stream.
+ g_nof_wb_streams : natural := 1;
+ -- = default 0, defines the number of channels (=time-multiplexed input signals): nof channels = 2**nof_chan
+ g_nof_chan : natural := 0;
+ -- = 1024, N point FFT
+ g_nof_points : natural := 64;
+ -- = 8 nof taps n the filter
+ g_nof_taps : natural := 8;
+ -- = 4, the number of blocks of g_nof_points each in the BG waveform (must be power of 2 due to that BG c_bg_block_len must be power of 2)
+ g_nof_blocks : natural := 4;
+ -- = 8, number of input bits
+ g_in_dat_w : natural := 8;
+ -- = 14, number of output bits: in_dat_w + natural((ceil_log2(nof_points))/2)
+ g_out_dat_w : natural := 16;
+ -- TRUE;
+ g_use_prefilter : boolean := false;
+ -- = false for complex input, true for two real inputs
+ g_use_separate : boolean := false;
g_use_bg : boolean := false;
g_coefs_file_prefix : string := "hex/chan_fil_coefs_wide"
);
@@ -262,7 +272,8 @@ begin
generic map(
g_nof_streams => c_nof_streams,
g_buf_dat_w => c_nof_complex * c_wpfb.fil_in_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => c_bg_data_file_index_arr,
g_file_name_prefix => c_bg_data_file_prefix
)
@@ -330,7 +341,8 @@ begin
);
time_map : process is
- variable sim_time_str_v : string(1 to 30); -- 30 chars should be enough
+ -- 30 chars should be enough
+ variable sim_time_str_v : string(1 to 30);
variable sim_time_len_v : natural;
begin
wait for 1000 ns;
@@ -370,8 +382,10 @@ begin
end if;
end if;
end process;
- scope_out_bin <= fft_index_to_bin_frequency(c_wpfb.wb_factor, c_wpfb.nof_points, scope_out_index, true, false, true); -- complex bin
- scope_out_band <= fft_index_to_bin_frequency(c_wpfb.wb_factor, c_wpfb.nof_points, scope_out_index, true, true, true); -- two real bin
+ -- complex bin
+ scope_out_bin <= fft_index_to_bin_frequency(c_wpfb.wb_factor, c_wpfb.nof_points, scope_out_index, true, false, true);
+ -- two real bin
+ scope_out_band <= fft_index_to_bin_frequency(c_wpfb.wb_factor, c_wpfb.nof_points, scope_out_index, true, true, true);
scope_out_power <= real(scope_out_sosi(0).re)**2 + real(scope_out_sosi(0).im)**2;
scope_out_ampl <= SQRT(scope_out_power);
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
index bcccc8f0fa31e1664aae2e7e1243f84cd18db896..1ae92d7e56579836a1e1528edda891dec9d0fea6 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
@@ -107,7 +107,8 @@ entity tb_wpfb_unit_wide is
-- end record;
-- TB generics
- g_diff_margin : integer := 5; -- maximum difference between HDL output and expected output (> 0 to allow minor rounding differences)
+ -- maximum difference between HDL output and expected output (> 0 to allow minor rounding differences)
+ g_diff_margin : integer := 5;
-- for complex diff margin = 3 appears sufficient
-- for two_real diff margin = 5 appears sufficient
-- if stage_dat_w >> 18 >= fft_out_dat_w then g_diff_margin = 1 is sufficient
@@ -151,8 +152,10 @@ entity tb_wpfb_unit_wide is
g_data_file_c : string := "data/run_pfb_complex_m_noise_complex_8b_16taps_32points_16b_16b.dat";
g_data_file_c_nof_lines : natural := 1600;
- g_data_file_nof_lines : natural := 1600; -- actual number of lines with input data to simulate from the data files, must be <= g_data_file_*_nof_lines
- g_enable_in_val_gaps : boolean := false -- when false then in_val flow control active continuously, else with random inactive gaps
+ -- actual number of lines with input data to simulate from the data files, must be <= g_data_file_*_nof_lines
+ g_data_file_nof_lines : natural := 1600;
+ -- when false then in_val flow control active continuously, else with random inactive gaps
+ g_enable_in_val_gaps : boolean := false
);
end entity tb_wpfb_unit_wide;
@@ -165,14 +168,17 @@ architecture tb of tb_wpfb_unit_wide is
constant c_in_complex : boolean := not g_wpfb.use_separate;
constant c_nof_channels : natural := 2**g_wpfb.nof_chan;
- constant c_nof_coefs : natural := g_wpfb.nof_taps * g_wpfb.nof_points; -- nof PFIR coef
+ -- nof PFIR coef
+ constant c_nof_coefs : natural := g_wpfb.nof_taps * g_wpfb.nof_points;
constant c_nof_data_per_block : natural := g_wpfb.nof_points * c_nof_channels;
constant c_nof_valid_per_block : natural := c_nof_data_per_block / g_wpfb.wb_factor;
constant c_rnd_factor : natural := sel_a_b(g_enable_in_val_gaps, 3, 1);
- constant c_dut_block_latency : natural := func_wpfb_maximum_sop_latency(g_wpfb); -- choose large enough for output to have become available
- constant c_dut_clk_latency : natural := c_nof_valid_per_block * c_dut_block_latency * c_rnd_factor; -- worst case
+ -- choose large enough for output to have become available
+ constant c_dut_block_latency : natural := func_wpfb_maximum_sop_latency(g_wpfb);
+ -- worst case
+ constant c_dut_clk_latency : natural := c_nof_valid_per_block * c_dut_block_latency * c_rnd_factor;
-- PFIR coefficients file access
constant c_coefs_dat_file_prefix : string := sel_a_b(c_in_complex, g_coefs_file_prefix_c, g_coefs_file_prefix_ab) &
@@ -188,22 +194,32 @@ architecture tb of tb_wpfb_unit_wide is
-- Data file access (Header + PFIR coefficients + WG data + PFIR data + PFFT data)
constant c_nof_lines_header : natural := 4;
- constant c_nof_lines_pfir_coefs : natural := c_nof_coefs; -- PFIR coefficients
- constant c_nof_lines_a_wg_dat : natural := g_data_file_a_nof_lines; -- Real input A via in_re, one value per line
- constant c_nof_lines_a_pfir_dat : natural := g_data_file_a_nof_lines; -- Real pfir A, one value per line
- constant c_nof_lines_a_pfft_dat : natural := g_data_file_a_nof_lines / c_nof_complex; -- Half spectrum, two values per line (re, im)
+ -- PFIR coefficients
+ constant c_nof_lines_pfir_coefs : natural := c_nof_coefs;
+ -- Real input A via in_re, one value per line
+ constant c_nof_lines_a_wg_dat : natural := g_data_file_a_nof_lines;
+ -- Real pfir A, one value per line
+ constant c_nof_lines_a_pfir_dat : natural := g_data_file_a_nof_lines;
+ -- Half spectrum, two values per line (re, im)
+ constant c_nof_lines_a_pfft_dat : natural := g_data_file_a_nof_lines / c_nof_complex;
constant c_nof_lines_a_wg_header : natural := c_nof_lines_header + c_nof_lines_pfir_coefs;
constant c_nof_lines_a_pfir_header : natural := c_nof_lines_header + c_nof_lines_pfir_coefs + c_nof_lines_a_wg_dat;
constant c_nof_lines_a_pfft_header : natural := c_nof_lines_header + c_nof_lines_pfir_coefs + c_nof_lines_a_wg_dat + c_nof_lines_a_pfir_dat;
- constant c_nof_lines_b_wg_dat : natural := g_data_file_b_nof_lines; -- Real input A via in_re, one value per line
- constant c_nof_lines_b_pfir_dat : natural := g_data_file_b_nof_lines; -- Real pfir A, one value per line
- constant c_nof_lines_b_pfft_dat : natural := g_data_file_b_nof_lines / c_nof_complex; -- Half spectrum, two values per line (re, im)
+ -- Real input A via in_re, one value per line
+ constant c_nof_lines_b_wg_dat : natural := g_data_file_b_nof_lines;
+ -- Real pfir A, one value per line
+ constant c_nof_lines_b_pfir_dat : natural := g_data_file_b_nof_lines;
+ -- Half spectrum, two values per line (re, im)
+ constant c_nof_lines_b_pfft_dat : natural := g_data_file_b_nof_lines / c_nof_complex;
constant c_nof_lines_b_wg_header : natural := c_nof_lines_header + c_nof_lines_pfir_coefs;
constant c_nof_lines_b_pfir_header : natural := c_nof_lines_header + c_nof_lines_pfir_coefs + c_nof_lines_b_wg_dat;
constant c_nof_lines_b_pfft_header : natural := c_nof_lines_header + c_nof_lines_pfir_coefs + c_nof_lines_b_wg_dat + c_nof_lines_b_pfir_dat;
- constant c_nof_lines_c_wg_dat : natural := g_data_file_c_nof_lines; -- Complex input, two values per line (re, im)
- constant c_nof_lines_c_pfir_dat : natural := g_data_file_c_nof_lines; -- Complex pfir, two values per line (re, im)
- constant c_nof_lines_c_pfft_dat : natural := g_data_file_c_nof_lines; -- Full spectrum, two values per line (re, im)
+ -- Complex input, two values per line (re, im)
+ constant c_nof_lines_c_wg_dat : natural := g_data_file_c_nof_lines;
+ -- Complex pfir, two values per line (re, im)
+ constant c_nof_lines_c_pfir_dat : natural := g_data_file_c_nof_lines;
+ -- Full spectrum, two values per line (re, im)
+ constant c_nof_lines_c_pfft_dat : natural := g_data_file_c_nof_lines;
constant c_nof_lines_c_wg_header : natural := c_nof_lines_header + c_nof_lines_pfir_coefs;
constant c_nof_lines_c_pfir_header : natural := c_nof_lines_header + c_nof_lines_pfir_coefs + c_nof_lines_c_wg_dat;
constant c_nof_lines_c_pfft_header : natural := c_nof_lines_header + c_nof_lines_pfir_coefs + c_nof_lines_c_wg_dat + c_nof_lines_c_pfir_dat;
@@ -214,52 +230,83 @@ architecture tb of tb_wpfb_unit_wide is
signal clk : std_logic := '0';
signal sclk : std_logic := '0';
signal rst : std_logic := '0';
- signal random : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
-
- signal coefs_dat_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef for all taps as read from via c_coefs_dat_file_prefix
- signal coefs_ref_c_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef for all taps as read from via g_data_file_c
- signal coefs_ref_a_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef for all taps as read from via g_data_file_a
- signal coefs_ref_b_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef for all taps as read from via g_data_file_b
-
- signal input_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- one value per line (A via re input)
- signal input_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- one value per line (B via im input)
- signal input_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0); -- two values per line (re, im)
-
- signal exp_filter_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- one value per line (A via re input)
- signal exp_filter_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- one value per line (B via im input)
- signal exp_filter_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0); -- two values per line (re, im)
- signal exp_filter_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- one value per line (re input)
- signal exp_filter_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- one value per line (im input)
-
- signal output_data_a_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, re
- signal output_data_a_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, im
- signal output_data_b_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, re
- signal output_data_b_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, im
- signal output_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- full spectrum, re
- signal output_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- full spectrum, im
-
- signal exp_output_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- half spectrum, two values per line (re, im)
- signal exp_output_data_a_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, re
- signal exp_output_data_a_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, im
- signal exp_output_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- half spectrum, two values per line (re, im)
- signal exp_output_data_b_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, re
- signal exp_output_data_b_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0); -- half spectrum, im
- signal exp_output_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0); -- full spectrum, two values per line (re, im)
- signal exp_output_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- full spectrum, re
- signal exp_output_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0); -- full spectrum, im
+ -- use different lengths to have different random sequences
+ signal random : std_logic_vector(15 downto 0) := (others => '0');
+
+ -- = PFIR coef for all taps as read from via c_coefs_dat_file_prefix
+ signal coefs_dat_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0);
+ -- = PFIR coef for all taps as read from via g_data_file_c
+ signal coefs_ref_c_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0);
+ -- = PFIR coef for all taps as read from via g_data_file_a
+ signal coefs_ref_a_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0);
+ -- = PFIR coef for all taps as read from via g_data_file_b
+ signal coefs_ref_b_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0);
+
+ -- one value per line (A via re input)
+ signal input_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- one value per line (B via im input)
+ signal input_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- two values per line (re, im)
+ signal input_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0);
+
+ -- one value per line (A via re input)
+ signal exp_filter_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- one value per line (B via im input)
+ signal exp_filter_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- two values per line (re, im)
+ signal exp_filter_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0);
+ -- one value per line (re input)
+ signal exp_filter_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- one value per line (im input)
+ signal exp_filter_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+
+ -- half spectrum, re
+ signal output_data_a_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, im
+ signal output_data_a_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, re
+ signal output_data_b_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, im
+ signal output_data_b_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- full spectrum, re
+ signal output_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- full spectrum, im
+ signal output_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+
+ -- half spectrum, two values per line (re, im)
+ signal exp_output_data_a_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- half spectrum, re
+ signal exp_output_data_a_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, im
+ signal exp_output_data_a_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, two values per line (re, im)
+ signal exp_output_data_b_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- half spectrum, re
+ signal exp_output_data_b_re_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- half spectrum, im
+ signal exp_output_data_b_im_arr : t_integer_arr(0 to g_data_file_nof_lines / c_nof_complex - 1) := (others => 0);
+ -- full spectrum, two values per line (re, im)
+ signal exp_output_data_c_arr : t_integer_arr(0 to g_data_file_nof_lines * c_nof_complex - 1) := (others => 0);
+ -- full spectrum, re
+ signal exp_output_data_c_re_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
+ -- full spectrum, im
+ signal exp_output_data_c_im_arr : t_integer_arr(0 to g_data_file_nof_lines - 1) := (others => 0);
-- Input
signal in_re_arr : t_fft_slv_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);
signal in_im_arr : t_fft_slv_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);
- signal in_re_data : std_logic_vector(g_wpfb.wb_factor * c_in_dat_w - 1 downto 0); -- scope data only for stream 0
- signal in_im_data : std_logic_vector(g_wpfb.wb_factor * c_in_dat_w - 1 downto 0); -- scope data only for stream 0
+ -- scope data only for stream 0
+ signal in_re_data : std_logic_vector(g_wpfb.wb_factor * c_in_dat_w - 1 downto 0);
+ -- scope data only for stream 0
+ signal in_im_data : std_logic_vector(g_wpfb.wb_factor * c_in_dat_w - 1 downto 0);
signal in_val : std_logic := '0';
signal in_val_cnt : natural := 0;
signal in_blk_val : std_logic;
signal in_blk_val_cnt : natural := 0;
signal in_gap : std_logic := '0';
signal in_sosi_arr : t_dp_sosi_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0) := (others => c_dp_sosi_rst);
- signal in_blk_time : integer := 0; -- input block time counter
+ -- input block time counter
+ signal in_blk_time : integer := 0;
signal in_sosi_val : t_dp_sosi;
signal ref_sosi_ctrl : t_dp_sosi;
@@ -275,9 +322,12 @@ architecture tb of tb_wpfb_unit_wide is
signal fil_sosi_arr : t_dp_sosi_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);
signal fil_re_arr : t_fft_slv_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);
signal fil_im_arr : t_fft_slv_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);
- signal fil_re_data : std_logic_vector(g_wpfb.wb_factor * c_fil_dat_w - 1 downto 0); -- scope data only for stream 0
- signal fil_im_data : std_logic_vector(g_wpfb.wb_factor * c_fil_dat_w - 1 downto 0); -- scope data only for stream 0
- signal fil_val : std_logic := '0'; -- for parallel output
+ -- scope data only for stream 0
+ signal fil_re_data : std_logic_vector(g_wpfb.wb_factor * c_fil_dat_w - 1 downto 0);
+ -- scope data only for stream 0
+ signal fil_im_data : std_logic_vector(g_wpfb.wb_factor * c_fil_dat_w - 1 downto 0);
+ -- for parallel output
+ signal fil_val : std_logic := '0';
-- Filter in sclk domain
signal fil_re_scope : integer;
@@ -294,18 +344,25 @@ architecture tb of tb_wpfb_unit_wide is
signal out_sosi_arr : t_dp_sosi_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0) := (others => c_dp_sosi_rst);
signal out_re_arr : t_fft_slv_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);
signal out_im_arr : t_fft_slv_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);
- signal out_re_data : std_logic_vector(g_wpfb.wb_factor * c_out_dat_w - 1 downto 0); -- scope data only for stream 0
- signal out_im_data : std_logic_vector(g_wpfb.wb_factor * c_out_dat_w - 1 downto 0); -- scope data only for stream 0
- signal out_val : std_logic := '0'; -- for parallel output
+ -- scope data only for stream 0
+ signal out_re_data : std_logic_vector(g_wpfb.wb_factor * c_out_dat_w - 1 downto 0);
+ -- scope data only for stream 0
+ signal out_im_data : std_logic_vector(g_wpfb.wb_factor * c_out_dat_w - 1 downto 0);
+ -- for parallel output
+ signal out_val : std_logic := '0';
signal out_val_cnt : natural := 0;
- signal out_blk_time : integer := 0; -- output block time counter
+ -- output block time counter
+ signal out_blk_time : integer := 0;
-- Output in sclk domain
signal out_re_scope : integer := 0;
signal out_im_scope : integer := 0;
- signal out_val_a : std_logic := '0'; -- for real A
- signal out_val_b : std_logic := '0'; -- for real B
- signal out_val_c : std_logic := '0'; -- for complex(A,B)
+ -- for real A
+ signal out_val_a : std_logic := '0';
+ -- for real B
+ signal out_val_b : std_logic := '0';
+ -- for complex(A,B)
+ signal out_val_c : std_logic := '0';
signal out_channel : natural := 0;
signal out_cnt : natural := 0;
signal out_bin_cnt : natural := 0;
@@ -369,18 +426,26 @@ begin
in_re_arr <= (others => (others => '0'));
in_im_arr <= (others => (others => '0'));
in_val <= '0';
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
+ -- Wait until reset has finished
+ proc_common_wait_until_low(clk, rst);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(clk, 10);
-- apply stimuli
- for I in 0 to g_data_file_nof_lines / g_wpfb.wb_factor - 1 loop -- serial
- for K in 0 to c_nof_channels - 1 loop -- serial
- for S in 0 to g_wpfb.nof_wb_streams - 1 loop -- parallel
- for P in 0 to g_wpfb.wb_factor - 1 loop -- parallel
+ -- serial
+ for I in 0 to g_data_file_nof_lines / g_wpfb.wb_factor - 1 loop
+ -- serial
+ for K in 0 to c_nof_channels - 1 loop
+ -- parallel
+ for S in 0 to g_wpfb.nof_wb_streams - 1 loop
+ -- parallel
+ for P in 0 to g_wpfb.wb_factor - 1 loop
if c_big_endian_wb_in = true then
- vP := g_wpfb.wb_factor - 1 - P; -- time to big endian
+ -- time to big endian
+ vP := g_wpfb.wb_factor - 1 - P;
else
- vP := P; -- time in little endian
+ -- time in little endian
+ vP := P;
end if;
if K = 1 or S = 1 then
-- if present then serial channel 1 carries zero data to be able to recognize the serial channel order in the wave window
@@ -399,10 +464,12 @@ begin
end if;
end loop;
end loop;
- in_val <= '1'; -- serial
+ -- serial
+ in_val <= '1';
proc_common_wait_some_cycles(clk, 1);
if in_gap = '1' then
- in_val <= '0'; -- serial
+ -- serial
+ in_val <= '0';
proc_common_wait_some_cycles(clk, 1);
end if;
end loop;
@@ -410,7 +477,8 @@ begin
-- Wait until done
in_val <= '0';
- proc_common_wait_some_cycles(clk, c_dut_clk_latency); -- wait for DUT latency
+ -- wait for DUT latency
+ proc_common_wait_some_cycles(clk, c_dut_clk_latency);
tb_end_almost <= '1';
proc_common_wait_some_cycles(clk, 100);
tb_end <= '1';
@@ -421,8 +489,10 @@ begin
u_ref_sosi_ctrl : entity dp_lib.dp_block_gen
generic map (
- g_use_src_in => false, -- when true use src_in.ready else use snk_in.valid for flow control
- g_nof_data => c_nof_valid_per_block, -- nof data per block
+ -- when true use src_in.ready else use snk_in.valid for flow control
+ g_use_src_in => false,
+ -- nof data per block
+ g_nof_data => c_nof_valid_per_block,
g_nof_blk_per_sync => g_wpfb.nof_blk_per_sync,
g_empty => 0,
g_channel => 0,
@@ -679,13 +749,17 @@ begin
u_in_re_scope : entity common_lib.common_wideband_data_scope
generic map (
g_sim => true,
- g_wideband_factor => g_wpfb.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => true, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_in_dat_w -- Actual width of the data samples
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor => g_wpfb.wb_factor,
+ -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian => true,
+ -- Actual width of the data samples
+ g_dat_w => c_in_dat_w
)
port map (
-- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
+ -- sample clk, use only for simulation purposes
+ SCLK => sclk,
-- Streaming input data
in_data => in_re_data,
@@ -700,13 +774,17 @@ begin
u_in_im_scope : entity common_lib.common_wideband_data_scope
generic map (
g_sim => true,
- g_wideband_factor => g_wpfb.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => true, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_in_dat_w -- Actual width of the data samples
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor => g_wpfb.wb_factor,
+ -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian => true,
+ -- Actual width of the data samples
+ g_dat_w => c_in_dat_w
)
port map (
-- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
+ -- sample clk, use only for simulation purposes
+ SCLK => sclk,
-- Streaming input data
in_data => in_im_data,
@@ -721,13 +799,17 @@ begin
u_fil_re_scope : entity common_lib.common_wideband_data_scope
generic map (
g_sim => true,
- g_wideband_factor => g_wpfb.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => true, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_fil_dat_w -- Actual width of the data samples
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor => g_wpfb.wb_factor,
+ -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian => true,
+ -- Actual width of the data samples
+ g_dat_w => c_fil_dat_w
)
port map (
-- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
+ -- sample clk, use only for simulation purposes
+ SCLK => sclk,
-- Streaming input data
in_data => fil_re_data,
@@ -742,13 +824,17 @@ begin
u_fil_im_scope : entity common_lib.common_wideband_data_scope
generic map (
g_sim => true,
- g_wideband_factor => g_wpfb.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => true, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_fil_dat_w -- Actual width of the data samples
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor => g_wpfb.wb_factor,
+ -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian => true,
+ -- Actual width of the data samples
+ g_dat_w => c_fil_dat_w
)
port map (
-- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
+ -- sample clk, use only for simulation purposes
+ SCLK => sclk,
-- Streaming input data
in_data => fil_im_data,
@@ -763,13 +849,17 @@ begin
u_out_re_scope : entity common_lib.common_wideband_data_scope
generic map (
g_sim => true,
- g_wideband_factor => g_wpfb.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => false, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_out_dat_w -- Actual width of the data samples
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor => g_wpfb.wb_factor,
+ -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian => false,
+ -- Actual width of the data samples
+ g_dat_w => c_out_dat_w
)
port map (
-- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
+ -- sample clk, use only for simulation purposes
+ SCLK => sclk,
-- Streaming input data
in_data => out_re_data,
@@ -784,13 +874,17 @@ begin
u_out_im_scope : entity common_lib.common_wideband_data_scope
generic map (
g_sim => true,
- g_wideband_factor => g_wpfb.wb_factor, -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
- g_wideband_big_endian => false, -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
- g_dat_w => c_out_dat_w -- Actual width of the data samples
+ -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
+ g_wideband_factor => g_wpfb.wb_factor,
+ -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+ g_wideband_big_endian => false,
+ -- Actual width of the data samples
+ g_dat_w => c_out_dat_w
)
port map (
-- Sample clock
- SCLK => sclk, -- sample clk, use only for simulation purposes
+ -- sample clk, use only for simulation purposes
+ SCLK => sclk,
-- Streaming input data
in_data => out_im_data,
diff --git a/libraries/io/aduh/src/vhdl/aduh_dd.vhd b/libraries/io/aduh/src/vhdl/aduh_dd.vhd
index 1049b42901e2346e305cb0e2391a5395e118934e..e37a2044a0ead41d8f28cbe47dec8cdcf9300309 100644
--- a/libraries/io/aduh/src/vhdl/aduh_dd.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_dd.vhd
@@ -56,22 +56,30 @@ use work.aduh_dd_pkg.all;
entity aduh_dd is
generic (
g_sim : boolean := false;
- g_nof_dp_phs_clk : natural := 1; -- nof dp_phs_clk that can be used to detect the word phase
+ -- nof dp_phs_clk that can be used to detect the word phase
+ g_nof_dp_phs_clk : natural := 1;
g_ai : t_c_aduh_dd_ai := c_aduh_dd_ai
);
port (
-- LVDS Interface
-- . g_ai.nof_sp = 4, fixed support 4 signal paths A,B,C,D
- ADC_BI_A : in std_logic_vector(g_ai.port_w - 1 downto 0) := (others => '0'); -- fixed ADC_BI port width port_w = 8
- ADC_BI_B : in std_logic_vector(g_ai.port_w - 1 downto 0) := (others => '0'); -- each ADC_BI port carries the data from 1 signal path
- ADC_BI_C : in std_logic_vector(g_ai.port_w - 1 downto 0) := (others => '0'); -- ports A,B connect to one ADU, ports C,D connect to another ADU
+ -- fixed ADC_BI port width port_w = 8
+ ADC_BI_A : in std_logic_vector(g_ai.port_w - 1 downto 0) := (others => '0');
+ -- each ADC_BI port carries the data from 1 signal path
+ ADC_BI_B : in std_logic_vector(g_ai.port_w - 1 downto 0) := (others => '0');
+ -- ports A,B connect to one ADU, ports C,D connect to another ADU
+ ADC_BI_C : in std_logic_vector(g_ai.port_w - 1 downto 0) := (others => '0');
ADC_BI_D : in std_logic_vector(g_ai.port_w - 1 downto 0) := (others => '0');
- ADC_BI_A_CLK : in std_logic := '0'; -- lvds clock from ADU_AB
- ADC_BI_D_CLK : in std_logic := '0'; -- lvds clock from ADU_CD
+ -- lvds clock from ADU_AB
+ ADC_BI_A_CLK : in std_logic := '0';
+ -- lvds clock from ADU_CD
+ ADC_BI_D_CLK : in std_logic := '0';
- ADC_BI_A_CLK_RST : out std_logic; -- release synchronises ADU_AB DCLK divider
- ADC_BI_D_CLK_RST : out std_logic; -- release synchronises ADU_CD DCLK divider
+ -- release synchronises ADU_AB DCLK divider
+ ADC_BI_A_CLK_RST : out std_logic;
+ -- release synchronises ADU_CD DCLK divider
+ ADC_BI_D_CLK_RST : out std_logic;
-- MM Interface
ab_status : out std_logic_vector(c_word_w - 1 downto 0);
@@ -111,9 +119,12 @@ architecture str of aduh_dd is
constant c_in_dat_delay_arr_cd : t_natural_arr(g_ai.nof_ports * g_ai.port_w - 1 downto 0) := g_ai.deskew.dat_delay_arr_c & g_ai.deskew.dat_delay_arr_d;
-- Use c_rx_fifo_fill sufficiently larger than the moment where *_CLK_RST gets applied
- constant c_rx_fifo_size : natural := 32; -- see common_fifo_dc_lock_control used in lvds_dd for comment
- constant c_rx_fifo_fill : natural := 17; -- see common_fifo_dc_lock_control used in lvds_dd for comment
- constant c_rx_fifo_margin : natural := 2; -- use +-2 because with fill level 10001b = 17 accept +-1 so 10000b = 16 and 10010b = 18,
+ -- see common_fifo_dc_lock_control used in lvds_dd for comment
+ constant c_rx_fifo_size : natural := 32;
+ -- see common_fifo_dc_lock_control used in lvds_dd for comment
+ constant c_rx_fifo_fill : natural := 17;
+ -- use +-2 because with fill level 10001b = 17 accept +-1 so 10000b = 16 and 10010b = 18,
+ constant c_rx_fifo_margin : natural := 2;
-- but also +2 for misvalue 10011b = 19 in case rd_usedw is not clocked in reliably
signal ADC_BI_A_rewire : std_logic_vector(ADC_BI_A'range);
@@ -173,10 +184,14 @@ begin
begin
src_out_arr <= (others => c_dp_sosi_rst);
for I in 0 to c_dp_factor - 1 loop
- src_out_arr(0).data((I + 1) * g_ai.port_w - 1 downto I * g_ai.port_w) <= rx_dat_ab((I + 1) * c_in_dat_w - 1 downto I * c_in_dat_w + g_ai.port_w); -- A at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
- src_out_arr(1).data((I + 1) * g_ai.port_w - 1 downto I * g_ai.port_w) <= rx_dat_ab((I + 1) * c_in_dat_w - g_ai.port_w - 1 downto I * c_in_dat_w ); -- B at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
- src_out_arr(2).data((I + 1) * g_ai.port_w - 1 downto I * g_ai.port_w) <= rx_dat_cd((I + 1) * c_in_dat_w - 1 downto I * c_in_dat_w + g_ai.port_w); -- C at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
- src_out_arr(3).data((I + 1) * g_ai.port_w - 1 downto I * g_ai.port_w) <= rx_dat_cd((I + 1) * c_in_dat_w - g_ai.port_w - 1 downto I * c_in_dat_w ); -- D at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ -- A at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ src_out_arr(0).data((I + 1) * g_ai.port_w - 1 downto I * g_ai.port_w) <= rx_dat_ab((I + 1) * c_in_dat_w - 1 downto I * c_in_dat_w + g_ai.port_w);
+ -- B at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ src_out_arr(1).data((I + 1) * g_ai.port_w - 1 downto I * g_ai.port_w) <= rx_dat_ab((I + 1) * c_in_dat_w - g_ai.port_w - 1 downto I * c_in_dat_w );
+ -- C at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ src_out_arr(2).data((I + 1) * g_ai.port_w - 1 downto I * g_ai.port_w) <= rx_dat_cd((I + 1) * c_in_dat_w - 1 downto I * c_in_dat_w + g_ai.port_w);
+ -- D at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ src_out_arr(3).data((I + 1) * g_ai.port_w - 1 downto I * g_ai.port_w) <= rx_dat_cd((I + 1) * c_in_dat_w - g_ai.port_w - 1 downto I * c_in_dat_w );
end loop;
src_out_arr(0).valid <= rx_val_ab;
src_out_arr(1).valid <= rx_val_ab;
@@ -210,7 +225,8 @@ begin
-- DD --> Rx domain interface at in_clk rate or g_rx_factor lower rate (via FIFO)
rx_rst => dp_rst,
rx_clk => dp_clk,
- rx_dat => obin_dat_ab, -- big endian rx_dat output for rx_factor = 2, samples AB at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ -- big endian rx_dat output for rx_factor = 2, samples AB at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ rx_dat => obin_dat_ab,
rx_val => obin_val_ab,
rx_locked => ab_locked,
@@ -240,7 +256,8 @@ begin
-- DD --> Rx domain interface at in_clk rate or g_rx_factor lower rate (via FIFO)
rx_rst => dp_rst,
rx_clk => dp_clk,
- rx_dat => obin_dat_cd, -- big endian rx_dat output for rx_factor = 2, samples CD at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ -- big endian rx_dat output for rx_factor = 2, samples CD at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ rx_dat => obin_dat_cd,
rx_val => obin_val_cd,
rx_locked => cd_locked,
@@ -253,26 +270,32 @@ begin
-- Connect ADU 0 via port A and B using only clock from A
ADC_BI_A_CLK_RST <= in_clk_ab_rst when g_ai.clk_rst_invert = false else not in_clk_ab_rst;
- in_clk_ab_rst <= '0'; -- no ADC clk reset
+ -- no ADC clk reset
+ in_clk_ab_rst <= '0';
u_lvdsh_dd_phs4_ab : entity work.lvdsh_dd_phs4
generic map (
g_sim => g_sim,
- g_wb_factor => c_dp_factor, -- fixed wideband factor = 4
- g_nof_dp_phs_clk => g_nof_dp_phs_clk, -- nof dp_phs_clk that can be used to detect lock
- g_in_dat_w => c_in_dat_w -- nof PHY data bits
+ -- fixed wideband factor = 4
+ g_wb_factor => c_dp_factor,
+ -- nof dp_phs_clk that can be used to detect lock
+ g_nof_dp_phs_clk => g_nof_dp_phs_clk,
+ -- nof PHY data bits
+ g_in_dat_w => c_in_dat_w
)
port map (
-- PHY input interface
in_clk => ADC_BI_A_CLK,
- in_dat => in_dat_ab, -- input samples AB [t0], [t1], [t2], [t3], [t4], [t5], [t6], [t7], ... --> time
+ -- input samples AB [t0], [t1], [t2], [t3], [t4], [t5], [t6], [t7], ... --> time
+ in_dat => in_dat_ab,
-- DD --> Rx domain interface at in_clk rate or g_wb_factor lower rate (via FIFO)
dp_rst => dp_rst,
dp_clk => dp_clk,
dp_phs_clk_vec => dp_phs_clk_vec,
dp_phs_clk_en_vec => ab_dp_phs_clk_en_vec,
- dp_dat => obin_dat_ab, -- big endian output samples AB at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ -- big endian output samples AB at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ dp_dat => obin_dat_ab,
dp_val => obin_val_ab,
-- Rx status monitor
@@ -285,26 +308,32 @@ begin
-- Connect ADU 1 via port C and D using only clock from D
ADC_BI_D_CLK_RST <= in_clk_cd_rst when g_ai.clk_rst_invert = false else not in_clk_cd_rst;
- in_clk_cd_rst <= '0'; -- no ADC clk reset
+ -- no ADC clk reset
+ in_clk_cd_rst <= '0';
u_lvdsh_dd_phs4_cd : entity work.lvdsh_dd_phs4
generic map (
g_sim => g_sim,
- g_wb_factor => c_dp_factor, -- fixed wideband factor = 4
- g_nof_dp_phs_clk => g_nof_dp_phs_clk, -- nof dp_phs_clk that can be used to detect lock
- g_in_dat_w => c_in_dat_w -- nof PHY data bits
+ -- fixed wideband factor = 4
+ g_wb_factor => c_dp_factor,
+ -- nof dp_phs_clk that can be used to detect lock
+ g_nof_dp_phs_clk => g_nof_dp_phs_clk,
+ -- nof PHY data bits
+ g_in_dat_w => c_in_dat_w
)
port map (
-- PHY input interface
in_clk => ADC_BI_D_CLK,
- in_dat => in_dat_cd, -- input samples CD [t0], [t1], [t2], [t3], [t4], [t5], [t6], [t7], ... --> time
+ -- input samples CD [t0], [t1], [t2], [t3], [t4], [t5], [t6], [t7], ... --> time
+ in_dat => in_dat_cd,
-- DD --> Rx domain interface at in_clk rate or g_wb_factor=4 lower rate (via FIFO)
dp_rst => dp_rst,
dp_clk => dp_clk,
dp_phs_clk_vec => dp_phs_clk_vec,
dp_phs_clk_en_vec => cd_dp_phs_clk_en_vec,
- dp_dat => obin_dat_cd, -- big endian output samples CD at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ -- big endian output samples CD at [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ dp_dat => obin_dat_cd,
dp_val => obin_val_cd,
-- Rx status monitor
diff --git a/libraries/io/aduh/src/vhdl/aduh_dd_pkg.vhd b/libraries/io/aduh/src/vhdl/aduh_dd_pkg.vhd
index 01bd165fc42f86d0ca4107318b86081748bbcc07..d2efb4e0898cfd562e7e94c7c04ad37ab678763e 100644
--- a/libraries/io/aduh/src/vhdl/aduh_dd_pkg.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_dd_pkg.vhd
@@ -26,10 +26,12 @@ use common_lib.common_pkg.all;
package aduh_dd_pkg is
-- ADU Interface
- type t_c_aduh_delays is record -- Input de-skew buffer delays: unit 50 ps, range 0..15
+ -- Input de-skew buffer delays: unit 50 ps, range 0..15
+ type t_c_aduh_delays is record
clk_delay_a : natural;
clk_delay_d : natural;
- dat_delay_arr_a : t_natural_arr(7 downto 0); -- width is c_aduh_dd_ai.port_w = 8
+ -- width is c_aduh_dd_ai.port_w = 8
+ dat_delay_arr_a : t_natural_arr(7 downto 0);
dat_delay_arr_b : t_natural_arr(7 downto 0);
dat_delay_arr_c : t_natural_arr(7 downto 0);
dat_delay_arr_d : t_natural_arr(7 downto 0);
@@ -38,17 +40,26 @@ package aduh_dd_pkg is
constant c_aduh_delays : t_c_aduh_delays := (0, 0, (others => 0), (others => 0), (others => 0), (others => 0));
type t_c_aduh_dd_ai is record
- nof_sp : natural; -- = 4; -- Fixed support 4 signal paths A,B,C,D, whether they contain active data depends on nof_adu
- nof_adu : natural; -- = 2; -- When 2 ADUs then use all 4 ports A,B,C,D, one ADU on ports A,B and one ADU on ports C,D,
+ -- = 4; -- Fixed support 4 signal paths A,B,C,D, whether they contain active data depends on nof_adu
+ nof_sp : natural;
+ -- = 2; -- When 2 ADUs then use all 4 ports A,B,C,D, one ADU on ports A,B and one ADU on ports C,D,
+ nof_adu : natural;
-- when 1 ADU then only use ports C,D
- nof_ports : natural; -- = 2; -- Fixed 2 ADC BI ports per ADU
- port_w : natural; -- = 8; -- Fixed 8 bit ADC BI port width, the ADC sample width is also 8 bit
- dd_factor : natural; -- = 2; -- Fixed double data rate factor for lvds data (800 MSps) and lvds clock (400 MHz)
- rx_factor : natural; -- = 2; -- when 1 then the data path processing clock frequency is 400 MHz (= lvds clock / 1)
+ -- = 2; -- Fixed 2 ADC BI ports per ADU
+ nof_ports : natural;
+ -- = 8; -- Fixed 8 bit ADC BI port width, the ADC sample width is also 8 bit
+ port_w : natural;
+ -- = 2; -- Fixed double data rate factor for lvds data (800 MSps) and lvds clock (400 MHz)
+ dd_factor : natural;
+ -- = 2; -- when 1 then the data path processing clock frequency is 400 MHz (= lvds clock / 1)
+ rx_factor : natural;
-- when 2 then the data path processing clock frequency is 200 MHz (= lvds clock / 2)
- clk_rst_enable : boolean; -- = TRUE; -- default TRUE for initial DCLK_RST pulse to control the ADC DCLK phase, else FALSE for no DCLK_RST pulse
- clk_rst_invert : boolean; -- = FALSE; -- default FALSE because DCLK_RST pulse on ADC is active high, use TRUE for active low pulse to compensate for P/N cross
- deskew : t_c_aduh_delays; -- Input de-skew buffer delays
+ -- = TRUE; -- default TRUE for initial DCLK_RST pulse to control the ADC DCLK phase, else FALSE for no DCLK_RST pulse
+ clk_rst_enable : boolean;
+ -- = FALSE; -- default FALSE because DCLK_RST pulse on ADC is active high, use TRUE for active low pulse to compensate for P/N cross
+ clk_rst_invert : boolean;
+ -- Input de-skew buffer delays
+ deskew : t_c_aduh_delays;
end record;
constant c_aduh_dd_ai : t_c_aduh_dd_ai := (4, 2, 2, 8, 2, 2, true, false, c_aduh_delays);
diff --git a/libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd b/libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd
index 03ac392efcb7d236aaee0e361d844f15f240e463..76e8c6053b4821eec9458506f5bbe2aa6ada69e0 100644
--- a/libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd
@@ -34,10 +34,14 @@ use common_lib.common_pkg.all;
entity aduh_mean_sum is
generic (
g_symbol_w : natural := 12;
- g_nof_symbols_per_data : natural := 4; -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
- g_nof_accumulations : natural := 800 * 10**6; -- integration time in symbols
- g_sum_truncate : boolean := true; -- when TRUE truncate (keep MS part) else resize (keep sign and LS part)
- g_sum_w : natural := 32 -- typcially MM word width
+ -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data : natural := 4;
+ -- integration time in symbols
+ g_nof_accumulations : natural := 800 * 10**6;
+ -- when TRUE truncate (keep MS part) else resize (keep sign and LS part)
+ g_sum_truncate : boolean := true;
+ -- typcially MM word width
+ g_sum_w : natural := 32
);
port (
clk : in std_logic;
@@ -50,7 +54,8 @@ entity aduh_mean_sum is
-- Accumulation outputs
sum : out std_logic_vector(g_sum_w - 1 downto 0);
- sum_sync : out std_logic -- at sum_sync there is a new sum
+ -- at sum_sync there is a new sum
+ sum_sync : out std_logic
);
end aduh_mean_sum;
@@ -87,7 +92,8 @@ begin
-- Accumulate per symbol stream in the in_data
gen_acc : for I in 0 to g_nof_symbols_per_data - 1 generate
- symbol_arr(I) <= in_data((g_nof_symbols_per_data - I) * g_symbol_w - 1 downto (g_nof_symbols_per_data - I - 1) * g_symbol_w); -- put big endian MS part t0 at array index 0
+ -- put big endian MS part t0 at array index 0
+ symbol_arr(I) <= in_data((g_nof_symbols_per_data - I) * g_symbol_w - 1 downto (g_nof_symbols_per_data - I - 1) * g_symbol_w);
u_acc : entity common_lib.common_accumulate
generic map (
@@ -96,13 +102,15 @@ begin
port map(
rst => rst,
clk => clk,
- sload => in_sync, -- Reload the accumlators with 0 at the sync or with the valid sample after the sync
+ -- Reload the accumlators with 0 at the sync or with the valid sample after the sync
+ sload => in_sync,
in_val => in_val,
in_dat => symbol_arr(I),
out_dat => acc_arr(I)
);
- acc_vec((g_nof_symbols_per_data - I) * c_acc_w - 1 downto (g_nof_symbols_per_data - I - 1) * c_acc_w) <= acc_arr(I); -- put array index 0 at big endian MS part t0
+ -- put array index 0 at big endian MS part t0
+ acc_vec((g_nof_symbols_per_data - I) * c_acc_w - 1 downto (g_nof_symbols_per_data - I - 1) * c_acc_w) <= acc_arr(I);
end generate;
no_tree : if g_nof_symbols_per_data = 1 generate
@@ -115,8 +123,10 @@ begin
u_sum : entity common_lib.common_adder_tree
generic map (
g_representation => "SIGNED",
- g_pipeline => c_acc_sum_pipeline, -- amount of pipelining per stage
- g_nof_inputs => g_nof_symbols_per_data, -- >= 1, nof stages = ceil_log2(g_nof_inputs)
+ -- amount of pipelining per stage
+ g_pipeline => c_acc_sum_pipeline,
+ -- >= 1, nof stages = ceil_log2(g_nof_inputs)
+ g_nof_inputs => g_nof_symbols_per_data,
g_dat_w => c_acc_w,
g_sum_w => c_acc_sum_w
)
@@ -128,7 +138,8 @@ begin
u_in_sync_p : entity common_lib.common_pipeline_sl
generic map (
- g_pipeline => c_acc_sum_nof_stages * c_acc_sum_pipeline, -- latency of common_adder_tree
+ -- latency of common_adder_tree
+ g_pipeline => c_acc_sum_nof_stages * c_acc_sum_pipeline,
g_reset_value => 0
)
port map (
diff --git a/libraries/io/aduh/src/vhdl/aduh_monitor.vhd b/libraries/io/aduh/src/vhdl/aduh_monitor.vhd
index d88e08481c21c62dc19d30c78f4d04a1cd620439..128f97fb4f666c8e080850b16d6b642c95d3e92f 100644
--- a/libraries/io/aduh/src/vhdl/aduh_monitor.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_monitor.vhd
@@ -48,43 +48,57 @@ use dp_lib.dp_stream_pkg.all;
entity aduh_monitor is
generic (
g_symbol_w : natural := 8;
- g_nof_symbols_per_data : natural := 4; -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
- g_nof_accumulations : natural := 800 * 10**6; -- integration time in symbols, defines internal accumulator widths
+ -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data : natural := 4;
+ -- integration time in symbols, defines internal accumulator widths
+ g_nof_accumulations : natural := 800 * 10**6;
g_buffer_nof_symbols : natural := 1024;
- g_buffer_use_sync : boolean := false -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+ -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+ g_buffer_use_sync : boolean := false
);
port (
mm_rst : in std_logic;
mm_clk : in std_logic;
- buf_mosi : in t_mem_mosi; -- read and overwrite access to the data buffer
+ -- read and overwrite access to the data buffer
+ buf_mosi : in t_mem_mosi;
buf_miso : out t_mem_miso;
-- Streaming inputs
st_rst : in std_logic;
st_clk : in std_logic;
- in_sosi : in t_dp_sosi; -- Signal path with data 4 800MHz 8b samples in time per one 32b word @ 200MHz
+ -- Signal path with data 4 800MHz 8b samples in time per one 32b word @ 200MHz
+ in_sosi : in t_dp_sosi;
-- Monitor outputs
- stat_mean_sum : out std_logic_vector(63 downto 0); -- use fixed 64 bit sum width
- stat_pwr_sum : out std_logic_vector(63 downto 0); -- use fixed 64 bit sum width
- stat_sync : out std_logic -- at the stat_sync there are new mean_sum and pwr_sum statistics available
+ -- use fixed 64 bit sum width
+ stat_mean_sum : out std_logic_vector(63 downto 0);
+ -- use fixed 64 bit sum width
+ stat_pwr_sum : out std_logic_vector(63 downto 0);
+ -- at the stat_sync there are new mean_sum and pwr_sum statistics available
+ stat_sync : out std_logic
);
end aduh_monitor;
architecture str of aduh_monitor is
- constant c_data_w : natural := g_nof_symbols_per_data * g_symbol_w; -- = 32, must be <= 32 to fit the u_data_buffer
- constant c_stat_w : natural := 2 * c_word_w; -- support upto 64 bit sum width, this is more than enough without truncation and no accumulator overflow
+ -- = 32, must be <= 32 to fit the u_data_buffer
+ constant c_data_w : natural := g_nof_symbols_per_data * g_symbol_w;
+ -- support upto 64 bit sum width, this is more than enough without truncation and no accumulator overflow
+ constant c_stat_w : natural := 2 * c_word_w;
constant c_buffer_nof_data : natural := g_buffer_nof_symbols / g_nof_symbols_per_data;
begin
u_mean : entity work.aduh_mean_sum
generic map (
g_symbol_w => g_symbol_w,
- g_nof_symbols_per_data => g_nof_symbols_per_data, -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
- g_nof_accumulations => g_nof_accumulations, -- integration time in symbols
- g_sum_truncate => false, -- when TRUE truncate (keep MS part) else resize (keep sign and LS part)
- g_sum_w => c_stat_w -- typcially MM word width = 32
+ -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data => g_nof_symbols_per_data,
+ -- integration time in symbols
+ g_nof_accumulations => g_nof_accumulations,
+ -- when TRUE truncate (keep MS part) else resize (keep sign and LS part)
+ g_sum_truncate => false,
+ -- typcially MM word width = 32
+ g_sum_w => c_stat_w
)
port map (
clk => st_clk,
@@ -103,10 +117,14 @@ begin
u_power : entity work.aduh_power_sum
generic map (
g_symbol_w => g_symbol_w,
- g_nof_symbols_per_data => g_nof_symbols_per_data, -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
- g_nof_accumulations => g_nof_accumulations, -- integration time in symbols
- g_pwr_sum_truncate => false, -- when TRUE truncate (keep MS part) else resize (keep sign and LS part)
- g_pwr_sum_w => c_stat_w -- typcially MM word width = 32
+ -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data => g_nof_symbols_per_data,
+ -- integration time in symbols
+ g_nof_accumulations => g_nof_accumulations,
+ -- when TRUE truncate (keep MS part) else resize (keep sign and LS part)
+ g_pwr_sum_truncate => false,
+ -- typcially MM word width = 32
+ g_pwr_sum_w => c_stat_w
)
port map (
clk => st_clk,
@@ -124,16 +142,19 @@ begin
u_data_mon: entity diag_lib.diag_data_buffer
generic map (
- g_data_w => c_data_w, -- <= c_word_w = 32b, the MM word width
+ -- <= c_word_w = 32b, the MM word width
+ g_data_w => c_data_w,
g_nof_data => c_buffer_nof_data,
- g_use_in_sync => g_buffer_use_sync -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+ -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+ g_use_in_sync => g_buffer_use_sync
)
port map (
-- Memory-mapped clock domain
mm_rst => mm_rst,
mm_clk => mm_clk,
- ram_mm_mosi => buf_mosi, -- read and overwrite access to the data buffer
+ -- read and overwrite access to the data buffer
+ ram_mm_mosi => buf_mosi,
ram_mm_miso => buf_miso,
-- Streaming clock domain
diff --git a/libraries/io/aduh/src/vhdl/aduh_monitor_reg.vhd b/libraries/io/aduh/src/vhdl/aduh_monitor_reg.vhd
index d0e218257dd80fee4abca99ce38c1a43bb2195c4..f96d4b122ec7cefabd22f148a900f16e3aea42a6 100644
--- a/libraries/io/aduh/src/vhdl/aduh_monitor_reg.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_monitor_reg.vhd
@@ -43,23 +43,33 @@ use common_lib.common_mem_pkg.all;
entity aduh_monitor_reg is
generic (
- g_cross_clock_domain : boolean := true -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
- st_mon_mean_sum : in std_logic_vector(c_longword_w - 1 downto 0); -- use fixed 64 bit sum width
- st_mon_power_sum : in std_logic_vector(c_longword_w - 1 downto 0); -- use fixed 64 bit sum width
- st_mon_sync : in std_logic -- at the mon_sync there are new mean_sum and pwr_sum statistics available
+ -- use fixed 64 bit sum width
+ st_mon_mean_sum : in std_logic_vector(c_longword_w - 1 downto 0);
+ -- use fixed 64 bit sum width
+ st_mon_power_sum : in std_logic_vector(c_longword_w - 1 downto 0);
+ -- at the mon_sync there are new mean_sum and pwr_sum statistics available
+ st_mon_sync : in std_logic
);
end aduh_monitor_reg;
@@ -67,7 +77,8 @@ architecture rtl of aduh_monitor_reg is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 2**2,
init_sl => '0');
@@ -104,20 +115,25 @@ begin
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
when 0 =>
sla_out.rddata(31 downto 0) <= mm_mon_mean_sum(31 downto 0);
- mm_mon_mean_sum_hi <= mm_mon_mean_sum(63 downto 32); -- first read low part and preserve high part
+ -- first read low part and preserve high part
+ mm_mon_mean_sum_hi <= mm_mon_mean_sum(63 downto 32);
when 1 =>
sla_out.rddata(31 downto 0) <= mm_mon_mean_sum_hi;
when 2 =>
sla_out.rddata(31 downto 0) <= mm_mon_power_sum(31 downto 0);
- mm_mon_power_sum_hi <= mm_mon_power_sum(63 downto 32); -- first read low part and preserve high part
+ -- first read low part and preserve high part
+ mm_mon_power_sum_hi <= mm_mon_power_sum(63 downto 32);
when 3 =>
sla_out.rddata(31 downto 0) <= mm_mon_power_sum_hi;
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
end if;
end if;
@@ -140,7 +156,8 @@ begin
-- signals if it is necessary (to avoid using more logic than necessary).
------------------------------------------------------------------------------
- no_cross : if g_cross_clock_domain = false generate -- so mm_clk = st_clk
+ -- so mm_clk = st_clk
+ no_cross : if g_cross_clock_domain = false generate
p_mm_clk : process(mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -153,7 +170,8 @@ begin
end if;
end if;
end process;
- end generate; -- no_cross
+ -- no_cross
+ end generate;
gen_cross : if g_cross_clock_domain = true generate
u_mean_sum : entity common_lib.common_reg_cross_domain
@@ -163,13 +181,16 @@ begin
port map (
in_rst => st_rst,
in_clk => st_clk,
- in_new => st_mon_sync, -- when '1' then new in_dat is available after g_in_new_latency
+ -- when '1' then new in_dat is available after g_in_new_latency
+ in_new => st_mon_sync,
in_dat => st_mon_mean_sum,
- in_done => OPEN, -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done => OPEN,
out_rst => mm_rst,
out_clk => mm_clk,
out_dat => mm_mon_mean_sum,
- out_new => open -- when '1' then the out_dat was updated with in_dat due to in_new
+ -- when '1' then the out_dat was updated with in_dat due to in_new
+ out_new => open
);
u_pwr_sum : entity common_lib.common_reg_cross_domain
@@ -179,14 +200,18 @@ begin
port map (
in_rst => st_rst,
in_clk => st_clk,
- in_new => st_mon_sync, -- when '1' then new in_dat is available after g_in_new_latency
+ -- when '1' then new in_dat is available after g_in_new_latency
+ in_new => st_mon_sync,
in_dat => st_mon_power_sum,
- in_done => OPEN, -- pulses when no more pending in_new
+ -- pulses when no more pending in_new
+ in_done => OPEN,
out_rst => mm_rst,
out_clk => mm_clk,
out_dat => mm_mon_power_sum,
- out_new => open -- when '1' then the out_dat was updated with in_dat due to in_new
+ -- when '1' then the out_dat was updated with in_dat due to in_new
+ out_new => open
);
- end generate; -- gen_cross
+ -- gen_cross
+ end generate;
end rtl;
diff --git a/libraries/io/aduh/src/vhdl/aduh_pll.vhd b/libraries/io/aduh/src/vhdl/aduh_pll.vhd
index 4f0723adec991243a41e39e50a72eab5781958e2..760dc4086c3784a8c442791b7468640e3a8ddd26 100644
--- a/libraries/io/aduh/src/vhdl/aduh_pll.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_pll.vhd
@@ -81,30 +81,42 @@ entity aduh_pll is
-- LVDS Interface
-- . ADU_AB
- ADC_BI_AB_OVR : in std_logic := '0'; -- the ADU outputs one overflow bit, shared per 2 signal paths A,B
- ADC_BI_A : in std_logic_vector(g_ai.port_w - 1 downto 0); -- fixed ADC_BI port width port_w = 8
- ADC_BI_B : in std_logic_vector(g_ai.port_w - 1 downto 0); -- each ADC_BI port carries the data from 1 signal path
- ADC_BI_A_CLK : in std_logic; -- lvdsh_clk(1)
- ADC_BI_A_CLK_RST : out std_logic; -- release synchronises port A DCLK divider
+ -- the ADU outputs one overflow bit, shared per 2 signal paths A,B
+ ADC_BI_AB_OVR : in std_logic := '0';
+ -- fixed ADC_BI port width port_w = 8
+ ADC_BI_A : in std_logic_vector(g_ai.port_w - 1 downto 0);
+ -- each ADC_BI port carries the data from 1 signal path
+ ADC_BI_B : in std_logic_vector(g_ai.port_w - 1 downto 0);
+ -- lvdsh_clk(1)
+ ADC_BI_A_CLK : in std_logic;
+ -- release synchronises port A DCLK divider
+ ADC_BI_A_CLK_RST : out std_logic;
-- . ADU_CD
ADC_BI_CD_OVR : in std_logic := '0';
ADC_BI_C : in std_logic_vector(g_ai.port_w - 1 downto 0);
- ADC_BI_D : in std_logic_vector(g_ai.port_w - 1 downto 0); -- ports A,B connect to one ADU, ports C,D connect to another ADU
- ADC_BI_D_CLK : in std_logic; -- lvdsh_clk(0)
- ADC_BI_D_CLK_RST : out std_logic; -- release synchronises port D DCLK divider
+ -- ports A,B connect to one ADU, ports C,D connect to another ADU
+ ADC_BI_D : in std_logic_vector(g_ai.port_w - 1 downto 0);
+ -- lvdsh_clk(0)
+ ADC_BI_D_CLK : in std_logic;
+ -- release synchronises port D DCLK divider
+ ADC_BI_D_CLK_RST : out std_logic;
-- DP Interface
dp_clk : in std_logic;
-- . Control
- restart : in std_logic_vector(g_ai.nof_clocks - 1 downto 0); -- [ 0] = [ ADU_CD] Shared restart control for ADU-CD (nof_adu=1) or both ADU-AB and ADU-CD (nof_adu=2)
+ -- [ 0] = [ ADU_CD] Shared restart control for ADU-CD (nof_adu=1) or both ADU-AB and ADU-CD (nof_adu=2)
+ restart : in std_logic_vector(g_ai.nof_clocks - 1 downto 0);
-- [1:0] = [ADU_AB ADU_CD] Seperate restart control for per ADU (nof_adu=2)
- delay_settings : in t_natural_arr(func_aduh_pll_lvds_dat_w(g_ai) - 1 downto 0) := (others => 0); -- [ovrAB, portA, portB, ovrCD, portC, portD] or [ovrCD, portC, portD] : IOE data delay settings when g_use_dpa = FALSE
- cda_settings : in t_natural_arr(func_aduh_pll_lvds_dat_w(g_ai) - 1 downto 0) := (others => 0); -- [ovrAB, portA, portB, ovrCD, portC, portD] or [ovrCD, portC, portD] : channel data alignment settings
+ -- [ovrAB, portA, portB, ovrCD, portC, portD] or [ovrCD, portC, portD] : IOE data delay settings when g_use_dpa = FALSE
+ delay_settings : in t_natural_arr(func_aduh_pll_lvds_dat_w(g_ai) - 1 downto 0) := (others => 0);
+ -- [ovrAB, portA, portB, ovrCD, portC, portD] or [ovrCD, portC, portD] : channel data alignment settings
+ cda_settings : in t_natural_arr(func_aduh_pll_lvds_dat_w(g_ai) - 1 downto 0) := (others => 0);
-- . Streaming
- src_out : out t_dp_sosi_arr(0 to g_ai.nof_sp - 1) -- = [0:3] = ADC_BI ports [A,B,C,D] when nof_adu=2,
+ -- = [0:3] = ADC_BI ports [A,B,C,D] when nof_adu=2,
+ src_out : out t_dp_sosi_arr(0 to g_ai.nof_sp - 1)
-- = [0:3] = ADC_BI ports [0,0,C,D] when nof_adu=1
);
end aduh_pll;
@@ -114,17 +126,20 @@ architecture str of aduh_pll is
-- LVDS domain
-----------------------------------------------------------------------------
- constant c_lvds_clk_freq : natural := g_ai.lvds_data_rate / g_ai.lvds_deser_factor; -- 400 MHz, when lvds_clk from the adc08d1020 ADC on ADU provides the DDR of the sample clock
+ -- 400 MHz, when lvds_clk from the adc08d1020 ADC on ADU provides the DDR of the sample clock
+ constant c_lvds_clk_freq : natural := g_ai.lvds_data_rate / g_ai.lvds_deser_factor;
-- 200 MHz, when lvdsh_clk is connected to the dp_clk
-- Treat the LVDS input interface per reference clock, so use 1 or 2 lvdsh_pll
- constant c_lvdsh_dat_w : natural := func_aduh_pll_lvdsh_dat_w(g_ai); -- lvdsh_dat_w = lvds_dat_w / g_ai.nof_clocks
+ -- lvdsh_dat_w = lvds_dat_w / g_ai.nof_clocks
+ constant c_lvdsh_dat_w : natural := func_aduh_pll_lvdsh_dat_w(g_ai);
constant c_rcvdh_dat_w : natural := c_lvdsh_dat_w * g_ai.dp_deser_factor;
type t_lvdsh_dat_arr is array (integer range <>) of std_logic_vector(c_lvdsh_dat_w - 1 downto 0);
type t_rcvdh_dat_arr is array (integer range <>) of std_logic_vector(c_rcvdh_dat_w - 1 downto 0);
-- The dp_dat carries dp_deser_factor=4 samples for t0,t1,t2,t3 at 31:0, the optional overflow bit is carried via dp_ovr
- constant c_dp_dat_w : natural := g_ai.port_w * g_ai.dp_deser_factor; -- [31:0] = [t0,t1,t2,t3]
+ -- [31:0] = [t0,t1,t2,t3]
+ constant c_dp_dat_w : natural := g_ai.port_w * g_ai.dp_deser_factor;
type t_dp_dat_arr is array (integer range <>) of std_logic_vector(c_dp_dat_w - 1 downto 0);
@@ -137,22 +152,28 @@ architecture str of aduh_pll is
-- LVDS input
signal lvdsh_clk : t_sl_arr( g_ai.nof_clocks - 1 downto 0);
- signal lvdsh_dat : t_lvdsh_dat_arr(g_ai.nof_clocks - 1 downto 0); -- serialized LVDS Rx input data
+ -- serialized LVDS Rx input data
+ signal lvdsh_dat : t_lvdsh_dat_arr(g_ai.nof_clocks - 1 downto 0);
-----------------------------------------------------------------------------
-- Data Path clock domain, after clock domain crossing FIFO in LVDSH
-----------------------------------------------------------------------------
-- Index related to g_ai.nof_clocks, similar as for lvdsh_dat
- signal rcvdh_dat : t_rcvdh_dat_arr(g_ai.nof_clocks - 1 downto 0); -- received de-serialized data
+ -- received de-serialized data
+ signal rcvdh_dat : t_rcvdh_dat_arr(g_ai.nof_clocks - 1 downto 0);
signal rcvdh_val : t_sl_arr( g_ai.nof_clocks - 1 downto 0);
- signal porth_dat : t_rcvdh_dat_arr(g_ai.nof_clocks - 1 downto 0); -- received transpose rewired data
+ -- received transpose rewired data
+ signal porth_dat : t_rcvdh_dat_arr(g_ai.nof_clocks - 1 downto 0);
signal porth_val : t_sl_arr( g_ai.nof_clocks - 1 downto 0);
-- Index related to g_ai.nof_adu, similar as for src_out
- signal dp_ovr : t_sl_arr( 0 to g_ai.nof_sp - 1); -- [0:3]=[AB,AB,CD,CD] or [0:3]=[ 0, 0, CD,CD], vector OR of porth_dat overflow bits at t0,t1,t2,t3
- signal dp_dat : t_dp_dat_arr(0 to g_ai.nof_sp - 1); -- [0:3]=[ A, B, C, D] or [0:3]=[ 0, 0, C, D]
- signal dp_val : t_sl_arr( 0 to g_ai.nof_sp - 1); -- [0:3]=[ A, B, C, D] or [0:3]=[ 0, 0, C, D]
+ -- [0:3]=[AB,AB,CD,CD] or [0:3]=[ 0, 0, CD,CD], vector OR of porth_dat overflow bits at t0,t1,t2,t3
+ signal dp_ovr : t_sl_arr( 0 to g_ai.nof_sp - 1);
+ -- [0:3]=[ A, B, C, D] or [0:3]=[ 0, 0, C, D]
+ signal dp_dat : t_dp_dat_arr(0 to g_ai.nof_sp - 1);
+ -- [0:3]=[ A, B, C, D] or [0:3]=[ 0, 0, C, D]
+ signal dp_val : t_sl_arr( 0 to g_ai.nof_sp - 1);
begin
-- nof_clocks use_lvds_clk supported
-- 1 TRUE YES
@@ -179,20 +200,26 @@ begin
-- 1 2 YES - oABoCD
-- 2 2 YES oAB oCD
- input_one_lvdsh_pll : if g_ai.nof_clocks = 1 generate -- Use 1 clock, so there can be 1 or 2 ADUs
- ADC_BI_D_CLK_RST <= lvdsh_clk_rst(0); -- ADU lvdsh_clk phase reset control
- lvdsh_clk(0) <= ADC_BI_D_CLK when g_ai.use_lvds_clk = true else dp_clk; -- Only use the lvdsh_clk from ADU on port CD or use the dp_clk as LVDS Rx reference clock
- one_adu : if g_ai.nof_adu = 1 generate -- Use ADU on port CD
+ -- Use 1 clock, so there can be 1 or 2 ADUs
+ input_one_lvdsh_pll : if g_ai.nof_clocks = 1 generate
+ -- ADU lvdsh_clk phase reset control
+ ADC_BI_D_CLK_RST <= lvdsh_clk_rst(0);
+ -- Only use the lvdsh_clk from ADU on port CD or use the dp_clk as LVDS Rx reference clock
+ lvdsh_clk(0) <= ADC_BI_D_CLK when g_ai.use_lvds_clk = true else dp_clk;
+ -- Use ADU on port CD
+ one_adu : if g_ai.nof_adu = 1 generate
no_ovr : if g_ai.nof_ovr = 0 generate lvdsh_dat(0) <= ADC_BI_C & ADC_BI_D; end generate;
gen_ovr : if g_ai.nof_ovr = 1 generate lvdsh_dat(0) <= ADC_BI_CD_OVR & ADC_BI_C & ADC_BI_D; end generate;
end generate;
- two_adu : if g_ai.nof_adu = 2 generate -- Use both ADUs
+ -- Use both ADUs
+ two_adu : if g_ai.nof_adu = 2 generate
no_ovr : if g_ai.nof_ovr = 0 generate lvdsh_dat(0) <= ADC_BI_A & ADC_BI_B & ADC_BI_C & ADC_BI_D; end generate;
gen_ovr : if g_ai.nof_ovr = 1 generate lvdsh_dat(0) <= ADC_BI_AB_OVR & ADC_BI_A & ADC_BI_B & ADC_BI_CD_OVR & ADC_BI_C & ADC_BI_D; end generate;
end generate;
end generate;
- input_two_lvdsh_pll : if g_ai.nof_clocks = 2 generate -- Use 2 clocks, so there are also 2 ADU
+ -- Use 2 clocks, so there are also 2 ADU
+ input_two_lvdsh_pll : if g_ai.nof_clocks = 2 generate
ADC_BI_A_CLK_RST <= lvdsh_clk_rst(1);
ADC_BI_D_CLK_RST <= lvdsh_clk_rst(0);
@@ -221,11 +248,13 @@ begin
port map (
-- PHY LVDS Interface
lvds_clk_rst => lvdsh_clk_rst(I),
- lvds_clk => lvdsh_clk(I), -- the lvdsh_clk frequency is c_lvds_clk_freq
+ -- the lvdsh_clk frequency is c_lvds_clk_freq
+ lvds_clk => lvdsh_clk(I),
lvds_dat => lvdsh_dat(I),
-- DP Streaming Interface
- dp_clk => dp_clk, -- the dp_clk frequency is g_lvds_data_rate / g_dp_deser_factor
+ -- the dp_clk frequency is g_lvds_data_rate / g_dp_deser_factor
+ dp_clk => dp_clk,
-- . Control
dp_lvds_reset => restart(I),
@@ -236,7 +265,8 @@ begin
dp_dat => rcvdh_dat(I),
dp_val => rcvdh_val(I)
);
- end generate; -- gen_clk
+ -- gen_clk
+ end generate;
-----------------------------------------------------------------------------
-- Handle lvdsh_pll output
@@ -298,154 +328,269 @@ begin
porth_val <= rcvdh_val;
gen_dp_1_1_1 : if g_ai.nof_adu = 1 and g_ai.nof_clocks = 1 and g_ai.nof_ovr = 1 generate
- porth_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ) <= rcvdh_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ); -- bit OVR_CD
- porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port C
- porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port D
+ -- bit OVR_CD
+ porth_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ) <= rcvdh_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w );
+ -- port C
+ porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+ -- port D
+ porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
-- port [0:1]=[A,B] is not used
- dp_ovr(2) <= dp_ovr(3); -- bit OVR_C = OVR_CD
- dp_ovr(3) <= vector_or(porth_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w)); -- bit OVR_D = OVR_CD
- dp_dat(2) <= porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w); -- port C
- dp_dat(3) <= porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w); -- port D
- dp_val(2) <= porth_val(0); -- port C
- dp_val(3) <= porth_val(0); -- port D
+ -- bit OVR_C = OVR_CD
+ dp_ovr(2) <= dp_ovr(3);
+ -- bit OVR_D = OVR_CD
+ dp_ovr(3) <= vector_or(porth_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w));
+ -- port C
+ dp_dat(2) <= porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w);
+ -- port D
+ dp_dat(3) <= porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w);
+ -- port C
+ dp_val(2) <= porth_val(0);
+ -- port D
+ dp_val(3) <= porth_val(0);
src_out(0) <= c_dp_sosi_rst;
src_out(1) <= c_dp_sosi_rst;
- src_out(2).data <= RESIZE_DP_DATA(dp_ovr(2) & dp_dat(2)); -- port C
- src_out(3).data <= RESIZE_DP_DATA(dp_ovr(3) & dp_dat(3)); -- port D
- src_out(2).valid <= dp_val(2); -- port C
- src_out(3).valid <= dp_val(3); -- port D
+ -- port C
+ src_out(2).data <= RESIZE_DP_DATA(dp_ovr(2) & dp_dat(2));
+ -- port D
+ src_out(3).data <= RESIZE_DP_DATA(dp_ovr(3) & dp_dat(3));
+ -- port C
+ src_out(2).valid <= dp_val(2);
+ -- port D
+ src_out(3).valid <= dp_val(3);
end generate;
gen_dp_1_1_0 : if g_ai.nof_adu = 1 and g_ai.nof_clocks = 1 and g_ai.nof_ovr = 0 generate
- porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port C
- porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port D
+ -- port C
+ porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+ -- port D
+ porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
-- port [0:1]=[A,B] is not used
- dp_dat(2) <= porth_dat(0)(2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w); -- port C
- dp_dat(3) <= porth_dat(0)(1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w); -- port D
- dp_val(2) <= porth_val(0); -- port C
- dp_val(3) <= porth_val(0); -- port D
+ -- port C
+ dp_dat(2) <= porth_dat(0)(2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w);
+ -- port D
+ dp_dat(3) <= porth_dat(0)(1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w);
+ -- port C
+ dp_val(2) <= porth_val(0);
+ -- port D
+ dp_val(3) <= porth_val(0);
src_out(0) <= c_dp_sosi_rst;
src_out(1) <= c_dp_sosi_rst;
- src_out(2).data <= RESIZE_DP_DATA(dp_dat(2)); -- port C
- src_out(3).data <= RESIZE_DP_DATA(dp_dat(3)); -- port D
- src_out(2).valid <= dp_val(2); -- port C
- src_out(3).valid <= dp_val(3); -- port D
+ -- port C
+ src_out(2).data <= RESIZE_DP_DATA(dp_dat(2));
+ -- port D
+ src_out(3).data <= RESIZE_DP_DATA(dp_dat(3));
+ -- port C
+ src_out(2).valid <= dp_val(2);
+ -- port D
+ src_out(3).valid <= dp_val(3);
end generate;
gen_dp_2_1_1 : if g_ai.nof_adu = 2 and g_ai.nof_clocks = 1 and g_ai.nof_ovr = 1 generate
- porth_dat(0)(g_ai.dp_deser_factor + 4 * c_dp_dat_w downto 4 * c_dp_dat_w + 1) <= rcvdh_dat(0)(g_ai.dp_deser_factor + 4 * c_dp_dat_w downto 4 * c_dp_dat_w + 1); -- bit OVR_AB
- porth_dat(0)( 4 * c_dp_dat_w downto 3 * c_dp_dat_w + 1) <= transpose(rcvdh_dat(0)( 4 * c_dp_dat_w downto 3 * c_dp_dat_w + 1), g_ai.dp_deser_factor, g_ai.port_w); -- port A
- porth_dat(0)( 3 * c_dp_dat_w downto 2 * c_dp_dat_w + 1) <= transpose(rcvdh_dat(0)( 3 * c_dp_dat_w downto 2 * c_dp_dat_w + 1), g_ai.dp_deser_factor, g_ai.port_w); -- port B
- porth_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ) <= rcvdh_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ); -- bit OVR_CD
- porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port C
- porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port D
-
- dp_ovr(0) <= dp_ovr(1); -- bit OVR_A = OVR_AB
- dp_ovr(1) <= vector_or(porth_dat(0)(g_ai.dp_deser_factor + 4 * c_dp_dat_w downto 4 * c_dp_dat_w + 1)); -- bit OVR_B = OVR_AB
- dp_ovr(2) <= dp_ovr(3); -- bit OVR_C = OVR_CD
- dp_ovr(3) <= vector_or(porth_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w )); -- bit OVR_D = OVR_CD
- dp_dat(0) <= porth_dat(0)( 4 * c_dp_dat_w downto 3 * c_dp_dat_w + 1); -- port A
- dp_dat(1) <= porth_dat(0)( 3 * c_dp_dat_w downto 2 * c_dp_dat_w + 1); -- port B
- dp_dat(2) <= porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ); -- port C
- dp_dat(3) <= porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ); -- port D
- dp_val(0) <= porth_val(0); -- port A
- dp_val(1) <= porth_val(0); -- port B
- dp_val(2) <= porth_val(0); -- port C
- dp_val(3) <= porth_val(0); -- port D
-
- src_out(0).data <= RESIZE_DP_DATA(dp_ovr(0) & dp_dat(0)); -- port A
- src_out(1).data <= RESIZE_DP_DATA(dp_ovr(1) & dp_dat(1)); -- port B
- src_out(2).data <= RESIZE_DP_DATA(dp_ovr(2) & dp_dat(2)); -- port C
- src_out(3).data <= RESIZE_DP_DATA(dp_ovr(3) & dp_dat(3)); -- port D
- src_out(0).valid <= dp_val(0); -- port A
- src_out(1).valid <= dp_val(1); -- port B
- src_out(2).valid <= dp_val(2); -- port C
- src_out(3).valid <= dp_val(3); -- port D
+ -- bit OVR_AB
+ porth_dat(0)(g_ai.dp_deser_factor + 4 * c_dp_dat_w downto 4 * c_dp_dat_w + 1) <= rcvdh_dat(0)(g_ai.dp_deser_factor + 4 * c_dp_dat_w downto 4 * c_dp_dat_w + 1);
+ -- port A
+ porth_dat(0)( 4 * c_dp_dat_w downto 3 * c_dp_dat_w + 1) <= transpose(rcvdh_dat(0)( 4 * c_dp_dat_w downto 3 * c_dp_dat_w + 1), g_ai.dp_deser_factor, g_ai.port_w);
+ -- port B
+ porth_dat(0)( 3 * c_dp_dat_w downto 2 * c_dp_dat_w + 1) <= transpose(rcvdh_dat(0)( 3 * c_dp_dat_w downto 2 * c_dp_dat_w + 1), g_ai.dp_deser_factor, g_ai.port_w);
+ -- bit OVR_CD
+ porth_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ) <= rcvdh_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w );
+ -- port C
+ porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+ -- port D
+ porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+
+ -- bit OVR_A = OVR_AB
+ dp_ovr(0) <= dp_ovr(1);
+ -- bit OVR_B = OVR_AB
+ dp_ovr(1) <= vector_or(porth_dat(0)(g_ai.dp_deser_factor + 4 * c_dp_dat_w downto 4 * c_dp_dat_w + 1));
+ -- bit OVR_C = OVR_CD
+ dp_ovr(2) <= dp_ovr(3);
+ -- bit OVR_D = OVR_CD
+ dp_ovr(3) <= vector_or(porth_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ));
+ -- port A
+ dp_dat(0) <= porth_dat(0)( 4 * c_dp_dat_w downto 3 * c_dp_dat_w + 1);
+ -- port B
+ dp_dat(1) <= porth_dat(0)( 3 * c_dp_dat_w downto 2 * c_dp_dat_w + 1);
+ -- port C
+ dp_dat(2) <= porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w );
+ -- port D
+ dp_dat(3) <= porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w );
+ -- port A
+ dp_val(0) <= porth_val(0);
+ -- port B
+ dp_val(1) <= porth_val(0);
+ -- port C
+ dp_val(2) <= porth_val(0);
+ -- port D
+ dp_val(3) <= porth_val(0);
+
+ -- port A
+ src_out(0).data <= RESIZE_DP_DATA(dp_ovr(0) & dp_dat(0));
+ -- port B
+ src_out(1).data <= RESIZE_DP_DATA(dp_ovr(1) & dp_dat(1));
+ -- port C
+ src_out(2).data <= RESIZE_DP_DATA(dp_ovr(2) & dp_dat(2));
+ -- port D
+ src_out(3).data <= RESIZE_DP_DATA(dp_ovr(3) & dp_dat(3));
+ -- port A
+ src_out(0).valid <= dp_val(0);
+ -- port B
+ src_out(1).valid <= dp_val(1);
+ -- port C
+ src_out(2).valid <= dp_val(2);
+ -- port D
+ src_out(3).valid <= dp_val(3);
end generate;
gen_dp_2_1_0 : if g_ai.nof_adu = 2 and g_ai.nof_clocks = 1 and g_ai.nof_ovr = 0 generate
- porth_dat(0)( 4 * c_dp_dat_w - 1 downto 3 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 4 * c_dp_dat_w - 1 downto 3 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port A
- porth_dat(0)( 3 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 3 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port B
- porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port C
- porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port D
-
- dp_dat(0) <= porth_dat(0)(4 * c_dp_dat_w - 1 downto 3 * c_dp_dat_w); -- port A
- dp_dat(1) <= porth_dat(0)(3 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w); -- port B
- dp_dat(2) <= porth_dat(0)(2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w); -- port C
- dp_dat(3) <= porth_dat(0)(1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w); -- port D
- dp_val(0) <= porth_val(0); -- port A
- dp_val(1) <= porth_val(0); -- port B
- dp_val(2) <= porth_val(0); -- port C
- dp_val(3) <= porth_val(0); -- port D
-
- src_out(0).data <= RESIZE_DP_DATA(dp_dat(0)); -- port A
- src_out(1).data <= RESIZE_DP_DATA(dp_dat(1)); -- port B
- src_out(2).data <= RESIZE_DP_DATA(dp_dat(2)); -- port C
- src_out(3).data <= RESIZE_DP_DATA(dp_dat(3)); -- port D
- src_out(0).valid <= dp_val(0); -- port A
- src_out(1).valid <= dp_val(1); -- port B
- src_out(2).valid <= dp_val(2); -- port C
- src_out(3).valid <= dp_val(3); -- port D
+ -- port A
+ porth_dat(0)( 4 * c_dp_dat_w - 1 downto 3 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 4 * c_dp_dat_w - 1 downto 3 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+ -- port B
+ porth_dat(0)( 3 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 3 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+ -- port C
+ porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+ -- port D
+ porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+
+ -- port A
+ dp_dat(0) <= porth_dat(0)(4 * c_dp_dat_w - 1 downto 3 * c_dp_dat_w);
+ -- port B
+ dp_dat(1) <= porth_dat(0)(3 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w);
+ -- port C
+ dp_dat(2) <= porth_dat(0)(2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w);
+ -- port D
+ dp_dat(3) <= porth_dat(0)(1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w);
+ -- port A
+ dp_val(0) <= porth_val(0);
+ -- port B
+ dp_val(1) <= porth_val(0);
+ -- port C
+ dp_val(2) <= porth_val(0);
+ -- port D
+ dp_val(3) <= porth_val(0);
+
+ -- port A
+ src_out(0).data <= RESIZE_DP_DATA(dp_dat(0));
+ -- port B
+ src_out(1).data <= RESIZE_DP_DATA(dp_dat(1));
+ -- port C
+ src_out(2).data <= RESIZE_DP_DATA(dp_dat(2));
+ -- port D
+ src_out(3).data <= RESIZE_DP_DATA(dp_dat(3));
+ -- port A
+ src_out(0).valid <= dp_val(0);
+ -- port B
+ src_out(1).valid <= dp_val(1);
+ -- port C
+ src_out(2).valid <= dp_val(2);
+ -- port D
+ src_out(3).valid <= dp_val(3);
end generate;
gen_dp_2_2_1 : if g_ai.nof_adu = 2 and g_ai.nof_clocks = 2 and g_ai.nof_ovr = 1 generate
- porth_dat(1)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ) <= rcvdh_dat(1)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ); -- bit OVR_AB
- porth_dat(1)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(1)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port A
- porth_dat(1)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(1)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port B
- porth_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ) <= rcvdh_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ); -- bit OVR_CD
- porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port C
- porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port D
-
- dp_ovr(0) <= dp_ovr(1); -- bit OVR_A = OVR_AB
- dp_ovr(1) <= vector_or(porth_dat(1)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w)); -- bit OVR_B = OVR_AB
- dp_ovr(2) <= dp_ovr(3); -- bit OVR_C = OVR_CD
- dp_ovr(3) <= vector_or(porth_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w)); -- bit OVR_D = OVR_CD
- dp_dat(0) <= porth_dat(1)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w); -- port A
- dp_dat(1) <= porth_dat(1)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w); -- port B
- dp_dat(2) <= porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w); -- port C
- dp_dat(3) <= porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w); -- port D
- dp_val(0) <= porth_val(1); -- port A
- dp_val(1) <= porth_val(1); -- port B
- dp_val(2) <= porth_val(0); -- port C
- dp_val(3) <= porth_val(0); -- port D
-
- src_out(0).data <= RESIZE_DP_DATA(dp_ovr(0) & dp_dat(0)); -- port A
- src_out(1).data <= RESIZE_DP_DATA(dp_ovr(1) & dp_dat(1)); -- port B
- src_out(2).data <= RESIZE_DP_DATA(dp_ovr(2) & dp_dat(2)); -- port C
- src_out(3).data <= RESIZE_DP_DATA(dp_ovr(3) & dp_dat(3)); -- port D
- src_out(0).valid <= dp_val(0); -- port A
- src_out(1).valid <= dp_val(1); -- port B
- src_out(2).valid <= dp_val(2); -- port C
- src_out(3).valid <= dp_val(3); -- port D
+ -- bit OVR_AB
+ porth_dat(1)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ) <= rcvdh_dat(1)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w );
+ -- port A
+ porth_dat(1)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(1)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+ -- port B
+ porth_dat(1)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(1)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+ -- bit OVR_CD
+ porth_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w ) <= rcvdh_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w );
+ -- port C
+ porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+ -- port D
+ porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+
+ -- bit OVR_A = OVR_AB
+ dp_ovr(0) <= dp_ovr(1);
+ -- bit OVR_B = OVR_AB
+ dp_ovr(1) <= vector_or(porth_dat(1)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w));
+ -- bit OVR_C = OVR_CD
+ dp_ovr(2) <= dp_ovr(3);
+ -- bit OVR_D = OVR_CD
+ dp_ovr(3) <= vector_or(porth_dat(0)(g_ai.dp_deser_factor + 2 * c_dp_dat_w - 1 downto 2 * c_dp_dat_w));
+ -- port A
+ dp_dat(0) <= porth_dat(1)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w);
+ -- port B
+ dp_dat(1) <= porth_dat(1)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w);
+ -- port C
+ dp_dat(2) <= porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w);
+ -- port D
+ dp_dat(3) <= porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w);
+ -- port A
+ dp_val(0) <= porth_val(1);
+ -- port B
+ dp_val(1) <= porth_val(1);
+ -- port C
+ dp_val(2) <= porth_val(0);
+ -- port D
+ dp_val(3) <= porth_val(0);
+
+ -- port A
+ src_out(0).data <= RESIZE_DP_DATA(dp_ovr(0) & dp_dat(0));
+ -- port B
+ src_out(1).data <= RESIZE_DP_DATA(dp_ovr(1) & dp_dat(1));
+ -- port C
+ src_out(2).data <= RESIZE_DP_DATA(dp_ovr(2) & dp_dat(2));
+ -- port D
+ src_out(3).data <= RESIZE_DP_DATA(dp_ovr(3) & dp_dat(3));
+ -- port A
+ src_out(0).valid <= dp_val(0);
+ -- port B
+ src_out(1).valid <= dp_val(1);
+ -- port C
+ src_out(2).valid <= dp_val(2);
+ -- port D
+ src_out(3).valid <= dp_val(3);
end generate;
gen_dp_2_2_0 : if g_ai.nof_adu = 2 and g_ai.nof_clocks = 2 and g_ai.nof_ovr = 0 generate
- porth_dat(1)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(1)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port A
- porth_dat(1)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(1)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port B
- porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port C
- porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w); -- port D
-
- dp_dat(0) <= porth_dat(1)(2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w); -- port A
- dp_dat(1) <= porth_dat(1)(1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w); -- port B
- dp_dat(2) <= porth_dat(0)(2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w); -- port C
- dp_dat(3) <= porth_dat(0)(1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w); -- port D
- dp_val(0) <= porth_val(1); -- port A
- dp_val(1) <= porth_val(1); -- port B
- dp_val(2) <= porth_val(0); -- port C
- dp_val(3) <= porth_val(0); -- port D
-
- src_out(0).data <= RESIZE_DP_DATA(dp_dat(0)); -- port A
- src_out(1).data <= RESIZE_DP_DATA(dp_dat(1)); -- port B
- src_out(2).data <= RESIZE_DP_DATA(dp_dat(2)); -- port C
- src_out(3).data <= RESIZE_DP_DATA(dp_dat(3)); -- port D
- src_out(0).valid <= dp_val(0); -- port A
- src_out(1).valid <= dp_val(1); -- port B
- src_out(2).valid <= dp_val(2); -- port C
- src_out(3).valid <= dp_val(3); -- port D
+ -- port A
+ porth_dat(1)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(1)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+ -- port B
+ porth_dat(1)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(1)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+ -- port C
+ porth_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+ -- port D
+ porth_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ) <= transpose(rcvdh_dat(0)( 1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w ), g_ai.dp_deser_factor, g_ai.port_w);
+
+ -- port A
+ dp_dat(0) <= porth_dat(1)(2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w);
+ -- port B
+ dp_dat(1) <= porth_dat(1)(1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w);
+ -- port C
+ dp_dat(2) <= porth_dat(0)(2 * c_dp_dat_w - 1 downto 1 * c_dp_dat_w);
+ -- port D
+ dp_dat(3) <= porth_dat(0)(1 * c_dp_dat_w - 1 downto 0 * c_dp_dat_w);
+ -- port A
+ dp_val(0) <= porth_val(1);
+ -- port B
+ dp_val(1) <= porth_val(1);
+ -- port C
+ dp_val(2) <= porth_val(0);
+ -- port D
+ dp_val(3) <= porth_val(0);
+
+ -- port A
+ src_out(0).data <= RESIZE_DP_DATA(dp_dat(0));
+ -- port B
+ src_out(1).data <= RESIZE_DP_DATA(dp_dat(1));
+ -- port C
+ src_out(2).data <= RESIZE_DP_DATA(dp_dat(2));
+ -- port D
+ src_out(3).data <= RESIZE_DP_DATA(dp_dat(3));
+ -- port A
+ src_out(0).valid <= dp_val(0);
+ -- port B
+ src_out(1).valid <= dp_val(1);
+ -- port C
+ src_out(2).valid <= dp_val(2);
+ -- port D
+ src_out(3).valid <= dp_val(3);
end generate;
end str;
diff --git a/libraries/io/aduh/src/vhdl/aduh_pll_pkg.vhd b/libraries/io/aduh/src/vhdl/aduh_pll_pkg.vhd
index f9d4ff32066f5729f9f1a190d0752808ba6e74c5..601e1d9f5449a16b7f5bb02c2ca0e90f7b407208 100644
--- a/libraries/io/aduh/src/vhdl/aduh_pll_pkg.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_pll_pkg.vhd
@@ -26,30 +26,46 @@ use IEEE.numeric_std.all;
package aduh_pll_pkg is
-- ADU Interface
type t_c_aduh_pll_ai is record
- nof_sp : natural; -- = 4; -- Fixed support 4 signal paths A,B,C,D, whether they contain active data depends on nof_adu
- nof_adu : natural; -- = 2; -- When 2 ADUs then use all 4 ports A,B,C,D, one ADU on ports A,B and one ADU on ports C,D,
+ -- = 4; -- Fixed support 4 signal paths A,B,C,D, whether they contain active data depends on nof_adu
+ nof_sp : natural;
+ -- = 2; -- When 2 ADUs then use all 4 ports A,B,C,D, one ADU on ports A,B and one ADU on ports C,D,
+ nof_adu : natural;
-- when 1 ADU then only use ports C,D
- nof_ports : natural; -- = 2; -- Fixed 2 ADC BI ports per ADU
- port_w : natural; -- = 8; -- Fixed 8 bit ADC BI port width, the ADC sample width is also 8 bit
- nof_ovr : natural; -- = 0; -- There is 1 overflow bit per ADU, use 0 to ignore the overflow input
- lvds_data_rate : natural; -- = 800; -- The ADC sample rate is 800 Msps, so the LVDS rate is 800 Mbps per ADC BI data line,
- use_dpa : boolean; -- = TRUE; -- When TRUE use LVDS_RX with DPA, else used fixed IOE delays and/or lvds_clk_phase instead of DPA
- use_lvds_clk : boolean; -- = TRUE; -- When TRUE use the one or both ADC BI lvds_clk, else use the single dp_clk to capture the lvds data
- use_lvds_clk_rst : boolean; -- = FALSE; -- When TRUE then support reset pulse to ADU to align the lvds_clk to the dp_clk, else no support
- lvds_clk_phase : natural; -- = 0; -- Use PLL phase 0 for edge aligned, phase 180 for center aligned. Only for no DPA
- nof_clocks : natural; -- = 2; -- Must be <= nof_adu
+ -- = 2; -- Fixed 2 ADC BI ports per ADU
+ nof_ports : natural;
+ -- = 8; -- Fixed 8 bit ADC BI port width, the ADC sample width is also 8 bit
+ port_w : natural;
+ -- = 0; -- There is 1 overflow bit per ADU, use 0 to ignore the overflow input
+ nof_ovr : natural;
+ -- = 800; -- The ADC sample rate is 800 Msps, so the LVDS rate is 800 Mbps per ADC BI data line,
+ lvds_data_rate : natural;
+ -- = TRUE; -- When TRUE use LVDS_RX with DPA, else used fixed IOE delays and/or lvds_clk_phase instead of DPA
+ use_dpa : boolean;
+ -- = TRUE; -- When TRUE use the one or both ADC BI lvds_clk, else use the single dp_clk to capture the lvds data
+ use_lvds_clk : boolean;
+ -- = FALSE; -- When TRUE then support reset pulse to ADU to align the lvds_clk to the dp_clk, else no support
+ use_lvds_clk_rst : boolean;
+ -- = 0; -- Use PLL phase 0 for edge aligned, phase 180 for center aligned. Only for no DPA
+ lvds_clk_phase : natural;
+ -- = 2; -- Must be <= nof_adu
+ nof_clocks : natural;
-- 1 --> Use ADC BI clock D or dp_clk for one or both ADU
-- 2 --> Use ADC BI clock A for/from ADU-AB and clock D for/from the ADU-CD
- lvds_deser_factor : natural; -- = 2; -- The ADC sampled data comes in with a DDR lvds_clk, so lvds_data_rate / 2 or
+ -- = 2; -- The ADC sampled data comes in with a DDR lvds_clk, so lvds_data_rate / 2 or
+ lvds_deser_factor : natural;
-- the 4 when the Data Path clock dp_clk is also used as LVDS data reference lvds_clk clock
- dp_deser_factor : natural; -- = 4; -- The Data Path clock dp_clk frequency is 200 MHz, so lvds_data_rate / 4
+ -- = 4; -- The Data Path clock dp_clk frequency is 200 MHz, so lvds_data_rate / 4
+ dp_deser_factor : natural;
end record;
constant c_aduh_pll_ai : t_c_aduh_pll_ai := (4, 2, 2, 8, 0, 800, true, true, false, 0, 2, 2, 4);
- function func_aduh_pll_adu_dat_w(ai : t_c_aduh_pll_ai) return natural; -- LVDS data width per ADU: two ADCs with one optional overflow bit
- function func_aduh_pll_lvds_dat_w(ai : t_c_aduh_pll_ai) return natural; -- LVDS data width per ADUH: one or two ADUs
- function func_aduh_pll_lvdsh_dat_w(ai : t_c_aduh_pll_ai) return natural; -- LVDS data width per LVDSH: dependent on whether one or two LVDS reference clocks are used
+ -- LVDS data width per ADU: two ADCs with one optional overflow bit
+ function func_aduh_pll_adu_dat_w(ai : t_c_aduh_pll_ai) return natural;
+ -- LVDS data width per ADUH: one or two ADUs
+ function func_aduh_pll_lvds_dat_w(ai : t_c_aduh_pll_ai) return natural;
+ -- LVDS data width per LVDSH: dependent on whether one or two LVDS reference clocks are used
+ function func_aduh_pll_lvdsh_dat_w(ai : t_c_aduh_pll_ai) return natural;
end aduh_pll_pkg;
diff --git a/libraries/io/aduh/src/vhdl/aduh_power_sum.vhd b/libraries/io/aduh/src/vhdl/aduh_power_sum.vhd
index 4b0f5a0cee1ef4dcc4e32542f67af25f1b781430..73c5849249c864afb45a69f5755de4ba4d38e772 100644
--- a/libraries/io/aduh/src/vhdl/aduh_power_sum.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_power_sum.vhd
@@ -37,10 +37,14 @@ entity aduh_power_sum is
g_technology : natural := c_tech_select_default;
g_variant : string := "RTL";
g_symbol_w : natural := 12;
- g_nof_symbols_per_data : natural := 4; -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
- g_nof_accumulations : natural := 800 * 10**6; -- integration time in symbols
- g_pwr_sum_truncate : boolean := true; -- when TRUE truncate (keep MS part) else resize (keep sign and LS part)
- g_pwr_sum_w : natural := 32 -- typcially MM word width (= 32) or double MM word width (= 64)
+ -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data : natural := 4;
+ -- integration time in symbols
+ g_nof_accumulations : natural := 800 * 10**6;
+ -- when TRUE truncate (keep MS part) else resize (keep sign and LS part)
+ g_pwr_sum_truncate : boolean := true;
+ -- typcially MM word width (= 32) or double MM word width (= 64)
+ g_pwr_sum_w : natural := 32
);
port (
clk : in std_logic;
@@ -53,7 +57,8 @@ entity aduh_power_sum is
-- Accumulation outputs
pwr_sum : out std_logic_vector(g_pwr_sum_w - 1 downto 0);
- pwr_sum_sync : out std_logic -- af sum_sync there is a new sum
+ -- af sum_sync there is a new sum
+ pwr_sum_sync : out std_logic
);
end aduh_power_sum;
@@ -78,11 +83,16 @@ begin
g_variant => g_variant,
g_in_a_w => g_symbol_w,
g_in_b_w => g_symbol_w,
- g_out_p_w => c_prod_w, -- <= g_in_a_w + g_in_b_w
- g_nof_mult => g_nof_symbols_per_data, -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_product => 1, -- 0 or 1
- g_pipeline_output => 0, -- >= 0
+ -- <= g_in_a_w + g_in_b_w
+ g_out_p_w => c_prod_w,
+ -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+ g_nof_mult => g_nof_symbols_per_data,
+ -- 0 or 1
+ g_pipeline_input => 0,
+ -- 0 or 1
+ g_pipeline_product => 1,
+ -- >= 0
+ g_pipeline_output => 0,
g_representation => "SIGNED"
)
port map (
@@ -95,7 +105,8 @@ begin
u_prod_sync : entity common_lib.common_pipeline_sl
generic map (
- g_pipeline => c_pipeline_prod, -- = 1, must match total pipelining of u_prod_data
+ -- = 1, must match total pipelining of u_prod_data
+ g_pipeline => c_pipeline_prod,
g_reset_value => 0
)
port map (
@@ -107,7 +118,8 @@ begin
u_prod_val : entity common_lib.common_pipeline_sl
generic map (
- g_pipeline => c_pipeline_prod, -- = 1, must match total pipelining of u_prod_data
+ -- = 1, must match total pipelining of u_prod_data
+ g_pipeline => c_pipeline_prod,
g_reset_value => 0
)
port map (
diff --git a/libraries/io/aduh/src/vhdl/aduh_quad.vhd b/libraries/io/aduh/src/vhdl/aduh_quad.vhd
index 1d93bfab80e3d775c5f7414f737925cfa03da25d..c07b710c6a32b99b582b30d957bb724ff2f05240 100644
--- a/libraries/io/aduh/src/vhdl/aduh_quad.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_quad.vhd
@@ -32,7 +32,8 @@ entity aduh_quad is
generic (
-- ADC Interface
g_sim : boolean := false;
- g_nof_dp_phs_clk : natural := 1; -- nof dp_phs_clk that can be used to detect the word phase
+ -- nof dp_phs_clk that can be used to detect the word phase
+ g_nof_dp_phs_clk : natural := 1;
g_ai : t_c_aduh_dd_ai := c_aduh_dd_ai
);
port (
@@ -55,7 +56,8 @@ entity aduh_quad is
dp_phs_clk_vec : in std_logic_vector(g_nof_dp_phs_clk - 1 downto 0);
-- . data
- aduh_sosi_arr : out t_dp_sosi_arr(0 to g_ai.nof_sp - 1); -- = [0:3] = ADC_BI ports [A,B,C,D]
+ -- = [0:3] = ADC_BI ports [A,B,C,D]
+ aduh_sosi_arr : out t_dp_sosi_arr(0 to g_ai.nof_sp - 1);
-- . status
aduh_ab_status : out std_logic_vector(c_word_w - 1 downto 0);
@@ -70,7 +72,8 @@ entity aduh_quad is
aduh_cd_stable_ack : in std_logic;
aduh_cd_control : in std_logic_vector(c_word_w - 1 downto 0);
- aduh_verify_res : out t_slv_32_arr(0 to g_ai.nof_sp - 1); -- [8,7:0]
+ -- [8,7:0]
+ aduh_verify_res : out t_slv_32_arr(0 to g_ai.nof_sp - 1);
aduh_verify_res_val : out std_logic_vector(0 to g_ai.nof_sp - 1);
aduh_verify_res_ack : in std_logic_vector(0 to g_ai.nof_sp - 1)
);
@@ -78,14 +81,17 @@ end aduh_quad;
architecture str of aduh_quad is
constant c_dp_factor : natural := g_ai.rx_factor * g_ai.dd_factor;
- constant c_wideband_factor : natural := c_dp_factor; -- Wideband rate factor = 4 for dp_clk is 200 MHz frequency and sample frequency Fs is 800 MHz
+ -- Wideband rate factor = 4 for dp_clk is 200 MHz frequency and sample frequency Fs is 800 MHz
+ constant c_wideband_factor : natural := c_dp_factor;
- constant c_adc_pattern_sel : t_natural_arr(0 to g_ai.nof_sp - 1) := (0, 1, 0, 1); -- signal path [A, B, C, D] = ADC [I, Q, I, Q]
+ -- signal path [A, B, C, D] = ADC [I, Q, I, Q]
+ constant c_adc_pattern_sel : t_natural_arr(0 to g_ai.nof_sp - 1) := (0, 1, 0, 1);
signal aduh_ab_dp_phs_clk_en_vec : std_logic_vector(g_nof_dp_phs_clk - 1 downto 0);
signal aduh_cd_dp_phs_clk_en_vec : std_logic_vector(g_nof_dp_phs_clk - 1 downto 0);
- signal i_aduh_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1); -- = [0:3] = ADC_BI ports [A,B,C,D]
+ -- = [0:3] = ADC_BI ports [A,B,C,D]
+ signal i_aduh_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1);
begin
-- ADC [A,B,C,D] input samples
aduh_sosi_arr <= i_aduh_sosi_arr;
@@ -106,11 +112,15 @@ begin
ADC_BI_C => ADC_BI_C,
ADC_BI_D => ADC_BI_D,
- ADC_BI_A_CLK => ADC_BI_A_CLK, -- lvds clock from ADU_AB
- ADC_BI_D_CLK => ADC_BI_D_CLK, -- lvds clock from ADU_CD
+ -- lvds clock from ADU_AB
+ ADC_BI_A_CLK => ADC_BI_A_CLK,
+ -- lvds clock from ADU_CD
+ ADC_BI_D_CLK => ADC_BI_D_CLK,
- ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST, -- release synchronises ADU_AB DCLK divider
- ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST, -- release synchronises ADU_CD DCLK divider
+ -- release synchronises ADU_AB DCLK divider
+ ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST,
+ -- release synchronises ADU_CD DCLK divider
+ ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
-- DP Interface
dp_rst => dp_rst,
@@ -136,12 +146,15 @@ begin
-- ADC pattern verification
gen_verify : for I in 0 to g_ai.nof_sp - 1 generate
- aduh_verify_res(I)(c_word_w - 1 downto g_ai.port_w + 1) <= (others => '0'); -- unused bits [31:9]
+ -- unused bits [31:9]
+ aduh_verify_res(I)(c_word_w - 1 downto g_ai.port_w + 1) <= (others => '0');
u_adc : entity work.aduh_verify
generic map (
- g_symbol_w => g_ai.port_w, -- = 8, fixed
- g_nof_symbols_per_data => c_wideband_factor -- = 4, fixed, big endian in_sosi.data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ -- = 8, fixed
+ g_symbol_w => g_ai.port_w,
+ -- = 4, fixed, big endian in_sosi.data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data => c_wideband_factor
)
port map (
rst => dp_rst,
@@ -152,7 +165,8 @@ begin
-- Static control input (connect via MM or leave open to use default)
pattern_sel => c_adc_pattern_sel(I),
- verify_res => aduh_verify_res(I)(g_ai.port_w downto 0), -- [8,7:0]
+ -- [8,7:0]
+ verify_res => aduh_verify_res(I)(g_ai.port_w downto 0),
verify_res_val => aduh_verify_res_val(I),
verify_res_ack => aduh_verify_res_ack(I)
);
diff --git a/libraries/io/aduh/src/vhdl/aduh_quad_reg.vhd b/libraries/io/aduh/src/vhdl/aduh_quad_reg.vhd
index f048db7912d07bc2d7a453e609826a997f82b1f1..4fa853a2c2f30c29a43c1b4da6804cbb136a7d48 100644
--- a/libraries/io/aduh/src/vhdl/aduh_quad_reg.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_quad_reg.vhd
@@ -52,19 +52,27 @@ use common_lib.common_mem_pkg.all;
entity aduh_quad_reg is
generic (
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_nof_dp_phs_clk : natural := 1 -- nof dp_phs_clk that can be used to detect the word phase
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
+ -- nof dp_phs_clk that can be used to detect the word phase
+ g_nof_dp_phs_clk : natural := 1
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
st_aduh_ab_status : in std_logic_vector(c_word_w - 1 downto 0);
@@ -102,7 +110,8 @@ architecture rtl of aduh_quad_reg is
constant c_nof_dat : natural := 8;
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_nof_dat,
init_sl => '0');
@@ -151,10 +160,14 @@ begin
-- Access event, register values
mm_aduh_ab_stable_ack <= '0';
mm_aduh_cd_stable_ack <= '0';
- mm_aduh_ab_control <= (others => '0'); -- default reset all unused control bits
- mm_aduh_cd_control <= (others => '0'); -- default reset all unused control bits
- mm_aduh_ab_control(g_nof_dp_phs_clk - 1 downto 0) <= (others => '1'); -- default enable all dp_phs_clk for ADU-AB
- mm_aduh_cd_control(g_nof_dp_phs_clk - 1 downto 0) <= (others => '1'); -- default enable all dp_phs_clk for ADU-CD
+ -- default reset all unused control bits
+ mm_aduh_ab_control <= (others => '0');
+ -- default reset all unused control bits
+ mm_aduh_cd_control <= (others => '0');
+ -- default enable all dp_phs_clk for ADU-AB
+ mm_aduh_ab_control(g_nof_dp_phs_clk - 1 downto 0) <= (others => '1');
+ -- default enable all dp_phs_clk for ADU-CD
+ mm_aduh_cd_control(g_nof_dp_phs_clk - 1 downto 0) <= (others => '1');
mm_aduh_a_verify_res_ack <= '0';
mm_aduh_b_verify_res_ack <= '0';
@@ -182,42 +195,53 @@ begin
mm_aduh_ab_control <= sla_in.wrdata(31 downto 0);
when 7 =>
mm_aduh_cd_control <= sla_in.wrdata(31 downto 0);
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read ADUH locked status
when 0 =>
mm_aduh_ab_stable_ack <= '1';
- sla_out.rddata(0) <= mm_aduh_ab_locked; -- ADU AB
+ -- ADU AB
+ sla_out.rddata(0) <= mm_aduh_ab_locked;
sla_out.rddata(1) <= mm_aduh_ab_stable;
- sla_out.rddata(31 downto 2) <= mm_aduh_ab_status(31 downto 2); -- extra status info for debug
+ -- extra status info for debug
+ sla_out.rddata(31 downto 2) <= mm_aduh_ab_status(31 downto 2);
when 1 =>
mm_aduh_cd_stable_ack <= '1';
- sla_out.rddata(0) <= mm_aduh_cd_locked; -- ADU CD
+ -- ADU CD
+ sla_out.rddata(0) <= mm_aduh_cd_locked;
sla_out.rddata(1) <= mm_aduh_cd_stable;
- sla_out.rddata(31 downto 2) <= mm_aduh_cd_status(31 downto 2); -- extra status info for debug
+ -- extra status info for debug
+ sla_out.rddata(31 downto 2) <= mm_aduh_cd_status(31 downto 2);
-- Read ADUH ADC verify test pattern status
when 2 =>
mm_aduh_a_verify_res_ack <= '1';
- sla_out.rddata(8 downto 0) <= mm_aduh_a_verify_res(8 downto 0); -- ADC A
+ -- ADC A
+ sla_out.rddata(8 downto 0) <= mm_aduh_a_verify_res(8 downto 0);
sla_out.rddata(12) <= mm_aduh_a_verify_res_val;
when 3 =>
mm_aduh_b_verify_res_ack <= '1';
- sla_out.rddata(8 downto 0) <= mm_aduh_b_verify_res(8 downto 0); -- ADC B
+ -- ADC B
+ sla_out.rddata(8 downto 0) <= mm_aduh_b_verify_res(8 downto 0);
sla_out.rddata(12) <= mm_aduh_b_verify_res_val;
when 4 =>
mm_aduh_c_verify_res_ack <= '1';
- sla_out.rddata(8 downto 0) <= mm_aduh_c_verify_res(8 downto 0); -- ADC C
+ -- ADC C
+ sla_out.rddata(8 downto 0) <= mm_aduh_c_verify_res(8 downto 0);
sla_out.rddata(12) <= mm_aduh_c_verify_res_val;
when 5 =>
mm_aduh_d_verify_res_ack <= '1';
- sla_out.rddata(8 downto 0) <= mm_aduh_d_verify_res(8 downto 0); -- ADC D
+ -- ADC D
+ sla_out.rddata(8 downto 0) <= mm_aduh_d_verify_res(8 downto 0);
sla_out.rddata(12) <= mm_aduh_d_verify_res_val;
when 6 =>
@@ -226,7 +250,8 @@ begin
when 7 =>
-- Read back dp_phs_clk select control
sla_out.rddata(31 downto 0) <= mm_aduh_cd_control;
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
end if;
end if;
@@ -249,7 +274,8 @@ begin
-- signals if it is necessary (to avoid using more logic than necessary).
------------------------------------------------------------------------------
- no_cross : if g_cross_clock_domain = false generate -- so mm_clk = st_clk
+ -- so mm_clk = st_clk
+ no_cross : if g_cross_clock_domain = false generate
mm_aduh_ab_status <= st_aduh_ab_status;
mm_aduh_ab_locked <= st_aduh_ab_locked;
mm_aduh_ab_stable <= st_aduh_ab_stable;
@@ -277,7 +303,8 @@ begin
mm_aduh_d_verify_res <= st_aduh_d_verify_res;
mm_aduh_d_verify_res_val <= st_aduh_d_verify_res_val;
st_aduh_d_verify_res_ack <= mm_aduh_d_verify_res_ack;
- end generate; -- no_cross
+ -- no_cross
+ end generate;
gen_cross : if g_cross_clock_domain = true generate
-- ADUH extra status registers
@@ -529,6 +556,7 @@ begin
out_clk => st_clk,
out_pulse => st_aduh_d_verify_res_ack
);
- end generate; -- gen_cross
+ -- gen_cross
+ end generate;
end rtl;
diff --git a/libraries/io/aduh/src/vhdl/aduh_quad_scope.vhd b/libraries/io/aduh/src/vhdl/aduh_quad_scope.vhd
index 061f02161ba6b9da748f3f11d2cc292c43925558..98868140c8630c0ac67f20349156f2f6f59a7ed5 100644
--- a/libraries/io/aduh/src/vhdl/aduh_quad_scope.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_quad_scope.vhd
@@ -38,17 +38,21 @@ entity aduh_quad_scope is
g_ai : t_c_aduh_dd_ai := c_aduh_dd_ai
);
port (
- DCLK : in std_logic := '0'; -- digital processing clk
+ -- digital processing clk
+ DCLK : in std_logic := '0';
-- Streaming samples (can be from ADU or from internal WG)
- sp_sosi_arr : in t_dp_sosi_arr(0 to g_ai.nof_sp - 1) -- = [0:3] = Signal Paths [A,B,C,D]
+ -- = [0:3] = Signal Paths [A,B,C,D]
+ sp_sosi_arr : in t_dp_sosi_arr(0 to g_ai.nof_sp - 1)
);
end aduh_quad_scope;
architecture beh of aduh_quad_scope is
- constant c_wideband_factor : natural := g_ai.rx_factor * g_ai.dd_factor; -- Wideband rate factor = 4 for dp_clk is 200 MHz frequency and sample frequency Fs is 800 MHz
+ -- Wideband rate factor = 4 for dp_clk is 200 MHz frequency and sample frequency Fs is 800 MHz
+ constant c_wideband_factor : natural := g_ai.rx_factor * g_ai.dd_factor;
- signal dp_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1); -- = DP [3:0] = ADU Signal Paths [D,C,B,A]
+ -- = DP [3:0] = ADU Signal Paths [D,C,B,A]
+ signal dp_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1);
begin
-- Reverse wire ADUH range [0:3] = A,B,C,D to DP [3:0] range
rewire : for I in 0 to g_ai.nof_sp - 1 generate
@@ -70,6 +74,7 @@ begin
DCLK => DCLK,
-- Streaming samples
- sp_sosi_arr => dp_sosi_arr -- = [3:0] = Signal Paths [D,C,B,A]
+ -- = [3:0] = Signal Paths [D,C,B,A]
+ sp_sosi_arr => dp_sosi_arr
);
end beh;
diff --git a/libraries/io/aduh/src/vhdl/aduh_verify.vhd b/libraries/io/aduh/src/vhdl/aduh_verify.vhd
index b198cf47acfbe6a96e80d3d7cb69166baee1b0db..be16ece986ff97d5870597b004e1dafe7560d69b 100644
--- a/libraries/io/aduh/src/vhdl/aduh_verify.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_verify.vhd
@@ -96,18 +96,22 @@ use dp_lib.dp_stream_pkg.all;
entity aduh_verify is
generic (
- g_symbol_w : natural := 8; -- Fixed
- g_nof_symbols_per_data : natural := 4 -- Fixed, big endian in_sosi.data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ -- Fixed
+ g_symbol_w : natural := 8;
+ -- Fixed, big endian in_sosi.data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data : natural := 4
);
port (
rst : in std_logic;
clk : in std_logic;
-- ST input
- in_sosi : in t_dp_sosi; -- signal path data with 4 800MHz 8b samples in time per one 32b word @ 200MHz
+ -- signal path data with 4 800MHz 8b samples in time per one 32b word @ 200MHz
+ in_sosi : in t_dp_sosi;
-- Static control input (connect via MM or leave open to use default)
- pattern_sel : in natural range 0 to 1 := 0; -- 0 = DI, 1 = DQ
+ -- 0 = DI, 1 = DQ
+ pattern_sel : in natural range 0 to 1 := 0;
verify_res : out std_logic_vector(g_symbol_w downto 0);
verify_res_val : out std_logic;
verify_res_ack : in std_logic
@@ -115,18 +119,22 @@ entity aduh_verify is
end aduh_verify;
architecture rtl of aduh_verify is
- constant c_tp_symbol : t_slv_8_arr(0 to 1) := (X"02", X"01"); -- = (I, Q), use patter_sel to select
+ -- = (I, Q), use patter_sel to select
+ constant c_tp_symbol : t_slv_8_arr(0 to 1) := (X"02", X"01");
- type t_nibble_arr is array (integer range <>) of std_logic_vector(0 to g_nof_symbols_per_data - 1); -- here use index [0:3] for the big endian nibbles
+ -- here use index [0:3] for the big endian nibbles
+ type t_nibble_arr is array (integer range <>) of std_logic_vector(0 to g_nof_symbols_per_data - 1);
signal symbols : t_slv_8_arr(0 to g_nof_symbols_per_data - 1);
- signal symb : std_logic_vector(0 to g_nof_symbols_per_data - 1); -- here use index [0:3] for the big endian nibbles
+ -- here use index [0:3] for the big endian nibbles
+ signal symb : std_logic_vector(0 to g_nof_symbols_per_data - 1);
signal symb_err : std_logic_vector(0 to g_nof_symbols_per_data - 1);
signal bits : t_nibble_arr(g_symbol_w - 1 downto 0);
signal in_val : std_logic;
signal nxt_in_val : std_logic;
- signal in_symb : std_logic_vector(0 to g_nof_symbols_per_data - 1); -- here use index [0:3] for the big endian nibbles
+ -- here use index [0:3] for the big endian nibbles
+ signal in_symb : std_logic_vector(0 to g_nof_symbols_per_data - 1);
signal nxt_in_symb : std_logic_vector(0 to g_nof_symbols_per_data - 1);
signal in_symb_err : std_logic;
signal nxt_in_symb_err : std_logic;
@@ -190,9 +198,11 @@ begin
end process;
nxt_in_val <= in_sosi.valid;
- nxt_in_symb <= symb; -- 1 nibbles stream for the mapped symbols
+ -- 1 nibbles stream for the mapped symbols
+ nxt_in_symb <= symb;
nxt_in_symb_err <= vector_or(symb_err);
- nxt_in_bits <= bits; -- 8 nibbles streams, one per symbol bit
+ -- 8 nibbles streams, one per symbol bit
+ nxt_in_bits <= bits;
------------------------------------------------------------------------------
-- 2) Verify the test pattern for:
diff --git a/libraries/io/aduh/src/vhdl/aduh_verify_bit.vhd b/libraries/io/aduh/src/vhdl/aduh_verify_bit.vhd
index 92b1cb9eca414554815d2ce222bdeb70915ff5cc..28ab3c5a130e42f1b7c9898790b97a01c2b92598 100644
--- a/libraries/io/aduh/src/vhdl/aduh_verify_bit.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_verify_bit.vhd
@@ -31,7 +31,8 @@ use common_lib.common_pkg.all;
entity aduh_verify_bit is
generic (
- g_nof_symbols_per_data : natural := 4 -- Fixed, big endian in_sosi.data, t0 in MSsymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ -- Fixed, big endian in_sosi.data, t0 in MSsymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data : natural := 4
);
port (
rst : in std_logic;
@@ -50,7 +51,8 @@ entity aduh_verify_bit is
end aduh_verify_bit;
architecture rtl of aduh_verify_bit is
- constant c_nof_init : natural := 2; -- need two dat words to initialize the ref_dat
+ -- need two dat words to initialize the ref_dat
+ constant c_nof_init : natural := 2;
type t_state is (s_init, s_verify);
@@ -68,7 +70,8 @@ architecture rtl of aduh_verify_bit is
if unsigned(prev_nibble) = 16#6# and unsigned(nibble) = 16#4# then return TO_UVEC(16#9#, g_nof_symbols_per_data); end if;
if unsigned(prev_nibble) = 16#4# and unsigned(nibble) = 16#9# then return TO_UVEC(16#9#, g_nof_symbols_per_data); end if;
- return TO_UVEC(0, g_nof_symbols_per_data); -- else return invalid value
+ -- else return invalid value
+ return TO_UVEC(0, g_nof_symbols_per_data);
end;
signal ref_dat : std_logic_vector(0 to g_nof_symbols_per_data - 1);
@@ -78,7 +81,8 @@ architecture rtl of aduh_verify_bit is
signal state : t_state;
signal nxt_state : t_state;
- signal init_done : std_logic; -- fits NATURAL RANGE 0 TO c_nof_init-1;
+ -- fits NATURAL RANGE 0 TO c_nof_init-1;
+ signal init_done : std_logic;
signal nxt_init_done : std_logic;
signal i_verify_res : std_logic;
signal nxt_verify_res : std_logic;
@@ -119,19 +123,23 @@ begin
if state = s_init then
if in_val = '1' then
if in_dat_err = '1' then
- nxt_verify_res <= '1'; -- if the first two data word already contain incorrect pattern symbols
+ -- if the first two data word already contain incorrect pattern symbols
+ nxt_verify_res <= '1';
end if;
if init_done = '0' then
nxt_ref_dat <= in_dat;
- nxt_init_done <= '1'; -- init done because c_nof_init-1 = 1 valid in_dat have been received
+ -- init done because c_nof_init-1 = 1 valid in_dat have been received
+ nxt_init_done <= '1';
else
- nxt_prev_ref_dat <= in_dat; -- prepare prev_ref_dat and ref_dat for next in_dat
+ -- prepare prev_ref_dat and ref_dat for next in_dat
+ nxt_prev_ref_dat <= in_dat;
nxt_ref_dat <= func_tp_seq(ref_dat, in_dat);
nxt_verify_res_val <= '1';
nxt_state <= s_verify;
end if;
end if;
- else -- state = s_verify
+ -- state = s_verify
+ else
if verify_res_ack = '1' then
-- prepare for new verification interval
nxt_init_done <= '0';
@@ -141,13 +149,16 @@ begin
else
-- update verify_res during this verification interval
-- . operate independent of in_val='1', because the ADC data is continous
- nxt_prev_ref_dat <= ref_dat; -- prepare prev_ref_dat and prev_ref_dat for next in_dat
+ -- prepare prev_ref_dat and prev_ref_dat for next in_dat
+ nxt_prev_ref_dat <= ref_dat;
nxt_ref_dat <= func_tp_seq(prev_ref_dat, ref_dat);
if in_dat_err = '1' then
- nxt_verify_res <= '1'; -- capture incorrect pattern symbols
+ -- capture incorrect pattern symbols
+ nxt_verify_res <= '1';
end if;
if unsigned(in_dat) /= unsigned(ref_dat) then
- nxt_verify_res <= '1'; -- capture incorrect pattern sequence
+ -- capture incorrect pattern sequence
+ nxt_verify_res <= '1';
end if;
end if;
end if;
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_dd.vhd b/libraries/io/aduh/src/vhdl/lvdsh_dd.vhd
index 5fe812727c8326a2a0463d2438331509d4bd6e66..97ad3fde841d03e0388e923f63bd09171871d56a 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_dd.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_dd.vhd
@@ -64,17 +64,24 @@ use common_lib.common_pkg.all;
entity lvdsh_dd is
generic (
- g_dd_factor : natural := 2; -- = 2, fixed double data rate factor
- g_in_dat_w : natural := 16; -- nof PHY data bits
- g_in_dat_delay_arr : t_natural_arr := array_init(0, 16); -- nof must match g_in_dat_w
+ -- = 2, fixed double data rate factor
+ g_dd_factor : natural := 2;
+ -- nof PHY data bits
+ g_in_dat_w : natural := 16;
+ -- nof must match g_in_dat_w
+ g_in_dat_delay_arr : t_natural_arr := array_init(0, 16);
g_in_clk_delay : natural := 0;
g_in_clk_rst_invert : boolean := false;
g_use_in_delay : boolean := false;
g_rx_big_endian : boolean := false;
- g_rx_factor : natural := 1; -- 1, 2, 4, ... must be a power of 2 because of the mixed width FIFO
- g_rx_fifo_size : natural := 32; -- see common_fifo_dc_lock_control for comment
- g_rx_fifo_fill : natural := 16; -- see common_fifo_dc_lock_control for comment
- g_rx_fifo_margin : natural := 0 -- use 0, 1 independend of g_rx_factor, because the mixed width FIFO (g_rx_factor > 1) goes from narrow wr to wide rx, so +-1 is enough for wide side.
+ -- 1, 2, 4, ... must be a power of 2 because of the mixed width FIFO
+ g_rx_factor : natural := 1;
+ -- see common_fifo_dc_lock_control for comment
+ g_rx_fifo_size : natural := 32;
+ -- see common_fifo_dc_lock_control for comment
+ g_rx_fifo_fill : natural := 16;
+ -- use 0, 1 independend of g_rx_factor, because the mixed width FIFO (g_rx_factor > 1) goes from narrow wr to wide rx, so +-1 is enough for wide side.
+ g_rx_fifo_margin : natural := 0
);
port (
-- PHY input delay config clock
@@ -84,19 +91,25 @@ entity lvdsh_dd is
-- PHY input interface
in_clk : in std_logic;
- in_dat : in std_logic_vector(g_in_dat_w - 1 downto 0); -- sample [t0], [t1], [t2], [t3], [t4], [t5], [t6], [t7], ... --> time
+ -- sample [t0], [t1], [t2], [t3], [t4], [t5], [t6], [t7], ... --> time
+ in_dat : in std_logic_vector(g_in_dat_w - 1 downto 0);
in_clk_rst : out std_logic;
-- DD domain output interface (no FIFO)
out_clk : out std_logic;
- out_dat_hi : out std_logic_vector(g_in_dat_w - 1 downto 0); -- sample [t1], [t3], [t5], [t7], ...
- out_dat_lo : out std_logic_vector(g_in_dat_w - 1 downto 0); -- sample [t0], [t2], [t4], [t6], ...
+ -- sample [t1], [t3], [t5], [t7], ...
+ out_dat_hi : out std_logic_vector(g_in_dat_w - 1 downto 0);
+ -- sample [t0], [t2], [t4], [t6], ...
+ out_dat_lo : out std_logic_vector(g_in_dat_w - 1 downto 0);
-- DD --> Rx domain interface at in_clk rate or g_rx_factor lower rate (via FIFO)
rx_rst : in std_logic := '1';
- rx_clk : in std_logic := '1'; -- default little endian rx_dat output:
- rx_dat : out std_logic_vector(g_rx_factor * g_dd_factor * g_in_dat_w - 1 downto 0); -- . sample [t1, t0], [t3, t2], [t5, t4], [t7, t6], ... when g_rx_factor = 1
- rx_val : out std_logic; -- . sample [t3, t2, t1, t0], [t7, t6, t5, t4], ... when g_rx_factor = 2
+ -- default little endian rx_dat output:
+ rx_clk : in std_logic := '1';
+ -- . sample [t1, t0], [t3, t2], [t5, t4], [t7, t6], ... when g_rx_factor = 1
+ rx_dat : out std_logic_vector(g_rx_factor * g_dd_factor * g_in_dat_w - 1 downto 0);
+ -- . sample [t3, t2, t1, t0], [t7, t6, t5, t4], ... when g_rx_factor = 2
+ rx_val : out std_logic;
-- Rx FIFO control
rx_locked : out std_logic;
@@ -106,14 +119,18 @@ entity lvdsh_dd is
end lvdsh_dd;
architecture str of lvdsh_dd is
- constant c_rx_fifo_lsusedw_w : natural := true_log2(g_rx_factor); -- nof least significant bits of wrusedw that are skipped for rdusedw due to parallelization by g_rx_factor
+ -- nof least significant bits of wrusedw that are skipped for rdusedw due to parallelization by g_rx_factor
+ constant c_rx_fifo_lsusedw_w : natural := true_log2(g_rx_factor);
constant c_rx_fifo_rdusedw_w : natural := ceil_log2(g_rx_fifo_size);
constant c_rx_fifo_wrusedw_w : natural := c_rx_fifo_rdusedw_w + c_rx_fifo_lsusedw_w;
- constant c_in_dly_w : natural := 1 + g_in_dat_w; -- 1 extra for the in_clk
- constant c_in_delay_arr : t_natural_arr(c_in_dly_w - 1 downto 0) := g_in_clk_delay & g_in_dat_delay_arr; -- [16, 15:0]
+ -- 1 extra for the in_clk
+ constant c_in_dly_w : natural := 1 + g_in_dat_w;
+ -- [16, 15:0]
+ constant c_in_delay_arr : t_natural_arr(c_in_dly_w - 1 downto 0) := g_in_clk_delay & g_in_dat_delay_arr;
- constant c_out_dat_w : natural := g_dd_factor * g_in_dat_w; -- hi & lo
+ -- hi & lo
+ constant c_out_dat_w : natural := g_dd_factor * g_in_dat_w;
-- DD clock domain (in_clk = wr_clk = out_clk)
signal in_vec : std_logic_vector(c_in_dly_w - 1 downto 0);
@@ -125,21 +142,31 @@ architecture str of lvdsh_dd is
signal fifo_wr_ful : std_logic;
signal fifo_wr_req : std_logic := '0';
- signal fifo_wr_dat : std_logic_vector(c_out_dat_w - 1 downto 0); -- hi & lo
- signal nxt_fifo_wr_dat : std_logic_vector(c_out_dat_w - 1 downto 0); -- hi & lo
+ -- hi & lo
+ signal fifo_wr_dat : std_logic_vector(c_out_dat_w - 1 downto 0);
+ -- hi & lo
+ signal nxt_fifo_wr_dat : std_logic_vector(c_out_dat_w - 1 downto 0);
-- Cross clock domains from wr_clk to rd_clk
- signal fifo_wrusedw : std_logic_vector(c_rx_fifo_wrusedw_w - 1 downto 0); -- wr_clk domain
- signal fifo_rdusedw : std_logic_vector(c_rx_fifo_rdusedw_w - 1 downto 0); -- wr_clk domain
- signal rx_fifo_rdusedw : std_logic_vector(c_rx_fifo_rdusedw_w - 1 downto 0); -- rd_clk domain
+ -- wr_clk domain
+ signal fifo_wrusedw : std_logic_vector(c_rx_fifo_wrusedw_w - 1 downto 0);
+ -- wr_clk domain
+ signal fifo_rdusedw : std_logic_vector(c_rx_fifo_rdusedw_w - 1 downto 0);
+ -- rd_clk domain
+ signal rx_fifo_rdusedw : std_logic_vector(c_rx_fifo_rdusedw_w - 1 downto 0);
-- Cross clock domains from rd_clk to wr_clk
- signal wr_clk_rst : std_logic_vector(0 downto 0); -- rd_clk domain
- signal rx_clk_rst : std_logic_vector(0 downto 0); -- rd_clk domain
- signal i_in_clk_rst : std_logic_vector(0 downto 0); -- wr_clk domain
-
- signal dc_fifo_rst : std_logic; -- rd_clk domain
- signal wr_fifo_rst : std_logic; -- wr_clk domain
+ -- rd_clk domain
+ signal wr_clk_rst : std_logic_vector(0 downto 0);
+ -- rd_clk domain
+ signal rx_clk_rst : std_logic_vector(0 downto 0);
+ -- wr_clk domain
+ signal i_in_clk_rst : std_logic_vector(0 downto 0);
+
+ -- rd_clk domain
+ signal dc_fifo_rst : std_logic;
+ -- wr_clk domain
+ signal wr_fifo_rst : std_logic;
-- Rx clock domain (rx_clk = rd_clk) for DSP
signal rx_fifo_rd_req : std_logic;
@@ -150,7 +177,8 @@ begin
-----------------------------------------------------------------------------
-- Input delay
- in_vec <= in_clk & in_dat; -- [16, 15:0]
+ -- [16, 15:0]
+ in_vec <= in_clk & in_dat;
gen_in_dly : if g_use_in_delay = true generate
u_buf_in : entity common_lib.common_iobuf_in
@@ -227,9 +255,11 @@ begin
g_out_delay_len => 1
)
port map (
- in_rst => dc_fifo_rst, -- need to apply dc_fifo_rst asynchronously to reset rd_usedw in case of dc lock lost due to stopped wr_clk
+ -- need to apply dc_fifo_rst asynchronously to reset rd_usedw in case of dc lock lost due to stopped wr_clk
+ in_rst => dc_fifo_rst,
in_clk => rx_clk,
- in_dat => '0', -- connecting '0' is equivalent to connecting dc_fifo_rst
+ -- connecting '0' is equivalent to connecting dc_fifo_rst
+ in_dat => '0',
out_clk => wr_clk,
out_cap => wr_fifo_rst
);
@@ -293,8 +323,10 @@ begin
-- Input FIFO dual clock lock control
u_fifo_dc_lock_control : entity common_lib.common_fifo_dc_lock_control
generic map (
- g_hold_wr_clk_rst => 2, -- >= 1, nof cycles to hold the wr_clk_rst
- g_hold_dc_fifo_rst => 31, -- >= 1, nof cycles to hold the dc_fifo_rst, sufficiently long for wr_clk to have restarted after wr_clk_rst release
+ -- >= 1, nof cycles to hold the wr_clk_rst
+ g_hold_wr_clk_rst => 2,
+ -- >= 1, nof cycles to hold the dc_fifo_rst, sufficiently long for wr_clk to have restarted after wr_clk_rst release
+ g_hold_dc_fifo_rst => 31,
g_rd_fill_level => g_rx_fifo_fill,
g_rd_fill_margin => g_rx_fifo_margin
)
@@ -335,7 +367,8 @@ begin
rd_dat => rx_fifo_rd_dat,
rd_req => rx_fifo_rd_req,
rd_emp => OPEN,
- rdusedw => OPEN, -- instead use wrusedw via common_acapture_slv
+ -- instead use wrusedw via common_acapture_slv
+ rdusedw => OPEN,
rd_val => rx_val
);
@@ -346,7 +379,8 @@ begin
gen_lower_rate : if g_rx_factor > 1 generate
u_fifo_n2w : entity common_lib.common_fifo_dc_mixed_widths
generic map (
- g_nof_words => g_rx_fifo_size * g_rx_factor, -- FIFO size in nof wr_dat words
+ -- FIFO size in nof wr_dat words
+ g_nof_words => g_rx_fifo_size * g_rx_factor,
g_wr_dat_w => c_out_dat_w,
g_rd_dat_w => c_out_dat_w * g_rx_factor
)
@@ -361,7 +395,8 @@ begin
rd_dat => rx_fifo_rd_dat,
rd_req => rx_fifo_rd_req,
rd_emp => OPEN,
- rdusedw => OPEN, -- instead use wrusedw via common_acapture_slv
+ -- instead use wrusedw via common_acapture_slv
+ rdusedw => OPEN,
rd_val => rx_val
);
@@ -373,7 +408,8 @@ begin
end generate;
gen_big_endian : if g_rx_big_endian = true generate
- rx_dat <= hton(rx_fifo_rd_dat, g_in_dat_w, g_rx_factor * g_dd_factor); -- rewire
+ -- rewire
+ rx_dat <= hton(rx_fifo_rd_dat, g_in_dat_w, g_rx_factor * g_dd_factor);
end generate;
end str;
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd b/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd
index 66abbf9d9fb7bc899413b3f570e7c29f346ba432..fda3ae0286bb3fba54b93dcbda7f7cfbfceb35b7 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd
@@ -114,28 +114,38 @@ use common_lib.common_pkg.all;
entity lvdsh_dd_phs4 is
generic (
g_sim : boolean := false;
- g_wb_factor : natural := 4; -- fixed wideband factor 4 = c_rx_factor*c_dd_factor
- g_dp_phs_clk_period : natural := 32; -- number of dp_clk periods per dp_phs_clk period, must match g_clk*_divide_by in unb_clk200_pll
- g_nof_dp_phs_clk : natural := 2; -- nof dp_phs_clk that can be used to detect lock
- g_maintain_phs : boolean := true; -- when TRUE maintain the stable lock once it is found, else keep on checking whether the stable lock is still stable
- g_wb_use_rising_edge : boolean := false; -- when TRUE using rising edge of dp_clk domain to capture wb_sync as reference for dp_sync from in_clk domain, else use falling edge
- g_in_dat_w : natural := 8 -- nof PHY data bits
+ -- fixed wideband factor 4 = c_rx_factor*c_dd_factor
+ g_wb_factor : natural := 4;
+ -- number of dp_clk periods per dp_phs_clk period, must match g_clk*_divide_by in unb_clk200_pll
+ g_dp_phs_clk_period : natural := 32;
+ -- nof dp_phs_clk that can be used to detect lock
+ g_nof_dp_phs_clk : natural := 2;
+ -- when TRUE maintain the stable lock once it is found, else keep on checking whether the stable lock is still stable
+ g_maintain_phs : boolean := true;
+ -- when TRUE using rising edge of dp_clk domain to capture wb_sync as reference for dp_sync from in_clk domain, else use falling edge
+ g_wb_use_rising_edge : boolean := false;
+ -- nof PHY data bits
+ g_in_dat_w : natural := 8
);
port (
-- PHY input interface
in_clk : in std_logic := '1';
- in_dat : in std_logic_vector(g_in_dat_w - 1 downto 0); -- input samples [t0], [t1], [t2], [t3], [t4], [t5], [t6], [t7], ... --> time
+ -- input samples [t0], [t1], [t2], [t3], [t4], [t5], [t6], [t7], ... --> time
+ in_dat : in std_logic_vector(g_in_dat_w - 1 downto 0);
-- DD --> Rx domain interface at in_clk rate or g_wb_factor lower rate (via FIFO)
dp_rst : in std_logic := '1';
dp_clk : in std_logic := '1';
dp_phs_clk_vec : in std_logic_vector(g_nof_dp_phs_clk - 1 downto 0);
- dp_phs_clk_en_vec : in std_logic_vector(g_nof_dp_phs_clk - 1 downto 0); -- only the enabled dp_phs_clk will be used
- dp_dat : out std_logic_vector(g_wb_factor * g_in_dat_w - 1 downto 0); -- big endian output samples [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ -- only the enabled dp_phs_clk will be used
+ dp_phs_clk_en_vec : in std_logic_vector(g_nof_dp_phs_clk - 1 downto 0);
+ -- big endian output samples [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ dp_dat : out std_logic_vector(g_wb_factor * g_in_dat_w - 1 downto 0);
dp_val : out std_logic;
-- Rx status monitor
- out_status : out std_logic_vector(c_word_w - 1 downto 0); -- extra status information for debug
+ -- extra status information for debug
+ out_status : out std_logic_vector(c_word_w - 1 downto 0);
out_phs_locked : out std_logic;
out_word_locked : out std_logic;
out_word_stable : out std_logic;
@@ -146,44 +156,65 @@ end lvdsh_dd_phs4;
architecture str of lvdsh_dd_phs4 is
constant c_word_align_en : boolean := true;
- constant c_dd_factor : natural := 2; -- fixed double data rate factor
- constant c_rx_factor : natural := 2; -- fixed for g_wb_factor = c_rx_factor*c_dd_factor = 4
- constant c_dp_phs_align_en : boolean := g_nof_dp_phs_clk > 0; -- if there are no dp_phs_clk then fall back to raw data mode
- constant c_nof_dp_phs_clk : natural := sel_a_b(c_dp_phs_align_en, g_nof_dp_phs_clk, 1); -- map to dummy 1 when g_nof_dp_phs_clk=0 to avoid compile error on NATURAL RANGE 0 TO -1
-
- constant c_in_period_w : natural := 3; -- large enough to account for dd_factor and small to be able to detect short in_clk inactive period
+ -- fixed double data rate factor
+ constant c_dd_factor : natural := 2;
+ -- fixed for g_wb_factor = c_rx_factor*c_dd_factor = 4
+ constant c_rx_factor : natural := 2;
+ -- if there are no dp_phs_clk then fall back to raw data mode
+ constant c_dp_phs_align_en : boolean := g_nof_dp_phs_clk > 0;
+ -- map to dummy 1 when g_nof_dp_phs_clk=0 to avoid compile error on NATURAL RANGE 0 TO -1
+ constant c_nof_dp_phs_clk : natural := sel_a_b(c_dp_phs_align_en, g_nof_dp_phs_clk, 1);
+
+ -- large enough to account for dd_factor and small to be able to detect short in_clk inactive period
+ constant c_in_period_w : natural := 3;
constant c_dp_detect_period : natural := 2**c_in_period_w / c_dd_factor;
- constant c_raw_phs_w : natural := g_wb_factor; -- = 4 * 1b = 4b
+ -- = 4 * 1b = 4b
+ constant c_raw_phs_w : natural := g_wb_factor;
constant c_sync_w : natural := 1;
- constant c_dp_dat_w : natural := g_wb_factor * g_in_dat_w; -- = 4 * 8b = 32b
+ -- = 4 * 8b = 32b
+ constant c_dp_dat_w : natural := g_wb_factor * g_in_dat_w;
constant c_fifo_dat_w : natural := c_raw_phs_w + c_sync_w + c_dp_dat_w;
- constant c_fifo_size : natural := 256; -- 36b * 256 = 1 M9K
+ -- 36b * 256 = 1 M9K
+ constant c_fifo_size : natural := 256;
constant c_fifo_size_w : natural := ceil_log2(c_fifo_size);
- constant c_fifo_wr_pipeline : natural := 1; -- 0 or 1 optionally to pipeline FIFO wr_req to have mor margin with dp_clk edge
+ -- 0 or 1 optionally to pipeline FIFO wr_req to have mor margin with dp_clk edge
+ constant c_fifo_wr_pipeline : natural := 1;
constant c_in_rst_delay_len : natural := 16;
constant c_delay_len : natural := c_meta_delay_len;
constant c_word_req_lat : natural := 4;
constant c_dp_phs_align_restart_w : natural := 5;
- constant c_in_dd_phs_locked_w : natural := sel_a_b(g_sim, 12, 30); -- used to ensure that dd_phs_locked is only declared if dd_phs is detected ok for at least 2**(g_dd_phs_locked_w-1) in_clk cycles
- constant c_dp_dd_phs_timeout_w : natural := c_in_dd_phs_locked_w; -- dd_phs locked timeout in dp_clk domain, so c_dd_factor=2 longer than c_in_dd_phs_locked_w, because c_in_dd_phs_locked_w runs
+ -- used to ensure that dd_phs_locked is only declared if dd_phs is detected ok for at least 2**(g_dd_phs_locked_w-1) in_clk cycles
+ constant c_in_dd_phs_locked_w : natural := sel_a_b(g_sim, 12, 30);
+ -- dd_phs locked timeout in dp_clk domain, so c_dd_factor=2 longer than c_in_dd_phs_locked_w, because c_in_dd_phs_locked_w runs
+ constant c_dp_dd_phs_timeout_w : natural := c_in_dd_phs_locked_w;
-- in the in_clk domain. This is enough to find stable lock if it is possible to have stable lock at the selected dp_phs_clk.
- constant c_wb_sync_period : natural := g_dp_phs_clk_period; -- nof dp_clk cycles for wb_sync period, must be > c_wb_sync_roundtrip
+ -- nof dp_clk cycles for wb_sync period, must be > c_wb_sync_roundtrip
+ constant c_wb_sync_period : natural := g_dp_phs_clk_period;
constant c_wb_cnt_w : natural := ceil_log2(c_wb_sync_period);
- constant c_wb_sync_in_latency : natural := 5; -- estimated nof dp_clk cycles latency of wb_sync transfer from dp_clk to in_clk domain and the latency in lvdsh_dd_phs4_align
- constant c_wb_fifo_fill_latency : natural := 5; -- estimated nof dp_clk cycles latency of fifo_rdusedw - fifo_wrused
- constant c_wb_fifo_fill_level : integer := 12; -- set expected FIFO fill level on read side (mean level +- 1 can occur)
- constant c_wb_sync_roundtrip : natural := c_wb_sync_in_latency + c_wb_fifo_fill_latency + c_wb_fifo_fill_level; -- achieve this nof dp_clk cycles from getting wb_sync back via dp_sync
+ -- estimated nof dp_clk cycles latency of wb_sync transfer from dp_clk to in_clk domain and the latency in lvdsh_dd_phs4_align
+ constant c_wb_sync_in_latency : natural := 5;
+ -- estimated nof dp_clk cycles latency of fifo_rdusedw - fifo_wrused
+ constant c_wb_fifo_fill_latency : natural := 5;
+ -- set expected FIFO fill level on read side (mean level +- 1 can occur)
+ constant c_wb_fifo_fill_level : integer := 12;
+ -- achieve this nof dp_clk cycles from getting wb_sync back via dp_sync
+ constant c_wb_sync_roundtrip : natural := c_wb_sync_in_latency + c_wb_fifo_fill_latency + c_wb_fifo_fill_level;
constant c_wb_sync_roundtrip_margin : natural := 2;
constant c_wb_sync_roundtrip_max : natural := c_wb_sync_roundtrip + c_wb_sync_roundtrip_margin;
constant c_wb_sync_roundtrip_min : natural := c_wb_sync_roundtrip - c_wb_sync_roundtrip_margin;
- constant c_wb_fifo_fill_margin : natural := 2; -- some symmetrical FIFO filled margin >= 0, use 0 in theory, use 1 to allow some timing uncertainty in rdusedw of dual clock FIFO
- constant c_wb_fifo_fill_margin_p : natural := c_wb_fifo_fill_margin; -- some FIFO more filled margin >= 0, use 0 or 1 to allow 8 and 9
- constant c_wb_fifo_fill_margin_n : natural := c_wb_fifo_fill_margin; -- some FIFO less filled margin >= 0, use 1 or 2 to allow 7 and 6
- constant c_wb_fifo_fill_max : natural := c_wb_fifo_fill_level + c_wb_fifo_fill_margin_p; -- maximum FIFO fill level at any time
- constant c_wb_fifo_fill_min : natural := c_wb_fifo_fill_level - c_wb_fifo_fill_margin_n; -- minimum FIFO fill level during lock
+ -- some symmetrical FIFO filled margin >= 0, use 0 in theory, use 1 to allow some timing uncertainty in rdusedw of dual clock FIFO
+ constant c_wb_fifo_fill_margin : natural := 2;
+ -- some FIFO more filled margin >= 0, use 0 or 1 to allow 8 and 9
+ constant c_wb_fifo_fill_margin_p : natural := c_wb_fifo_fill_margin;
+ -- some FIFO less filled margin >= 0, use 1 or 2 to allow 7 and 6
+ constant c_wb_fifo_fill_margin_n : natural := c_wb_fifo_fill_margin;
+ -- maximum FIFO fill level at any time
+ constant c_wb_fifo_fill_max : natural := c_wb_fifo_fill_level + c_wb_fifo_fill_margin_p;
+ -- minimum FIFO fill level during lock
+ constant c_wb_fifo_fill_min : natural := c_wb_fifo_fill_level - c_wb_fifo_fill_margin_n;
-- view debug signals in Wave Window
signal dbg_c_dp_phs_align_en : boolean := c_dp_phs_align_en;
@@ -191,7 +222,8 @@ architecture str of lvdsh_dd_phs4 is
signal dbg_c_wb_sync_in_latency : natural := c_wb_sync_in_latency;
signal dbg_c_wb_fifo_fill_latency : natural := c_wb_fifo_fill_latency;
signal dbg_c_wb_fifo_fill_max : natural := c_wb_fifo_fill_max;
- signal dbg_c_wb_fifo_fill_level : natural := c_wb_fifo_fill_level; -- must be > c_word_req_lat to ensure that fifo_rdusedw > 0
+ -- must be > c_word_req_lat to ensure that fifo_rdusedw > 0
+ signal dbg_c_wb_fifo_fill_level : natural := c_wb_fifo_fill_level;
signal dbg_c_wb_fifo_fill_min : natural := c_wb_fifo_fill_min;
signal dbg_c_wb_sync_roundtrip : natural := c_wb_sync_roundtrip;
signal dbg_c_wb_sync_roundtrip_max: natural := c_wb_sync_roundtrip_max;
@@ -237,10 +269,13 @@ architecture str of lvdsh_dd_phs4 is
signal r_in : t_in_reg;
signal nxt_r_in : t_in_reg;
- signal in_dat_hi : std_logic_vector(g_in_dat_w - 1 downto 0); -- input samples [t1], [t3], [t5], [t7], ... --> time
- signal in_dat_lo : std_logic_vector(g_in_dat_w - 1 downto 0); -- input samples [t0], [t2], [t4], [t6], ... --> time
+ -- input samples [t1], [t3], [t5], [t7], ... --> time
+ signal in_dat_hi : std_logic_vector(g_in_dat_w - 1 downto 0);
+ -- input samples [t0], [t2], [t4], [t6], ... --> time
+ signal in_dat_lo : std_logic_vector(g_in_dat_w - 1 downto 0);
- signal raw_phs : std_logic_vector(g_wb_factor - 1 downto 0); -- measured dd phase before realignment
+ -- measured dd phase before realignment
+ signal raw_phs : std_logic_vector(g_wb_factor - 1 downto 0);
signal dd_phs_locked : std_logic;
signal dd_sync : std_logic_vector(g_wb_factor - 1 downto 0);
signal dd_sync_sl : std_logic;
@@ -260,7 +295,8 @@ architecture str of lvdsh_dd_phs4 is
le_dat : std_logic_vector(c_dp_dat_w - 1 downto 0);
le_val : std_logic;
dp_raw_phs : std_logic_vector(g_wb_factor - 1 downto 0);
- dp_dat : std_logic_vector(g_wb_factor * g_in_dat_w - 1 downto 0); -- big endian output samples [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ -- big endian output samples [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ dp_dat : std_logic_vector(g_wb_factor * g_in_dat_w - 1 downto 0);
dp_val : std_logic;
dp_phs_locked : std_logic;
dp_phs_align_en : std_logic;
@@ -325,7 +361,8 @@ begin
-- The dp_word_lock_failed can still occur, but only if the course check on wb_cnt_roundtrip latency and fifo_rdusedw FIFO fill
-- level fails by more than a +-1 margin.
--dp_phs_align_restart <= dp_phs_timeout OR dp_phs_lock_lost OR r_dp.dp_word_lock_failed; -- a) should be robust enough to never detect loss lock as long as in_clk stays active
- dp_phs_align_restart <= dp_phs_timeout or dp_phs_lock_lost or (r_dp.dp_word_lock_failed and not r_dp.dp_maintain_phs); -- b) even a bit stronger then a)
+ -- b) even a bit stronger then a)
+ dp_phs_align_restart <= dp_phs_timeout or dp_phs_lock_lost or (r_dp.dp_word_lock_failed and not r_dp.dp_maintain_phs);
--dp_phs_align_restart <= (dp_phs_timeout OR dp_phs_lock_lost OR r_dp.dp_word_lock_failed) AND (NOT r_dp.dp_maintain_phs); -- c) is equivalent to b) so should not make a difference
-- Extend dp_phs_align_restart to filter out any subsequent restart triggers
@@ -347,7 +384,8 @@ begin
u_common_evt_0 : entity common_lib.common_evt
generic map (
g_evt_type => "RISING",
- g_out_reg => false -- if TRUE then the output is registered, else it is not
+ -- if TRUE then the output is registered, else it is not
+ g_out_reg => false
)
port map (
rst => dp_rst,
@@ -374,7 +412,8 @@ begin
g_delay_len => c_in_rst_delay_len
)
port map (
- rst => r_dp.dp_in_rst_req, -- asynchronous rst ensures that it will take effect also when in_clk is not running
+ -- asynchronous rst ensures that it will take effect also when in_clk is not running
+ rst => r_dp.dp_in_rst_req,
clk => in_clk,
din => '0',
dout => in_rst
@@ -431,7 +470,8 @@ begin
generic map (
g_rising_edge => g_wb_use_rising_edge,
g_rst_level => '0',
- g_delay_len => c_delay_len -- typically 1 should be sufficient, but more is fine too
+ -- typically 1 should be sufficient, but more is fine too
+ g_delay_len => c_delay_len
)
port map (
rst => dp_rst,
@@ -475,11 +515,14 @@ begin
out_val => dd_val
);
- dd_sync_sl <= andv(dd_sync); -- after sample phase realignment the dd_sync derived from dp_clk_phs in the in_clk domain toggles between 0x0 and 0xF.
+ -- after sample phase realignment the dd_sync derived from dp_clk_phs in the in_clk domain toggles between 0x0 and 0xF.
+ dd_sync_sl <= andv(dd_sync);
nxt_r_in.dd_sync_locked <= '0' when dd_phs_locked = '0' else
- '1' when dd_sync_sl = '1' else r_in.dd_sync_locked; -- dd_phs_locked goes '1' when dd_sync_sl='0', so dd_sync_locked starts after next dd_sync_sl rising event
- end generate; -- gen_dp_phs_align_en_1
+ -- dd_phs_locked goes '1' when dd_sync_sl='0', so dd_sync_locked starts after next dd_sync_sl rising event
+ '1' when dd_sync_sl = '1' else r_in.dd_sync_locked;
+ -- gen_dp_phs_align_en_1
+ end generate;
------------------------------------------------------------------------------
-- Support raw data without realignment
@@ -497,7 +540,8 @@ begin
);
nxt_r_in.dd_in_data <= in_dat_hi & in_dat_lo & r_in.in_dat_hi & r_in.in_dat_lo;
- nxt_r_in.dd_in_val <= not r_in.dd_in_val; -- toggle to implement c_dd_factor=2 divider
+ -- toggle to implement c_dd_factor=2 divider
+ nxt_r_in.dd_in_val <= not r_in.dd_in_val;
------------------------------------------------------------------------------
-- Use a dual clock FIFO to bring the data to the dp_clk domain
@@ -537,14 +581,20 @@ begin
rd_val => fifo_rd_val
);
- nxt_r_dp.le_raw_phs <= fifo_rd_dat(c_raw_phs_w + c_sync_w + c_dp_dat_w - 1 downto c_sync_w + c_dp_dat_w); -- 4b
- nxt_r_dp.le_sync <= fifo_rd_dat( c_dp_dat_w); -- 1b
- nxt_r_dp.le_dat <= fifo_rd_dat( c_dp_dat_w - 1 downto 0); -- 32b
+ -- 4b
+ nxt_r_dp.le_raw_phs <= fifo_rd_dat(c_raw_phs_w + c_sync_w + c_dp_dat_w - 1 downto c_sync_w + c_dp_dat_w);
+ -- 1b
+ nxt_r_dp.le_sync <= fifo_rd_dat( c_dp_dat_w);
+ -- 32b
+ nxt_r_dp.le_dat <= fifo_rd_dat( c_dp_dat_w - 1 downto 0);
nxt_r_dp.le_val <= fifo_rd_val;
- nxt_r_dp.dp_raw_phs <= r_dp.le_raw_phs when r_dp.le_val = '1' else r_dp.dp_raw_phs; -- Keep measured phase in little endian order
- nxt_r_dp.dp_sync_cap <= r_dp.le_sync when r_dp.le_val = '1' else r_dp.dp_sync_cap; -- Hold to avoid false dp_sync_cap due to fifo_rd_req='0'
- nxt_r_dp.dp_dat <= hton(r_dp.le_dat, g_in_dat_w, g_wb_factor) when r_dp.le_val = '1' else r_dp.dp_dat; -- Rewire le_dat data words with [t3, t2, t1, t0] to big endian dp_dat data words with sample order [t0, t1, t2, t3]
+ -- Keep measured phase in little endian order
+ nxt_r_dp.dp_raw_phs <= r_dp.le_raw_phs when r_dp.le_val = '1' else r_dp.dp_raw_phs;
+ -- Hold to avoid false dp_sync_cap due to fifo_rd_req='0'
+ nxt_r_dp.dp_sync_cap <= r_dp.le_sync when r_dp.le_val = '1' else r_dp.dp_sync_cap;
+ -- Rewire le_dat data words with [t3, t2, t1, t0] to big endian dp_dat data words with sample order [t0, t1, t2, t3]
+ nxt_r_dp.dp_dat <= hton(r_dp.le_dat, g_in_dat_w, g_wb_factor) when r_dp.le_val = '1' else r_dp.dp_dat;
nxt_r_dp.dp_val <= r_dp.le_val;
nxt_r_dp.prev_dp_sync_cap <= r_dp.dp_sync_cap;
@@ -553,9 +603,11 @@ begin
dp_dat <= r_dp.dp_dat;
dp_val <= r_dp.dp_val;
- dp_phs_val <= '1' when r_dp.dp_val = '1' or r_dp.dp_word_req_dly(c_word_req_lat - 1) = '0' else '0'; -- Mask the gaps in dp_val due to fifo_rd_req='0'
+ -- Mask the gaps in dp_val due to fifo_rd_req='0'
+ dp_phs_val <= '1' when r_dp.dp_val = '1' or r_dp.dp_word_req_dly(c_word_req_lat - 1) = '0' else '0';
- nxt_r_dp.dp_phs_locked <= dp_phs_val; -- The input phase is locked when the FIFO does not run empty, so the in_clk is running active AND that dd_phs=c_exp_phs.
+ -- The input phase is locked when the FIFO does not run empty, so the in_clk is running active AND that dd_phs=c_exp_phs.
+ nxt_r_dp.dp_phs_locked <= dp_phs_val;
out_phs_locked <= r_dp.dp_phs_locked;
@@ -608,7 +660,8 @@ begin
end if;
end if;
end process;
- end generate; -- gen_dp_phs_align_en_2
+ -- gen_dp_phs_align_en_2
+ end generate;
------------------------------------------------------------------------------
-- DD phase lock timeout
@@ -624,8 +677,10 @@ begin
count => dp_phs_timeout_cnt
);
- dp_phs_timeout_cnt_clr <= dp_in_clk_stopped or r_dp.dp_phs_locked or dp_phs_timeout; -- clear the dp_phs_timeout timer when there is no active in_clk or when the dp_phs is locked
- dp_phs_timeout <= dp_phs_timeout_cnt(dp_phs_timeout_cnt'high); -- dp_phs_timeout pulse also restarts the timer
+ -- clear the dp_phs_timeout timer when there is no active in_clk or when the dp_phs is locked
+ dp_phs_timeout_cnt_clr <= dp_in_clk_stopped or r_dp.dp_phs_locked or dp_phs_timeout;
+ -- dp_phs_timeout pulse also restarts the timer
+ dp_phs_timeout <= dp_phs_timeout_cnt(dp_phs_timeout_cnt'high);
------------------------------------------------------------------------------
-- Determine DP word lock based on the wb_sync - dp_sync roundtrip latency via in_clk domain
@@ -683,23 +738,28 @@ begin
nxt_r_dp.dp_word_locked <= r_dp.dp_word_locked;
if r_dp.dp_word_locked = '0' then
-- Word lock acquisition
- if r_dp.dp_sync = '1' then -- dp_sync implies also that the FIFO is not empty, so no need to check fifo_rd_emp to avoid false dp_phs_val via dp_word_req_dly
+ -- dp_sync implies also that the FIFO is not empty, so no need to check fifo_rd_emp to avoid false dp_phs_val via dp_word_req_dly
+ if r_dp.dp_sync = '1' then
-- Adjust wb_sync - dp_sync roundtrip latency to become c_wb_sync_roundtrip
if unsigned(wb_cnt) < c_wb_sync_roundtrip then
- nxt_r_dp.dp_word_req <= '0'; -- too early dp_sync so slip 1 word
+ -- too early dp_sync so slip 1 word
+ nxt_r_dp.dp_word_req <= '0';
elsif unsigned(wb_cnt) = c_wb_sync_roundtrip then
- nxt_r_dp.dp_word_locked <= '1'; -- declare word locked
+ -- declare word locked
+ nxt_r_dp.dp_word_locked <= '1';
-- Fine check FIFO fill level when lock is declared
if unsigned(fifo_rdusedw) < c_wb_fifo_fill_min then
- nxt_r_dp.dp_word_lock_failed <= '1'; -- unexpected change in FIFO fill level, so recover via in_rst
+ -- unexpected change in FIFO fill level, so recover via in_rst
+ nxt_r_dp.dp_word_lock_failed <= '1';
end if;
end if;
-- Fine check that latency is incrementing properly during word lock acquisition
if unsigned(r_dp.wb_cnt_roundtrip_hold) > 0 then
if unsigned(r_dp.wb_cnt_roundtrip_hold) /= unsigned(r_dp.wb_cnt_roundtrip) - 1 then
- nxt_r_dp.dp_word_lock_failed <= '1'; -- wrong roundtrip latency increment, so recover via in_rst
+ -- wrong roundtrip latency increment, so recover via in_rst
+ nxt_r_dp.dp_word_lock_failed <= '1';
end if;
end if;
end if;
@@ -709,11 +769,13 @@ begin
-- Fine check roundtrip latency during stable word lock
if wb_roundtrip_expected = '0' and r_dp.dp_maintain_phs = '0' then
-- After achieving dp_word_locked, but while dp_maintain_phs is still '0' the wb_cnt_roundtrip must exactly match c_wb_sync_roundtrip.
- nxt_r_dp.dp_word_lock_failed <= '1'; -- word lock lost, so recover via in_rst
+ -- word lock lost, so recover via in_rst
+ nxt_r_dp.dp_word_lock_failed <= '1';
end if;
-- Fine check FIFO fill level during stable word lock
if unsigned(fifo_rdusedw) < c_wb_fifo_fill_min then
- nxt_r_dp.dp_word_lock_failed <= '1'; -- unexpected change in FIFO fill level, so recover via in_rst
+ -- unexpected change in FIFO fill level, so recover via in_rst
+ nxt_r_dp.dp_word_lock_failed <= '1';
end if;
end if;
end if;
@@ -727,11 +789,14 @@ begin
nxt_r_dp.dp_word_locked <= r_dp.dp_word_locked;
if r_dp.dp_word_locked = '0' then
-- Word lock acquisition
- if fifo_rd_emp = '0' then -- no dp_sync in raw mode, so need to use fifo_rd_emp to check that FIFO is not empty to avoid false dp_phs_val due to dp_word_req_dly
+ -- no dp_sync in raw mode, so need to use fifo_rd_emp to check that FIFO is not empty to avoid false dp_phs_val due to dp_word_req_dly
+ if fifo_rd_emp = '0' then
if unsigned(fifo_rdusedw) <= c_wb_fifo_fill_level - c_word_req_lat then
- nxt_r_dp.dp_word_req <= '0'; -- too few words in FIFO so slip 1 word
+ -- too few words in FIFO so slip 1 word
+ nxt_r_dp.dp_word_req <= '0';
elsif unsigned(fifo_rdusedw) >= c_wb_fifo_fill_min then
- nxt_r_dp.dp_word_locked <= '1'; -- declare word locked
+ -- declare word locked
+ nxt_r_dp.dp_word_locked <= '1';
end if;
end if;
else
@@ -739,7 +804,8 @@ begin
-- Fine check FIFO fill level during stable word lock
if unsigned(fifo_rdusedw) < c_wb_fifo_fill_min then
- nxt_r_dp.dp_word_lock_failed <= '1'; -- unexpected change in FIFO fill level, so recover via in_rst
+ -- unexpected change in FIFO fill level, so recover via in_rst
+ nxt_r_dp.dp_word_lock_failed <= '1';
end if;
end if;
end if;
@@ -747,10 +813,12 @@ begin
-- Course check roundtrip latency and FIFO fill level at any time
if unsigned(wb_cnt) > c_wb_sync_roundtrip_max then
- nxt_r_dp.dp_word_lock_failed <= '1'; -- timeout dp_sync, so recover via in_rst
+ -- timeout dp_sync, so recover via in_rst
+ nxt_r_dp.dp_word_lock_failed <= '1';
end if;
if unsigned(fifo_rdusedw) > c_wb_fifo_fill_max then
- nxt_r_dp.dp_word_lock_failed <= '1'; -- unexpected change in FIFO fill level, so recover via in_rst
+ -- unexpected change in FIFO fill level, so recover via in_rst
+ nxt_r_dp.dp_word_lock_failed <= '1';
end if;
end process;
@@ -768,14 +836,22 @@ begin
begin
-- Debug monitor status
i_out_status <= (others => '0');
- i_out_status( 3) <= dp_fifo_fill_stable; -- 1 bit
- i_out_status( 4) <= dp_phs_stable; -- 1 bit
- i_out_status( 5) <= wb_roundtrip_stable; -- 1 bit
- i_out_status( 7 downto 6) <= dp_in_clk_stable & dp_in_clk_detected; -- 2 bit
- i_out_status(15 downto 8) <= fifo_rdusedw; -- c_fifo_size_w = 8
- i_out_status(23 downto 16) <= RESIZE_UVEC(r_dp.wb_cnt_roundtrip, 8); -- c_wb_cnt_w <= 8
- i_out_status(27 downto 24) <= TO_UVEC(r_dp.dp_phs_clk_select, 4); -- g_nof_dp_phs_clk <= 6, fits in 4 bit
- i_out_status(31 downto 28) <= r_dp.dp_raw_phs; -- g_wb_factor = 4
+ -- 1 bit
+ i_out_status( 3) <= dp_fifo_fill_stable;
+ -- 1 bit
+ i_out_status( 4) <= dp_phs_stable;
+ -- 1 bit
+ i_out_status( 5) <= wb_roundtrip_stable;
+ -- 2 bit
+ i_out_status( 7 downto 6) <= dp_in_clk_stable & dp_in_clk_detected;
+ -- c_fifo_size_w = 8
+ i_out_status(15 downto 8) <= fifo_rdusedw;
+ -- c_wb_cnt_w <= 8
+ i_out_status(23 downto 16) <= RESIZE_UVEC(r_dp.wb_cnt_roundtrip, 8);
+ -- g_nof_dp_phs_clk <= 6, fits in 4 bit
+ i_out_status(27 downto 24) <= TO_UVEC(r_dp.dp_phs_clk_select, 4);
+ -- g_wb_factor = 4
+ i_out_status(31 downto 28) <= r_dp.dp_raw_phs;
end process;
out_status <= i_out_status;
@@ -791,7 +867,8 @@ begin
dbg_status_15_8_fifo_rdusedw <= i_out_status(15 downto 8);
dbg_status_23_16_wb_cnt_roundtrip <= i_out_status(23 downto 16);
dbg_status_27_24_dp_phs_clk_select <= i_out_status(27 downto 24);
- dbg_status_31_28_dp_raw_phs <= i_out_status(31 downto 28) when r_dp.dp_val = '1' and r_dp.le_val = '1'; -- latch to view only yhe raw_phs when in lock
+ -- latch to view only yhe raw_phs when in lock
+ dbg_status_31_28_dp_raw_phs <= i_out_status(31 downto 28) when r_dp.dp_val = '1' and r_dp.le_val = '1';
end generate;
------------------------------------------------------------------------------
@@ -804,7 +881,8 @@ begin
clk => dp_clk,
-- MM
r_in => r_dp.dp_word_locked,
- r_stable => i_out_word_stable, -- monitors lvdsh_dd_phs4 overalll data output stable (both phs and word)
+ -- monitors lvdsh_dd_phs4 overalll data output stable (both phs and word)
+ r_stable => i_out_word_stable,
r_stable_ack => out_word_stable_ack
);
@@ -814,7 +892,8 @@ begin
clk => dp_clk,
-- MM
r_in => r_dp.dp_phs_locked,
- r_stable => dp_phs_stable, -- monitors lvdsh_dd_phs4_align data output stable
+ -- monitors lvdsh_dd_phs4_align data output stable
+ r_stable => dp_phs_stable,
r_stable_ack => out_word_stable_ack
);
@@ -824,7 +903,8 @@ begin
clk => dp_clk,
-- MM
r_in => dp_fifo_fill_lock,
- r_stable => dp_fifo_fill_stable, -- monitors FIFO fill level between min and max
+ -- monitors FIFO fill level between min and max
+ r_stable => dp_fifo_fill_stable,
r_stable_ack => out_word_stable_ack
);
@@ -834,7 +914,8 @@ begin
clk => dp_clk,
-- MM
r_in => wb_roundtrip_lock,
- r_stable => wb_roundtrip_stable, -- monitors roundtrip latency of wb_sync --> dp_sync via in_clk domain between +-1
+ -- monitors roundtrip latency of wb_sync --> dp_sync via in_clk domain between +-1
+ r_stable => wb_roundtrip_stable,
r_stable_ack => out_word_stable_ack
);
@@ -885,7 +966,8 @@ begin
r_dp.le_raw_phs <= (others => '0');
r_dp.le_val <= '0';
r_dp.dp_raw_phs <= (others => '0');
- r_dp.dp_dat <= (others => '0'); -- to avoid Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 in simulation
+ -- to avoid Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 in simulation
+ r_dp.dp_dat <= (others => '0');
r_dp.dp_val <= '0';
r_dp.dp_phs_locked <= '0';
r_dp.dp_phs_align_en <= '0';
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4_align.vhd b/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4_align.vhd
index ac360a443eb4f34d7929ed05be2ef3956f1bcbc7..f78ed4f525082985ab15100f6141a20ecdb1466c 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4_align.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4_align.vhd
@@ -40,44 +40,66 @@ use common_lib.common_pkg.all;
entity lvdsh_dd_phs4_align is
generic (
- g_wb_factor : natural := 4; -- fixed wideband factor 4 = c_rx_factor*c_dd_factor
- g_nof_dp_phs_clk : natural := 2; -- nof dp_phs_clk that can be used to detect lock
- g_dp_phs_clk_period : natural := 32; -- number of dp_clk periods per dp_phs_clk period, must match g_clk*_divide_by in unb_clk200_pll
- g_dd_phs_locked_w : natural := 8; -- used to ensure that dd_phs_locked is only declared if dd_phs_detected is stable for at least 2**(g_dd_phs_locked_w-1) cycles
- g_in_dat_w : natural := 8 -- nof PHY data bits
+ -- fixed wideband factor 4 = c_rx_factor*c_dd_factor
+ g_wb_factor : natural := 4;
+ -- nof dp_phs_clk that can be used to detect lock
+ g_nof_dp_phs_clk : natural := 2;
+ -- number of dp_clk periods per dp_phs_clk period, must match g_clk*_divide_by in unb_clk200_pll
+ g_dp_phs_clk_period : natural := 32;
+ -- used to ensure that dd_phs_locked is only declared if dd_phs_detected is stable for at least 2**(g_dd_phs_locked_w-1) cycles
+ g_dd_phs_locked_w : natural := 8;
+ -- nof PHY data bits
+ g_in_dat_w : natural := 8
);
port (
-- DP clock reference for word alignment
- dp_phs_clk_vec : in std_logic_vector(g_nof_dp_phs_clk - 1 downto 0); -- used as data input for in_clk domain
+ -- used as data input for in_clk domain
+ dp_phs_clk_vec : in std_logic_vector(g_nof_dp_phs_clk - 1 downto 0);
dp_phs_clk_select : in natural range 0 to g_nof_dp_phs_clk - 1 := 0;
-- PHY input interface
in_rst : in std_logic := '0';
in_clk : in std_logic := '1';
- in_dat_hi : in std_logic_vector(g_in_dat_w - 1 downto 0); -- input samples [t1], [t3], [t5], [t7], ... --> time
- in_dat_lo : in std_logic_vector(g_in_dat_w - 1 downto 0); -- input samples [t0], [t2], [t4], [t6], ... --> time
+ -- input samples [t1], [t3], [t5], [t7], ... --> time
+ in_dat_hi : in std_logic_vector(g_in_dat_w - 1 downto 0);
+ -- input samples [t0], [t2], [t4], [t6], ... --> time
+ in_dat_lo : in std_logic_vector(g_in_dat_w - 1 downto 0);
in_maintain_phs : in std_logic := '0';
- raw_phs : out std_logic_vector( g_wb_factor - 1 downto 0); -- the measured sample phase before realignment
- out_phs_locked : out std_logic; -- '1' when realigned sample phase is stable and correct for at least 2**(g_dd_phs_locked_w-1) cycles
- out_sync : out std_logic_vector( g_wb_factor - 1 downto 0); -- the measured word phase after realignment
- out_dat : out std_logic_vector(g_in_dat_w * g_wb_factor - 1 downto 0); -- output words in little endian format [t3, t2, t1, t0]
+ -- the measured sample phase before realignment
+ raw_phs : out std_logic_vector( g_wb_factor - 1 downto 0);
+ -- '1' when realigned sample phase is stable and correct for at least 2**(g_dd_phs_locked_w-1) cycles
+ out_phs_locked : out std_logic;
+ -- the measured word phase after realignment
+ out_sync : out std_logic_vector( g_wb_factor - 1 downto 0);
+ -- output words in little endian format [t3, t2, t1, t0]
+ out_dat : out std_logic_vector(g_in_dat_w * g_wb_factor - 1 downto 0);
out_val : out std_logic
);
end lvdsh_dd_phs4_align;
architecture str of lvdsh_dd_phs4_align is
- constant c_ref_pipeline : natural := 1; -- need pipeline to achieve 400 MHz when g_nof_dp_phs_clk=8
- constant c_align_pipeline : natural := 1; -- use pipeline to achieve 400 MHz
- constant c_offset_delay_len : integer := c_ref_pipeline + c_align_pipeline; -- = 1+1
- constant c_delay_len : natural := c_meta_delay_len + c_offset_delay_len; -- = 3 + 1+1
- constant c_dd_factor : natural := 2; -- fixed double data rate factor
- constant c_rx_factor : natural := 2; -- fixed for g_wb_factor = c_rx_factor*c_dd_factor = 4
+ -- need pipeline to achieve 400 MHz when g_nof_dp_phs_clk=8
+ constant c_ref_pipeline : natural := 1;
+ -- use pipeline to achieve 400 MHz
+ constant c_align_pipeline : natural := 1;
+ -- = 1+1
+ constant c_offset_delay_len : integer := c_ref_pipeline + c_align_pipeline;
+ -- = 3 + 1+1
+ constant c_delay_len : natural := c_meta_delay_len + c_offset_delay_len;
+ -- fixed double data rate factor
+ constant c_dd_factor : natural := 2;
+ -- fixed for g_wb_factor = c_rx_factor*c_dd_factor = 4
+ constant c_rx_factor : natural := 2;
constant c_in_phs_clk_period : natural := c_dd_factor * g_dp_phs_clk_period;
- constant c_dd_phs_w : natural := g_wb_factor; -- = 4 * 1b = 4b
- constant c_dd_dat_w : natural := g_wb_factor * g_in_dat_w; -- = 4 * 8b = 32b
- constant c_exp_raw_phs_arr : t_natural_arr(g_wb_factor - 1 downto 0) := (3, 6, 12, 9); -- the expected word phase before realignment is fixed, the other values in the range indicate incorrect phase detection
- constant c_exp_phs : natural := 3; -- the expected word phase after realignment is fixed, the other values in the range indicate incorrect phase detection
+ -- = 4 * 1b = 4b
+ constant c_dd_phs_w : natural := g_wb_factor;
+ -- = 4 * 8b = 32b
+ constant c_dd_dat_w : natural := g_wb_factor * g_in_dat_w;
+ -- the expected word phase before realignment is fixed, the other values in the range indicate incorrect phase detection
+ constant c_exp_raw_phs_arr : t_natural_arr(g_wb_factor - 1 downto 0) := (3, 6, 12, 9);
+ -- the expected word phase after realignment is fixed, the other values in the range indicate incorrect phase detection
+ constant c_exp_phs : natural := 3;
signal ref_r_vec : std_logic_vector(g_nof_dp_phs_clk - 1 downto 0);
signal ref_f_vec : std_logic_vector(g_nof_dp_phs_clk - 1 downto 0);
@@ -155,7 +177,8 @@ begin
g_clk_factor => c_rx_factor
)
port map (
- in_clk => dp_phs_clk_vec(I), -- used as data input for in_clk domain
+ -- used as data input for in_clk domain
+ in_clk => dp_phs_clk_vec(I),
rst => in_rst,
clk => in_clk,
phase => ref_r_vec(I),
@@ -171,7 +194,8 @@ begin
g_clk_factor => c_rx_factor
)
port map (
- in_clk => dp_phs_clk_vec(I), -- used as data input for in_clk domain
+ -- used as data input for in_clk domain
+ in_clk => dp_phs_clk_vec(I),
rst => in_rst,
clk => in_clk,
phase => ref_f_vec(I),
@@ -250,19 +274,24 @@ begin
nxt_r.ref_f <= ref_f;
-- derive toggling phs_r and phs_f in phase with '0' to '1' transition in ref_r and ref_f to support dp_phs_clk that runs some factors 2 slower than dp_clk
- nxt_r.ref_init <= '0' when r.ref_r = '0' and r.ref_f = '0' else r.ref_init; -- wait for dp_phs_clk low after in_rst release
+ -- wait for dp_phs_clk low after in_rst release
+ nxt_r.ref_init <= '0' when r.ref_r = '0' and r.ref_f = '0' else r.ref_init;
- nxt_r.ref_r_val <= '1' when r.ref_init = '0' and ref_r = '1' else r.ref_r_val; -- wait for dp_phs_clk high
- nxt_r.ref_f_val <= '1' when r.ref_init = '0' and ref_f = '1' else r.ref_f_val; -- wait for dp_phs_clk high
+ -- wait for dp_phs_clk high
+ nxt_r.ref_r_val <= '1' when r.ref_init = '0' and ref_r = '1' else r.ref_r_val;
+ -- wait for dp_phs_clk high
+ nxt_r.ref_f_val <= '1' when r.ref_init = '0' and ref_f = '1' else r.ref_f_val;
nxt_r.phs_r <= '0' when r.ref_r_val = '0' or (ref_r = '1' and r.ref_r = '0') else not r.phs_r;
nxt_r.phs_f <= '0' when r.ref_f_val = '0' or (ref_f = '1' and r.ref_f = '0') else not r.phs_f;
-- use ref_r and ref_f via phs to adjust the sample phase within a word of wb_factor samples and via sync to measure the word phase
- sync_r <= r.ref_r; -- use registered r.ref_r and r.ref_f instead of ref_r and ref_f direct to have dd_sync = 0xF instead of 0xC, 0x3
+ -- use registered r.ref_r and r.ref_f instead of ref_r and ref_f direct to have dd_sync = 0xF instead of 0xC, 0x3
+ sync_r <= r.ref_r;
sync_f <= r.ref_f;
- nxt_r.sync_init <= '0' when sync_r = '0' and sync_f = '0' else r.sync_init; -- wait for dp_phs_clk low after in_rst release
+ -- wait for dp_phs_clk low after in_rst release
+ nxt_r.sync_init <= '0' when sync_r = '0' and sync_f = '0' else r.sync_init;
nxt_r.sync_r <= '0' when r.sync_init = '1' else sync_r;
nxt_r.sync_f <= '0' when r.sync_init = '1' else sync_f;
@@ -295,7 +324,8 @@ begin
nxt_r.d_phs <= r.phs_r & r.phs_f when r.phs_r = r.phs_f else r.phs_f & r.prev_phs_r;
nxt_r.d_sync <= r.sync_r & r.sync_f when r.phs_r = r.phs_f else r.sync_f & r.prev_sync_r;
nxt_r.d_dat <= r.in_dat_hi & r.in_dat_lo when r.phs_r = r.phs_f else r.in_dat_lo & r.prev_in_dat_hi;
- nxt_r.d_raw_phs <= r.phs_r & r.phs_f; -- preserve captured d phase for monitoring purposes
+ -- preserve captured d phase for monitoring purposes
+ nxt_r.d_raw_phs <= r.phs_r & r.phs_f;
------------------------------------------------------------------------------
-- Adjust double sample phase offset
@@ -313,7 +343,8 @@ begin
nxt_r.dd_sync <= r.d_sync & r.prev_d_sync when (r.phs_r = '1' and r.phs_f = '1') or (r.phs_r = '0' and r.phs_f = '1') else r.dd_sync;
nxt_r.dd_dat <= r.d_dat & r.prev_d_dat when (r.phs_r = '1' and r.phs_f = '1') or (r.phs_r = '0' and r.phs_f = '1') else r.dd_dat;
nxt_r.dd_val <= '1' when (r.phs_r = '1' and r.phs_f = '1') or (r.phs_r = '0' and r.phs_f = '1') else '0';
- nxt_r.dd_raw_phs <= r.d_raw_phs & r.prev_d_raw_phs; -- preserve captured dd phase for monitoring purposes
+ -- preserve captured dd phase for monitoring purposes
+ nxt_r.dd_raw_phs <= r.d_raw_phs & r.prev_d_raw_phs;
nxt_r.prev_dd_raw_phs <= r.dd_raw_phs;
@@ -341,7 +372,8 @@ begin
generic map (
g_active_level => '1',
g_delayed_w => g_dd_phs_locked_w,
- g_delayed_lo => g_dd_phs_locked_w - 3 -- must be <= g_dd_phs_locked_w-1
+ -- must be <= g_dd_phs_locked_w-1
+ g_delayed_lo => g_dd_phs_locked_w - 3
)
port map (
rst => in_rst,
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd b/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd
index 23773da0a6501691d47ea9729e3fdfc2a58d168b..33614cbcd4344a2111188f16d1b2bbdbd6daf21a 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd
@@ -77,27 +77,34 @@ use common_lib.common_pkg.all;
entity lvdsh_dd_wb4 is
generic (
g_sim : boolean := false;
- g_sim_phase : natural := 0; -- range 0:3 (= g_wb_factor-1)
+ -- range 0:3 (= g_wb_factor-1)
+ g_sim_phase : natural := 0;
g_use_in_clk_rst : boolean := false;
- g_wb_factor : natural := 4; -- fixed wideband factor 4 = c_rx_factor*c_dd_factor
- g_in_dat_w : natural := 8 -- nof PHY data bits
+ -- fixed wideband factor 4 = c_rx_factor*c_dd_factor
+ g_wb_factor : natural := 4;
+ -- nof PHY data bits
+ g_in_dat_w : natural := 8
);
port (
-- PHY input interface
in_clk_rst : out std_logic;
in_clk : in std_logic;
- in_dat : in std_logic_vector(g_in_dat_w - 1 downto 0); -- input samples [t0], [t1], [t2], [t3], [t4], [t5], [t6], [t7], ... --> time
+ -- input samples [t0], [t1], [t2], [t3], [t4], [t5], [t6], [t7], ... --> time
+ in_dat : in std_logic_vector(g_in_dat_w - 1 downto 0);
-- DD --> Rx domain interface at in_clk rate or g_dp_factor lower rate (via FIFO)
dp_rst : in std_logic := '1';
dp_clk : in std_logic := '1';
dp_clkq : in std_logic := '0';
- dp_dat : out std_logic_vector(g_wb_factor * g_in_dat_w - 1 downto 0); -- big endian output samples [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ -- big endian output samples [t0, t1, t2, t3], [t4, t5, t6, t7], ...
+ dp_dat : out std_logic_vector(g_wb_factor * g_in_dat_w - 1 downto 0);
dp_val : out std_logic;
-- Rx status monitor
- dp_sync_phase : out natural range 0 to 2 * g_wb_factor - 1; -- valid dclk phases are 0:3 because g_wb_factor=4, however the detection need twice this range
- dp_status : out std_logic_vector(c_word_w - 1 downto 0); -- extra status information for debug
+ -- valid dclk phases are 0:3 because g_wb_factor=4, however the detection need twice this range
+ dp_sync_phase : out natural range 0 to 2 * g_wb_factor - 1;
+ -- extra status information for debug
+ dp_status : out std_logic_vector(c_word_w - 1 downto 0);
dp_locked : out std_logic;
dp_stable : out std_logic;
dp_stable_ack : in std_logic := '0'
@@ -111,14 +118,22 @@ architecture str of lvdsh_dd_wb4 is
constant c_tsetup_delay_in_hi : boolean := false;
constant c_tsetup_delay_in_lo : boolean := false;
- constant c_dd_factor : natural := 2; -- fixed double data rate factor
- constant c_rx_factor : natural := 2; -- fixed for g_wb_factor = c_rx_factor*c_dd_factor = 4
- constant c_wb_sync_latency : natural := 16; -- nof dp_clk cycles from getting wb_sync back via dp_sync
- constant c_wb_sync_period : natural := 32; -- nof dp_clk cycles for wb_sync period, must be > c_wb_sync_latency
- constant c_wb_sync_timeout : natural := 1024; -- nof dp_clk cycles for wb_sync timeout, must be >>> c_wb_sync_latency
- constant c_dp_fifo_margin : natural := 16; -- rd side, almost full or almost empty margin
- constant c_dp_fifo_size : natural := c_wb_sync_latency + c_dp_fifo_margin; -- rd side
- constant c_in_fifo_size : natural := c_rx_factor * c_dp_fifo_size; -- wr side
+ -- fixed double data rate factor
+ constant c_dd_factor : natural := 2;
+ -- fixed for g_wb_factor = c_rx_factor*c_dd_factor = 4
+ constant c_rx_factor : natural := 2;
+ -- nof dp_clk cycles from getting wb_sync back via dp_sync
+ constant c_wb_sync_latency : natural := 16;
+ -- nof dp_clk cycles for wb_sync period, must be > c_wb_sync_latency
+ constant c_wb_sync_period : natural := 32;
+ -- nof dp_clk cycles for wb_sync timeout, must be >>> c_wb_sync_latency
+ constant c_wb_sync_timeout : natural := 1024;
+ -- rd side, almost full or almost empty margin
+ constant c_dp_fifo_margin : natural := 16;
+ -- rd side
+ constant c_dp_fifo_size : natural := c_wb_sync_latency + c_dp_fifo_margin;
+ -- wr side
+ constant c_in_fifo_size : natural := c_rx_factor * c_dp_fifo_size;
constant c_wb_cnt_w : natural := ceil_log2(c_wb_sync_timeout + 1);
@@ -126,12 +141,14 @@ architecture str of lvdsh_dd_wb4 is
constant c_sync_in_dat_w : natural := c_wb_sync_w + g_in_dat_w;
constant c_in_rst_extend_w : natural := 8;
- constant c_in_rst_delay_len : natural := 4; -- choose even value to fit expected g_sim_phase
+ -- choose even value to fit expected g_sim_phase
+ constant c_in_rst_delay_len : natural := 4;
constant c_fifo_wr_dat_w : natural := c_dd_factor * c_sync_in_dat_w;
constant c_fifo_rd_dat_w : natural := c_rx_factor * c_fifo_wr_dat_w;
- constant c_rx_sync_w : natural := c_rx_factor * c_dd_factor * c_wb_sync_w; -- = 4*1
+ -- = 4*1
+ constant c_rx_sync_w : natural := c_rx_factor * c_dd_factor * c_wb_sync_w;
constant c_rx_dat_w : natural := c_rx_factor * c_dd_factor * g_in_dat_w;
type t_reg is record
@@ -139,8 +156,10 @@ architecture str of lvdsh_dd_wb4 is
status : std_logic_vector(c_word_w - 1 downto 0);
be_sync : std_logic_vector(c_rx_sync_w - 1 downto 0);
be_dat : std_logic_vector(c_rx_dat_w - 1 downto 0);
- sync_phase : natural range 0 to 2 * g_wb_factor - 1; -- valid dclk phases are 0:3 because g_wb_factor=4, however the detection need twice this range
- dat_phase : natural range 0 to g_wb_factor - 1; -- valid dclk phases are 0:3 because g_wb_factor=4
+ -- valid dclk phases are 0:3 because g_wb_factor=4, however the detection need twice this range
+ sync_phase : natural range 0 to 2 * g_wb_factor - 1;
+ -- valid dclk phases are 0:3 because g_wb_factor=4
+ dat_phase : natural range 0 to g_wb_factor - 1;
rx_sync : std_logic_vector(c_rx_sync_w - 1 downto 0);
rx_dat : std_logic_vector(c_rx_dat_w - 1 downto 0);
rx_val : std_logic;
@@ -323,7 +342,8 @@ begin
-- Dual clock FIFO, mixed width
u_common_fifo_dc_mixed_widths : entity common_lib.common_fifo_dc_mixed_widths
generic map (
- g_nof_words => c_in_fifo_size, -- FIFO size in nof wr_dat words
+ -- FIFO size in nof wr_dat words
+ g_nof_words => c_in_fifo_size,
g_wr_dat_w => c_fifo_wr_dat_w,
g_rd_dat_w => c_fifo_rd_dat_w
)
@@ -355,7 +375,8 @@ begin
-- Extract sync and data. The FIFO output is in little endian order, symbol index [3:0] = sample [t3 t2 t1 t0]
gen_le : for I in 0 to g_wb_factor - 1 generate
- le_sync( I ) <= dp_fifo_rd_dat(g_in_dat_w + I * c_sync_in_dat_w) and dp_fifo_rd_val; -- only accept sync when there is valid FIFO read data
+ -- only accept sync when there is valid FIFO read data
+ le_sync( I ) <= dp_fifo_rd_dat(g_in_dat_w + I * c_sync_in_dat_w) and dp_fifo_rd_val;
le_dat((I + 1) * g_in_dat_w - 1 downto I * g_in_dat_w) <= dp_fifo_rd_dat(g_in_dat_w + I * c_sync_in_dat_w - 1 downto I * c_sync_in_dat_w);
end generate;
@@ -377,12 +398,18 @@ begin
-- Set phase based on where the valid be_sync "1111" is detected in two cycles
-- Signal illegal be_sync combinations that can occur if the in_clk and dp_clk edges are too close
nxt_r.sync_phase <= r.sync_phase;
- if r.be_sync = "1111" and be_sync = "0000" then nxt_r.sync_phase <= 0; end if; -- F0
- if r.be_sync = "0111" and be_sync = "1000" then nxt_r.sync_phase <= 1; end if; -- 78
- if r.be_sync = "0011" and be_sync = "1100" then nxt_r.sync_phase <= 2; end if; -- 3C
- if r.be_sync = "0001" and be_sync = "1110" then nxt_r.sync_phase <= 3; end if; -- 1E
- if r.be_sync = "1011" and be_sync = "0100" then nxt_r.sync_phase <= 5; end if; -- B4 = swap hi lo of 78, so map to phase 4+1=5
- if r.be_sync = "0010" and be_sync = "1101" then nxt_r.sync_phase <= 7; end if; -- 2D = swap hi lo of 1E, so map to phase 4+3=7
+ -- F0
+ if r.be_sync = "1111" and be_sync = "0000" then nxt_r.sync_phase <= 0; end if;
+ -- 78
+ if r.be_sync = "0111" and be_sync = "1000" then nxt_r.sync_phase <= 1; end if;
+ -- 3C
+ if r.be_sync = "0011" and be_sync = "1100" then nxt_r.sync_phase <= 2; end if;
+ -- 1E
+ if r.be_sync = "0001" and be_sync = "1110" then nxt_r.sync_phase <= 3; end if;
+ -- B4 = swap hi lo of 78, so map to phase 4+1=5
+ if r.be_sync = "1011" and be_sync = "0100" then nxt_r.sync_phase <= 5; end if;
+ -- 2D = swap hi lo of 1E, so map to phase 4+3=7
+ if r.be_sync = "0010" and be_sync = "1101" then nxt_r.sync_phase <= 7; end if;
-- F0 = swap hi lo of F0, so phase 4 cannot be distinghuised from phase 0
-- 3C = swap hi lo of 3C, so phase 6 cannot be distinghuised from phase 2
-- Map sync_phase 0:3 and 5:7 on dat_phase 0:3
@@ -414,8 +441,10 @@ begin
variable v_rsync : std_logic_vector(c_rx_sync_w - 1 downto 0);
variable v_sync : std_logic_vector(c_rx_sync_w - 1 downto 0);
begin
- v_rsync := r.be_sync(2) & r.be_sync(3) & r.be_sync(0) & r.be_sync(1); -- swap hi lo
- v_sync := be_sync(2) & be_sync(3) & be_sync(0) & be_sync(1); -- swap hi lo
+ -- swap hi lo
+ v_rsync := r.be_sync(2) & r.be_sync(3) & r.be_sync(0) & r.be_sync(1);
+ -- swap hi lo
+ v_sync := be_sync(2) & be_sync(3) & be_sync(0) & be_sync(1);
nxt_r.rx_sync <= (others => '0');
case r.sync_phase is
@@ -423,8 +452,10 @@ begin
when 1 => nxt_r.rx_sync <= r.be_sync(2 downto 0) & be_sync(3);
when 2 => nxt_r.rx_sync <= r.be_sync(1 downto 0) & be_sync(3 downto 2);
when 3 => nxt_r.rx_sync <= r.be_sync(0) & be_sync(3 downto 1);
- when 5 => nxt_r.rx_sync <= v_rsync(2 downto 0) & v_sync(3); -- as phase 1
- when 7 => nxt_r.rx_sync <= v_rsync(0) & v_sync(3 downto 1); -- as phase 3
+ -- as phase 1
+ when 5 => nxt_r.rx_sync <= v_rsync(2 downto 0) & v_sync(3);
+ -- as phase 3
+ when 7 => nxt_r.rx_sync <= v_rsync(0) & v_sync(3 downto 1);
when others => null;
end case;
@@ -468,10 +499,14 @@ begin
u_common_switch_dp_cnt_rst : entity common_lib.common_switch
generic map (
- g_rst_level => '1', -- Defines the output level at reset.
- g_priority_lo => false, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
- g_or_high => false, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
- g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ -- Defines the output level at reset.
+ g_rst_level => '1',
+ -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
+ g_priority_lo => false,
+ -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
+ g_or_high => false,
+ -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ g_and_low => false
)
port map (
rst => dp_rst,
@@ -483,10 +518,14 @@ begin
u_common_switch_dp_cnt_clr : entity common_lib.common_switch
generic map (
- g_rst_level => '1', -- Defines the output level at reset.
- g_priority_lo => true, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
- g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
- g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ -- Defines the output level at reset.
+ g_rst_level => '1',
+ -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
+ g_priority_lo => true,
+ -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
+ g_or_high => true,
+ -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ g_and_low => false
)
port map (
rst => dp_rst,
@@ -517,7 +556,8 @@ begin
nxt_r.lock_state <= 3;
else
-- too late r.dp_sync
- nxt_r.dp_in_rst_req <= '1'; -- recover by resetting the input
+ -- recover by resetting the input
+ nxt_r.dp_in_rst_req <= '1';
nxt_r.lock_state <= 4;
end if;
end if;
@@ -528,16 +568,20 @@ begin
if r.dp_sync = '1' then
if unsigned(wb_cnt) /= c_wb_sync_latency then
-- unexpected r.dp_sync
- nxt_r.dp_in_rst_req <= '1'; -- recover by resetting the input,
- nxt_r.dp_locked <= '0'; -- and finding lock again
+ -- recover by resetting the input,
+ nxt_r.dp_in_rst_req <= '1';
+ -- and finding lock again
+ nxt_r.dp_locked <= '0';
nxt_r.lock_state <= 5;
end if;
end if;
end if;
else
-- Timeout r.dp_sync
- nxt_r.dp_in_rst_req <= '1'; -- recover by resetting the input,
- nxt_r.dp_locked <= '0'; -- and finding lock again
+ -- recover by resetting the input,
+ nxt_r.dp_in_rst_req <= '1';
+ -- and finding lock again
+ nxt_r.dp_locked <= '0';
nxt_r.lock_state <= 6;
end if;
end process;
@@ -548,7 +592,8 @@ begin
g_meta_delay_len => c_meta_delay_len
)
port map (
- in_clk => in_clk, -- used as data input for dp_clk
+ -- used as data input for dp_clk
+ in_clk => in_clk,
rst => dp_rst,
clk => dp_clk,
--clk => dp_clkq,
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_pll.vhd b/libraries/io/aduh/src/vhdl/lvdsh_pll.vhd
index c4d13dbe00914037cbe5a6482969102c55a49d9d..1a21f98d182233fd13bd6e3441c754340f0e49e7 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_pll.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_pll.vhd
@@ -70,10 +70,14 @@ use dp_lib.dp_stream_pkg.all;
entity lvdsh_pll is
generic (
- g_lvds_w : natural := 16; -- bits
- g_lvds_data_rate : natural := 800; -- Msps
- g_lvds_clk_freq : natural := 400; -- MHz
- g_lvds_clk_phase : natural := 0; -- degrees, only for no DPA
+ -- bits
+ g_lvds_w : natural := 16;
+ -- Msps
+ g_lvds_data_rate : natural := 800;
+ -- MHz
+ g_lvds_clk_freq : natural := 400;
+ -- degrees, only for no DPA
+ g_lvds_clk_phase : natural := 0;
g_use_lvds_clk_rst : boolean := false;
g_deser_factor : natural := 4;
g_use_dpa : boolean := true;
@@ -81,16 +85,20 @@ entity lvdsh_pll is
);
port (
-- PHY LVDS Interface
- lvds_clk_rst : out std_logic; -- release synchronises lvds_clk phase
+ -- release synchronises lvds_clk phase
+ lvds_clk_rst : out std_logic;
lvds_clk : in std_logic;
lvds_dat : in std_logic_vector(g_lvds_w - 1 downto 0);
-- DP Streaming Interface
- dp_clk : in std_logic; -- dp_clk frequency is g_lvds_data_rate / g_deser_factor
+ -- dp_clk frequency is g_lvds_data_rate / g_deser_factor
+ dp_clk : in std_logic;
-- . Control
- dp_lvds_reset : in std_logic := '0'; -- LVDS interface reset, necessary if the lvds_clk was not present at power up or if it was temporarily removed
- dp_delay_settings : in t_natural_arr(g_lvds_w - 1 downto 0) := array_init(0, g_lvds_w); -- only used for non DPA mode
+ -- LVDS interface reset, necessary if the lvds_clk was not present at power up or if it was temporarily removed
+ dp_lvds_reset : in std_logic := '0';
+ -- only used for non DPA mode
+ dp_delay_settings : in t_natural_arr(g_lvds_w - 1 downto 0) := array_init(0, g_lvds_w);
dp_cda_settings : in t_natural_arr(g_lvds_w - 1 downto 0) := array_init(0, g_lvds_w);
-- . Streaming
@@ -108,7 +116,8 @@ architecture rtl of lvdsh_pll is
-- probably reclocks the CDA reset to the rx_clk domain.
constant c_use_dp_clk_for_cda_reset : boolean := true;
- constant c_wait_cnt_w : natural := 5; -- >=1, use wider, e.g. 5, to be able to recognize the rx_dat result during each CDA control step in simulation
+ -- >=1, use wider, e.g. 5, to be able to recognize the rx_dat result during each CDA control step in simulation
+ constant c_wait_cnt_w : natural := 5;
constant c_rx_dat_w : natural := g_deser_factor * g_lvds_w;
@@ -117,21 +126,26 @@ architecture rtl of lvdsh_pll is
-- PLL control
signal dp_lvds_reset_release : std_logic;
signal dp_pll_reset : std_logic;
- signal pll_locked : std_logic; -- LVDS_RX PLL locked (called rx_locked, but simulation shows it is asynchronous to rx_clk)
+ -- LVDS_RX PLL locked (called rx_locked, but simulation shows it is asynchronous to rx_clk)
+ signal pll_locked : std_logic;
signal rx_pll_locked : std_logic;
-- DPA control
signal rx_cda_settings : t_natural_arr(g_lvds_w - 1 downto 0) := array_init(0, g_lvds_w);
- signal rx_dpa_reset : std_logic; -- LVDS DPA reset (called rx_reset)
+ -- LVDS DPA reset (called rx_reset)
+ signal rx_dpa_reset : std_logic;
signal rx_dpa_reset_slv : std_logic_vector(g_lvds_w - 1 downto 0);
- signal rx_dpa_locked_slv : std_logic_vector(g_lvds_w - 1 downto 0); -- LVDS DPA locked
+ -- LVDS DPA locked
+ signal rx_dpa_locked_slv : std_logic_vector(g_lvds_w - 1 downto 0);
signal rx_dpa_locked : std_logic;
signal rx_fifo_reset : std_logic;
signal rx_fifo_reset_slv : std_logic_vector(g_lvds_w - 1 downto 0);
-- Deserialized data
- signal rx_clk : std_logic; -- same frequency as dp_clk, but with unknown phase offset
- signal rx_eye_locked : std_logic; -- sampling occurs in the eye
+ -- same frequency as dp_clk, but with unknown phase offset
+ signal rx_clk : std_logic;
+ -- sampling occurs in the eye
+ signal rx_eye_locked : std_logic;
signal nxt_rx_eye_locked : std_logic;
-- Channel Data Alignment
@@ -193,7 +207,8 @@ begin
g_rst_level => '0',
g_p_in_level => '1',
g_ep_out_level => '1',
- g_extend_w => 1 -- ep_out will be active for 2**1 = 2 dp_clk cyles
+ -- ep_out will be active for 2**1 = 2 dp_clk cyles
+ g_extend_w => 1
)
port map (
clk => dp_clk,
@@ -208,7 +223,8 @@ begin
g_rst_level => '1',
g_p_in_level => '1',
g_ep_out_level => '1',
- g_extend_w => 4 -- ep_out will be active for 2**4 = 16 dp_clk cyles
+ -- ep_out will be active for 2**4 = 16 dp_clk cyles
+ g_extend_w => 4
)
port map (
clk => dp_clk,
@@ -231,9 +247,12 @@ begin
g_deser_factor => g_deser_factor
)
port map (
- pll_areset => dp_pll_reset, -- asynchronous, minimum pulse width is 10 ns
- rx_cda_reset => cda_reset_slv, -- asynchronous, minimum pulse width is 1 rx_outclock cycle
- rx_channel_data_align => rx_cda_ctrl, -- the data slips one bit for every pulse, minimum pulse width is 1 rx_outclock cycle
+ -- asynchronous, minimum pulse width is 10 ns
+ pll_areset => dp_pll_reset,
+ -- asynchronous, minimum pulse width is 1 rx_outclock cycle
+ rx_cda_reset => cda_reset_slv,
+ -- the data slips one bit for every pulse, minimum pulse width is 1 rx_outclock cycle
+ rx_channel_data_align => rx_cda_ctrl,
rx_in => lvds_dat,
rx_inclock => lvds_clk,
rx_locked => pll_locked,
@@ -242,7 +261,8 @@ begin
);
nxt_rx_eye_locked <= rx_pll_locked;
- end generate; -- no_dpa
+ -- no_dpa
+ end generate;
---------------------------------------------------------------------------
-- Input use DPA
@@ -257,13 +277,18 @@ begin
g_deser_factor => g_deser_factor
)
port map (
- pll_areset => dp_pll_reset, -- asynchronous, minimum pulse width is 10 ns
- rx_cda_reset => cda_reset_slv, -- asynchronous, minimum pulse width is 1 rx_outclock cycle
- rx_channel_data_align => rx_cda_ctrl, -- the data slips one bit for every pulse, minimum pulse width is 1 rx_outclock cycle
- rx_fifo_reset => rx_fifo_reset_slv, -- asynchronous, minimum pulse width is 1 rx_outclock cycle
+ -- asynchronous, minimum pulse width is 10 ns
+ pll_areset => dp_pll_reset,
+ -- asynchronous, minimum pulse width is 1 rx_outclock cycle
+ rx_cda_reset => cda_reset_slv,
+ -- the data slips one bit for every pulse, minimum pulse width is 1 rx_outclock cycle
+ rx_channel_data_align => rx_cda_ctrl,
+ -- asynchronous, minimum pulse width is 1 rx_outclock cycle
+ rx_fifo_reset => rx_fifo_reset_slv,
rx_in => lvds_dat,
rx_inclock => lvds_clk,
- rx_reset => rx_dpa_reset_slv, -- asynchronous, minimum pulse width is 1 rx_outclock cycle
+ -- asynchronous, minimum pulse width is 1 rx_outclock cycle
+ rx_reset => rx_dpa_reset_slv,
rx_dpa_locked => rx_dpa_locked_slv,
rx_locked => pll_locked,
rx_out => rx_dat,
@@ -275,7 +300,8 @@ begin
if dp_pll_reset = '1' then
rx_dpa_reset <= '1';
elsif rising_edge(rx_clk) then
- rx_dpa_reset <= not rx_pll_locked; -- release the DPA reset after the PLL has locked
+ -- release the DPA reset after the PLL has locked
+ rx_dpa_reset <= not rx_pll_locked;
end if;
end process;
@@ -294,11 +320,13 @@ begin
rst => dp_pll_reset,
clk => rx_clk,
in_sig => rx_eye_locked,
- out_evt => rx_fifo_reset -- reset the DPA FIFO after the DPA got locked
+ -- reset the DPA FIFO after the DPA got locked
+ out_evt => rx_fifo_reset
);
rx_fifo_reset_slv <= (others => rx_fifo_reset);
- end generate; -- gen_dpa
+ -- gen_dpa
+ end generate;
p_rx_dpa_reg : process(dp_pll_reset, rx_clk)
begin
@@ -322,7 +350,8 @@ begin
if dp_pll_reset = '1' then
rx_cda_reset <= '1';
elsif rising_edge(rx_clk) then
- rx_cda_reset <= not rx_eye_locked; -- release the CDA reset when the LVDS data is sampled in the eye
+ -- release the CDA reset when the LVDS data is sampled in the eye
+ rx_cda_reset <= not rx_eye_locked;
end if;
end process;
@@ -332,10 +361,12 @@ begin
g_rst_level => '1'
)
port map (
- rst => rx_cda_reset, -- use rx_cda_reset in rx_clk domain
+ -- use rx_cda_reset in rx_clk domain
+ rst => rx_cda_reset,
clk => dp_clk,
din => '0',
- dout => dp_cda_reset -- use dp_cda_reset in dp_clk domain
+ -- use dp_cda_reset in dp_clk domain
+ dout => dp_cda_reset
);
-- release the CDA reset when the LVDS data is sampled in the eye
@@ -353,7 +384,8 @@ begin
rx_val <= '0';
elsif rising_edge(rx_clk) then
rx_cda_state <= nxt_rx_cda_state;
- rx_cda_ctrl <= nxt_rx_cda_ctrl; -- apply the preset nof bit slip pulses
+ -- apply the preset nof bit slip pulses
+ rx_cda_ctrl <= nxt_rx_cda_ctrl;
rx_cda_cnt <= nxt_rx_cda_cnt;
rx_wait_cnt <= nxt_rx_wait_cnt;
rx_val <= nxt_rx_val;
@@ -371,7 +403,8 @@ begin
-- Immediately after rx_cda_reset release apply the preset number of CDA bit
-- slip pulses for each LVDS data line as set by the dp_cda_settings.
- rx_cda_settings <= dp_cda_settings; -- the dp_cda_settings are stable, so no need to use register stages to synchronise them into the rx_clk domain
+ -- the dp_cda_settings are stable, so no need to use register stages to synchronise them into the rx_clk domain
+ rx_cda_settings <= dp_cda_settings;
nxt_rx_cda_cnt <= rx_cda_cnt + 1 when rx_cda_cnt_en = '1' else rx_cda_cnt;
nxt_rx_wait_cnt <= (others => '0') when rx_wait_cnt_clr = '1' else INCR_UVEC(rx_wait_cnt, 1);
@@ -406,7 +439,8 @@ begin
if rx_wait_cnt(rx_wait_cnt'high) = '1' then
nxt_rx_cda_state <= s_cda_ctrl;
end if;
- when others => -- = s_cda_done
+ -- = s_cda_done
+ when others =>
nxt_rx_val <= '1';
end case;
end process;
diff --git a/libraries/io/aduh/src/vhdl/mms_aduh_monitor.vhd b/libraries/io/aduh/src/vhdl/mms_aduh_monitor.vhd
index 7596ed7d3f238130bb4313f31be3c65f0afd51c1..3873e57929bce23fed657e50d2fb1212cffdbbf8 100644
--- a/libraries/io/aduh/src/vhdl/mms_aduh_monitor.vhd
+++ b/libraries/io/aduh/src/vhdl/mms_aduh_monitor.vhd
@@ -35,36 +35,46 @@ use dp_lib.dp_stream_pkg.all;
entity mms_aduh_monitor is
generic (
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
g_symbol_w : natural := 8;
- g_nof_symbols_per_data : natural := 4; -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
- g_nof_accumulations : natural := 800 * 10**6; -- integration time in symbols, defines internal accumulator widths
+ -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data : natural := 4;
+ -- integration time in symbols, defines internal accumulator widths
+ g_nof_accumulations : natural := 800 * 10**6;
g_buffer_nof_symbols : natural := 1024;
- g_buffer_use_sync : boolean := false -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+ -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+ g_buffer_use_sync : boolean := false
);
port (
-- Memory-mapped clock domain
mm_rst : in std_logic;
mm_clk : in std_logic;
- reg_mosi : in t_mem_mosi; -- read only access to the mean_sum and power_sum
+ -- read only access to the mean_sum and power_sum
+ reg_mosi : in t_mem_mosi;
reg_miso : out t_mem_miso;
- buf_mosi : in t_mem_mosi; -- read and overwrite access to the data buffer
+ -- read and overwrite access to the data buffer
+ buf_mosi : in t_mem_mosi;
buf_miso : out t_mem_miso;
-- Streaming clock domain
st_rst : in std_logic;
st_clk : in std_logic;
- in_sosi : in t_dp_sosi -- Signal path with data g_nof_symbols_per_data=4 8bit samples in time per one 32bit word
+ -- Signal path with data g_nof_symbols_per_data=4 8bit samples in time per one 32bit word
+ in_sosi : in t_dp_sosi
);
end mms_aduh_monitor;
architecture str of mms_aduh_monitor is
-- Monitor outputs
- signal mon_mean_sum : std_logic_vector(c_longword_w - 1 downto 0); -- use fixed 64 bit sum width
- signal mon_power_sum : std_logic_vector(c_longword_w - 1 downto 0); -- use fixed 64 bit sum width
- signal mon_sync : std_logic; -- at the mon_sync there are new mean_sum and pwr_sum statistics available
+ -- use fixed 64 bit sum width
+ signal mon_mean_sum : std_logic_vector(c_longword_w - 1 downto 0);
+ -- use fixed 64 bit sum width
+ signal mon_power_sum : std_logic_vector(c_longword_w - 1 downto 0);
+ -- at the mon_sync there are new mean_sum and pwr_sum statistics available
+ signal mon_sync : std_logic;
begin
u_mm_reg : entity work.aduh_monitor_reg
generic map (
diff --git a/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd b/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd
index e3407f76de1905261e1e7ba7c5529cf9cdceb7ec..7ba1c648560780aa5846794c438336f60f253b58 100644
--- a/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd
+++ b/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd
@@ -32,22 +32,28 @@ use dp_lib.dp_stream_pkg.all;
entity mms_aduh_monitor_arr is
generic (
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
g_nof_streams : positive := 1;
g_symbol_w : natural := 8;
- g_nof_symbols_per_data : natural := 4; -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
- g_nof_accumulations : natural := 800 * 10**6; -- integration time in symbols, defines internal accumulator widths
+ -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data : natural := 4;
+ -- integration time in symbols, defines internal accumulator widths
+ g_nof_accumulations : natural := 800 * 10**6;
g_buffer_nof_symbols : natural := 1024;
- g_buffer_use_sync : boolean := false -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+ -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+ g_buffer_use_sync : boolean := false
);
port (
-- Memory-mapped clock domain
mm_rst : in std_logic;
mm_clk : in std_logic;
- reg_mosi : in t_mem_mosi; -- read only access to the mean_sum and power_sum
+ -- read only access to the mean_sum and power_sum
+ reg_mosi : in t_mem_mosi;
reg_miso : out t_mem_miso;
- buf_mosi : in t_mem_mosi; -- read and overwrite access to the data buffer
+ -- read and overwrite access to the data buffer
+ buf_mosi : in t_mem_mosi;
buf_miso : out t_mem_miso;
-- Streaming clock domain
diff --git a/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd b/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd
index fa266c8ac29c8aaf567413f4060699f6eb5af014..6b6a87de7e78c1001ecc7629cd5a838152b3a33c 100644
--- a/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd
+++ b/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd
@@ -33,9 +33,11 @@ entity mms_aduh_quad is
generic (
-- General
g_sim : boolean := false;
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
-- ADC Interface
- g_nof_dp_phs_clk : natural := 1; -- nof dp_phs_clk that can be used to detect the word phase
+ -- nof dp_phs_clk that can be used to detect the word phase
+ g_nof_dp_phs_clk : natural := 1;
g_ai : t_c_aduh_dd_ai := c_aduh_dd_ai
);
port (
@@ -65,7 +67,8 @@ entity mms_aduh_quad is
dp_phs_clk_vec : in std_logic_vector(g_nof_dp_phs_clk - 1 downto 0);
-- . data
- aduh_sosi_arr : out t_dp_sosi_arr(0 to g_ai.nof_sp - 1) -- = [0:3] = ADC_BI ports [A,B,C,D]
+ -- = [0:3] = ADC_BI ports [A,B,C,D]
+ aduh_sosi_arr : out t_dp_sosi_arr(0 to g_ai.nof_sp - 1)
);
end mms_aduh_quad;
@@ -82,7 +85,8 @@ architecture str of mms_aduh_quad is
signal aduh_cd_stable_ack : std_logic;
signal aduh_cd_control : std_logic_vector(c_word_w - 1 downto 0);
- signal aduh_verify_res : t_slv_32_arr(0 to g_ai.nof_sp - 1); -- [8,7:0]
+ -- [8,7:0]
+ signal aduh_verify_res : t_slv_32_arr(0 to g_ai.nof_sp - 1);
signal aduh_verify_res_val : std_logic_vector(0 to g_ai.nof_sp - 1);
signal aduh_verify_res_ack : std_logic_vector(0 to g_ai.nof_sp - 1);
begin
diff --git a/libraries/io/aduh/tb/vhdl/adc08d1020.vhd b/libraries/io/aduh/tb/vhdl/adc08d1020.vhd
index 0aa985cab26f1f293e946da78a0637df7c68268b..13faf311a5606ead7271cf2e70822f624c289457 100644
--- a/libraries/io/aduh/tb/vhdl/adc08d1020.vhd
+++ b/libraries/io/aduh/tb/vhdl/adc08d1020.vhd
@@ -35,8 +35,10 @@ use common_lib.common_pkg.all;
entity adc08d1020 is
generic (
- g_clk_period : time := 1250 ps; -- Sample clock period of CLK
- g_dclk_init_phase : natural := 0 -- When 0 then use default phase for DCLK, else use the other DDR phase
+ -- Sample clock period of CLK
+ g_clk_period : time := 1250 ps;
+ -- When 0 then use default phase for DCLK, else use the other DDR phase
+ g_dclk_init_phase : natural := 0
);
port (
AI : in integer := 0;
@@ -50,22 +52,29 @@ entity adc08d1020 is
OVR : out std_logic;
test_pattern_en : in std_logic := '0';
- lvds_skew_di : in t_natural_arr(7 downto 0) := (others => 0); -- ps unit
- lvds_skew_dq : in t_natural_arr(7 downto 0) := (others => 0); -- ps unit
- lvds_skew_ovr : in natural := 0; -- ps unit
- lvds_skew_dclk : in natural := 0 -- ps unit
+ -- ps unit
+ lvds_skew_di : in t_natural_arr(7 downto 0) := (others => 0);
+ -- ps unit
+ lvds_skew_dq : in t_natural_arr(7 downto 0) := (others => 0);
+ -- ps unit
+ lvds_skew_ovr : in natural := 0;
+ -- ps unit
+ lvds_skew_dclk : in natural := 0
);
end adc08d1020;
architecture beh of adc08d1020 is
- constant c_nof_adc : natural := 2; -- for AI and AQ
+ -- for AI and AQ
+ constant c_nof_adc : natural := 2;
type t_adc_dat_arr is array (integer range <>) of std_logic_vector(7 downto 0);
- signal adc_dat : t_adc_dat_arr(0 to c_nof_adc - 1); -- [0] = AI, [1] = AQ
+ -- [0] = AI, [1] = AQ
+ signal adc_dat : t_adc_dat_arr(0 to c_nof_adc - 1);
signal adc_ovr : std_logic;
- signal tp_cnt : natural := 0; -- test pattern sequence index counter
+ -- test pattern sequence index counter
+ signal tp_cnt : natural := 0;
signal dclk_dis : std_logic := '0';
signal ddr_clk : std_logic := sel_a_b(g_dclk_init_phase, '1', '0');
@@ -111,7 +120,8 @@ begin
v_cnt := 0;
elsif rising_edge(CLK) then
dclk_dis <= '0';
- if v_cnt < 8 then -- latency 3 or 4 CLK cycles and 4 ns propagation delay, so in total about 8 CLK cycles
+ -- latency 3 or 4 CLK cycles and 4 ns propagation delay, so in total about 8 CLK cycles
+ if v_cnt < 8 then
dclk_dis <= '1';
v_cnt := v_cnt + 1;
end if;
diff --git a/libraries/io/aduh/tb/vhdl/adu_half.vhd b/libraries/io/aduh/tb/vhdl/adu_half.vhd
index a63ad7e17f9d25078972eedb83daf8cc44f86e97..2bda830051eb753798d7757099371b9713a3c2a4 100644
--- a/libraries/io/aduh/tb/vhdl/adu_half.vhd
+++ b/libraries/io/aduh/tb/vhdl/adu_half.vhd
@@ -36,7 +36,8 @@ use i2c_lib.i2c_dev_adu_pkg.all;
entity adu_half is
generic (
- g_dclk_init_phase : natural := 0 -- When 0 then use default phase for DCLK, else use the other DDR phase
+ -- When 0 then use default phase for DCLK, else use the other DDR phase
+ g_dclk_init_phase : natural := 0
);
port (
AI : in integer := 0;
@@ -44,7 +45,8 @@ entity adu_half is
AOVR : in std_logic := '0';
CLK : in std_logic := '0';
DCLK : out std_logic;
- DCLK_RST : in std_logic := '1'; -- inverted
+ -- inverted
+ DCLK_RST : in std_logic := '1';
DI : out std_logic_vector(7 downto 0);
DQ : out std_logic_vector(7 downto 0);
OVR : out std_logic;
@@ -52,20 +54,27 @@ entity adu_half is
SDA : inout std_logic;
test_pattern_en : in std_logic := '0';
- lvds_skew_di : in t_natural_arr(7 downto 0) := (others => 0); -- ps unit
- lvds_skew_dq : in t_natural_arr(7 downto 0) := (others => 0); -- ps unit
- lvds_skew_ovr : in natural := 0; -- ps unit
- lvds_skew_dclk : in natural := 0 -- ps unit
+ -- ps unit
+ lvds_skew_di : in t_natural_arr(7 downto 0) := (others => 0);
+ -- ps unit
+ lvds_skew_dq : in t_natural_arr(7 downto 0) := (others => 0);
+ -- ps unit
+ lvds_skew_ovr : in natural := 0;
+ -- ps unit
+ lvds_skew_dclk : in natural := 0
);
end adu_half;
architecture beh of adu_half is
- constant c_dclk_rst_invert : boolean := false; -- Default FALSE because DCLK_RST on ADC is active high, use TRUE to model for a P/N cross
+ -- Default FALSE because DCLK_RST on ADC is active high, use TRUE to model for a P/N cross
+ constant c_dclk_rst_invert : boolean := false;
-- Model I2C slaves on the bus
- constant c_max1618_address : std_logic_vector := TO_UVEC(I2C_ADU_MAX1617_ADR, 7); -- MAX1618 address MID MID
+ -- MAX1618 address MID MID
+ constant c_max1618_address : std_logic_vector := TO_UVEC(I2C_ADU_MAX1617_ADR, 7);
constant c_max1618_temp : integer := 60;
- constant c_io_expander_address : std_logic_vector := TO_UVEC(I2C_ADU_PCA9555_ADR, 7); -- ADR_PCA9555 address
+ -- ADR_PCA9555 address
+ constant c_io_expander_address : std_logic_vector := TO_UVEC(I2C_ADU_PCA9555_ADR, 7);
signal DI_rewire : std_logic_vector(7 downto 0);
signal DQ_rewire : std_logic_vector(7 downto 0);
@@ -131,8 +140,10 @@ begin
);
-- I2C bus
- SCL <= 'H'; -- model I2C pull up
- SDA <= 'H'; -- model I2C pull up
+ -- model I2C pull up
+ SCL <= 'H';
+ -- model I2C pull up
+ SDA <= 'H';
u_sens_temp : entity i2c_lib.dev_max1618
generic map (
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd
index 628f882bf3b38ba3b2398bd61efadc839893a14b..85cf0e78c81a6577a3445eab26d388cf601391a9 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd
@@ -38,11 +38,15 @@ end tb_aduh_dd;
architecture tb of tb_aduh_dd is
-- ADU board
constant c_adc_w : natural := 8;
- constant c_ana_diff : natural := 16; -- analogue offset value between the port A, B, C, D
+ -- analogue offset value between the port A, B, C, D
+ constant c_ana_diff : natural := 16;
- constant c_lvds_skew_zero : t_natural_arr(c_adc_w - 1 downto 0) := (others => 0); -- ps unit
- constant c_lvds_skew_init : t_natural_arr(c_adc_w - 1 downto 0) := (350, 300, 250, 200, 150, 100, 50, 0); -- ps unit
- constant c_lvds_skew_clk : natural := 35; -- ps unit
+ -- ps unit
+ constant c_lvds_skew_zero : t_natural_arr(c_adc_w - 1 downto 0) := (others => 0);
+ -- ps unit
+ constant c_lvds_skew_init : t_natural_arr(c_adc_w - 1 downto 0) := (350, 300, 250, 200, 150, 100, 50, 0);
+ -- ps unit
+ constant c_lvds_skew_clk : natural := 35;
constant c_dclk_init_phase_a : natural := 0;
constant c_dclk_init_phase_b : natural := 0;
@@ -62,20 +66,28 @@ architecture tb of tb_aduh_dd is
constant c_ai : t_c_aduh_dd_ai := (4, 2, 2, c_adc_w, 2, 2, true, false, (7, 7, (0, 1, 2, 3, 4, 5, 6, 7),
(0, 1, 2, 3, 4, 5, 6, 7),
(0, 1, 2, 3, 4, 5, 6, 7),
- (0, 1, 2, 3, 4, 5, 6, 7))); -- use defaults, compensate for c_lvds_skew_init
+ -- use defaults, compensate for c_lvds_skew_init
+ (0, 1, 2, 3, 4, 5, 6, 7)));
- constant c_dp_factor : natural := c_ai.rx_factor * c_ai.dd_factor; -- = 4 = 2 * 2
+ -- = 4 = 2 * 2
+ constant c_dp_factor : natural := c_ai.rx_factor * c_ai.dd_factor;
- constant c_sample_period : time := 1250 ps; -- 800 MTps
- constant c_dp_clk_period : time := c_sample_period * c_dp_factor; -- 200 MHz
+ -- 800 MTps
+ constant c_sample_period : time := 1250 ps;
+ -- 200 MHz
+ constant c_dp_clk_period : time := c_sample_period * c_dp_factor;
- constant c_dp_clk_skew : natural := 235; -- ps unit, model skew between dp_clk and SCLK, both are in lock with the same reference
+ -- ps unit, model skew between dp_clk and SCLK, both are in lock with the same reference
+ constant c_dp_clk_skew : natural := 235;
- constant c_dp_phs_clk_step : time := c_dp_clk_period / 32; -- the PLL can output clocks with phase shifts of 360/32 = 11.25 degrees
- constant c_dp_phs_clk_period : natural := 32; -- number of dp_clk periods per dp_phs_clk period
+ -- the PLL can output clocks with phase shifts of 360/32 = 11.25 degrees
+ constant c_dp_phs_clk_step : time := c_dp_clk_period / 32;
+ -- number of dp_clk periods per dp_phs_clk period
+ constant c_dp_phs_clk_period : natural := 32;
constant c_nof_dp_phs_clk : natural := 1;
- constant c_dp_dat_w : natural := c_dp_factor * c_adc_w; -- 32 bit
+ -- 32 bit
+ constant c_dp_dat_w : natural := c_dp_factor * c_adc_w;
constant c_rl : natural := 1;
constant c_verify_delay : natural := 10;
@@ -84,29 +96,42 @@ architecture tb of tb_aduh_dd is
type t_dp_data_arr is array (integer range <>) of std_logic_vector(c_dp_dat_w - 1 downto 0);
-- Analogue
- signal ANA_DAT : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- Common ADC reference data source
- signal ANA_A : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port A
- signal ANA_B : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port B
- signal ANA_C : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port C
- signal ANA_D : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port D
- signal SCLK : std_logic := '1'; -- central sample clock = 800 MHz
- signal DCLK_AB : std_logic; -- digital lvds clock = 400 MHz (DDR)
- signal DCLK_CD : std_logic; -- digital lvds clock = 400 MHz (DDR)
- signal DCLK_RST_AB : std_logic; -- synchronise digital lvds clock
- signal DCLK_RST_CD : std_logic; -- synchronise digital lvds clock
+ -- Common ADC reference data source
+ signal ANA_DAT : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port A
+ signal ANA_A : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port B
+ signal ANA_B : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port C
+ signal ANA_C : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port D
+ signal ANA_D : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- central sample clock = 800 MHz
+ signal SCLK : std_logic := '1';
+ -- digital lvds clock = 400 MHz (DDR)
+ signal DCLK_AB : std_logic;
+ -- digital lvds clock = 400 MHz (DDR)
+ signal DCLK_CD : std_logic;
+ -- synchronise digital lvds clock
+ signal DCLK_RST_AB : std_logic;
+ -- synchronise digital lvds clock
+ signal DCLK_RST_CD : std_logic;
signal DIG_A : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_B : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_C : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_D : std_logic_vector(c_ai.port_w - 1 downto 0);
signal test_pattern_en : std_logic := '0';
- signal lvds_skew_di : t_natural_arr(c_ai.port_w - 1 downto 0) := c_lvds_skew_zero; -- c_lvds_skew_init;
- signal lvds_skew_dq : t_natural_arr(c_ai.port_w - 1 downto 0) := c_lvds_skew_zero; -- c_lvds_skew_init;
+ -- c_lvds_skew_init;
+ signal lvds_skew_di : t_natural_arr(c_ai.port_w - 1 downto 0) := c_lvds_skew_zero;
+ -- c_lvds_skew_init;
+ signal lvds_skew_dq : t_natural_arr(c_ai.port_w - 1 downto 0) := c_lvds_skew_zero;
signal lvds_skew_dclk : natural := c_lvds_skew_clk;
-- Digital streaming
signal tb_end : std_logic := '0';
- signal dp_clk_ref : std_logic := '1'; -- digital data path clock = 200 MHz (deser factor 4);
+ -- digital data path clock = 200 MHz (deser factor 4);
+ signal dp_clk_ref : std_logic := '1';
signal dp_clk : std_logic;
signal dp_rst : std_logic;
signal dp_phs_cnt : natural := 0;
@@ -304,6 +329,7 @@ begin
end if;
end process;
- end generate; -- gen_verify
+ -- gen_verify
+ end generate;
end tb;
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd
index b2f46d0e3544b6393b2e9b74044d0e50a9bfa078..a071397d665a89133ffcc793bf4d765a11f77a24 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd
@@ -40,8 +40,10 @@ use dp_lib.tb_dp_pkg.all;
entity tb_aduh_mean_sum is
generic (
- g_nof_symbols_per_data : natural := 1; -- choose 1 or 4, nof symbols (= ADC samples) per data word
- g_random_control : boolean := true -- use TRUE for random stream flow control, use FALSE for initial debugging
+ -- choose 1 or 4, nof symbols (= ADC samples) per data word
+ g_nof_symbols_per_data : natural := 1;
+ -- use TRUE for random stream flow control, use FALSE for initial debugging
+ g_random_control : boolean := true
);
end tb_aduh_mean_sum;
@@ -52,16 +54,19 @@ architecture tb of tb_aduh_mean_sum is
constant c_symbol_w : natural := 8;
constant c_sum_truncate : boolean := true;
- constant c_sum_w : natural := c_word_w; -- = 32
+ -- = 32
+ constant c_sum_w : natural := c_word_w;
constant c_data_w : natural := g_nof_symbols_per_data * c_symbol_w;
constant c_nof_sync : natural := 10;
constant c_nof_block_per_sync : natural := 2;
- constant c_nof_symbols_per_block : natural := 8; -- nof symbols (= ADC samples) per block
+ -- nof symbols (= ADC samples) per block
+ constant c_nof_symbols_per_block : natural := 8;
constant c_nof_symbols_per_sync : natural := c_nof_block_per_sync * c_nof_symbols_per_block;
- constant c_nof_accumulations : natural := c_nof_symbols_per_sync; -- integration time in symbols
+ -- integration time in symbols
+ constant c_nof_accumulations : natural := c_nof_symbols_per_sync;
constant c_exp_sum_arr : t_natural_arr(0 to 3) := (0, 120, 376, 632);
@@ -70,7 +75,8 @@ architecture tb of tb_aduh_mean_sum is
signal rst : std_logic;
signal clk : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
signal st_en : std_logic := '1';
signal st_sosi : t_dp_sosi := c_dp_sosi_rst;
@@ -93,7 +99,8 @@ begin
random_0 <= func_common_random(random_0) when rising_edge(clk);
--st_en <= NOT st_en WHEN rising_edge(clk);
--st_en <= random_0(random_0'HIGH);
- end generate; -- else the st_en line is always active
+ -- else the st_en line is always active
+ end generate;
p_st_stimuli : process
variable v_symbol : natural := 0;
@@ -105,10 +112,12 @@ begin
-- Run some sync intervals with DSP counter data for the data field
for I in 0 to c_nof_sync - 1 loop
-- Generate st_sosi with sync at sop
- proc_dp_gen_block_data(c_rl, true, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, true, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi);
v_symbol := v_symbol + c_nof_symbols_per_block;
for J in 0 to c_nof_block_per_sync - 2 loop
- proc_dp_gen_block_data(c_rl, true, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi); -- no sync
+ -- no sync
+ proc_dp_gen_block_data(c_rl, true, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi);
v_symbol := v_symbol + c_nof_symbols_per_block;
end loop;
end loop;
@@ -127,17 +136,23 @@ begin
-- Add BSN to the ST data
p_in_sosi : process(st_sosi, bsn)
begin
- in_sosi <= st_sosi; -- sync at sop, data
- in_sosi.bsn <= TO_DP_BSN(bsn); -- bsn at sop
+ -- sync at sop, data
+ in_sosi <= st_sosi;
+ -- bsn at sop
+ in_sosi.bsn <= TO_DP_BSN(bsn);
end process;
u_dut : entity work.aduh_mean_sum
generic map (
g_symbol_w => c_symbol_w,
- g_nof_symbols_per_data => g_nof_symbols_per_data, -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
- g_nof_accumulations => c_nof_accumulations, -- integration time in symbols
- g_sum_truncate => c_sum_truncate, -- when TRUE truncate (keep MS part) else resize (keep sign and LS part)
- g_sum_w => c_sum_w -- typcially MM word width = 32
+ -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data => g_nof_symbols_per_data,
+ -- integration time in symbols
+ g_nof_accumulations => c_nof_accumulations,
+ -- when TRUE truncate (keep MS part) else resize (keep sign and LS part)
+ g_sum_truncate => c_sum_truncate,
+ -- typcially MM word width = 32
+ g_sum_w => c_sum_w
)
port map (
clk => clk,
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd
index ca47377b5db52ab8045708d26ccdb18e57965c0c..ecaea678a2f43c2287bac26ea88cfc35345b5d25 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd
@@ -34,9 +34,12 @@ architecture tb of tb_aduh_pll is
-- Conclusion from the c_model_rx_clk_* investigations:
-- . It appears that it is not possible to avoid the DCLK->rx_clk divide by 2
-- phase uncertainty by releasing the CDA reset in the dp-clk domain.
- constant c_model_rx_clk_phase_uncertainty_in_time : boolean := true; -- When TRUE model DPA lock at different relative SCLK phase in time (0..dp_deser_factor-1)
- constant c_model_rx_clk_phase_uncertainty_in_space : boolean := false; -- When TRUE model DPA lock at different relative SCLK phase for each of the rx_clk (0..nof_clocks-1)
- constant c_model_rx_clk_hold_reference : boolean := true; -- When TRUE AND nof_clocks>1 then keep rx_clk(0) active so that rx_clk(0) is a reference
+ -- When TRUE model DPA lock at different relative SCLK phase in time (0..dp_deser_factor-1)
+ constant c_model_rx_clk_phase_uncertainty_in_time : boolean := true;
+ -- When TRUE model DPA lock at different relative SCLK phase for each of the rx_clk (0..nof_clocks-1)
+ constant c_model_rx_clk_phase_uncertainty_in_space : boolean := false;
+ -- When TRUE AND nof_clocks>1 then keep rx_clk(0) active so that rx_clk(0) is a reference
+ constant c_model_rx_clk_hold_reference : boolean := true;
-- Conclusion from the c_model_lvds_skew investigations:
-- . It appears that the DPA model in altera_mf.vhd does not model DPA for
@@ -44,7 +47,8 @@ architecture tb of tb_aduh_pll is
-- model ppm drift which occurs in soft CDR (clock data recovery) mode,
-- such as needed e.g. for SGMII. In the Chip Planner the SERDES_RX that
-- implements the DPA is connected but presented as a black box.
- constant c_model_lvds_skew : boolean := false; -- When TRUE model DPA lock at different relative SCLK phase in time (0..dp_deser_factor-1)
+ -- When TRUE model DPA lock at different relative SCLK phase in time (0..dp_deser_factor-1)
+ constant c_model_lvds_skew : boolean := false;
-- Conclusion from the c_model_dclk_phase investigations:
-- . Use
@@ -59,7 +63,8 @@ architecture tb of tb_aduh_pll is
-- c_model_rx_clk_phase_uncertainty_in_time effect to become void anyway.
-- Anyway it is safe to state that using the ADC DCLK_RST is a proper
-- means to align the lvds_clk from all ADU in a system to the dp_clk.
- constant c_model_dclk_phase : boolean := false; -- When TRUE start DCLK_CD with different phase then DCLK_AB, else use same phase for both
+ -- When TRUE start DCLK_CD with different phase then DCLK_AB, else use same phase for both
+ constant c_model_dclk_phase : boolean := false;
-- TYPE t_c_aduh_pll_ai IS RECORD
-- nof_sp : NATURAL; -- = 4; -- Fixed support 4 signal paths A,B,C,D, whether they contain active data depends on nof_adu
@@ -85,7 +90,8 @@ architecture tb of tb_aduh_pll is
-- CONSTANT c_ai : t_c_aduh_pll_ai := (4, 2, 2, 8, 0, 800, FALSE, TRUE, FALSE, 0, 2, 2, 4); -- model no dpa, use lvds_clk, lvds_clk_phase = 0
-- CONSTANT c_ai : t_c_aduh_pll_ai := (4, 2, 2, 8, 0, 800, FALSE, TRUE, FALSE, 90, 2, 2, 4); -- model no dpa, use lvds_clk, lvds_clk_phase = 90
-- CONSTANT c_ai : t_c_aduh_pll_ai := (4, 2, 2, 8, 0, 800, TRUE, FALSE, FALSE, 0, 1, 4, 4); -- model use dpa, use dp_clk
- constant c_ai : t_c_aduh_pll_ai := (4, 2, 2, 8, 0, 800, true, true, false, 0, 2, 2, 4); -- model use dpa, use lvds_clk
+ -- model use dpa, use lvds_clk
+ constant c_ai : t_c_aduh_pll_ai := (4, 2, 2, 8, 0, 800, true, true, false, 0, 2, 2, 4);
-- CONSTANT c_ai : t_c_aduh_pll_ai := (4, 2, 2, 8, 0, 800, TRUE, TRUE, TRUE, 0, 2, 2, 4); -- model use dpa, use lvds_clk, use lvds_clk_rst
-- Conclusion on c_ai:
@@ -94,40 +100,61 @@ architecture tb of tb_aduh_pll is
-- . If DCLK_RST is supported by BN - ADU then using lvds_clk as LVDS_RX PLL reference with lvds_clk_rst to ADU is preferred.
-- . Not using DPA and using the lvds_clk should also be tried and verified on the BN - ADU hardware.
- constant c_sample_freq : natural := c_ai.lvds_data_rate; -- Msps
+ -- Msps
+ constant c_sample_freq : natural := c_ai.lvds_data_rate;
constant c_sample_period : time := 1000000 ps / c_sample_freq;
- constant c_pll_reset_time : time := 20 ns; -- minimum 10 ns
- constant c_measurement_period : time := 50 us; -- minimum depends on number of data line toggles for DPA, which can take 10-s of us for MSbit counter data,
+ -- minimum 10 ns
+ constant c_pll_reset_time : time := 20 ns;
+ -- minimum depends on number of data line toggles for DPA, which can take 10-s of us for MSbit counter data,
+ constant c_measurement_period : time := 50 us;
-- because DPA lock is only achieved after about 256 toggles
- constant c_lvds_skew_zero : t_natural_arr(7 downto 0) := ( 0, 0, 0, 0, 0, 0, 0, 0); -- ps unit
- constant c_lvds_skew_init : t_natural_arr(7 downto 0) := (70, 60, 50, 40, 30, 20, 10, 0); -- ps unit
- constant c_lvds_skew_ovr : natural := 55; -- ps unit
- constant c_lvds_skew_clk : natural := 35; -- ps unit
+ -- ps unit
+ constant c_lvds_skew_zero : t_natural_arr(7 downto 0) := ( 0, 0, 0, 0, 0, 0, 0, 0);
+ -- ps unit
+ constant c_lvds_skew_init : t_natural_arr(7 downto 0) := (70, 60, 50, 40, 30, 20, 10, 0);
+ -- ps unit
+ constant c_lvds_skew_ovr : natural := 55;
+ -- ps unit
+ constant c_lvds_skew_clk : natural := 35;
constant c_dp_clk_period : time := c_ai.dp_deser_factor * c_sample_period;
- constant c_dp_clk_skew : natural := 335; -- ps unit, model skew between dp_clk and SCLK, both are in lock with the same reference
+ -- ps unit, model skew between dp_clk and SCLK, both are in lock with the same reference
+ constant c_dp_clk_skew : natural := 335;
- constant c_ana_diff : natural := 16; -- analogue offset value between the port A, B, C, D
+ -- analogue offset value between the port A, B, C, D
+ constant c_ana_diff : natural := 16;
- constant c_adc_w : natural := c_ai.port_w; -- 8 bit
- constant c_dp_dat_w : natural := c_adc_w * c_ai.dp_deser_factor; -- 32 bit
+ -- 8 bit
+ constant c_adc_w : natural := c_ai.port_w;
+ -- 32 bit
+ constant c_dp_dat_w : natural := c_adc_w * c_ai.dp_deser_factor;
type t_dp_data_arr is array (integer range <>) of std_logic_vector(c_dp_dat_w - 1 downto 0);
-- ADC : c_ai.port_w = 8-bit
- signal ANA_DAT : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- Common ADC reference data source
- signal ANA_A : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port A
- signal ANA_B : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port B
- signal ANA_C : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port C
- signal ANA_D : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0'); -- ADC port D
+ -- Common ADC reference data source
+ signal ANA_DAT : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port A
+ signal ANA_A : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port B
+ signal ANA_B : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port C
+ signal ANA_C : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
+ -- ADC port D
+ signal ANA_D : std_logic_vector(c_ai.port_w - 1 downto 0) := (others => '0');
signal ANA_OVR : std_logic := '0';
- signal SCLK : std_logic := '1'; -- central sample clock = 800 MHz
- signal DCLK_AB : std_logic; -- digital lvds clock = 400 MHz (DDR)
- signal DCLK_CD : std_logic; -- digital lvds clock = 400 MHz (DDR)
- signal DCLK_RST_AB : std_logic; -- synchronise digital lvds clock
- signal DCLK_RST_CD : std_logic; -- synchronise digital lvds clock
+ -- central sample clock = 800 MHz
+ signal SCLK : std_logic := '1';
+ -- digital lvds clock = 400 MHz (DDR)
+ signal DCLK_AB : std_logic;
+ -- digital lvds clock = 400 MHz (DDR)
+ signal DCLK_CD : std_logic;
+ -- synchronise digital lvds clock
+ signal DCLK_RST_AB : std_logic;
+ -- synchronise digital lvds clock
+ signal DCLK_RST_CD : std_logic;
signal DIG_A : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_B : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_C : std_logic_vector(c_ai.port_w - 1 downto 0);
@@ -142,14 +169,19 @@ architecture tb of tb_aduh_pll is
signal lvds_skew_dclk : natural := c_lvds_skew_clk;
-- Digital
- signal dp_clk_ref : std_logic := '1'; -- digital data path clock = 200 MHz (deser factor 4);
- signal dp_clk : std_logic := '1'; -- digital data path clock = 200 MHz (deser factor 4);
+ -- digital data path clock = 200 MHz (deser factor 4);
+ signal dp_clk_ref : std_logic := '1';
+ -- digital data path clock = 200 MHz (deser factor 4);
+ signal dp_clk : std_logic := '1';
-- DUT
signal dp_restart : std_logic_vector(c_ai.nof_clocks - 1 downto 0);
- signal dp_delay_settings : t_natural_arr(func_aduh_pll_lvds_dat_w(c_ai) - 1 downto 0) := (others => 0); -- ADC_BI IOE data delay settings when g_use_dpa = FALSE
- signal dp_cda_settings : t_natural_arr(func_aduh_pll_lvds_dat_w(c_ai) - 1 downto 0) := (others => 1); -- ADC_BI channel data alignment settings
- signal dp_sosi : t_dp_sosi_arr(0 to c_ai.nof_sp - 1); -- ADC_BI ports [0:3] = [A,B,C,D]
+ -- ADC_BI IOE data delay settings when g_use_dpa = FALSE
+ signal dp_delay_settings : t_natural_arr(func_aduh_pll_lvds_dat_w(c_ai) - 1 downto 0) := (others => 0);
+ -- ADC_BI channel data alignment settings
+ signal dp_cda_settings : t_natural_arr(func_aduh_pll_lvds_dat_w(c_ai) - 1 downto 0) := (others => 1);
+ -- ADC_BI ports [0:3] = [A,B,C,D]
+ signal dp_sosi : t_dp_sosi_arr(0 to c_ai.nof_sp - 1);
-- Verify
signal restart_any : std_logic := '0';
@@ -178,7 +210,8 @@ begin
ANA_B <= INCR_UVEC(ANA_DAT, 1 * c_ana_diff);
ANA_C <= INCR_UVEC(ANA_DAT, 2 * c_ana_diff);
ANA_D <= INCR_UVEC(ANA_DAT, 3 * c_ana_diff);
- ANA_OVR <= not ANA_OVR when rising_edge(SCLK); -- simple overflow model used for both ADC
+ -- simple overflow model used for both ADC
+ ANA_OVR <= not ANA_OVR when rising_edge(SCLK);
-- Same sample clock for all ADC
SCLK <= not SCLK after c_sample_period / 2;
@@ -246,14 +279,18 @@ begin
lvds_skew_dq <= c_lvds_skew_zero;
-- Wait for the ADU
- dp_restart <= (others => '1'); -- assert the LVDS RX PLL reset
+ -- assert the LVDS RX PLL reset
+ dp_restart <= (others => '1');
wait until rising_edge(DCLK_AB);
- wait until rising_edge(DCLK_CD); -- wait to ensure that the DCLKs are active
- wait for 1 * c_sample_period; -- set arbitrary initial phase
+ -- wait to ensure that the DCLKs are active
+ wait until rising_edge(DCLK_CD);
+ -- set arbitrary initial phase
+ wait for 1 * c_sample_period;
-- Run several measurement with ADU
for I in 0 to 10 loop
- wait for c_pll_reset_time; -- ensure mimimum LVDS RX PLL reset time
+ -- ensure mimimum LVDS RX PLL reset time
+ wait for c_pll_reset_time;
if c_model_rx_clk_phase_uncertainty_in_time = true then
-- The next measurement will start 1 SCLK c_sample_period later to
@@ -277,26 +314,31 @@ begin
-- retimed to the rx_clk domain anyway and the phase relation between
-- the rx_clk derived from ADU0 and ADU1 may differ.
for J in c_ai.nof_clocks - 1 downto 0 loop
- dp_restart(J) <= '0'; -- release the LVDS RX PLL(J) reset
+ -- release the LVDS RX PLL(J) reset
+ dp_restart(J) <= '0';
wait for c_sample_period;
end loop;
end if;
- dp_restart <= (others => '0'); -- release the LVDS RX PLL reset
+ -- release the LVDS RX PLL reset
+ dp_restart <= (others => '0');
-- Begin of the measurement
if c_model_lvds_skew = true then
wait for c_measurement_period;
- lvds_skew_di <= (700, 500, 250, 140, 130, 320, 60, 50); -- ps unit
- lvds_skew_dq <= (700, 500, 250, 140, 130, 320, 60, 50); -- ps unit
+ -- ps unit
+ lvds_skew_di <= (700, 500, 250, 140, 130, 320, 60, 50);
+ -- ps unit
+ lvds_skew_dq <= (700, 500, 250, 140, 130, 320, 60, 50);
wait for 10 * c_measurement_period;
lvds_skew_di <= c_lvds_skew_zero;
lvds_skew_dq <= c_lvds_skew_zero;
end if;
wait for c_measurement_period;
- dp_restart <= (others => '1'); -- assert the LVDS RX PLL reset
+ -- assert the LVDS RX PLL reset
+ dp_restart <= (others => '1');
if c_model_rx_clk_hold_reference = true then
-- Do not assert LVDS RX PLL reset for rx_clk 0, so keep this one
@@ -349,7 +391,8 @@ begin
cda_settings => dp_cda_settings,
-- . Streaming
- src_out => dp_sosi -- = [0:3] = ADC_BI ports [A,B,C,D]
+ -- = [0:3] = ADC_BI ports [A,B,C,D]
+ src_out => dp_sosi
);
-----------------------------------------------------------------------------
@@ -378,12 +421,14 @@ begin
-- Enable verify after the valid goes active and continue until valid goes low
verify_valid(I) <= dp_sosi(I).valid when rising_edge(dp_clk);
verify_restart(I) <= dp_restart((I * c_ai.nof_clocks) / c_ai.nof_sp);
- verify_en(I) <= verify_valid(I) and not verify_restart(I); -- also and with dp_restart, because of latency in dp_sosi.valid
+ -- also and with dp_restart, because of latency in dp_sosi.valid
+ verify_en(I) <= verify_valid(I) and not verify_restart(I);
-- Verify that the symbols in the data are incrementing per ADC (ready not used, empty not used)
verify_data(I) <= dp_sosi(I).data(c_dp_dat_w - 1 downto 0);
proc_dp_verify_symbols(1, c_dp_dat_w, c_adc_w, dp_clk, verify_en(I), sl1, dp_sosi(I).valid, sl0, verify_data(I), slv0, prev_verify_data(I));
- end generate; -- gen_verify_increment
+ -- gen_verify_increment
+ end generate;
-- Verify the data alignment between the ADCs by checking the expected c_ana_diff offset
gen_verify_alignment : for I in 1 to c_ai.nof_sp - 1 generate
@@ -399,5 +444,6 @@ begin
end if;
end if;
end process;
- end generate; -- gen_verify_alignment
+ -- gen_verify_alignment
+ end generate;
end tb;
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_power_sum.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_power_sum.vhd
index 05a46a4529b24f42ef5d771d42522302c4523a06..82f881f99cb488da28452e666d13b7ea4de68476 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_power_sum.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_power_sum.vhd
@@ -40,8 +40,10 @@ use dp_lib.tb_dp_pkg.all;
entity tb_aduh_power_sum is
generic (
- g_nof_symbols_per_data : natural := 4; -- choose 1 or 4, nof symbols (= ADC samples) per data word
- g_random_control : boolean := true -- use TRUE for random stream flow control, use FALSE for initial debugging
+ -- choose 1 or 4, nof symbols (= ADC samples) per data word
+ g_nof_symbols_per_data : natural := 4;
+ -- use TRUE for random stream flow control, use FALSE for initial debugging
+ g_random_control : boolean := true
);
end tb_aduh_power_sum;
@@ -50,10 +52,12 @@ architecture tb of tb_aduh_power_sum is
constant c_rl : natural := 1;
constant c_symbol_w : natural := 8;
- constant c_nof_symbols_per_block : natural := 8; -- nof symbols (= ADC samples) per block
+ -- nof symbols (= ADC samples) per block
+ constant c_nof_symbols_per_block : natural := 8;
constant c_pwr_sum_truncate : boolean := true;
- constant c_pwr_sum_w : natural := c_word_w; -- = 32
+ -- = 32
+ constant c_pwr_sum_w : natural := c_word_w;
constant c_data_w : natural := g_nof_symbols_per_data * c_symbol_w;
@@ -61,7 +65,8 @@ architecture tb of tb_aduh_power_sum is
constant c_nof_block_per_sync : natural := 2;
constant c_nof_symbols_per_sync : natural := c_nof_block_per_sync * c_nof_symbols_per_block;
- constant c_nof_accumulations : natural := c_nof_symbols_per_sync; -- integration time in symbols
+ -- integration time in symbols
+ constant c_nof_accumulations : natural := c_nof_symbols_per_sync;
constant c_exp_sum_arr : t_natural_arr(0 to 3) := (0, 1240, 9176, 25304);
@@ -70,7 +75,8 @@ architecture tb of tb_aduh_power_sum is
signal rst : std_logic;
signal clk : std_logic := '1';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
signal st_en : std_logic := '1';
signal st_sosi : t_dp_sosi := c_dp_sosi_rst;
@@ -91,7 +97,8 @@ begin
random_0 <= func_common_random(random_0) when rising_edge(clk);
--st_en <= NOT st_en WHEN rising_edge(clk);
--st_en <= random_0(random_0'HIGH);
- end generate; -- else the st_en line is always active
+ -- else the st_en line is always active
+ end generate;
p_st_stimuli : process
variable v_symbol : natural := 0;
@@ -104,10 +111,12 @@ begin
wait until rising_edge(clk);
for I in 0 to c_nof_sync - 1 loop
-- Generate st_sosi with sync at sop
- proc_dp_gen_block_data(c_rl, true, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi); -- next sync
+ -- next sync
+ proc_dp_gen_block_data(c_rl, true, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi);
v_symbol := v_symbol + c_nof_symbols_per_block;
for J in 0 to c_nof_block_per_sync - 2 loop
- proc_dp_gen_block_data(c_rl, true, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi); -- no sync
+ -- no sync
+ proc_dp_gen_block_data(c_rl, true, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi);
v_symbol := v_symbol + c_nof_symbols_per_block;
end loop;
end loop;
@@ -126,17 +135,23 @@ begin
-- Add BSN to the ST data
p_in_sosi : process(st_sosi, bsn)
begin
- in_sosi <= st_sosi; -- sync at sop, data
- in_sosi.bsn <= TO_DP_BSN(bsn); -- bsn at sop
+ -- sync at sop, data
+ in_sosi <= st_sosi;
+ -- bsn at sop
+ in_sosi.bsn <= TO_DP_BSN(bsn);
end process;
u_dut : entity work.aduh_power_sum
generic map (
g_symbol_w => c_symbol_w,
- g_nof_symbols_per_data => g_nof_symbols_per_data, -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
- g_nof_accumulations => c_nof_accumulations, -- integration time in symbols
- g_pwr_sum_truncate => c_pwr_sum_truncate, -- when TRUE truncate (keep MS part) else resize (keep sign and LS part)
- g_pwr_sum_w => c_pwr_sum_w -- typcially MM word width = 32
+ -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data => g_nof_symbols_per_data,
+ -- integration time in symbols
+ g_nof_accumulations => c_nof_accumulations,
+ -- when TRUE truncate (keep MS part) else resize (keep sign and LS part)
+ g_pwr_sum_truncate => c_pwr_sum_truncate,
+ -- typcially MM word width = 32
+ g_pwr_sum_w => c_pwr_sum_w
)
port map (
clk => clk,
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd
index 6140c2af10c0223f8835cb838f58141ca5b1965a..87a2cd53a927d02468af7ae79247d2f8aac0ac65 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd
@@ -44,27 +44,36 @@ architecture tb of tb_aduh_verify is
-- rx_factor : NATURAL; -- = 2
-- deskew : t_c_aduh_delays; -- = (0, 0, (OTHERS=>0), (OTHERS=>0), (OTHERS=>0), (OTHERS=>0)) -- clock: a, b, data: a, b, c, d
--END RECORD;
- constant c_ai : t_c_aduh_dd_ai := c_aduh_dd_ai; -- use defaults
+ -- use defaults
+ constant c_ai : t_c_aduh_dd_ai := c_aduh_dd_ai;
- constant c_dp_factor : natural := c_ai.rx_factor * c_ai.dd_factor; -- = 4 = 2 * 2
+ -- = 4 = 2 * 2
+ constant c_dp_factor : natural := c_ai.rx_factor * c_ai.dd_factor;
- constant c_sample_period : time := 1250 ps; -- 800 MTps
- constant c_dp_clk_period : time := c_sample_period * c_dp_factor; -- 200 MHz
+ -- 800 MTps
+ constant c_sample_period : time := 1250 ps;
+ -- 200 MHz
+ constant c_dp_clk_period : time := c_sample_period * c_dp_factor;
- constant c_dp_phs_clk_step : time := c_dp_clk_period / 32; -- the PLL can output clocks with phase shifts of 360/32 = 11.25 degrees
- constant c_dp_phs_clk_period : natural := 32; -- number of dp_clk periods per dp_phs_clk period
+ -- the PLL can output clocks with phase shifts of 360/32 = 11.25 degrees
+ constant c_dp_phs_clk_step : time := c_dp_clk_period / 32;
+ -- number of dp_clk periods per dp_phs_clk period
+ constant c_dp_phs_clk_period : natural := 32;
constant c_nof_dp_phs_clk : natural := 1;
signal tb_end : std_logic := '0';
-- Analogue
- signal SCLK : std_logic := '1'; -- central sample clock = 800 MHz
- signal DCLK : std_logic; -- digital lvds clock = 400 MHz (DDR)
+ -- central sample clock = 800 MHz
+ signal SCLK : std_logic := '1';
+ -- digital lvds clock = 400 MHz (DDR)
+ signal DCLK : std_logic;
signal DIG_A : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_B : std_logic_vector(c_ai.port_w - 1 downto 0);
-- Digital streaming
- signal dp_clk : std_logic := '1'; -- digital data path clock = 200 MHz (deser factor 4);
+ -- digital data path clock = 200 MHz (deser factor 4);
+ signal dp_clk : std_logic := '1';
signal dp_rst : std_logic;
signal dp_phs_cnt : natural := 0;
signal dp_phs_clk : std_logic := '1';
@@ -80,15 +89,19 @@ architecture tb of tb_aduh_verify is
signal ab_stable_ack : std_logic := '0';
signal test_pattern_en : std_logic;
- signal verify_ok : std_logic; -- verify that verify_res indicates OK when expected
- signal verify_wrong : std_logic; -- verify that verify_res indicates ERROR when expected
+ -- verify that verify_res indicates OK when expected
+ signal verify_ok : std_logic;
+ -- verify that verify_res indicates ERROR when expected
+ signal verify_wrong : std_logic;
- signal a_pattern_sel : natural range 0 to 1 := 0; -- 0 = DI, 1 = DQ
+ -- 0 = DI, 1 = DQ
+ signal a_pattern_sel : natural range 0 to 1 := 0;
signal a_verify_res : std_logic_vector(c_ai.port_w downto 0);
signal a_verify_res_val : std_logic;
signal a_verify_res_ack : std_logic;
- signal b_pattern_sel : natural range 0 to 1 := 1; -- 0 = DI, 1 = DQ
+ -- 0 = DI, 1 = DQ
+ signal b_pattern_sel : natural range 0 to 1 := 1;
signal b_verify_res : std_logic_vector(c_ai.port_w downto 0);
signal b_verify_res_val : std_logic;
signal b_verify_res_ack : std_logic;
@@ -114,8 +127,10 @@ begin
u_verify_a : entity work.aduh_verify
generic map (
- g_symbol_w => c_ai.port_w, -- = 8, fixed
- g_nof_symbols_per_data => c_dp_factor -- = 4, fixed, big endian in_sosi.data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ -- = 8, fixed
+ g_symbol_w => c_ai.port_w,
+ -- = 4, fixed, big endian in_sosi.data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data => c_dp_factor
)
port map (
rst => dp_rst,
@@ -133,8 +148,10 @@ begin
u_verify_b : entity work.aduh_verify
generic map (
- g_symbol_w => c_ai.port_w, -- = 8, fixed
- g_nof_symbols_per_data => c_dp_factor -- = 4, fixed, big endian in_sosi.data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ -- = 8, fixed
+ g_symbol_w => c_ai.port_w,
+ -- = 4, fixed, big endian in_sosi.data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_symbols_per_data => c_dp_factor
)
port map (
rst => dp_rst,
diff --git a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd.vhd b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd.vhd
index 86a3bdb9b0adab0c1e1f28f77ef444e82368945e..dd2fe67969ab16927a66765c77e7b7fe3a1c44c4 100644
--- a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd.vhd
@@ -33,19 +33,27 @@ end tb_lvdsh_dd;
architecture tb of tb_lvdsh_dd is
constant c_config_clk_period : time := 10 ns;
- constant c_sp_clk_period : time := 1250 ps; -- 800 MSps sample clock
- constant c_in_clk_period : time := c_sp_clk_period * 2; -- 400 MHz double data rate clock
+ -- 800 MSps sample clock
+ constant c_sp_clk_period : time := 1250 ps;
+ -- 400 MHz double data rate clock
+ constant c_in_clk_period : time := c_sp_clk_period * 2;
constant c_in_dat_w : natural := 8;
- constant c_in_dat_delay_arr : t_natural_arr(0 to c_in_dat_w - 1) := array_init(0, c_in_dat_w, 1); -- nof must match g_dat_w
+ -- nof must match g_dat_w
+ constant c_in_dat_delay_arr : t_natural_arr(0 to c_in_dat_w - 1) := array_init(0, c_in_dat_w, 1);
constant c_in_clk_delay : natural := c_in_dat_delay_arr(c_in_dat_w - 1) + 1;
- constant c_out_dat_w : natural := 2 * c_in_dat_w; -- hi & lo
+ -- hi & lo
+ constant c_out_dat_w : natural := 2 * c_in_dat_w;
constant c_rx_big_endian : boolean := true;
- constant c_rx_factor : natural := 2; -- 1, 2, 4, ... must be a power of 2 because of the mixed width FIFO
- constant c_rx_fifo_size : natural := 32; -- see common_fifo_dc_lock_control used in lvds_dd for comment
- constant c_rx_fifo_fill : natural := 16; -- see common_fifo_dc_lock_control used in lvds_dd for comment
-
- constant c_rx_clk_period : time := c_rx_factor * c_in_clk_period; -- 200 MHz data path processing clock
+ -- 1, 2, 4, ... must be a power of 2 because of the mixed width FIFO
+ constant c_rx_factor : natural := 2;
+ -- see common_fifo_dc_lock_control used in lvds_dd for comment
+ constant c_rx_fifo_size : natural := 32;
+ -- see common_fifo_dc_lock_control used in lvds_dd for comment
+ constant c_rx_fifo_fill : natural := 16;
+
+ -- 200 MHz data path processing clock
+ constant c_rx_clk_period : time := c_rx_factor * c_in_clk_period;
signal tb_end : std_logic := '0';
signal config_rst : std_logic := '1';
diff --git a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd
index c40e2ec4f3215b1909a805446cd450a995bd2510..b575cc376a0b265ec3eeb709c53bc82d7ea278d4 100644
--- a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd
@@ -58,14 +58,21 @@ use common_lib.tb_common_pkg.all;
entity tb_lvdsh_dd_phs4 is
generic (
- g_dclk_drift : time := -2 ps; -- 0 ps, use -2 ps or 2 ps to model the range of sample phase uncertainty by letting the sclk and dclk drift with respect to the dp_clk,
+ -- 0 ps, use -2 ps or 2 ps to model the range of sample phase uncertainty by letting the sclk and dclk drift with respect to the dp_clk,
+ g_dclk_drift : time := -2 ps;
-- use factor 2 value because of integer divide by 2 for rising and falling edge per sclk clock period.
- g_dclk_offon : boolean := false; -- when TRUE switch the dclk off-on periodically, to model ADU not present or ADU restart or ADU replaced, use FALSE when g_dclk_drift/=0 ps
- g_dp_phs_clk_period : natural := 32; -- number of dp_clk periods per dp_phs_clk period
- g_nof_dp_phs_clk : natural := 4; -- nof dp_phs_clk that can be used to detect the lock, use 1 or 4 to ease interpretation of results when g_dclk_drift/=0 ps
- g_dp_phs_clk_en_mask : natural := 16#FF#; -- bit mask to individually enable or disable a dp_phs_clk in range [g_nof_dp_phs_clk-1:0]
- g_dp_phs_clk_en_vary : boolean := false; -- use FALSE to use g_dp_phs_clk_en_mask, else use TRUE to vary g_dp_phs_clk_en_vec (assuming g_nof_dp_phs_clk>1)
- g_in_phase : natural := 0 -- 0:3
+ -- when TRUE switch the dclk off-on periodically, to model ADU not present or ADU restart or ADU replaced, use FALSE when g_dclk_drift/=0 ps
+ g_dclk_offon : boolean := false;
+ -- number of dp_clk periods per dp_phs_clk period
+ g_dp_phs_clk_period : natural := 32;
+ -- nof dp_phs_clk that can be used to detect the lock, use 1 or 4 to ease interpretation of results when g_dclk_drift/=0 ps
+ g_nof_dp_phs_clk : natural := 4;
+ -- bit mask to individually enable or disable a dp_phs_clk in range [g_nof_dp_phs_clk-1:0]
+ g_dp_phs_clk_en_mask : natural := 16#FF#;
+ -- use FALSE to use g_dp_phs_clk_en_mask, else use TRUE to vary g_dp_phs_clk_en_vec (assuming g_nof_dp_phs_clk>1)
+ g_dp_phs_clk_en_vary : boolean := false;
+ -- 0:3
+ g_in_phase : natural := 0
);
end tb_lvdsh_dd_phs4;
@@ -75,17 +82,25 @@ architecture tb of tb_lvdsh_dd_phs4 is
constant c_wb_factor : natural := c_dd_factor * c_rx_factor;
constant c_sim : boolean := true;
- constant c_tb_duration : natural := sel_a_b(g_dclk_drift /= 0 ps or g_dclk_offon = true, 3000, 10); -- nof tb intervals for tb duration
- constant c_tb_init : natural := sel_a_b(g_dclk_drift /= 0 ps or g_dclk_offon = true, 20, 20); -- nof tb intervals for tb init before verify_en
-
- constant c_clk_factor : natural := 100; -- slow down dclk to improve modelling dclk phase uncertainy with g_dclk_drift, which is minimal 2 ps
- constant c_ref_s_clk_period : time := c_clk_factor * 1.25 ns; -- 800 MHz sample clock for dp_sample_dat monitor
- constant c_adc_s_clk_period : time := c_ref_s_clk_period + g_dclk_drift; -- 800 MHz single data rate ADC sample clock with optional drift
- constant c_ref_dp_clk_period : time := c_ref_s_clk_period * c_wb_factor; -- 200 MHz data clock for Data Path processing
- constant c_dp_phs_clk_step : time := c_ref_dp_clk_period / 32; -- the PLL can output clocks with phase shifts of 360/32 = 11.25 degrees
+ -- nof tb intervals for tb duration
+ constant c_tb_duration : natural := sel_a_b(g_dclk_drift /= 0 ps or g_dclk_offon = true, 3000, 10);
+ -- nof tb intervals for tb init before verify_en
+ constant c_tb_init : natural := sel_a_b(g_dclk_drift /= 0 ps or g_dclk_offon = true, 20, 20);
+
+ -- slow down dclk to improve modelling dclk phase uncertainy with g_dclk_drift, which is minimal 2 ps
+ constant c_clk_factor : natural := 100;
+ -- 800 MHz sample clock for dp_sample_dat monitor
+ constant c_ref_s_clk_period : time := c_clk_factor * 1.25 ns;
+ -- 800 MHz single data rate ADC sample clock with optional drift
+ constant c_adc_s_clk_period : time := c_ref_s_clk_period + g_dclk_drift;
+ -- 200 MHz data clock for Data Path processing
+ constant c_ref_dp_clk_period : time := c_ref_s_clk_period * c_wb_factor;
+ -- the PLL can output clocks with phase shifts of 360/32 = 11.25 degrees
+ constant c_dp_phs_clk_step : time := c_ref_dp_clk_period / 32;
constant c_dp_phs_clk_en_mask : std_logic_vector(g_nof_dp_phs_clk - 1 downto 0) := TO_UVEC(g_dp_phs_clk_en_mask, g_nof_dp_phs_clk);
- constant c_interval : natural := 180; -- some unit tb interval
+ -- some unit tb interval
+ constant c_interval : natural := 180;
constant c_on_interval : time := (c_tb_duration * c_interval / 3 + 3) * c_ref_s_clk_period;
constant c_off_interval : time := (c_tb_duration * c_interval / 3 + 7) * c_ref_s_clk_period;
--CONSTANT c_off_interval : TIME := 1 * c_ref_s_clk_period; -- if multiple of c_wb_factor=4 then the off period is only noticed by the FIFO running empty
@@ -94,9 +109,12 @@ architecture tb of tb_lvdsh_dd_phs4 is
constant c_init : natural := 0;
constant c_in_dat_w : natural := 8;
constant c_dp_dat_w : natural := c_wb_factor * c_in_dat_w;
- constant c_dp_phase_even2 : boolean := g_in_phase mod 2 = 0; -- TRUE for g_in_phase=0,2 and FALSE for g_in_phase=1,3
- constant c_dp_phase_even4 : boolean := g_in_phase < 2; -- TRUE for g_in_phase=0,1 and FALSE for g_in_phase=2,3
- constant c_dp_phase_latency : natural := 1; -- account for internal pipeling to be able to compare dp_sample_phase with the in_sample_phase
+ -- TRUE for g_in_phase=0,2 and FALSE for g_in_phase=1,3
+ constant c_dp_phase_even2 : boolean := g_in_phase mod 2 = 0;
+ -- TRUE for g_in_phase=0,1 and FALSE for g_in_phase=2,3
+ constant c_dp_phase_even4 : boolean := g_in_phase < 2;
+ -- account for internal pipeling to be able to compare dp_sample_phase with the in_sample_phase
+ constant c_dp_phase_latency : natural := 1;
signal tb_g_dclk_drift : time := g_dclk_drift;
signal tb_g_dclk_offon : boolean := g_dclk_offon;
@@ -107,7 +125,8 @@ architecture tb of tb_lvdsh_dd_phs4 is
signal adc_s_clk : std_logic := '1';
signal adc_d_clk : std_logic := '1';
signal adc_d_clk_off : std_logic := '0';
- signal adc_d_clkg : std_logic := '1'; -- = adc_d_clk gated with adc_d_clk_off
+ -- = adc_d_clk gated with adc_d_clk_off
+ signal adc_d_clkg : std_logic := '1';
signal ref_s_clk : std_logic := '1';
signal ref_d_clk : std_logic := '1';
signal ref_dp_clk : std_logic := '1';
@@ -137,7 +156,8 @@ architecture tb of tb_lvdsh_dd_phs4 is
signal in_sample_phase : natural;
signal dp_sample_phase : natural;
- signal dp_status : std_logic_vector(c_word_w - 1 downto 0); -- extra status information for debug
+ -- extra status information for debug
+ signal dp_status : std_logic_vector(c_word_w - 1 downto 0);
signal dp_phs_locked : std_logic;
signal dp_word_locked : std_logic;
signal dp_word_stable : std_logic;
@@ -167,7 +187,8 @@ begin
dp_clk_vec(I) <= transport ref_dp_clk after (real(I) + 0.5) * c_ref_s_clk_period;
end generate;
- dp_clk <= dp_clk_vec(0) when c_dp_phase_even4 = true else dp_clk_vec(2); -- actually c_dp_phase_even4=TRUE can not truely be modeled from the outside in this tb
+ -- actually c_dp_phase_even4=TRUE can not truely be modeled from the outside in this tb
+ dp_clk <= dp_clk_vec(0) when c_dp_phase_even4 = true else dp_clk_vec(2);
--dp_clk <= dp_clk_vec(0);
-- Create DP phase reference clock
diff --git a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd
index 83c07b0cabdc84ea95aed6bb499fe2e12803d7c5..c2ba133fc01d2e27febf59405d05d5850edd13ec 100644
--- a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd
@@ -32,29 +32,40 @@ use common_lib.tb_common_pkg.all;
entity tb_lvdsh_dd_wb4 is
generic (
- g_dclk_drift : time := 0 ps; -- 0 ps, use -2 ps or 2 ps to model the range of sample phase uncertainty by letting the sclk and dclk drift with respect to the dp_clk,
+ -- 0 ps, use -2 ps or 2 ps to model the range of sample phase uncertainty by letting the sclk and dclk drift with respect to the dp_clk,
+ g_dclk_drift : time := 0 ps;
-- use factor 2 value because of integer divide by 2 for rising and falling edge per sclk clock period.
- g_dclk_offon : boolean := true; -- when TRUE switch the dclk off-on periodically, to model ADU not present or ADU restart or ADU replaced
- g_in_phase : natural := 1 -- 0:3
+ -- when TRUE switch the dclk off-on periodically, to model ADU not present or ADU restart or ADU replaced
+ g_dclk_offon : boolean := true;
+ -- 0:3
+ g_in_phase : natural := 1
);
end tb_lvdsh_dd_wb4;
architecture tb of tb_lvdsh_dd_wb4 is
constant c_sim : boolean := true;
- constant c_tb_duration : natural := sel_a_b(g_dclk_drift /= 0 ps or g_dclk_offon = true, 1000, 10); -- nof tb intervals for tb duration
- constant c_tb_init : natural := sel_a_b(g_dclk_drift /= 0 ps or g_dclk_offon = true, 50, 5); -- nof tb intervals for tb init before verify_en
- constant c_interval : natural := 180; -- some unit tb interval
+ -- nof tb intervals for tb duration
+ constant c_tb_duration : natural := sel_a_b(g_dclk_drift /= 0 ps or g_dclk_offon = true, 1000, 10);
+ -- nof tb intervals for tb init before verify_en
+ constant c_tb_init : natural := sel_a_b(g_dclk_drift /= 0 ps or g_dclk_offon = true, 50, 5);
+ -- some unit tb interval
+ constant c_interval : natural := 180;
constant c_offon_interval : natural := c_interval * c_tb_duration / 13;
constant c_dd_factor : natural := 2;
constant c_rx_factor : natural := 2;
constant c_wb_factor : natural := c_dd_factor * c_rx_factor;
- constant c_clk_factor : natural := 100; -- slow down dclk to improve modelling dclk phase uncertainy with g_dclk_drift, which is minimal 2 ps
-
- constant c_sclk_period : time := c_clk_factor * 1.25 ns + g_dclk_drift; -- 800 MHz single data rate ADC sample clock with optional drift
- constant c_dp_sclk_period : time := c_clk_factor * 1.25 ns; -- 800 MHz sample clock for dp_sample_dat monitor
- constant c_dp_clk_period : time := c_clk_factor * 5 ns; -- 200 MHz data clock for Data Path processing
- constant c_dp_clk_delay : time := (0.0 + 0.05) * c_dp_clk_period; -- = 0 degrees
+ -- slow down dclk to improve modelling dclk phase uncertainy with g_dclk_drift, which is minimal 2 ps
+ constant c_clk_factor : natural := 100;
+
+ -- 800 MHz single data rate ADC sample clock with optional drift
+ constant c_sclk_period : time := c_clk_factor * 1.25 ns + g_dclk_drift;
+ -- 800 MHz sample clock for dp_sample_dat monitor
+ constant c_dp_sclk_period : time := c_clk_factor * 1.25 ns;
+ -- 200 MHz data clock for Data Path processing
+ constant c_dp_clk_period : time := c_clk_factor * 5 ns;
+ -- = 0 degrees
+ constant c_dp_clk_delay : time := (0.0 + 0.05) * c_dp_clk_period;
--CONSTANT c_dp_clk_delay : TIME := (0.125 + 0.05)*c_dp_clk_period; -- = 45 degrees
--CONSTANT c_dp_clk_delay : TIME := (0.25 + 0.05)*c_dp_clk_period; -- = 90 degrees
--CONSTANT c_dp_clk_delay : TIME := (0.375 + 0.05)*c_dp_clk_period; -- = 135 degrees
@@ -97,7 +108,8 @@ architecture tb of tb_lvdsh_dd_wb4 is
signal prev_dp_sample_dat : std_logic_vector(c_in_dat_w - 1 downto 0);
signal dp_sync_phase : natural;
- signal dp_status : std_logic_vector(c_word_w - 1 downto 0); -- extra status information for debug
+ -- extra status information for debug
+ signal dp_status : std_logic_vector(c_word_w - 1 downto 0);
signal dp_locked : std_logic;
signal dp_stable : std_logic;
signal dp_stable_ack : std_logic;
diff --git a/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd b/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd
index e3afe02e4dd069485bda88d42e5aa2c83254ca63..b823fcb1e046242ec26e7be370f92106f793355c 100644
--- a/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd
@@ -47,20 +47,27 @@ architecture tb of tb_mms_aduh_quad is
-- rx_factor : NATURAL; -- = 2
-- deskew : t_c_aduh_delays; -- = (0, 0, (OTHERS=>0), (OTHERS=>0), (OTHERS=>0), (OTHERS=>0)) -- clock: a, b, data: a, b, c, d
--END RECORD;
- constant c_ai : t_c_aduh_dd_ai := c_aduh_dd_ai; -- use defaults
+ -- use defaults
+ constant c_ai : t_c_aduh_dd_ai := c_aduh_dd_ai;
- constant c_dp_factor : natural := c_ai.rx_factor * c_ai.dd_factor; -- = 4 = 2 * 2
+ -- = 4 = 2 * 2
+ constant c_dp_factor : natural := c_ai.rx_factor * c_ai.dd_factor;
- constant c_sample_period : time := 1250 ps; -- 800 MTps
- constant c_dp_clk_period : time := c_sample_period * c_dp_factor; -- 200 MHz
- constant c_mm_clk_period : time := 20 ns; -- 50 MHz
+ -- 800 MTps
+ constant c_sample_period : time := 1250 ps;
+ -- 200 MHz
+ constant c_dp_clk_period : time := c_sample_period * c_dp_factor;
+ -- 50 MHz
+ constant c_mm_clk_period : time := 20 ns;
constant c_aduh_verify_val_bi : natural := 12;
constant c_aduh_verify_res_hi : natural := 8;
constant c_aduh_verify_res_mask : natural := 2**(c_aduh_verify_res_hi + 1) - 1;
- constant c_dp_phs_clk_step : time := c_dp_clk_period / 32; -- the PLL can output clocks with phase shifts of 360/32 = 11.25 degrees
- constant c_dp_phs_clk_period : natural := 32; -- number of dp_clk periods per dp_phs_clk period
+ -- the PLL can output clocks with phase shifts of 360/32 = 11.25 degrees
+ constant c_dp_phs_clk_step : time := c_dp_clk_period / 32;
+ -- number of dp_clk periods per dp_phs_clk period
+ constant c_dp_phs_clk_period : natural := 32;
constant c_nof_dp_phs_clk : natural := 1;
procedure proc_verify_bist_expect_ok(aduh_a_verify, aduh_b_verify, aduh_c_verify, aduh_d_verify : std_logic_vector) is
@@ -90,16 +97,20 @@ architecture tb of tb_mms_aduh_quad is
signal tb_end : std_logic := '0';
-- Analogue
- signal SCLK : std_logic := '1'; -- central sample clock = 800 MHz
- signal DCLK_AB : std_logic; -- digital lvds clock = 400 MHz (DDR)
- signal DCLK_CD : std_logic; -- digital lvds clock = 400 MHz (DDR)
+ -- central sample clock = 800 MHz
+ signal SCLK : std_logic := '1';
+ -- digital lvds clock = 400 MHz (DDR)
+ signal DCLK_AB : std_logic;
+ -- digital lvds clock = 400 MHz (DDR)
+ signal DCLK_CD : std_logic;
signal DIG_A : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_B : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_C : std_logic_vector(c_ai.port_w - 1 downto 0);
signal DIG_D : std_logic_vector(c_ai.port_w - 1 downto 0);
-- Digital streaming
- signal dp_clk : std_logic := '1'; -- digital data path clock = 200 MHz (deser factor 4);
+ -- digital data path clock = 200 MHz (deser factor 4);
+ signal dp_clk : std_logic := '1';
signal dp_rst : std_logic;
signal dp_phs_cnt : natural := 0;
signal dp_phs_clk : std_logic := '1';
@@ -108,7 +119,8 @@ architecture tb of tb_mms_aduh_quad is
signal aduh_sosi_arr : t_dp_sosi_arr(0 to c_ai.nof_sp - 1);
-- MM Interface
- signal mm_clk : std_logic := '1'; -- MM control clock = 50 MHz
+ -- MM control clock = 50 MHz
+ signal mm_clk : std_logic := '1';
signal mm_rst : std_logic;
-- MM aduh quad register
@@ -119,7 +131,8 @@ architecture tb of tb_mms_aduh_quad is
signal aduh_c_verify : std_logic_vector(c_word_w - 1 downto 0);
signal aduh_d_verify : std_logic_vector(c_word_w - 1 downto 0);
- signal reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ADUH locked status and pattern verify for two half ADUs so 4 ADC inputs A, B, C and D
+ -- ADUH locked status and pattern verify for two half ADUs so 4 ADC inputs A, B, C and D
+ signal reg_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_miso : t_mem_miso;
signal test_pattern_en : std_logic;
diff --git a/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd b/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd
index 17cf28b17d78790290144ff56dc9bce813acbad8..83594d78b03425ba7377972dbf3a0d2f4ccdde69 100644
--- a/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd
@@ -28,7 +28,8 @@ end tb_tb_lvdsh_dd_phs4;
architecture tb of tb_tb_lvdsh_dd_phs4 is
constant c_dp_phs_clk_period : natural := 32;
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 3
-- > run -all
diff --git a/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd b/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd
index b8a9829f2f99b0a06dca746401372971382b5306..dba3e0b364e4e67e2e0a44937fe22dbda96d16af 100644
--- a/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd
@@ -27,7 +27,8 @@ entity tb_tb_lvdsh_dd_wb4 is
end tb_tb_lvdsh_dd_wb4;
architecture tb of tb_tb_lvdsh_dd_wb4 is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- > as 3
-- > run -all
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 354f571a7053fc7debabc577e870572ad5762111..51cbed67c61cb1c83d79a2663bfc64e2f5b913a0 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -154,15 +154,20 @@ use dp_lib.dp_stream_pkg.all;
entity io_ddr is
generic(
- g_sim_model : boolean := false; -- when FALSE use IP and external DDR3 model, else when TRUE: use fast behavioural model, requires no external memory (uses memory array).
+ -- when FALSE use IP and external DDR3 model, else when TRUE: use fast behavioural model, requires no external memory (uses memory array).
+ g_sim_model : boolean := false;
g_technology : natural := c_tech_select_default;
g_tech_ddr : t_c_tech_ddr;
- g_cross_domain_dvr_ctlr : boolean := true; -- use TRUE when MM clock is used for the access control, use FALSE when ctlr_clk_in=ctlr_clk_out is used to avoid extra latency
+ -- use TRUE when MM clock is used for the access control, use FALSE when ctlr_clk_in=ctlr_clk_out is used to avoid extra latency
+ g_cross_domain_dvr_ctlr : boolean := true;
g_wr_data_w : natural := 32;
- g_wr_fifo_depth : natural := 256; -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
- g_rd_fifo_depth : natural := 256; -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ g_wr_fifo_depth : natural := 256;
+ -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ g_rd_fifo_depth : natural := 256;
g_rd_data_w : natural := 32;
- g_wr_flush_mode : string := "VAL"; -- "VAL", "SOP", "SYN"
+ -- "VAL", "SOP", "SYN"
+ g_wr_flush_mode : string := "VAL";
g_wr_flush_use_channel : boolean := false;
g_wr_flush_start_channel : natural := 0;
g_wr_flush_nof_channels : positive := 1
@@ -176,15 +181,18 @@ entity io_ddr is
ctlr_clk_out : out std_logic;
ctlr_rst_out : out std_logic;
- ctlr_clk_in : in std_logic; -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in : in std_logic; -- connect ctlr_rst_out to ctlr_rst_in at top level
+ -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_clk_in : in std_logic;
+ -- connect ctlr_rst_out to ctlr_rst_in at top level
+ ctlr_rst_in : in std_logic;
-- MM clock + reset
mm_rst : in std_logic := '1';
mm_clk : in std_logic := '0';
-- MM interface
- reg_io_ddr_mosi : in t_mem_mosi := c_mem_mosi_rst; -- register for DDR controller status info
+ -- register for DDR controller status info
+ reg_io_ddr_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_io_ddr_miso : out t_mem_miso;
state_vec : out std_logic_vector(1 downto 0);
@@ -199,7 +207,8 @@ entity io_ddr is
wr_clk : in std_logic;
wr_rst : in std_logic;
- wr_fifo_usedw : out std_logic_vector(ceil_log2(g_wr_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr) / g_wr_data_w) ) - 1 downto 0); -- for monitoring purposes
+ -- for monitoring purposes
+ wr_fifo_usedw : out std_logic_vector(ceil_log2(g_wr_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr) / g_wr_data_w) ) - 1 downto 0);
wr_sosi : in t_dp_sosi;
wr_siso : out t_dp_siso;
ctlr_wr_flush_en_o : out std_logic;
@@ -232,18 +241,25 @@ architecture str of io_ddr is
constant c_wr_use_ctrl : boolean := sel_a_b(g_wr_flush_mode = "SOP", true, false);
constant c_wr_fifo_use_ctrl : boolean := c_wr_use_sync or c_wr_use_ctrl;
- constant c_ddr_nofbytes_w : natural := func_tech_ddr_module_nofbytes_w(g_tech_ddr); -- log2(number of bytes)
- constant c_ddr_gigabytes : integer := func_tech_ddr_module_gigabytes(g_tech_ddr); -- units value GiByte when value > 1 or 2**value GiByte when value < 0
- constant c_ctlr_nof_bytes_per_word : natural := func_tech_ddr_ctlr_ip_data_w(g_tech_ddr) / c_byte_w; -- unit byte
+ -- log2(number of bytes)
+ constant c_ddr_nofbytes_w : natural := func_tech_ddr_module_nofbytes_w(g_tech_ddr);
+ -- units value GiByte when value > 1 or 2**value GiByte when value < 0
+ constant c_ddr_gigabytes : integer := func_tech_ddr_module_gigabytes(g_tech_ddr);
+ -- unit byte
+ constant c_ctlr_nof_bytes_per_word : natural := func_tech_ddr_ctlr_ip_data_w(g_tech_ddr) / c_byte_w;
constant c_ctlr_address_w : natural := func_tech_ddr_ctlr_address_w(g_tech_ddr);
constant c_ctlr_data_w : natural := func_tech_ddr_ctlr_data_w(g_tech_ddr);
- constant c_wr_fifo_depth : natural := g_wr_fifo_depth * (c_ctlr_data_w / g_wr_data_w); -- get FIFO depth at write side
+ -- get FIFO depth at write side
+ constant c_wr_fifo_depth : natural := g_wr_fifo_depth * (c_ctlr_data_w / g_wr_data_w);
- constant c_wr_fifo_af_margin : natural := 8 + 1; -- use 8 (>= 4 default) to be safe and use +1 to compensate for latency introduced by registering wr_siso.ready due to RL=0
+ -- use 8 (>= 4 default) to be safe and use +1 to compensate for latency introduced by registering wr_siso.ready due to RL=0
+ constant c_wr_fifo_af_margin : natural := 8 + 1;
- constant c_nof_rd_bursts_max : natural := sel_a_b(g_tech_ddr.name = "DDR3", 1, 3); -- max number of rd bursts in queue, derived empirically from simulation, seems fixed 1 for DDR3 and seems to match (g_tech_ddr.command_queue_depth-1)/2 for DDR4
- constant c_rd_fifo_af_margin : natural := 8 + c_nof_rd_bursts_max * g_tech_ddr.maxburstsize; -- use 8 (>= 4 default) to be safe and use sufficient extra margin to fit one or more rd burst accesses of g_tech_ddr.maxburstsize each
+ -- max number of rd bursts in queue, derived empirically from simulation, seems fixed 1 for DDR3 and seems to match (g_tech_ddr.command_queue_depth-1)/2 for DDR4
+ constant c_nof_rd_bursts_max : natural := sel_a_b(g_tech_ddr.name = "DDR3", 1, 3);
+ -- use 8 (>= 4 default) to be safe and use sufficient extra margin to fit one or more rd burst accesses of g_tech_ddr.maxburstsize each
+ constant c_rd_fifo_af_margin : natural := 8 + c_nof_rd_bursts_max * g_tech_ddr.maxburstsize;
constant c_mem_reg_adr_w : natural := 2;
constant c_mem_reg_dat_w : natural := 32;
@@ -265,15 +281,18 @@ architecture str of io_ddr is
signal ctlr_wr_flush_snk_in : t_dp_sosi := c_dp_sosi_rst;
- signal ctlr_wr_snk_out : t_dp_siso := c_dp_siso_rdy; -- default xon='1'
+ -- default xon='1'
+ signal ctlr_wr_snk_out : t_dp_siso := c_dp_siso_rdy;
signal ctlr_wr_snk_in : t_dp_sosi := c_dp_sosi_rst;
signal ctlr_rd_src_in : t_dp_siso;
signal ctlr_rd_src_out : t_dp_sosi := c_dp_sosi_rst;
-- Monitor only
- signal ctlr_wr_fifo_usedw : std_logic_vector(ceil_log2(g_wr_fifo_depth) - 1 downto 0); -- read side depth of the write FIFO
- signal ctlr_rd_fifo_usedw : std_logic_vector(ceil_log2(g_rd_fifo_depth) - 1 downto 0); -- write side depth of the read FIFO
+ -- read side depth of the write FIFO
+ signal ctlr_wr_fifo_usedw : std_logic_vector(ceil_log2(g_wr_fifo_depth) - 1 downto 0);
+ -- write side depth of the read FIFO
+ signal ctlr_rd_fifo_usedw : std_logic_vector(ceil_log2(g_rd_fifo_depth) - 1 downto 0);
signal reg_rd_arr : std_logic_vector(c_mem_reg_io_ddr.nof_dat - 1 downto 0);
signal wr_fifo_full : std_logic;
signal wr_fifo_full_reg : std_logic;
@@ -357,8 +376,10 @@ begin
u_dp_flush : entity dp_lib.dp_flush
generic map (
g_ready_latency => 0,
- g_framed_xon => c_wr_fifo_use_ctrl, -- stop flushing when flush_en is low and a sop (or sync via sop) has arrived
- g_framed_xoff => false -- immediately start flushing when flush_en goes high
+ -- stop flushing when flush_en is low and a sop (or sync via sop) has arrived
+ g_framed_xon => c_wr_fifo_use_ctrl,
+ -- immediately start flushing when flush_en goes high
+ g_framed_xoff => false
)
port map (
rst => ctlr_rst_in,
@@ -415,7 +436,8 @@ begin
g_rd_data_w => g_rd_data_w,
g_use_ctrl => false,
g_wr_fifo_size => g_rd_fifo_depth,
- g_wr_fifo_af_margin => c_rd_fifo_af_margin, -- >=4 (required by dp_fifo)
+ -- >=4 (required by dp_fifo)
+ g_wr_fifo_af_margin => c_rd_fifo_af_margin,
g_rd_fifo_rl => 1
)
port map (
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd b/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
index f6d57ea25d3390821ac3d43f6829d5a24689f686..342ad34bdbe9839c137bd79634c3b37ad77e3d9c 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
@@ -103,22 +103,27 @@ architecture str of io_ddr_driver is
signal burstbegin : std_logic;
signal burstbegin_evt : std_logic;
- signal burst_size : positive range 1 to 2**g_tech_ddr.maxburstsize_w - 1 := 1; -- burst size >= 1
+ -- burst size >= 1
+ signal burst_size : positive range 1 to 2**g_tech_ddr.maxburstsize_w - 1 := 1;
signal nxt_burst_size : positive;
- signal burst_wr_cnt : natural range 0 to 2**g_tech_ddr.maxburstsize_w - 1 := 0; -- count down from burst_size to 0
+ -- count down from burst_size to 0
+ signal burst_wr_cnt : natural range 0 to 2**g_tech_ddr.maxburstsize_w - 1 := 0;
signal nxt_burst_wr_cnt : natural range 0 to 2**g_tech_ddr.maxburstsize_w - 1;
signal cur_address : std_logic_vector(c_ctlr_address_w - 1 downto 0) := (others => '0');
signal nxt_cur_address : std_logic_vector(c_ctlr_address_w - 1 downto 0);
- signal address_cnt : std_logic_vector(c_ctlr_address_w - 1 downto 0) := (others => '0'); -- count down nof addresses = nof ctlr data words
+ -- count down nof addresses = nof ctlr data words
+ signal address_cnt : std_logic_vector(c_ctlr_address_w - 1 downto 0) := (others => '0');
signal nxt_address_cnt : std_logic_vector(c_ctlr_address_w - 1 downto 0);
signal address_cnt_is_0 : std_logic;
signal nxt_address_cnt_is_0 : std_logic;
begin
-- Map original dvr interface signals to t_mem_ctlr_mosi/miso
- dvr_miso.done <= dvr_done; -- Requested wr or rd sequence is done
+ -- Requested wr or rd sequence is done
+ dvr_miso.done <= dvr_done;
dvr_en <= dvr_mosi.burstbegin;
- dvr_wr_not_rd <= dvr_mosi.wr; -- No need to use dvr_mosi.rd
+ -- No need to use dvr_mosi.rd
+ dvr_wr_not_rd <= dvr_mosi.wr;
dvr_start_address <= dvr_mosi.address(c_ctlr_address_w - 1 downto 0);
dvr_nof_data <= dvr_mosi.burstsize(c_ctlr_address_w - 1 downto 0);
@@ -167,7 +172,8 @@ begin
rd_src_out.valid <= ctlr_miso.rdval;
rd_src_out.data <= RESIZE_DP_DATA(ctlr_miso.rddata);
- wr_snk_out.xon <= ctlr_miso.done; -- xon when controller init is done so ready for access
+ -- xon when controller init is done so ready for access
+ wr_snk_out.xon <= ctlr_miso.done;
p_state : process(prev_state, state,
dvr_en, dvr_wr_not_rd, dvr_start_address, dvr_nof_data,
@@ -175,13 +181,17 @@ begin
burstbegin_evt, burst_size, burst_wr_cnt, cur_address, address_cnt, address_cnt_is_0)
begin
nxt_state <= state;
- ctlr_mosi.address <= RESIZE_MEM_CTLR_ADDRESS(cur_address); -- no need to hold during burst, because the Avalon constantBurstBehaviour=FALSE (default) of the DDR IP slave
+ -- no need to hold during burst, because the Avalon constantBurstBehaviour=FALSE (default) of the DDR IP slave
+ ctlr_mosi.address <= RESIZE_MEM_CTLR_ADDRESS(cur_address);
ctlr_mosi.wrdata <= RESIZE_MEM_CTLR_DATA(wr_snk_in.data);
ctlr_mosi.wr <= '0';
ctlr_mosi.rd <= '0';
- burstbegin <= '0'; -- use burstbegin and burstbegin_evt to assert ctrl_mosi.burstbegin for one clock cylce only, independent of ctrl_miso.wait_request_n
- ctlr_mosi.burstbegin <= burstbegin_evt; -- only used for legacy DDR controllers, because the controller can derive it internally by counting wr and rd accesses
- ctlr_mosi.burstsize <= TO_MEM_CTLR_BURSTSIZE(burst_size); -- burstsize >= 1,
+ -- use burstbegin and burstbegin_evt to assert ctrl_mosi.burstbegin for one clock cylce only, independent of ctrl_miso.wait_request_n
+ burstbegin <= '0';
+ -- only used for legacy DDR controllers, because the controller can derive it internally by counting wr and rd accesses
+ ctlr_mosi.burstbegin <= burstbegin_evt;
+ -- burstsize >= 1,
+ ctlr_mosi.burstsize <= TO_MEM_CTLR_BURSTSIZE(burst_size);
-- no need to hold during burst, because the Avalon constantBurstBehaviour=FALSE (default) of the DDR IP slave
wr_snk_out.ready <= '0';
nxt_dvr_done <= '0';
@@ -191,25 +201,33 @@ begin
case state is
- when s_wr_burst => -- Performs the rest of burst when burst_size > 1
- if wr_snk_in.valid = '1' then -- it is allowed that valid is not always active during a burst
+ -- Performs the rest of burst when burst_size > 1
+ when s_wr_burst =>
+ -- it is allowed that valid is not always active during a burst
+ if wr_snk_in.valid = '1' then
ctlr_mosi.wr <= '1';
if ctlr_miso.waitrequest_n = '1' then
- wr_snk_out.ready <= '1'; -- wr side uses latency of 0, so wr_snk_out.ready<='1' acknowledges a successful write request.
+ -- wr side uses latency of 0, so wr_snk_out.ready<='1' acknowledges a successful write request.
+ wr_snk_out.ready <= '1';
nxt_burst_wr_cnt <= burst_wr_cnt - 1;
- if burst_wr_cnt = 1 then -- check for the last cycle of this burst sequence
- nxt_state <= s_wr_request; -- initiate a new wr burst or goto idle via the wr_request state, simulation shows going directly idle by checking address_cnt_is_0 here does not save a cycle
+ -- check for the last cycle of this burst sequence
+ if burst_wr_cnt = 1 then
+ -- initiate a new wr burst or goto idle via the wr_request state, simulation shows going directly idle by checking address_cnt_is_0 here does not save a cycle
+ nxt_state <= s_wr_request;
end if;
end if;
end if;
- when s_wr_request => -- Performs 1 write access and goes into s_wr_burst when requested burst_size >1
- if address_cnt_is_0 = '1' then -- end address reached
+ -- Performs 1 write access and goes into s_wr_burst when requested burst_size >1
+ when s_wr_request =>
+ -- end address reached
+ if address_cnt_is_0 = '1' then
nxt_dvr_done <= '1';
nxt_state <= s_idle;
elsif wr_snk_in.valid = '1' then
ctlr_mosi.wr <= '1';
- burstbegin <= '1'; -- assert ctlr_mosi.burstbegin for one clock cycle only
+ -- assert ctlr_mosi.burstbegin for one clock cycle only
+ burstbegin <= '1';
if ctlr_miso.waitrequest_n = '1' then
-- Always perform 1st write here
wr_snk_out.ready <= '1';
@@ -219,18 +237,23 @@ begin
-- Return for next wr request or perform any remaining writes in this burst
nxt_state <= s_wait;
if burst_size > 1 then
- nxt_state <= s_wr_burst; -- first burst wr cycle is done here, the rest are done in s_wr_burst
+ -- first burst wr cycle is done here, the rest are done in s_wr_burst
+ nxt_state <= s_wr_burst;
end if;
end if;
end if;
- when s_rd_request => -- Posts a read request for a burst (1...g_tech_ddr.maxburstsize)
- if address_cnt_is_0 = '1' then -- end address reached
+ -- Posts a read request for a burst (1...g_tech_ddr.maxburstsize)
+ when s_rd_request =>
+ -- end address reached
+ if address_cnt_is_0 = '1' then
nxt_dvr_done <= '1';
nxt_state <= s_idle;
- elsif rd_src_in.ready = '1' then -- the external FIFO uses almost full level assert its snk_out.ready and can then still accept the maximum rd burst of words
+ -- the external FIFO uses almost full level assert its snk_out.ready and can then still accept the maximum rd burst of words
+ elsif rd_src_in.ready = '1' then
ctlr_mosi.rd <= '1';
- burstbegin <= '1'; -- assert ctlr_mosi.burstbegin for one clock cycle only
+ -- assert ctlr_mosi.burstbegin for one clock cycle only
+ burstbegin <= '1';
if ctlr_miso.waitrequest_n = '1' then
nxt_cur_address <= INCR_UVEC(cur_address, burst_size);
nxt_address_cnt <= INCR_UVEC(address_cnt, -burst_size);
@@ -242,9 +265,12 @@ begin
-- In this state address_cnt is valid and in the next state burst_size (that depends on address_cnt) will be valid.
-- Therefore this wait state is inserted between any requests.
when s_wait =>
- if prev_state = s_wr_request then nxt_state <= s_wr_request; end if; -- between wr-wr burst requests
- if prev_state = s_rd_request then nxt_state <= s_rd_request; end if; -- between rd-rd burst requests
- if prev_state = s_idle then -- between wr and rd accesses
+ -- between wr-wr burst requests
+ if prev_state = s_wr_request then nxt_state <= s_wr_request; end if;
+ -- between rd-rd burst requests
+ if prev_state = s_rd_request then nxt_state <= s_rd_request; end if;
+ -- between wr and rd accesses
+ if prev_state = s_idle then
if dvr_wr_not_rd = '1' then
nxt_state <= s_wr_request;
else
@@ -256,16 +282,19 @@ begin
nxt_cur_address <= dvr_start_address;
nxt_address_cnt <= dvr_nof_data;
nxt_burst_wr_cnt <= 0;
- nxt_dvr_done <= '1'; -- assert dvr_done after s_init or keep it asserted after a finished access
+ -- assert dvr_done after s_init or keep it asserted after a finished access
+ nxt_dvr_done <= '1';
if dvr_en = '1' then
nxt_dvr_done <= '0';
nxt_state <= s_wait;
end if;
- when others => -- s_init
+ -- s_init
+ when others =>
nxt_dvr_done <= '0';
if ctlr_miso.done = '1' then
- nxt_state <= s_idle; -- and assert dvr_done when in s_idle to indicate ctlr_miso.done
+ -- and assert dvr_done when in s_idle to indicate ctlr_miso.done
+ nxt_state <= s_idle;
end if;
end case;
end process;
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
index 5300dd78d81f2e32ff1c8695bca041c463c25c64..90bc9e7ce6bf8ed22ef7a9825d25b38f72a04e1c 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
@@ -43,7 +43,8 @@ use dp_lib.dp_stream_pkg.all;
entity io_ddr_driver_flush_ctrl is
generic (
- g_mode : string := "VAL"; -- "VAL", "SOP", "SYN"
+ -- "VAL", "SOP", "SYN"
+ g_mode : string := "VAL";
g_use_channel : boolean := false;
g_start_channel : natural := 0;
g_nof_channels : positive := 1
@@ -97,8 +98,10 @@ begin
p_reg : process(rst, clk)
begin
if rst = '1' then
- state <= s_flush; -- default start in flush mode after power up,
- ctlr_wr_flush_en <= '1'; -- so default write flush is enabled
+ -- default start in flush mode after power up,
+ state <= s_flush;
+ -- so default write flush is enabled
+ ctlr_wr_flush_en <= '1';
elsif rising_edge(clk) then
state <= nxt_state;
ctlr_wr_flush_en <= nxt_ctlr_wr_flush_en;
@@ -122,10 +125,12 @@ begin
if dvr_en = '1' and dvr_wr_not_rd = '1' then
nxt_state <= s_stop;
end if;
- when others => -- s_stop
+ -- s_stop
+ when others =>
state_vec <= TO_UVEC(3, 2);
nxt_ctlr_wr_flush_en <= '1';
- if flush_dis = '1' then -- flush_dis comes from sosi control (valid, sop or sync) from look ahead (RL=0) write FIFO
+ -- flush_dis comes from sosi control (valid, sop or sync) from look ahead (RL=0) write FIFO
+ if flush_dis = '1' then
nxt_ctlr_wr_flush_en <= '0';
nxt_state <= s_idle;
end if;
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd b/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd
index c86a29d671dca2f7c9d94dbf23284a47054fda00..092e57d633217e379d75ab7d74e61409ac349504 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd
@@ -58,12 +58,16 @@ use diag_lib.diag_pkg.all;
entity io_ddr_reg is
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
dvr_miso : in t_mem_ctlr_miso;
@@ -74,7 +78,8 @@ end io_ddr_reg;
architecture rtl of io_ddr_reg is
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(8),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 8,
init_sl => '0');
@@ -108,29 +113,37 @@ begin
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Write Block Sync
when 0 =>
- i_dvr_mosi.burstbegin <= sla_in.wrdata(0); -- default to '0' so MM write '1' will yield a pulse of one mm_clk clock cycle
+ -- default to '0' so MM write '1' will yield a pulse of one mm_clk clock cycle
+ i_dvr_mosi.burstbegin <= sla_in.wrdata(0);
when 1 =>
- i_dvr_mosi.wr <= sla_in.wrdata(0); -- = wr_not_rd, so no need to control i_dvr_mosi.rd
+ -- = wr_not_rd, so no need to control i_dvr_mosi.rd
+ i_dvr_mosi.wr <= sla_in.wrdata(0);
when 5 =>
i_dvr_mosi.address <= sla_in.wrdata(c_mem_ctlr_address_w - 1 downto 0);
when 6 =>
i_dvr_mosi.burstsize <= sla_in.wrdata(c_mem_ctlr_burstsize_w - 1 downto 0);
when 7 =>
i_dvr_mosi.flush <= sla_in.wrdata(0);
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read Block Sync
when 2 =>
- sla_out.rddata(0) <= dvr_miso.done; -- read only
+ -- read only
+ sla_out.rddata(0) <= dvr_miso.done;
when 7 =>
- sla_out.rddata(0) <= i_dvr_mosi.flush; -- readback
- when others => null; -- unused MM addresses
+ -- readback
+ sla_out.rddata(0) <= i_dvr_mosi.flush;
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd b/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
index b2d2043afdd1c1fef515e5f5d9250e75369cd64f..608d266847c707a4935abdf8375536d94ca8fa66 100644
--- a/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
@@ -34,10 +34,13 @@ entity mms_io_ddr is
g_technology : natural := c_tech_select_default;
g_tech_ddr : t_c_tech_ddr;
g_wr_data_w : natural := 32;
- g_wr_fifo_depth : natural := 256; -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
- g_rd_fifo_depth : natural := 256; -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ g_wr_fifo_depth : natural := 256;
+ -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ g_rd_fifo_depth : natural := 256;
g_rd_data_w : natural := 32;
- g_wr_flush_mode : string := "VAL"; -- "VAL", "SOP", "SYN"
+ -- "VAL", "SOP", "SYN"
+ g_wr_flush_mode : string := "VAL";
g_wr_flush_use_channel : boolean := false;
g_wr_flush_start_channel : natural := 0;
g_wr_flush_nof_channels : positive := 1
@@ -51,22 +54,26 @@ entity mms_io_ddr is
ctlr_clk_out : out std_logic;
ctlr_rst_out : out std_logic;
- ctlr_clk_in : in std_logic; -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in : in std_logic; -- connect ctlr_rst_out to ctlr_rst_in at top level
+ -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_clk_in : in std_logic;
+ -- connect ctlr_rst_out to ctlr_rst_in at top level
+ ctlr_rst_in : in std_logic;
-- MM clock + reset
mm_rst : in std_logic := '1';
mm_clk : in std_logic := '0';
-- MM interface
- reg_io_ddr_mosi : in t_mem_mosi := c_mem_mosi_rst; -- register for DDR controller status info
+ -- register for DDR controller status info
+ reg_io_ddr_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_io_ddr_miso : out t_mem_miso;
-- Write FIFO clock domain
wr_clk : in std_logic;
wr_rst : in std_logic;
- wr_fifo_usedw : out std_logic_vector(ceil_log2(g_wr_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr) / g_wr_data_w) ) - 1 downto 0); -- for monitoring purposes
+ -- for monitoring purposes
+ wr_fifo_usedw : out std_logic_vector(ceil_log2(g_wr_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr) / g_wr_data_w) ) - 1 downto 0);
wr_sosi : in t_dp_sosi;
wr_siso : out t_dp_siso;
@@ -119,7 +126,8 @@ begin
g_sim_model => g_sim_model,
g_technology => g_technology,
g_tech_ddr => g_tech_ddr,
- g_cross_domain_dvr_ctlr => true, -- mm_dvr_mosi from io_ddr_reg is in mm_clk domain and needs be crossed to the ctlr_clk_in domain by io_ddr_cross_domain in io_ddr
+ -- mm_dvr_mosi from io_ddr_reg is in mm_clk domain and needs be crossed to the ctlr_clk_in domain by io_ddr_cross_domain in io_ddr
+ g_cross_domain_dvr_ctlr => true,
g_wr_data_w => g_wr_data_w,
g_wr_fifo_depth => g_wr_fifo_depth,
g_rd_fifo_depth => g_rd_fifo_depth,
@@ -135,7 +143,8 @@ begin
ctlr_ref_rst => ctlr_ref_rst,
-- DDR controller clock domain
- ctlr_clk_out => ctlr_clk_out, -- output clock of the ddr controller is used as DP clk.
+ -- output clock of the ddr controller is used as DP clk.
+ ctlr_clk_out => ctlr_clk_out,
ctlr_rst_out => ctlr_rst_out,
ctlr_clk_in => ctlr_clk_in,
diff --git a/libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd b/libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd
index be2513f6b93f75347ec33acfea1a0e859227fcd5..d67446bb6ffe050e6bd6c815fe865fd92b468207 100644
--- a/libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd
+++ b/libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd
@@ -60,17 +60,22 @@ entity mms_io_ddr_diag is
g_sim_model_ddr : boolean := false;
g_technology : natural := c_tech_select_default;
- g_dp_data_w : natural := 32; -- DP data width, func_tech_ddr_ctlr_data_w(g_io_tech_ddr)/g_dp_data_w must be a power of 2 due to the mixed width FIFO
- g_dp_seq_dat_w : natural := 32; -- >= 1, test sequence data width. Choose g_dp_seq_dat_w <= g_dp_data_w. The seq data gets replicated to fill g_dp_data_w.
- g_dp_wr_fifo_depth : natural := 2048; -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) to make full use of M9K which have at least 256 words
- g_dp_rd_fifo_depth : natural := 2048; -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) or factors of 2 more to fit max number of read bursts
+ -- DP data width, func_tech_ddr_ctlr_data_w(g_io_tech_ddr)/g_dp_data_w must be a power of 2 due to the mixed width FIFO
+ g_dp_data_w : natural := 32;
+ -- >= 1, test sequence data width. Choose g_dp_seq_dat_w <= g_dp_data_w. The seq data gets replicated to fill g_dp_data_w.
+ g_dp_seq_dat_w : natural := 32;
+ -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) to make full use of M9K which have at least 256 words
+ g_dp_wr_fifo_depth : natural := 2048;
+ -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) or factors of 2 more to fit max number of read bursts
+ g_dp_rd_fifo_depth : natural := 2048;
-- IO_DDR
g_io_tech_ddr : t_c_tech_ddr;
-- DIAG data buffer
g_db_use_db : boolean := false;
- g_db_buf_nof_data : natural := 1024 -- nof words per data buffer
+ -- nof words per data buffer
+ g_db_buf_nof_data : natural := 1024
);
port (
---------------------------------------------------------------------------
@@ -79,7 +84,8 @@ entity mms_io_ddr_diag is
mm_rst : in std_logic;
mm_clk : in std_logic;
dp_rst : in std_logic;
- dp_clk : in std_logic; -- use alternative external clock or externally connect to ctlr_clk_out
+ -- use alternative external clock or externally connect to ctlr_clk_out
+ dp_clk : in std_logic;
---------------------------------------------------------------------------
-- IO_DDR
@@ -92,11 +98,14 @@ entity mms_io_ddr_diag is
ctlr_clk_out : out std_logic;
ctlr_rst_out : out std_logic;
- ctlr_clk_in : in std_logic; -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in : in std_logic; -- connect ctlr_rst_out to ctlr_rst_in at top level
+ -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_clk_in : in std_logic;
+ -- connect ctlr_rst_out to ctlr_rst_in at top level
+ ctlr_rst_in : in std_logic;
-- MM interface
- reg_io_ddr_mosi : in t_mem_mosi := c_mem_mosi_rst; -- register for DDR controller status info
+ -- register for DDR controller status info
+ reg_io_ddr_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_io_ddr_miso : out t_mem_miso;
-- Write / read FIFO status for monitoring purposes (in dp_clk domain)
@@ -121,32 +130,41 @@ entity mms_io_ddr_diag is
-- DIAG Tx seq
---------------------------------------------------------------------------
-- MM interface
- reg_tx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst; -- Tx seq control (one per stream because c_reg_tx_seq_broadcast=FALSE)
+ -- Tx seq control (one per stream because c_reg_tx_seq_broadcast=FALSE)
+ reg_tx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_tx_seq_miso : out t_mem_miso;
---------------------------------------------------------------------------
-- DIAG rx seq with optional data buffer
---------------------------------------------------------------------------
-- MM interface
- reg_data_buf_mosi : in t_mem_mosi := c_mem_mosi_rst; -- DB control register (one per stream)
+ -- DB control register (one per stream)
+ reg_data_buf_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_data_buf_miso : out t_mem_miso;
- ram_data_buf_mosi : in t_mem_mosi := c_mem_mosi_rst; -- DB buffer RAM (one per streams)
+ -- DB buffer RAM (one per streams)
+ ram_data_buf_mosi : in t_mem_mosi := c_mem_mosi_rst;
ram_data_buf_miso : out t_mem_miso;
- reg_rx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst; -- Rx seq control register (one per streams)
+ -- Rx seq control register (one per streams)
+ reg_rx_seq_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_rx_seq_miso : out t_mem_miso
);
end mms_io_ddr_diag;
architecture str of mms_io_ddr_diag is
- constant c_io_wr_fifo_depth : natural := (g_dp_wr_fifo_depth * g_dp_data_w) / func_tech_ddr_ctlr_data_w(g_io_tech_ddr); -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
- constant c_io_rd_fifo_depth : natural := (g_dp_rd_fifo_depth * g_dp_data_w) / func_tech_ddr_ctlr_data_w(g_io_tech_ddr); -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
-
- signal bg_siso_arr : t_dp_siso_arr(0 downto 0) := (others => c_dp_siso_rdy); -- Default xon='1'
- signal bg_sosi_arr : t_dp_sosi_arr(0 downto 0); -- Output SOSI that contains the waveform data
-
- signal db_siso_arr : t_dp_siso_arr(0 downto 0) := (others => c_dp_siso_rdy); -- Default ready='1'
+ -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ constant c_io_wr_fifo_depth : natural := (g_dp_wr_fifo_depth * g_dp_data_w) / func_tech_ddr_ctlr_data_w(g_io_tech_ddr);
+ -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ constant c_io_rd_fifo_depth : natural := (g_dp_rd_fifo_depth * g_dp_data_w) / func_tech_ddr_ctlr_data_w(g_io_tech_ddr);
+
+ -- Default xon='1'
+ signal bg_siso_arr : t_dp_siso_arr(0 downto 0) := (others => c_dp_siso_rdy);
+ -- Output SOSI that contains the waveform data
+ signal bg_sosi_arr : t_dp_sosi_arr(0 downto 0);
+
+ -- Default ready='1'
+ signal db_siso_arr : t_dp_siso_arr(0 downto 0) := (others => c_dp_siso_rdy);
signal db_sosi_arr : t_dp_sosi_arr(0 downto 0);
begin
------------------------------------------------------------------------------
@@ -259,10 +277,13 @@ begin
-- General
g_nof_streams => 1,
-- DB settings
- g_data_type => e_data, -- define the sosi field that gets stored: e_data=data, e_complex=im&re, e_real=re, e_imag=im,
- g_data_w => c_word_w, -- only capture the lowest c_word_w=32 bits of the g_dp_data_w
+ -- define the sosi field that gets stored: e_data=data, e_complex=im&re, e_real=re, e_imag=im,
+ g_data_type => e_data,
+ -- only capture the lowest c_word_w=32 bits of the g_dp_data_w
+ g_data_w => c_word_w,
g_buf_nof_data => g_db_buf_nof_data,
- g_buf_use_sync => false, -- when TRUE start filling the buffer at the in_sync, else after the last word was read,
+ -- when TRUE start filling the buffer at the in_sync, else after the last word was read,
+ g_buf_use_sync => false,
-- Rx_seq
g_seq_dat_w => g_dp_seq_dat_w
)
diff --git a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
index 912ae3b3eb5ccc6b9f54f6eea6ee3842351e523f..ccbbad3f55926b34038f785b931e9581eb1570f5 100644
--- a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
@@ -43,22 +43,33 @@ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_io_ddr is
generic (
- g_sim_model : boolean := true; -- FALSE;
+ -- FALSE;
+ g_sim_model : boolean := true;
g_technology : natural := c_tech_select_default;
g_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
--g_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
g_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_16g_1600m_64;
--g_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_16g_1600m_72_64;
- g_tb_end : boolean := true; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
- g_cross_domain_dvr_ctlr : boolean := true; -- when TRUE insert clock cross domain logic and also insert clock cross domain logic when g_dvr_clk_period/=c_ctlr_clk_period
- g_dvr_clk_period : time := 5 ns; -- 200 MHz
- g_dp_factor : natural := 4; -- 1 or power of 2, c_dp_data_w = c_ctlr_data_w / g_dp_factor
- g_block_len : natural := 100; -- block length for a DDR write access and read back access in number of c_ctlr_data_w words
- g_nof_block : natural := 2; -- number of blocks that will be written to DDR and readback from DDR
- g_nof_wr_per_block : natural := 1; -- number of write accesses per block
- g_nof_rd_per_block : natural := 1; -- number of read accesses per block
- g_nof_repeat : natural := 1; -- number of stimuli repeats with write flush after each repeat
- g_wr_flush_mode : string := "VAL" -- "VAL", "SOP", "SYN"
+ -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ g_tb_end : boolean := true;
+ -- when TRUE insert clock cross domain logic and also insert clock cross domain logic when g_dvr_clk_period/=c_ctlr_clk_period
+ g_cross_domain_dvr_ctlr : boolean := true;
+ -- 200 MHz
+ g_dvr_clk_period : time := 5 ns;
+ -- 1 or power of 2, c_dp_data_w = c_ctlr_data_w / g_dp_factor
+ g_dp_factor : natural := 4;
+ -- block length for a DDR write access and read back access in number of c_ctlr_data_w words
+ g_block_len : natural := 100;
+ -- number of blocks that will be written to DDR and readback from DDR
+ g_nof_block : natural := 2;
+ -- number of write accesses per block
+ g_nof_wr_per_block : natural := 1;
+ -- number of read accesses per block
+ g_nof_rd_per_block : natural := 1;
+ -- number of stimuli repeats with write flush after each repeat
+ g_nof_repeat : natural := 1;
+ -- "VAL", "SOP", "SYN"
+ g_wr_flush_mode : string := "VAL"
);
port (
tb_end : out std_logic
@@ -77,11 +88,16 @@ architecture str of tb_io_ddr is
constant c_exp_nofbytes_w : natural := func_tech_ddr_module_nofbytes_w(c_tech_ddr);
constant c_exp_nof_bytes_per_word : natural := func_tech_ddr_ctlr_ip_data_w(c_tech_ddr) / c_byte_w;
- constant c_dp_clk_period : time := 5 ns; -- 200 MHz
- constant c_mm_clk_period : time := 8 ns; -- 125 MHz
- constant c_ctlr_ref_clk_period : time := sel_a_b(g_sim_model, c_dp_clk_period, sel_a_b(c_tech_ddr.name = "DDR3", 5 ns, 40 ns)); -- 200 MHz for DDR3 on UniBoard and 25 MHz for DDR4 on UniBoard2, use dp clock for sim_model
- constant c_ctlr_clk_freq : natural := c_tech_ddr.mts / c_tech_ddr.rsl; -- 200 MHz
- constant c_ctlr_clk_period : time := (1000000 / c_ctlr_clk_freq) * 1 ps; -- 5000 ps
+ -- 200 MHz
+ constant c_dp_clk_period : time := 5 ns;
+ -- 125 MHz
+ constant c_mm_clk_period : time := 8 ns;
+ -- 200 MHz for DDR3 on UniBoard and 25 MHz for DDR4 on UniBoard2, use dp clock for sim_model
+ constant c_ctlr_ref_clk_period : time := sel_a_b(g_sim_model, c_dp_clk_period, sel_a_b(c_tech_ddr.name = "DDR3", 5 ns, 40 ns));
+ -- 200 MHz
+ constant c_ctlr_clk_freq : natural := c_tech_ddr.mts / c_tech_ddr.rsl;
+ -- 5000 ps
+ constant c_ctlr_clk_period : time := (1000000 / c_ctlr_clk_freq) * 1 ps;
constant c_cross_domain_dvr_ctlr : boolean := g_cross_domain_dvr_ctlr or g_dvr_clk_period /= c_ctlr_clk_period;
constant c_ctlr_address_w : natural := func_tech_ddr_ctlr_address_w(c_tech_ddr);
@@ -89,8 +105,10 @@ architecture str of tb_io_ddr is
constant c_dp_data_w : natural := c_ctlr_data_w / g_dp_factor;
- constant c_wr_fifo_depth : natural := 256; -- defined at DDR side of the FIFO
- constant c_rd_fifo_depth : natural := 256; -- defined at DDR side of the FIFO
+ -- defined at DDR side of the FIFO
+ constant c_wr_fifo_depth : natural := 256;
+ -- defined at DDR side of the FIFO
+ constant c_rd_fifo_depth : natural := 256;
-- Frame size for sop/eop
constant c_wr_frame_size : natural := 32;
@@ -168,7 +186,8 @@ architecture str of tb_io_ddr is
signal dbg_c_ctlr_wr_not_rd_arr : std_logic_vector(0 to c_nof_access - 1) := c_ctlr_wr_not_rd_arr;
signal dbg_c_tech_ddr : t_c_tech_ddr := c_tech_ddr;
- signal dbg_c_exp_gigabytes : integer := c_exp_gigabytes; -- = 0 for sim model, else nof GB
+ -- = 0 for sim model, else nof GB
+ signal dbg_c_exp_gigabytes : integer := c_exp_gigabytes;
signal dbg_c_exp_nofbytes_w : natural := c_exp_nofbytes_w;
signal ddr_gigabytes : integer;
signal dbg_c_exp_nof_bytes_per_word : natural := c_exp_nof_bytes_per_word;
@@ -322,9 +341,11 @@ begin
dvr_wr_flush_en <= '0';
-- Wait until the wr fifo has been flushed and the rd fifo has been read empty
- proc_common_wait_some_cycles(ctlr_clk, c_tech_ddr.command_queue_depth * c_tech_ddr.maxburstsize); -- rd FIFO may still get filled some more
+ -- rd FIFO may still get filled some more
+ proc_common_wait_some_cycles(ctlr_clk, c_tech_ddr.command_queue_depth * c_tech_ddr.maxburstsize);
proc_common_wait_some_cycles(ctlr_clk, largest(TO_UINT(wr_fifo_usedw) / g_dp_factor, TO_UINT(rd_fifo_usedw)));
- proc_common_wait_some_cycles(ctlr_clk, 10); -- some extra margin
+ -- some extra margin
+ proc_common_wait_some_cycles(ctlr_clk, 10);
assert unsigned(wr_fifo_usedw) < g_dp_factor report "[ERROR] Write FIFO is flushed but not empty!" severity FAILURE;
assert unsigned(rd_fifo_usedw) = 0 report "[ERROR] Read FIFO is not empty!" severity FAILURE;
@@ -427,9 +448,11 @@ begin
end process;
-- Map original dvr interface signals to t_mem_ctlr_mosi/miso
- dvr_done <= dvr_miso.done; -- Requested wr or rd sequence is done
+ -- Requested wr or rd sequence is done
+ dvr_done <= dvr_miso.done;
dvr_mosi.burstbegin <= dvr_en;
- dvr_mosi.wr <= dvr_wr_not_rd; -- No need to use dvr_mosi.rd
+ -- No need to use dvr_mosi.rd
+ dvr_mosi.wr <= dvr_wr_not_rd;
dvr_mosi.address <= RESIZE_MEM_CTLR_ADDRESS(dvr_start_address);
dvr_mosi.burstsize <= RESIZE_MEM_CTLR_BURSTSIZE(dvr_nof_data);
dvr_mosi.flush <= dvr_wr_flush_en;
@@ -441,8 +464,10 @@ begin
g_tech_ddr => c_tech_ddr,
g_cross_domain_dvr_ctlr => c_cross_domain_dvr_ctlr,
g_wr_data_w => c_dp_data_w,
- g_wr_fifo_depth => c_wr_fifo_depth, -- defined at DDR side of the FIFO.
- g_rd_fifo_depth => c_rd_fifo_depth, -- defined at DDR side of the FIFO.
+ -- defined at DDR side of the FIFO.
+ g_wr_fifo_depth => c_wr_fifo_depth,
+ -- defined at DDR side of the FIFO.
+ g_rd_fifo_depth => c_rd_fifo_depth,
g_rd_data_w => c_dp_data_w,
g_wr_flush_mode => g_wr_flush_mode,
g_wr_flush_use_channel => false,
@@ -458,7 +483,8 @@ begin
ctlr_clk_out => ctlr_clk,
ctlr_rst_out => ctlr_rst,
- ctlr_clk_in => ctlr_clk, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_clk_in => ctlr_clk,
ctlr_rst_in => ctlr_rst,
-- MM clock domain
diff --git a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
index 664d68451b79dc659ed4b483e4c3b1f15046c7b4..d952f8e30fe705dd4622ed2fb85586f4e6f333c2 100644
--- a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
@@ -41,11 +41,14 @@ architecture tb of tb_tb_io_ddr is
constant c_technology : natural := c_tech_select_default;
constant c_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
--CONSTANT c_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
- constant c_tech_ddr4 : t_c_tech_ddr := func_tech_sel_ddr(c_technology = c_tech_arria10_e1sg, c_tech_ddr4_4g_1600m, c_tech_ddr4_8g_1600m); -- use 4GB for unb2b, 8GB for unb2c
- constant c_tech_ddr : t_c_tech_ddr := func_tech_sel_ddr(c_technology, c_tech_ddr3, c_tech_ddr4); -- Select DDR3 or DDR4 dependent on the technology
+ -- use 4GB for unb2b, 8GB for unb2c
+ constant c_tech_ddr4 : t_c_tech_ddr := func_tech_sel_ddr(c_technology = c_tech_arria10_e1sg, c_tech_ddr4_4g_1600m, c_tech_ddr4_8g_1600m);
+ -- Select DDR3 or DDR4 dependent on the technology
+ constant c_tech_ddr : t_c_tech_ddr := func_tech_sel_ddr(c_technology, c_tech_ddr3, c_tech_ddr4);
constant c_tb_end_vec : std_logic_vector(15 downto 0) := (others => '1');
- signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ -- sufficiently long to fit all tb instances
+ signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec;
signal tb_end : std_logic := '0';
begin
-- g_sim_model : BOOLEAN := FALSE;
diff --git a/libraries/io/ddr3/src/vhdl/ddr3.vhd b/libraries/io/ddr3/src/vhdl/ddr3.vhd
index 0798866d0fb50015b3fad9619f1ba5f6c357993a..1c8595e167b145d86bedf6c834ef435a312d2e1d 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3.vhd
@@ -37,19 +37,29 @@ use work.ddr3_pkg.all;
entity ddr3 is
generic(
- g_phy : natural := 1; -- 0: ALTMEMPHY 1: UNIPHY_MASTER 2: UNIPHY_SLAVE
+ -- 0: ALTMEMPHY 1: UNIPHY_MASTER 2: UNIPHY_SLAVE
+ g_phy : natural := 1;
g_ddr : t_c_ddr3_phy;
- g_mts : natural := 800; -- Megatransfers per second
+ -- Megatransfers per second
+ g_mts : natural := 800;
g_wr_data_w : natural := c_ddr3_ctlr_data_w;
- g_wr_use_ctrl : boolean := false; -- TRUE to allow filling the WR FIFO (by disabling flush) after an EOP
- g_wr_fifo_depth : natural := 128; -- >=16 AND >c_ddr3_ctlr_maxburstsize , defined at read side of write FIFO.
- g_rd_fifo_depth : natural := 256; -- >=16 AND >c_ddr3_ctlr_maxburstsize > c_ddr3_ctrl_nof_latent_reads, defined at write side of read FIFO.
+ -- TRUE to allow filling the WR FIFO (by disabling flush) after an EOP
+ g_wr_use_ctrl : boolean := false;
+ -- >=16 AND >c_ddr3_ctlr_maxburstsize , defined at read side of write FIFO.
+ g_wr_fifo_depth : natural := 128;
+ -- >=16 AND >c_ddr3_ctlr_maxburstsize > c_ddr3_ctrl_nof_latent_reads, defined at write side of read FIFO.
+ g_rd_fifo_depth : natural := 256;
g_rd_data_w : natural := c_ddr3_ctlr_data_w;
- g_flush_wr_fifo : boolean := false; -- TRUE instantiates a dp_flush + controller to flush the write fifo when the driver is not ready to write
- g_flush_ext_ena : boolean := false; -- TRUE enables the external flush_ena signal and discards flushing when driver is not ready. FALSE enables flushing when driver is not ready
- g_flush_sop : boolean := false; -- When FALSE, flushing is stopped by valid data. When TRUE flushing is stopped by SOP
- g_flush_sop_sync : boolean := false; -- When TRUE, flushing is stopped by receiving SOP and SYNC
- g_flush_sop_channel : boolean := false; -- WHEN TRUE, flushing is stopped by receiving SOP and specified channel.
+ -- TRUE instantiates a dp_flush + controller to flush the write fifo when the driver is not ready to write
+ g_flush_wr_fifo : boolean := false;
+ -- TRUE enables the external flush_ena signal and discards flushing when driver is not ready. FALSE enables flushing when driver is not ready
+ g_flush_ext_ena : boolean := false;
+ -- When FALSE, flushing is stopped by valid data. When TRUE flushing is stopped by SOP
+ g_flush_sop : boolean := false;
+ -- When TRUE, flushing is stopped by receiving SOP and SYNC
+ g_flush_sop_sync : boolean := false;
+ -- WHEN TRUE, flushing is stopped by receiving SOP and specified channel.
+ g_flush_sop_channel : boolean := false;
g_flush_sop_start_channel : natural := 0;
g_flush_nof_channels : natural := 0
);
@@ -59,12 +69,16 @@ entity ddr3 is
mm_clk : in std_logic := '0';
ctlr_ref_clk : in std_logic;
- ctlr_rst : in std_logic; -- asynchronous reset input to controller
+ -- asynchronous reset input to controller
+ ctlr_rst : in std_logic;
- ctlr_gen_clk : out std_logic; -- Controller generated clock
+ -- Controller generated clock
+ ctlr_gen_clk : out std_logic;
ctlr_gen_rst : out std_logic;
- ctlr_gen_clk_2x : out std_logic; -- Controller generated double frequency clock
- ctlr_gen_rst_2x : out std_logic; -- ctlr_gen_rst synchronized to ctlr_gen_clk_2x
+ -- Controller generated double frequency clock
+ ctlr_gen_clk_2x : out std_logic;
+ -- ctlr_gen_rst synchronized to ctlr_gen_clk_2x
+ ctlr_gen_rst_2x : out std_logic;
ctlr_init_done : out std_logic;
ctlr_rdy : out std_logic;
@@ -83,7 +97,8 @@ entity ddr3 is
reg_io_ddr_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_io_ddr_miso : out t_mem_miso := c_mem_miso_rst;
- flush_ena : in std_logic; -- When toggled '1' the write-fifo flusher is enabled and stops flushing when configured trigger condition is met.
+ -- When toggled '1' the write-fifo flusher is enabled and stops flushing when configured trigger condition is met.
+ flush_ena : in std_logic;
wr_sosi : in t_dp_sosi;
wr_siso : out t_dp_siso;
@@ -109,7 +124,8 @@ entity ddr3 is
end ddr3;
architecture str of ddr3 is
- constant c_wr_fifo_depth : natural := g_wr_fifo_depth * (c_ddr3_ctlr_data_w / g_wr_data_w); -- Multiply fifo depth by the fifo's rd/wr width ratio to get write side depth
+ -- Multiply fifo depth by the fifo's rd/wr width ratio to get write side depth
+ constant c_wr_fifo_depth : natural := g_wr_fifo_depth * (c_ddr3_ctlr_data_w / g_wr_data_w);
constant c_latency : natural := 1;
@@ -133,7 +149,8 @@ architecture str of ddr3 is
signal dvr_cur_addr : t_ddr3_addr;
signal dvr_flush : std_logic := '0';
- signal ctlr_wr_siso : t_dp_siso := c_dp_siso_rdy; -- default xon='1'
+ -- default xon='1'
+ signal ctlr_wr_siso : t_dp_siso := c_dp_siso_rdy;
signal ctlr_wr_sosi : t_dp_sosi;
signal flush_wr_siso : t_dp_siso;
@@ -142,7 +159,8 @@ architecture str of ddr3 is
signal ctlr_rd_siso : t_dp_siso;
signal ctlr_rd_sosi : t_dp_sosi;
- signal wr_fifo_usedw : std_logic_vector(ceil_log2(g_wr_fifo_depth) - 1 downto 0); -- read side depth of the write FIFO
+ -- read side depth of the write FIFO
+ signal wr_fifo_usedw : std_logic_vector(ceil_log2(g_wr_fifo_depth) - 1 downto 0);
signal local_cal_success : std_logic;
signal local_cal_fail : std_logic;
@@ -170,7 +188,8 @@ begin
g_rd_data_w => c_ddr3_ctlr_data_w,
g_use_ctrl => g_wr_use_ctrl,
g_wr_fifo_size => c_wr_fifo_depth,
- g_wr_fifo_af_margin => 4 + c_latency, -- default (4) + c_latency to compensate for latency introduced by registering wr_siso.ready
+ -- default (4) + c_latency to compensate for latency introduced by registering wr_siso.ready
+ g_wr_fifo_af_margin => 4 + c_latency,
g_rd_fifo_rl => 0
)
port map (
@@ -190,11 +209,14 @@ begin
src_out => flush_wr_sosi
);
- u_dp_flush : entity dp_lib.dp_flush -- Always instantiate the flusher as it also contains a RL adapter
+ -- Always instantiate the flusher as it also contains a RL adapter
+ u_dp_flush : entity dp_lib.dp_flush
generic map (
g_ready_latency => 0,
- g_framed_xon => g_wr_use_ctrl, -- stop flushing when dvr_flush is low and a sop has arrived
- g_framed_xoff => false -- immediately start flushing when dvr_flush goes high
+ -- stop flushing when dvr_flush is low and a sop has arrived
+ g_framed_xon => g_wr_use_ctrl,
+ -- immediately start flushing when dvr_flush goes high
+ g_framed_xoff => false
)
port map (
rst => i_ctlr_gen_rst,
@@ -204,9 +226,11 @@ begin
snk_out => flush_wr_siso,
src_out => ctlr_wr_sosi,
- src_in => ctlr_wr_siso, -- fixed streaming xon='1'
+ -- fixed streaming xon='1'
+ src_in => ctlr_wr_siso,
- flush_en => dvr_flush -- memory mapped xon/xoff control
+ -- memory mapped xon/xoff control
+ flush_en => dvr_flush
);
gen_flush : if g_flush_wr_fifo = true generate
@@ -240,7 +264,8 @@ begin
g_rd_data_w => g_rd_data_w,
g_use_ctrl => false,
g_wr_fifo_size => g_rd_fifo_depth,
- g_wr_fifo_af_margin => c_ddr3_ctrl_nof_latent_reads, -- >=4 (required by dp_fifo)
+ -- >=4 (required by dp_fifo)
+ g_wr_fifo_af_margin => c_ddr3_ctrl_nof_latent_reads,
g_rd_fifo_rl => 1
)
port map (
@@ -293,29 +318,45 @@ begin
u_reg_map : entity common_lib.common_reg_r_w_dc
generic map (
- g_cross_clock_domain => true, -- : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_in_new_latency => 0, -- : NATURAL := 0; -- >= 0
- g_readback => false, -- : BOOLEAN := FALSE; -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
- g_reg => c_mem_reg_io_ddr, -- : t_c_mem := c_mem_reg;
- g_init_reg => (others => '0') -- : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := (OTHERS => '0')
+ -- : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain => true,
+ -- : NATURAL := 0; -- >= 0
+ g_in_new_latency => 0,
+ -- : BOOLEAN := FALSE; -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+ g_readback => false,
+ -- : t_c_mem := c_mem_reg;
+ g_reg => c_mem_reg_io_ddr,
+ -- : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := (OTHERS => '0')
+ g_init_reg => (others => '0')
)
port map (
-- Clocks and reset
- mm_rst => mm_rst, -- : IN STD_LOGIC; -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- : IN STD_LOGIC; -- memory-mapped bus clock
- st_rst => i_ctlr_gen_rst, -- : IN STD_LOGIC; -- reset synchronous with st_clk
- st_clk => i_ctlr_gen_clk, -- : IN STD_LOGIC; -- other clock domain clock
+ -- : IN STD_LOGIC; -- reset synchronous with mm_clk
+ mm_rst => mm_rst,
+ -- : IN STD_LOGIC; -- memory-mapped bus clock
+ mm_clk => mm_clk,
+ -- : IN STD_LOGIC; -- reset synchronous with st_clk
+ st_rst => i_ctlr_gen_rst,
+ -- : IN STD_LOGIC; -- other clock domain clock
+ st_clk => i_ctlr_gen_clk,
-- Memory Mapped Slave in mm_clk domain
- sla_in => reg_io_ddr_mosi, -- : IN t_mem_mosi; -- actual ranges defined by g_reg
- sla_out => reg_io_ddr_miso, -- : OUT t_mem_miso; -- actual ranges defined by g_reg
+ -- : IN t_mem_mosi; -- actual ranges defined by g_reg
+ sla_in => reg_io_ddr_mosi,
+ -- : OUT t_mem_miso; -- actual ranges defined by g_reg
+ sla_out => reg_io_ddr_miso,
-- MM registers in st_clk domain
- reg_wr_arr => OPEN, -- : OUT STD_LOGIC_VECTOR( g_reg.nof_dat-1 DOWNTO 0);
- reg_rd_arr => OPEN, -- : OUT STD_LOGIC_VECTOR( g_reg.nof_dat-1 DOWNTO 0);
- in_new => '1', -- : IN STD_LOGIC := '1';
- in_reg => mm_reg_io_ddr, -- : IN STD_LOGIC_VECTOR(g_reg.dat_w*g_reg.nof_dat-1 DOWNTO 0);
- out_reg => open -- : OUT STD_LOGIC_VECTOR(g_reg.dat_w*g_reg.nof_dat-1 DOWNTO 0)
+ -- : OUT STD_LOGIC_VECTOR( g_reg.nof_dat-1 DOWNTO 0);
+ reg_wr_arr => OPEN,
+ -- : OUT STD_LOGIC_VECTOR( g_reg.nof_dat-1 DOWNTO 0);
+ reg_rd_arr => OPEN,
+ -- : IN STD_LOGIC := '1';
+ in_new => '1',
+ -- : IN STD_LOGIC_VECTOR(g_reg.dat_w*g_reg.nof_dat-1 DOWNTO 0);
+ in_reg => mm_reg_io_ddr,
+ -- : OUT STD_LOGIC_VECTOR(g_reg.dat_w*g_reg.nof_dat-1 DOWNTO 0)
+ out_reg => open
);
mm_reg_io_ddr <= RESIZE_UVEC(local_cal_fail & local_cal_success & i_ctlr_gen_rst & flush_ena & i_ctlr_rdy & i_ctlr_init_done, 32);
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd b/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd
index 77dc5117a99f21672b57d83657b4d3d2ab0bc5a5..04ee0c9557b66b7308d82c0536ac539d289cbf4d 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd
@@ -44,7 +44,8 @@ entity ddr3_driver is
dvr_en : in std_logic := '1';
dvr_wr_not_rd : in std_logic;
- dvr_done : out std_logic; -- Requested wr or rd sequence is done.
+ -- Requested wr or rd sequence is done.
+ dvr_done : out std_logic;
wr_val : in std_logic;
wr_rdy : out std_logic;
@@ -59,10 +60,13 @@ entity ddr3_driver is
end ddr3_driver;
architecture str of ddr3_driver is
- constant c_chip_addr_w : natural := ceil_log2(g_ddr.cs_w); -- Chip sel lines converted to logical address
- constant c_address_w : natural := c_chip_addr_w + g_ddr.ba_w + g_ddr.a_w + g_ddr.a_col_w + 1; -- 1 bit added to detect overflow
+ -- Chip sel lines converted to logical address
+ constant c_chip_addr_w : natural := ceil_log2(g_ddr.cs_w);
+ -- 1 bit added to detect overflow
+ constant c_address_w : natural := c_chip_addr_w + g_ddr.ba_w + g_ddr.a_w + g_ddr.a_col_w + 1;
- constant c_margin : natural := 2; -- wr_burst_size is updated one cycle after reading actual nof available words.
+ -- wr_burst_size is updated one cycle after reading actual nof available words.
+ constant c_margin : natural := 2;
-- Subtract two (wr_fifo_usedw and wr_burst_size are both registered) so we cannot
-- post a request for a too large burst size, which could cause the wr_burst state
-- to be two valid words short.
@@ -94,10 +98,13 @@ architecture str of ddr3_driver is
signal nxt_cur_address : std_logic_vector(c_address_w - 1 downto 0);
signal diff_address : std_logic_vector(c_address_w - 1 downto 0);
- signal addresses_rem : std_logic_vector(31 downto 0); -- nof words (on the user side interface) to rd/wr until end addr is reached
- signal reg_addresses_rem : std_logic_vector(31 downto 0); -- nof words (on the user side interface) to rd/wr until end addr is reached
+ -- nof words (on the user side interface) to rd/wr until end addr is reached
+ signal addresses_rem : std_logic_vector(31 downto 0);
+ -- nof words (on the user side interface) to rd/wr until end addr is reached
+ signal reg_addresses_rem : std_logic_vector(31 downto 0);
- signal reg_wr_fifo_usedw : std_logic_vector(ceil_log2(g_wr_fifo_depth) - 1 downto 0); -- read side depth of the write FIFO
+ -- read side depth of the write FIFO
+ signal reg_wr_fifo_usedw : std_logic_vector(ceil_log2(g_wr_fifo_depth) - 1 downto 0);
begin
ctlr_burst_size <= i_ctlr_burst_size;
dvr_done <= i_dvr_done;
@@ -149,7 +156,8 @@ begin
-- Read burst size is smallest of c_ddr3_ctlr_maxburstsize and addresses_rem
v_burst_size := c_ddr3_ctlr_maxburstsize;
- if unsigned(reg_addresses_rem) >= 1 then -- prevent assigning <0 value to natural
+ -- prevent assigning <0 value to natural
+ if unsigned(reg_addresses_rem) >= 1 then
if v_burst_size > signed('0' & reg_addresses_rem) then v_burst_size := TO_UINT(reg_addresses_rem); end if;
else
v_burst_size := 0;
@@ -171,34 +179,45 @@ begin
case state is
- when s_wr_burst => -- Performs the burst portion (word 2+)
+ -- Performs the burst portion (word 2+)
+ when s_wr_burst =>
ctlr_wr_req <= '1';
- if ctlr_rdy = '1' then -- when local_ready goes low, that cycle does not count as a burst cycle
+ -- when local_ready goes low, that cycle does not count as a burst cycle
+ if ctlr_rdy = '1' then
nxt_req_burst_cycles <= INCR_UVEC(req_burst_cycles, -1);
- wr_rdy <= '1'; -- wr side uses latency of 0, so wr_rdy<='1' acknowledges a successful write request.
- if unsigned(req_burst_cycles) = 1 then -- Then we're in the last cycle of this burst sequence
- nxt_state <= s_wr_request; -- We can only initiate a burst through the wr_request state
+ -- wr side uses latency of 0, so wr_rdy<='1' acknowledges a successful write request.
+ wr_rdy <= '1';
+ -- Then we're in the last cycle of this burst sequence
+ if unsigned(req_burst_cycles) = 1 then
+ -- We can only initiate a burst through the wr_request state
+ nxt_state <= s_wr_request;
end if;
end if;
- when s_wr_request => -- Performs 1 write or read and goes into s_wr_burst when requested write words >1
+ -- Performs 1 write or read and goes into s_wr_burst when requested write words >1
+ when s_wr_request =>
nxt_state <= s_wait3;
- if unsigned(reg_addresses_rem) = 0 then -- end address reached
+ -- end address reached
+ if unsigned(reg_addresses_rem) = 0 then
nxt_dvr_done <= '1';
nxt_state <= s_idle;
elsif ctlr_rdy = '1' then
if wr_val = '1' then
-- Always perform 1st write here
- ctlr_burst <= '1'; -- assert burst begin: strictly this is a burst of 1.
+ -- assert burst begin: strictly this is a burst of 1.
+ ctlr_burst <= '1';
ctlr_wr_req <= '1';
wr_rdy <= '1';
- i_ctlr_burst_size <= TO_UVEC(1, c_ddr3_ctlr_maxburstsize_w); -- Set ctlr_burst_size to 1 by default
+ -- Set ctlr_burst_size to 1 by default
+ i_ctlr_burst_size <= TO_UVEC(1, c_ddr3_ctlr_maxburstsize_w);
if wr_burst_size > 1 then
-- Perform any remaining writes in a burst
nxt_state <= s_wr_burst;
- nxt_req_burst_cycles <= TO_UVEC(wr_burst_size-1, c_ddr3_ctlr_maxburstsize_w); -- Forward the required nof burst cycles (-1 as we've done the 1st in this state already) to burst state
+ -- Forward the required nof burst cycles (-1 as we've done the 1st in this state already) to burst state
+ nxt_req_burst_cycles <= TO_UVEC(wr_burst_size-1, c_ddr3_ctlr_maxburstsize_w);
i_ctlr_burst_size <= TO_UVEC(wr_burst_size , c_ddr3_ctlr_maxburstsize_w);
- end if; -- ELSE: there is only 1 word, so no need for remaining burst
+ -- ELSE: there is only 1 word, so no need for remaining burst
+ end if;
nxt_cur_address <= INCR_UVEC(cur_address, unsigned(i_ctlr_burst_size) * c_ddr3_ctlr_rsl);
-- IF UNSIGNED(i_ctlr_burst_size) = 1 THEN -- Prevents FSM from going into this state again too soon (reg_addresses_rem invalid)
-- nxt_state <= s_wait3;
@@ -206,16 +225,20 @@ begin
end if;
end if;
- when s_rd_request => -- Posts a read request for a burst (0...c_ddr3_ctlr_maxburstsize)
+ -- Posts a read request for a burst (0...c_ddr3_ctlr_maxburstsize)
+ when s_rd_request =>
nxt_state <= s_wait3;
- if unsigned(reg_addresses_rem) = 0 then -- end address reached
+ -- end address reached
+ if unsigned(reg_addresses_rem) = 0 then
nxt_dvr_done <= '1';
nxt_state <= s_idle;
else
- if rd_rdy = '1' then -- Fifo uses its internal almost_full signal to toggle its snk_out.rdy
+ -- Fifo uses its internal almost_full signal to toggle its snk_out.rdy
+ if rd_rdy = '1' then
if ctlr_rdy = '1' then
ctlr_rd_req <= '1';
- ctlr_burst <= '1'; -- assert burst begin: strictly this is a burst of 1.
+ -- assert burst begin: strictly this is a burst of 1.
+ ctlr_burst <= '1';
i_ctlr_burst_size <= TO_UVEC(rd_burst_size, c_ddr3_ctlr_maxburstsize_w);
if rd_burst_size = 0 then i_ctlr_burst_size <= TO_UVEC(1, c_ddr3_ctlr_maxburstsize_w); end if;
nxt_cur_address <= INCR_UVEC(cur_address, unsigned(i_ctlr_burst_size) * c_ddr3_ctlr_rsl);
@@ -252,7 +275,8 @@ begin
nxt_state <= s_wait1;
end if;
- when others => -- s_init
+ -- s_init
+ when others =>
if ctlr_init_done = '1' then
nxt_state <= s_idle;
end if;
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_flush_ctrl.vhd b/libraries/io/ddr3/src/vhdl/ddr3_flush_ctrl.vhd
index 8f59eddac9f720d41848965ec3339d7760fb19ad..a9b56f8e8008f229a4016165de6086c579654258 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_flush_ctrl.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_flush_ctrl.vhd
@@ -52,10 +52,14 @@ use dp_lib.dp_stream_pkg.all;
entity ddr3_flush_ctrl is
generic (
- g_ext_ena : boolean := false; -- TRUE: Enables the external flesh_ena signaland discards the dvr_done signal
- g_sop : boolean := false; -- Stop flushing on SOP, otherwise stop flushing on valid data
- g_sop_sync : boolean := false; -- Stop flushing when SOP and SYNC are received, otherwise flushing is stopped on valid data
- g_sop_channel : boolean := false; -- When g_sop=TRUE, also check if the channel matches g_sop_start_channel
+ -- TRUE: Enables the external flesh_ena signaland discards the dvr_done signal
+ g_ext_ena : boolean := false;
+ -- Stop flushing on SOP, otherwise stop flushing on valid data
+ g_sop : boolean := false;
+ -- Stop flushing when SOP and SYNC are received, otherwise flushing is stopped on valid data
+ g_sop_sync : boolean := false;
+ -- When g_sop=TRUE, also check if the channel matches g_sop_start_channel
+ g_sop_channel : boolean := false;
g_sop_start_channel : natural := 0;
g_nof_channels : natural := 0
);
@@ -93,19 +97,22 @@ begin
-- allowed to fill up too much).
-- Also flush the ddr3 module's FIFO when it is reading.
- gen_sop : if g_sop = true generate -- Disable flushing on arrival of SOP
+ -- Disable flushing on arrival of SOP
+ gen_sop : if g_sop = true generate
-- gen_sop_only: IF g_sop_channel = FALSE GENERATE
-- flush_dis <= '1' WHEN wr_sosi.sop='1' ELSE '0';
-- END GENERATE;
-- gen_channel : IF g_sop_channel = TRUE GENERATE -- Only disable flushing on arrival of specific channel SOP
-- flush_dis <= '1' WHEN wr_sosi.sop='1' AND UNSIGNED(wr_sosi.channel(c_channel_w-1 DOWNTO 0))=g_sop_start_channel ELSE '0';
-- END GENERATE;
- gen_sync : if g_sop_sync = true generate -- Only disable flushing on arrival of SOP that is accompanied with a SYNC
+ -- Only disable flushing on arrival of SOP that is accompanied with a SYNC
+ gen_sync : if g_sop_sync = true generate
flush_dis <= '1' when wr_sosi.sop = '1' and wr_sosi.sync = '1' else '0';
end generate;
end generate;
- gen_val : if g_sop = false generate -- Disable flushing on arrival of 1st valid data
+ -- Disable flushing on arrival of 1st valid data
+ gen_val : if g_sop = false generate
flush_dis <= wr_sosi.valid;
end generate;
@@ -139,7 +146,8 @@ begin
elsif g_ext_ena = true then
nxt_state <= s_idle;
end if;
- when others => -- s_stop
+ -- s_stop
+ when others =>
dvr_flush <= '1';
if flush_dis = '1' then
nxt_state <= s_idle;
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
index 9805ce05f447b20129cfd0ea6e91afebd082efab..e59450d7fed0adc78b12727ffb0e587761d31102 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
@@ -27,15 +27,24 @@ use IEEE.numeric_std.all;
package ddr3_pkg is
-- DDR3 (definitions similar as in ug_altmemphy.pdf)
type t_c_ddr3_phy is record
- a_w : natural; -- = 16;
- a_row_w : natural; -- = 16; -- = a_w, row address width, via a_w lines
- a_col_w : natural; -- = 10; -- <= a_w, col address width, via a_w lines
- ba_w : natural; -- = 3;
- dq_w : natural; -- = 64;
- dqs_w : natural; -- = 8; -- = dq_w / nof_dq_per_dqs;
- dm_w : natural; -- = 8;
- cs_w : natural; -- = 2;
- clk_w : natural; -- = 2;
+ -- = 16;
+ a_w : natural;
+ -- = 16; -- = a_w, row address width, via a_w lines
+ a_row_w : natural;
+ -- = 10; -- <= a_w, col address width, via a_w lines
+ a_col_w : natural;
+ -- = 3;
+ ba_w : natural;
+ -- = 64;
+ dq_w : natural;
+ -- = 8; -- = dq_w / nof_dq_per_dqs;
+ dqs_w : natural;
+ -- = 8;
+ dm_w : natural;
+ -- = 2;
+ cs_w : natural;
+ -- = 2;
+ clk_w : natural;
end record;
constant c_ddr3_phy : t_c_ddr3_phy := (16, 16, 10, 3, 64, 8, 8, 2, 2);
@@ -45,30 +54,47 @@ package ddr3_pkg is
evt : std_logic;
oct_rup : std_logic;
oct_rdn : std_logic;
- nc : std_logic; -- not connected, needed to be able to initialize constant record which has to have more than one field in VHDL
+ -- not connected, needed to be able to initialize constant record which has to have more than one field in VHDL
+ nc : std_logic;
end record;
- type t_ddr3_phy_io is record -- Do not use this type in Quartus! Use the _sel version instead.
- dq : std_logic_vector(c_ddr3_phy.dq_w - 1 downto 0); -- data bus
- dqs : std_logic_vector(c_ddr3_phy.dqs_w - 1 downto 0); -- data strobe bus
+ -- Do not use this type in Quartus! Use the _sel version instead.
+ type t_ddr3_phy_io is record
+ -- data bus
+ dq : std_logic_vector(c_ddr3_phy.dq_w - 1 downto 0);
+ -- data strobe bus
+ dqs : std_logic_vector(c_ddr3_phy.dqs_w - 1 downto 0);
dqs_n : std_logic_vector(c_ddr3_phy.dqs_w - 1 downto 0);
- scl : std_logic; -- I2C
+ -- I2C
+ scl : std_logic;
sda : std_logic;
end record;
type t_ddr3_phy_ou is record
- a : std_logic_vector(c_ddr3_phy.a_w - 1 downto 0); -- row and column address
- ba : std_logic_vector(c_ddr3_phy.ba_w - 1 downto 0); -- bank address
- dm : std_logic_vector(c_ddr3_phy.dm_w - 1 downto 0); -- data mask bus
- cas_n : std_logic; -- _VECTOR(0 DOWNTO 0); -- column address strobe
- ras_n : std_logic; -- _VECTOR(0 DOWNTO 0); -- row address strobe
- we_n : std_logic; -- _VECTOR(0 DOWNTO 0); -- write enable signal
- reset_n : std_logic; -- reset signal
- ck : std_logic_vector(c_ddr3_phy.clk_w - 1 downto 0); -- clock, positive edge clock
- ck_n : std_logic_vector(c_ddr3_phy.clk_w - 1 downto 0); -- clock, negative edge clock
- odt : std_logic_vector(c_ddr3_phy.cs_w - 1 downto 0); -- on-die termination control signal
- cke : std_logic_vector(c_ddr3_phy.cs_w - 1 downto 0); -- clock enable
- cs_n : std_logic_vector(c_ddr3_phy.cs_w - 1 downto 0); -- chip select
+ -- row and column address
+ a : std_logic_vector(c_ddr3_phy.a_w - 1 downto 0);
+ -- bank address
+ ba : std_logic_vector(c_ddr3_phy.ba_w - 1 downto 0);
+ -- data mask bus
+ dm : std_logic_vector(c_ddr3_phy.dm_w - 1 downto 0);
+ -- _VECTOR(0 DOWNTO 0); -- column address strobe
+ cas_n : std_logic;
+ -- _VECTOR(0 DOWNTO 0); -- row address strobe
+ ras_n : std_logic;
+ -- _VECTOR(0 DOWNTO 0); -- write enable signal
+ we_n : std_logic;
+ -- reset signal
+ reset_n : std_logic;
+ -- clock, positive edge clock
+ ck : std_logic_vector(c_ddr3_phy.clk_w - 1 downto 0);
+ -- clock, negative edge clock
+ ck_n : std_logic_vector(c_ddr3_phy.clk_w - 1 downto 0);
+ -- on-die termination control signal
+ odt : std_logic_vector(c_ddr3_phy.cs_w - 1 downto 0);
+ -- clock enable
+ cke : std_logic_vector(c_ddr3_phy.cs_w - 1 downto 0);
+ -- chip select
+ cs_n : std_logic_vector(c_ddr3_phy.cs_w - 1 downto 0);
end record;
constant c_ddr3_phy_in_rst : t_ddr3_phy_in := ('0', 'X', 'X', 'X');
@@ -80,7 +106,8 @@ package ddr3_pkg is
type t_ddr3_phy_ou_arr is array(natural range <>) of t_ddr3_phy_ou;
type t_ddr3_addr is record
- chip : std_logic_vector(ceil_log2(c_ddr3_phy.cs_w) - 1 downto 0); -- Note: The controller interprets the chip address as logical address (NOT individual chip sel lines), hence ceil_log2
+ -- Note: The controller interprets the chip address as logical address (NOT individual chip sel lines), hence ceil_log2
+ chip : std_logic_vector(ceil_log2(c_ddr3_phy.cs_w) - 1 downto 0);
bank : std_logic_vector( c_ddr3_phy.ba_w - 1 downto 0);
row : std_logic_vector( c_ddr3_phy.a_row_w - 1 downto 0);
column : std_logic_vector( c_ddr3_phy.a_col_w - 1 downto 0);
@@ -88,12 +115,15 @@ package ddr3_pkg is
type t_ddr3_addr_arr is array(natural range <>) of t_ddr3_addr;
- constant c_ddr3_ctlr_data_w : natural := 256; -- = 64 (PHY dq width) * 2 (use both PHY clock edges) * 2 (PHY transfer at double rate)
- constant c_ddr3_ctlr_rsl : natural := c_ddr3_ctlr_data_w / c_ddr3_phy.dq_w; -- =4
+ -- = 64 (PHY dq width) * 2 (use both PHY clock edges) * 2 (PHY transfer at double rate)
+ constant c_ddr3_ctlr_data_w : natural := 256;
+ -- =4
+ constant c_ddr3_ctlr_rsl : natural := c_ddr3_ctlr_data_w / c_ddr3_phy.dq_w;
constant c_ddr3_ctlr_rsl_w : natural := ceil_log2(c_ddr3_ctlr_rsl);
constant c_ddr3_ctlr_maxburstsize : natural := 64;
constant c_ddr3_ctlr_maxburstsize_w : natural := ceil_log2(c_ddr3_ctlr_maxburstsize+1);
- constant c_ddr3_ctrl_nof_latent_reads : natural := 100; -- The downside to having a command cue: even after de-asserting read requests, the ALTMEMPHY keeps processing your cued read requests.
+ -- The downside to having a command cue: even after de-asserting read requests, the ALTMEMPHY keeps processing your cued read requests.
+ constant c_ddr3_ctrl_nof_latent_reads : natural := 100;
-- This makes sure 100 words are still available in the read FIFO after it de-asserted its siso.ready signal towards the ddr3 read side.
constant c_ddr3_phy_oct_w : natural := 14;
@@ -107,15 +137,22 @@ package ddr3_pkg is
-- 4 rows * 1024 cols * 64 bits / 128bits per associative mem array element = 2048 = default ALTMEMPHY mem_model array depth.
constant c_ddr3_addr_hi_sim : t_ddr3_addr := ((others => '0'), (others => '0'), TO_UVEC(3, c_ddr3_phy.a_row_w), TO_UVEC(2**c_ddr3_phy_4g.a_col_w - c_ddr3_ctlr_rsl, c_ddr3_phy_4g.a_col_w));
- constant c_ddr3_address_hi_sim : natural := 4092; -- TB uses generated mem model with 2ki addresses of 128k - so the array holds 4096 64-bit words. End address is 4092 (resolution=4: last write=4092,4093,4094,4095.)
+ -- TB uses generated mem model with 2ki addresses of 128k - so the array holds 4096 64-bit words. End address is 4092 (resolution=4: last write=4092,4093,4094,4095.)
+ constant c_ddr3_address_hi_sim : natural := 4092;
type t_ddr3_seq is record
- wr_chunksize : positive; -- := 64;
- wr_nof_chunks : positive; -- := 1;
- rd_chunksize : positive; -- := 16;
- rd_nof_chunks : positive; -- := 4;
- gapsize : natural; -- := 0;
- nof_blocks : positive; -- := 5;
+ -- := 64;
+ wr_chunksize : positive;
+ -- := 1;
+ wr_nof_chunks : positive;
+ -- := 16;
+ rd_chunksize : positive;
+ -- := 4;
+ rd_nof_chunks : positive;
+ -- := 0;
+ gapsize : natural;
+ -- := 5;
+ nof_blocks : positive;
end record;
constant c_ddr3_seq : t_ddr3_seq := (64, 1, 16, 4, 0, 5);
@@ -123,52 +160,98 @@ package ddr3_pkg is
-- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
component ip_stratixiv_ddr3_uphy_4g_800_master is
port (
- pll_ref_clk : in std_logic; -- pll_ref_clk.clk
- global_reset_n : in std_logic; -- global_reset.reset_n
- soft_reset_n : in std_logic; -- soft_reset.reset_n
- afi_clk : out std_logic; -- afi_clk.clk
- afi_half_clk : out std_logic; -- afi_half_clk.clk
- afi_reset_n : out std_logic; -- afi_reset.reset_n
- mem_a : out std_logic_vector(14 downto 0); -- memory.mem_a
- mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
- mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
- mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
- mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
- mem_ras_n : out std_logic; -- .mem_ras_n
- mem_cas_n : out std_logic; -- .mem_cas_n
- mem_we_n : out std_logic; -- .mem_we_n
- mem_reset_n : out std_logic; -- .mem_reset_n
- mem_dq : inout std_logic_vector(63 downto 0); -- .mem_dq
- mem_dqs : inout std_logic_vector(7 downto 0); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(7 downto 0); -- .mem_dqs_n
- mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
- avl_ready : out std_logic; -- avl.waitrequest_n
- avl_burstbegin : in std_logic; -- .beginbursttransfer
- avl_addr : in std_logic_vector(26 downto 0); -- .address
- avl_rdata_valid : out std_logic; -- .readdatavalid
- avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
- avl_wdata : in std_logic_vector(255 downto 0); -- .writedata
- avl_be : in std_logic_vector(31 downto 0); -- .byteenable
- avl_read_req : in std_logic; -- .read
- avl_write_req : in std_logic; -- .write
- avl_size : in std_logic_vector(6 downto 0); -- .burstcount
- local_init_done : out std_logic; -- status.local_init_done
- local_cal_success : out std_logic; -- .local_cal_success
- local_cal_fail : out std_logic; -- .local_cal_fail
- oct_rdn : in std_logic; -- oct.rdn
- oct_rup : in std_logic; -- .rup
- seriesterminationcontrol : out std_logic_vector(13 downto 0); -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol : out std_logic_vector(13 downto 0); -- .parallelterminationcontrol
- pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
- pll_write_clk : out std_logic; -- .pll_write_clk
- pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
- pll_locked : out std_logic; -- .pll_locked
- pll_avl_clk : out std_logic; -- .pll_avl_clk
- pll_config_clk : out std_logic; -- .pll_config_clk
- dll_delayctrl : out std_logic_vector(5 downto 0) -- dll_sharing.dll_delayctrl
+ -- pll_ref_clk.clk
+ pll_ref_clk : in std_logic;
+ -- global_reset.reset_n
+ global_reset_n : in std_logic;
+ -- soft_reset.reset_n
+ soft_reset_n : in std_logic;
+ -- afi_clk.clk
+ afi_clk : out std_logic;
+ -- afi_half_clk.clk
+ afi_half_clk : out std_logic;
+ -- afi_reset.reset_n
+ afi_reset_n : out std_logic;
+ -- memory.mem_a
+ mem_a : out std_logic_vector(14 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(2 downto 0);
+ -- .mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- .mem_dm
+ mem_dm : out std_logic_vector(7 downto 0);
+ -- .mem_ras_n
+ mem_ras_n : out std_logic;
+ -- .mem_cas_n
+ mem_cas_n : out std_logic;
+ -- .mem_we_n
+ mem_we_n : out std_logic;
+ -- .mem_reset_n
+ mem_reset_n : out std_logic;
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(63 downto 0);
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(7 downto 0);
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(7 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- avl.waitrequest_n
+ avl_ready : out std_logic;
+ -- .beginbursttransfer
+ avl_burstbegin : in std_logic;
+ -- .address
+ avl_addr : in std_logic_vector(26 downto 0);
+ -- .readdatavalid
+ avl_rdata_valid : out std_logic;
+ -- .readdata
+ avl_rdata : out std_logic_vector(255 downto 0);
+ -- .writedata
+ avl_wdata : in std_logic_vector(255 downto 0);
+ -- .byteenable
+ avl_be : in std_logic_vector(31 downto 0);
+ -- .read
+ avl_read_req : in std_logic;
+ -- .write
+ avl_write_req : in std_logic;
+ -- .burstcount
+ avl_size : in std_logic_vector(6 downto 0);
+ -- status.local_init_done
+ local_init_done : out std_logic;
+ -- .local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic;
+ -- oct.rdn
+ oct_rdn : in std_logic;
+ -- .rup
+ oct_rup : in std_logic;
+ -- oct_sharing.seriesterminationcontrol
+ seriesterminationcontrol : out std_logic_vector(13 downto 0);
+ -- .parallelterminationcontrol
+ parallelterminationcontrol : out std_logic_vector(13 downto 0);
+ -- pll_sharing.pll_mem_clk
+ pll_mem_clk : out std_logic;
+ -- .pll_write_clk
+ pll_write_clk : out std_logic;
+ -- .pll_write_clk_pre_phy_clk
+ pll_write_clk_pre_phy_clk : out std_logic;
+ -- .pll_addr_cmd_clk
+ pll_addr_cmd_clk : out std_logic;
+ -- .pll_locked
+ pll_locked : out std_logic;
+ -- .pll_avl_clk
+ pll_avl_clk : out std_logic;
+ -- .pll_config_clk
+ pll_config_clk : out std_logic;
+ -- dll_sharing.dll_delayctrl
+ dll_delayctrl : out std_logic_vector(5 downto 0)
);
end component;
@@ -176,50 +259,94 @@ package ddr3_pkg is
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
component ip_stratixiv_ddr3_uphy_4g_800_slave is
port (
- pll_ref_clk : in std_logic; -- pll_ref_clk.clk
- global_reset_n : in std_logic; -- global_reset.reset_n
- soft_reset_n : in std_logic; -- soft_reset.reset_n
- afi_clk : out std_logic; -- afi_clk.clk
- afi_half_clk : out std_logic; -- afi_half_clk.clk
- afi_reset_n : out std_logic; -- afi_reset.reset_n
- mem_a : out std_logic_vector(14 downto 0); -- memory.mem_a
- mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
- mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
- mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
- mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
- mem_ras_n : out std_logic; -- .mem_ras_n
- mem_cas_n : out std_logic; -- .mem_cas_n
- mem_we_n : out std_logic; -- .mem_we_n
- mem_reset_n : out std_logic; -- .mem_reset_n
- mem_dq : inout std_logic_vector(63 downto 0); -- .mem_dq
- mem_dqs : inout std_logic_vector(7 downto 0); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(7 downto 0); -- .mem_dqs_n
- mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
- avl_ready : out std_logic; -- avl.waitrequest_n
- avl_burstbegin : in std_logic; -- .beginbursttransfer
- avl_addr : in std_logic_vector(26 downto 0); -- .address
- avl_rdata_valid : out std_logic; -- .readdatavalid
- avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
- avl_wdata : in std_logic_vector(255 downto 0); -- .writedata
- avl_be : in std_logic_vector(31 downto 0); -- .byteenable
- avl_read_req : in std_logic; -- .read
- avl_write_req : in std_logic; -- .write
- avl_size : in std_logic_vector(6 downto 0); -- .burstcount
- local_init_done : out std_logic; -- status.local_init_done
- local_cal_success : out std_logic; -- .local_cal_success
- local_cal_fail : out std_logic; -- .local_cal_fail
- seriesterminationcontrol : in std_logic_vector(13 downto 0); -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol : in std_logic_vector(13 downto 0); -- .parallelterminationcontrol
- pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
- pll_write_clk : out std_logic; -- .pll_write_clk
- pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
- pll_locked : out std_logic; -- .pll_locked
- pll_avl_clk : out std_logic; -- .pll_avl_clk
- pll_config_clk : out std_logic; -- .pll_config_clk
- dll_delayctrl : out std_logic_vector(5 downto 0) -- dll_sharing.dll_delayctrl
+ -- pll_ref_clk.clk
+ pll_ref_clk : in std_logic;
+ -- global_reset.reset_n
+ global_reset_n : in std_logic;
+ -- soft_reset.reset_n
+ soft_reset_n : in std_logic;
+ -- afi_clk.clk
+ afi_clk : out std_logic;
+ -- afi_half_clk.clk
+ afi_half_clk : out std_logic;
+ -- afi_reset.reset_n
+ afi_reset_n : out std_logic;
+ -- memory.mem_a
+ mem_a : out std_logic_vector(14 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(2 downto 0);
+ -- .mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- .mem_dm
+ mem_dm : out std_logic_vector(7 downto 0);
+ -- .mem_ras_n
+ mem_ras_n : out std_logic;
+ -- .mem_cas_n
+ mem_cas_n : out std_logic;
+ -- .mem_we_n
+ mem_we_n : out std_logic;
+ -- .mem_reset_n
+ mem_reset_n : out std_logic;
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(63 downto 0);
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(7 downto 0);
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(7 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- avl.waitrequest_n
+ avl_ready : out std_logic;
+ -- .beginbursttransfer
+ avl_burstbegin : in std_logic;
+ -- .address
+ avl_addr : in std_logic_vector(26 downto 0);
+ -- .readdatavalid
+ avl_rdata_valid : out std_logic;
+ -- .readdata
+ avl_rdata : out std_logic_vector(255 downto 0);
+ -- .writedata
+ avl_wdata : in std_logic_vector(255 downto 0);
+ -- .byteenable
+ avl_be : in std_logic_vector(31 downto 0);
+ -- .read
+ avl_read_req : in std_logic;
+ -- .write
+ avl_write_req : in std_logic;
+ -- .burstcount
+ avl_size : in std_logic_vector(6 downto 0);
+ -- status.local_init_done
+ local_init_done : out std_logic;
+ -- .local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic;
+ -- oct_sharing.seriesterminationcontrol
+ seriesterminationcontrol : in std_logic_vector(13 downto 0);
+ -- .parallelterminationcontrol
+ parallelterminationcontrol : in std_logic_vector(13 downto 0);
+ -- pll_sharing.pll_mem_clk
+ pll_mem_clk : out std_logic;
+ -- .pll_write_clk
+ pll_write_clk : out std_logic;
+ -- .pll_write_clk_pre_phy_clk
+ pll_write_clk_pre_phy_clk : out std_logic;
+ -- .pll_addr_cmd_clk
+ pll_addr_cmd_clk : out std_logic;
+ -- .pll_locked
+ pll_locked : out std_logic;
+ -- .pll_avl_clk
+ pll_avl_clk : out std_logic;
+ -- .pll_config_clk
+ pll_config_clk : out std_logic;
+ -- dll_sharing.dll_delayctrl
+ dll_delayctrl : out std_logic_vector(5 downto 0)
);
end component;
@@ -252,21 +379,36 @@ package ddr3_pkg is
DAT_DATA_WIDTH : integer := 32
);
port (
- mem_a : in std_logic_vector(14 downto 0) := (others => 'X'); -- mem_a
- mem_ba : in std_logic_vector(2 downto 0) := (others => 'X'); -- mem_ba
- mem_ck : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_ck
- mem_ck_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_ck_n
- mem_cke : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_cke
- mem_cs_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_cs_n
- mem_dm : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dm
- mem_ras_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ras_n
- mem_cas_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_cas_n
- mem_we_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_we_n
- mem_reset_n : in std_logic := 'X'; -- mem_reset_n
- mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
- mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_odt : in std_logic_vector(1 downto 0) := (others => 'X') -- mem_odt
+ -- mem_a
+ mem_a : in std_logic_vector(14 downto 0) := (others => 'X');
+ -- mem_ba
+ mem_ba : in std_logic_vector(2 downto 0) := (others => 'X');
+ -- mem_ck
+ mem_ck : in std_logic_vector(1 downto 0) := (others => 'X');
+ -- mem_ck_n
+ mem_ck_n : in std_logic_vector(1 downto 0) := (others => 'X');
+ -- mem_cke
+ mem_cke : in std_logic_vector(1 downto 0) := (others => 'X');
+ -- mem_cs_n
+ mem_cs_n : in std_logic_vector(1 downto 0) := (others => 'X');
+ -- mem_dm
+ mem_dm : in std_logic_vector(7 downto 0) := (others => 'X');
+ -- mem_ras_n
+ mem_ras_n : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- mem_cas_n
+ mem_cas_n : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- mem_we_n
+ mem_we_n : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- mem_reset_n
+ mem_reset_n : in std_logic := 'X';
+ -- mem_dq
+ mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X');
+ -- mem_dqs
+ mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X');
+ -- mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X');
+ -- mem_odt
+ mem_odt : in std_logic_vector(1 downto 0) := (others => 'X')
);
end component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en;
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_reg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_reg.vhd
index 6cefa51713fd98b935a4ba013ecbad71bd9ce535..68cffe39fba77e8179c3390e6b4b4c26400fbd31 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_reg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_reg.vhd
@@ -52,14 +52,20 @@ entity ddr3_reg is
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
st_en_evt : out std_logic;
@@ -77,7 +83,8 @@ end ddr3_reg;
architecture rtl of ddr3_reg is
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(7),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 7,
init_sl => '0');
-- Registers in mm_clk domain
@@ -130,13 +137,16 @@ begin
mm_start_address <= sla_in.wrdata(31 downto 0);
when 6 =>
mm_end_address <= sla_in.wrdata(31 downto 0);
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read Block Sync
when 2 =>
@@ -145,7 +155,8 @@ begin
sla_out.rddata(0) <= mm_init_done;
when 4 =>
sla_out.rddata(0) <= mm_ctlr_rdy;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd b/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
index f73e223e0a9390c9a795c0dae746d1b2c4f72aa5..a851d492e7348fcd1288ed21ec5214feead35cf5 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
@@ -32,8 +32,10 @@ entity ddr3_seq is
);
port (
-- Clocks and reset
- dp_rst : in std_logic; -- reset synchronous with st_clk
- dp_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with st_clk
+ dp_rst : in std_logic;
+ -- other clock domain clock
+ dp_clk : in std_logic;
en_evt : out std_logic;
wr_not_rd : out std_logic;
@@ -71,13 +73,16 @@ architecture rtl of ddr3_seq is
wr_chunks_offset : natural;
wr_block_cnt : natural;
wr_chunks_cnt : natural;
- switch_cnt : natural; -- Counter that counts the write and read accesses to determine the switch between read and write phase.
- page_cnt : natural; -- Counter that counts the number of write accesses to determuine the page-swap.
+ -- Counter that counts the write and read accesses to determine the switch between read and write phase.
+ switch_cnt : natural;
+ -- Counter that counts the number of write accesses to determuine the page-swap.
+ page_cnt : natural;
first_write : std_logic;
sync_ok_out : std_logic;
start_addr : std_logic_vector(c_address_w - 1 downto 0);
end_addr : std_logic_vector(c_address_w - 1 downto 0);
- state : state_type; -- The state machine.
+ -- The state machine.
+ state : state_type;
end record;
signal r, rin : reg_type;
@@ -112,7 +117,8 @@ begin
when s_write =>
if(done = '1' and ctlr_rdy = '1') then
v.wr_not_rd := '1';
- if(sync_ok_in = '1') then -- Only write when good sync pattern on the input.
+ -- Only write when good sync pattern on the input.
+ if(sync_ok_in = '1') then
v.ddr3_en := '1';
end if;
v.start_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset + r.wr_chunks_offset, c_address_w);
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd b/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
index 1c6b86fceee59f6e3323959a2570408782acf5cf..95d348ccf85ecf5a3145047c62383765fb51b9fc 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
@@ -39,14 +39,18 @@ entity ddr3_transpose is
g_nof_blk_per_sync : natural := 16;
g_use_complex : boolean := true;
g_ena_pre_transp : boolean := true;
- g_phy : natural := 1; -- 0: ALTMEMPHY 1: UNIPHY_MASTER 2: UNIPHY_SLAVE
- g_mts : natural := 800; -- Megatransfers per second
+ -- 0: ALTMEMPHY 1: UNIPHY_MASTER 2: UNIPHY_SLAVE
+ g_phy : natural := 1;
+ -- Megatransfers per second
+ g_mts : natural := 800;
g_ddr3_seq : t_ddr3_seq := c_ddr3_seq;
g_select_file : string := "UNUSED"
);
port (
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
dp_ref_clk : in std_logic;
dp_ref_rst : in std_logic;
@@ -69,7 +73,8 @@ entity ddr3_transpose is
src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-- Memory Mapped
- ram_ss_ss_transp_mosi : in t_mem_mosi; -- channel select control
+ -- channel select control
+ ram_ss_ss_transp_mosi : in t_mem_mosi;
ram_ss_ss_transp_miso : out t_mem_miso;
ser_term_ctrl_out : out std_logic_vector(13 downto 0);
@@ -87,8 +92,10 @@ end ddr3_transpose;
architecture str of ddr3_transpose is
constant c_min_fifo_size : positive := 256;
constant c_blocksize : positive := g_ddr3_seq.wr_nof_chunks * g_ddr3_seq.wr_chunksize;
- constant c_wr_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size); -- c_blocksize * 2;
- constant c_rd_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size); -- c_blocksize * 2;
+ -- c_blocksize * 2;
+ constant c_wr_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size);
+ -- c_blocksize * 2;
+ constant c_rd_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size);
constant c_total_data_w : natural := g_nof_streams * g_in_dat_w;
constant c_complex_data_w : natural := c_total_data_w * c_nof_complex;
@@ -303,7 +310,8 @@ begin
count => cnt_sop
);
- nof_sop <= INCR_UVEC(cnt_sop, 1); -- +1 because the sop at the sync also counts
+ -- +1 because the sop at the sync also counts
+ nof_sop <= INCR_UVEC(cnt_sop, 1);
nxt_mon_nof_sop <= nof_sop when transpose_in_sosi.sync = '1' else i_mon_nof_sop;
sync_ok_in <= '1' when TO_UINT(i_mon_nof_sop) = g_nof_blk_per_sync and TO_UINT(nof_sop) <= g_nof_blk_per_sync else '0';
@@ -323,7 +331,8 @@ begin
u_sync_bsn_fifo : entity common_lib.common_fifo_sc
generic map (
- g_use_lut => true, -- Make this FIFO in logic, since it's only 2 words deep.
+ -- Make this FIFO in logic, since it's only 2 words deep.
+ g_use_lut => true,
g_reset => false,
g_init => false,
g_dat_w => c_dp_stream_bsn_w,
diff --git a/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd b/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd
index 7d093d8240745146facb1811b6a369bbb1331649..7a8f4d2cd0408a9c591623ee58739810f5d5e13d 100644
--- a/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd
@@ -49,9 +49,11 @@ entity mms_ddr3 is
mm_clk : in std_logic;
ctlr_ref_clk : in std_logic;
- ctlr_rst : in std_logic; -- asynchronous reset input to controller
+ -- asynchronous reset input to controller
+ ctlr_rst : in std_logic;
- ctlr_gen_clk : out std_logic; -- Controller generated clock
+ -- Controller generated clock
+ ctlr_gen_clk : out std_logic;
ctlr_gen_rst : out std_logic;
wr_clk : in std_logic;
diff --git a/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd b/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd
index a3f76a4de78e12b8cdd0a734f0819b34a3c7bb41..ea7183ac786b54c26d26eeba9bccbeafa1edbc93 100644
--- a/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd
+++ b/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd
@@ -49,9 +49,11 @@ entity mms_ddr3_capture is
mm_clk : in std_logic;
ctlr_ref_clk : in std_logic;
- ctlr_rst : in std_logic; -- asynchronous reset input to controller
+ -- asynchronous reset input to controller
+ ctlr_rst : in std_logic;
- ctlr_gen_clk : out std_logic; -- Controller generated clock
+ -- Controller generated clock
+ ctlr_gen_clk : out std_logic;
ctlr_gen_rst : out std_logic;
wr_clk : in std_logic;
@@ -128,7 +130,8 @@ begin
rd_clk => mm_clk,
rd_rst => mm_rst,
- rd_fifo_usedw => rd_fifo_usedw, -- relative to FIFO wr side
+ -- relative to FIFO wr side
+ rd_fifo_usedw => rd_fifo_usedw,
ctrl_mosi => ddr3_mosi,
ctrl_miso => ddr3_miso,
diff --git a/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd b/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd
index 49cac0f0c209e2375bb3808fb67beb8a86fbc42b..a980b8c8422e5c5fd8fc5201064b9c4d6cea3674 100644
--- a/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd
@@ -37,9 +37,11 @@ entity seq_ddr3 is
);
port (
ctlr_ref_clk : in std_logic;
- ctlr_rst : in std_logic; -- asynchronous reset input to controller
+ -- asynchronous reset input to controller
+ ctlr_rst : in std_logic;
- ctlr_gen_clk : out std_logic; -- Controller generated clock
+ -- Controller generated clock
+ ctlr_gen_clk : out std_logic;
ctlr_gen_rst : out std_logic;
wr_clk : in std_logic;
@@ -75,8 +77,10 @@ end seq_ddr3;
architecture str of seq_ddr3 is
constant c_min_fifo_size : positive := 256;
constant c_blocksize : positive := g_ddr3_seq.wr_nof_chunks * g_ddr3_seq.wr_chunksize;
- constant c_wr_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size); -- c_blocksize * 2;
- constant c_rd_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size); -- c_blocksize * 2;
+ -- c_blocksize * 2;
+ constant c_wr_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size);
+ -- c_blocksize * 2;
+ constant c_rd_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size);
signal i_ctlr_gen_rst : std_logic;
signal i_ctlr_gen_clk : std_logic;
diff --git a/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
index 4c6005a9a84132cd378bb8e1c011ca4bf8ffc0dc..86146c9f0e8b06ee92bebf9a1de49b5e6d331348 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
@@ -53,13 +53,17 @@ entity tb_ddr3 is
end entity tb_ddr3;
architecture str of tb_ddr3 is
- constant c_phy : natural := 1; -- 0: ALTMEMPHY 1: UNIPHY_MASTER 2: UNIPHY_SLAVE
- constant c_mts : natural := 800; -- Available options: 800 and 1066
+ -- 0: ALTMEMPHY 1: UNIPHY_MASTER 2: UNIPHY_SLAVE
+ constant c_phy : natural := 1;
+ -- Available options: 800 and 1066
+ constant c_mts : natural := 800;
- constant c_ctlr_ref_clk_per : time := 5 ns; -- 200 MHz
+ -- 200 MHz
+ constant c_ctlr_ref_clk_per : time := 5 ns;
constant c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
- constant c_data_w : natural := 256; -- 32;
+ -- 32;
+ constant c_data_w : natural := 256;
signal ctlr_ref_clk : std_logic := '0';
signal ctlr_rst : std_logic := '1';
@@ -122,7 +126,8 @@ begin
wait until ctlr_init_done = '1';
for i in 0 to 1 loop
- wait until rising_edge(ctlr_gen_clk); -- Give the driver FSM a cycle to go into idle mode
+ -- Give the driver FSM a cycle to go into idle mode
+ wait until rising_edge(ctlr_gen_clk);
end loop;
-- START WRITE
@@ -151,7 +156,8 @@ begin
-- READ DONE
wait until dvr_done = '1';
- wait for 2 us; -- 'Done' means all requests are posted. Wait for the last read data to arrive.
+ -- 'Done' means all requests are posted. Wait for the last read data to arrive.
+ wait for 2 us;
assert snk_diag_res_val = '1' report "[ERROR] DIAG_RES INVALID!" severity FAILURE;
assert snk_diag_res = '0' report "[ERROR] NON-ZERO DIAG_RES!" severity FAILURE;
@@ -215,21 +221,36 @@ begin
DAT_DATA_WIDTH => 32
)
port map (
- mem_a => phy_ou.a(c_ddr.a_w - 1 downto 0), -- memory.mem_a
- mem_ba => phy_ou.ba, -- .mem_ba
- mem_ck => phy_ou.ck, -- .mem_ck
- mem_ck_n => phy_ou.ck_n, -- .mem_ck_n
- mem_cke => phy_ou.cke(c_ddr.cs_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(c_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_dm => phy_ou.dm, -- .mem_dm
- mem_ras_n => ras_n, -- .mem_ras_n
- mem_cas_n => cas_n, -- .mem_cas_n
- mem_we_n => we_n, -- .mem_we_n
- mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
- mem_dq => phy_io.dq, -- .mem_dq
- mem_dqs => phy_io.dqs, -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n, -- .mem_dqs_n
- mem_odt => phy_ou.odt -- .mem_odt
+ -- memory.mem_a
+ mem_a => phy_ou.a(c_ddr.a_w - 1 downto 0),
+ -- .mem_ba
+ mem_ba => phy_ou.ba,
+ -- .mem_ck
+ mem_ck => phy_ou.ck,
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n,
+ -- .mem_cke
+ mem_cke => phy_ou.cke(c_ddr.cs_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(c_ddr.cs_w - 1 downto 0),
+ -- .mem_dm
+ mem_dm => phy_ou.dm,
+ -- .mem_ras_n
+ mem_ras_n => ras_n,
+ -- .mem_cas_n
+ mem_cas_n => cas_n,
+ -- .mem_we_n
+ mem_we_n => we_n,
+ -- .mem_reset_n
+ mem_reset_n => phy_ou.reset_n,
+ -- .mem_dq
+ mem_dq => phy_io.dq,
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs,
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n,
+ -- .mem_odt
+ mem_odt => phy_ou.odt
);
ras_n(0) <= phy_ou.ras_n;
diff --git a/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd b/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
index a9e1cb53c3872c3e5cddc1c6e95ae51db0e4dfe1..b3c42579f163072c027283c5af570285fd52cf9b 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
@@ -113,7 +113,8 @@ architecture tb of tb_ddr3_transpose is
constant c_page_size : positive := c_blocksize * g_nof_blocks;
constant c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
- constant c_mts : natural := 800; -- 1066; --800
+ -- 1066; --800
+ constant c_mts : natural := 800;
constant c_phy : natural := 1;
constant c_data_w : natural := 64;
@@ -127,7 +128,8 @@ architecture tb of tb_ddr3_transpose is
constant c_bg_nof_output_streams : positive := 4;
constant c_bg_buf_dat_w : positive := c_nof_complex * 8;
constant c_bg_buf_adr_w : positive := ceil_log2(c_bg_block_len);
- constant c_bg_data_file_prefix : string := "UNUSED"; -- "../../../src/hex/tb_bg_dat";
+ -- "../../../src/hex/tb_bg_dat";
+ constant c_bg_data_file_prefix : string := "UNUSED";
constant c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, 128, 1);
-- Configuration of the databuffers:
diff --git a/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
index 36e13b7c4385aabb52983a03d86ae9f6905b389e..e0923ed100d9eff99d690f16c3d3892e59ba337a 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
@@ -54,7 +54,8 @@ architecture tb of tb_mms_ddr3 is
----------------------------------------------------------------------------
-- Clocks and resets
----------------------------------------------------------------------------
- constant c_mm_clk_period : time := 8 ns; -- 200 ps;
+ -- 200 ps;
+ constant c_mm_clk_period : time := 8 ns;
constant c_dp_clk_period : time := 5 ns;
constant c_dp_pps_period : natural := 64;
@@ -88,7 +89,8 @@ architecture tb of tb_mms_ddr3 is
-- Compose the Constants for the DUT
constant c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
- constant c_mts : natural := 800; -- 1066; --800
+ -- 1066; --800
+ constant c_mts : natural := 800;
constant c_phy : natural := 1;
constant c_wr_data_w : natural := 64;
constant c_wr_use_ctrl : boolean := false;
@@ -275,7 +277,8 @@ begin
rd_clk => dp_clk,
rd_rst => dp_rst,
- rd_fifo_usedw => open, -- relative to FIFO wr side
+ -- relative to FIFO wr side
+ rd_fifo_usedw => open,
ddr3_in => phy_in,
ddr3_io => phy_io,
diff --git a/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
index fc800b38d513edd0b609061c21a99684ed293e9b..49865535e6a767463182ccebb8377f01e620e07d 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
@@ -62,7 +62,8 @@ architecture tb of tb_seq_ddr3 is
----------------------------------------------------------------------------
-- Clocks and resets
----------------------------------------------------------------------------
- constant c_mm_clk_period : time := 8 ns; -- 200 ps;
+ -- 200 ps;
+ constant c_mm_clk_period : time := 8 ns;
constant c_dp_clk_period : time := 5 ns;
constant c_dp_pps_period : natural := 64;
@@ -106,7 +107,8 @@ architecture tb of tb_seq_ddr3 is
constant c_page_size : positive := c_blocksize * g_nof_blocks;
constant c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
- constant c_mts : natural := 1066; -- 1066; --800
+ -- 1066; --800
+ constant c_mts : natural := 1066;
constant c_phy : natural := 1;
constant c_data_w : natural := 64;
diff --git a/libraries/io/epcs/src/vhdl/epcs_reg.vhd b/libraries/io/epcs/src/vhdl/epcs_reg.vhd
index ba976cc634c979adf20c371e3f36da0f9351c792..515395c8270e2c9fc6ec791d8f0f41694f105f5c 100644
--- a/libraries/io/epcs/src/vhdl/epcs_reg.vhd
+++ b/libraries/io/epcs/src/vhdl/epcs_reg.vhd
@@ -76,11 +76,13 @@ end epcs_reg;
architecture rtl of epcs_reg is
-- For safety, address range unprotection requires the following word to be written:
- constant c_unprotect_passphrase : std_logic_vector(c_word_w - 1 downto 0 ) := x"BEDA221E"; -- "Bedazzle"
+ -- "Bedazzle"
+ constant c_unprotect_passphrase : std_logic_vector(c_word_w - 1 downto 0 ) := x"BEDA221E";
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(6),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 6,
init_sl => '0');
@@ -129,19 +131,24 @@ begin
if sla_in.wrdata(c_word_w - 1 downto 0) = c_unprotect_passphrase then
mm_unprotect_address_range <= '1';
else
- mm_unprotect_address_range <= '0'; -- Writing anything else protects the range again
+ -- Writing anything else protects the range again
+ mm_unprotect_address_range <= '0';
end if;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
when 5 =>
sla_out.rddata(0) <= epcs_out_busy;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/libraries/io/epcs/src/vhdl/mms_epcs.vhd b/libraries/io/epcs/src/vhdl/mms_epcs.vhd
index d7c837f85891751e521a4e7b9a3743d6d1db465f..a13f363c5eb259753e726d1e9bbd48a590b695a6 100644
--- a/libraries/io/epcs/src/vhdl/mms_epcs.vhd
+++ b/libraries/io/epcs/src/vhdl/mms_epcs.vhd
@@ -54,9 +54,12 @@ entity mms_epcs is
generic (
g_technology : natural := c_tech_select_default;
g_sim_flash_model : boolean := false;
- g_protect_addr_range : boolean := false; -- TRUE protects range set below by requiring specific passphrase to be written via MM
- g_protected_addr_lo : natural := 0; -- Byte address
- g_protected_addr_hi : natural := 6029311 -- Byte address, for UniBoard1 this is 23 sectors*1024 pages*256 bytes -1 = 6029311
+ -- TRUE protects range set below by requiring specific passphrase to be written via MM
+ g_protect_addr_range : boolean := false;
+ -- Byte address
+ g_protected_addr_lo : natural := 0;
+ -- Byte address, for UniBoard1 this is 23 sectors*1024 pages*256 bytes -1 = 6029311
+ g_protected_addr_hi : natural := 6029311
);
port (
mm_rst : in std_logic;
@@ -93,7 +96,8 @@ architecture str of mms_epcs is
constant c_fifo_depth_bits : natural := c_epcs_page_size * c_epcs_data_w;
-- FIFO depths relative to epcs and user data widths
- constant c_epcs_fifo_depth : natural := c_fifo_depth_bits / c_epcs_data_w * 2; -- *2 because we need the full depth (without the *2) but we can't 'max out' the FIFO.
+ -- *2 because we need the full depth (without the *2) but we can't 'max out' the FIFO.
+ constant c_epcs_fifo_depth : natural := c_fifo_depth_bits / c_epcs_data_w * 2;
constant c_user_fifo_depth : natural := c_fifo_depth_bits / c_user_data_w;
-- We want to monitor FIFO contents on the user side
signal user_to_epcs_fifo_usedw : std_logic_vector(ceil_log2(c_user_fifo_depth) - 1 downto 0);
diff --git a/libraries/io/epcs/tb/vhdl/tb_mms_epcs.vhd b/libraries/io/epcs/tb/vhdl/tb_mms_epcs.vhd
index 3007341facc88214a23d440573f8f8fc8083ae5b..293e61e9fdc593d69474592ed3d6f7d5cf612802 100644
--- a/libraries/io/epcs/tb/vhdl/tb_mms_epcs.vhd
+++ b/libraries/io/epcs/tb/vhdl/tb_mms_epcs.vhd
@@ -79,10 +79,12 @@ begin
----------------------------------------------------------------------------
mm_rst <= '1', '0' after c_mm_clk_period * 7;
- mm_clk <= not mm_clk after c_mm_clk_period / 2; -- MM clock (125 MHz)
+ -- MM clock (125 MHz)
+ mm_clk <= not mm_clk after c_mm_clk_period / 2;
epcs_rst <= '1', '0' after c_epcs_clk_period * 7;
- epcs_clk <= not epcs_clk after c_epcs_clk_period / 2; -- EPCS clock for ASMI_PARALLEL, 20MHz
+ -- EPCS clock for ASMI_PARALLEL, 20MHz
+ epcs_clk <= not epcs_clk after c_epcs_clk_period / 2;
----------------------------------------------------------------------------
-- Stimuli for MM reg_input slave port
@@ -154,8 +156,10 @@ begin
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
tb_rd_data <= dpmm_data_miso.rddata(c_word_w - 1 downto 0);
- end loop; -- read usedw words
- end loop; -- while usedw>0
+ -- read usedw words
+ end loop;
+ -- while usedw>0
+ end loop;
wait;
end process;
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
index 0e1f4a27346a68a5b3529e6909f6b7425a1c4db6..639dcd924cc0ff0ee08c9a90004e15d28ccb32e8 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
@@ -484,7 +484,8 @@ begin
wait until rising_edge(mm_clk);
proc_tech_tse_setup(c_tech_stratixiv, false, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi);
sim_eth_mm_bus_switch <= '0';
wait;
end process;
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
index a607d66323baea9c444ddb34f40d2d2ac0fc8256..00bebe4426d28dd7fec3a1047921dc3bd076386b 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
@@ -49,16 +49,23 @@ entity unb1_eth_10g is
g_design_name : string := "unb1_eth_10g";
g_design_note : string := "revision info";
g_technology : natural := c_tech_stratixiv;
- g_sim : boolean := false; -- set by ModelSim
- g_sim_unb_nr : natural := 0; -- set by ModelSim
- g_sim_node_nr : natural := 0; -- set by ModelSim
- g_stamp_date : natural := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : natural := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
+ -- set by ModelSim
+ g_sim : boolean := false;
+ -- set by ModelSim
+ g_sim_unb_nr : natural := 0;
+ -- set by ModelSim
+ g_sim_node_nr : natural := 0;
+ -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_date : natural := 0;
+ -- Time (HHMMSS) -- set by QSF
+ g_stamp_time : natural := 0;
+ -- SVN revision -- set by QSF
+ g_stamp_svn : natural := 0
);
port (
-- GENERAL
- CLK : in std_logic; -- dp_clk is generated by SOPC altpll
+ -- dp_clk is generated by SOPC altpll
+ CLK : in std_logic;
PPS : in std_logic;
WDI : out std_logic;
INTA : inout std_logic;
@@ -79,7 +86,8 @@ entity unb1_eth_10g is
ETH_SGOUT : out std_logic;
-- Transceiver clocks
- SA_CLK : in std_logic := '0'; -- SerDes Clock BN-BI / SI_FN
+ -- SerDes Clock BN-BI / SI_FN
+ SA_CLK : in std_logic := '0';
-- Serial I/O: 10GbE receivers
SI_FN_0_TX : out std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
@@ -95,14 +103,16 @@ entity unb1_eth_10g is
SI_FN_1_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_2_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_3_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
- SI_FN_RSTN : out std_logic := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ SI_FN_RSTN : out std_logic := '1'
-- So we need to assign a '1' to it.
);
end unb1_eth_10g;
architecture str of unb1_eth_10g is
-- Firmware version x.y
- constant c_fw_version : t_unb1_board_fw_version := (1, 0); --
+ --
+ constant c_fw_version : t_unb1_board_fw_version := (1, 0);
-- CONSTANT c_eth_packet_size --FIXME
@@ -112,16 +122,21 @@ architecture str of unb1_eth_10g is
constant c_nof_10GbE_streams : natural := c_nof_streams;
constant c_nof_bsn_mon_streams : natural := 5;
- constant c_data_w : natural := 64; -- c_tech_tse_data_w;
+ -- c_tech_tse_data_w;
+ constant c_data_w : natural := 64;
-- Block generator
constant c_bg_addr_w : natural := 9;
constant c_bg_block_size : natural := 365;
- constant c_bg_gapsize : natural := c_bg_block_size / 2; -- Full (no gaps in data) BG output rate = 200MHz * 64b = 12.8Gbps. Including gap size: (365/(365+182))*12.8Gbps=8.54Gbps.
+ -- Full (no gaps in data) BG output rate = 200MHz * 64b = 12.8Gbps. Including gap size: (365/(365+182))*12.8Gbps=8.54Gbps.
+ constant c_bg_gapsize : natural := c_bg_block_size / 2;
constant c_bg_calc_blocks_per_sync : natural := 200000000 / (c_bg_block_size + c_bg_gapsize);
- constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, c_bg_calc_blocks_per_sync); -- 200000*(900+100) = 200000000 cycles = 1 second
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable
- '0', -- enable_sync
+ -- 200000*(900+100) = 200000000 cycles = 1 second
+ constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, c_bg_calc_blocks_per_sync);
+ -- enable
+ constant c_bg_ctrl : t_diag_block_gen := ('0',
+ -- enable_sync
+ '0',
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
@@ -132,16 +147,20 @@ architecture str of unb1_eth_10g is
-- dp_offload_tx
-- . IP total length : 2948 (UDP total lenth) + 20 (Ip header length) = 2968
-- . UDP total length: 8 (UDP header) + 20 (usr header) + 2920 (payload bytes) = 2948 -- 1488
- constant c_ip_length : natural := c_bg_block_size * 8 + 50; -- 2970;
- constant c_udp_length : natural := c_bg_block_size * 8 + 30; -- 2950;
- constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 9 + 1; -- Total header bits = 512
+ -- 2970;
+ constant c_ip_length : natural := c_bg_block_size * 8 + 50;
+ -- 2950;
+ constant c_udp_length : natural := c_bg_block_size * 8 + 30;
+ -- Total header bits = 512
+ constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 9 + 1;
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(c_ip_length) ), -- 1508) ),
+ -- 1508) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(c_ip_length) ),
( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
@@ -152,7 +171,8 @@ architecture str of unb1_eth_10g is
( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(c_udp_length) ), -- 1488) ),
+ -- 1488) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(c_udp_length) ),
( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
@@ -405,8 +425,10 @@ begin
src_in_arr => dp_offload_rx_snk_out_arr,
-- Data to be send by 10G
- snk_out_arr => mms_dp_xonoff_src_in_arr, -- dp_offload_tx_src_in_arr,
- snk_in_arr => mms_dp_xonoff_src_out_arr, -- dp_offload_tx_src_out_arr,
+ -- dp_offload_tx_src_in_arr,
+ snk_out_arr => mms_dp_xonoff_src_in_arr,
+ -- dp_offload_tx_src_out_arr,
+ snk_in_arr => mms_dp_xonoff_src_out_arr,
-- Serial XAUI IO
xaui_tx_arr => xaui_tx_arr,
@@ -426,7 +448,8 @@ begin
generic map (
g_nof_streams => c_nof_streams,
g_buf_dat_w => c_data_w,
- g_buf_addr_w => c_bg_addr_w, -- ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ -- ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_buf_addr_w => c_bg_addr_w,
g_file_name_prefix => "UNUSED",
g_diag_block_gen_rst => c_bg_ctrl
)
@@ -617,8 +640,10 @@ begin
process(hdr_fields_in_arr)
begin
hdr_fields_in_rx_arr <= hdr_fields_in_arr;
- hdr_fields_in_rx_arr(0)(field_hi(c_hdr_field_arr, "eth_dst_mac" ) downto field_lo(c_hdr_field_arr, "eth_dst_mac" )) <= x"00074306C700"; -- jop63
- hdr_fields_in_rx_arr(0)(field_hi(c_hdr_field_arr, "ip_dst_addr" ) downto field_lo(c_hdr_field_arr, "ip_dst_addr" )) <= x"c0a80102"; -- jop63
+ -- jop63
+ hdr_fields_in_rx_arr(0)(field_hi(c_hdr_field_arr, "eth_dst_mac" ) downto field_lo(c_hdr_field_arr, "eth_dst_mac" )) <= x"00074306C700";
+ -- jop63
+ hdr_fields_in_rx_arr(0)(field_hi(c_hdr_field_arr, "ip_dst_addr" ) downto field_lo(c_hdr_field_arr, "ip_dst_addr" )) <= x"c0a80102";
end process;
-----------------------------------------------------------------------------
@@ -627,9 +652,12 @@ begin
u_header_check : entity dp_lib.dp_offload_rx_filter_mm
generic map(
g_bypass => c_bypass_rx_filter,
- g_nof_streams => c_nof_streams, -- : POSITIVE;
- g_data_w => c_data_w, -- : NATURAL;
- g_hdr_field_arr => c_hdr_field_arr -- : t_common_field_arr
+ -- : POSITIVE;
+ g_nof_streams => c_nof_streams,
+ -- : NATURAL;
+ g_data_w => c_data_w,
+ -- : t_common_field_arr
+ g_hdr_field_arr => c_hdr_field_arr
)
port map(
@@ -710,8 +738,10 @@ begin
reg_data_buf_mosi => reg_diag_data_buffer_mosi,
reg_data_buf_miso => reg_diag_data_buffer_miso,
- in_sync => dp_offload_rx_filter_src_out_arr(0).sync, -- dp_offload_rx_src_out_arr(0).sync,
- in_sosi_arr => dp_offload_rx_filter_src_out_arr -- dp_offload_rx_src_out_arr
+ -- dp_offload_rx_src_out_arr(0).sync,
+ in_sync => dp_offload_rx_filter_src_out_arr(0).sync,
+ -- dp_offload_rx_src_out_arr
+ in_sosi_arr => dp_offload_rx_filter_src_out_arr
);
-----------------------------------------------------------------------------
diff --git a/libraries/io/eth/designs/unb1_eth_10g/tb/vhdl/tb_unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/tb/vhdl/tb_unb1_eth_10g.vhd
index c5c71f81fa43ba7a20ca0d14a1c3fa3a97b55141..f31ad15dfd2ec25f5fb48d63538f8ba8a4672983 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/tb/vhdl/tb_unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/tb/vhdl/tb_unb1_eth_10g.vhd
@@ -50,9 +50,12 @@ end tb_unb1_eth_10g;
architecture tb of tb_unb1_eth_10g is
constant c_sim : boolean := true;
- constant c_unb1_board_nr : natural := 0; -- UniBoard 0
- constant c_node_nr_lcu : natural := 3; -- FN3
- constant c_node_nr_dut : natural := 2; -- FN2
+ -- UniBoard 0
+ constant c_unb1_board_nr : natural := 0;
+ -- FN3
+ constant c_node_nr_lcu : natural := 3;
+ -- FN2
+ constant c_node_nr_dut : natural := 2;
constant c_id_lcu : std_logic_vector(7 downto 0) := TO_UVEC(c_unb1_board_nr, c_unb1_board_nof_uniboard_w ) & TO_UVEC(c_node_nr_lcu, c_unb1_board_nof_chip_w);
constant c_id_dut : std_logic_vector(7 downto 0) := TO_UVEC(c_unb1_board_nr, c_unb1_board_nof_uniboard_w ) & TO_UVEC(c_node_nr_dut, c_unb1_board_nof_chip_w);
constant c_version : std_logic_vector(1 downto 0) := "00";
@@ -85,8 +88,10 @@ begin
----------------------------------------------------------------------------
-- Externally generated clocks
----------------------------------------------------------------------------
- clk <= not clk after c_clk_period / 2; -- External clock (200 MHz)
- eth_clk <= not eth_clk after c_eth_clk_period / 2; -- Ethernet ref clock (25 MHz)
+ -- External clock (200 MHz)
+ clk <= not clk after c_clk_period / 2;
+ -- Ethernet ref clock (25 MHz)
+ eth_clk <= not eth_clk after c_eth_clk_period / 2;
sa_clk <= not sa_clk after c_sa_clk_period / 2;
------------------------------------------------------------------------------
diff --git a/libraries/io/eth/src/vhdl/avs2_eth.vhd b/libraries/io/eth/src/vhdl/avs2_eth.vhd
index 2171c73796e907dd156c99b587f5a5e47e508da5..70cf96de22d7f60e98302d6daf8525a1bbf479dd 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth.vhd
+++ b/libraries/io/eth/src/vhdl/avs2_eth.vhd
@@ -98,11 +98,14 @@ architecture wrap of avs2_eth is
signal udp_rx_src_in_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0);
-- MM interface
- signal tse_sla_in : t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ signal tse_sla_in : t_mem_mosi;
signal tse_sla_out : t_mem_miso;
- signal reg_sla_in : t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ signal reg_sla_in : t_mem_mosi;
signal reg_sla_out : t_mem_miso;
- signal ram_sla_in : t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- ETH rx frame and tx frame memory
+ signal ram_sla_in : t_mem_mosi;
signal ram_sla_out : t_mem_miso;
-- LED interface
@@ -110,8 +113,10 @@ architecture wrap of avs2_eth is
begin
-- Run internal ST at MM clock
-- Disable UDP off-load interface
- udp_tx_snk_in_arr <= (others => c_dp_sosi_rst); -- default not valid if not used
- udp_rx_src_in_arr <= (others => c_dp_siso_rdy); -- default ready if not used
+ -- default not valid if not used
+ udp_tx_snk_in_arr <= (others => c_dp_sosi_rst);
+ -- default ready if not used
+ udp_rx_src_in_arr <= (others => c_dp_siso_rdy);
-- TSE MAC
-- . MOSI
@@ -152,11 +157,16 @@ begin
u_eth : entity work.eth
port map (
-- Clocks and reset
- mm_rst => csi_mm_reset, -- reset synchronous with mm_clk
- mm_clk => csi_mm_clk, -- memory-mapped bus clock
- eth_clk => coe_eth_clk_export, -- ethernet phy reference clock
- st_rst => csi_mm_reset, -- reset synchronous with st_clk
- st_clk => csi_mm_clk, -- packet stream clock
+ -- reset synchronous with mm_clk
+ mm_rst => csi_mm_reset,
+ -- memory-mapped bus clock
+ mm_clk => csi_mm_clk,
+ -- ethernet phy reference clock
+ eth_clk => coe_eth_clk_export,
+ -- reset synchronous with st_clk
+ st_rst => csi_mm_reset,
+ -- packet stream clock
+ st_clk => csi_mm_clk,
-- UDP transmit interface
udp_tx_snk_in_arr => udp_tx_snk_in_arr,
@@ -166,12 +176,16 @@ begin
udp_rx_src_out_arr => OPEN,
-- Memory Mapped Slaves
- tse_sla_in => tse_sla_in, -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ tse_sla_in => tse_sla_in,
tse_sla_out => tse_sla_out,
- reg_sla_in => reg_sla_in, -- ETH control and status registers
+ -- ETH control and status registers
+ reg_sla_in => reg_sla_in,
reg_sla_out => reg_sla_out,
- reg_sla_interrupt => ins_interrupt_irq, -- ETH interrupt
- ram_sla_in => ram_sla_in, -- ETH rx frame and tx frame memory
+ -- ETH interrupt
+ reg_sla_interrupt => ins_interrupt_irq,
+ -- ETH rx frame and tx frame memory
+ ram_sla_in => ram_sla_in,
ram_sla_out => ram_sla_out,
-- PHY interface
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd b/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
index d648f26fb1cb1a3e9c804714afad5c500ffa4798..048d776d65de66af1f7b85555885b9324efb707b 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
@@ -45,25 +45,30 @@ entity avs2_eth_coe is
mms_tse_write : in std_logic;
mms_tse_read : in std_logic;
mms_tse_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_tse_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 0
- mms_tse_waitrequest : out std_logic; -- necessary because read latency is 0
+ -- read latency is 0
+ mms_tse_readdata : out std_logic_vector(c_word_w - 1 downto 0);
+ -- necessary because read latency is 0
+ mms_tse_waitrequest : out std_logic;
-- ETH registers
mms_reg_address : in std_logic_vector(c_eth_reg_addr_w - 1 downto 0);
mms_reg_write : in std_logic;
mms_reg_read : in std_logic;
mms_reg_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_reg_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 1
+ -- read latency is 1
+ mms_reg_readdata : out std_logic_vector(c_word_w - 1 downto 0);
-- ETH packet RAM
mms_ram_address : in std_logic_vector(c_eth_ram_addr_w - 1 downto 0);
mms_ram_write : in std_logic;
mms_ram_read : in std_logic;
mms_ram_writedata : in std_logic_vector(c_word_w - 1 downto 0);
- mms_ram_readdata : out std_logic_vector(c_word_w - 1 downto 0); -- read latency is 2
+ -- read latency is 2
+ mms_ram_readdata : out std_logic_vector(c_word_w - 1 downto 0);
-- Interrupt Sender interface
- ins_interrupt_irq : out std_logic; -- relates to the ETH registers port
+ -- relates to the ETH registers port
+ ins_interrupt_irq : out std_logic;
----------------------------------------------------------------------------
-- User side
diff --git a/libraries/io/eth/src/vhdl/eth.vhd b/libraries/io/eth/src/vhdl/eth.vhd
index 1906bdf36dd1c4a233978c6a4135f43b0d0d166b..6296a0d5748d2ae2d574c1adedfdca821a943ee1 100644
--- a/libraries/io/eth/src/vhdl/eth.vhd
+++ b/libraries/io/eth/src/vhdl/eth.vhd
@@ -42,42 +42,60 @@ use technology_lib.technology_select_pkg.all;
entity eth is
generic (
g_technology : natural := c_tech_select_default;
- g_init_ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := X"00000000"; -- 0.0.0.0
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_ETH_PHY : string := "LVDS"; -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+ -- 0.0.0.0
+ g_init_ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := X"00000000";
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
+ -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+ g_ETH_PHY : string := "LVDS";
g_ihl20 : boolean := false;
- g_frm_discard_en : boolean := false; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+ -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+ g_frm_discard_en : boolean := false;
g_sim : boolean := false;
- g_sim_level : natural := 0 -- when g_sim = TRUE, then 0 = use IP; 1 = use fast serdes model
+ -- when g_sim = TRUE, then 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- eth_clk : in std_logic; -- ethernet phy reference clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- packet stream clock
-
- cal_rec_clk : in std_logic := '0'; -- Calibration & reconfig clock when using XCVR
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- ethernet phy reference clock
+ eth_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- packet stream clock
+ st_clk : in std_logic;
+
+ -- Calibration & reconfig clock when using XCVR
+ cal_rec_clk : in std_logic := '0';
-- UDP transmit interface
- udp_tx_snk_in_arr : in t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_sosi_rst); -- ST sinks, default not valid if not used
+ -- ST sinks, default not valid if not used
+ udp_tx_snk_in_arr : in t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_sosi_rst);
udp_tx_snk_out_arr : out t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0);
-- UDP receive interface
- udp_rx_src_in_arr : in t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_siso_rdy); -- ST sources, default ready if not used
+ -- ST sources, default ready if not used
+ udp_rx_src_in_arr : in t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_siso_rdy);
udp_rx_src_out_arr : out t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0);
-- Memory Mapped Slaves
- tse_sla_in : in t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ tse_sla_in : in t_mem_mosi;
tse_sla_out : out t_mem_miso;
- reg_sla_in : in t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ reg_sla_in : in t_mem_mosi;
reg_sla_out : out t_mem_miso;
- reg_sla_interrupt : out std_logic; -- Interrupt
- ram_sla_in : in t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ reg_sla_interrupt : out std_logic;
+ -- ETH rx frame and tx frame memory
+ ram_sla_in : in t_mem_mosi;
ram_sla_out : out t_mem_miso;
-- Monitoring
- rx_flushed_frm_cnt : out std_logic_vector(c_word_w - 1 downto 0); -- only used in simulation, because it will get optimized away in synthesis
+ -- only used in simulation, because it will get optimized away in synthesis
+ rx_flushed_frm_cnt : out std_logic_vector(c_word_w - 1 downto 0);
-- PHY interface
eth_txp : out std_logic;
@@ -100,19 +118,25 @@ architecture str of eth is
nof_dat => c_eth_ram_nof_words,
init_sl => '0');
- signal mem_in : t_mem_mosi; -- big endian on ST and TSE MAC network side
- signal mem_out : t_mem_miso; -- big endian on ST and TSE MAC network side
- signal mem_in_endian : t_mem_mosi; -- keep big endian on MM side
- signal mem_out_endian : t_mem_miso; -- keep big endian on MM side
+ -- big endian on ST and TSE MAC network side
+ signal mem_in : t_mem_mosi;
+ -- big endian on ST and TSE MAC network side
+ signal mem_out : t_mem_miso;
+ -- keep big endian on MM side
+ signal mem_in_endian : t_mem_mosi;
+ -- keep big endian on MM side
+ signal mem_out_endian : t_mem_miso;
------------------------------------------------------------------------------
-- ETH stream
------------------------------------------------------------------------------
-- Multiplex - demultiplex
- constant c_mux_nof_ports : natural := 1 + c_eth_nof_udp_ports; -- One for control + nof UDP ports
+ -- One for control + nof UDP ports
+ constant c_mux_nof_ports : natural := 1 + c_eth_nof_udp_ports;
constant c_demux_nof_ports : natural := c_mux_nof_ports;
- constant c_demux_combined : boolean := false; -- when TRUE then all downstream sinks must be ready, when FALSE then only the
+ -- when TRUE then all downstream sinks must be ready, when FALSE then only the
+ constant c_demux_combined : boolean := false;
-- selected sink needs to be ready (see dp_demux for more explanation).
-- All Rx (so UDP off-load and other ETH traffic)
signal rx_adapt_siso : t_dp_siso;
@@ -264,8 +288,10 @@ begin
u_adapt : entity dp_lib.dp_latency_adapter
generic map (
- g_in_latency => c_eth_rx_ready_latency, -- = 2
- g_out_latency => c_eth_ready_latency -- = 1
+ -- = 2
+ g_in_latency => c_eth_rx_ready_latency,
+ -- = 1
+ g_out_latency => c_eth_ready_latency
)
port map (
rst => st_rst,
@@ -288,14 +314,17 @@ begin
clk => st_clk,
-- Streaming Sink
- snk_in_err => rx_adapt_sosi.err(c_tech_tse_error_w - 1 downto 0), -- preserve error field from TSE MAC stream
+ -- preserve error field from TSE MAC stream
+ snk_in_err => rx_adapt_sosi.err(c_tech_tse_error_w - 1 downto 0),
snk_in => rx_adapt_sosi,
snk_out => rx_adapt_siso,
-- Streaming Source
src_in => rx_crc_siso,
- src_out => rx_crc_sosi, -- replaced CRC word by snk_in_err, so CRC word /=0 indicates any TSE error
- src_out_err => open -- flag snk_in_err/=0 at src_out.eop
+ -- replaced CRC word by snk_in_err, so CRC word /=0 indicates any TSE error
+ src_out => rx_crc_sosi,
+ -- flag snk_in_err/=0 at src_out.eop
+ src_out_err => open
);
------------------------------------------------------------------------------
@@ -450,9 +479,12 @@ begin
-- Streaming Source
-- . The src_rd, src_ack and src_done act instead of src_in.ready to have src_in ready per frame instead of per data word
- src_rd => rx_frame_rd, -- request frame pulse
- src_ack => rx_frame_ack, -- acknowledge request
- src_done => rx_frame_done, -- signal frame received
+ -- request frame pulse
+ src_rd => rx_frame_rd,
+ -- acknowledge request
+ src_ack => rx_frame_ack,
+ -- signal frame received
+ src_done => rx_frame_done,
src_out => rx_frame_sosi,
-- Monitoring
@@ -574,17 +606,21 @@ begin
g_use_error => false,
g_nof_input => c_mux_nof_ports,
g_use_fifo => false,
- g_fifo_size => array_init(1024, c_mux_nof_ports), -- input FIFOs are not used, but generic must match g_nof_input
- g_fifo_fill => array_init( 0, c_mux_nof_ports) -- input FIFOs are not used, but generic must match g_nof_input
+ -- input FIFOs are not used, but generic must match g_nof_input
+ g_fifo_size => array_init(1024, c_mux_nof_ports),
+ -- input FIFOs are not used, but generic must match g_nof_input
+ g_fifo_fill => array_init( 0, c_mux_nof_ports)
)
port map (
rst => st_rst,
clk => st_clk,
-- ST sinks
- snk_out_arr => mux_siso_arr, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out_arr => mux_siso_arr,
snk_in_arr => mux_sosi_arr,
-- ST source
- src_in => tx_mux_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => tx_mux_siso,
src_out => tx_mux_sosi
);
@@ -615,9 +651,11 @@ begin
-- TSE MAC
------------------------------------------------------------------------------
tx_hdr_siso <= tse_tx_siso;
- tse_tx_sosi <= func_dp_stream_error_set(tx_hdr_sosi, 0); -- set err field (value 0 for OK)
+ -- set err field (value 0 for OK)
+ tse_tx_sosi <= func_dp_stream_error_set(tx_hdr_sosi, 0);
- tse_tx_mac_in.crc_fwd <= '0'; -- when '0' then TSE MAC generates the TX CRC field
+ -- when '0' then TSE MAC generates the TX CRC field
+ tse_tx_mac_in.crc_fwd <= '0';
u_tech_tse : entity tech_tse_lib.tech_tse
generic map (
@@ -645,7 +683,8 @@ begin
tx_snk_out => tse_tx_siso,
-- . MAC specific
tx_mac_in => tse_tx_mac_in,
- tx_mac_out => tse_tx_mac_out, -- OPEN
+ -- OPEN
+ tx_mac_out => tse_tx_mac_out,
-- MAC receive interface
-- . ST Source
rx_src_in => tse_rx_siso,
diff --git a/libraries/io/eth/src/vhdl/eth_buffer.vhd b/libraries/io/eth/src/vhdl/eth_buffer.vhd
index 957ce8ecae7f891691d35a5ca1caa545338ae70c..cbb10e4af786919f25b5c5af77e5ca3100400be0 100644
--- a/libraries/io/eth/src/vhdl/eth_buffer.vhd
+++ b/libraries/io/eth/src/vhdl/eth_buffer.vhd
@@ -39,18 +39,24 @@ entity eth_buffer is
);
port (
-- Clocks and reset
- rst : in std_logic; -- reset synchronous with clk
- clk : in std_logic; -- packet stream clock
+ -- reset synchronous with clk
+ rst : in std_logic;
+ -- packet stream clock
+ clk : in std_logic;
-- Streaming Sink
snk_in : in t_dp_sosi;
- snk_out : out t_dp_siso := c_dp_siso_rdy; -- internal u_fifo is always ready for packet data
+ -- internal u_fifo is always ready for packet data
+ snk_out : out t_dp_siso := c_dp_siso_rdy;
-- Streaming Source
-- . The src_rd, src_ack and src_done act instead of src_in.ready to have src_in ready per frame instead of per data word
- src_rd : in std_logic; -- a pulse causes the next frame to sourced out from the internal u_fifo if available
- src_ack : out std_logic; -- acknowledge the src_rd pulse
- src_done : out std_logic; -- frame received
+ -- a pulse causes the next frame to sourced out from the internal u_fifo if available
+ src_rd : in std_logic;
+ -- acknowledge the src_rd pulse
+ src_ack : out std_logic;
+ -- frame received
+ src_done : out std_logic;
src_out : out t_dp_sosi;
-- Monitoring
@@ -59,9 +65,11 @@ entity eth_buffer is
end eth_buffer;
architecture str of eth_buffer is
- constant c_nof_frames : natural := 2; -- support at least 2 max size frames in the FIFO
+ -- support at least 2 max size frames in the FIFO
+ constant c_nof_frames : natural := 2;
constant c_fifo_nof_words : natural := 2**(ceil_log2(c_nof_frames * c_eth_frame_nof_words));
- constant c_fifo_almost_full : natural := c_fifo_nof_words - 32; -- little margin is sufficient, because flush u_fifo will start immediately
+ -- little margin is sufficient, because flush u_fifo will start immediately
+ constant c_fifo_almost_full : natural := c_fifo_nof_words - 32;
type t_state_enum is (
s_idle,
@@ -139,7 +147,8 @@ begin
rst => rst,
clk => clk,
-- ST sink
- snk_out => OPEN, -- the frame FIFO can not get full, because frames will get flushed when it is almost full
+ -- the frame FIFO can not get full, because frames will get flushed when it is almost full
+ snk_out => OPEN,
snk_in => snk_in,
usedw => fifo_usedw,
-- ST source
@@ -205,16 +214,20 @@ begin
if frm_ack = '1' then
nxt_src_ack <= '1';
if frm_busy = '0' then
- nxt_state <= s_idle; -- the u_fifo was empty, allow host to request src_rd again
+ -- the u_fifo was empty, allow host to request src_rd again
+ nxt_state <= s_idle;
end if;
end if;
if frm_done = '1' then
- nxt_src_done <= '1'; -- indicate that new rx frame is available
+ -- indicate that new rx frame is available
+ nxt_src_done <= '1';
nxt_state <= s_idle;
end if;
- when others => -- s_flush
+ -- s_flush
+ when others =>
if frm_done = '1' then
- nxt_src_ack <= '1'; -- acknowledge a src_rd that may have occured during flush, allow host to request src_rd again
+ -- acknowledge a src_rd that may have occured during flush, allow host to request src_rd again
+ nxt_src_ack <= '1';
nxt_flushed_frm_cnt <= INCR_UVEC(i_flushed_frm_cnt, 1);
nxt_state <= s_idle;
end if;
diff --git a/libraries/io/eth/src/vhdl/eth_checksum.vhd b/libraries/io/eth/src/vhdl/eth_checksum.vhd
index a07bd80977169ec968030a3651ac23e67e7a9d6d..5d62c05890598da41c5a8fc85781fafa5453a1a2 100644
--- a/libraries/io/eth/src/vhdl/eth_checksum.vhd
+++ b/libraries/io/eth/src/vhdl/eth_checksum.vhd
@@ -69,12 +69,14 @@ architecture rtl of eth_checksum is
signal prev_in_eop : std_logic;
signal prev_in_eop_dly : std_logic;
- signal word_sum_cin : unsigned(0 downto 0); -- carry in
+ -- carry in
+ signal word_sum_cin : unsigned(0 downto 0);
signal word_sum_dat : unsigned(c_halfword_w - 1 downto 0);
signal word_sum : unsigned(c_halfword_w downto 0);
signal nxt_word_sum : unsigned(c_halfword_w downto 0);
- signal sum_cin : unsigned(0 downto 0); -- carry in
+ -- carry in
+ signal sum_cin : unsigned(0 downto 0);
signal sum_dat : unsigned(c_halfword_w - 1 downto 0);
signal sum : unsigned(c_halfword_w downto 0);
signal nxt_sum : unsigned(c_halfword_w downto 0);
@@ -146,7 +148,8 @@ begin
sum;
-- Accumulate the last carry
- last_dat <= sum(c_halfword_w - 1 downto 0) + sum_cin + word_sum_cin; -- Also add word_sum_cin in the case that the last word has a carry.
+ -- Also add word_sum_cin in the case that the last word has a carry.
+ last_dat <= sum(c_halfword_w - 1 downto 0) + sum_cin + word_sum_cin;
-- Checksum is 1-complement of the sum
nxt_checksum <= not(std_logic_vector(last_dat)) when prev_in_eop_dly = '1' else i_checksum;
diff --git a/libraries/io/eth/src/vhdl/eth_control.vhd b/libraries/io/eth/src/vhdl/eth_control.vhd
index 35ea4905fa6aaeaffce2c6b99704b78cbebb6916..a3e2a4b9fec5fb95eadbdff6ffdecc3fdc612230 100644
--- a/libraries/io/eth/src/vhdl/eth_control.vhd
+++ b/libraries/io/eth/src/vhdl/eth_control.vhd
@@ -38,16 +38,19 @@ entity eth_control is
-- Control registers
reg_config : in t_eth_mm_reg_config;
reg_control : in t_eth_mm_reg_control;
- reg_continue_wr : in std_logic; -- used to know that control reg has been written and ETH module can continue from TX_PENDING state
+ -- used to know that control reg has been written and ETH module can continue from TX_PENDING state
+ reg_continue_wr : in std_logic;
reg_status : out t_eth_mm_reg_status;
- reg_status_wr : in std_logic; -- used to know that status reg has been read and can be cleared to remove the sla_interrupt
+ -- used to know that status reg has been read and can be cleared to remove the sla_interrupt
+ reg_status_wr : in std_logic;
-- Streaming sink Rx frame
-- . The rcv_rd, rcv_ack and rcv_done act instead of rcv_out.ready to have rcv_out ready per frame instead of per data word
rcv_rd : out std_logic;
rcv_ack : in std_logic;
rcv_done : in std_logic;
- rcv_in : in t_dp_sosi; -- packet memory is always ready for packet data
+ -- packet memory is always ready for packet data
+ rcv_in : in t_dp_sosi;
rcv_hdr_words_arr : in t_network_total_header_32b_arr;
rcv_hdr_status : in t_eth_hdr_status;
@@ -63,7 +66,8 @@ end eth_control;
architecture rtl of eth_control is
-- Internal source ready latency of this component
- constant c_this_src_latency : natural := 1; -- xmt_in, xmt_out
+ -- xmt_in, xmt_out
+ constant c_this_src_latency : natural := 1;
type t_state_enum is (
s_idle,
@@ -108,7 +112,8 @@ architecture rtl of eth_control is
signal i_mem_in : t_mem_mosi;
signal nxt_mem_in : t_mem_mosi;
- signal rd_val : std_logic_vector(0 to c_mem_ram_rd_latency); -- use [0] to combinatorially store rd (= rd_en)
+ -- use [0] to combinatorially store rd (= rd_en)
+ signal rd_val : std_logic_vector(0 to c_mem_ram_rd_latency);
signal nxt_rd_val : std_logic_vector(1 to c_mem_ram_rd_latency);
signal rd_sop : std_logic_vector( rd_val'range);
signal nxt_rd_sop : std_logic_vector(nxt_rd_val'range);
@@ -212,10 +217,12 @@ begin
nxt_mem_in.wr <= '1';
end if;
if rcv_in.sop = '1' then
- nxt_mem_in.address <= TO_MEM_ADDRESS(c_eth_ram_rx_offset); -- rx buffer starts at address 0
+ -- rx buffer starts at address 0
+ nxt_mem_in.address <= TO_MEM_ADDRESS(c_eth_ram_rx_offset);
end if;
-- Prepare the Tx header
- if hdr_en = '1' then -- tx buffer starts at address 380
+ -- tx buffer starts at address 380
+ if hdr_en = '1' then
nxt_mem_in.address <= TO_MEM_ADDRESS(c_eth_ram_tx_offset + hdr_word_cnt);
nxt_mem_in.wrdata <= RESIZE_MEM_DATA(hdr_response_arr(hdr_word_cnt));
nxt_mem_in.wr <= '1';
@@ -227,7 +234,8 @@ begin
nxt_xmt_word_cnt <= xmt_word_cnt;
if xmt_siso.ready = '1' then
nxt_mem_in.rd <= '1';
- nxt_xmt_word_cnt <= xmt_word_cnt + 1; -- rd_en side counter
+ -- rd_en side counter
+ nxt_xmt_word_cnt <= xmt_word_cnt + 1;
end if;
end if;
end process;
@@ -254,8 +262,10 @@ begin
-- adapt mem read latency to xmt ready latency
u_xmt_out_adapter : entity dp_lib.dp_latency_adapter
generic map (
- g_in_latency => c_mem_ram_rd_latency + 1, -- = 2 + 1 latency for xmt_siso.ready -> nxt_mem_in.rd
- g_out_latency => c_this_src_latency -- = 1
+ -- = 2 + 1 latency for xmt_siso.ready -> nxt_mem_in.rd
+ g_in_latency => c_mem_ram_rd_latency + 1,
+ -- = 1
+ g_out_latency => c_this_src_latency
)
port map (
rst => rst,
@@ -302,47 +312,64 @@ begin
p_state : process(state, reg_control, reg_continue_wr, rcv_in, rcv_ack, rcv_done, hdr_word_cnt, xmt_siso, xmt_word_cnt, tx_nof_words, xmt_done)
begin
- nxt_rcv_rd <= '0'; -- read frame start pulse
- nxt_hdr_en <= '0'; -- prepare response header enable
- nxt_hdr_done <= '0'; -- prepare response header done
- nxt_tx_insert <= '0'; -- accept tx insert request
- nxt_xmt_start <= '0'; -- write frame start pulse
- nxt_xmt_en <= '0'; -- write frame enable
+ -- read frame start pulse
+ nxt_rcv_rd <= '0';
+ -- prepare response header enable
+ nxt_hdr_en <= '0';
+ -- prepare response header done
+ nxt_hdr_done <= '0';
+ -- accept tx insert request
+ nxt_tx_insert <= '0';
+ -- write frame start pulse
+ nxt_xmt_start <= '0';
+ -- write frame enable
+ nxt_xmt_en <= '0';
nxt_state <= state;
case state is
when s_idle =>
- if reg_control.tx_request = '1' then -- MM master requests to insert an extra tx frame
+ -- MM master requests to insert an extra tx frame
+ if reg_control.tx_request = '1' then
nxt_tx_insert <= '1';
nxt_state <= s_tx_pending;
end if;
- if reg_control.rx_en = '1' then -- MM master enables default Rx-Tx operation so request a new rx frame
+ -- MM master enables default Rx-Tx operation so request a new rx frame
+ if reg_control.rx_en = '1' then
nxt_rcv_rd <= '1';
nxt_state <= s_rx_request;
end if;
when s_rx_request =>
- if rcv_in.sop = '1' then -- busy receiving a new frame (best check for sop, so no need to check rcv_busy, rcv_err in eth_rx_frame)
+ -- busy receiving a new frame (best check for sop, so no need to check rcv_busy, rcv_err in eth_rx_frame)
+ if rcv_in.sop = '1' then
nxt_state <= s_rx_frame;
- elsif rcv_ack = '1' then -- rcv ack with no rcv sop, so there was no rx frame pending, try request again
+ -- rcv ack with no rcv sop, so there was no rx frame pending, try request again
+ elsif rcv_ack = '1' then
nxt_state <= s_idle;
end if;
when s_rx_frame =>
- if rcv_done = '1' then -- frame received
+ -- frame received
+ if rcv_done = '1' then
nxt_state <= s_hdr_response;
end if;
- when s_hdr_response => -- prepare tx header for rx response
+ -- prepare tx header for rx response
+ when s_hdr_response =>
if hdr_word_cnt < c_network_total_header_32b_nof_words - 1 then
nxt_hdr_en <= '1';
else
- nxt_hdr_done <= '1'; -- new frame received and response prepared
+ -- new frame received and response prepared
+ nxt_hdr_done <= '1';
nxt_state <= s_tx_pending;
end if;
- when s_tx_pending => -- wait for MM master
- if reg_continue_wr = '1' then -- MM master done
- if reg_control.tx_en = '1' then -- continue with response tx frame
+ -- wait for MM master
+ when s_tx_pending =>
+ -- MM master done
+ if reg_continue_wr = '1' then
+ -- continue with response tx frame
+ if reg_control.tx_en = '1' then
nxt_xmt_start <= '1';
nxt_state <= s_tx_frame;
- else -- do not response tx frame
+ -- do not response tx frame
+ else
nxt_state <= s_idle;
end if;
end if;
@@ -350,11 +377,14 @@ begin
if xmt_siso.ready = '0' or xmt_word_cnt < unsigned(tx_nof_words) - 1 then
nxt_xmt_en <= '1';
else
- nxt_state <= s_tx_done; -- frame transmitted
+ -- frame transmitted
+ nxt_state <= s_tx_done;
end if;
- when others => -- s_tx_done
+ -- s_tx_done
+ when others =>
if xmt_done = '1' then
- nxt_state <= s_idle; -- frame transmitted, to be safe wait for xmt_done
+ -- frame transmitted, to be safe wait for xmt_done
+ nxt_state <= s_idle;
end if;
end case;
end process;
diff --git a/libraries/io/eth/src/vhdl/eth_crc_ctrl.vhd b/libraries/io/eth/src/vhdl/eth_crc_ctrl.vhd
index cca9ed98fb289e57e9ecace746e8f0979463b474..71565b9a0fa9ddb328efb92430b999304c1b966b 100644
--- a/libraries/io/eth/src/vhdl/eth_crc_ctrl.vhd
+++ b/libraries/io/eth/src/vhdl/eth_crc_ctrl.vhd
@@ -42,19 +42,23 @@ entity eth_crc_ctrl is
clk : in std_logic;
-- Streaming Sink
- snk_in_err : in std_logic_vector; -- error vector from TSE MAC t_eth_stream
+ -- error vector from TSE MAC t_eth_stream
+ snk_in_err : in std_logic_vector;
snk_in : in t_dp_sosi;
snk_out : out t_dp_siso;
-- Streaming Source
src_in : in t_dp_siso;
- src_out : out t_dp_sosi; -- replaced CRC word by snk_in_err, so CRC word /=0 indicates any TSE error
- src_out_err : out std_logic -- flag snk_in_err/=0 at src_out.eop
+ -- replaced CRC word by snk_in_err, so CRC word /=0 indicates any TSE error
+ src_out : out t_dp_sosi;
+ -- flag snk_in_err/=0 at src_out.eop
+ src_out_err : out std_logic
);
end eth_crc_ctrl;
architecture rtl of eth_crc_ctrl is
- constant c_tail_nof_words : natural := 2; -- if empty /=0 then the CRC is straddled over the last two packet words
+ -- if empty /=0 then the CRC is straddled over the last two packet words
+ constant c_tail_nof_words : natural := 2;
constant c_tail_high : natural := c_tail_nof_words - 1;
signal i_src_out : t_dp_sosi;
@@ -93,7 +97,8 @@ begin
rst => rst,
clk => clk,
in_sop => i_src_out.sop,
- in_eop => in_err_hold(0), -- Checking only bit [0] is sufficient, because bit [0] contains the logic OR of bits [5:1]
+ -- Checking only bit [0] is sufficient, because bit [0] contains the logic OR of bits [5:1]
+ in_eop => in_err_hold(0),
eop_extend => src_out_err
);
@@ -108,7 +113,8 @@ begin
-- tail replace: replace the CRC word with the in_err when the eop has arrived
if cur_tail_inputs(0).eop = '1' then
- new_tail_inputs(0).data(c_eth_data_w - 1 downto 0) <= in_err; -- cur_tail_inputs(0).empty = 0
+ -- cur_tail_inputs(0).empty = 0
+ new_tail_inputs(0).data(c_eth_data_w - 1 downto 0) <= in_err;
case to_integer(unsigned(cur_tail_inputs(0).empty(c_eth_empty_w - 1 downto 0))) is
when 1 => new_tail_inputs(0).data(c_eth_data_w - 1 downto 0) <= in_err(3 * c_byte_w - 1 downto 0) & c_slv0(1 * c_byte_w - 1 downto 0);
new_tail_inputs(1).data(c_eth_data_w - 1 downto 0) <= cur_tail_inputs(1).data(4 * c_byte_w - 1 downto 1 * c_byte_w) & in_err(4 * c_byte_w - 1 downto 3 * c_byte_w);
diff --git a/libraries/io/eth/src/vhdl/eth_crc_word.vhd b/libraries/io/eth/src/vhdl/eth_crc_word.vhd
index b848b5e0b3a7cbb794c679bab9a521210d842814..835214db94e9487a1d306bbf0980106d10793acb 100644
--- a/libraries/io/eth/src/vhdl/eth_crc_word.vhd
+++ b/libraries/io/eth/src/vhdl/eth_crc_word.vhd
@@ -68,7 +68,8 @@ architecture rtl of eth_crc_word is
begin
-- Direct connection between snk and src to support series connection of this component in a stream
src_out <= snk_in;
- snk_out <= src_in; -- default this component is always ready thanks to c_eth_stream_rdy, but the downstream component may overrule this
+ -- default this component is always ready thanks to c_eth_stream_rdy, but the downstream component may overrule this
+ snk_out <= src_in;
crc_word <= i_crc_word;
crc_word_val <= i_crc_word_val;
diff --git a/libraries/io/eth/src/vhdl/eth_frm_discard.vhd b/libraries/io/eth/src/vhdl/eth_frm_discard.vhd
index 19b1deed09cc7750f238d67cbb2661ff9a695e1f..cb257c347e0b338a98018377e6eeb37316bd4115 100644
--- a/libraries/io/eth/src/vhdl/eth_frm_discard.vhd
+++ b/libraries/io/eth/src/vhdl/eth_frm_discard.vhd
@@ -81,34 +81,41 @@ begin
p_frm_discard : process(i_frm_discard, hdr_status_complete, hdr_status, reg_config, reg_demux)
begin
- nxt_frm_discard <= i_frm_discard; -- default keep discard status (instead of '1'), to more clearly see when a change occurs frm_discard
+ -- default keep discard status (instead of '1'), to more clearly see when a change occurs frm_discard
+ nxt_frm_discard <= i_frm_discard;
if hdr_status_complete = '1' then
- nxt_frm_discard <= '1'; -- default discard
+ -- default discard
+ nxt_frm_discard <= '1';
-- ARP
if hdr_status.is_arp = '1' then
- nxt_frm_discard <= '0'; -- support ARP
+ -- support ARP
+ nxt_frm_discard <= '0';
end if;
-- IP
if hdr_status.is_ip = '1' then
-- IP/ICMP
if hdr_status.is_icmp = '1' then
- nxt_frm_discard <= '0'; -- support IP/ICMP = ping
+ -- support IP/ICMP = ping
+ nxt_frm_discard <= '0';
end if;
-- IP/UDP
if hdr_status.is_udp = '1' then
if g_support_dhcp = true and hdr_status.is_dhcp = '1' then
- nxt_frm_discard <= '0'; -- support IP/UDP/DHCP
+ -- support IP/UDP/DHCP
+ nxt_frm_discard <= '0';
end if;
if unsigned(hdr_status.udp_port) = unsigned(reg_config.udp_port) then
- nxt_frm_discard <= '0'; -- support IP/UDP FPGA node Monitoring and Control
+ -- support IP/UDP FPGA node Monitoring and Control
+ nxt_frm_discard <= '0';
end if;
if g_support_udp_onload = true then
for I in 1 to c_eth_nof_udp_ports loop
if reg_demux.udp_ports_en(I) = '1' and unsigned(reg_demux.udp_ports(I)) = unsigned(hdr_status.udp_port) then
- nxt_frm_discard <= '0'; -- support IP/UDP FPGA node streaming data onload via UDP port I
+ -- support IP/UDP FPGA node streaming data onload via UDP port I
+ nxt_frm_discard <= '0';
end if;
end loop;
end if;
diff --git a/libraries/io/eth/src/vhdl/eth_hdr.vhd b/libraries/io/eth/src/vhdl/eth_hdr.vhd
index 04060bdb252d7277542a5d5e98d6d17ac35f0dee..0b4fbd5646586553407c136b5bea70680661c906 100644
--- a/libraries/io/eth/src/vhdl/eth_hdr.vhd
+++ b/libraries/io/eth/src/vhdl/eth_hdr.vhd
@@ -43,8 +43,10 @@ entity eth_hdr is
);
port (
-- Clocks and reset
- rst : in std_logic; -- reset synchronous with clk
- clk : in std_logic; -- packet stream clock
+ -- reset synchronous with clk
+ rst : in std_logic;
+ -- packet stream clock
+ clk : in std_logic;
-- Streaming Sink
snk_in : in t_dp_sosi;
diff --git a/libraries/io/eth/src/vhdl/eth_hdr_ctrl.vhd b/libraries/io/eth/src/vhdl/eth_hdr_ctrl.vhd
index b3b8e2fdde4b328cc9ec3aa0b031363ffb44797b..c42710e68f064805aa24afac41581a8db99cb01c 100644
--- a/libraries/io/eth/src/vhdl/eth_hdr_ctrl.vhd
+++ b/libraries/io/eth/src/vhdl/eth_hdr_ctrl.vhd
@@ -49,7 +49,8 @@ entity eth_hdr_ctrl is
frm_discard_val : in std_logic := '1';
-- ST interface
- snk_in_word_cnt : in natural range 0 to c_network_total_header_32b_nof_words; -- snk_in hdr word count
+ -- snk_in hdr word count
+ snk_in_word_cnt : in natural range 0 to c_network_total_header_32b_nof_words;
snk_in : in t_dp_sosi;
snk_out : out t_dp_siso;
src_in : in t_dp_siso;
@@ -114,7 +115,8 @@ begin
snk_out => OPEN,
snk_in => snk_in,
-- ST source
- src_in => src_in, -- must not use snk_out.ready here to avoid wrong first payload data
+ -- must not use snk_out.ready here to avoid wrong first payload data
+ src_in => src_in,
next_src_out => next_src_out,
pend_src_out => OPEN,
src_out_reg => i_src_out
@@ -132,7 +134,8 @@ begin
p_state : process(state, src_word_cnt, i_src_out, snk_in, snk_in_word_cnt, frm_discard, frm_discard_val,
src_in, hdr_words_arr, hdr_status, snk_in_eop_hold, next_src_out)
begin
- snk_out <= c_dp_siso_rdy; -- default accept sink input
+ -- default accept sink input
+ snk_out <= c_dp_siso_rdy;
nxt_state <= state;
nxt_src_word_cnt <= src_word_cnt;
nxt_src_out <= i_src_out;
@@ -204,7 +207,8 @@ begin
end if;
end if;
end if;
- when others => -- s_src_data
+ -- s_src_data
+ when others =>
-- continue the input payload and output it
snk_out.ready <= src_in.ready;
nxt_src_out <= next_src_out;
diff --git a/libraries/io/eth/src/vhdl/eth_hdr_status.vhd b/libraries/io/eth/src/vhdl/eth_hdr_status.vhd
index 469b00c370ed78dc17bce8b3f8d6ad2d9ed342cc..ea224c21145247acfe2cc6d0d2484352b22d4e7d 100644
--- a/libraries/io/eth/src/vhdl/eth_hdr_status.vhd
+++ b/libraries/io/eth/src/vhdl/eth_hdr_status.vhd
@@ -122,7 +122,8 @@ begin
-- Use IP header checksum field read from the frame header
gen_read : if g_ip_header_checksum_calculate = false generate
ip_checksum <= hdr_fields.ip.header_checksum;
- ip_checksum_val <= calc_checksum_val; -- use u_calc_checksum only for valid control
+ -- use u_calc_checksum only for valid control
+ ip_checksum_val <= calc_checksum_val;
end generate;
-- If it is an IP packet then update the hdr_status IP checksum fields, else leave them 0
diff --git a/libraries/io/eth/src/vhdl/eth_hdr_store.vhd b/libraries/io/eth/src/vhdl/eth_hdr_store.vhd
index ab6f7b520206be015a53a58b9202c1794c2d3eeb..8702977f70bcf3a055f1cb987760c81138345b8c 100644
--- a/libraries/io/eth/src/vhdl/eth_hdr_store.vhd
+++ b/libraries/io/eth/src/vhdl/eth_hdr_store.vhd
@@ -78,12 +78,14 @@ architecture rtl of eth_hdr_store is
signal word_cnt : natural range 0 to c_network_total_header_32b_nof_words;
signal nxt_word_cnt : natural;
- signal i_hdr_words_arr : t_network_total_header_32b_arr := (others => (others => '0')); -- init to avoid numeric_std warning, no need to rst
+ -- init to avoid numeric_std warning, no need to rst
+ signal i_hdr_words_arr : t_network_total_header_32b_arr := (others => (others => '0'));
signal nxt_hdr_words_arr : t_network_total_header_32b_arr;
signal nxt_hdr_words_arr_val : std_logic_vector(hdr_fields_val'range);
signal i_hdr_fields_val : std_logic_vector(hdr_fields_val'range);
signal nxt_hdr_fields_val : std_logic_vector(hdr_fields_val'range);
- signal i_hdr_data : std_logic_vector(c_word_w - 1 downto 0) := (others => '0'); -- init to avoid numeric_std warning, no need to rst
+ -- init to avoid numeric_std warning, no need to rst
+ signal i_hdr_data : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
signal nxt_hdr_data : std_logic_vector(c_word_w - 1 downto 0);
signal nxt_hdr_data_val : std_logic;
begin
@@ -108,10 +110,12 @@ begin
-- internal
word_cnt <= nxt_word_cnt;
-- output
- i_hdr_words_arr <= nxt_hdr_words_arr; -- stored array of 11 words
+ -- stored array of 11 words
+ i_hdr_words_arr <= nxt_hdr_words_arr;
hdr_words_arr_val <= nxt_hdr_words_arr_val;
i_hdr_fields_val <= nxt_hdr_fields_val;
- i_hdr_data <= nxt_hdr_data; -- current word
+ -- current word
+ i_hdr_data <= nxt_hdr_data;
hdr_data_val <= nxt_hdr_data_val;
end if;
end process;
diff --git a/libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd b/libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd
index 02b167448fe219cdd3b5f72fb60974a197e074f0..c8eb0fd216a30ca1ce18c3fe92bf43d08bfb14b1 100644
--- a/libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd
+++ b/libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd
@@ -133,7 +133,8 @@ begin
when Eth_SrcMAC0 =>
if snk_in.valid = '1' then
- if snk_in.data(c_network_eth_type_slv'range) = TO_UVEC(c_network_eth_type_ip, c_network_eth_type_w) then -- if IPv4 frame
+ -- if IPv4 frame
+ if snk_in.data(c_network_eth_type_slv'range) = TO_UVEC(c_network_eth_type_ip, c_network_eth_type_w) then
state <= Eth_SrcMAC1;
else
state <= Idle;
@@ -142,16 +143,20 @@ begin
when Eth_SrcMAC1 =>
if snk_in.valid = '1' then
- if snk_in.data(27 downto 24) = TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w) then -- if ihl = 5 words = 20 bytes, nothing to do
+ -- if ihl = 5 words = 20 bytes, nothing to do
+ if snk_in.data(27 downto 24) = TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w) then
state <= Idle;
else
state <= IPv4_lengths;
- i_src_out.data(27 downto 24) <= TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w); -- make IHL = 5 words = 20 bytes
+ -- make IHL = 5 words = 20 bytes
+ i_src_out.data(27 downto 24) <= TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w);
i_src_out.data(c_network_ip_total_length_w - 1 downto 0) <= std_logic_vector(
unsigned(snk_in.data(c_network_ip_total_length_w - 1 downto 0)) -
((unsigned(snk_in.data(27 downto 24)) - to_unsigned(c_network_ip_header_length, c_network_ip_header_length_w)) & "00")
- ); -- correct Total Length = input Total Length - (input IHL - fixed IHL),
- ihl <= unsigned(snk_in.data(27 downto 24)); -- save input IHL
+ -- correct Total Length = input Total Length - (input IHL - fixed IHL),
+ );
+ -- save input IHL
+ ihl <= unsigned(snk_in.data(27 downto 24));
end if;
end if;
@@ -182,7 +187,8 @@ begin
when IPv4_DestIP =>
if snk_in.valid = '1' then
- i_src_out.valid <= '0'; -- do not allow option words to get through this module
+ -- do not allow option words to get through this module
+ i_src_out.valid <= '0';
state <= IPv4_Options;
ihl <= ihl - 1;
if ihl = 2 then
@@ -192,7 +198,8 @@ begin
when IPv4_Options =>
if snk_in.valid = '1' then
- i_src_out.valid <= '0'; -- do not allow option words to get through this module
+ -- do not allow option words to get through this module
+ i_src_out.valid <= '0';
ihl <= ihl - 1;
if ihl = 2 then
state <= IPv4_Payload;
diff --git a/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd b/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd
index c3c8b74b5e33c147986287a947798270017c919d..f5b4db1fc50401633828d925a2b37a40efc8bc4b 100644
--- a/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd
+++ b/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd
@@ -62,9 +62,11 @@ architecture rtl of eth_ip_header_checksum is
-- calculate which word(s) of the incoming snk_in stream should contain the checksum.
constant c_hdr_crc_word_hi : natural := sel_a_b((c_hdr_crc_bit_hi / g_data_w) > 0, c_hdr_crc_bit_hi / g_data_w,
- sel_a_b( c_hdr_crc_bit_hi > (c_hdr_len mod g_data_w), 1, 0)); --special case as the last hdr word can be < g_data_w.
+ --special case as the last hdr word can be < g_data_w.
+ sel_a_b( c_hdr_crc_bit_hi > (c_hdr_len mod g_data_w), 1, 0));
constant c_hdr_crc_word_lo : natural := sel_a_b((c_hdr_crc_bit_lo / g_data_w) > 0, c_hdr_crc_bit_lo / g_data_w,
- sel_a_b( c_hdr_crc_bit_lo > (c_hdr_len mod g_data_w), 1, 0)); --special case as the last hdr word can be < g_data_w.
+ --special case as the last hdr word can be < g_data_w.
+ sel_a_b( c_hdr_crc_bit_lo > (c_hdr_len mod g_data_w), 1, 0));
-- calculate in which bit range of the selected word(s) the checksum should go.
constant c_crc_hi_bit_in_word : natural := g_data_w - ((c_hdr_len - c_hdr_crc_bit_hi) mod g_data_w);
@@ -89,7 +91,8 @@ begin
---------------------------------------------------
-- process to insert checksum in outgoing stream --
---------------------------------------------------
- gen_insert_crc_one : if c_crc_in_one_word generate -- checksum is in 1 word.
+ -- checksum is in 1 word.
+ gen_insert_crc_one : if c_crc_in_one_word generate
p_insert_crc_one : process(dp_pipeline_src_out, checksum, count, reg_done)
variable v_count : natural := 0;
begin
@@ -156,7 +159,8 @@ begin
-------------------------------------------------------------------------------
u_dp_pipeline : entity dp_lib.dp_pipeline
generic map (
- g_pipeline => 1 -- fixed to 1 as common_counter has fixed latency of 1 (cannot be higher)
+ -- fixed to 1 as common_counter has fixed latency of 1 (cannot be higher)
+ g_pipeline => 1
)
port map (
rst => rst,
diff --git a/libraries/io/eth/src/vhdl/eth_mm_reg_frame.vhd b/libraries/io/eth/src/vhdl/eth_mm_reg_frame.vhd
index f7877190291bc43d4f57d53c9160730315108a13..b46566721494ca5024d644848bb711d414efa7a1 100644
--- a/libraries/io/eth/src/vhdl/eth_mm_reg_frame.vhd
+++ b/libraries/io/eth/src/vhdl/eth_mm_reg_frame.vhd
@@ -30,14 +30,20 @@ use work.eth_pkg.all;
entity eth_mm_reg_frame is
port (
-- Clocks and reset
- rst : in std_logic; -- reset synchronous with clk
- clk : in std_logic; -- packet stream clock
+ -- reset synchronous with clk
+ rst : in std_logic;
+ -- packet stream clock
+ clk : in std_logic;
-- Inputs need for the frame register
- hdr_fields : in t_network_total_header; -- Header info
- hdr_status : in t_eth_hdr_status; -- Header info
- erc_word : in std_logic_vector(c_eth_data_w - 1 downto 0); -- Extracted CRC word (enumerate: 0=OK, >0 AND odd = Error)
- reg_config : in t_eth_mm_reg_config; -- Config setting
+ -- Header info
+ hdr_fields : in t_network_total_header;
+ -- Header info
+ hdr_status : in t_eth_hdr_status;
+ -- Extracted CRC word (enumerate: 0=OK, >0 AND odd = Error)
+ erc_word : in std_logic_vector(c_eth_data_w - 1 downto 0);
+ -- Config setting
+ reg_config : in t_eth_mm_reg_config;
-- Frame register
reg_frame : out t_eth_mm_reg_frame
diff --git a/libraries/io/eth/src/vhdl/eth_mm_registers.vhd b/libraries/io/eth/src/vhdl/eth_mm_registers.vhd
index f2011b02744ca3320d56d07def554b374d3a27f8..12d18c2138c60ed22827a7e34ec508b082bbdcd1 100644
--- a/libraries/io/eth/src/vhdl/eth_mm_registers.vhd
+++ b/libraries/io/eth/src/vhdl/eth_mm_registers.vhd
@@ -30,15 +30,21 @@ use work.eth_pkg.all;
entity eth_mm_registers is
generic (
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_init_ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := X"00000000" -- 0.0.0.0
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
+ -- 0.0.0.0
+ g_init_ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := X"00000000"
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave
sla_in : in t_mem_mosi;
@@ -50,11 +56,13 @@ entity eth_mm_registers is
st_reg_demux : out t_eth_mm_reg_demux;
st_reg_config : out t_eth_mm_reg_config;
st_reg_control : out t_eth_mm_reg_control;
- st_reg_continue_wr : out std_logic; -- used to know that control reg has been written and ETH module can continue
+ -- used to know that control reg has been written and ETH module can continue
+ st_reg_continue_wr : out std_logic;
-- . read only
st_reg_frame : in t_eth_mm_reg_frame;
st_reg_status : in t_eth_mm_reg_status;
- st_reg_status_wr : out std_logic -- used to know that status reg has been read and can be cleared to remove the sla_interrupt
+ -- used to know that status reg has been read and can be cleared to remove the sla_interrupt
+ st_reg_status_wr : out std_logic
);
end eth_mm_registers;
@@ -82,7 +90,8 @@ architecture str of eth_mm_registers is
constant c_in_latency : natural := 1;
-- Input register
- signal sla_in_reg : t_mem_mosi; -- so c_in_latency = 1
+ -- so c_in_latency = 1
+ signal sla_in_reg : t_mem_mosi;
-- Register store
signal mm_vec_wr : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0);
@@ -123,13 +132,18 @@ begin
mm_vec_config <= mm_vec_wr((c_eth_reg_config_nof_words + c_eth_reg_config_wi) * c_mm_reg.dat_w - 1 downto c_eth_reg_config_wi * c_mm_reg.dat_w);
mm_vec_control <= mm_vec_wr((c_eth_reg_control_nof_words + c_eth_reg_control_wi) * c_mm_reg.dat_w - 1 downto c_eth_reg_control_wi * c_mm_reg.dat_w);
- st_reg_demux <= func_eth_mm_reg_demux(st_vec_demux); -- Demux UDP registers
- st_reg_config <= func_eth_mm_reg_config(st_vec_config); -- Packet config registers
- st_reg_control <= func_eth_mm_reg_control(st_vec_control); -- Rx control registers
+ -- Demux UDP registers
+ st_reg_demux <= func_eth_mm_reg_demux(st_vec_demux);
+ -- Packet config registers
+ st_reg_config <= func_eth_mm_reg_config(st_vec_config);
+ -- Rx control registers
+ st_reg_control <= func_eth_mm_reg_control(st_vec_control);
-- . read only
- st_vec_frame <= func_eth_mm_reg_frame(st_reg_frame); -- Rx frame registers
- st_vec_status <= func_eth_mm_reg_status(st_reg_status); -- ETH status registers
+ -- Rx frame registers
+ st_vec_frame <= func_eth_mm_reg_frame(st_reg_frame);
+ -- ETH status registers
+ st_vec_status <= func_eth_mm_reg_status(st_reg_status);
mm_vec_rd <= mm_vec_status & mm_vec_frame & mm_vec_control & mm_vec_config & mm_vec_demux;
@@ -242,7 +256,8 @@ begin
in_rst => mm_rst,
in_clk => mm_clk,
in_dat => mm_vec_demux,
- in_new => sla_in_reg.wr, -- using the slave wr is OK to trigger a cross clock domain
+ -- using the slave wr is OK to trigger a cross clock domain
+ in_new => sla_in_reg.wr,
in_done => OPEN,
out_rst => st_rst,
out_clk => st_clk,
@@ -255,7 +270,8 @@ begin
in_rst => mm_rst,
in_clk => mm_clk,
in_dat => mm_vec_config,
- in_new => sla_in_reg.wr, -- using the slave wr is OK to trigger a cross clock domain
+ -- using the slave wr is OK to trigger a cross clock domain
+ in_new => sla_in_reg.wr,
in_done => OPEN,
out_rst => st_rst,
out_clk => st_clk,
@@ -268,7 +284,8 @@ begin
in_rst => mm_rst,
in_clk => mm_clk,
in_dat => mm_vec_control,
- in_new => sla_in_reg.wr, -- using the slave wr is OK to trigger a cross clock domain
+ -- using the slave wr is OK to trigger a cross clock domain
+ in_new => sla_in_reg.wr,
in_done => OPEN,
out_rst => st_rst,
out_clk => st_clk,
diff --git a/libraries/io/eth/src/vhdl/eth_pkg.vhd b/libraries/io/eth/src/vhdl/eth_pkg.vhd
index d7f2fe2b9b4777d8538e73b6f443a7b0605c8b50..070551b666d7ea99f101e75a122fe241d572ae3e 100644
--- a/libraries/io/eth/src/vhdl/eth_pkg.vhd
+++ b/libraries/io/eth/src/vhdl/eth_pkg.vhd
@@ -29,29 +29,39 @@ use dp_lib.dp_stream_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
- constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
- constant c_eth_empty_w : natural := c_tech_tse_empty_w; -- = ceil_log2(c_word_sz) = 2;
- constant c_eth_error_w : natural := c_tech_tse_error_w; -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
-
- constant c_eth_rx_ready_latency : natural := c_tech_tse_rx_ready_latency; -- = 2 = default when FIFO is used
- constant c_eth_tx_ready_latency : natural := c_tech_tse_tx_ready_latency; -- = 0, c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
- constant c_eth_ready_latency : natural := 1; -- = 1, fixed ETH module internal RL
+ -- = c_word_w
+ constant c_eth_data_w : natural := c_tech_tse_data_w;
+ -- = ceil_log2(c_word_sz) = 2;
+ constant c_eth_empty_w : natural := c_tech_tse_empty_w;
+ -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
+ constant c_eth_error_w : natural := c_tech_tse_error_w;
+
+ -- = 2 = default when FIFO is used
+ constant c_eth_rx_ready_latency : natural := c_tech_tse_rx_ready_latency;
+ -- = 0, c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
+ constant c_eth_tx_ready_latency : natural := c_tech_tse_tx_ready_latency;
+ -- = 1, fixed ETH module internal RL
+ constant c_eth_ready_latency : natural := 1;
-- Maximum feasible frame size
- constant c_eth_max_frame_sz : natural := 1024 * 9; -- 9 kByte fits 9020 = word align (2) + eth header (14) + maximum jumbo payload (9000) + CRC (4)
+ -- 9 kByte fits 9020 = word align (2) + eth header (14) + maximum jumbo payload (9000) + CRC (4)
+ constant c_eth_max_frame_sz : natural := 1024 * 9;
constant c_eth_max_frame_nof_words : natural := c_eth_max_frame_sz / c_word_sz;
- constant c_eth_max_frame_nof_words_w : natural := ceil_log2(c_eth_max_frame_nof_words); -- = 12 bit
+ -- = 12 bit
+ constant c_eth_max_frame_nof_words_w : natural := ceil_log2(c_eth_max_frame_nof_words);
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
-- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
- constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
+ -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
+ constant c_eth_frame_sz : natural := 1024 * 2;
-- when the module is used in an Nios II SOPC system
-- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
- constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
+ -- >= 9 bit, <= 12 bit
+ constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words);
type t_eth_data_arr is array (integer range <>) of std_logic_vector(c_eth_data_w - 1 downto 0);
@@ -79,12 +89,15 @@ package eth_pkg is
-- Definitions for eth demux udp
------------------------------------------------------------------------------
- constant c_eth_nof_udp_ports : natural := 4; -- support 2, 4, 8, ... UDP off-load ports
- constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1); -- + 1 for all other packets that go to the default port
+ -- support 2, 4, 8, ... UDP off-load ports
+ constant c_eth_nof_udp_ports : natural := 4;
+ -- + 1 for all other packets that go to the default port
+ constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1);
constant c_eth_nof_channels : natural := 2**c_eth_channel_w;
-- Default Rx UDP port for UDP onload
- constant c_eth_rx_udp_port : std_logic_vector(15 downto 0) := TO_UVEC(6001, 16); -- 0x1771 = 6001
+ -- 0x1771 = 6001
+ constant c_eth_rx_udp_port : std_logic_vector(15 downto 0) := TO_UVEC(6001, 16);
------------------------------------------------------------------------------
-- MM register map
@@ -106,30 +119,46 @@ package eth_pkg is
-- . write/read back registers
type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
type t_eth_mm_reg_demux is record
- udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
- udp_ports : t_eth_demux_ports_arr; -- [15:0]
+ -- [16]
+ udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports);
+ -- [15:0]
+ udp_ports : t_eth_demux_ports_arr;
end record;
type t_eth_mm_reg_config is record
- udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- [15:0]
- ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- [31:0]
- mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- [15:0], [31:0]
+ -- [15:0]
+ udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ -- [31:0]
+ ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0);
+ -- [15:0], [31:0]
+ mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
end record;
type t_eth_mm_reg_control is record
- tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_request : std_logic; -- 1 bit
- tx_en : std_logic; -- 1 bit
- rx_en : std_logic; -- 1 bit
+ -- 12 bit
+ tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0);
+ -- 2 bit
+ tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0);
+ -- 1 bit
+ tx_request : std_logic;
+ -- 1 bit
+ tx_en : std_logic;
+ -- 1 bit
+ rx_en : std_logic;
end record;
- type t_eth_mm_reg_control_bi is record -- bit indices
- tx_nof_words : natural; -- [26:18]
- tx_empty : natural; -- [17:16]
- tx_request : natural; -- [2]
- tx_en : natural; -- [1]
- rx_en : natural; -- [0]
+ -- bit indices
+ type t_eth_mm_reg_control_bi is record
+ -- [26:18]
+ tx_nof_words : natural;
+ -- [17:16]
+ tx_empty : natural;
+ -- [2]
+ tx_request : natural;
+ -- [1]
+ tx_en : natural;
+ -- [0]
+ rx_en : natural;
end record;
constant c_eth_mm_reg_control_bi : t_eth_mm_reg_control_bi := (18, 16, 2, 1, 0);
@@ -149,36 +178,58 @@ package eth_pkg is
eth_mac_error : std_logic_vector(c_eth_error_w - 1 downto 0);
end record;
- type t_eth_mm_reg_frame_bi is record -- bit indices
- is_dhcp : natural; -- [15]
- is_udp_ctrl_port : natural; -- [14]
- is_udp : natural; -- [13]
- is_icmp : natural; -- [12]
- ip_address_match : natural; -- [11]
- ip_checksum_is_ok : natural; -- [10]
- is_ip : natural; -- [9]
- is_arp : natural; -- [8]
- mac_address_match : natural; -- [7]
- eth_mac_error : natural; -- [6] not used, [5:0] = TSE MAC error
+ -- bit indices
+ type t_eth_mm_reg_frame_bi is record
+ -- [15]
+ is_dhcp : natural;
+ -- [14]
+ is_udp_ctrl_port : natural;
+ -- [13]
+ is_udp : natural;
+ -- [12]
+ is_icmp : natural;
+ -- [11]
+ ip_address_match : natural;
+ -- [10]
+ ip_checksum_is_ok : natural;
+ -- [9]
+ is_ip : natural;
+ -- [8]
+ is_arp : natural;
+ -- [7]
+ mac_address_match : natural;
+ -- [6] not used, [5:0] = TSE MAC error
+ eth_mac_error : natural;
end record;
constant c_eth_mm_reg_frame_bi : t_eth_mm_reg_frame_bi := (15, 14, 13, 12, 11, 10, 9, 8, 7, 0);
constant c_eth_mm_reg_frame_rst : t_eth_mm_reg_frame := ('0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'));
type t_eth_mm_reg_status is record
- rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_avail : std_logic; -- 1 bit
- tx_done : std_logic; -- 1 bit
- rx_avail : std_logic; -- 1 bit
+ -- 12 bit
+ rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0);
+ -- 2 bit
+ rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0);
+ -- 1 bit
+ tx_avail : std_logic;
+ -- 1 bit
+ tx_done : std_logic;
+ -- 1 bit
+ rx_avail : std_logic;
end record;
- type t_eth_mm_reg_status_bi is record -- bit indices
- rx_nof_words : natural; -- [26:18]
- rx_empty : natural; -- [17:16]
- tx_avail : natural; -- [2]
- tx_done : natural; -- [1]
- rx_avail : natural; -- [0]
+ -- bit indices
+ type t_eth_mm_reg_status_bi is record
+ -- [26:18]
+ rx_nof_words : natural;
+ -- [17:16]
+ rx_empty : natural;
+ -- [2]
+ tx_avail : natural;
+ -- [1]
+ tx_done : natural;
+ -- [0]
+ rx_avail : natural;
end record;
constant c_eth_mm_reg_status_bi : t_eth_mm_reg_status_bi := (18, 16, 2, 1, 0);
@@ -204,9 +255,12 @@ package eth_pkg is
c_eth_reg_config_nof_words +
c_eth_reg_control_nof_words +
c_eth_reg_frame_nof_words +
- c_eth_reg_status_nof_words; -- 4 + 4 + 1 + 1 + 1 = 11
- constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- 11 + 1 for c_eth_continue_wi = 12
- constant c_eth_reg_addr_span : natural := 2**c_eth_reg_addr_w; -- = 16
+ -- 4 + 4 + 1 + 1 + 1 = 11
+ c_eth_reg_status_nof_words;
+ -- 11 + 1 for c_eth_continue_wi = 12
+ constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1);
+ -- = 16
+ constant c_eth_reg_addr_span : natural := 2**c_eth_reg_addr_w;
------------------------------------------------------------------------------
-- Definitions for ETH Rx packet buffer and Tx packet buffer
@@ -227,8 +281,10 @@ package body eth_pkg is
begin
-- Demux UDP MM registers
for I in 1 to c_eth_nof_udp_ports loop
- v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w); -- [16] = UDP port enable
- v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w); -- [15:0] = UDP port number
+ -- [16] = UDP port enable
+ v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w);
+ -- [15:0] = UDP port number
+ v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w);
end loop;
return v_reg;
@@ -237,10 +293,13 @@ package body eth_pkg is
function func_eth_mm_reg_demux(mm_reg : t_eth_mm_reg_demux) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_demux_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
+ -- rsvd
+ v_reg := (others => '0');
for I in 1 to c_eth_nof_udp_ports loop
- v_reg(c_network_udp_port_w + (I - 1) * c_word_w) := mm_reg.udp_ports_en(I); -- [16] = UDP port enable
- v_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w) := mm_reg.udp_ports(I); -- [15:0] = UDP port number
+ -- [16] = UDP port enable
+ v_reg(c_network_udp_port_w + (I - 1) * c_word_w) := mm_reg.udp_ports_en(I);
+ -- [15:0] = UDP port number
+ v_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w) := mm_reg.udp_ports(I);
end loop;
return v_reg;
end func_eth_mm_reg_demux;
@@ -249,21 +308,30 @@ package body eth_pkg is
function func_eth_mm_reg_config(mm_reg : std_logic_vector) return t_eth_mm_reg_config is
variable v_reg : t_eth_mm_reg_config;
begin
- v_reg.udp_port := mm_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w); -- [15:0] = control UDP port number
- v_reg.ip_address := mm_reg( 3 * c_word_w - 1 downto 2 * c_word_w); -- [31:0] = this node IP address
- v_reg.mac_address(47 downto 32) := mm_reg( c_halfword_w + c_word_w - 1 downto c_word_w); -- [47:32] = this node MAC address
- v_reg.mac_address(31 downto 0) := mm_reg( c_word_w - 1 downto 0); -- [31:0] = this node MAC address
+ -- [15:0] = control UDP port number
+ v_reg.udp_port := mm_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w);
+ -- [31:0] = this node IP address
+ v_reg.ip_address := mm_reg( 3 * c_word_w - 1 downto 2 * c_word_w);
+ -- [47:32] = this node MAC address
+ v_reg.mac_address(47 downto 32) := mm_reg( c_halfword_w + c_word_w - 1 downto c_word_w);
+ -- [31:0] = this node MAC address
+ v_reg.mac_address(31 downto 0) := mm_reg( c_word_w - 1 downto 0);
return v_reg;
end func_eth_mm_reg_config;
function func_eth_mm_reg_config(mm_reg : t_eth_mm_reg_config) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_config_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w) := mm_reg.udp_port; -- [15:0] = control UDP port number
- v_reg( 3 * c_word_w - 1 downto 2 * c_word_w) := mm_reg.ip_address; -- [31:0] = this node IP address
- v_reg( c_halfword_w + c_word_w - 1 downto c_word_w) := mm_reg.mac_address(47 downto 32); -- [47:32] = this node MAC address
- v_reg( c_word_w - 1 downto 0) := mm_reg.mac_address(31 downto 0); -- [31:0] = this node MAC address
+ -- rsvd
+ v_reg := (others => '0');
+ -- [15:0] = control UDP port number
+ v_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w) := mm_reg.udp_port;
+ -- [31:0] = this node IP address
+ v_reg( 3 * c_word_w - 1 downto 2 * c_word_w) := mm_reg.ip_address;
+ -- [47:32] = this node MAC address
+ v_reg( c_halfword_w + c_word_w - 1 downto c_word_w) := mm_reg.mac_address(47 downto 32);
+ -- [31:0] = this node MAC address
+ v_reg( c_word_w - 1 downto 0) := mm_reg.mac_address(31 downto 0);
return v_reg;
end func_eth_mm_reg_config;
@@ -271,23 +339,34 @@ package body eth_pkg is
function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control is
variable v_reg : t_eth_mm_reg_control;
begin
- v_reg.tx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
- v_reg.tx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16); -- [17:16]
- v_reg.tx_request := mm_reg( 2); -- [2]
- v_reg.tx_en := mm_reg( 1); -- [1]
- v_reg.rx_en := mm_reg( 0); -- [0]
+ -- [29:18]
+ v_reg.tx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16);
+ -- [17:16]
+ v_reg.tx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16);
+ -- [2]
+ v_reg.tx_request := mm_reg( 2);
+ -- [1]
+ v_reg.tx_en := mm_reg( 1);
+ -- [0]
+ v_reg.rx_en := mm_reg( 0);
return v_reg;
end func_eth_mm_reg_control;
function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_control_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.tx_nof_words; -- [29:18]
- v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.tx_empty; -- [17:16]
- v_reg( 2) := mm_reg.tx_request; -- [2]
- v_reg( 1) := mm_reg.tx_en; -- [1]
- v_reg( 0) := mm_reg.rx_en; -- [0]
+ -- rsvd
+ v_reg := (others => '0');
+ -- [29:18]
+ v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.tx_nof_words;
+ -- [17:16]
+ v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.tx_empty;
+ -- [2]
+ v_reg( 2) := mm_reg.tx_request;
+ -- [1]
+ v_reg( 1) := mm_reg.tx_en;
+ -- [0]
+ v_reg( 0) := mm_reg.rx_en;
return v_reg;
end func_eth_mm_reg_control;
@@ -295,33 +374,54 @@ package body eth_pkg is
function func_eth_mm_reg_frame(mm_reg : std_logic_vector) return t_eth_mm_reg_frame is
variable v_reg : t_eth_mm_reg_frame;
begin
- v_reg.is_dhcp := mm_reg( c_byte_w + 7); -- [15]
- v_reg.is_udp_ctrl_port := mm_reg( c_byte_w + 6); -- [14]
- v_reg.is_udp := mm_reg( c_byte_w + 5); -- [13]
- v_reg.is_icmp := mm_reg( c_byte_w + 4); -- [12]
- v_reg.ip_address_match := mm_reg( c_byte_w + 3); -- [11]
- v_reg.ip_checksum_is_ok := mm_reg( c_byte_w + 2); -- [10]
- v_reg.is_ip := mm_reg( c_byte_w + 1); -- [9]
- v_reg.is_arp := mm_reg( c_byte_w + 0); -- [8]
- v_reg.mac_address_match := mm_reg( c_byte_w - 1); -- [7]
- v_reg.eth_mac_error := mm_reg(c_eth_error_w - 1 downto 0); -- [7] not used, [5:0] = TSE MAC error
+ -- [15]
+ v_reg.is_dhcp := mm_reg( c_byte_w + 7);
+ -- [14]
+ v_reg.is_udp_ctrl_port := mm_reg( c_byte_w + 6);
+ -- [13]
+ v_reg.is_udp := mm_reg( c_byte_w + 5);
+ -- [12]
+ v_reg.is_icmp := mm_reg( c_byte_w + 4);
+ -- [11]
+ v_reg.ip_address_match := mm_reg( c_byte_w + 3);
+ -- [10]
+ v_reg.ip_checksum_is_ok := mm_reg( c_byte_w + 2);
+ -- [9]
+ v_reg.is_ip := mm_reg( c_byte_w + 1);
+ -- [8]
+ v_reg.is_arp := mm_reg( c_byte_w + 0);
+ -- [7]
+ v_reg.mac_address_match := mm_reg( c_byte_w - 1);
+ -- [7] not used, [5:0] = TSE MAC error
+ v_reg.eth_mac_error := mm_reg(c_eth_error_w - 1 downto 0);
return v_reg;
end func_eth_mm_reg_frame;
function func_eth_mm_reg_frame(mm_reg : t_eth_mm_reg_frame) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_frame_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg( c_byte_w + 7) := mm_reg.is_dhcp; -- [15]
- v_reg( c_byte_w + 6) := mm_reg.is_udp_ctrl_port; -- [14]
- v_reg( c_byte_w + 5) := mm_reg.is_udp; -- [13]
- v_reg( c_byte_w + 4) := mm_reg.is_icmp; -- [12]
- v_reg( c_byte_w + 3) := mm_reg.ip_address_match; -- [11]
- v_reg( c_byte_w + 2) := mm_reg.ip_checksum_is_ok; -- [10]
- v_reg( c_byte_w + 1) := mm_reg.is_ip; -- [9]
- v_reg( c_byte_w + 0) := mm_reg.is_arp; -- [8]
- v_reg( c_byte_w - 1) := mm_reg.mac_address_match; -- [7]
- v_reg(c_eth_error_w - 1 downto 0) := mm_reg.eth_mac_error; -- [6] not used, [5:0] = TSE MAC error
+ -- rsvd
+ v_reg := (others => '0');
+ -- [15]
+ v_reg( c_byte_w + 7) := mm_reg.is_dhcp;
+ -- [14]
+ v_reg( c_byte_w + 6) := mm_reg.is_udp_ctrl_port;
+ -- [13]
+ v_reg( c_byte_w + 5) := mm_reg.is_udp;
+ -- [12]
+ v_reg( c_byte_w + 4) := mm_reg.is_icmp;
+ -- [11]
+ v_reg( c_byte_w + 3) := mm_reg.ip_address_match;
+ -- [10]
+ v_reg( c_byte_w + 2) := mm_reg.ip_checksum_is_ok;
+ -- [9]
+ v_reg( c_byte_w + 1) := mm_reg.is_ip;
+ -- [8]
+ v_reg( c_byte_w + 0) := mm_reg.is_arp;
+ -- [7]
+ v_reg( c_byte_w - 1) := mm_reg.mac_address_match;
+ -- [6] not used, [5:0] = TSE MAC error
+ v_reg(c_eth_error_w - 1 downto 0) := mm_reg.eth_mac_error;
return v_reg;
end func_eth_mm_reg_frame;
@@ -329,23 +429,34 @@ package body eth_pkg is
function func_eth_mm_reg_status(mm_reg : std_logic_vector) return t_eth_mm_reg_status is
variable v_reg : t_eth_mm_reg_status;
begin
- v_reg.rx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
- v_reg.rx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16); -- [17:16]
- v_reg.tx_avail := mm_reg( 2); -- [2]
- v_reg.tx_done := mm_reg( 1); -- [1]
- v_reg.rx_avail := mm_reg( 0); -- [0]
+ -- [29:18]
+ v_reg.rx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16);
+ -- [17:16]
+ v_reg.rx_empty := mm_reg( c_eth_empty_w + 16 - 1 downto 16);
+ -- [2]
+ v_reg.tx_avail := mm_reg( 2);
+ -- [1]
+ v_reg.tx_done := mm_reg( 1);
+ -- [0]
+ v_reg.rx_avail := mm_reg( 0);
return v_reg;
end func_eth_mm_reg_status;
function func_eth_mm_reg_status(mm_reg : t_eth_mm_reg_status) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_status_nof_words * c_word_w - 1 downto 0);
begin
- v_reg := (others => '0'); -- rsvd
- v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.rx_nof_words; -- [29:18]
- v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.rx_empty; -- [17:16]
- v_reg( 2) := mm_reg.tx_avail; -- [2]
- v_reg( 1) := mm_reg.tx_done; -- [1]
- v_reg( 0) := mm_reg.rx_avail; -- [0]
+ -- rsvd
+ v_reg := (others => '0');
+ -- [29:18]
+ v_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16) := mm_reg.rx_nof_words;
+ -- [17:16]
+ v_reg( c_eth_empty_w + 16 - 1 downto 16) := mm_reg.rx_empty;
+ -- [2]
+ v_reg( 2) := mm_reg.tx_avail;
+ -- [1]
+ v_reg( 1) := mm_reg.tx_done;
+ -- [0]
+ v_reg( 0) := mm_reg.rx_avail;
return v_reg;
end func_eth_mm_reg_status;
diff --git a/libraries/io/eth/src/vhdl/eth_statistics.vhd b/libraries/io/eth/src/vhdl/eth_statistics.vhd
index 1282286c2294bc7addafcf80414ee802f8fe5ca3..141d2e2ee00aafb0e5f4d5dbc20189dafd52fa6d 100644
--- a/libraries/io/eth/src/vhdl/eth_statistics.vhd
+++ b/libraries/io/eth/src/vhdl/eth_statistics.vhd
@@ -50,15 +50,21 @@ use technology_lib.technology_select_pkg.all;
entity eth_statistics is
generic (
- g_runtime_nof_packets : natural; -- Run the test bench for nof_packets before asserting tb_end
- g_runtime_timeout : time; -- Report Failure if g_runtime_nof_packets is not reached before this time
- g_check_nof_valid : boolean := false; -- True enables valid count checking at tb_end. Reports Failure in case of mismatch.
- g_check_nof_valid_ref : natural := 0 -- Reference (= expected) valid count
+ -- Run the test bench for nof_packets before asserting tb_end
+ g_runtime_nof_packets : natural;
+ -- Report Failure if g_runtime_nof_packets is not reached before this time
+ g_runtime_timeout : time;
+ -- True enables valid count checking at tb_end. Reports Failure in case of mismatch.
+ g_check_nof_valid : boolean := false;
+ -- Reference (= expected) valid count
+ g_check_nof_valid_ref : natural := 0
);
port (
eth_serial_in : in std_logic;
- eth_src_out : out t_dp_sosi; -- Output received sosi
- tb_end : out std_logic -- To be used to stop test-bench generated clocks
+ -- Output received sosi
+ eth_src_out : out t_dp_sosi;
+ -- To be used to stop test-bench generated clocks
+ tb_end : out std_logic
);
end eth_statistics;
diff --git a/libraries/io/eth/src/vhdl/eth_stream.vhd b/libraries/io/eth/src/vhdl/eth_stream.vhd
index 4f66bb93cf47bbfd77d74d69500110e20b01490d..d5cb2877d73f6db90e7295c2ae87d7f7d48b769c 100644
--- a/libraries/io/eth/src/vhdl/eth_stream.vhd
+++ b/libraries/io/eth/src/vhdl/eth_stream.vhd
@@ -51,21 +51,29 @@ use technology_lib.technology_select_pkg.all;
entity eth_stream is
generic (
g_technology : natural := c_tech_select_default;
- g_ETH_PHY : string := "LVDS"; -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+ -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+ g_ETH_PHY : string := "LVDS";
g_rx_udp_port : natural := TO_UINT(c_eth_rx_udp_port);
g_jumbo_en : boolean := true;
g_sim : boolean := false;
- g_sim_level : natural := 0 -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
+ -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
+ g_sim_level : natural := 0
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- eth_clk : in std_logic; -- ethernet phy reference clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- packet stream clock
-
- cal_rec_clk : in std_logic := '0'; -- Calibration & reconfig clock when using XCVR
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- ethernet phy reference clock
+ eth_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- packet stream clock
+ st_clk : in std_logic;
+
+ -- Calibration & reconfig clock when using XCVR
+ cal_rec_clk : in std_logic := '0';
-- TSE setup
src_mac : in std_logic_vector(c_48 - 1 downto 0);
@@ -80,7 +88,8 @@ entity eth_stream is
udp_rx_src_out : out t_dp_sosi;
-- Memory Mapped Slaves
- tse_ctlr_copi : in t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ tse_ctlr_copi : in t_mem_mosi;
tse_ctlr_cipo : out t_mem_miso;
-- PHY interface
@@ -139,10 +148,14 @@ begin
port map (
-- Clocks and reset
mm_rst => mm_rst,
- mm_clk => mm_clk, -- MM
- eth_clk => eth_clk, -- 125 MHz
- tx_snk_clk => st_clk, -- DP
- rx_src_clk => st_clk, -- DP
+ -- MM
+ mm_clk => mm_clk,
+ -- 125 MHz
+ eth_clk => eth_clk,
+ -- DP
+ tx_snk_clk => st_clk,
+ -- DP
+ rx_src_clk => st_clk,
-- TSE setup
src_mac => src_mac,
diff --git a/libraries/io/eth/src/vhdl/eth_stream_udp.vhd b/libraries/io/eth/src/vhdl/eth_stream_udp.vhd
index d914ff1dc8a3dd1966fc5a4bd59919b646d8a08f..cfb90db4a014648b7fb702e33d0201eb2272f57a 100644
--- a/libraries/io/eth/src/vhdl/eth_stream_udp.vhd
+++ b/libraries/io/eth/src/vhdl/eth_stream_udp.vhd
@@ -106,7 +106,8 @@ begin
-- Streaming Source
src_in => tse_tx_siso,
- src_out => tse_tx_sosi -- with err field value 0 for OK
+ -- with err field value 0 for OK
+ src_out => tse_tx_sosi
);
------------------------------------------------------------------------------
@@ -116,8 +117,10 @@ begin
-- Adapt the TSE RX source ready latency from 2 to 1
u_adapt : entity dp_lib.dp_latency_adapter
generic map (
- g_in_latency => c_eth_rx_ready_latency, -- = 2
- g_out_latency => c_eth_ready_latency -- = 1
+ -- = 2
+ g_in_latency => c_eth_rx_ready_latency,
+ -- = 1
+ g_out_latency => c_eth_ready_latency
)
port map (
rst => st_rst,
@@ -163,17 +166,20 @@ begin
p_rx_discard : process(st_rst, st_clk)
begin
if st_rst = '1' then
- rx_eth_discard <= '1'; -- default discard
+ -- default discard
+ rx_eth_discard <= '1';
rx_eth_discard_val <= '0';
elsif rising_edge(st_clk) then
-- Default keep rx_eth_discard status (instead of '1'), to more clearly
-- see when a change occurs
if rx_hdr_status_complete = '1' then
- rx_eth_discard <= '1'; -- default discard
+ -- default discard
+ rx_eth_discard <= '1';
if rx_hdr_status.is_ip = '1' and
rx_hdr_status.is_udp = '1' and
TO_UINT(rx_hdr_status.udp_port) = g_rx_udp_port then
- rx_eth_discard <= '0'; -- pass on IP/UDP stream for g_rx_udp_port
+ -- pass on IP/UDP stream for g_rx_udp_port
+ rx_eth_discard <= '0';
end if;
end if;
diff --git a/libraries/io/eth/src/vhdl/eth_tester.vhd b/libraries/io/eth/src/vhdl/eth_tester.vhd
index 932dcfa20c169fc16909bf3ad5eb589ddc3418e4..be850b81f66e183833b2ab633ed1e0b81e137dc1 100644
--- a/libraries/io/eth/src/vhdl/eth_tester.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester.vhd
@@ -41,7 +41,8 @@ entity eth_tester is
g_nof_streams : natural := 1;
g_bg_sync_timeout : natural := c_eth_tester_sync_timeout;
g_nof_octet_generate : natural := 1;
- g_nof_octet_output : natural := 4; -- must be multiple of g_nof_octet_generate.
+ -- must be multiple of g_nof_octet_generate.
+ g_nof_octet_output : natural := 4;
g_use_eth_header : boolean := true;
g_use_ip_udp_header : boolean := true;
g_use_dp_header : boolean := true;
@@ -49,7 +50,8 @@ entity eth_tester is
g_hdr_field_arr : t_common_field_arr := c_eth_tester_hdr_field_arr;
g_hdr_field_sel : std_logic_vector := c_eth_tester_hdr_field_sel;
g_hdr_app_len : natural := c_eth_tester_app_hdr_len;
- g_remove_crc : boolean := true -- use TRUE when using sim_tse and tech_tse link interface,
+ -- use TRUE when using sim_tse and tech_tse link interface,
+ g_remove_crc : boolean := true
-- use FALSE when streaming link interface
);
port (
@@ -94,11 +96,13 @@ entity eth_tester is
end eth_tester;
architecture str of eth_tester is
- constant c_dp_split_reg_adr_w : natural := 1; -- 1 for 1 stream in dp_split
+ -- 1 for 1 stream in dp_split
+ constant c_dp_split_reg_adr_w : natural := 1;
signal ref_sync_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal dp_length_arr : t_natural_arr(g_nof_streams - 1 downto 0); -- tx block length
+ -- tx block length
+ signal dp_length_arr : t_natural_arr(g_nof_streams - 1 downto 0);
-- MM port multiplexers
-- . Tx
diff --git a/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd b/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
index 7d83b02996112591506ca1ff75bae7de8236604e..6743979753018ba20eff902b300895d31c1ee384 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
@@ -30,9 +30,12 @@ use common_lib.common_field_pkg.all;
use common_lib.common_network_layers_pkg.all;
package eth_tester_pkg is
- constant c_eth_tester_bg_block_len_max : natural := c_network_eth_payload_jumbo_max; -- 9000 octets
- constant c_eth_tester_rx_block_len_max : natural := c_network_eth_payload_jumbo_max + c_network_eth_crc_len; -- 9004 octets
- constant c_eth_tester_eth_packet_len_max : natural := c_network_eth_word_align_len + c_network_eth_frame_jumbo_max; -- 9020 octets = 2 word align + 14 header + 9000 + 4 crc
+ -- 9000 octets
+ constant c_eth_tester_bg_block_len_max : natural := c_network_eth_payload_jumbo_max;
+ -- 9004 octets
+ constant c_eth_tester_rx_block_len_max : natural := c_network_eth_payload_jumbo_max + c_network_eth_crc_len;
+ -- 9020 octets = 2 word align + 14 header + 9000 + 4 crc
+ constant c_eth_tester_eth_packet_len_max : natural := c_network_eth_word_align_len + c_network_eth_frame_jumbo_max;
-- Support maximum (2**31-1)/200e6 = 10.7 s BG sync interval for sync timeout
-- in BSN monitors, assuming st_clk at 200 MHz and with maximum NATURAL value
@@ -63,15 +66,18 @@ package eth_tester_pkg is
-- Default use destination MAC/IP/UDP = 0, so these have to be MM programmed
-- before eth_tester packets can be send.
constant c_eth_tester_hdr_field_arr : t_common_field_arr(c_eth_tester_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("word_align" ), "RW", 16, field_default(0) ), -- Tx TSE IP will strip these 2 padding bytes
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ), -- c_eth_tester_eth_dst_mac
+ -- Tx TSE IP will strip these 2 padding bytes
+ ( field_name_pad("word_align" ), "RW", 16, field_default(0) ),
+ -- c_eth_tester_eth_dst_mac
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
+ -- depends on BG block size, so set by data path
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ),
( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
@@ -79,11 +85,14 @@ package eth_tester_pkg is
( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_eth_tester_ip_dst_addr
+ -- c_eth_tester_ip_dst_addr
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ),
( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_eth_tester_udp_dst_port
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
+ -- c_eth_tester_udp_dst_port
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
+ -- depends on BG block size, so set by data path
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ),
( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
( field_name_pad("dp_length" ), "RW", 16, field_default(0) ),
@@ -91,10 +100,13 @@ package eth_tester_pkg is
( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
);
- constant c_eth_tester_reg_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_eth_tester_hdr_field_arr, c_word_w)); -- = 5
- constant c_eth_tester_reg_hdr_dat_addr_span : natural := 2**c_eth_tester_reg_hdr_dat_addr_w; -- = 32
+ -- = 5
+ constant c_eth_tester_reg_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_eth_tester_hdr_field_arr, c_word_w));
+ -- = 32
+ constant c_eth_tester_reg_hdr_dat_addr_span : natural := 2**c_eth_tester_reg_hdr_dat_addr_w;
- constant c_eth_tester_app_hdr_len : natural := 12; -- octets
+ -- octets
+ constant c_eth_tester_app_hdr_len : natural := 12;
-- Source ETH MAC/IP/UDP:
-- . MAC address 00:22:86:08:pp:qq = UNB_ETH_SRC_MAC_BASE in
@@ -109,7 +121,8 @@ package eth_tester_pkg is
-- Default eth_tester UDP port for first stream via 1GbE.
-- Do not use UDP port 0x1388 = 5000 for eth_tester, because port 5000 is
-- used for M&C via 1GbE-I.
- constant c_eth_tester_udp_port : std_logic_vector(15 downto 0) := TO_UVEC(6001, 16); -- 0x1771 = 6001
+ -- 0x1771 = 6001
+ constant c_eth_tester_udp_port : std_logic_vector(15 downto 0) := TO_UVEC(6001, 16);
type t_eth_tester_app_header is record
dp_length : std_logic_vector(15 downto 0);
@@ -127,11 +140,14 @@ package eth_tester_pkg is
-- Map global node index on UniBoard2 to node src MAC, IP and UDP port
function func_eth_tester_gn_index_to_mac_15_0(gn_index : natural; eth_port_index : natural) return std_logic_vector;
- function func_eth_tester_gn_index_to_mac_15_0(gn_index : natural) return std_logic_vector; -- default use 1GbE port I
+ -- default use 1GbE port I
+ function func_eth_tester_gn_index_to_mac_15_0(gn_index : natural) return std_logic_vector;
function func_eth_tester_gn_index_to_ip_15_0(gn_index : natural; eth_port_index : natural) return std_logic_vector;
- function func_eth_tester_gn_index_to_ip_15_0(gn_index : natural) return std_logic_vector; -- default use 1GbE port I
+ -- default use 1GbE port I
+ function func_eth_tester_gn_index_to_ip_15_0(gn_index : natural) return std_logic_vector;
function func_eth_tester_gn_index_to_udp_7_0(gn_index : natural; eth_port_index : natural) return std_logic_vector;
- function func_eth_tester_gn_index_to_udp_7_0(gn_index : natural) return std_logic_vector; -- default use 1GbE port I
+ -- default use 1GbE port I
+ function func_eth_tester_gn_index_to_udp_7_0(gn_index : natural) return std_logic_vector;
-- Map packet header fields to t_eth_tester_header record
function func_eth_tester_map_header(hdr_fields_raw : std_logic_vector) return t_eth_tester_header;
@@ -143,7 +159,8 @@ package body eth_tester_pkg is
-- Assume gn_index < 256.
-- Use default address for 1GbE II (eth_port_index = 0) and
-- an address offset for 1GbE II (eth_port_index = 1)
- constant c_unb_nr : natural := gn_index / c_4; -- 4 PN per Uniboard2
+ -- 4 PN per Uniboard2
+ constant c_unb_nr : natural := gn_index / c_4;
constant c_node_nr : natural := gn_index mod c_4;
constant c_offset : natural := eth_port_index * c_4;
constant c_mac_15_0 : std_logic_vector(15 downto 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr + c_offset, 8);
@@ -153,31 +170,36 @@ package body eth_tester_pkg is
function func_eth_tester_gn_index_to_mac_15_0(gn_index : natural) return std_logic_vector is
begin
- return func_eth_tester_gn_index_to_mac_15_0(gn_index, 0); -- default use 1GbE port I
+ -- default use 1GbE port I
+ return func_eth_tester_gn_index_to_mac_15_0(gn_index, 0);
end func_eth_tester_gn_index_to_mac_15_0;
function func_eth_tester_gn_index_to_ip_15_0(gn_index : natural; eth_port_index : natural) return std_logic_vector is
-- Assume gn_index < 256.
-- Use default address for 1GbE II (eth_port_index = 0) and
-- an address offset for 1GbE II (eth_port_index = 1)
- constant c_unb_nr : natural := gn_index / c_4; -- 4 PN per Uniboard2
+ -- 4 PN per Uniboard2
+ constant c_unb_nr : natural := gn_index / c_4;
constant c_node_nr : natural := gn_index mod c_4;
constant c_offset : natural := eth_port_index * c_4;
- constant c_ip_15_0 : std_logic_vector(15 downto 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr + 1 + c_offset, 8); -- +1 to avoid IP = *.*.*.0
+ -- +1 to avoid IP = *.*.*.0
+ constant c_ip_15_0 : std_logic_vector(15 downto 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr + 1 + c_offset, 8);
begin
return c_ip_15_0;
end func_eth_tester_gn_index_to_ip_15_0;
function func_eth_tester_gn_index_to_ip_15_0(gn_index : natural) return std_logic_vector is
begin
- return func_eth_tester_gn_index_to_ip_15_0(gn_index, 0); -- default use 1GbE port I
+ -- default use 1GbE port I
+ return func_eth_tester_gn_index_to_ip_15_0(gn_index, 0);
end func_eth_tester_gn_index_to_ip_15_0;
function func_eth_tester_gn_index_to_udp_7_0(gn_index : natural; eth_port_index : natural) return std_logic_vector is
-- Assume gn_index < 128.
-- Use default udp port for 1GbE I (eth_port_index = 0) and
-- an increment udp port for 1GbE II (eth_port_index = 1)
- constant c_offset : natural := eth_port_index * c_128; -- MSbit 7
+ -- MSbit 7
+ constant c_offset : natural := eth_port_index * c_128;
constant c_udp_7_0 : std_logic_vector(7 downto 0) := TO_UVEC(gn_index + c_offset, 8);
begin
return c_udp_7_0;
@@ -185,7 +207,8 @@ package body eth_tester_pkg is
function func_eth_tester_gn_index_to_udp_7_0(gn_index : natural) return std_logic_vector is
begin
- return func_eth_tester_gn_index_to_udp_7_0(gn_index, 0); -- default use 1GbE port I
+ -- default use 1GbE port I
+ return func_eth_tester_gn_index_to_udp_7_0(gn_index, 0);
end func_eth_tester_gn_index_to_udp_7_0;
function func_eth_tester_map_header(hdr_fields_raw : std_logic_vector) return t_eth_tester_header is
diff --git a/libraries/io/eth/src/vhdl/eth_tester_rx.vhd b/libraries/io/eth/src/vhdl/eth_tester_rx.vhd
index e64d5c042e51cbb413214b7d26899e1bfe7b6a17..9ce63977a42b7069479bc6ed63a228dfc0a7d886 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_rx.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_rx.vhd
@@ -37,12 +37,15 @@ use work.eth_tester_pkg.all;
entity eth_tester_rx is
generic (
- g_bg_sync_timeout : natural := 220 * 10**6; -- 10% margin for nominal 1 s with st_clk at 200MHz
+ -- 10% margin for nominal 1 s with st_clk at 200MHz
+ g_bg_sync_timeout : natural := 220 * 10**6;
g_nof_octet_unpack : natural := 1;
- g_nof_octet_input : natural := 4; -- must be multiple of g_nof_octet_generate
+ -- must be multiple of g_nof_octet_generate
+ g_nof_octet_input : natural := 4;
g_use_dp_header : boolean := true;
g_hdr_field_arr : t_common_field_arr := c_eth_tester_hdr_field_arr;
- g_remove_crc : boolean := true -- use TRUE when using sim_tse and tech_tse link interface,
+ -- use TRUE when using sim_tse and tech_tse link interface,
+ g_remove_crc : boolean := true
-- use FALSE when streaming link interface
);
port (
@@ -53,7 +56,8 @@ entity eth_tester_rx is
st_clk : in std_logic;
ref_sync : in std_logic;
- exp_length : in natural range 0 to 2**c_halfword_w - 1; -- 16 bit
+ -- 16 bit
+ exp_length : in natural range 0 to 2**c_halfword_w - 1;
-- UDP receive interface
rx_udp_sosi : in t_dp_sosi;
@@ -67,7 +71,8 @@ entity eth_tester_rx is
end eth_tester_rx;
architecture str of eth_tester_rx is
- constant c_nof_total_counts : natural := 3; -- 0 = nof_sop, 1 = nof_valid, 2 = nof_crc_corrupt
+ -- 0 = nof_sop, 1 = nof_valid, 2 = nof_crc_corrupt
+ constant c_nof_total_counts : natural := 3;
constant c_empty_w : natural := ceil_log2(g_nof_octet_input);
constant c_error_w : natural := 1;
@@ -133,8 +138,10 @@ begin
snk_in_arr(0) => rx_udp_sosi,
src_out_arr(0) => rx_offload_sosi,
- hdr_fields_out_arr(0) => hdr_fields_out_slv, -- Valid at src_out_arr(i).sop, use for sosi.sync
- hdr_fields_raw_arr(0) => hdr_fields_raw_slv -- Valid at src_out_arr(i).sop and beyond, use for sosi.bsn
+ -- Valid at src_out_arr(i).sop, use for sosi.sync
+ hdr_fields_out_arr(0) => hdr_fields_out_slv,
+ -- Valid at src_out_arr(i).sop and beyond, use for sosi.bsn
+ hdr_fields_raw_arr(0) => hdr_fields_raw_slv
);
-- View record in Wave Window
@@ -170,7 +177,8 @@ begin
u_rx_fifo : entity dp_lib.dp_fifo_sc
generic map (
g_data_w => c_in_data_w,
- g_bsn_w => c_diag_bg_bsn_init_w, -- = 64 bit
+ -- = 64 bit
+ g_bsn_w => c_diag_bg_bsn_init_w,
g_empty_w => c_empty_w,
g_error_w => c_error_w,
g_use_bsn => true,
@@ -244,9 +252,12 @@ begin
end if;
end process;
- in_strobe_arr(0) <= unpacked_sosi.sop; -- count total nof Rx packets
- in_strobe_arr(1) <= unpacked_sosi.valid; -- count total nof Rx valid samples
- in_strobe_arr(2) <= crc_corrupt; -- count total nof corrupted Rx packets
+ -- count total nof Rx packets
+ in_strobe_arr(0) <= unpacked_sosi.sop;
+ -- count total nof Rx valid samples
+ in_strobe_arr(1) <= unpacked_sosi.valid;
+ -- count total nof corrupted Rx packets
+ in_strobe_arr(2) <= crc_corrupt;
u_dp_strobe_total_count : entity dp_lib.dp_strobe_total_count
generic map (
diff --git a/libraries/io/eth/src/vhdl/eth_tester_tx.vhd b/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
index 2544df663b6c2ee9ed1d22ab1802262c3c22ed3a..df315316e69e620d6c8db2f4bbde0d261f1ff7a5 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
@@ -45,9 +45,11 @@ use work.eth_tester_pkg.all;
entity eth_tester_tx is
generic (
- g_bg_sync_timeout : natural := 220 * 10**6; -- 10% margin for nominal 1 s with st_clk at 200MHz
+ -- 10% margin for nominal 1 s with st_clk at 200MHz
+ g_bg_sync_timeout : natural := 220 * 10**6;
g_nof_octet_generate : natural := 1;
- g_nof_octet_output : natural := 4; -- must be multiple of g_nof_octet_generate
+ -- must be multiple of g_nof_octet_generate
+ g_nof_octet_output : natural := 4;
g_use_eth_header : boolean := true;
g_use_ip_udp_header : boolean := true;
g_use_dp_header : boolean := true;
@@ -70,7 +72,8 @@ entity eth_tester_tx is
ip_src_addr : in std_logic_vector(c_network_ip_addr_w - 1 downto 0);
udp_src_port : in std_logic_vector(c_network_udp_port_w - 1 downto 0);
- tx_length : out natural range 0 to 2**c_halfword_w - 1; -- 16 bit
+ -- 16 bit
+ tx_length : out natural range 0 to 2**c_halfword_w - 1;
tx_fifo_rd_emp : out std_logic;
tx_udp_sosi : out t_dp_sosi;
@@ -102,9 +105,11 @@ architecture str of eth_tester_tx is
constant c_fifo_size : natural := true_log_pow2(c_fifo_fill + c_packet_sz_max);
constant c_fifo_size_w : natural := ceil_log2(c_fifo_size);
- constant c_nof_total_counts : natural := 1; -- one to count Tx packets
+ -- one to count Tx packets
+ constant c_nof_total_counts : natural := 1;
- constant c_nof_repack_words : natural := g_nof_octet_output / g_nof_octet_generate; -- yields integer as g_nof_octet_output is multiple of g_nof_octet_generate.
+ -- yields integer as g_nof_octet_output is multiple of g_nof_octet_generate.
+ constant c_nof_repack_words : natural := g_nof_octet_output / g_nof_octet_generate;
constant c_generate_data_w : natural := g_nof_octet_generate * c_octet_w;
constant c_out_data_w : natural := g_nof_octet_output * c_octet_w;
constant c_nof_symbols_max : natural := c_network_eth_payload_jumbo_max;
@@ -167,7 +172,8 @@ begin
generic map (
g_nof_streams => 1,
g_use_bg_buffer_ram => false,
- g_buf_addr_w => c_diag_bg_mem_adrs_w, -- = 24, use full range 2**24 for BG addr --> data values
+ -- = 24, use full range 2**24 for BG addr --> data values
+ g_buf_addr_w => c_diag_bg_mem_adrs_w,
g_buf_dat_w => c_octet_w
)
port map (
@@ -176,9 +182,11 @@ begin
mm_clk => mm_clk,
dp_rst => st_rst,
dp_clk => st_clk,
- en_sync => st_pps, -- block generator enable sync pulse in ST clock domain
+ -- block generator enable sync pulse in ST clock domain
+ en_sync => st_pps,
-- MM interface
- reg_bg_ctrl_mosi => reg_bg_ctrl_copi, -- BG control register (one for all streams)
+ -- BG control register (one for all streams)
+ reg_bg_ctrl_mosi => reg_bg_ctrl_copi,
reg_bg_ctrl_miso => reg_bg_ctrl_cipo,
-- ST interface
bg_ctrl_hold_arr(0) => bg_ctrl_hold,
@@ -246,7 +254,8 @@ begin
in_split_siso <= out_split_siso_arr(1);
end generate;
- u_pack : entity dp_lib.dp_repack_data -- repack generated words to output width.
+ -- repack generated words to output width.
+ u_pack : entity dp_lib.dp_repack_data
generic map (
g_in_dat_w => c_generate_data_w,
g_in_nof_words => c_nof_repack_words,
@@ -258,7 +267,8 @@ begin
port map (
rst => st_rst,
clk => st_clk,
- snk_out => out_split_siso_arr(1), -- connect dp_split head part, tail is discarded.
+ -- connect dp_split head part, tail is discarded.
+ snk_out => out_split_siso_arr(1),
snk_in => out_split_sosi_arr(1),
src_out => tx_packed_sosi
);
@@ -266,7 +276,8 @@ begin
u_tx_fifo : entity dp_lib.dp_fifo_fill_eop
generic map (
g_data_w => c_out_data_w,
- g_bsn_w => c_diag_bg_bsn_init_w, -- = 64 bit
+ -- = 64 bit
+ g_bsn_w => c_diag_bg_bsn_init_w,
g_empty_w => c_empty_w,
g_use_bsn => true,
g_use_empty => true,
@@ -334,7 +345,8 @@ begin
-- The bg_block_len is still valid because bg_ctrl_hold holds the BG settings
-- until it restarts, so no need to pass bg_block_len on via e.g. the channel
-- field in u_fifo.
- bg_block_len <= split_nof_symbols when c_use_split else TO_UINT(bg_ctrl_hold.samples_per_packet(15 downto 0)); -- packet lenghts fit in 16b
+ -- packet lenghts fit in 16b
+ bg_block_len <= split_nof_symbols when c_use_split else TO_UINT(bg_ctrl_hold.samples_per_packet(15 downto 0));
app_total_length <= g_hdr_app_len + bg_block_len when rising_edge(st_clk);
udp_total_length <= c_network_udp_header_len + app_total_length when rising_edge(st_clk);
ip_total_length <= c_network_ip_header_len + udp_total_length when rising_edge(st_clk);
@@ -383,7 +395,8 @@ begin
src_out_arr(0) => tx_offload_sosi,
src_in_arr(0) => tx_offload_siso,
- hdr_fields_in_arr(0) => hdr_fields_slv_in, -- hdr_fields_slv_in_arr(i) is considered valid @ snk_in_arr(i).sop
+ -- hdr_fields_slv_in_arr(i) is considered valid @ snk_in_arr(i).sop
+ hdr_fields_in_arr(0) => hdr_fields_slv_in,
hdr_fields_out_arr(0) => hdr_fields_slv_tx
);
@@ -459,7 +472,8 @@ begin
in_sosi_arr(0) => tx_fifo_sosi
);
- in_strobe_arr(0) <= tx_fifo_sosi.sop when rising_edge(st_clk); -- count total nof Tx packets
+ -- count total nof Tx packets
+ in_strobe_arr(0) <= tx_fifo_sosi.sop when rising_edge(st_clk);
u_dp_strobe_total_count : entity dp_lib.dp_strobe_total_count
generic map (
diff --git a/libraries/io/eth/src/vhdl/eth_udp_channel.vhd b/libraries/io/eth/src/vhdl/eth_udp_channel.vhd
index 76bdc91b615317005d7ef87966cb643d5f6859e8..a4ea29a1ac7fa59fa76b1650458a8de025aa9c61 100644
--- a/libraries/io/eth/src/vhdl/eth_udp_channel.vhd
+++ b/libraries/io/eth/src/vhdl/eth_udp_channel.vhd
@@ -63,11 +63,13 @@ begin
-- Determine the demux UDP stream channel number
p_udp_ports : process(hdr_status, reg_demux)
begin
- nxt_channel <= 0; -- default use control via channel 0
+ -- default use control via channel 0
+ nxt_channel <= 0;
for I in 1 to c_eth_nof_udp_ports loop
if hdr_status.is_udp = '1' and reg_demux.udp_ports_en(I) = '1' then
if unsigned(hdr_status.udp_port) = unsigned(reg_demux.udp_ports(I)) then
- nxt_channel <= I; -- UDP offload channels : channel>0
+ -- UDP offload channels : channel>0
+ nxt_channel <= I;
end if;
end if;
end loop;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth.vhd b/libraries/io/eth/tb/vhdl/tb_eth.vhd
index 9a880edc0917423d26593dff98b1f4c8d74e23e9..1124cbc83c502adab498634f678285909869e3e4 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth.vhd
@@ -60,10 +60,14 @@ entity tb_eth is
g_technology_dut : natural := c_tech_select_default;
g_technology_lcu : natural := c_tech_select_default;
g_sim : boolean := true;
- g_sim_level : natural := 1; -- when g_sim = TRUE, then 0 = use IP; 1 = use fast serdes model
- g_frm_discard_en : boolean := false; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
- g_flush_test_en : boolean := false; -- when TRUE send many large frames to enforce flush in eth_buffer
- g_tb_end : boolean := true; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ -- when g_sim = TRUE, then 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 1;
+ -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+ g_frm_discard_en : boolean := false;
+ -- when TRUE send many large frames to enforce flush in eth_buffer
+ g_flush_test_en : boolean := false;
+ -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ g_tb_end : boolean := true;
-- g_data_type = c_tb_tech_tse_data_type_symbols = 0
-- g_data_type = c_tb_tech_tse_data_type_counter = 1
-- g_data_type = c_tb_tech_tse_data_type_arp = 2
@@ -77,28 +81,37 @@ entity tb_eth is
end tb_eth;
architecture tb of tb_eth is
- constant sys_clk_period : time := 10 ns; -- 100 MHz
- constant eth_clk_period : time := 8 ns; -- 125 MHz
+ -- 100 MHz
+ constant sys_clk_period : time := 10 ns;
+ -- 125 MHz
+ constant eth_clk_period : time := 8 ns;
constant cable_delay : time := sel_a_b(g_sim_level = 0, 12 ns, 0 ns);
- constant c_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ constant c_cross_clock_domain : boolean := true;
-- TSE constants
constant c_promis_en : boolean := false;
- constant c_tx_ready_latency : natural := c_tech_tse_tx_ready_latency; -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
- constant c_nof_tx_not_valid : natural := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
+ constant c_tx_ready_latency : natural := c_tech_tse_tx_ready_latency;
+ -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ constant c_nof_tx_not_valid : natural := 0;
-- Payload user data
- constant c_tb_nof_data : natural := 0; -- nof UDP user data, nof ping padding data
- constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data; -- nof IP data,
+ -- nof UDP user data, nof ping padding data
+ constant c_tb_nof_data : natural := 0;
+ -- nof IP data,
+ constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data;
-- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
- constant c_tb_reply_payload : boolean := true; -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
+ -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
+ constant c_tb_reply_payload : boolean := true;
-- Packet headers
-- . Ethernet header
constant c_lcu_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"10FA01020300";
- constant c_dut_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ -- = 12-34-56-78-9A-BC
+ constant c_dut_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"123456789ABC";
constant c_dut_src_mac_hi : natural := TO_UINT(c_dut_src_mac(c_network_eth_mac_addr_w - 1 downto c_word_w));
constant c_dut_src_mac_lo : natural := TO_UINT(c_dut_src_mac( c_word_w - 1 downto 0));
-- support only ARP and IPv4 over ETH
@@ -111,12 +124,16 @@ architecture tb of tb_eth is
constant c_discard_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
src_mac => c_lcu_src_mac,
eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w));
- constant c_exp_eth_header : t_network_eth_header := (dst_mac => c_tx_eth_header.src_mac, -- \/
- src_mac => c_tx_eth_header.dst_mac, -- /\
- eth_type => c_tx_eth_header.eth_type); -- =
+ -- \/
+ constant c_exp_eth_header : t_network_eth_header := (dst_mac => c_tx_eth_header.src_mac,
+ -- /\
+ src_mac => c_tx_eth_header.dst_mac,
+ -- =
+ eth_type => c_tx_eth_header.eth_type);
-- . IP header
- constant c_lcu_ip_addr : natural := 16#05060708#; -- = 05:06:07:08
+ -- = 05:06:07:08
+ constant c_lcu_ip_addr : natural := 16#05060708#;
constant c_dut_ip_addr : natural := 16#01020304#;
constant c_tb_ip_total_length : natural := c_network_ip_total_length + c_tb_ip_nof_data;
@@ -133,22 +150,35 @@ architecture tb of tb_eth is
fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
- header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
+ -- init value (or try 0xEBBD = 60349)
+ header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w),
src_ip_addr => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
dst_ip_addr => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w));
- constant c_exp_ip_header : t_network_ip_header := (version => c_tx_ip_header.version, -- =
- header_length => c_tx_ip_header.header_length, -- =
- services => c_tx_ip_header.services, -- =
- total_length => c_tx_ip_header.total_length, -- =
- identification => c_tx_ip_header.identification, -- =
- flags => c_tx_ip_header.flags, -- =
- fragment_offset => c_tx_ip_header.fragment_offset, -- =
- time_to_live => c_tx_ip_header.time_to_live, -- =
- protocol => c_tx_ip_header.protocol, -- =
- header_checksum => c_tx_ip_header.header_checksum, -- init value
- src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
- dst_ip_addr => c_tx_ip_header.src_ip_addr); -- /\
+ -- =
+ constant c_exp_ip_header : t_network_ip_header := (version => c_tx_ip_header.version,
+ -- =
+ header_length => c_tx_ip_header.header_length,
+ -- =
+ services => c_tx_ip_header.services,
+ -- =
+ total_length => c_tx_ip_header.total_length,
+ -- =
+ identification => c_tx_ip_header.identification,
+ -- =
+ flags => c_tx_ip_header.flags,
+ -- =
+ fragment_offset => c_tx_ip_header.fragment_offset,
+ -- =
+ time_to_live => c_tx_ip_header.time_to_live,
+ -- =
+ protocol => c_tx_ip_header.protocol,
+ -- init value
+ header_checksum => c_tx_ip_header.header_checksum,
+ -- \/
+ src_ip_addr => c_tx_ip_header.dst_ip_addr,
+ -- /\
+ dst_ip_addr => c_tx_ip_header.src_ip_addr);
-- . ARP packet
constant c_tx_arp_packet : t_network_arp_packet := (htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
@@ -165,62 +195,92 @@ architecture tb of tb_eth is
ptype => c_tx_arp_packet.ptype,
hlen => c_tx_arp_packet.hlen,
plen => c_tx_arp_packet.plen,
- oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
- sha => c_tx_arp_packet.tha, -- \/
- spa => c_tx_arp_packet.tpa, -- /\ \/
- tha => c_tx_arp_packet.sha, -- / \ /\
- tpa => c_tx_arp_packet.spa); -- / \
+ -- reply
+ oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w),
+ -- \/
+ sha => c_tx_arp_packet.tha,
+ -- /\ \/
+ spa => c_tx_arp_packet.tpa,
+ -- / \ /\
+ tha => c_tx_arp_packet.sha,
+ -- / \
+ tpa => c_tx_arp_packet.spa);
-- . ICMP header
- constant c_tx_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w), -- ping request
+ -- ping request
+ constant c_tx_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w),
code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
- checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
+ -- init value
+ checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w),
id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
-- checksum is 0x0800 + original checksum
constant c_exp_icmp_checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0) := TO_UVEC( 2048 + TO_UINT(c_tx_icmp_header.checksum), c_network_icmp_checksum_w);
- constant c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
+ -- ping reply
+ constant c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w),
code => c_tx_icmp_header.code,
checksum => c_exp_icmp_checksum,
id => c_tx_icmp_header.id,
sequence => c_tx_icmp_header.sequence);
-- . UDP header
- constant c_dut_udp_port_ctrl : natural := 11; -- ETH demux UDP for control
- constant c_dut_udp_port_st0 : natural := 57; -- ETH demux UDP port 0
- constant c_dut_udp_port_st1 : natural := 58; -- ETH demux UDP port 1
- constant c_dut_udp_port_st2 : natural := 59; -- ETH demux UDP port 2
- constant c_dut_udp_port_en : natural := 16#10000#; -- ETH demux UDP port enable bit 16
- constant c_lcu_udp_port : natural := 10; -- UDP port used for src_port
- constant c_dut_udp_port_st : natural := c_dut_udp_port_st0; -- UDP port used for dst_port
+ -- ETH demux UDP for control
+ constant c_dut_udp_port_ctrl : natural := 11;
+ -- ETH demux UDP port 0
+ constant c_dut_udp_port_st0 : natural := 57;
+ -- ETH demux UDP port 1
+ constant c_dut_udp_port_st1 : natural := 58;
+ -- ETH demux UDP port 2
+ constant c_dut_udp_port_st2 : natural := 59;
+ -- ETH demux UDP port enable bit 16
+ constant c_dut_udp_port_en : natural := 16#10000#;
+ -- UDP port used for src_port
+ constant c_lcu_udp_port : natural := 10;
+ -- UDP port used for dst_port
+ constant c_dut_udp_port_st : natural := c_dut_udp_port_st0;
constant c_tb_udp_total_length : natural := c_network_udp_total_length + c_tb_nof_data;
constant c_tx_udp_header : t_network_udp_header := (src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
- dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
+ -- or use c_dut_udp_port_st#
+ dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w),
total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
- checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
-
- constant c_exp_udp_header : t_network_udp_header := (src_port => c_tx_udp_header.dst_port, -- \/
- dst_port => c_tx_udp_header.src_port, -- /\
- total_length => c_tx_udp_header.total_length, -- =
- checksum => c_tx_udp_header.checksum); -- init value
-
- signal tx_total_header : t_network_total_header; -- transmitted packet header
- signal discard_total_header: t_network_total_header; -- transmitted packet header for to be discarded packet
- signal exp_total_header : t_network_total_header; -- expected received packet header
+ -- init value
+ checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w));
+
+ -- \/
+ constant c_exp_udp_header : t_network_udp_header := (src_port => c_tx_udp_header.dst_port,
+ -- /\
+ dst_port => c_tx_udp_header.src_port,
+ -- =
+ total_length => c_tx_udp_header.total_length,
+ -- init value
+ checksum => c_tx_udp_header.checksum);
+
+ -- transmitted packet header
+ signal tx_total_header : t_network_total_header;
+ -- transmitted packet header for to be discarded packet
+ signal discard_total_header: t_network_total_header;
+ -- expected received packet header
+ signal exp_total_header : t_network_total_header;
-- ETH control
constant c_dut_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
constant c_dut_control_tx_en : natural := 2**c_eth_mm_reg_control_bi.tx_en;
-- Clocks and reset
- signal eth_clk : std_logic := '0'; -- tse reference clock
- signal sys_clk : std_logic := '0'; -- system clock
- signal st_clk : std_logic; -- stream clock
- signal st_rst : std_logic := '1'; -- reset synchronous with st_clk
- signal mm_clk : std_logic; -- memory-mapped bus clock
- signal mm_rst : std_logic := '1'; -- reset synchronous with mm_clk
+ -- tse reference clock
+ signal eth_clk : std_logic := '0';
+ -- system clock
+ signal sys_clk : std_logic := '0';
+ -- stream clock
+ signal st_clk : std_logic;
+ -- reset synchronous with st_clk
+ signal st_rst : std_logic := '1';
+ -- memory-mapped bus clock
+ signal mm_clk : std_logic;
+ -- reset synchronous with mm_clk
+ signal mm_rst : std_logic := '1';
-- ETH TSE interface
signal dut_tse_init : std_logic := '1';
@@ -279,8 +339,10 @@ architecture tb of tb_eth is
begin
-- run 50 us
- eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
- sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
+ -- TSE reference clock
+ eth_clk <= not eth_clk after eth_clk_period / 2;
+ -- System clock
+ sys_clk <= not sys_clk after sys_clk_period / 2;
mm_clk <= sys_clk;
st_clk <= sys_clk;
@@ -351,20 +413,28 @@ begin
while mm_rst = '1' loop wait until rising_edge(mm_clk); end loop;
-- Setup the DEMUX UDP
- proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 0, c_dut_udp_port_en + c_dut_udp_port_st0, mm_clk, eth_reg_miso, eth_reg_mosi); -- UDP port stream 0
- proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 1, c_dut_udp_port_en + c_dut_udp_port_st1, mm_clk, eth_reg_miso, eth_reg_mosi); -- UDP port stream 1
- proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 2, c_dut_udp_port_en + c_dut_udp_port_st2, mm_clk, eth_reg_miso, eth_reg_mosi); -- UDP port stream 2
+ -- UDP port stream 0
+ proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 0, c_dut_udp_port_en + c_dut_udp_port_st0, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- UDP port stream 1
+ proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 1, c_dut_udp_port_en + c_dut_udp_port_st1, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- UDP port stream 2
+ proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 2, c_dut_udp_port_en + c_dut_udp_port_st2, mm_clk, eth_reg_miso, eth_reg_mosi);
proc_mem_mm_bus_rd(c_eth_reg_demux_wi + 0, mm_clk, eth_reg_miso, eth_reg_mosi);
proc_mem_mm_bus_rd(c_eth_reg_demux_wi + 1, mm_clk, eth_reg_miso, eth_reg_mosi);
proc_mem_mm_bus_rd(c_eth_reg_demux_wi + 2, mm_clk, eth_reg_miso, eth_reg_mosi);
-- Setup the RX config
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 0, c_dut_src_mac_lo, mm_clk, eth_reg_miso, eth_reg_mosi); -- control MAC address lo word
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 1, c_dut_src_mac_hi, mm_clk, eth_reg_miso, eth_reg_mosi); -- control MAC address hi halfword
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 2, c_dut_ip_addr, mm_clk, eth_reg_miso, eth_reg_mosi); -- control IP address
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 3, c_dut_udp_port_ctrl, mm_clk, eth_reg_miso, eth_reg_mosi); -- control UDP port
+ -- control MAC address lo word
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 0, c_dut_src_mac_lo, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- control MAC address hi halfword
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 1, c_dut_src_mac_hi, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- control IP address
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 2, c_dut_ip_addr, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- control UDP port
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 3, c_dut_udp_port_ctrl, mm_clk, eth_reg_miso, eth_reg_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_dut_control_rx_en, mm_clk, eth_reg_miso, eth_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_dut_control_rx_en, mm_clk, eth_reg_miso, eth_reg_mosi);
dut_eth_init <= '0';
-- Wait for TSE init
@@ -377,15 +447,18 @@ begin
-- wait for rx_avail interrupt
if eth_reg_interrupt = '1' then
-- read status register to read the status
- proc_mem_mm_bus_rd(c_eth_reg_status_wi + 0, mm_clk, eth_reg_miso, eth_reg_mosi); -- read result available in eth_mm_reg_status
+ -- read result available in eth_mm_reg_status
+ proc_mem_mm_bus_rd(c_eth_reg_status_wi + 0, mm_clk, eth_reg_miso, eth_reg_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
eth_mm_reg_status <= func_eth_mm_reg_status(eth_reg_miso.rddata);
wait until rising_edge(mm_clk);
-- write status register to acknowledge the interrupt
- proc_mem_mm_bus_wr(c_eth_reg_status_wi + 0, 0, mm_clk, eth_reg_miso, eth_reg_mosi); -- void value
+ -- void value
+ proc_mem_mm_bus_wr(c_eth_reg_status_wi + 0, 0, mm_clk, eth_reg_miso, eth_reg_mosi);
-- prepare control register for response
if c_tb_reply_payload = true then
- eth_mm_reg_control.tx_nof_words <= INCR_UVEC(eth_mm_reg_status.rx_nof_words, -1); -- -1 to skip the CRC word for the response
+ -- -1 to skip the CRC word for the response
+ eth_mm_reg_control.tx_nof_words <= INCR_UVEC(eth_mm_reg_status.rx_nof_words, -1);
eth_mm_reg_control.tx_empty <= eth_mm_reg_status.rx_empty;
else
eth_mm_reg_control.tx_nof_words <= TO_UVEC(c_network_total_header_32b_nof_words, c_eth_max_frame_nof_words_w);
@@ -410,7 +483,8 @@ begin
v_eth_control_word := func_eth_mm_reg_control(eth_mm_reg_control);
proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, TO_UINT(v_eth_control_word), mm_clk, eth_reg_miso, eth_reg_mosi);
-- write continue register to make the ETH module continue
- proc_mem_mm_bus_wr(c_eth_reg_continue_wi, 0, mm_clk, eth_reg_miso, eth_reg_mosi); -- void value
+ -- void value
+ proc_mem_mm_bus_wr(c_eth_reg_continue_wi, 0, mm_clk, eth_reg_miso, eth_reg_mosi);
end if;
wait until rising_edge(mm_clk);
end loop;
@@ -454,7 +528,8 @@ begin
lcu_tx_sosi.empty <= (others => '0');
lcu_tx_sosi.err <= (others => '0');
-- . MAC specific
- lcu_tx_mac_in.crc_fwd <= '0'; -- when '0' then TSE MAC generates the TX CRC field
+ -- when '0' then TSE MAC generates the TX CRC field
+ lcu_tx_mac_in.crc_fwd <= '0';
while lcu_init /= '0' loop wait until rising_edge(st_clk); end loop;
for I in 0 to 9 loop wait until rising_edge(st_clk); end loop;
@@ -633,9 +708,11 @@ begin
rx_timeout <= 0;
elsif rx_pkt_cnt > 0 then
if tx_pkt_cnt = rx_pkt_cnt + rx_pkt_discarded_cnt + TO_UINT(rx_pkt_flushed_cnt) then
- rx_end <= '1'; -- do not wait for rx_timeout if all expected packets have been received
+ -- do not wait for rx_timeout if all expected packets have been received
+ rx_end <= '1';
end if;
- elsif rx_timeout > 5000 then -- sufficiently large value determined by trial
+ -- sufficiently large value determined by trial
+ elsif rx_timeout > 5000 then
rx_end <= '1';
end if;
wait until rising_edge(st_clk);
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd b/libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd
index 60e4727e698b334b8922460be6fc3ffaabce6664..3c6071ade0af28cdfe56bb960182073ee642c896 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd
@@ -46,13 +46,15 @@ entity tb_eth_checksum is
end tb_eth_checksum;
architecture tb of tb_eth_checksum is
- constant clk_period : time := 10 ns; -- 100 MHz
+ -- 100 MHz
+ constant clk_period : time := 10 ns;
constant c_exp_checksum : natural := 16#442E#;
-- Minimum nof clk cycles between eop and sop
constant c_checksum_latency : natural := 3;
- constant c_wait_eop_sop : natural := 10; -- >= c_checksum_latency-1;
+ -- >= c_checksum_latency-1;
+ constant c_wait_eop_sop : natural := 10;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
@@ -172,7 +174,8 @@ begin
src_out.sop <= '0';
src_out.data <= RESIZE_DP_DATA(X"44224000");
wait until rising_edge(clk);
- src_out.data <= RESIZE_DP_DATA(X"80061e2b"); -- overwrite these "0000" with the last 2, now empty, bytes "1e2b", to keep the seem expected result
+ -- overwrite these "0000" with the last 2, now empty, bytes "1e2b", to keep the seem expected result
+ src_out.data <= RESIZE_DP_DATA(X"80061e2b");
wait until rising_edge(clk);
src_out.data <= RESIZE_DP_DATA(X"8c7c19ac");
wait until rising_edge(clk);
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_crc_ctrl.vhd b/libraries/io/eth/tb/vhdl/tb_eth_crc_ctrl.vhd
index 115c8f00b04ad1668726e60cc5b2405051553399..0b6442c0330b53bda6d1526647b6976baa5f7436 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_crc_ctrl.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_crc_ctrl.vhd
@@ -41,15 +41,21 @@ end tb_eth_crc_ctrl;
architecture tb of tb_eth_crc_ctrl is
-- DUT ready latency
- constant c_dut_latency : natural := 1; -- fixed 1 for dp_pipeline
- constant c_tx_latency : natural := c_dut_latency; -- TX ready latency of TB
- constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ -- fixed 1 for dp_pipeline
+ constant c_dut_latency : natural := 1;
+ -- TX ready latency of TB
+ constant c_tx_latency : natural := c_dut_latency;
+ -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0);
constant c_tx_offset_sop : natural := 0;
- constant c_tx_period_sop : natural := 17; -- sop in data valid cycle 0, 17, ...
+ -- sop in data valid cycle 0, 17, ...
+ constant c_tx_period_sop : natural := 17;
constant c_tx_offset_eop : natural := c_tx_period_sop - 1;
constant c_tx_period_eop : natural := c_tx_period_sop;
- constant c_rx_latency : natural := c_dut_latency; -- RX ready latency from DUT
- constant c_verify_en_wait : natural := 5; -- wait some cycles before asserting verify enable
+ -- RX ready latency from DUT
+ constant c_rx_latency : natural := c_dut_latency;
+ -- wait some cycles before asserting verify enable
+ constant c_verify_en_wait : natural := 5;
constant c_random_w : natural := 19;
@@ -95,10 +101,13 @@ architecture tb of tb_eth_crc_ctrl is
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := TO_UVEC(1000, c_dp_data_w);
- constant c_last_word : natural := 16#70717273#; -- 0 or > 0, use 0x70717273 to observe all 4 bytes
- constant c_empty : natural := 0; -- try all possible values: 0, 1, 2, or 3
+ -- 0 or > 0, use 0x70717273 to observe all 4 bytes
+ constant c_last_word : natural := 16#70717273#;
+ -- try all possible values: 0, 1, 2, or 3
+ constant c_empty : natural := 0;
- signal snk_in_error : std_logic_vector(c_word_w - 1 downto 0); -- use full word range, instead of only range [c_tse_error_w-1:0], to observe all 4 bytes in this tb
+ -- use full word range, instead of only range [c_tse_error_w-1:0], to observe all 4 bytes in this tb
+ signal snk_in_error : std_logic_vector(c_word_w - 1 downto 0);
signal snk_in : t_dp_sosi;
signal snk_out : t_dp_siso;
@@ -143,7 +152,8 @@ begin
-- Interface TB tx - DUT sink
in_ready <= snk_out.ready;
- snk_in_error <= TO_UVEC(c_last_word, snk_in_error'length); -- use odd number for test purposes, because bit [0] must contain the logic OR of bits [1:5]
+ -- use odd number for test purposes, because bit [0] must contain the logic OR of bits [1:5]
+ snk_in_error <= TO_UVEC(c_last_word, snk_in_error'length);
snk_in.data <= RESIZE_DP_DATA(in_data);
snk_in.valid <= in_val;
snk_in.sop <= in_sop;
@@ -164,7 +174,8 @@ begin
clk => clk,
-- Streaming Sink
- snk_in_err => snk_in_error, -- error vector from TSE MAC t_eth_stream
+ -- error vector from TSE MAC t_eth_stream
+ snk_in_err => snk_in_error,
snk_in => snk_in,
snk_out => snk_out,
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_hdr.vhd b/libraries/io/eth/tb/vhdl/tb_eth_hdr.vhd
index 2a04c64dcd8cfba247491c8e81bc116f1428e6ac..fe73669504803a2776b51488bc57bf55139cce7f 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_hdr.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_hdr.vhd
@@ -41,15 +41,20 @@ end tb_eth_hdr;
architecture tb of tb_eth_hdr is
-- DUT ready latency
- constant c_dut_latency : natural := 1; -- fixed 1 for eth_hdr
- constant c_tx_latency : natural := c_dut_latency; -- TX ready latency of TB
- constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ -- fixed 1 for eth_hdr
+ constant c_dut_latency : natural := 1;
+ -- TX ready latency of TB
+ constant c_tx_latency : natural := c_dut_latency;
+ -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ constant c_tx_void : natural := sel_a_b(c_tx_latency, 1, 0);
constant c_tx_offset_sop : natural := 0;
constant c_tx_period_sop : natural := 30;
constant c_tx_offset_eop : natural := c_tx_period_sop - 1;
constant c_tx_period_eop : natural := c_tx_period_sop;
- constant c_rx_latency : natural := c_dut_latency; -- RX ready latency from DUT
- constant c_verify_en_wait : natural := 16; -- wait some cycles before asserting verify enable
+ -- RX ready latency from DUT
+ constant c_rx_latency : natural := c_dut_latency;
+ -- wait some cycles before asserting verify enable
+ constant c_verify_en_wait : natural := 16;
constant c_random_w : natural := 19;
@@ -132,7 +137,8 @@ begin
snk_in.valid <= in_val;
snk_in.sop <= in_sop;
snk_in.eop <= in_eop;
- snk_in.empty <= (others => '0'); -- not used
+ -- not used
+ snk_in.empty <= (others => '0');
-- Interface DUT source - TB rx
src_in.ready <= out_ready;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd b/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
index 22a401dde7a9a6baebb9b51dae8b5ac60456f4f0..54a3c26d208f236ce1c52c389c08074385446583 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
@@ -38,7 +38,8 @@ entity tb_eth_IHL_to_20 is
end tb_eth_IHL_to_20;
architecture tb of tb_eth_IHL_to_20 is
- constant clk_period : time := 5 ns; -- 100 MHz
+ -- 100 MHz
+ constant clk_period : time := 5 ns;
signal tb_end : std_logic := '0';
signal clk : std_logic := '0';
@@ -61,7 +62,8 @@ architecture tb of tb_eth_IHL_to_20 is
begin
snk_in.sop <= '1';
snk_in.valid <= '1';
- snk_in.data <= RESIZE_DP_DATA(X"0000FFFF"); -- Eth header
+ -- Eth header
+ snk_in.data <= RESIZE_DP_DATA(X"0000FFFF");
wait until rising_edge(clk);
snk_in.sop <= '0';
snk_in.data <= RESIZE_DP_DATA(X"FFFFFFFF");
@@ -70,7 +72,8 @@ architecture tb of tb_eth_IHL_to_20 is
wait until rising_edge(clk);
snk_in.data <= RESIZE_DP_DATA(X"00000800");
wait until rising_edge(clk);
- snk_in.data <= RESIZE_DP_DATA(X"4" & -- IPv4 header
+ -- IPv4 header
+ snk_in.data <= RESIZE_DP_DATA(X"4" &
TO_UVEC(IHL,c_network_ip_header_length_w) &
X"00" &
TO_UVEC((IHL + UDP_payload_len + 2) * 4,c_network_ip_total_length_w));
@@ -85,21 +88,25 @@ architecture tb of tb_eth_IHL_to_20 is
wait until rising_edge(clk);
for I in 6 to IHL loop
- snk_in.data <= RESIZE_DP_DATA(X"BAD000" & TO_UVEC(I,c_network_ip_header_length_w)); -- optionnal option word
+ -- optionnal option word
+ snk_in.data <= RESIZE_DP_DATA(X"BAD000" & TO_UVEC(I,c_network_ip_header_length_w));
wait until rising_edge(clk);
end loop;
- snk_in.data <= RESIZE_DP_DATA(X"10FA10FA"); -- UDP header
+ -- UDP header
+ snk_in.data <= RESIZE_DP_DATA(X"10FA10FA");
wait until rising_edge(clk);
snk_in.data <= RESIZE_DP_DATA(TO_UVEC((UDP_payload_len + 2) * 4,c_network_udp_total_length_w) & X"0000");
wait until rising_edge(clk);
- for I in 0 to UDP_payload_len - 1 loop -- UDP payload
+ -- UDP payload
+ for I in 0 to UDP_payload_len - 1 loop
snk_in.data <= RESIZE_DP_DATA(X"BEEF" & TO_UVEC(I,16));
wait until rising_edge(clk);
end loop;
- snk_in.data <= RESIZE_DP_DATA(X"CCCCCCCC"); -- Eth CRC
+ -- Eth CRC
+ snk_in.data <= RESIZE_DP_DATA(X"CCCCCCCC");
snk_in.eop <= '1';
wait until rising_edge(clk);
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd b/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd
index 61a076e891c390cf8dccab7f9f23c3dea846daae..b9787ec754a666ff7818363f32ac186b0b33080e 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd
@@ -66,13 +66,16 @@ use dp_lib.tb_dp_pkg.all;
entity tb_eth_ip_header_checksum is
generic (
-- general
- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always e_active, e_random or e_pulse flow control
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
+ -- always e_active, e_random or e_pulse flow control
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse;
+ -- always e_active, e_random or e_pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
g_print_en : boolean := true;
-- specific
g_data_w : natural := 64;
g_symbol_w : natural := 8;
- g_empty : natural := 6; -- number of empty symbols in header when g_symbol_w < g_data_w, must be < c_nof_symbols_per_data
+ -- number of empty symbols in header when g_symbol_w < g_data_w, must be < c_nof_symbols_per_data
+ g_empty : natural := 6;
g_pkt_len : natural := 240;
g_pkt_gap : natural := 16
);
@@ -88,7 +91,8 @@ architecture tb of tb_eth_ip_header_checksum is
-- . If g_symbol_w = g_data_w then boundary is at g_data_w, so empty is 0.
-- . If g_symbol_w < g_data_w then boundary is at last symbol, so empty is 1.
constant c_nof_symbols_per_data : natural := g_data_w / g_symbol_w;
- constant c_nof_symbols_per_bsn : natural := c_dp_stream_bsn_w / g_symbol_w; -- = 64 / g_symbol_w
+ -- = 64 / g_symbol_w
+ constant c_nof_symbols_per_bsn : natural := c_dp_stream_bsn_w / g_symbol_w;
constant c_bsn_w : natural := sel_a_b(c_nof_symbols_per_data = 1,
g_symbol_w * c_nof_symbols_per_bsn,
g_symbol_w * (c_nof_symbols_per_bsn - g_empty));
@@ -106,7 +110,8 @@ architecture tb of tb_eth_ip_header_checksum is
constant c_dsp_max : unsigned(g_data_w - 1 downto 0) := (others => '1');
constant c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := TO_DP_SOSI_UNSIGNED('0', '0', '0', '0', c_data_max, c_dsp_max, c_dsp_max, c_unsigned_0, c_unsigned_0, c_unsigned_0, c_unsigned_0);
- constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones; -- default only accept increment +1
+ -- default only accept increment +1
+ constant c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones;
constant c_expected_pkt_len : natural := g_pkt_len;
constant c_sync_period : natural := 5;
@@ -123,150 +128,281 @@ architecture tb of tb_eth_ip_header_checksum is
-- Tx offload
-----------------------------------------------------------------------------
-- From apertif_udp_offload_pkg.vhd:
- constant c_udp_offload_nof_hdr_fields : natural := 3 + 12 + 4 + 3; -- 22, 448b; 7 64b words
- constant c_udp_offload_nof_hdr_words_default : natural := 26; -- 23 single word + 3 double word = 26 32b words
+ -- 22, 448b; 7 64b words
+ constant c_udp_offload_nof_hdr_fields : natural := 3 + 12 + 4 + 3;
+ -- 23 single word + 3 double word = 26 32b words
+ constant c_udp_offload_nof_hdr_words_default : natural := 26;
constant c_udp_offload_nof_hdr_words_shortened : natural := c_udp_offload_nof_hdr_words_default - 1;
constant c_udp_offload_nof_hdr_words : natural := sel_a_b(c_use_shortened_header, c_udp_offload_nof_hdr_words_shortened, c_udp_offload_nof_hdr_words_default);
-- Notes:
-- . pre-calculated ip_header_checksum is valid only for UNB0, FN0 targeting IP 10.10.10.10
-- . udp_total_length = 176 beamlets * 64b / 8b = 1408B + 14 DP bytes + 8 UDP bytes = 1430B
- constant c_udp_offload_hdr_field_arr : t_common_field_arr(c_udp_offload_nof_hdr_fields - 1 downto 0) := ( -- index
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ), -- 21
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(x"0123456789AB") ), -- 20
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ), -- 19
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), -- 18
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ), -- 17
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ), -- 16
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ), -- 15
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ), -- 14
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ), -- 13
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ), -- 12
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ), -- 11
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ), -- 10
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ), -- 9, will be calculated by DUT
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ), -- 8
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ), -- 7
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ), -- 6
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- 5
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ), -- 4
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ), -- 3
- ( field_name_pad("dp_reserved" ), "RW", 47, field_default(x"010203040506") ), -- 2
- ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ), -- 1
- ( field_name_pad("dp_bsn" ), "RW", c_bsn_w, field_default(0) ) ); -- 0
+ -- index
+ constant c_udp_offload_hdr_field_arr : t_common_field_arr(c_udp_offload_nof_hdr_fields - 1 downto 0) := (
+ -- 21
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ),
+ -- 20
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(x"0123456789AB") ),
+ -- 19
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
+ -- 18
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
+ -- 17
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
+ -- 16
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
+ -- 15
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ),
+ -- 14
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
+ -- 13
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
+ -- 12
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ -- 11
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
+ -- 10
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
+ -- 9, will be calculated by DUT
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
+ -- 8
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ),
+ -- 7
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ),
+ -- 6
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
+ -- 5
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
+ -- 4
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ),
+ -- 3
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+ -- 2
+ ( field_name_pad("dp_reserved" ), "RW", 47, field_default(x"010203040506") ),
+ -- 1
+ ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
+ -- 0
+ ( field_name_pad("dp_bsn" ), "RW", c_bsn_w, field_default(0) ) );
-- TX: Corresponding storage of c_udp_offload_hdr_field_arr in MM register words
-- . Note: It appears that the tx_hdr_word read values are the MM write values, so read of value from logic fields (with MM override '0', e.g. dp_bsn, eth_src_mac) is not supported.
- constant c_expected_tx_hdr_word_arr_default : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_default - 1) := ( -- word address
- X"00000000", -- 0 = dp_bsn[31:0] -- readback is MM value, not the logic value
- X"00000000", -- 1 = dp_bsn[c_bsn_w-1:32]
- X"00000000", -- 2 = dp_sync
- X"03040506", -- 3 = dp_reserved[31:0]
- X"00000102", -- 4 = dp_reserved[47:32]
- X"00000000", -- 5 = udp_checksum
- X"00000596", -- 6 = udp_total_length
- X"00000000", -- 7 = udp_dst_port
- X"00000000", -- 8 = udp_src_port -- readback is MM value, not the logic value
- X"C0A80001", -- 9 = ip_dst_addr
- X"C0A80009", -- 10 = ip_src_addr
- X"00000000", -- 11 = ip_header_checksum
- X"00000011", -- 12 = ip_protocol
- X"0000007F", -- 13 = ip_time_to_live
- X"00000000", -- 14 = ip_fragment_offset
- X"00000002", -- 15 = ip_flags
- X"00000000", -- 16 = ip_identification
- X"000005AA", -- 17 = ip_total_length
- X"00000000", -- 18 = ip_services
- X"00000005", -- 19 = ip_header_length
- X"00000004", -- 20 = ip_version
- X"00000800", -- 21 = eth_type[15:0]
- X"456789AB", -- 22 = eth_src_mac[31:0] -- readback is MM value, not the logic value
- X"00000123", -- 23 = eth_src_mac[47:32]
- X"214368AC", -- 24 = eth_dst_mac[31:0]
- X"0000001B"); -- 25 = eth_dst_mac[47:32]
-
- constant c_expected_tx_hdr_word_arr_shortened : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_shortened - 1) := ( -- word address
- X"00000000", -- 0 = dp_bsn[c_bsn_w-1:0] -- readback is MM value, not the logic value
- X"00000000", -- 1 = dp_sync
- X"03040506", -- 2 = dp_reserved[31:0]
- X"00000102", -- 3 = dp_reserved[47:32]
- X"00000000", -- 4 = udp_checksum
- X"00000596", -- 5 = udp_total_length
- X"00000000", -- 6 = udp_dst_port
- X"00000000", -- 7 = udp_src_port -- readback is MM value, not the logic value
- X"C0A80001", -- 8 = ip_dst_addr
- X"C0A80009", -- 9 = ip_src_addr
- X"00000000", -- 10 = ip_header_checksum
- X"00000011", -- 11 = ip_protocol
- X"0000007F", -- 12 = ip_time_to_live
- X"00000000", -- 13 = ip_fragment_offset
- X"00000002", -- 14 = ip_flags
- X"00000000", -- 15 = ip_identification
- X"000005AA", -- 16 = ip_total_length
- X"00000000", -- 17 = ip_services
- X"00000005", -- 18 = ip_header_length
- X"00000004", -- 19 = ip_version
- X"00000800", -- 20 = eth_type[15:0]
- X"456789AB", -- 21 = eth_src_mac[31:0] -- readback is MM value, not the logic value
- X"00000123", -- 22 = eth_src_mac[47:32]
- X"214368AC", -- 23 = eth_dst_mac[31:0]
- X"0000001B"); -- 24 = eth_dst_mac[47:32]
+ -- word address
+ constant c_expected_tx_hdr_word_arr_default : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_default - 1) := (
+ -- 0 = dp_bsn[31:0] -- readback is MM value, not the logic value
+ X"00000000",
+ -- 1 = dp_bsn[c_bsn_w-1:32]
+ X"00000000",
+ -- 2 = dp_sync
+ X"00000000",
+ -- 3 = dp_reserved[31:0]
+ X"03040506",
+ -- 4 = dp_reserved[47:32]
+ X"00000102",
+ -- 5 = udp_checksum
+ X"00000000",
+ -- 6 = udp_total_length
+ X"00000596",
+ -- 7 = udp_dst_port
+ X"00000000",
+ -- 8 = udp_src_port -- readback is MM value, not the logic value
+ X"00000000",
+ -- 9 = ip_dst_addr
+ X"C0A80001",
+ -- 10 = ip_src_addr
+ X"C0A80009",
+ -- 11 = ip_header_checksum
+ X"00000000",
+ -- 12 = ip_protocol
+ X"00000011",
+ -- 13 = ip_time_to_live
+ X"0000007F",
+ -- 14 = ip_fragment_offset
+ X"00000000",
+ -- 15 = ip_flags
+ X"00000002",
+ -- 16 = ip_identification
+ X"00000000",
+ -- 17 = ip_total_length
+ X"000005AA",
+ -- 18 = ip_services
+ X"00000000",
+ -- 19 = ip_header_length
+ X"00000005",
+ -- 20 = ip_version
+ X"00000004",
+ -- 21 = eth_type[15:0]
+ X"00000800",
+ -- 22 = eth_src_mac[31:0] -- readback is MM value, not the logic value
+ X"456789AB",
+ -- 23 = eth_src_mac[47:32]
+ X"00000123",
+ -- 24 = eth_dst_mac[31:0]
+ X"214368AC",
+ -- 25 = eth_dst_mac[47:32]
+ X"0000001B");
+
+ -- word address
+ constant c_expected_tx_hdr_word_arr_shortened : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_shortened - 1) := (
+ -- 0 = dp_bsn[c_bsn_w-1:0] -- readback is MM value, not the logic value
+ X"00000000",
+ -- 1 = dp_sync
+ X"00000000",
+ -- 2 = dp_reserved[31:0]
+ X"03040506",
+ -- 3 = dp_reserved[47:32]
+ X"00000102",
+ -- 4 = udp_checksum
+ X"00000000",
+ -- 5 = udp_total_length
+ X"00000596",
+ -- 6 = udp_dst_port
+ X"00000000",
+ -- 7 = udp_src_port -- readback is MM value, not the logic value
+ X"00000000",
+ -- 8 = ip_dst_addr
+ X"C0A80001",
+ -- 9 = ip_src_addr
+ X"C0A80009",
+ -- 10 = ip_header_checksum
+ X"00000000",
+ -- 11 = ip_protocol
+ X"00000011",
+ -- 12 = ip_time_to_live
+ X"0000007F",
+ -- 13 = ip_fragment_offset
+ X"00000000",
+ -- 14 = ip_flags
+ X"00000002",
+ -- 15 = ip_identification
+ X"00000000",
+ -- 16 = ip_total_length
+ X"000005AA",
+ -- 17 = ip_services
+ X"00000000",
+ -- 18 = ip_header_length
+ X"00000005",
+ -- 19 = ip_version
+ X"00000004",
+ -- 20 = eth_type[15:0]
+ X"00000800",
+ -- 21 = eth_src_mac[31:0] -- readback is MM value, not the logic value
+ X"456789AB",
+ -- 22 = eth_src_mac[47:32]
+ X"00000123",
+ -- 23 = eth_dst_mac[31:0]
+ X"214368AC",
+ -- 24 = eth_dst_mac[47:32]
+ X"0000001B");
-- RX: Corresponding storage of c_udp_offload_hdr_field_arr in MM register words
- constant c_expected_rx_hdr_word_arr_default : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_default - 1) := ( -- word address
- X"00000002", -- 0 = dp_bsn[31:0] -- dynamic value obtained from simulation
- X"00000000", -- 1 = dp_bsn[c_bsn_w-1:32]
- X"00000001", -- 2 = dp_sync -- dynamic value obtained from simulation
- X"03040506", -- 3 = dp_reserved[31:0]
- X"00000102", -- 4 = dp_reserved[47:32]
- X"00000000", -- 5 = udp_checksum
- X"00000596", -- 6 = udp_total_length
- X"00000000", -- 7 = udp_dst_port
- X"00000000", -- 8 = udp_src_port
- X"C0A80001", -- 9 = ip_dst_addr
- X"C0A80009", -- 10 = ip_src_addr
- X"000074E8", -- 11 = ip_header_checksum
- X"00000011", -- 12 = ip_protocol
- X"0000007F", -- 13 = ip_time_to_live
- X"00000000", -- 14 = ip_fragment_offset
- X"00000002", -- 15 = ip_flags
- X"00000000", -- 16 = ip_identification
- X"000005AA", -- 17 = ip_total_length
- X"00000000", -- 18 = ip_services
- X"00000005", -- 19 = ip_header_length
- X"00000004", -- 20 = ip_version
- X"00000800", -- 21 = eth_type[15:0]
- X"86080000", -- 22 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
- X"00000022", -- 23 = eth_src_mac[47:32]
- X"214368AC", -- 24 = eth_dst_mac[31:0]
- X"0000001B"); -- 25 = eth_dst_mac[47:32]
-
- constant c_expected_rx_hdr_word_arr_shortened : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_shortened - 1) := ( -- word address
- X"00000002", -- 0 = dp_bsn[c_bsn_w-1:0] -- dynamic value obtained from simulation
- X"00000001", -- 1 = dp_sync -- dynamic value obtained from simulation
- X"03040506", -- 2 = dp_reserved[31:0]
- X"00000102", -- 3 = dp_reserved[47:32]
- X"00000000", -- 4 = udp_checksum
- X"00000596", -- 5 = udp_total_length
- X"00000000", -- 6 = udp_dst_port
- X"00000000", -- 7 = udp_src_port
- X"C0A80001", -- 8 = ip_dst_addr
- X"C0A80009", -- 9 = ip_src_addr
- X"000074E8", -- 10 = ip_header_checksum
- X"00000011", -- 11 = ip_protocol
- X"0000007F", -- 12 = ip_time_to_live
- X"00000000", -- 13 = ip_fragment_offset
- X"00000002", -- 14 = ip_flags
- X"00000000", -- 15 = ip_identification
- X"000005AA", -- 16 = ip_total_length
- X"00000000", -- 17 = ip_services
- X"00000005", -- 18 = ip_header_length
- X"00000004", -- 19 = ip_version
- X"00000800", -- 20 = eth_type[15:0]
- X"86080000", -- 21 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
- X"00000022", -- 22 = eth_src_mac[47:32]
- X"214368AC", -- 23 = eth_dst_mac[31:0]
- X"0000001B"); -- 24 = eth_dst_mac[47:32]
+ -- word address
+ constant c_expected_rx_hdr_word_arr_default : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_default - 1) := (
+ -- 0 = dp_bsn[31:0] -- dynamic value obtained from simulation
+ X"00000002",
+ -- 1 = dp_bsn[c_bsn_w-1:32]
+ X"00000000",
+ -- 2 = dp_sync -- dynamic value obtained from simulation
+ X"00000001",
+ -- 3 = dp_reserved[31:0]
+ X"03040506",
+ -- 4 = dp_reserved[47:32]
+ X"00000102",
+ -- 5 = udp_checksum
+ X"00000000",
+ -- 6 = udp_total_length
+ X"00000596",
+ -- 7 = udp_dst_port
+ X"00000000",
+ -- 8 = udp_src_port
+ X"00000000",
+ -- 9 = ip_dst_addr
+ X"C0A80001",
+ -- 10 = ip_src_addr
+ X"C0A80009",
+ -- 11 = ip_header_checksum
+ X"000074E8",
+ -- 12 = ip_protocol
+ X"00000011",
+ -- 13 = ip_time_to_live
+ X"0000007F",
+ -- 14 = ip_fragment_offset
+ X"00000000",
+ -- 15 = ip_flags
+ X"00000002",
+ -- 16 = ip_identification
+ X"00000000",
+ -- 17 = ip_total_length
+ X"000005AA",
+ -- 18 = ip_services
+ X"00000000",
+ -- 19 = ip_header_length
+ X"00000005",
+ -- 20 = ip_version
+ X"00000004",
+ -- 21 = eth_type[15:0]
+ X"00000800",
+ -- 22 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
+ X"86080000",
+ -- 23 = eth_src_mac[47:32]
+ X"00000022",
+ -- 24 = eth_dst_mac[31:0]
+ X"214368AC",
+ -- 25 = eth_dst_mac[47:32]
+ X"0000001B");
+
+ -- word address
+ constant c_expected_rx_hdr_word_arr_shortened : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_shortened - 1) := (
+ -- 0 = dp_bsn[c_bsn_w-1:0] -- dynamic value obtained from simulation
+ X"00000002",
+ -- 1 = dp_sync -- dynamic value obtained from simulation
+ X"00000001",
+ -- 2 = dp_reserved[31:0]
+ X"03040506",
+ -- 3 = dp_reserved[47:32]
+ X"00000102",
+ -- 4 = udp_checksum
+ X"00000000",
+ -- 5 = udp_total_length
+ X"00000596",
+ -- 6 = udp_dst_port
+ X"00000000",
+ -- 7 = udp_src_port
+ X"00000000",
+ -- 8 = ip_dst_addr
+ X"C0A80001",
+ -- 9 = ip_src_addr
+ X"C0A80009",
+ -- 10 = ip_header_checksum
+ X"000074E8",
+ -- 11 = ip_protocol
+ X"00000011",
+ -- 12 = ip_time_to_live
+ X"0000007F",
+ -- 13 = ip_fragment_offset
+ X"00000000",
+ -- 14 = ip_flags
+ X"00000002",
+ -- 15 = ip_identification
+ X"00000000",
+ -- 16 = ip_total_length
+ X"000005AA",
+ -- 17 = ip_services
+ X"00000000",
+ -- 18 = ip_header_length
+ X"00000005",
+ -- 19 = ip_version
+ X"00000004",
+ -- 20 = eth_type[15:0]
+ X"00000800",
+ -- 21 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
+ X"86080000",
+ -- 22 = eth_src_mac[47:32]
+ X"00000022",
+ -- 23 = eth_dst_mac[31:0]
+ X"214368AC",
+ -- 24 = eth_dst_mac[47:32]
+ X"0000001B");
-- Override ('1') only the Ethernet fields so we can use MM defaults there
constant c_hdr_field_ovr_init : std_logic_vector(c_udp_offload_nof_hdr_fields - 1 downto 0) := "101" & "111111111111" & "1111" & "100";
@@ -350,12 +486,15 @@ begin
u_dp_stream_stimuli : entity dp_lib.dp_stream_stimuli
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 15,
g_pulse_active => c_stimuli_pulse_active,
g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_stimuli,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -377,9 +516,12 @@ begin
src_out => stimuli_src_out,
-- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ -- expected verify_snk_in after end of stimuli
+ last_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ last_snk_in_evt => last_snk_in_evt,
+ -- signal end of tb as far as this dp_stream_stimuli is concerned
+ tb_end => tb_end
);
------------------------------------------------------------------------------
@@ -402,7 +544,8 @@ begin
-- . after the test
verify_last_snk_in_evt.sync <= last_snk_in_evt;
- verify_last_snk_in_evt.bsn <= last_snk_in_evt; -- thanks to using rx_hdr_fields_raw_arr for bsn field
+ -- thanks to using rx_hdr_fields_raw_arr for bsn field
+ verify_last_snk_in_evt.bsn <= last_snk_in_evt;
verify_last_snk_in_evt.data <= last_snk_in_evt;
verify_last_snk_in_evt.re <= '0';
verify_last_snk_in_evt.im <= '0';
@@ -415,12 +558,15 @@ begin
u_dp_stream_verify : entity dp_lib.dp_stream_verify
generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
+ -- only one stream so choose index 0
+ g_instance_nr => 0,
-- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ -- use different random width for stimuli and for verify to have different random sequences
+ g_random_w => 14,
g_pulse_active => c_verify_pulse_active,
g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- always active, random or pulse flow control
+ g_flow_control => g_flow_control_verify,
-- initializations
g_sync_period => c_sync_period,
g_sync_offset => c_sync_offset,
@@ -439,11 +585,14 @@ begin
snk_in => verify_snk_in,
-- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+ -- enable verify to verify that the verify_snk_in fields are incrementing
+ verify_snk_in_enable => verify_snk_in_enable,
-- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ -- expected verify_snk_in after end of stimuli
+ expected_snk_in => last_snk_in,
+ -- trigger verify to verify the last_snk_in
+ verify_expected_snk_in_evt => verify_last_snk_in_evt
);
------------------------------------------------------------------------------
@@ -464,7 +613,8 @@ begin
rst => dp_rst,
clk => dp_clk,
- snk_out => OPEN, -- stimuli_src_in
+ -- stimuli_src_in
+ snk_out => OPEN,
snk_in => stimuli_src_out,
src_in => dp_fifo_sc_src_in,
@@ -635,7 +785,8 @@ begin
proc_mem_mm_bus_rd(0, mm_clk, reg_dp_offload_rx_hdr_dat_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
v_word := reg_dp_offload_rx_hdr_dat_miso.rddata(31 downto 0);
- rx_hdr_word <= v_word; -- View word in wave window
+ -- View word in wave window
+ rx_hdr_word <= v_word;
if c_use_shortened_header then
assert v_word = INCR_UVEC(c_expected_rx_hdr_word_arr_shortened(0), 1) report "Unexpected dp_bsn from MM" severity ERROR;
else
@@ -649,7 +800,8 @@ begin
end if;
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
v_word := reg_dp_offload_rx_hdr_dat_miso.rddata(31 downto 0);
- rx_hdr_word <= v_word; -- View word in wave window
+ -- View word in wave window
+ rx_hdr_word <= v_word;
assert v_word = TO_UVEC(0, 32) report "Unexpected dp_sync from MM" severity ERROR;
wait;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd b/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd
index 4f5554d5c58725cdae4ff317350bf1af924c5860..786ec69b61db07e9d7b701aa33b9304c745fc1c6 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd
@@ -47,8 +47,10 @@ use work.tb_eth_tester_pkg.all;
entity tb_eth_stream_udp is
generic (
- g_tb_index : natural := 0; -- use to incremental delay logging from tb instances in tb_tb
- g_nof_sync : natural := 2; -- number of BG sync intervals to set c_run_time
+ -- use to incremental delay logging from tb instances in tb_tb
+ g_tb_index : natural := 0;
+ -- number of BG sync intervals to set c_run_time
+ g_nof_sync : natural := 2;
g_udp_port_match : boolean := true;
-- t_diag_block_gen_integer =
@@ -60,15 +62,19 @@ entity tb_eth_stream_udp is
-- nat: mem_low_adrs
-- nat: mem_high_adrs
-- nat: bsn_init
- g_bg_ctrl : t_diag_block_gen_integer := ('1', '1', 50, 3, 200, 0, c_diag_bg_mem_max_adr, 0) -- for first stream
+ -- for first stream
+ g_bg_ctrl : t_diag_block_gen_integer := ('1', '1', 50, 3, 200, 0, c_diag_bg_mem_max_adr, 0)
);
end tb_eth_stream_udp;
architecture tb of tb_eth_stream_udp is
- constant c_tb_str : string := "tb-" & natural'image(g_tb_index) & " : "; -- use to distinguish logging from tb instances in tb_tb
- constant mm_clk_period : time := 10 ns; -- 100 MHz
+ -- use to distinguish logging from tb instances in tb_tb
+ constant c_tb_str : string := "tb-" & natural'image(g_tb_index) & " : ";
+ -- 100 MHz
+ constant mm_clk_period : time := 10 ns;
constant c_nof_st_clk_per_s : natural := 200 * 10**6;
- constant st_clk_period : time := (10**9 / c_nof_st_clk_per_s) * 1 ns; -- 5 ns, 200 MHz
+ -- 5 ns, 200 MHz
+ constant st_clk_period : time := (10**9 / c_nof_st_clk_per_s) * 1 ns;
constant c_bg_block_len : natural := g_bg_ctrl.samples_per_packet;
constant c_bg_slot_len : natural := c_bg_block_len + g_bg_ctrl.gapsize;
@@ -100,7 +106,8 @@ architecture tb of tb_eth_stream_udp is
constant c_mon_nof_valid_rx : natural := c_mon_nof_sop_rx * c_nof_valid_per_packet;
-- Use sim default src MAC, IP, UDP port from eth_tester_pkg.vhd and based on c_gn_index
- constant c_gn_index : natural := 17; -- global node index
+ -- global node index
+ constant c_gn_index : natural := 17;
constant c_gn_eth_src_mac : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := c_eth_tester_eth_src_mac_47_16 & func_eth_tester_gn_index_to_mac_15_0(c_gn_index);
constant c_gn_ip_src_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := c_eth_tester_ip_src_addr_31_16 & func_eth_tester_gn_index_to_ip_15_0(c_gn_index);
constant c_gn_udp_src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0) := c_eth_tester_udp_src_port_15_8 & TO_UVEC(c_gn_index, 8);
@@ -194,8 +201,10 @@ begin
-- Set destination MAC/IP/UDP port in tx header
-- The MM addresses follow from byte address_offset // 4 in eth.peripheral.yaml
proc_mem_mm_bus_wr(16#7#, c_dst_udp_port, mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
- proc_mem_mm_bus_wr(16#10#, TO_SINT(c_eth_tester_ip_dst_addr), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi); -- use signed to fit 32 b in INTEGER
- proc_mem_mm_bus_wr(16#18#, TO_SINT(c_eth_tester_eth_dst_mac(31 downto 0)), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi); -- use signed to fit 32 b in INTEGER
+ -- use signed to fit 32 b in INTEGER
+ proc_mem_mm_bus_wr(16#10#, TO_SINT(c_eth_tester_ip_dst_addr), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
+ -- use signed to fit 32 b in INTEGER
+ proc_mem_mm_bus_wr(16#18#, TO_SINT(c_eth_tester_eth_dst_mac(31 downto 0)), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
proc_mem_mm_bus_wr(16#19#, TO_UINT(c_eth_tester_eth_dst_mac(47 downto 32)), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
---------------------------------------------------------------------------
@@ -207,8 +216,10 @@ begin
proc_mem_mm_bus_wr(3, g_bg_ctrl.gapsize, mm_clk, reg_bg_ctrl_copi);
proc_mem_mm_bus_wr(4, g_bg_ctrl.mem_low_adrs, mm_clk, reg_bg_ctrl_copi);
proc_mem_mm_bus_wr(5, g_bg_ctrl.mem_high_adrs, mm_clk, reg_bg_ctrl_copi);
- proc_mem_mm_bus_wr(6, g_bg_ctrl.bsn_init, mm_clk, reg_bg_ctrl_copi); -- low part
- proc_mem_mm_bus_wr(7, 0, mm_clk, reg_bg_ctrl_copi); -- high part
+ -- low part
+ proc_mem_mm_bus_wr(6, g_bg_ctrl.bsn_init, mm_clk, reg_bg_ctrl_copi);
+ -- high part
+ proc_mem_mm_bus_wr(7, 0, mm_clk, reg_bg_ctrl_copi);
-- Enable the BG at st_pps pulse.
proc_mem_mm_bus_wr(0, 3, mm_clk, reg_bg_ctrl_copi);
proc_common_wait_some_cycles(mm_clk, 10);
@@ -232,7 +243,8 @@ begin
proc_common_wait_some_cycles(st_clk, g_tb_index * 100);
-- Print logging
- print_str(""); -- log empty line between tb results
+ -- log empty line between tb results
+ print_str("");
print_str(c_tb_str &
"ETH bit rate :" &
" c_bg_nof_bps = " & real'image(c_bg_nof_bps) & " bps");
@@ -357,7 +369,8 @@ begin
generic map (
g_nof_streams => 1,
g_bg_sync_timeout => c_eth_tester_sync_timeout,
- g_remove_crc => false -- no CRC with streaming loopback
+ -- no CRC with streaming loopback
+ g_remove_crc => false
)
port map (
-- Clocks and reset
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
index 96ef9afd24438b4c80ca128d7ecca136a433d12f..d627df5bc324df0baeb3b6b47959741a11b296f1 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
@@ -56,12 +56,18 @@ use tech_tse_lib.tb_tech_tse_pkg.all;
entity tb_eth_tester is
generic (
- g_tb_index : natural := 0; -- use to incremental delay logging from tb instances in tb_tb
- g_nof_sync : natural := 2; -- number of BG sync intervals to set c_run_time
- g_nof_streams : natural := 1; -- <= c_eth_nof_udp_ports = 4 when g_loopback_tx_rx = 1
- g_loopback_eth : boolean := true; -- FALSE = sosi loopback, TRUE = eth loopback (using sim_tse or tech_tse)
- g_eth_sim_level : natural := 1; -- when g_loopback_eth = TRUE, then 0 = use tech_tse IP; 1 = use fast sim_tse model
- g_corrupted_en : boolean := false; -- when TRUE cause a corrupted Rx packet, when tech_tse is used
+ -- use to incremental delay logging from tb instances in tb_tb
+ g_tb_index : natural := 0;
+ -- number of BG sync intervals to set c_run_time
+ g_nof_sync : natural := 2;
+ -- <= c_eth_nof_udp_ports = 4 when g_loopback_tx_rx = 1
+ g_nof_streams : natural := 1;
+ -- FALSE = sosi loopback, TRUE = eth loopback (using sim_tse or tech_tse)
+ g_loopback_eth : boolean := true;
+ -- when g_loopback_eth = TRUE, then 0 = use tech_tse IP; 1 = use fast sim_tse model
+ g_eth_sim_level : natural := 1;
+ -- when TRUE cause a corrupted Rx packet, when tech_tse is used
+ g_corrupted_en : boolean := false;
-- t_diag_block_gen_integer =
-- sl: enable
@@ -74,8 +80,10 @@ entity tb_eth_tester is
-- nat: bsn_init
--g_bg_ctrl_first : t_diag_block_gen_integer := ('1', '1', 50, 3, 100, 0, c_diag_bg_mem_max_adr, 0); -- for first stream
--g_bg_ctrl_others : t_diag_block_gen_integer := ('1', '1', 30, 3, 10, 0, c_diag_bg_mem_max_adr, 0) -- for other streams
- g_bg_ctrl_first : t_diag_block_gen_integer := ('1', '1', 50, 3, 200, 0, c_diag_bg_mem_max_adr, 0); -- for first stream
- g_bg_ctrl_others : t_diag_block_gen_integer := ('1', '1', 30, 3, 10, 0, c_diag_bg_mem_max_adr, 0) -- for other streams
+ -- for first stream
+ g_bg_ctrl_first : t_diag_block_gen_integer := ('1', '1', 50, 3, 200, 0, c_diag_bg_mem_max_adr, 0);
+ -- for other streams
+ g_bg_ctrl_others : t_diag_block_gen_integer := ('1', '1', 30, 3, 10, 0, c_diag_bg_mem_max_adr, 0)
);
port (
tb_end : out std_logic
@@ -83,11 +91,15 @@ entity tb_eth_tester is
end tb_eth_tester;
architecture tb of tb_eth_tester is
- constant c_tb_str : string := "tb-" & natural'image(g_tb_index) & " : "; -- use to distinguish logging from tb instances in tb_tb
- constant eth_clk_period : time := 8 ns; -- 125 MHz
- constant mm_clk_period : time := 10 ns; -- 100 MHz
+ -- use to distinguish logging from tb instances in tb_tb
+ constant c_tb_str : string := "tb-" & natural'image(g_tb_index) & " : ";
+ -- 125 MHz
+ constant eth_clk_period : time := 8 ns;
+ -- 100 MHz
+ constant mm_clk_period : time := 10 ns;
constant c_nof_st_clk_per_s : natural := 200 * 10**6;
- constant st_clk_period : time := (10**9 / c_nof_st_clk_per_s) * 1 ns; -- 5 ns, 200 MHz
+ -- 5 ns, 200 MHz
+ constant st_clk_period : time := (10**9 / c_nof_st_clk_per_s) * 1 ns;
constant c_bg_block_len_first : natural := g_bg_ctrl_first.samples_per_packet;
constant c_bg_block_len_others : natural := g_bg_ctrl_others.samples_per_packet;
@@ -137,7 +149,8 @@ architecture tb of tb_eth_tester is
constant c_mon_nof_valid_others_rx : natural := c_mon_nof_sop_others * c_nof_valid_per_packet_others;
-- Use sim default src MAC, IP, UDP port from eth_tester_pkg.vhd and based on c_gn_index
- constant c_gn_index : natural := 17; -- global node index
+ -- global node index
+ constant c_gn_index : natural := 17;
constant c_gn_eth_src_mac : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := c_eth_tester_eth_src_mac_47_16 & func_eth_tester_gn_index_to_mac_15_0(c_gn_index);
constant c_gn_ip_src_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := c_eth_tester_ip_src_addr_31_16 & func_eth_tester_gn_index_to_ip_15_0(c_gn_index);
constant c_gn_udp_src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0) := c_eth_tester_udp_src_port_15_8 & TO_UVEC(c_gn_index, 8);
@@ -185,7 +198,8 @@ architecture tb of tb_eth_tester is
-- . reg_strobe_total_count
signal tx_total_count_nof_packet_arr : t_natural_arr(g_nof_streams - 1 downto 0);
signal rx_total_count_nof_packet_arr : t_natural_arr(g_nof_streams - 1 downto 0);
- signal exp_total_count_nof_packet_arr : t_natural_arr(g_nof_streams - 1 downto 0); -- same for both tx and rx
+ -- same for both tx and rx
+ signal exp_total_count_nof_packet_arr : t_natural_arr(g_nof_streams - 1 downto 0);
signal rx_total_count_nof_valid_arr : t_natural_arr(g_nof_streams - 1 downto 0);
signal rx_exp_total_count_nof_valid_arr : t_natural_arr(g_nof_streams - 1 downto 0);
@@ -202,10 +216,12 @@ architecture tb of tb_eth_tester is
signal rx_mon_latency_arr : t_natural_arr(g_nof_streams - 1 downto 0);
-- ETH link, used when g_loopback_eth = TRUE
- signal eth_tx_udp_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_sosi_rst); -- default rst if not used
+ -- default rst if not used
+ signal eth_tx_udp_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_sosi_rst);
signal eth_tx_udp_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0);
signal eth_rx_udp_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0);
- signal eth_rx_udp_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_siso_rst); -- default rst if not used
+ -- default rst if not used
+ signal eth_rx_udp_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_siso_rst);
signal reg_eth_copi : t_mem_copi := c_mem_copi_rst;
signal reg_eth_cipo : t_mem_cipo;
@@ -250,7 +266,8 @@ begin
rx_exp_total_count_nof_valid_arr <= (others => c_nof_sync_others * c_total_count_nof_valid_per_sync_others);
rx_exp_total_count_nof_valid_arr(0) <= c_nof_sync_first * c_total_count_nof_valid_per_sync_first;
- rx_exp_total_count_nof_corrupted_arr <= (others => 0); -- default no Rx errors
+ -- default no Rx errors
+ rx_exp_total_count_nof_corrupted_arr <= (others => 0);
if g_corrupted_en = true then
rx_exp_total_count_nof_corrupted_arr(0) <= 1;
end if;
@@ -280,9 +297,11 @@ begin
if g_loopback_eth = true then
-- Set up demux in eth Rx based on destination UDP port
- v_value := 2**16 + v_udp_dst_port; -- enable bit 16, udp port number [15:0]
+ -- enable bit 16, udp port number [15:0]
+ v_value := 2**16 + v_udp_dst_port;
for I in g_nof_streams - 1 downto 0 loop
- proc_mem_mm_bus_wr(0 + I, v_value + I, mm_clk, reg_eth_copi); -- increment udp_dst_port per stream
+ -- increment udp_dst_port per stream
+ proc_mem_mm_bus_wr(0 + I, v_value + I, mm_clk, reg_eth_copi);
end loop;
end if;
@@ -291,8 +310,10 @@ begin
-- Set destination MAC/IP/UDP port in tx header, increment udp_dst_port per stream
-- The MM addresses follow from byte address_offset // 4 in eth.peripheral.yaml
proc_mem_mm_bus_wr(v_offset + 16#7#, v_udp_dst_port + I, mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
- proc_mem_mm_bus_wr(v_offset + 16#10#, TO_SINT(c_eth_tester_ip_dst_addr), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi); -- use signed to fit 32 b in INTEGER
- proc_mem_mm_bus_wr(v_offset + 16#18#, TO_SINT(c_eth_tester_eth_dst_mac(31 downto 0)), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi); -- use signed to fit 32 b in INTEGER
+ -- use signed to fit 32 b in INTEGER
+ proc_mem_mm_bus_wr(v_offset + 16#10#, TO_SINT(c_eth_tester_ip_dst_addr), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
+ -- use signed to fit 32 b in INTEGER
+ proc_mem_mm_bus_wr(v_offset + 16#18#, TO_SINT(c_eth_tester_eth_dst_mac(31 downto 0)), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
proc_mem_mm_bus_wr(v_offset + 16#19#, TO_UINT(c_eth_tester_eth_dst_mac(47 downto 32)), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
end loop;
@@ -307,8 +328,10 @@ begin
proc_mem_mm_bus_wr(v_offset + 3, bg_ctrl_arr(I).gapsize, mm_clk, reg_bg_ctrl_copi);
proc_mem_mm_bus_wr(v_offset + 4, bg_ctrl_arr(I).mem_low_adrs, mm_clk, reg_bg_ctrl_copi);
proc_mem_mm_bus_wr(v_offset + 5, bg_ctrl_arr(I).mem_high_adrs, mm_clk, reg_bg_ctrl_copi);
- proc_mem_mm_bus_wr(v_offset + 6, bg_ctrl_arr(I).bsn_init, mm_clk, reg_bg_ctrl_copi); -- low part
- proc_mem_mm_bus_wr(v_offset + 7, 0, mm_clk, reg_bg_ctrl_copi); -- high part
+ -- low part
+ proc_mem_mm_bus_wr(v_offset + 6, bg_ctrl_arr(I).bsn_init, mm_clk, reg_bg_ctrl_copi);
+ -- high part
+ proc_mem_mm_bus_wr(v_offset + 7, 0, mm_clk, reg_bg_ctrl_copi);
-- Enable the BG at st_pps pulse.
proc_mem_mm_bus_wr(v_offset + 0, 3, mm_clk, reg_bg_ctrl_copi);
end loop;
@@ -337,7 +360,8 @@ begin
proc_common_wait_some_cycles(st_clk, g_tb_index * 100);
-- Print logging
- print_str(""); -- log empty line between tb results
+ -- log empty line between tb results
+ print_str("");
for I in g_nof_streams - 1 downto 0 loop
if I = 0 then
print_str(c_tb_str &
@@ -537,7 +561,8 @@ begin
generic map (
g_nof_streams => g_nof_streams,
g_bg_sync_timeout => c_eth_tester_sync_timeout,
- g_remove_crc => g_loopback_eth -- remove CRC inserted by TSE (sim or tech)
+ -- remove CRC inserted by TSE (sim or tech)
+ g_remove_crc => g_loopback_eth
)
port map (
-- Clocks and reset
@@ -603,7 +628,8 @@ begin
use_tech_tse : if g_eth_sim_level = 0 generate
p_eth_link : process(eth_txp)
begin
- eth_rxp <= transport eth_txp after 12 ns; -- apply cable delay
+ -- apply cable delay
+ eth_rxp <= transport eth_txp after 12 ns;
eth_corrupt <= '0';
-- Optionally force eth_rxp low to cause a CRC error
@@ -656,7 +682,8 @@ begin
-- Clocks and reset
mm_rst => mm_rst,
mm_clk => mm_clk,
- eth_clk => eth_clk, -- ethernet phy reference clock
+ -- ethernet phy reference clock
+ eth_clk => eth_clk,
st_rst => st_rst,
st_clk => st_clk,
@@ -668,12 +695,16 @@ begin
udp_rx_src_out_arr => eth_rx_udp_sosi_arr,
-- Memory Mapped Slaves
- tse_sla_in => tse_copi, -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ tse_sla_in => tse_copi,
tse_sla_out => tse_cipo,
- reg_sla_in => reg_eth_copi, -- ETH control and status registers
+ -- ETH control and status registers
+ reg_sla_in => reg_eth_copi,
reg_sla_out => reg_eth_cipo,
- reg_sla_interrupt => OPEN, -- Interrupt
- ram_sla_in => c_mem_copi_rst, -- ETH rx frame and tx frame memory
+ -- Interrupt
+ reg_sla_interrupt => OPEN,
+ -- ETH rx frame and tx frame memory
+ ram_sla_in => c_mem_copi_rst,
ram_sla_out => OPEN,
-- PHY interface
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd
index ad83dbe15cc888c3e90ef2a0b07a9270c368fb6e..135442e24848e3e55945cb422322cb5b03d310f6 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd
@@ -53,10 +53,13 @@ use tech_tse_lib.tb_tech_tse_pkg.all;
entity tb_eth_tester_high_bw is
generic (
- g_tb_index : natural := 0; -- use to incremental delay logging from tb instances in tb_tb
- g_nof_sync : natural := 2; -- number of BG sync intervals to set c_run_time
+ -- use to incremental delay logging from tb instances in tb_tb
+ g_tb_index : natural := 0;
+ -- number of BG sync intervals to set c_run_time
+ g_nof_sync : natural := 2;
g_nof_streams : natural := 1;
- g_nof_octet_output : natural := 96; -- maximum = 96 bytes as max dp.data field = 768 bits.
+ -- maximum = 96 bytes as max dp.data field = 768 bits.
+ g_nof_octet_output : natural := 96;
g_nof_octet_generate : natural := 96;
-- t_diag_block_gen_integer =
@@ -68,8 +71,10 @@ entity tb_eth_tester_high_bw is
-- nat: mem_low_adrs
-- nat: mem_high_adrs
-- nat: bsn_init
- g_bg_ctrl_first : t_diag_block_gen_integer := ('1', '1', 500, 3, 200, 0, c_diag_bg_mem_max_adr, 0); -- for first stream
- g_bg_ctrl_others : t_diag_block_gen_integer := ('1', '1', 300, 3, 10, 0, c_diag_bg_mem_max_adr, 0) -- for other streams
+ -- for first stream
+ g_bg_ctrl_first : t_diag_block_gen_integer := ('1', '1', 500, 3, 200, 0, c_diag_bg_mem_max_adr, 0);
+ -- for other streams
+ g_bg_ctrl_others : t_diag_block_gen_integer := ('1', '1', 300, 3, 10, 0, c_diag_bg_mem_max_adr, 0)
);
port (
tb_end : out std_logic
@@ -77,10 +82,13 @@ entity tb_eth_tester_high_bw is
end tb_eth_tester_high_bw;
architecture tb of tb_eth_tester_high_bw is
- constant c_tb_str : string := "tb-" & natural'image(g_tb_index) & " : "; -- use to distinguish logging from tb instances in tb_tb
- constant mm_clk_period : time := 10 ns; -- 100 MHz
+ -- use to distinguish logging from tb instances in tb_tb
+ constant c_tb_str : string := "tb-" & natural'image(g_tb_index) & " : ";
+ -- 100 MHz
+ constant mm_clk_period : time := 10 ns;
constant c_nof_st_clk_per_s : natural := 200 * 10**6;
- constant st_clk_period : time := (10**9 / c_nof_st_clk_per_s) * 1 ns; -- 5 ns, 200 MHz
+ -- 5 ns, 200 MHz
+ constant st_clk_period : time := (10**9 / c_nof_st_clk_per_s) * 1 ns;
constant c_bg_block_len_first : natural := ceil_div(g_bg_ctrl_first.samples_per_packet, g_nof_octet_generate);
constant c_bg_block_len_others : natural := ceil_div(g_bg_ctrl_others.samples_per_packet, g_nof_octet_generate);
@@ -128,7 +136,8 @@ architecture tb of tb_eth_tester_high_bw is
constant c_mon_nof_valid_others_rx : natural := c_mon_nof_sop_others * c_nof_valid_per_packet_others;
-- Use sim default src MAC, IP, UDP port from eth_tester_pkg.vhd and based on c_gn_index
- constant c_gn_index : natural := 17; -- global node index
+ -- global node index
+ constant c_gn_index : natural := 17;
constant c_gn_eth_src_mac : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := c_eth_tester_eth_src_mac_47_16 & func_eth_tester_gn_index_to_mac_15_0(c_gn_index);
constant c_gn_ip_src_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := c_eth_tester_ip_src_addr_31_16 & func_eth_tester_gn_index_to_ip_15_0(c_gn_index);
constant c_gn_udp_src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0) := c_eth_tester_udp_src_port_15_8 & TO_UVEC(c_gn_index, 8);
@@ -173,7 +182,8 @@ architecture tb of tb_eth_tester_high_bw is
-- . reg_strobe_total_count
signal tx_total_count_nof_packet_arr : t_natural_arr(g_nof_streams - 1 downto 0);
signal rx_total_count_nof_packet_arr : t_natural_arr(g_nof_streams - 1 downto 0);
- signal exp_total_count_nof_packet_arr : t_natural_arr(g_nof_streams - 1 downto 0); -- same for both tx and rx
+ -- same for both tx and rx
+ signal exp_total_count_nof_packet_arr : t_natural_arr(g_nof_streams - 1 downto 0);
signal rx_total_count_nof_valid_arr : t_natural_arr(g_nof_streams - 1 downto 0);
signal rx_exp_total_count_nof_valid_arr : t_natural_arr(g_nof_streams - 1 downto 0);
@@ -222,7 +232,8 @@ begin
rx_exp_total_count_nof_valid_arr <= (others => c_nof_sync_others * c_total_count_nof_valid_per_sync_others);
rx_exp_total_count_nof_valid_arr(0) <= c_nof_sync_first * c_total_count_nof_valid_per_sync_first;
- rx_exp_total_count_nof_corrupted_arr <= (others => 0); -- default no Rx errors
+ -- default no Rx errors
+ rx_exp_total_count_nof_corrupted_arr <= (others => 0);
wait;
end process;
@@ -249,8 +260,10 @@ begin
-- Set destination MAC/IP/UDP port in tx header, increment udp_dst_port per stream
-- The MM addresses follow from byte address_offset // 4 in eth.peripheral.yaml
proc_mem_mm_bus_wr(v_offset + 16#7#, v_udp_dst_port + I, mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
- proc_mem_mm_bus_wr(v_offset + 16#10#, TO_SINT(c_eth_tester_ip_dst_addr), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi); -- use signed to fit 32 b in INTEGER
- proc_mem_mm_bus_wr(v_offset + 16#18#, TO_SINT(c_eth_tester_eth_dst_mac(31 downto 0)), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi); -- use signed to fit 32 b in INTEGER
+ -- use signed to fit 32 b in INTEGER
+ proc_mem_mm_bus_wr(v_offset + 16#10#, TO_SINT(c_eth_tester_ip_dst_addr), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
+ -- use signed to fit 32 b in INTEGER
+ proc_mem_mm_bus_wr(v_offset + 16#18#, TO_SINT(c_eth_tester_eth_dst_mac(31 downto 0)), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
proc_mem_mm_bus_wr(v_offset + 16#19#, TO_UINT(c_eth_tester_eth_dst_mac(47 downto 32)), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
end loop;
@@ -268,8 +281,10 @@ begin
proc_mem_mm_bus_wr(v_offset + 3, bg_ctrl_arr(I).gapsize, mm_clk, reg_bg_ctrl_copi);
proc_mem_mm_bus_wr(v_offset + 4, bg_ctrl_arr(I).mem_low_adrs, mm_clk, reg_bg_ctrl_copi);
proc_mem_mm_bus_wr(v_offset + 5, bg_ctrl_arr(I).mem_high_adrs, mm_clk, reg_bg_ctrl_copi);
- proc_mem_mm_bus_wr(v_offset + 6, bg_ctrl_arr(I).bsn_init, mm_clk, reg_bg_ctrl_copi); -- low part
- proc_mem_mm_bus_wr(v_offset + 7, 0, mm_clk, reg_bg_ctrl_copi); -- high part
+ -- low part
+ proc_mem_mm_bus_wr(v_offset + 6, bg_ctrl_arr(I).bsn_init, mm_clk, reg_bg_ctrl_copi);
+ -- high part
+ proc_mem_mm_bus_wr(v_offset + 7, 0, mm_clk, reg_bg_ctrl_copi);
-- Enable the BG at st_pps pulse.
proc_mem_mm_bus_wr(v_offset + 0, 3, mm_clk, reg_bg_ctrl_copi);
end loop;
@@ -298,7 +313,8 @@ begin
proc_common_wait_some_cycles(st_clk, g_tb_index * 100);
-- Print logging
- print_str(""); -- log empty line between tb results
+ -- log empty line between tb results
+ print_str("");
for I in g_nof_streams - 1 downto 0 loop
if I = 0 then
print_str(c_tb_str &
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
index b5075a71f6009c929843d7f520d8e3e41f1d0abf..9705b175d5de64b2868fd4160cb278bf827a4237 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
@@ -34,8 +34,10 @@ use common_lib.common_network_layers_pkg.all;
use work.eth_tester_pkg.all;
package tb_eth_tester_pkg is
- constant c_eth_tester_eth_dst_mac : std_logic_vector(47 downto 0) := x"001B217176B9"; -- 001B217176B9 = DOP36-enp2s0
- constant c_eth_tester_ip_dst_addr : std_logic_vector(31 downto 0) := x"0A6300FE"; -- 0A6300FE = '10.99.0.254' = DOP36-enp2s0
+ -- 001B217176B9 = DOP36-enp2s0
+ constant c_eth_tester_eth_dst_mac : std_logic_vector(47 downto 0) := x"001B217176B9";
+ -- 0A6300FE = '10.99.0.254' = DOP36-enp2s0
+ constant c_eth_tester_ip_dst_addr : std_logic_vector(31 downto 0) := x"0A6300FE";
constant c_eth_tester_udp_dst_port : std_logic_vector(15 downto 0) := c_eth_tester_udp_port;
-- Ethernet packet length in octets inclduing eth header and CRC
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd b/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
index 14ea6f5af14c79e8bfce4a7af8df7af9d0d532e9..382ec4ef681dcb35fe7f4a316637b1863b5bbdb5 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
@@ -57,7 +57,8 @@ architecture tb of tb_eth_udp_offload is
constant c_nof_repeat : natural := 10;
constant c_bsn_w : natural := 16;
constant c_symbol_init : natural := 0;
- constant c_symbol_mod : integer := 2**g_symbol_w; -- used to avoid TO_UVEC warning for smaller g_symbol_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ -- used to avoid TO_UVEC warning for smaller g_symbol_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ constant c_symbol_mod : integer := 2**g_symbol_w;
constant c_err_init : natural := 0;
constant c_sync_period : natural := 7;
constant c_sync_offset : natural := 2;
@@ -65,30 +66,37 @@ architecture tb of tb_eth_udp_offload is
-- clock and reset
constant c_mm_clk_period : time := 20 ns;
constant c_st_clk_period : time := 5 ns;
- constant c_eth_clk_period : time := 8 ns; -- 125 MHz
+ -- 125 MHz
+ constant c_eth_clk_period : time := 8 ns;
-- ETH CONSTANTS
-- ===========================================================================================================================================================
-- Payload user data
- constant c_tb_nof_data : natural := 1440; -- nof UDP user data, nof ping padding data. NOTE: non-multiples of g_data_w/g_symbol_w not supported as dp_packet_enc/dec do not support encoding/decoding empty
- constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data; -- nof IP data,
+ -- nof UDP user data, nof ping padding data. NOTE: non-multiples of g_data_w/g_symbol_w not supported as dp_packet_enc/dec do not support encoding/decoding empty
+ constant c_tb_nof_data : natural := 1440;
+ -- nof IP data,
+ constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data;
-- Headers
-- . Ethernet header
constant c_lcu_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"10FA01020300";
- constant c_dut_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ -- = 12-34-56-78-9A-BC
+ constant c_dut_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"123456789ABC";
constant c_dut_src_mac_hi : natural := TO_UINT(c_dut_src_mac(c_network_eth_mac_addr_w - 1 downto c_word_w));
constant c_dut_src_mac_lo : natural := TO_UINT(c_dut_src_mac( c_word_w - 1 downto 0));
constant c_tx_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
src_mac => c_lcu_src_mac,
- eth_type => TO_UVEC(c_network_eth_type_ip, c_network_eth_type_w)); -- TO_UVEC(c_dut_ethertype, c_network_eth_type_w));
+ -- TO_UVEC(c_dut_ethertype, c_network_eth_type_w));
+ eth_type => TO_UVEC(c_network_eth_type_ip, c_network_eth_type_w));
-- . IP header
- constant c_lcu_ip_addr : natural := 16#05060708#; -- = 05:06:07:08
+ -- = 05:06:07:08
+ constant c_lcu_ip_addr : natural := 16#05060708#;
constant c_dut_ip_addr : natural := 16#01020304#;
constant c_tb_ip_total_length : natural := c_network_ip_total_length + c_tb_ip_nof_data;
- constant c_tb_ip_protocol : natural := c_network_ip_protocol_udp; -- sel_a_b(g_data_type-c_tb_tech_tse_data_type_ping, c_network_ip_protocol_udp, c_network_ip_protocol_icmp); -- support only ping protocol or UDP protocol over IP
+ -- sel_a_b(g_data_type-c_tb_tech_tse_data_type_ping, c_network_ip_protocol_udp, c_network_ip_protocol_icmp); -- support only ping protocol or UDP protocol over IP
+ constant c_tb_ip_protocol : natural := c_network_ip_protocol_udp;
constant c_tx_ip_header : t_network_ip_header := (version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
@@ -99,23 +107,33 @@ architecture tb of tb_eth_udp_offload is
fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
- header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
+ -- init value (or try 0xEBBD = 60349)
+ header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w),
src_ip_addr => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
dst_ip_addr => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w));
-- . UDP header
- constant c_dut_udp_port_ctrl : natural := 11; -- ETH demux UDP for control
- constant c_dut_udp_port_st0 : natural := 57; -- ETH demux UDP port 0
- constant c_dut_udp_port_st1 : natural := 58; -- ETH demux UDP port 1
- constant c_dut_udp_port_st2 : natural := 59; -- ETH demux UDP port 2
- constant c_dut_udp_port_en : natural := 16#10000#; -- ETH demux UDP port enable bit 16
- constant c_lcu_udp_port : natural := 10; -- UDP port used for src_port
- constant c_dut_udp_port_st : natural := c_dut_udp_port_st0; -- UDP port used for dst_port
+ -- ETH demux UDP for control
+ constant c_dut_udp_port_ctrl : natural := 11;
+ -- ETH demux UDP port 0
+ constant c_dut_udp_port_st0 : natural := 57;
+ -- ETH demux UDP port 1
+ constant c_dut_udp_port_st1 : natural := 58;
+ -- ETH demux UDP port 2
+ constant c_dut_udp_port_st2 : natural := 59;
+ -- ETH demux UDP port enable bit 16
+ constant c_dut_udp_port_en : natural := 16#10000#;
+ -- UDP port used for src_port
+ constant c_lcu_udp_port : natural := 10;
+ -- UDP port used for dst_port
+ constant c_dut_udp_port_st : natural := c_dut_udp_port_st0;
constant c_tb_udp_total_length : natural := c_network_udp_total_length + c_tb_nof_data;
constant c_tx_udp_header : t_network_udp_header := (src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
- dst_port => TO_UVEC(c_dut_udp_port_st, c_network_udp_port_w), -- or use c_dut_udp_port_ctrl
+ -- or use c_dut_udp_port_ctrl
+ dst_port => TO_UVEC(c_dut_udp_port_st, c_network_udp_port_w),
total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
- checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
+ -- init value
+ checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w));
constant c_word_align : std_logic_vector(c_network_total_header_32b_align_w - 1 downto 0) := (others => '0');
constant c_total_hdr_slv : std_logic_vector(c_network_total_header_32b_nof_words * c_word_w - 1 downto 0) := c_word_align &
@@ -143,7 +161,8 @@ architecture tb of tb_eth_udp_offload is
-- TSE constants
constant c_promis_en : boolean := false;
- constant c_tx_ready_latency : natural := c_tech_tse_tx_ready_latency; -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
+ -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
+ constant c_tx_ready_latency : natural := c_tech_tse_tx_ready_latency;
-- ETH control
constant c_dut_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
@@ -155,7 +174,8 @@ architecture tb of tb_eth_udp_offload is
signal tb_ip_hdr : t_network_ip_header := c_tx_ip_header;
signal tb_udp_hdr : t_network_udp_header := c_tx_udp_header;
- signal eth_clk : std_logic := '0'; -- tse reference clock
+ -- tse reference clock
+ signal eth_clk : std_logic := '0';
signal mm_clk : std_logic := '0';
signal mm_rst : std_logic;
signal st_rst : std_logic;
@@ -163,8 +183,10 @@ architecture tb of tb_eth_udp_offload is
signal tb_end : std_logic := '0';
- signal random_0 : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal random_1 : std_logic_vector(15 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ -- use different lengths to have different random sequences
+ signal random_0 : std_logic_vector(14 downto 0) := (others => '0');
+ -- use different lengths to have different random sequences
+ signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_0 : std_logic;
signal pulse_1 : std_logic;
signal pulse_en : std_logic := '1';
@@ -226,7 +248,8 @@ begin
st_clk <= (not st_clk) or tb_end after c_st_clk_period / 2;
st_rst <= '1', '0' after c_st_clk_period * 7;
- eth_clk <= not eth_clk or tb_end after c_eth_clk_period / 2; -- TSE reference clock
+ -- TSE reference clock
+ eth_clk <= not eth_clk or tb_end after c_eth_clk_period / 2;
random_0 <= func_common_random(random_0) when rising_edge(st_clk);
random_1 <= func_common_random(random_1) when rising_edge(st_clk);
@@ -291,16 +314,22 @@ begin
proc_common_wait_some_cycles(mm_clk, 5);
-- Set up the UDP demux
- proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 0, c_dut_udp_port_en + c_dut_udp_port_st0, mm_clk, eth_reg_miso, eth_reg_mosi); -- UDP port stream 0
+ -- UDP port stream 0
+ proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 0, c_dut_udp_port_en + c_dut_udp_port_st0, mm_clk, eth_reg_miso, eth_reg_mosi);
proc_common_wait_some_cycles(mm_clk, 5);
-- Setup the RX config
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 0, c_dut_src_mac_lo, mm_clk, eth_reg_miso, eth_reg_mosi); -- control MAC address lo word
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 1, c_dut_src_mac_hi, mm_clk, eth_reg_miso, eth_reg_mosi); -- control MAC address hi halfword
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 2, c_dut_ip_addr, mm_clk, eth_reg_miso, eth_reg_mosi); -- control IP address
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 3, c_dut_udp_port_ctrl, mm_clk, eth_reg_miso, eth_reg_mosi); -- control UDP port
+ -- control MAC address lo word
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 0, c_dut_src_mac_lo, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- control MAC address hi halfword
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 1, c_dut_src_mac_hi, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- control IP address
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 2, c_dut_ip_addr, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- control UDP port
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 3, c_dut_udp_port_ctrl, mm_clk, eth_reg_miso, eth_reg_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_dut_control_rx_en, mm_clk, eth_reg_miso, eth_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_dut_control_rx_en, mm_clk, eth_reg_miso, eth_reg_mosi);
dut_eth_init <= '0';
-- MM Stimuli: write HEADER to RAM
@@ -323,7 +352,8 @@ begin
proc_common_wait_some_cycles(st_clk, 50);
for R in 0 to c_nof_repeat - 1 loop
- v_sync := sel_a_b(R mod c_sync_period = c_sync_offset, '1', '0'); -- v_bsn = R
+ -- v_bsn = R
+ v_sync := sel_a_b(R mod c_sync_period = c_sync_offset, '1', '0');
proc_dp_gen_block_data(c_rl, true, g_data_w, g_symbol_w, v_symbol, 0, 0, c_tb_nof_data, v_channel, v_err, v_sync, TO_DP_BSN(R), st_clk, in_en, udp_tx_siso, udp_tx_sosi);
v_bsn := INCR_UVEC(v_bsn, 1);
v_symbol := (v_symbol + c_tb_nof_data) mod c_symbol_mod;
@@ -332,7 +362,8 @@ begin
end loop;
-- End of stimuli
- proc_common_wait_some_cycles(st_clk, 50); -- depends on stream control
+ -- depends on stream control
+ proc_common_wait_some_cycles(st_clk, 50);
verify_done <= '1';
proc_common_wait_some_cycles(st_clk, 1);
verify_done <= '0';
@@ -367,11 +398,14 @@ begin
-- DATA VERIFICATION
------------------------------------------------------------------------------
- verify_en <= '1' when rising_edge(st_clk) and udp_rx_sosi.sop = '1'; -- verify enable after first output sop
+ -- verify enable after first output sop
+ verify_en <= '1' when rising_edge(st_clk) and udp_rx_sosi.sop = '1';
-- SOSI control
- proc_dp_verify_valid(c_rl, st_clk, verify_en, udp_rx_siso.ready, prev_udp_rx_ready, udp_rx_sosi.valid); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_gap_invalid(st_clk, udp_rx_sosi.valid, udp_rx_sosi.sop, udp_rx_sosi.eop, out_gap); -- Verify that the output valid is low between blocks from eop to sop
+ -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_valid(c_rl, st_clk, verify_en, udp_rx_siso.ready, prev_udp_rx_ready, udp_rx_sosi.valid);
+ -- Verify that the output valid is low between blocks from eop to sop
+ proc_dp_verify_gap_invalid(st_clk, udp_rx_sosi.valid, udp_rx_sosi.sop, udp_rx_sosi.eop, out_gap);
-- SOSI data
-- . verify that the output is incrementing symbols, like the input stimuli
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
index f0db304df319bc52e955ad8d7fe7bbc449bdcc80..7294f7d67b01ce70a7b5f3d2373cbbe65d7f5114 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
@@ -43,7 +43,8 @@ architecture tb of tb_tb_eth is
constant c_technology_lcu : natural := c_tech_select_default;
constant c_tb_end_vec : std_logic_vector(15 downto 0) := (others => '1');
- signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ -- sufficiently long to fit all tb instances
+ signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec;
signal tb_end : std_logic := '0';
begin
-- g_technology_dut : NATURAL := c_tech_select_default;
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth_ip_header_checksum.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth_ip_header_checksum.vhd
index 3c0b451544d7a5bb79d6c094732410bd7867a345..85e1f6fde347a61ae1f82f8ae73f3dcf890e5400 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth_ip_header_checksum.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth_ip_header_checksum.vhd
@@ -25,13 +25,15 @@
library IEEE, dp_lib;
use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all; -- for t_dp_flow_control_enum
+-- for t_dp_flow_control_enum
+use dp_lib.tb_dp_pkg.all;
entity tb_tb_eth_ip_header_checksum is
end tb_tb_eth_ip_header_checksum;
architecture tb of tb_tb_eth_ip_header_checksum is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always e_active, e_random or e_pulse flow control
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth_stream_udp.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth_stream_udp.vhd
index 6ec8e8ecb7bfe6a025742a7c1deb774f97820fb2..77d095c8e2bf1f978b4042737867887d04cf33d6 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth_stream_udp.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth_stream_udp.vhd
@@ -38,7 +38,8 @@ architecture tb of tb_tb_eth_stream_udp is
constant c_eth_clk_MHz : natural := 125;
constant c_st_clk_MHz : natural := 200;
constant c_nof_sync : natural := 2;
- constant c_nof_blk : natural := 3; -- nof_blk per sync
+ -- nof_blk per sync
+ constant c_nof_blk : natural := 3;
-- Tx packet size and gap size in octets
constant c_block_len : natural := 50;
@@ -49,12 +50,15 @@ architecture tb of tb_tb_eth_stream_udp is
constant c_gap_len_min : natural := c_link_len * c_st_clk_MHz / c_eth_clk_MHz - c_block_len;
-- Choose c_gap_len somewhat larger to have packet link rate < 1 Gbps
- constant c_gap_len : natural := c_gap_len_min * 2; -- for g_nof_streams = 1
+ -- for g_nof_streams = 1
+ constant c_gap_len : natural := c_gap_len_min * 2;
-- BG ctrl
- constant c_high : natural := c_diag_bg_mem_max_adr; -- = 2**24
+ -- = 2**24
+ constant c_high : natural := c_diag_bg_mem_max_adr;
- constant c_bg_ctrl : t_diag_block_gen_integer := ('1', '1', c_block_len, c_nof_blk, c_gap_len, 0, c_high, 0); -- for first stream
+ -- for first stream
+ constant c_bg_ctrl : t_diag_block_gen_integer := ('1', '1', c_block_len, c_nof_blk, c_gap_len, 0, c_high, 0);
begin
-- g_tb_index : NATURAL := 0; -- use to incremental delay logging from tb instances in tb_tb
-- g_nof_sync : NATURAL := 2; -- number of BG sync intervals to set c_run_time
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd
index 5d5731ec82e95da17408db28991dd942aa916a9f..32ad7b6e06cc3364a409faf498fc1c28682738a1 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd
@@ -40,22 +40,27 @@ end tb_tb_eth_tester;
architecture tb of tb_tb_eth_tester is
-- Multi tb
- constant c_tb_w : natural := 100; -- sufficiently long to fit all tb instances
+ -- sufficiently long to fit all tb instances
+ constant c_tb_w : natural := 100;
constant c_tb_end_vec : std_logic_vector(c_tb_w - 1 downto 0) := (others => '1');
- signal tb_end_vec : std_logic_vector(c_tb_w - 1 downto 0) := c_tb_end_vec; -- best view as hex in Wave Window
+ -- best view as hex in Wave Window
+ signal tb_end_vec : std_logic_vector(c_tb_w - 1 downto 0) := c_tb_end_vec;
signal tb_end : std_logic := '0';
-- Tb
constant c_eth_clk_MHz : natural := 125;
constant c_st_clk_MHz : natural := 200;
constant c_nof_sync : natural := 2;
- constant c_nof_sync_many : natural := 50; -- sufficient to achieve Tx FIFO fill level
+ -- sufficient to achieve Tx FIFO fill level
+ constant c_nof_sync_many : natural := 50;
constant c_nof_streams : natural := 3;
- constant c_nof_blk : natural := 3; -- nof_blk per sync
+ -- nof_blk per sync
+ constant c_nof_blk : natural := 3;
-- Tx packet size and gap size in octets
- constant c_block_len : natural := 50; -- BG block length of first stream [0]
+ -- BG block length of first stream [0]
+ constant c_block_len : natural := 50;
constant c_block_len_odd : natural := 51;
constant c_block_len_jumbo : natural := 9000;
constant c_link_len : natural := func_eth_tester_eth_packet_on_link_length(c_block_len);
@@ -66,34 +71,48 @@ architecture tb of tb_tb_eth_tester is
constant c_slot_len_min : natural := c_block_len + c_gap_len_min;
-- Choose c_gap_len somewhat larger to have packet link rate < 1 Gbps
- constant c_gap_len : natural := c_gap_len_min * 2; -- for g_nof_streams = 1
+ -- for g_nof_streams = 1
+ constant c_gap_len : natural := c_gap_len_min * 2;
constant c_long_gap : natural := c_gap_len_min * 10;
- constant c_short_gap : natural := 10; -- to cause BG xon/xoff flow control
- constant c_zero_gap : natural := 0; -- to verify BG ready flow control
+ -- to cause BG xon/xoff flow control
+ constant c_short_gap : natural := 10;
+ -- to verify BG ready flow control
+ constant c_zero_gap : natural := 0;
-- Choose c_others_len > c_block_len, so same c_gap_len is suitable to
-- keep Ethernet link rate < 1 Gbps
- constant c_others_len : natural := 65; -- BG block length of other streams [c_nof_streams-1 : 1]
+ -- BG block length of other streams [c_nof_streams-1 : 1]
+ constant c_others_len : natural := 65;
-- BG ctrl
- constant c_high : natural := c_diag_bg_mem_max_adr; -- = 2**24
+ -- = 2**24
+ constant c_high : natural := c_diag_bg_mem_max_adr;
- constant c_bg_ctrl_rst : t_diag_block_gen_integer := ('0', '0', 1, c_nof_blk, c_gap_len, 0, c_high, 0); -- place holder for unused stream
+ -- place holder for unused stream
+ constant c_bg_ctrl_rst : t_diag_block_gen_integer := ('0', '0', 1, c_nof_blk, c_gap_len, 0, c_high, 0);
- constant c_bg_ctrl_one : t_diag_block_gen_integer := ('1', '1', c_block_len, c_nof_blk, c_gap_len, 0, c_high, 0); -- for first stream
- constant c_bg_ctrl_others : t_diag_block_gen_integer := ('1', '1', c_others_len, c_nof_blk, c_gap_len, 0, c_high, 0); -- for other streams
+ -- for first stream
+ constant c_bg_ctrl_one : t_diag_block_gen_integer := ('1', '1', c_block_len, c_nof_blk, c_gap_len, 0, c_high, 0);
+ -- for other streams
+ constant c_bg_ctrl_others : t_diag_block_gen_integer := ('1', '1', c_others_len, c_nof_blk, c_gap_len, 0, c_high, 0);
-- . BG with different block lengths and other payload values
-- The payload values are only verified manually using the Wave Window
- constant c_bg_ctrl_len_0 : t_diag_block_gen_integer := ('1', '1', c_block_len + 0, c_nof_blk, c_gap_len, 0, 0, 0); -- nof octets
- constant c_bg_ctrl_len_1 : t_diag_block_gen_integer := ('1', '1', c_block_len + 1, c_nof_blk, c_gap_len, 1, 1, 0); -- nof octets
- constant c_bg_ctrl_len_2 : t_diag_block_gen_integer := ('1', '1', c_block_len + 2, c_nof_blk, c_gap_len, 1, 7, 0); -- nof octets
- constant c_bg_ctrl_len_3 : t_diag_block_gen_integer := ('1', '1', c_block_len + 3, c_nof_blk, c_gap_len, c_high - 1, c_high - 1, 0); -- nof octets
+ -- nof octets
+ constant c_bg_ctrl_len_0 : t_diag_block_gen_integer := ('1', '1', c_block_len + 0, c_nof_blk, c_gap_len, 0, 0, 0);
+ -- nof octets
+ constant c_bg_ctrl_len_1 : t_diag_block_gen_integer := ('1', '1', c_block_len + 1, c_nof_blk, c_gap_len, 1, 1, 0);
+ -- nof octets
+ constant c_bg_ctrl_len_2 : t_diag_block_gen_integer := ('1', '1', c_block_len + 2, c_nof_blk, c_gap_len, 1, 7, 0);
+ -- nof octets
+ constant c_bg_ctrl_len_3 : t_diag_block_gen_integer := ('1', '1', c_block_len + 3, c_nof_blk, c_gap_len, c_high - 1, c_high - 1, 0);
constant c_bg_ctrl_corrupted : t_diag_block_gen_integer := ('1', '1', 1000, 1, 200, 0, c_high, 0);
- constant c_bg_ctrl_multiple_first : t_diag_block_gen_integer := ('1', '1', c_block_len, c_nof_blk, c_nof_streams * c_gap_len, 0, c_high, 0); -- for first stream
- constant c_bg_ctrl_multiple_others : t_diag_block_gen_integer := ('1', '1', c_others_len, c_nof_blk, c_nof_streams * c_gap_len, 0, c_high, 0); -- for other streams
+ -- for first stream
+ constant c_bg_ctrl_multiple_first : t_diag_block_gen_integer := ('1', '1', c_block_len, c_nof_blk, c_nof_streams * c_gap_len, 0, c_high, 0);
+ -- for other streams
+ constant c_bg_ctrl_multiple_others : t_diag_block_gen_integer := ('1', '1', c_others_len, c_nof_blk, c_nof_streams * c_gap_len, 0, c_high, 0);
begin
-- g_tb_index : NATURAL := 0; -- use to incremental delay logging from tb instances in tb_tb
-- g_nof_sync : NATURAL := 3; -- number of BG sync intervals to set c_run_time
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd
index b22af44ba50ef79cfff39471a0cb3f0b312ba25a..89f752f21e1d4aca42335188fa1bd5bb4c9540d5 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd
@@ -39,22 +39,27 @@ end tb_tb_eth_tester_high_bw;
architecture tb of tb_tb_eth_tester_high_bw is
-- Multi tb
- constant c_tb_w : natural := 100; -- sufficiently long to fit all tb instances
+ -- sufficiently long to fit all tb instances
+ constant c_tb_w : natural := 100;
constant c_tb_end_vec : std_logic_vector(c_tb_w - 1 downto 0) := (others => '1');
- signal tb_end_vec : std_logic_vector(c_tb_w - 1 downto 0) := c_tb_end_vec; -- best view as hex in Wave Window
+ -- best view as hex in Wave Window
+ signal tb_end_vec : std_logic_vector(c_tb_w - 1 downto 0) := c_tb_end_vec;
signal tb_end : std_logic := '0';
-- Tb
constant c_eth_clk_MHz : natural := 125;
constant c_st_clk_MHz : natural := 200;
constant c_nof_sync : natural := 2;
- constant c_nof_sync_many : natural := 50; -- sufficient to achieve Tx FIFO fill level
+ -- sufficient to achieve Tx FIFO fill level
+ constant c_nof_sync_many : natural := 50;
constant c_nof_streams : natural := 3;
- constant c_nof_blk : natural := 3; -- nof_blk per sync
+ -- nof_blk per sync
+ constant c_nof_blk : natural := 3;
-- Tx packet size and gap size in octets
- constant c_block_len : natural := 500; -- BG block length of first stream [0]
+ -- BG block length of first stream [0]
+ constant c_block_len : natural := 500;
constant c_block_len_jumbo : natural := 9000;
constant c_link_len : natural := func_eth_tester_eth_packet_on_link_length(c_block_len);
@@ -64,32 +69,46 @@ architecture tb of tb_tb_eth_tester_high_bw is
constant c_slot_len_min : natural := c_block_len + c_gap_len_min;
-- Choose c_gap_len somewhat larger to have packet link rate < 1 Gbps
- constant c_gap_len : natural := c_gap_len_min * 2; -- for g_nof_streams = 1
+ -- for g_nof_streams = 1
+ constant c_gap_len : natural := c_gap_len_min * 2;
constant c_long_gap : natural := c_gap_len_min * 10;
- constant c_short_gap : natural := 10; -- to cause BG xon/xoff flow control
- constant c_zero_gap : natural := 0; -- to verify BG ready flow control
+ -- to cause BG xon/xoff flow control
+ constant c_short_gap : natural := 10;
+ -- to verify BG ready flow control
+ constant c_zero_gap : natural := 0;
-- Choose c_others_len > c_block_len, so same c_gap_len is suitable to
-- keep Ethernet link rate < 1 Gbps
- constant c_others_len : natural := 65; -- BG block length of other streams [c_nof_streams-1 : 1]
+ -- BG block length of other streams [c_nof_streams-1 : 1]
+ constant c_others_len : natural := 65;
-- BG ctrl
- constant c_high : natural := c_diag_bg_mem_max_adr; -- = 2**24
+ -- = 2**24
+ constant c_high : natural := c_diag_bg_mem_max_adr;
- constant c_bg_ctrl_rst : t_diag_block_gen_integer := ('0', '0', 1, c_nof_blk, c_gap_len, 0, c_high, 0); -- place holder for unused stream
+ -- place holder for unused stream
+ constant c_bg_ctrl_rst : t_diag_block_gen_integer := ('0', '0', 1, c_nof_blk, c_gap_len, 0, c_high, 0);
- constant c_bg_ctrl_one : t_diag_block_gen_integer := ('1', '1', c_block_len, c_nof_blk, c_gap_len, 0, c_high, 0); -- for first stream
- constant c_bg_ctrl_others : t_diag_block_gen_integer := ('1', '1', c_others_len, c_nof_blk, c_gap_len, 0, c_high, 0); -- for other streams
+ -- for first stream
+ constant c_bg_ctrl_one : t_diag_block_gen_integer := ('1', '1', c_block_len, c_nof_blk, c_gap_len, 0, c_high, 0);
+ -- for other streams
+ constant c_bg_ctrl_others : t_diag_block_gen_integer := ('1', '1', c_others_len, c_nof_blk, c_gap_len, 0, c_high, 0);
-- . BG with different block lengths and other payload values
-- The payload values are only verified manually using the Wave Window
- constant c_bg_ctrl_len_0 : t_diag_block_gen_integer := ('1', '1', c_block_len + 0, c_nof_blk, c_gap_len, 0, 0, 0); -- nof octets
- constant c_bg_ctrl_len_1 : t_diag_block_gen_integer := ('1', '1', c_block_len + 1, c_nof_blk, c_gap_len, 1, 1, 0); -- nof octets
- constant c_bg_ctrl_len_2 : t_diag_block_gen_integer := ('1', '1', c_block_len + 2, c_nof_blk, c_gap_len, 1, 7, 0); -- nof octets
- constant c_bg_ctrl_len_3 : t_diag_block_gen_integer := ('1', '1', c_block_len + 3, c_nof_blk, c_gap_len, c_high - 1, c_high - 1, 0); -- nof octets
-
- constant c_bg_ctrl_multiple_first : t_diag_block_gen_integer := ('1', '1', c_block_len, c_nof_blk, c_nof_streams * c_gap_len, 0, c_high, 0); -- for first stream
- constant c_bg_ctrl_multiple_others : t_diag_block_gen_integer := ('1', '1', c_others_len, c_nof_blk, c_nof_streams * c_gap_len, 0, c_high, 0); -- for other streams
+ -- nof octets
+ constant c_bg_ctrl_len_0 : t_diag_block_gen_integer := ('1', '1', c_block_len + 0, c_nof_blk, c_gap_len, 0, 0, 0);
+ -- nof octets
+ constant c_bg_ctrl_len_1 : t_diag_block_gen_integer := ('1', '1', c_block_len + 1, c_nof_blk, c_gap_len, 1, 1, 0);
+ -- nof octets
+ constant c_bg_ctrl_len_2 : t_diag_block_gen_integer := ('1', '1', c_block_len + 2, c_nof_blk, c_gap_len, 1, 7, 0);
+ -- nof octets
+ constant c_bg_ctrl_len_3 : t_diag_block_gen_integer := ('1', '1', c_block_len + 3, c_nof_blk, c_gap_len, c_high - 1, c_high - 1, 0);
+
+ -- for first stream
+ constant c_bg_ctrl_multiple_first : t_diag_block_gen_integer := ('1', '1', c_block_len, c_nof_blk, c_nof_streams * c_gap_len, 0, c_high, 0);
+ -- for other streams
+ constant c_bg_ctrl_multiple_others : t_diag_block_gen_integer := ('1', '1', c_others_len, c_nof_blk, c_nof_streams * c_gap_len, 0, c_high, 0);
begin
-- g_tb_index : NATURAL := 0; -- use to incremental delay logging from tb instances in tb_tb
-- g_nof_sync : NATURAL := 3; -- number of BG sync intervals to set c_run_time
@@ -116,9 +135,12 @@ begin
-- Single stream
-----------------------------------------------------------------------------
-- Try different loopback interfaces
- u_st_10g : entity work.tb_eth_tester_high_bw generic map (0, c_nof_sync, 1, 8, 8, c_bg_ctrl_one, c_bg_ctrl_rst) port map (tb_end_vec(0)); -- 8 byte wide
- u_st_100g : entity work.tb_eth_tester_high_bw generic map (1, c_nof_sync, 1, 64, 64, c_bg_ctrl_one, c_bg_ctrl_rst) port map (tb_end_vec(1)); -- 64 byte wide
- u_st_max : entity work.tb_eth_tester_high_bw generic map (2, c_nof_sync, 1, 96, 96, c_bg_ctrl_one, c_bg_ctrl_rst) port map (tb_end_vec(2)); -- 96 byte wide as max dp.data width = 96*8=768 bits.
+ -- 8 byte wide
+ u_st_10g : entity work.tb_eth_tester_high_bw generic map (0, c_nof_sync, 1, 8, 8, c_bg_ctrl_one, c_bg_ctrl_rst) port map (tb_end_vec(0));
+ -- 64 byte wide
+ u_st_100g : entity work.tb_eth_tester_high_bw generic map (1, c_nof_sync, 1, 64, 64, c_bg_ctrl_one, c_bg_ctrl_rst) port map (tb_end_vec(1));
+ -- 96 byte wide as max dp.data width = 96*8=768 bits.
+ u_st_max : entity work.tb_eth_tester_high_bw generic map (2, c_nof_sync, 1, 96, 96, c_bg_ctrl_one, c_bg_ctrl_rst) port map (tb_end_vec(2));
-- Try large block size and nof blocks_per_sync = 1
u_st_jumbo1 : entity work.tb_eth_tester_high_bw generic map (10, c_nof_sync, 1, 96, 96,
diff --git a/libraries/io/eth1g/src/vhdl/eth1g.vhd b/libraries/io/eth1g/src/vhdl/eth1g.vhd
index 1e957edd5c04899dd31cbb2919c3f65059aab44a..1925a0869e960c8d50b926dd81b0ccd25e010490 100644
--- a/libraries/io/eth1g/src/vhdl/eth1g.vhd
+++ b/libraries/io/eth1g/src/vhdl/eth1g.vhd
@@ -42,40 +42,57 @@ use technology_lib.technology_select_pkg.all;
entity eth1g is
generic (
g_technology : natural := c_tech_select_default;
- g_init_ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := X"00000000"; -- 0.0.0.0
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_ETH_PHY : string := "LVDS"; -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+ -- 0.0.0.0
+ g_init_ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := X"00000000";
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
+ -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+ g_ETH_PHY : string := "LVDS";
g_ihl20 : boolean := false;
- g_frm_discard_en : boolean := false -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+ -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+ g_frm_discard_en : boolean := false
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- eth_clk : in std_logic; -- ethernet phy reference clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- packet stream clock
-
- cal_rec_clk : in std_logic := '0'; -- Calibration & reconfig clock when using XCVR
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- ethernet phy reference clock
+ eth_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- packet stream clock
+ st_clk : in std_logic;
+
+ -- Calibration & reconfig clock when using XCVR
+ cal_rec_clk : in std_logic := '0';
-- UDP transmit interface
- udp_tx_snk_in_arr : in t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_sosi_rst); -- ST sinks, default not valid if not used
+ -- ST sinks, default not valid if not used
+ udp_tx_snk_in_arr : in t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_sosi_rst);
udp_tx_snk_out_arr : out t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0);
-- UDP receive interface
- udp_rx_src_in_arr : in t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_siso_rdy); -- ST sources, default ready if not used
+ -- ST sources, default ready if not used
+ udp_rx_src_in_arr : in t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_siso_rdy);
udp_rx_src_out_arr : out t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0);
-- Memory Mapped Slaves
- tse_sla_in : in t_mem_mosi; -- ETH TSE MAC registers
+ -- ETH TSE MAC registers
+ tse_sla_in : in t_mem_mosi;
tse_sla_out : out t_mem_miso;
- reg_sla_in : in t_mem_mosi; -- ETH control and status registers
+ -- ETH control and status registers
+ reg_sla_in : in t_mem_mosi;
reg_sla_out : out t_mem_miso;
- reg_sla_interrupt : out std_logic; -- Interrupt
- ram_sla_in : in t_mem_mosi; -- ETH rx frame and tx frame memory
+ -- Interrupt
+ reg_sla_interrupt : out std_logic;
+ -- ETH rx frame and tx frame memory
+ ram_sla_in : in t_mem_mosi;
ram_sla_out : out t_mem_miso;
-- Monitoring
- rx_flushed_frm_cnt : out std_logic_vector(c_word_w - 1 downto 0); -- only used in simulation, because it will get optimized away in synthesis
+ -- only used in simulation, because it will get optimized away in synthesis
+ rx_flushed_frm_cnt : out std_logic_vector(c_word_w - 1 downto 0);
-- PHY interface
eth_txp : out std_logic;
@@ -98,19 +115,25 @@ architecture str of eth1g is
nof_dat => c_eth_ram_nof_words,
init_sl => '0');
- signal mem_in : t_mem_mosi; -- big endian on ST and TSE MAC network side
- signal mem_out : t_mem_miso; -- big endian on ST and TSE MAC network side
- signal mem_in_endian : t_mem_mosi; -- keep big endian on MM side
- signal mem_out_endian : t_mem_miso; -- keep big endian on MM side
+ -- big endian on ST and TSE MAC network side
+ signal mem_in : t_mem_mosi;
+ -- big endian on ST and TSE MAC network side
+ signal mem_out : t_mem_miso;
+ -- keep big endian on MM side
+ signal mem_in_endian : t_mem_mosi;
+ -- keep big endian on MM side
+ signal mem_out_endian : t_mem_miso;
------------------------------------------------------------------------------
-- ETH stream
------------------------------------------------------------------------------
-- Multiplex - demultiplex
- constant c_mux_nof_ports : natural := 1 + c_eth_nof_udp_ports; -- One for control + nof UDP ports
+ -- One for control + nof UDP ports
+ constant c_mux_nof_ports : natural := 1 + c_eth_nof_udp_ports;
constant c_demux_nof_ports : natural := c_mux_nof_ports;
- constant c_demux_combined : boolean := false; -- when TRUE then all downstream sinks must be ready, when FALSE then only the
+ -- when TRUE then all downstream sinks must be ready, when FALSE then only the
+ constant c_demux_combined : boolean := false;
-- selected sink needs to be ready (see dp_demux for more explanation).
-- All Rx (so UDP off-load and other ETH traffic)
signal rx_adapt_siso : t_dp_siso;
@@ -262,8 +285,10 @@ begin
u_adapt : entity dp_lib.dp_latency_adapter
generic map (
- g_in_latency => c_eth_rx_ready_latency, -- = 2
- g_out_latency => c_eth_ready_latency -- = 1
+ -- = 2
+ g_in_latency => c_eth_rx_ready_latency,
+ -- = 1
+ g_out_latency => c_eth_ready_latency
)
port map (
rst => st_rst,
@@ -286,14 +311,17 @@ begin
clk => st_clk,
-- Streaming Sink
- snk_in_err => rx_adapt_sosi.err(c_tech_tse_error_w - 1 downto 0), -- preserve error field from TSE MAC stream
+ -- preserve error field from TSE MAC stream
+ snk_in_err => rx_adapt_sosi.err(c_tech_tse_error_w - 1 downto 0),
snk_in => rx_adapt_sosi,
snk_out => rx_adapt_siso,
-- Streaming Source
src_in => rx_crc_siso,
- src_out => rx_crc_sosi, -- replaced CRC word by snk_in_err, so CRC word /=0 indicates any TSE error
- src_out_err => open -- flag snk_in_err/=0 at src_out.eop
+ -- replaced CRC word by snk_in_err, so CRC word /=0 indicates any TSE error
+ src_out => rx_crc_sosi,
+ -- flag snk_in_err/=0 at src_out.eop
+ src_out_err => open
);
------------------------------------------------------------------------------
@@ -448,9 +476,12 @@ begin
-- Streaming Source
-- . The src_rd, src_ack and src_done act instead of src_in.ready to have src_in ready per frame instead of per data word
- src_rd => rx_frame_rd, -- request frame pulse
- src_ack => rx_frame_ack, -- acknowledge request
- src_done => rx_frame_done, -- signal frame received
+ -- request frame pulse
+ src_rd => rx_frame_rd,
+ -- acknowledge request
+ src_ack => rx_frame_ack,
+ -- signal frame received
+ src_done => rx_frame_done,
src_out => rx_frame_sosi,
-- Monitoring
@@ -572,17 +603,21 @@ begin
g_use_error => false,
g_nof_input => c_mux_nof_ports,
g_use_fifo => false,
- g_fifo_size => array_init(1024, c_mux_nof_ports), -- input FIFOs are not used, but generic must match g_nof_input
- g_fifo_fill => array_init( 0, c_mux_nof_ports) -- input FIFOs are not used, but generic must match g_nof_input
+ -- input FIFOs are not used, but generic must match g_nof_input
+ g_fifo_size => array_init(1024, c_mux_nof_ports),
+ -- input FIFOs are not used, but generic must match g_nof_input
+ g_fifo_fill => array_init( 0, c_mux_nof_ports)
)
port map (
rst => st_rst,
clk => st_clk,
-- ST sinks
- snk_out_arr => mux_siso_arr, -- OUT = request to upstream ST source
+ -- OUT = request to upstream ST source
+ snk_out_arr => mux_siso_arr,
snk_in_arr => mux_sosi_arr,
-- ST source
- src_in => tx_mux_siso, -- IN = request from downstream ST sink
+ -- IN = request from downstream ST sink
+ src_in => tx_mux_siso,
src_out => tx_mux_sosi
);
@@ -613,9 +648,11 @@ begin
-- TSE MAC
------------------------------------------------------------------------------
tx_hdr_siso <= tse_tx_siso;
- tse_tx_sosi <= func_dp_stream_error_set(tx_hdr_sosi, 0); -- set err field (value 0 for OK)
+ -- set err field (value 0 for OK)
+ tse_tx_sosi <= func_dp_stream_error_set(tx_hdr_sosi, 0);
- tse_tx_mac_in.crc_fwd <= '0'; -- when '0' then TSE MAC generates the TX CRC field
+ -- when '0' then TSE MAC generates the TX CRC field
+ tse_tx_mac_in.crc_fwd <= '0';
u_tech_tse : entity tech_tse_lib.tech_tse
generic map (
@@ -639,7 +676,8 @@ begin
tx_snk_out => tse_tx_siso,
-- . MAC specific
tx_mac_in => tse_tx_mac_in,
- tx_mac_out => tse_tx_mac_out, -- OPEN
+ -- OPEN
+ tx_mac_out => tse_tx_mac_out,
-- MAC receive interface
-- . ST Source
rx_src_in => tse_rx_siso,
diff --git a/libraries/io/eth1g/src/vhdl/eth1g_master.vhd b/libraries/io/eth1g/src/vhdl/eth1g_master.vhd
index e96e339728011ec605ddd33938b177faf9be0984..5d6c98fea55893f86628bf8f55bba44ae0dd556c 100644
--- a/libraries/io/eth1g/src/vhdl/eth1g_master.vhd
+++ b/libraries/io/eth1g/src/vhdl/eth1g_master.vhd
@@ -43,7 +43,8 @@ use work.eth1g_mem_pkg.all;
entity eth1g_master is
generic (
- g_sim : boolean := false -- when true speed up led toggling in simulation
+ -- when true speed up led toggling in simulation
+ g_sim : boolean := false
);
port (
mm_rst : in std_logic;
@@ -64,30 +65,40 @@ end eth1g_master;
architecture rtl of eth1g_master is
-- ETH control
- constant c_reply_payload : boolean := false; -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
+ -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
+ constant c_reply_payload : boolean := false;
signal mm_init : std_logic := '1';
- signal tse_psc_access : std_logic := '0'; -- debug signal to view when PSC registers in TSE are accessed
+ -- debug signal to view when PSC registers in TSE are accessed
+ signal tse_psc_access : std_logic := '0';
-- TSE constants
- constant c_promis_en : boolean := false; -- FALSE receive only frames for this src_mac and broadcast, TRUE receive all
+ -- FALSE receive only frames for this src_mac and broadcast, TRUE receive all
+ constant c_promis_en : boolean := false;
-- Test bench supported packet data types
constant c_tb_tech_tse_data_type_symbols : natural := 0;
constant c_tb_tech_tse_data_type_counter : natural := 1;
constant c_tb_tech_tse_data_type_arp : natural := 2;
- constant c_tb_tech_tse_data_type_ping : natural := 3; -- over IP/ICMP
- constant c_tb_tech_tse_data_type_udp : natural := 4; -- over IP
+ -- over IP/ICMP
+ constant c_tb_tech_tse_data_type_ping : natural := 3;
+ -- over IP
+ constant c_tb_tech_tse_data_type_udp : natural := 4;
-- ETH control
constant c_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
-- . UDP header
- constant c_udp_port_ctrl : natural := 11; -- ETH demux UDP for control
- constant c_udp_port_st0 : natural := 57; -- ETH demux UDP port 0
- constant c_udp_port_st1 : natural := 58; -- ETH demux UDP port 1
- constant c_udp_port_st2 : natural := 59; -- ETH demux UDP port 2
- constant c_udp_port_en : natural := 16#10000#; -- ETH demux UDP port enable bit 16
+ -- ETH demux UDP for control
+ constant c_udp_port_ctrl : natural := 11;
+ -- ETH demux UDP port 0
+ constant c_udp_port_st0 : natural := 57;
+ -- ETH demux UDP port 1
+ constant c_udp_port_st1 : natural := 58;
+ -- ETH demux UDP port 2
+ constant c_udp_port_st2 : natural := 59;
+ -- ETH demux UDP port enable bit 16
+ constant c_udp_port_en : natural := 16#10000#;
-- used in eth setup
signal src_mac_hi : std_logic_vector(c_16 - 1 downto 0);
@@ -128,7 +139,8 @@ architecture rtl of eth1g_master is
--internals
eth_init : std_logic;
tse_init : std_logic;
- tse_psc_access : std_logic; -- debug signal to view when PSC registers in TSE are accessed
+ -- debug signal to view when PSC registers in TSE are accessed
+ tse_psc_access : std_logic;
ram_offset : natural;
state : t_state;
end record t_reg;
@@ -190,12 +202,14 @@ begin
-- END IF;
-- END IF;
--END PROCESS;
- mm_init <= '0' when rising_edge(mm_clk) and mm_rst = '0'; -- concurrent statement is equivalent to commented p_mm_init
+ -- concurrent statement is equivalent to commented p_mm_init
+ mm_init <= '0' when rising_edge(mm_clk) and mm_rst = '0';
p_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
- r <= (c_mem_mosi_rst, c_mem_mosi_rst, c_mem_mosi_rst, '1', '1', '0', 0, s_rst); -- reset all
+ -- reset all
+ r <= (c_mem_mosi_rst, c_mem_mosi_rst, c_mem_mosi_rst, '1', '1', '0', 0, s_rst);
elsif rising_edge(mm_clk) then
r <= nxt_r;
end if;
@@ -241,7 +255,8 @@ begin
case r.state is
when s_rst =>
- v := (c_mem_mosi_rst, c_mem_mosi_rst, c_mem_mosi_rst, '1', '1', '0', 0, s_rst); -- reset all
+ -- reset all
+ v := (c_mem_mosi_rst, c_mem_mosi_rst, c_mem_mosi_rst, '1', '1', '0', 0, s_rst);
if mm_init = '0' then v.state := s_wr_demux_0;
end if;
@@ -250,15 +265,18 @@ begin
when s_wr_demux_1 => proc_eth1g_mem_mm_bus_wr(c_eth_reg_demux_wi + 1, c_udp_port_en + c_udp_port_st1, v.reg_mosi); v.state := s_wr_demux_2;
when s_wr_demux_2 => proc_eth1g_mem_mm_bus_wr(c_eth_reg_demux_wi + 2, c_udp_port_en + c_udp_port_st2, v.reg_mosi); v.state := s_rd_demux_0;
--WHEN s_wr_demux_2 => proc_eth1g_mem_mm_bus_wr(c_eth_reg_demux_wi+2, c_udp_port_en+c_udp_port_st2, v.reg_mosi); v.state := s_wr_config_0;
- when s_rd_demux_0 => -- read back demux_0 settings
+ -- read back demux_0 settings
+ when s_rd_demux_0 =>
if lat_reg_rd = '0' then proc_eth1g_mem_mm_bus_rd(c_eth_reg_demux_wi + 0, v.reg_mosi);
elsif reg_rd_valid = '1' then v.state := s_rd_demux_1;
end if;
- when s_rd_demux_1 => -- read back demux_1 settings
+ -- read back demux_1 settings
+ when s_rd_demux_1 =>
if lat_reg_rd = '0' then proc_eth1g_mem_mm_bus_rd(c_eth_reg_demux_wi + 1, v.reg_mosi);
elsif reg_rd_valid = '1' then v.state := s_rd_demux_2;
end if;
- when s_rd_demux_2 => -- read back demux_2 settings
+ -- read back demux_2 settings
+ when s_rd_demux_2 =>
if lat_reg_rd = '0' then proc_eth1g_mem_mm_bus_rd(c_eth_reg_demux_wi + 2, v.reg_mosi);
elsif reg_rd_valid = '1' then v.state := s_wr_config_0;
end if;
@@ -274,7 +292,8 @@ begin
v.eth_init := '0';
v.tse_psc_access := '1';
- proc_eth1g_mem_mm_bus_rd(func_tech_tse_map_pcs_addr(16#22#), v.tse_mosi); -- REV --> 0x0901
+ -- REV --> 0x0901
+ proc_eth1g_mem_mm_bus_rd(func_tech_tse_map_pcs_addr(16#22#), v.tse_mosi);
v.state := s_wr_tse_if_mode;
when s_wr_tse_if_mode =>
@@ -298,9 +317,11 @@ begin
when s_wr_tse_control =>
if tse_miso.waitrequest = '0' then
if g_sim = true then
- proc_eth1g_mem_mm_bus_wr(func_tech_tse_map_pcs_addr(16#00#), 16#0140#, v.tse_mosi); -- PSC control, Auto negotiate disable
+ -- PSC control, Auto negotiate disable
+ proc_eth1g_mem_mm_bus_wr(func_tech_tse_map_pcs_addr(16#00#), 16#0140#, v.tse_mosi);
else
- proc_eth1g_mem_mm_bus_wr(func_tech_tse_map_pcs_addr(16#00#), 16#0140#, v.tse_mosi); -- PSC control, Auto negotiate disable
+ -- PSC control, Auto negotiate disable
+ proc_eth1g_mem_mm_bus_wr(func_tech_tse_map_pcs_addr(16#00#), 16#0140#, v.tse_mosi);
--proc_eth1g_mem_mm_bus_wr(func_tech_tse_map_pcs_addr(16#00#), 16#1140#, v.tse_mosi); -- PSC control, Auto negotiate enable
end if;
v.state := s_wr_tse_promis_en;
@@ -310,7 +331,8 @@ begin
if tse_miso.waitrequest = '0' then
v.tse_psc_access := '0';
if c_promis_en = false then
- proc_eth1g_mem_mm_bus_wr(16#008#, 16#0100004B#, v.tse_mosi); -- MAC control
+ -- MAC control
+ proc_eth1g_mem_mm_bus_wr(16#008#, 16#0100004B#, v.tse_mosi);
else
proc_eth1g_mem_mm_bus_wr(16#008#, 16#0100005B#, v.tse_mosi);
end if;
@@ -319,74 +341,86 @@ begin
when s_wr_tse_mac_0 =>
if tse_miso.waitrequest = '0' then
- proc_eth1g_mem_mm_bus_wr(16#00C#, src_mac_0, v.tse_mosi); -- MAC_0
+ -- MAC_0
+ proc_eth1g_mem_mm_bus_wr(16#00C#, src_mac_0, v.tse_mosi);
v.state := s_wr_tse_mac_1;
end if;
when s_wr_tse_mac_1 =>
if tse_miso.waitrequest = '0' then
- proc_eth1g_mem_mm_bus_wr(16#010#, src_mac_1, v.tse_mosi); -- MAC_1 <-- SRC_MAC
+ -- MAC_1 <-- SRC_MAC
+ proc_eth1g_mem_mm_bus_wr(16#010#, src_mac_1, v.tse_mosi);
v.state := s_wr_tse_tx_ipg_len;
end if;
when s_wr_tse_tx_ipg_len =>
if tse_miso.waitrequest = '0' then
- proc_eth1g_mem_mm_bus_wr(16#05C#, 16#0000000C#, v.tse_mosi); -- TX_IPG_LENGTH <-- interpacket gap = 12
+ -- TX_IPG_LENGTH <-- interpacket gap = 12
+ proc_eth1g_mem_mm_bus_wr(16#05C#, 16#0000000C#, v.tse_mosi);
v.state := s_wr_tse_frm_len;
end if;
when s_wr_tse_frm_len =>
if tse_miso.waitrequest = '0' then
--proc_eth1g_mem_mm_bus_wr(16#014#, 16#000005EE#, v.tse_mosi); -- FRM_LENGTH <-- receive max frame length = 1518
- proc_eth1g_mem_mm_bus_wr(16#014#, 16#0000233A#, v.tse_mosi); -- FRM_LENGTH <-- receive max frame length = 9018
+ -- FRM_LENGTH <-- receive max frame length = 9018
+ proc_eth1g_mem_mm_bus_wr(16#014#, 16#0000233A#, v.tse_mosi);
v.state := s_wr_tse_rx_section_empty;
end if;
when s_wr_tse_rx_section_empty =>
if tse_miso.waitrequest = '0' then
- proc_eth1g_mem_mm_bus_wr(16#01C#, c_tech_tse_rx_fifo_depth - 16, v.tse_mosi); -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_eth1g_mem_mm_bus_wr(16#01C#, c_tech_tse_rx_fifo_depth - 16, v.tse_mosi);
v.state := s_wr_tse_rx_section_full;
end if;
when s_wr_tse_rx_section_full =>
if tse_miso.waitrequest = '0' then
- proc_eth1g_mem_mm_bus_wr(16#020#, 16, v.tse_mosi); -- RX_SECTION_FULL <-- default 16
+ -- RX_SECTION_FULL <-- default 16
+ proc_eth1g_mem_mm_bus_wr(16#020#, 16, v.tse_mosi);
v.state := s_wr_tse_tx_section_empty;
end if;
when s_wr_tse_tx_section_empty =>
if tse_miso.waitrequest = '0' then
- proc_eth1g_mem_mm_bus_wr(16#024#, c_tech_tse_tx_fifo_depth - 16, v.tse_mosi); -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_eth1g_mem_mm_bus_wr(16#024#, c_tech_tse_tx_fifo_depth - 16, v.tse_mosi);
v.state := s_wr_tse_tx_section_full;
end if;
when s_wr_tse_tx_section_full =>
if tse_miso.waitrequest = '0' then
- proc_eth1g_mem_mm_bus_wr(16#028#, 16, v.tse_mosi); -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
+ -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
+ proc_eth1g_mem_mm_bus_wr(16#028#, 16, v.tse_mosi);
v.state := s_wr_tse_rx_almost_empty;
end if;
when s_wr_tse_rx_almost_empty =>
if tse_miso.waitrequest = '0' then
- proc_eth1g_mem_mm_bus_wr(16#02C#, 8, v.tse_mosi); -- RX_ALMOST_EMPTY <-- default 8
+ -- RX_ALMOST_EMPTY <-- default 8
+ proc_eth1g_mem_mm_bus_wr(16#02C#, 8, v.tse_mosi);
v.state := s_wr_tse_rx_almost_full;
end if;
when s_wr_tse_rx_almost_full =>
if tse_miso.waitrequest = '0' then
- proc_eth1g_mem_mm_bus_wr(16#030#, 8, v.tse_mosi); -- RX_ALMOST_FULL <-- default 8
+ -- RX_ALMOST_FULL <-- default 8
+ proc_eth1g_mem_mm_bus_wr(16#030#, 8, v.tse_mosi);
v.state := s_wr_tse_tx_almost_empty;
end if;
when s_wr_tse_tx_almost_empty =>
if tse_miso.waitrequest = '0' then
- proc_eth1g_mem_mm_bus_wr(16#034#, 8, v.tse_mosi); -- TX_ALMOST_EMPTY <-- default 8
+ -- TX_ALMOST_EMPTY <-- default 8
+ proc_eth1g_mem_mm_bus_wr(16#034#, 8, v.tse_mosi);
v.state := s_wr_tse_tx_almost_full;
end if;
when s_wr_tse_tx_almost_full =>
if tse_miso.waitrequest = '0' then
- proc_eth1g_mem_mm_bus_wr(16#038#, c_tech_tse_tx_ready_latency + 3, v.tse_mosi); -- TX_ALMOST_FULL <-- default 3
+ -- TX_ALMOST_FULL <-- default 3
+ proc_eth1g_mem_mm_bus_wr(16#038#, c_tech_tse_tx_ready_latency + 3, v.tse_mosi);
v.state := s_wait_interrupt_1;
v.tse_init := '0';
end if;
@@ -394,10 +428,12 @@ begin
-- -- start control loop -- --
when s_wait_interrupt_1 =>
if reg_interrupt = '1' then
- if lat_reg_rd = '0' then proc_eth1g_mem_mm_bus_rd(c_eth_reg_status_wi + 0, v.reg_mosi); -- read status register to read the status
+ -- read status register to read the status
+ if lat_reg_rd = '0' then proc_eth1g_mem_mm_bus_rd(c_eth_reg_status_wi + 0, v.reg_mosi);
elsif reg_rd_valid = '1' then
eth_mm_reg_status <= func_eth_mm_reg_status(reg_miso.rddata);
- proc_eth1g_mem_mm_bus_wr(c_eth_reg_status_wi + 0, 0, v.reg_mosi); -- write status register to acknowledge the interrupt
+ -- write status register to acknowledge the interrupt
+ proc_eth1g_mem_mm_bus_wr(c_eth_reg_status_wi + 0, 0, v.reg_mosi);
v.state := s_wait_interrupt_0;
end if;
end if;
@@ -406,7 +442,8 @@ begin
if reg_interrupt = '0' then
-- prepare control register for response
if c_reply_payload = true then
- eth_mm_reg_control.tx_nof_words <= INCR_UVEC(eth_mm_reg_status.rx_nof_words, -1); -- -1 to skip the CRC word for the response
+ -- -1 to skip the CRC word for the response
+ eth_mm_reg_control.tx_nof_words <= INCR_UVEC(eth_mm_reg_status.rx_nof_words, -1);
eth_mm_reg_control.tx_empty <= eth_mm_reg_status.rx_empty;
else
eth_mm_reg_control.tx_nof_words <= TO_UVEC(c_network_total_header_32b_nof_words, c_eth_max_frame_nof_words_w);
@@ -435,7 +472,8 @@ begin
when s_wr_control =>
v_eth_control_word := func_eth_mm_reg_control(eth_mm_reg_control);
proc_eth1g_mem_mm_bus_wr(c_eth_reg_control_wi + 0, TO_UINT(v_eth_control_word), v.reg_mosi); v.state := s_eth_continue;
- when s_eth_continue => proc_eth1g_mem_mm_bus_wr(c_eth_reg_continue_wi, 0, v.reg_mosi); v.state := s_wait_interrupt_1; -- write continue register to make the ETH module continue
+ -- write continue register to make the ETH module continue
+ when s_eth_continue => proc_eth1g_mem_mm_bus_wr(c_eth_reg_continue_wi, 0, v.reg_mosi); v.state := s_wait_interrupt_1;
when others => null;
end case;
diff --git a/libraries/io/eth1g/src/vhdl/eth1g_mem_pkg.vhd b/libraries/io/eth1g/src/vhdl/eth1g_mem_pkg.vhd
index 2829040000ac3f5f9a1f81185e1f8140da71b1d8..ccdbadc916e3c422ad1cb5a61c89b888f9dc7429 100644
--- a/libraries/io/eth1g/src/vhdl/eth1g_mem_pkg.vhd
+++ b/libraries/io/eth1g/src/vhdl/eth1g_mem_pkg.vhd
@@ -47,22 +47,30 @@ package eth1g_mem_pkg is
-- as signal).
-- Write data to the MM bus
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural; -- [31:0]
- constant wr_data : in integer; -- [31:0]
+ -- [31:0]
+ procedure proc_mem_mm_bus_wr(constant wr_addr : in natural;
+ -- [31:0]
+ constant wr_data : in integer;
signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
+ -- used for waitrequest
+ signal mm_miso : in t_mem_miso;
signal mm_mosi : out t_mem_mosi);
- procedure proc_mem_mm_bus_wr(constant wr_addr : in integer; -- [31:0]
- signal wr_data : in std_logic_vector; -- [31:0]
+ -- [31:0]
+ procedure proc_mem_mm_bus_wr(constant wr_addr : in integer;
+ -- [31:0]
+ signal wr_data : in std_logic_vector;
signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
+ -- used for waitrequest
+ signal mm_miso : in t_mem_miso;
signal mm_mosi : out t_mem_mosi);
-- Read data request to the MM bus
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural; -- [31:0]
+ -- [31:0]
+ procedure proc_mem_mm_bus_rd(constant rd_addr : in natural;
signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
+ -- used for waitrequest
+ signal mm_miso : in t_mem_miso;
signal mm_mosi : out t_mem_mosi);
-- Wait for read data valid after read latency mm_clk cycles
@@ -73,10 +81,13 @@ package eth1g_mem_pkg is
constant c_tech_tse_data_type_symbols : natural := 0;
constant c_tech_tse_data_type_counter : natural := 1;
constant c_tech_tse_data_type_arp : natural := 2;
- constant c_tech_tse_data_type_ping : natural := 3; -- over IP/ICMP
- constant c_tech_tse_data_type_udp : natural := 4; -- over IP
+ -- over IP/ICMP
+ constant c_tech_tse_data_type_ping : natural := 3;
+ -- over IP
+ constant c_tech_tse_data_type_udp : natural := 4;
- function func_tech_tse_header_size(data_type : natural) return natural; -- raw ethernet: 4 header words, protocol ethernet: 11 header words
+ -- raw ethernet: 4 header words, protocol ethernet: 11 header words
+ function func_tech_tse_header_size(data_type : natural) return natural;
-- Configure the TSE MAC
procedure proc_tech_tse_setup(constant c_promis_en : in boolean;
@@ -200,16 +211,22 @@ package body eth1g_mem_pkg is
begin
-- PSC control
psc_access <= '1';
- proc_mem_mm_bus_rd(func_map_pcs_addr(16#22#), mm_clk, mm_miso, mm_mosi); -- REV --> 0x0901
- proc_mem_mm_bus_wr(func_map_pcs_addr(16#28#), 16#0008#, mm_clk, mm_miso, mm_mosi); -- IF_MODE <-- Force 1GbE, no autonegatiation
- proc_mem_mm_bus_rd(func_map_pcs_addr(16#00#), mm_clk, mm_miso, mm_mosi); -- CONTROL --> 0x1140
- proc_mem_mm_bus_rd(func_map_pcs_addr(16#02#), mm_clk, mm_miso, mm_mosi); -- STATUS --> 0x000D
- proc_mem_mm_bus_wr(func_map_pcs_addr(16#00#), 16#0140#, mm_clk, mm_miso, mm_mosi); -- CONTROL <-- Auto negotiate disable
+ -- REV --> 0x0901
+ proc_mem_mm_bus_rd(func_map_pcs_addr(16#22#), mm_clk, mm_miso, mm_mosi);
+ -- IF_MODE <-- Force 1GbE, no autonegatiation
+ proc_mem_mm_bus_wr(func_map_pcs_addr(16#28#), 16#0008#, mm_clk, mm_miso, mm_mosi);
+ -- CONTROL --> 0x1140
+ proc_mem_mm_bus_rd(func_map_pcs_addr(16#00#), mm_clk, mm_miso, mm_mosi);
+ -- STATUS --> 0x000D
+ proc_mem_mm_bus_rd(func_map_pcs_addr(16#02#), mm_clk, mm_miso, mm_mosi);
+ -- CONTROL <-- Auto negotiate disable
+ proc_mem_mm_bus_wr(func_map_pcs_addr(16#00#), 16#0140#, mm_clk, mm_miso, mm_mosi);
--proc_mem_mm_bus_wr(func_map_pcs_addr(16#00#), 16#1140#, mm_clk, mm_miso, mm_mosi); -- CONTROL <-- Auto negotiate enable
psc_access <= '0';
-- MAC control
- proc_mem_mm_bus_rd(16#000#, mm_clk, mm_miso, mm_mosi); -- REV --> CUST_VERSION & 0x0901
+ -- REV --> CUST_VERSION & 0x0901
+ proc_mem_mm_bus_rd(16#000#, mm_clk, mm_miso, mm_mosi);
if c_promis_en = false then
proc_mem_mm_bus_wr(16#008#, 16#0100004B#, mm_clk, mm_miso, mm_mosi);
else
@@ -246,11 +263,15 @@ package body eth1g_mem_pkg is
-- [ 27] = DISABLE_RD_TIMEOUT = 0
-- [30-28] = RSVD = 000
-- [ 31] = CNT_RESET = 0, when 1 clear statistics
- proc_mem_mm_bus_wr(16#00C#, c_mac0, mm_clk, mm_miso, mm_mosi); -- MAC_0
- proc_mem_mm_bus_wr(16#010#, c_mac1, mm_clk, mm_miso, mm_mosi); -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
- proc_mem_mm_bus_wr(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi); -- TX_IPG_LENGTH <-- interpacket gap = 12
+ -- MAC_0
+ proc_mem_mm_bus_wr(16#00C#, c_mac0, mm_clk, mm_miso, mm_mosi);
+ -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
+ proc_mem_mm_bus_wr(16#010#, c_mac1, mm_clk, mm_miso, mm_mosi);
+ -- TX_IPG_LENGTH <-- interpacket gap = 12
+ proc_mem_mm_bus_wr(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi);
--proc_mem_mm_bus_wr(16#014#, 16#000005EE#, mm_clk, mm_miso, mm_mosi); -- FRM_LENGTH <-- receive max frame length = 1518
- proc_mem_mm_bus_wr(16#014#, 16#0000233A#, mm_clk, mm_miso, mm_mosi); -- FRM_LENGTH <-- receive max frame length = 9018
+ -- FRM_LENGTH <-- receive max frame length = 9018
+ proc_mem_mm_bus_wr(16#014#, 16#0000233A#, mm_clk, mm_miso, mm_mosi);
-- FIFO legenda:
-- . Tx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
@@ -272,17 +293,27 @@ package body eth1g_mem_pkg is
-- . c_tse_tx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Tx user respects ff_tx_rdy, to store a complete
-- ETH packet would require 1518 byte, so 2 M9K = 2k * 8b
-- . c_tse_rx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Rx user ff_rx_rdy is sufficiently active
- proc_mem_mm_bus_wr(16#01C#, c_tse_rx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
- proc_mem_mm_bus_wr(16#020#, 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_FULL <-- default 16
- proc_mem_mm_bus_wr(16#024#, c_tse_tx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
- proc_mem_mm_bus_wr(16#028#, 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
- proc_mem_mm_bus_wr(16#02C#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_EMPTY <-- default 8
- proc_mem_mm_bus_wr(16#030#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_FULL <-- default 8
- proc_mem_mm_bus_wr(16#034#, 8, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_EMPTY <-- default 8
- proc_mem_mm_bus_wr(16#038#, c_tx_ready_latency + 3, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_FULL <-- default 3
+ -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_mem_mm_bus_wr(16#01C#, c_tse_rx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi);
+ -- RX_SECTION_FULL <-- default 16
+ proc_mem_mm_bus_wr(16#020#, 16, mm_clk, mm_miso, mm_mosi);
+ -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_mem_mm_bus_wr(16#024#, c_tse_tx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi);
+ -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
+ proc_mem_mm_bus_wr(16#028#, 16, mm_clk, mm_miso, mm_mosi);
+ -- RX_ALMOST_EMPTY <-- default 8
+ proc_mem_mm_bus_wr(16#02C#, 8, mm_clk, mm_miso, mm_mosi);
+ -- RX_ALMOST_FULL <-- default 8
+ proc_mem_mm_bus_wr(16#030#, 8, mm_clk, mm_miso, mm_mosi);
+ -- TX_ALMOST_EMPTY <-- default 8
+ proc_mem_mm_bus_wr(16#034#, 8, mm_clk, mm_miso, mm_mosi);
+ -- TX_ALMOST_FULL <-- default 3
+ proc_mem_mm_bus_wr(16#038#, c_tx_ready_latency + 3, mm_clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd(16#0E8#, mm_clk, mm_miso, mm_mosi); -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
- proc_mem_mm_bus_rd(16#0EC#, mm_clk, mm_miso, mm_mosi); -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+ -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
+ proc_mem_mm_bus_rd(16#0E8#, mm_clk, mm_miso, mm_mosi);
+ -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+ proc_mem_mm_bus_rd(16#0EC#, mm_clk, mm_miso, mm_mosi);
wait until rising_edge(mm_clk);
end proc_tech_tse_setup;
diff --git a/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd b/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
index 1c7c417a59305b593829531394b9817d3c6799a6..6ccc432dfce3a58409613cb313adde331b15c9bf 100644
--- a/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
+++ b/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
@@ -59,9 +59,12 @@ entity tb_eth1g is
generic (
g_technology_dut : natural := c_tech_select_default;
g_technology_lcu : natural := c_tech_select_default;
- g_frm_discard_en : boolean := false; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
- g_flush_test_en : boolean := false; -- when TRUE send many large frames to enforce flush in eth_buffer
- g_tb_end : boolean := true; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+ g_frm_discard_en : boolean := false;
+ -- when TRUE send many large frames to enforce flush in eth_buffer
+ g_flush_test_en : boolean := false;
+ -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ g_tb_end : boolean := true;
-- g_data_type = c_tb_tech_tse_data_type_symbols = 0
-- g_data_type = c_tb_tech_tse_data_type_counter = 1
-- g_data_type = c_tb_tech_tse_data_type_arp = 2
@@ -75,31 +78,42 @@ entity tb_eth1g is
end tb_eth1g;
architecture tb of tb_eth1g is
- constant c_sim : boolean := false; -- TRUE;
- constant c_sim_level : natural := 1; -- 0 = use IP; 1 = use fast serdes model;
-
- constant sys_clk_period : time := 10 ns; -- 100 MHz
- constant eth_clk_period : time := 8 ns; -- 125 MHz
+ -- TRUE;
+ constant c_sim : boolean := false;
+ -- 0 = use IP; 1 = use fast serdes model;
+ constant c_sim_level : natural := 1;
+
+ -- 100 MHz
+ constant sys_clk_period : time := 10 ns;
+ -- 125 MHz
+ constant eth_clk_period : time := 8 ns;
constant cable_delay : time := 12 ns;
- constant c_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ constant c_cross_clock_domain : boolean := true;
-- TSE constants
constant c_promis_en : boolean := false;
- constant c_tx_ready_latency : natural := c_tech_tse_tx_ready_latency; -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
- constant c_nof_tx_not_valid : natural := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
+ constant c_tx_ready_latency : natural := c_tech_tse_tx_ready_latency;
+ -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ constant c_nof_tx_not_valid : natural := 0;
-- Payload user data
- constant c_tb_nof_data : natural := 0; -- nof UDP user data, nof ping padding data
- constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data; -- nof IP data,
+ -- nof UDP user data, nof ping padding data
+ constant c_tb_nof_data : natural := 0;
+ -- nof IP data,
+ constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data;
-- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
- constant c_tb_reply_payload : boolean := true; -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
+ -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
+ constant c_tb_reply_payload : boolean := true;
-- Packet headers
-- . Ethernet header
constant c_lcu_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"10FA01020300";
- constant c_dut_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ -- = 12-34-56-78-9A-BC
+ constant c_dut_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"123456789ABC";
constant c_dut_src_mac_hi : natural := TO_UINT(c_dut_src_mac(c_network_eth_mac_addr_w - 1 downto c_word_w));
constant c_dut_src_mac_lo : natural := TO_UINT(c_dut_src_mac( c_word_w - 1 downto 0));
-- support only ARP and IPv4 over ETH
@@ -112,12 +126,16 @@ architecture tb of tb_eth1g is
constant c_discard_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
src_mac => c_lcu_src_mac,
eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w));
- constant c_exp_eth_header : t_network_eth_header := (dst_mac => c_tx_eth_header.src_mac, -- \/
- src_mac => c_tx_eth_header.dst_mac, -- /\
- eth_type => c_tx_eth_header.eth_type); -- =
+ -- \/
+ constant c_exp_eth_header : t_network_eth_header := (dst_mac => c_tx_eth_header.src_mac,
+ -- /\
+ src_mac => c_tx_eth_header.dst_mac,
+ -- =
+ eth_type => c_tx_eth_header.eth_type);
-- . IP header
- constant c_lcu_ip_addr : natural := 16#05060708#; -- = 05:06:07:08
+ -- = 05:06:07:08
+ constant c_lcu_ip_addr : natural := 16#05060708#;
constant c_dut_ip_addr : natural := 16#01020304#;
constant c_tb_ip_total_length : natural := c_network_ip_total_length + c_tb_ip_nof_data;
@@ -134,22 +152,35 @@ architecture tb of tb_eth1g is
fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
- header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
+ -- init value (or try 0xEBBD = 60349)
+ header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w),
src_ip_addr => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
dst_ip_addr => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w));
- constant c_exp_ip_header : t_network_ip_header := (version => c_tx_ip_header.version, -- =
- header_length => c_tx_ip_header.header_length, -- =
- services => c_tx_ip_header.services, -- =
- total_length => c_tx_ip_header.total_length, -- =
- identification => c_tx_ip_header.identification, -- =
- flags => c_tx_ip_header.flags, -- =
- fragment_offset => c_tx_ip_header.fragment_offset, -- =
- time_to_live => c_tx_ip_header.time_to_live, -- =
- protocol => c_tx_ip_header.protocol, -- =
- header_checksum => c_tx_ip_header.header_checksum, -- init value
- src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
- dst_ip_addr => c_tx_ip_header.src_ip_addr); -- /\
+ -- =
+ constant c_exp_ip_header : t_network_ip_header := (version => c_tx_ip_header.version,
+ -- =
+ header_length => c_tx_ip_header.header_length,
+ -- =
+ services => c_tx_ip_header.services,
+ -- =
+ total_length => c_tx_ip_header.total_length,
+ -- =
+ identification => c_tx_ip_header.identification,
+ -- =
+ flags => c_tx_ip_header.flags,
+ -- =
+ fragment_offset => c_tx_ip_header.fragment_offset,
+ -- =
+ time_to_live => c_tx_ip_header.time_to_live,
+ -- =
+ protocol => c_tx_ip_header.protocol,
+ -- init value
+ header_checksum => c_tx_ip_header.header_checksum,
+ -- \/
+ src_ip_addr => c_tx_ip_header.dst_ip_addr,
+ -- /\
+ dst_ip_addr => c_tx_ip_header.src_ip_addr);
-- . ARP packet
constant c_tx_arp_packet : t_network_arp_packet := (htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
@@ -166,62 +197,92 @@ architecture tb of tb_eth1g is
ptype => c_tx_arp_packet.ptype,
hlen => c_tx_arp_packet.hlen,
plen => c_tx_arp_packet.plen,
- oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
- sha => c_tx_arp_packet.tha, -- \/
- spa => c_tx_arp_packet.tpa, -- /\ \/
- tha => c_tx_arp_packet.sha, -- / \ /\
- tpa => c_tx_arp_packet.spa); -- / \
+ -- reply
+ oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w),
+ -- \/
+ sha => c_tx_arp_packet.tha,
+ -- /\ \/
+ spa => c_tx_arp_packet.tpa,
+ -- / \ /\
+ tha => c_tx_arp_packet.sha,
+ -- / \
+ tpa => c_tx_arp_packet.spa);
-- . ICMP header
- constant c_tx_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w), -- ping request
+ -- ping request
+ constant c_tx_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w),
code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
- checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
+ -- init value
+ checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w),
id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
-- checksum is 0x0800 + original checksum
constant c_exp_icmp_checksum : std_logic_vector(c_network_icmp_checksum_w - 1 downto 0) := TO_UVEC( 2048 + TO_UINT(c_tx_icmp_header.checksum), c_network_icmp_checksum_w);
- constant c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
+ -- ping reply
+ constant c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w),
code => c_tx_icmp_header.code,
checksum => c_exp_icmp_checksum,
id => c_tx_icmp_header.id,
sequence => c_tx_icmp_header.sequence);
-- . UDP header
- constant c_dut_udp_port_ctrl : natural := 11; -- ETH demux UDP for control
- constant c_dut_udp_port_st0 : natural := 57; -- ETH demux UDP port 0
- constant c_dut_udp_port_st1 : natural := 58; -- ETH demux UDP port 1
- constant c_dut_udp_port_st2 : natural := 59; -- ETH demux UDP port 2
- constant c_dut_udp_port_en : natural := 16#10000#; -- ETH demux UDP port enable bit 16
- constant c_lcu_udp_port : natural := 10; -- UDP port used for src_port
- constant c_dut_udp_port_st : natural := c_dut_udp_port_st0; -- UDP port used for dst_port
+ -- ETH demux UDP for control
+ constant c_dut_udp_port_ctrl : natural := 11;
+ -- ETH demux UDP port 0
+ constant c_dut_udp_port_st0 : natural := 57;
+ -- ETH demux UDP port 1
+ constant c_dut_udp_port_st1 : natural := 58;
+ -- ETH demux UDP port 2
+ constant c_dut_udp_port_st2 : natural := 59;
+ -- ETH demux UDP port enable bit 16
+ constant c_dut_udp_port_en : natural := 16#10000#;
+ -- UDP port used for src_port
+ constant c_lcu_udp_port : natural := 10;
+ -- UDP port used for dst_port
+ constant c_dut_udp_port_st : natural := c_dut_udp_port_st0;
constant c_tb_udp_total_length : natural := c_network_udp_total_length + c_tb_nof_data;
constant c_tx_udp_header : t_network_udp_header := (src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
- dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
+ -- or use c_dut_udp_port_st#
+ dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w),
total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
- checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
-
- constant c_exp_udp_header : t_network_udp_header := (src_port => c_tx_udp_header.dst_port, -- \/
- dst_port => c_tx_udp_header.src_port, -- /\
- total_length => c_tx_udp_header.total_length, -- =
- checksum => c_tx_udp_header.checksum); -- init value
-
- signal tx_total_header : t_network_total_header; -- transmitted packet header
- signal discard_total_header: t_network_total_header; -- transmitted packet header for to be discarded packet
- signal exp_total_header : t_network_total_header; -- expected received packet header
+ -- init value
+ checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w));
+
+ -- \/
+ constant c_exp_udp_header : t_network_udp_header := (src_port => c_tx_udp_header.dst_port,
+ -- /\
+ dst_port => c_tx_udp_header.src_port,
+ -- =
+ total_length => c_tx_udp_header.total_length,
+ -- init value
+ checksum => c_tx_udp_header.checksum);
+
+ -- transmitted packet header
+ signal tx_total_header : t_network_total_header;
+ -- transmitted packet header for to be discarded packet
+ signal discard_total_header: t_network_total_header;
+ -- expected received packet header
+ signal exp_total_header : t_network_total_header;
-- ETH control
constant c_dut_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
constant c_dut_control_tx_en : natural := 2**c_eth_mm_reg_control_bi.tx_en;
-- Clocks and reset
- signal eth_clk : std_logic := '0'; -- tse reference clock
- signal sys_clk : std_logic := '0'; -- system clock
- signal st_clk : std_logic; -- stream clock
- signal st_rst : std_logic := '1'; -- reset synchronous with st_clk
- signal mm_clk : std_logic; -- memory-mapped bus clock
- signal mm_rst : std_logic := '1'; -- reset synchronous with mm_clk
+ -- tse reference clock
+ signal eth_clk : std_logic := '0';
+ -- system clock
+ signal sys_clk : std_logic := '0';
+ -- stream clock
+ signal st_clk : std_logic;
+ -- reset synchronous with st_clk
+ signal st_rst : std_logic := '1';
+ -- memory-mapped bus clock
+ signal mm_clk : std_logic;
+ -- reset synchronous with mm_clk
+ signal mm_rst : std_logic := '1';
-- ETH TSE interface
signal dut_tse_init : std_logic := '1';
@@ -278,8 +339,10 @@ architecture tb of tb_eth1g is
begin
-- run 50 us
- eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
- sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
+ -- TSE reference clock
+ eth_clk <= not eth_clk after eth_clk_period / 2;
+ -- System clock
+ sys_clk <= not sys_clk after sys_clk_period / 2;
mm_clk <= sys_clk;
st_clk <= sys_clk;
@@ -350,20 +413,28 @@ begin
while mm_rst = '1' loop wait until rising_edge(mm_clk); end loop;
-- Setup the DEMUX UDP
- proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 0, c_dut_udp_port_en + c_dut_udp_port_st0, mm_clk, eth_reg_miso, eth_reg_mosi); -- UDP port stream 0
- proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 1, c_dut_udp_port_en + c_dut_udp_port_st1, mm_clk, eth_reg_miso, eth_reg_mosi); -- UDP port stream 1
- proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 2, c_dut_udp_port_en + c_dut_udp_port_st2, mm_clk, eth_reg_miso, eth_reg_mosi); -- UDP port stream 2
+ -- UDP port stream 0
+ proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 0, c_dut_udp_port_en + c_dut_udp_port_st0, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- UDP port stream 1
+ proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 1, c_dut_udp_port_en + c_dut_udp_port_st1, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- UDP port stream 2
+ proc_mem_mm_bus_wr(c_eth_reg_demux_wi + 2, c_dut_udp_port_en + c_dut_udp_port_st2, mm_clk, eth_reg_miso, eth_reg_mosi);
proc_mem_mm_bus_rd(c_eth_reg_demux_wi + 0, mm_clk, eth_reg_miso, eth_reg_mosi);
proc_mem_mm_bus_rd(c_eth_reg_demux_wi + 1, mm_clk, eth_reg_miso, eth_reg_mosi);
proc_mem_mm_bus_rd(c_eth_reg_demux_wi + 2, mm_clk, eth_reg_miso, eth_reg_mosi);
-- Setup the RX config
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 0, c_dut_src_mac_lo, mm_clk, eth_reg_miso, eth_reg_mosi); -- control MAC address lo word
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 1, c_dut_src_mac_hi, mm_clk, eth_reg_miso, eth_reg_mosi); -- control MAC address hi halfword
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 2, c_dut_ip_addr, mm_clk, eth_reg_miso, eth_reg_mosi); -- control IP address
- proc_mem_mm_bus_wr(c_eth_reg_config_wi + 3, c_dut_udp_port_ctrl, mm_clk, eth_reg_miso, eth_reg_mosi); -- control UDP port
+ -- control MAC address lo word
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 0, c_dut_src_mac_lo, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- control MAC address hi halfword
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 1, c_dut_src_mac_hi, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- control IP address
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 2, c_dut_ip_addr, mm_clk, eth_reg_miso, eth_reg_mosi);
+ -- control UDP port
+ proc_mem_mm_bus_wr(c_eth_reg_config_wi + 3, c_dut_udp_port_ctrl, mm_clk, eth_reg_miso, eth_reg_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_dut_control_rx_en, mm_clk, eth_reg_miso, eth_reg_mosi); -- control rx en
+ -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, c_dut_control_rx_en, mm_clk, eth_reg_miso, eth_reg_mosi);
dut_eth_init <= '0';
-- Wait for TSE init
@@ -376,15 +447,18 @@ begin
-- wait for rx_avail interrupt
if eth_reg_interrupt = '1' then
-- read status register to read the status
- proc_mem_mm_bus_rd(c_eth_reg_status_wi + 0, mm_clk, eth_reg_miso, eth_reg_mosi); -- read result available in eth_mm_reg_status
+ -- read result available in eth_mm_reg_status
+ proc_mem_mm_bus_rd(c_eth_reg_status_wi + 0, mm_clk, eth_reg_miso, eth_reg_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
eth_mm_reg_status <= func_eth_mm_reg_status(eth_reg_miso.rddata);
wait until rising_edge(mm_clk);
-- write status register to acknowledge the interrupt
- proc_mem_mm_bus_wr(c_eth_reg_status_wi + 0, 0, mm_clk, eth_reg_miso, eth_reg_mosi); -- void value
+ -- void value
+ proc_mem_mm_bus_wr(c_eth_reg_status_wi + 0, 0, mm_clk, eth_reg_miso, eth_reg_mosi);
-- prepare control register for response
if c_tb_reply_payload = true then
- eth_mm_reg_control.tx_nof_words <= INCR_UVEC(eth_mm_reg_status.rx_nof_words, -1); -- -1 to skip the CRC word for the response
+ -- -1 to skip the CRC word for the response
+ eth_mm_reg_control.tx_nof_words <= INCR_UVEC(eth_mm_reg_status.rx_nof_words, -1);
eth_mm_reg_control.tx_empty <= eth_mm_reg_status.rx_empty;
else
eth_mm_reg_control.tx_nof_words <= TO_UVEC(c_network_total_header_32b_nof_words, c_eth_max_frame_nof_words_w);
@@ -409,7 +483,8 @@ begin
v_eth_control_word := func_eth_mm_reg_control(eth_mm_reg_control);
proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, TO_UINT(v_eth_control_word), mm_clk, eth_reg_miso, eth_reg_mosi);
-- write continue register to make the ETH module continue
- proc_mem_mm_bus_wr(c_eth_reg_continue_wi, 0, mm_clk, eth_reg_miso, eth_reg_mosi); -- void value
+ -- void value
+ proc_mem_mm_bus_wr(c_eth_reg_continue_wi, 0, mm_clk, eth_reg_miso, eth_reg_mosi);
end if;
wait until rising_edge(mm_clk);
end loop;
@@ -448,7 +523,8 @@ begin
lcu_tx_sosi.empty <= (others => '0');
lcu_tx_sosi.err <= (others => '0');
-- . MAC specific
- lcu_tx_mac_in.crc_fwd <= '0'; -- when '0' then TSE MAC generates the TX CRC field
+ -- when '0' then TSE MAC generates the TX CRC field
+ lcu_tx_mac_in.crc_fwd <= '0';
while lcu_init /= '0' loop wait until rising_edge(st_clk); end loop;
for I in 0 to 9 loop wait until rising_edge(st_clk); end loop;
@@ -624,7 +700,8 @@ begin
rx_timeout <= rx_timeout + 1;
if lcu_rx_sosi.valid = '1' then
rx_timeout <= 0;
- elsif rx_timeout > 5000 then -- sufficiently large value determined by trial
+ -- sufficiently large value determined by trial
+ elsif rx_timeout > 5000 then
rx_end <= '1';
end if;
wait until rising_edge(st_clk);
diff --git a/libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd b/libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd
index 98f9c0ae048fd7bf6a2ebfe6a8947a6712c1ae93..64e30de720174628ecddd458f1acc9e7ca9013b0 100644
--- a/libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd
+++ b/libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd
@@ -43,7 +43,8 @@ architecture tb of tb_tb_eth1g is
constant c_technology_lcu : natural := c_tech_select_default;
constant c_tb_end_vec : std_logic_vector(15 downto 0) := (others => '1');
- signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ -- sufficiently long to fit all tb instances
+ signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec;
signal tb_end : std_logic := '0';
begin
-- g_technology_dut : NATURAL := c_tech_select_default;
diff --git a/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd b/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
index 35261ba170dfffbae5967509bb1e84a9ad4b004c..80411121b3291362adc5d7092520233f2040c3b7 100644
--- a/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
+++ b/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
@@ -95,9 +95,11 @@ begin
)
port map (
corectl => start_sense,
- eoc => eoc, -- : OUT STD_LOGIC;
+ -- : OUT STD_LOGIC;
+ eoc => eoc,
reset => mm_rst,
- tempout => temp_data -- : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+ -- : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+ tempout => temp_data
);
-- The eoc signal goes high for one clock cycle of the 1-MHz internal oscillator clock,
@@ -115,7 +117,8 @@ begin
no_tech_fpga_temp_sens: if g_sim = true generate
-- temp = (693 * adc)/1024 - 265 => adc = (temp + 265)*1024/693
- temp_data <= TO_UVEC(458, temp_data'length); -- choose temp = 45 degrees so adc temp_data = 458
+ -- choose temp = 45 degrees so adc temp_data = 458
+ temp_data <= TO_UVEC(458, temp_data'length);
mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_temp_dat_w);
end generate;
diff --git a/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd b/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd
index 389c96fb2fa8618a86ac1229b8741c4a48083abb..247e54e005ed215f3a9224aed3f382186860ee3f 100644
--- a/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd
+++ b/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd
@@ -49,7 +49,8 @@ use work.i2c_pkg.all;
entity avs_i2c_master is
generic (
-- g_i2c_mm
- g_control_adr_w : natural := c_i2c_control_adr_w; -- =1, fixed
+ -- =1, fixed
+ g_control_adr_w : natural := c_i2c_control_adr_w;
g_protocol_adr_w : natural := c_i2c_protocol_adr_w;
g_result_adr_w : natural := c_i2c_result_adr_w;
-- g_i2c_phy
@@ -67,8 +68,10 @@ entity avs_i2c_master is
coe_sync_export : in std_logic := '1';
-- I2C interface
- coe_i2c_scl_export : inout std_logic; -- I2C Serial Clock Line
- coe_i2c_sda_export : inout std_logic; -- I2C Serial Data Line
+ -- I2C Serial Clock Line
+ coe_i2c_scl_export : inout std_logic;
+ -- I2C Serial Data Line
+ coe_i2c_sda_export : inout std_logic;
---------------------------------------------------------------------------
-- Avalon Clock Input interface: csi_*
@@ -80,22 +83,26 @@ entity avs_i2c_master is
-- Avalon Memory Mapped Slave interfaces: avs_*
---------------------------------------------------------------------------
-- MM slave I2C control register
- avs_control_address : in std_logic; -- g_control_adr_w=1
+ -- g_control_adr_w=1
+ avs_control_address : in std_logic;
avs_control_write : in std_logic;
avs_control_read : in std_logic;
- avs_control_writedata : in std_logic_vector(c_word_w - 1 downto 0); -- use default MM bus width for control
+ -- use default MM bus width for control
+ avs_control_writedata : in std_logic_vector(c_word_w - 1 downto 0);
avs_control_readdata : out std_logic_vector(c_word_w - 1 downto 0);
-- MM slave I2C protocol register
avs_protocol_address : in std_logic_vector(g_protocol_adr_w - 1 downto 0);
avs_protocol_write : in std_logic;
avs_protocol_read : in std_logic;
- avs_protocol_writedata : in std_logic_vector(c_byte_w - 1 downto 0); -- define MM bus data has same width as SMBus data
+ -- define MM bus data has same width as SMBus data
+ avs_protocol_writedata : in std_logic_vector(c_byte_w - 1 downto 0);
avs_protocol_readdata : out std_logic_vector(c_byte_w - 1 downto 0);
-- MM slave I2C result register
avs_result_address : in std_logic_vector(g_result_adr_w - 1 downto 0);
avs_result_write : in std_logic;
avs_result_read : in std_logic;
- avs_result_writedata : in std_logic_vector(c_byte_w - 1 downto 0); -- define MM bus data has same width as SMBus data
+ -- define MM bus data has same width as SMBus data
+ avs_result_writedata : in std_logic_vector(c_byte_w - 1 downto 0);
avs_result_readdata : out std_logic_vector(c_byte_w - 1 downto 0);
---------------------------------------------------------------------------
diff --git a/libraries/io/i2c/src/vhdl/i2c_bit.vhd b/libraries/io/i2c/src/vhdl/i2c_bit.vhd
index f2685c2b704c6dcf9c1041f2408041f4e0a0fb7d..89a8deab830301b710ba099397f37e54aca035cb 100644
--- a/libraries/io/i2c/src/vhdl/i2c_bit.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_bit.vhd
@@ -156,25 +156,36 @@ entity i2c_bit is
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
- ena : in std_logic; -- core enable signal
+ -- core enable signal
+ ena : in std_logic;
- clk_cnt : in unsigned(15 downto 0); -- clock prescale value
+ -- clock prescale value
+ clk_cnt : in unsigned(15 downto 0);
cmd : in std_logic_vector(3 downto 0);
- cmd_ack : out std_logic; -- command completed
- busy : out std_logic; -- i2c bus busy
- al : out std_logic; -- arbitration lost
+ -- command completed
+ cmd_ack : out std_logic;
+ -- i2c bus busy
+ busy : out std_logic;
+ -- arbitration lost
+ al : out std_logic;
din : in std_logic;
dout : out std_logic;
-- i2c lines
- scl_i : in std_logic; -- i2c clock line input
- scl_o : out std_logic; -- i2c clock line output
- scl_oen : out std_logic; -- i2c clock line output enable, active low
- sda_i : in std_logic; -- i2c data line input
- sda_o : out std_logic; -- i2c data line output
- sda_oen : out std_logic -- i2c data line output enable, active low
+ -- i2c clock line input
+ scl_i : in std_logic;
+ -- i2c clock line output
+ scl_o : out std_logic;
+ -- i2c clock line output enable, active low
+ scl_oen : out std_logic;
+ -- i2c data line input
+ sda_i : in std_logic;
+ -- i2c data line output
+ sda_o : out std_logic;
+ -- i2c data line output enable, active low
+ sda_oen : out std_logic
);
end entity i2c_bit;
@@ -189,14 +200,21 @@ architecture rtl of i2c_bit is
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state : states;
- signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
- signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
- signal dscl_oen : std_logic; -- delayed scl_oen signals
- signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
- signal clk_en, slave_wait : std_logic; -- clock generation signals
- signal ial : std_logic; -- internal arbitration lost signal
+ -- internal I2C lines
+ signal iscl_oen, isda_oen : std_logic;
+ -- check SDA status (multi-master arbitration)
+ signal sda_chk : std_logic;
+ -- delayed scl_oen signals
+ signal dscl_oen : std_logic;
+ -- synchronized SCL and SDA inputs
+ signal sSCL, sSDA : std_logic;
+ -- clock generation signals
+ signal clk_en, slave_wait : std_logic;
+ -- internal arbitration lost signal
+ signal ial : std_logic;
-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
- signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
+ -- clock divider counter (synthesis)
+ signal cnt : unsigned(15 downto 0);
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
@@ -239,11 +257,16 @@ begin
-- generate bus status controller
bus_status_ctrl: block
- signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA
- signal sta_condition : std_logic; -- start detected
- signal sto_condition : std_logic; -- stop detected
- signal cmd_stop : std_logic; -- STOP command
- signal ibusy : std_logic; -- internal busy signal
+ -- delayes sSCL and sSDA
+ signal dSCL, dSDA : std_logic;
+ -- start detected
+ signal sta_condition : std_logic;
+ -- stop detected
+ signal sto_condition : std_logic;
+ -- STOP command
+ signal cmd_stop : std_logic;
+ -- internal busy signal
+ signal ibusy : std_logic;
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
@@ -364,7 +387,8 @@ begin
isda_oen <= '1';
sda_chk <= '0';
else
- cmd_ack <= '0'; -- default no acknowledge
+ -- default no acknowledge
+ cmd_ack <= '0';
if (clk_en = '1') then
case (c_state) is
@@ -375,122 +399,181 @@ begin
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
- when others => c_state <= idle; -- NOP command
+ -- NOP command
+ when others => c_state <= idle;
end case;
- iscl_oen <= iscl_oen; -- keep SCL in same state
- isda_oen <= isda_oen; -- keep SDA in same state
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL in same state
+ iscl_oen <= iscl_oen;
+ -- keep SDA in same state
+ isda_oen <= isda_oen;
+ -- don't check SDA
+ sda_chk <= '0';
-- start
when start_a =>
c_state <= start_b;
- iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
- isda_oen <= '1'; -- set SDA high
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL in same state (for repeated start)
+ iscl_oen <= iscl_oen;
+ -- set SDA high
+ isda_oen <= '1';
+ -- don't check SDA
+ sda_chk <= '0';
when start_b =>
c_state <= start_c;
- iscl_oen <= '1'; -- set SCL high
- isda_oen <= '1'; -- keep SDA high
- sda_chk <= '0'; -- don't check SDA
+ -- set SCL high
+ iscl_oen <= '1';
+ -- keep SDA high
+ isda_oen <= '1';
+ -- don't check SDA
+ sda_chk <= '0';
when start_c =>
c_state <= start_d;
- iscl_oen <= '1'; -- keep SCL high
- isda_oen <= '0'; -- set SDA low
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL high
+ iscl_oen <= '1';
+ -- set SDA low
+ isda_oen <= '0';
+ -- don't check SDA
+ sda_chk <= '0';
when start_d =>
c_state <= start_e;
- iscl_oen <= '1'; -- keep SCL high
- isda_oen <= '0'; -- keep SDA low
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL high
+ iscl_oen <= '1';
+ -- keep SDA low
+ isda_oen <= '0';
+ -- don't check SDA
+ sda_chk <= '0';
when start_e =>
c_state <= idle;
- cmd_ack <= '1'; -- command completed
- iscl_oen <= '0'; -- set SCL low
- isda_oen <= '0'; -- keep SDA low
- sda_chk <= '0'; -- don't check SDA
+ -- command completed
+ cmd_ack <= '1';
+ -- set SCL low
+ iscl_oen <= '0';
+ -- keep SDA low
+ isda_oen <= '0';
+ -- don't check SDA
+ sda_chk <= '0';
-- stop
when stop_a =>
c_state <= stop_b;
- iscl_oen <= '0'; -- keep SCL low
- isda_oen <= '0'; -- set SDA low
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL low
+ iscl_oen <= '0';
+ -- set SDA low
+ isda_oen <= '0';
+ -- don't check SDA
+ sda_chk <= '0';
when stop_b =>
c_state <= stop_c;
- iscl_oen <= '1'; -- set SCL high
- isda_oen <= '0'; -- keep SDA low
- sda_chk <= '0'; -- don't check SDA
+ -- set SCL high
+ iscl_oen <= '1';
+ -- keep SDA low
+ isda_oen <= '0';
+ -- don't check SDA
+ sda_chk <= '0';
when stop_c =>
c_state <= stop_d;
- iscl_oen <= '1'; -- keep SCL high
- isda_oen <= '0'; -- keep SDA low
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL high
+ iscl_oen <= '1';
+ -- keep SDA low
+ isda_oen <= '0';
+ -- don't check SDA
+ sda_chk <= '0';
when stop_d =>
c_state <= idle;
- cmd_ack <= '1'; -- command completed
- iscl_oen <= '1'; -- keep SCL high
- isda_oen <= '1'; -- set SDA high
- sda_chk <= '0'; -- don't check SDA
+ -- command completed
+ cmd_ack <= '1';
+ -- keep SCL high
+ iscl_oen <= '1';
+ -- set SDA high
+ isda_oen <= '1';
+ -- don't check SDA
+ sda_chk <= '0';
-- read
when rd_a =>
c_state <= rd_b;
- iscl_oen <= '0'; -- keep SCL low
- isda_oen <= '1'; -- tri-state SDA
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL low
+ iscl_oen <= '0';
+ -- tri-state SDA
+ isda_oen <= '1';
+ -- don't check SDA
+ sda_chk <= '0';
when rd_b =>
c_state <= rd_c;
- iscl_oen <= '1'; -- set SCL high
- isda_oen <= '1'; -- tri-state SDA
- sda_chk <= '0'; -- don't check SDA
+ -- set SCL high
+ iscl_oen <= '1';
+ -- tri-state SDA
+ isda_oen <= '1';
+ -- don't check SDA
+ sda_chk <= '0';
when rd_c =>
c_state <= rd_d;
- iscl_oen <= '1'; -- keep SCL high
- isda_oen <= '1'; -- tri-state SDA
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL high
+ iscl_oen <= '1';
+ -- tri-state SDA
+ isda_oen <= '1';
+ -- don't check SDA
+ sda_chk <= '0';
when rd_d =>
c_state <= idle;
- cmd_ack <= '1'; -- command completed
- iscl_oen <= '0'; -- set SCL low
- isda_oen <= '1'; -- tri-state SDA
- sda_chk <= '0'; -- don't check SDA
+ -- command completed
+ cmd_ack <= '1';
+ -- set SCL low
+ iscl_oen <= '0';
+ -- tri-state SDA
+ isda_oen <= '1';
+ -- don't check SDA
+ sda_chk <= '0';
-- write
when wr_a =>
c_state <= wr_b;
- iscl_oen <= '0'; -- keep SCL low
- isda_oen <= din; -- set SDA
- sda_chk <= '0'; -- don't check SDA (SCL low)
+ -- keep SCL low
+ iscl_oen <= '0';
+ -- set SDA
+ isda_oen <= din;
+ -- don't check SDA (SCL low)
+ sda_chk <= '0';
when wr_b =>
c_state <= wr_c;
- iscl_oen <= '1'; -- set SCL high
- isda_oen <= din; -- keep SDA
- sda_chk <= '1'; -- check SDA
+ -- set SCL high
+ iscl_oen <= '1';
+ -- keep SDA
+ isda_oen <= din;
+ -- check SDA
+ sda_chk <= '1';
when wr_c =>
c_state <= wr_d;
- iscl_oen <= '1'; -- keep SCL high
- isda_oen <= din; -- keep SDA
- sda_chk <= '1'; -- check SDA
+ -- keep SCL high
+ iscl_oen <= '1';
+ -- keep SDA
+ isda_oen <= din;
+ -- check SDA
+ sda_chk <= '1';
when wr_d =>
c_state <= idle;
- cmd_ack <= '1'; -- command completed
- iscl_oen <= '0'; -- set SCL low
- isda_oen <= din; -- keep SDA
- sda_chk <= '0'; -- don't check SDA (SCL low)
+ -- command completed
+ cmd_ack <= '1';
+ -- set SCL low
+ iscl_oen <= '0';
+ -- keep SDA
+ isda_oen <= din;
+ -- don't check SDA (SCL low)
+ sda_chk <= '0';
when others =>
end case;
diff --git a/libraries/io/i2c/src/vhdl/i2c_bit_scl_sense.vhd b/libraries/io/i2c/src/vhdl/i2c_bit_scl_sense.vhd
index 81cd7c0a85b7107218a049c38919e9aa1ea2d2c8..56c7ee30a399a5943a7ba9c9b158863b2a2a8805 100644
--- a/libraries/io/i2c/src/vhdl/i2c_bit_scl_sense.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_bit_scl_sense.vhd
@@ -156,25 +156,36 @@ entity i2c_bit_scl_sense is
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
- ena : in std_logic; -- core enable signal
+ -- core enable signal
+ ena : in std_logic;
- clk_cnt : in unsigned(15 downto 0); -- clock prescale value
+ -- clock prescale value
+ clk_cnt : in unsigned(15 downto 0);
cmd : in std_logic_vector(3 downto 0);
- cmd_ack : out std_logic; -- command completed
- busy : out std_logic; -- i2c bus busy
- al : out std_logic; -- arbitration lost
+ -- command completed
+ cmd_ack : out std_logic;
+ -- i2c bus busy
+ busy : out std_logic;
+ -- arbitration lost
+ al : out std_logic;
din : in std_logic;
dout : out std_logic;
-- i2c lines
- scl_i : in std_logic; -- i2c clock line input
- scl_o : out std_logic; -- i2c clock line output
- scl_oen : out std_logic; -- i2c clock line output enable, active low
- sda_i : in std_logic; -- i2c data line input
- sda_o : out std_logic; -- i2c data line output
- sda_oen : out std_logic -- i2c data line output enable, active low
+ -- i2c clock line input
+ scl_i : in std_logic;
+ -- i2c clock line output
+ scl_o : out std_logic;
+ -- i2c clock line output enable, active low
+ scl_oen : out std_logic;
+ -- i2c data line input
+ sda_i : in std_logic;
+ -- i2c data line output
+ sda_o : out std_logic;
+ -- i2c data line output enable, active low
+ sda_oen : out std_logic
);
end entity i2c_bit_scl_sense;
@@ -189,14 +200,21 @@ architecture rtl of i2c_bit_scl_sense is
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state : states;
- signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
- signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
- signal dscl_oen : std_logic; -- delayed scl_oen signals
- signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
- signal clk_en, slave_wait : std_logic; -- clock generation signals
- signal ial : std_logic; -- internal arbitration lost signal
+ -- internal I2C lines
+ signal iscl_oen, isda_oen : std_logic;
+ -- check SDA status (multi-master arbitration)
+ signal sda_chk : std_logic;
+ -- delayed scl_oen signals
+ signal dscl_oen : std_logic;
+ -- synchronized SCL and SDA inputs
+ signal sSCL, sSDA : std_logic;
+ -- clock generation signals
+ signal clk_en, slave_wait : std_logic;
+ -- internal arbitration lost signal
+ signal ial : std_logic;
-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
- signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
+ -- clock divider counter (synthesis)
+ signal cnt : unsigned(15 downto 0);
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
@@ -239,11 +257,16 @@ begin
-- generate bus status controller
bus_status_ctrl: block
- signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA
- signal sta_condition : std_logic; -- start detected
- signal sto_condition : std_logic; -- stop detected
- signal cmd_stop : std_logic; -- STOP command
- signal ibusy : std_logic; -- internal busy signal
+ -- delayes sSCL and sSDA
+ signal dSCL, dSDA : std_logic;
+ -- start detected
+ signal sta_condition : std_logic;
+ -- stop detected
+ signal sto_condition : std_logic;
+ -- STOP command
+ signal cmd_stop : std_logic;
+ -- internal busy signal
+ signal ibusy : std_logic;
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
@@ -364,7 +387,8 @@ begin
isda_oen <= '1';
sda_chk <= '0';
else
- cmd_ack <= '0'; -- default no acknowledge
+ -- default no acknowledge
+ cmd_ack <= '0';
if (clk_en = '1') then
case (c_state) is
@@ -375,122 +399,181 @@ begin
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
- when others => c_state <= idle; -- NOP command
+ -- NOP command
+ when others => c_state <= idle;
end case;
- iscl_oen <= iscl_oen; -- keep SCL in same state
- isda_oen <= isda_oen; -- keep SDA in same state
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL in same state
+ iscl_oen <= iscl_oen;
+ -- keep SDA in same state
+ isda_oen <= isda_oen;
+ -- don't check SDA
+ sda_chk <= '0';
-- start
when start_a =>
c_state <= start_b;
- iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
- isda_oen <= '1'; -- set SDA high
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL in same state (for repeated start)
+ iscl_oen <= iscl_oen;
+ -- set SDA high
+ isda_oen <= '1';
+ -- don't check SDA
+ sda_chk <= '0';
when start_b =>
c_state <= start_c;
- iscl_oen <= '1'; -- set SCL high
- isda_oen <= '1'; -- keep SDA high
- sda_chk <= '0'; -- don't check SDA
+ -- set SCL high
+ iscl_oen <= '1';
+ -- keep SDA high
+ isda_oen <= '1';
+ -- don't check SDA
+ sda_chk <= '0';
when start_c =>
c_state <= start_d;
- iscl_oen <= '1'; -- keep SCL high
- isda_oen <= '0'; -- set SDA low
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL high
+ iscl_oen <= '1';
+ -- set SDA low
+ isda_oen <= '0';
+ -- don't check SDA
+ sda_chk <= '0';
when start_d =>
c_state <= start_e;
- iscl_oen <= '1'; -- keep SCL high
- isda_oen <= '0'; -- keep SDA low
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL high
+ iscl_oen <= '1';
+ -- keep SDA low
+ isda_oen <= '0';
+ -- don't check SDA
+ sda_chk <= '0';
when start_e =>
c_state <= idle;
- cmd_ack <= '1'; -- command completed
- iscl_oen <= '0'; -- set SCL low
- isda_oen <= '0'; -- keep SDA low
- sda_chk <= '0'; -- don't check SDA
+ -- command completed
+ cmd_ack <= '1';
+ -- set SCL low
+ iscl_oen <= '0';
+ -- keep SDA low
+ isda_oen <= '0';
+ -- don't check SDA
+ sda_chk <= '0';
-- stop
when stop_a =>
c_state <= stop_b;
- iscl_oen <= '0'; -- keep SCL low
- isda_oen <= '0'; -- set SDA low
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL low
+ iscl_oen <= '0';
+ -- set SDA low
+ isda_oen <= '0';
+ -- don't check SDA
+ sda_chk <= '0';
when stop_b =>
c_state <= stop_c;
- iscl_oen <= '1'; -- set SCL high
- isda_oen <= '0'; -- keep SDA low
- sda_chk <= '0'; -- don't check SDA
+ -- set SCL high
+ iscl_oen <= '1';
+ -- keep SDA low
+ isda_oen <= '0';
+ -- don't check SDA
+ sda_chk <= '0';
when stop_c =>
c_state <= stop_d;
- iscl_oen <= '1'; -- keep SCL high
- isda_oen <= '0'; -- keep SDA low
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL high
+ iscl_oen <= '1';
+ -- keep SDA low
+ isda_oen <= '0';
+ -- don't check SDA
+ sda_chk <= '0';
when stop_d =>
c_state <= idle;
- cmd_ack <= '1'; -- command completed
- iscl_oen <= '1'; -- keep SCL high
- isda_oen <= '1'; -- set SDA high
- sda_chk <= '0'; -- don't check SDA
+ -- command completed
+ cmd_ack <= '1';
+ -- keep SCL high
+ iscl_oen <= '1';
+ -- set SDA high
+ isda_oen <= '1';
+ -- don't check SDA
+ sda_chk <= '0';
-- read
when rd_a =>
c_state <= rd_b;
- iscl_oen <= '0'; -- keep SCL low
- isda_oen <= '1'; -- tri-state SDA
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL low
+ iscl_oen <= '0';
+ -- tri-state SDA
+ isda_oen <= '1';
+ -- don't check SDA
+ sda_chk <= '0';
when rd_b =>
c_state <= rd_c;
- iscl_oen <= '1'; -- set SCL high
- isda_oen <= '1'; -- tri-state SDA
- sda_chk <= '0'; -- don't check SDA
+ -- set SCL high
+ iscl_oen <= '1';
+ -- tri-state SDA
+ isda_oen <= '1';
+ -- don't check SDA
+ sda_chk <= '0';
when rd_c =>
c_state <= rd_d;
- iscl_oen <= '1'; -- keep SCL high
- isda_oen <= '1'; -- tri-state SDA
- sda_chk <= '0'; -- don't check SDA
+ -- keep SCL high
+ iscl_oen <= '1';
+ -- tri-state SDA
+ isda_oen <= '1';
+ -- don't check SDA
+ sda_chk <= '0';
when rd_d =>
c_state <= idle;
- cmd_ack <= '1'; -- command completed
- iscl_oen <= '0'; -- set SCL low
- isda_oen <= '1'; -- tri-state SDA
- sda_chk <= '0'; -- don't check SDA
+ -- command completed
+ cmd_ack <= '1';
+ -- set SCL low
+ iscl_oen <= '0';
+ -- tri-state SDA
+ isda_oen <= '1';
+ -- don't check SDA
+ sda_chk <= '0';
-- write
when wr_a =>
c_state <= wr_b;
- iscl_oen <= '0'; -- keep SCL low
- isda_oen <= din; -- set SDA
- sda_chk <= '0'; -- don't check SDA (SCL low)
+ -- keep SCL low
+ iscl_oen <= '0';
+ -- set SDA
+ isda_oen <= din;
+ -- don't check SDA (SCL low)
+ sda_chk <= '0';
when wr_b =>
c_state <= wr_c;
- iscl_oen <= '1'; -- set SCL high
- isda_oen <= din; -- keep SDA
- sda_chk <= '1'; -- check SDA
+ -- set SCL high
+ iscl_oen <= '1';
+ -- keep SDA
+ isda_oen <= din;
+ -- check SDA
+ sda_chk <= '1';
when wr_c =>
c_state <= wr_d;
- iscl_oen <= '1'; -- keep SCL high
- isda_oen <= din; -- keep SDA
- sda_chk <= '1'; -- check SDA
+ -- keep SCL high
+ iscl_oen <= '1';
+ -- keep SDA
+ isda_oen <= din;
+ -- check SDA
+ sda_chk <= '1';
when wr_d =>
c_state <= idle;
- cmd_ack <= '1'; -- command completed
- iscl_oen <= '0'; -- set SCL low
- isda_oen <= din; -- keep SDA
- sda_chk <= '0'; -- don't check SDA (SCL low)
+ -- command completed
+ cmd_ack <= '1';
+ -- set SCL low
+ iscl_oen <= '0';
+ -- keep SDA
+ isda_oen <= din;
+ -- don't check SDA (SCL low)
+ sda_chk <= '0';
when others =>
end case;
diff --git a/libraries/io/i2c/src/vhdl/i2c_byte.vhd b/libraries/io/i2c/src/vhdl/i2c_byte.vhd
index 1460a8c2728ffc8a2c3af891cf39a1163ddcdffb..36d5da47572860cab27945121c519414c6215f8b 100644
--- a/libraries/io/i2c/src/vhdl/i2c_byte.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_byte.vhd
@@ -96,11 +96,15 @@ entity i2c_byte is
);
port (
clk : in std_logic;
- rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
- nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
- ena : in std_logic; -- core enable signal
+ -- synchronous active high reset (WISHBONE compatible)
+ rst : in std_logic;
+ -- asynchornous active low reset (FPGA compatible)
+ nReset : in std_logic;
+ -- core enable signal
+ ena : in std_logic;
- clk_cnt : in unsigned(15 downto 0); -- 4x SCL
+ -- 4x SCL
+ clk_cnt : in unsigned(15 downto 0);
-- input signals
start,
@@ -111,19 +115,28 @@ entity i2c_byte is
din : in std_logic_vector(7 downto 0);
-- output signals
- cmd_ack : out std_logic; -- command done
+ -- command done
+ cmd_ack : out std_logic;
ack_out : out std_logic;
- i2c_busy : out std_logic; -- arbitration lost
- i2c_al : out std_logic; -- i2c bus busy
+ -- arbitration lost
+ i2c_busy : out std_logic;
+ -- i2c bus busy
+ i2c_al : out std_logic;
dout : out std_logic_vector(7 downto 0);
-- i2c lines
- scl_i : in std_logic; -- i2c clock line input
- scl_o : out std_logic; -- i2c clock line output
- scl_oen : out std_logic; -- i2c clock line output enable, active low
- sda_i : in std_logic; -- i2c data line input
- sda_o : out std_logic; -- i2c data line output
- sda_oen : out std_logic -- i2c data line output enable, active low
+ -- i2c clock line input
+ scl_i : in std_logic;
+ -- i2c clock line output
+ scl_o : out std_logic;
+ -- i2c clock line output enable, active low
+ scl_oen : out std_logic;
+ -- i2c data line input
+ sda_i : in std_logic;
+ -- i2c data line output
+ sda_o : out std_logic;
+ -- i2c data line output enable, active low
+ sda_oen : out std_logic
);
end entity i2c_byte;
@@ -133,25 +146,36 @@ architecture structural of i2c_byte is
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
- ena : in std_logic; -- core enable signal
+ -- core enable signal
+ ena : in std_logic;
- clk_cnt : in unsigned(15 downto 0); -- clock prescale value
+ -- clock prescale value
+ clk_cnt : in unsigned(15 downto 0);
cmd : in std_logic_vector(3 downto 0);
- cmd_ack : out std_logic; -- command done
- busy : out std_logic; -- i2c bus busy
- al : out std_logic; -- arbitration lost
+ -- command done
+ cmd_ack : out std_logic;
+ -- i2c bus busy
+ busy : out std_logic;
+ -- arbitration lost
+ al : out std_logic;
din : in std_logic;
dout : out std_logic;
-- i2c lines
- scl_i : in std_logic; -- i2c clock line input
- scl_o : out std_logic; -- i2c clock line output
- scl_oen : out std_logic; -- i2c clock line output enable, active low
- sda_i : in std_logic; -- i2c data line input
- sda_o : out std_logic; -- i2c data line output
- sda_oen : out std_logic -- i2c data line output enable, active low
+ -- i2c clock line input
+ scl_i : in std_logic;
+ -- i2c clock line output
+ scl_o : out std_logic;
+ -- i2c clock line output enable, active low
+ scl_oen : out std_logic;
+ -- i2c data line input
+ sda_i : in std_logic;
+ -- i2c data line output
+ sda_o : out std_logic;
+ -- i2c data line output enable, active low
+ sda_oen : out std_logic
);
end component i2c_bit;
component i2c_bit_scl_sense is
@@ -159,25 +183,36 @@ architecture structural of i2c_byte is
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
- ena : in std_logic; -- core enable signal
+ -- core enable signal
+ ena : in std_logic;
- clk_cnt : in unsigned(15 downto 0); -- clock prescale value
+ -- clock prescale value
+ clk_cnt : in unsigned(15 downto 0);
cmd : in std_logic_vector(3 downto 0);
- cmd_ack : out std_logic; -- command done
- busy : out std_logic; -- i2c bus busy
- al : out std_logic; -- arbitration lost
+ -- command done
+ cmd_ack : out std_logic;
+ -- i2c bus busy
+ busy : out std_logic;
+ -- arbitration lost
+ al : out std_logic;
din : in std_logic;
dout : out std_logic;
-- i2c lines
- scl_i : in std_logic; -- i2c clock line input
- scl_o : out std_logic; -- i2c clock line output
- scl_oen : out std_logic; -- i2c clock line output enable, active low
- sda_i : in std_logic; -- i2c data line input
- sda_o : out std_logic; -- i2c data line output
- sda_oen : out std_logic -- i2c data line output enable, active low
+ -- i2c clock line input
+ scl_i : in std_logic;
+ -- i2c clock line output
+ scl_o : out std_logic;
+ -- i2c clock line output enable, active low
+ scl_oen : out std_logic;
+ -- i2c data line input
+ sda_i : in std_logic;
+ -- i2c data line output
+ sda_o : out std_logic;
+ -- i2c data line output enable, active low
+ sda_oen : out std_logic
);
end component i2c_bit_scl_sense;
@@ -194,12 +229,14 @@ architecture structural of i2c_byte is
signal al : std_logic;
-- signals for shift register
- signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
+ -- 8bit shift register
+ signal sr : std_logic_vector(7 downto 0);
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
- signal dcnt : unsigned(2 downto 0); -- data counter
+ -- data counter
+ signal dcnt : unsigned(2 downto 0);
signal cnt_done : std_logic;
begin
-- hookup bit_controller
@@ -283,7 +320,8 @@ begin
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
- dcnt <= (others => '1'); -- load counter with 7
+ -- load counter with 7
+ dcnt <= (others => '1');
elsif (shift = '1') then
dcnt <= dcnt - 1;
end if;
@@ -340,7 +378,8 @@ begin
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
- else -- stop
+ -- stop
+ else
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
@@ -367,8 +406,10 @@ begin
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
- c_state <= st_write; -- stay in same state
- core_cmd <= I2C_CMD_WRITE; -- write next bit
+ -- stay in same state
+ c_state <= st_write;
+ -- write next bit
+ core_cmd <= I2C_CMD_WRITE;
shift <= '1';
end if;
end if;
@@ -379,8 +420,10 @@ begin
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
- c_state <= st_read; -- stay in same state
- core_cmd <= I2C_CMD_READ; -- read next bit
+ -- stay in same state
+ c_state <= st_read;
+ -- read next bit
+ core_cmd <= I2C_CMD_READ;
end if;
shift <= '1';
@@ -418,7 +461,8 @@ begin
host_ack <= '1';
end if;
- when others => -- illegal states
+ -- illegal states
+ when others =>
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander.vhd b/libraries/io/i2c/src/vhdl/i2c_commander.vhd
index 97c57a07b7176f32df7811d3e331de2fd6dff832..24392cd4cbf185aece91db03430bf90b7dd8d79d 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander.vhd
@@ -80,7 +80,8 @@ entity i2c_commander is
g_i2c_mm : t_c_i2c_mm;
g_i2c_phy : t_c_i2c_phy;
g_protocol_ram_init_file : string := "UNUSED";
- g_use_result_ram : boolean := false -- Default FALSE, because the protocol result in u_result_ram is only useful debug purposes, typically the commander status registers are sufficient
+ -- Default FALSE, because the protocol result in u_result_ram is only useful debug purposes, typically the commander status registers are sufficient
+ g_use_result_ram : boolean := false
);
port (
rst : in std_logic;
@@ -104,14 +105,17 @@ entity i2c_commander is
---------------------------------------------------------------------------
-- I2C interface
---------------------------------------------------------------------------
- scl : inout std_logic; -- I2C Serial Clock Line
- sda : inout std_logic -- I2C Serial Data Line
+ -- I2C Serial Clock Line
+ scl : inout std_logic;
+ -- I2C Serial Data Line
+ sda : inout std_logic
);
end i2c_commander;
architecture str of i2c_commander is
-- Use MM bus data width = SMBus data width = c_byte_w
- constant c_ram_rd_latency : natural := 1; -- instead of c_mem_ram_rd_latency = 2
+ -- instead of c_mem_ram_rd_latency = 2
+ constant c_ram_rd_latency : natural := 1;
constant c_protocol_ram : t_c_mem := (latency => c_ram_rd_latency,
adr_w => g_i2c_mm.protocol_adr_w,
@@ -135,9 +139,12 @@ architecture str of i2c_commander is
signal result_data_arr : t_slv_32_arr(0 to g_i2c_cmdr.nof_result_data_max - 1);
signal protocol_offset : natural;
- signal protocol_activate_pend : std_logic; -- pulse indicating new protocol list pending
- signal protocol_activate_evt : std_logic; -- pulse indicating new protocol list started
- signal result_ready_evt : std_logic; -- pulse indicating new result is available
+ -- pulse indicating new protocol list pending
+ signal protocol_activate_pend : std_logic;
+ -- pulse indicating new protocol list started
+ signal protocol_activate_evt : std_logic;
+ -- pulse indicating new result is available
+ signal result_ready_evt : std_logic;
-- SMBus control interface
signal protocol_rd_en : std_logic;
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander_aduh_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_commander_aduh_pkg.vhd
index befe290e7b1a3a79065a26b9e01bb8c5617d9e8a..6b397925427d7ec8b2e821105d5c35c2f1887b12 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander_aduh_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander_aduh_pkg.vhd
@@ -42,7 +42,8 @@ package i2c_commander_aduh_pkg is
constant k_protocol_list_5 : t_nat_natural_arr := c_i2c_adu_pca9555_protocol_list_set_atten_10_0db;
constant k_protocol_list_6 : t_nat_natural_arr := c_i2c_adu_pca9555_protocol_list_set_atten_10_6db;
constant k_protocol_list_7 : t_nat_natural_arr := c_i2c_adu_pca9555_protocol_list_set_cal;
- constant k_protocol_list_8 : t_nat_natural_arr := c_i2c_cmdr_protocol_list_end; -- use SMBUS_C_END for not used protocol lists
+ -- use SMBUS_C_END for not used protocol lists
+ constant k_protocol_list_8 : t_nat_natural_arr := c_i2c_cmdr_protocol_list_end;
constant k_protocol_list_9 : t_nat_natural_arr := c_i2c_cmdr_protocol_list_end;
constant k_protocol_list_10 : t_nat_natural_arr := c_i2c_cmdr_protocol_list_end;
constant k_protocol_list_11 : t_nat_natural_arr := c_i2c_cmdr_protocol_list_end;
@@ -176,12 +177,15 @@ package i2c_commander_aduh_pkg is
-- RAM sizes
constant k_protocol_ram_nof_dat : natural := ceil_div(k_protocol_ram_init'LENGTH, c_i2c_cmdr_mem_block_sz) * c_i2c_cmdr_mem_block_sz;
constant k_protocol_ram_adr_w : natural := ceil_log2(k_protocol_ram_nof_dat);
- constant k_result_adr_w : natural := k_protocol_ram_adr_w - 1; -- assume < 1 result byte per 2 protocol bytes
+ -- assume < 1 result byte per 2 protocol bytes
+ constant k_result_adr_w : natural := k_protocol_ram_adr_w - 1;
constant k_result_nof_dat : natural := 2**k_result_adr_w;
-- Commander settings
- constant k_nof_protocols : natural := 16; -- Must be >= actually used nof protocol lists in k_protocol_ram_init and <= c_i2c_cmdr_max_nof_protocols=16 protocols.
- constant k_nof_result_data_max : natural := 2; -- Must be >= the maximum nof read bytes in any protocol list in k_protocol_ram_init, choose 2 to also suit I2C read word
+ -- Must be >= actually used nof protocol lists in k_protocol_ram_init and <= c_i2c_cmdr_max_nof_protocols=16 protocols.
+ constant k_nof_protocols : natural := 16;
+ -- Must be >= the maximum nof read bytes in any protocol list in k_protocol_ram_init, choose 2 to also suit I2C read word
+ constant k_nof_result_data_max : natural := 2;
constant k_result_cnt_w : natural := k_result_adr_w;
------------------------------------------------------------------------------
@@ -200,14 +204,16 @@ package i2c_commander_aduh_pkg is
constant k_commander_nof_dat : natural := func_i2c_cmdr_mm_reg_nof_dat(c_i2c_cmdr_aduh_protocol_commander);
constant k_commander_adr_w : natural := ceil_log2(k_commander_nof_dat);
- constant c_i2c_cmdr_aduh_i2c_mm : t_c_i2c_mm := (k_commander_adr_w, -- use control_adr_w field to pass on k_commander_adr_w = ceil_log2(52) = 6
+ -- use control_adr_w field to pass on k_commander_adr_w = ceil_log2(52) = 6
+ constant c_i2c_cmdr_aduh_i2c_mm : t_c_i2c_mm := (k_commander_adr_w,
k_protocol_ram_adr_w,
k_protocol_ram_nof_dat,
k_result_adr_w,
k_result_nof_dat);
-- use full memory to avoid "Warning: Address pointed at port A is out of bound!" due to ram_crw_crw MegaWizard model in simulation
- constant c_i2c_cmdr_aduh_i2c_mm_sim : t_c_i2c_mm := (k_commander_adr_w, -- use control_adr_w field to pass on k_commander_adr_w = ceil_log2(52) = 6
+ -- use control_adr_w field to pass on k_commander_adr_w = ceil_log2(52) = 6
+ constant c_i2c_cmdr_aduh_i2c_mm_sim : t_c_i2c_mm := (k_commander_adr_w,
k_protocol_ram_adr_w,
2**k_protocol_ram_adr_w,
k_result_adr_w,
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander_ctrl.vhd b/libraries/io/i2c/src/vhdl/i2c_commander_ctrl.vhd
index 549f5ee46e320208c798f647de1ca1531c5bf1d3..01e34acf557b822d5e9457a4d03e436f119b7819 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander_ctrl.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander_ctrl.vhd
@@ -37,8 +37,10 @@ entity i2c_commander_ctrl is
);
port (
-- Clocks and reset
- rst : in std_logic; -- reset synchronous with clk
- clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with clk
+ rst : in std_logic;
+ -- memory-mapped bus clock
+ clk : in std_logic;
-- MM registers
protocol_wr : in std_logic;
@@ -72,7 +74,8 @@ architecture rtl of i2c_commander_ctrl is
signal nxt_protocol_offset : natural;
signal result_expected : std_logic_vector(c_word_w - 1 downto 0);
signal nxt_result_expected : std_logic_vector(c_word_w - 1 downto 0);
- signal expected_bi : natural range 0 to c_word_w - 1; -- bit index in result_expected
+ -- bit index in result_expected
+ signal expected_bi : natural range 0 to c_word_w - 1;
signal error_cnt : std_logic_vector(g_i2c_mm.protocol_adr_w - 1 downto 0);
signal nxt_error_cnt : std_logic_vector(g_i2c_mm.protocol_adr_w - 1 downto 0);
signal data_cnt : natural range 0 to g_i2c_cmdr.nof_result_data_max;
@@ -132,7 +135,8 @@ begin
if result_ready_evt = '1' then
nxt_state <= c_i2c_cmdr_state_done;
end if;
- when others => -- = c_i2c_cmdr_state_done
+ -- = c_i2c_cmdr_state_done
+ when others =>
if protocol_status_rd = '1' then
nxt_state <= c_i2c_cmdr_state_idle;
end if;
@@ -161,7 +165,8 @@ begin
end if;
else
-- the result_expected at the bit index contains '1' so it marks an I2C read data byte
- nxt_data_arr(data_cnt) <= RESIZE_UVEC(result_wr_dat, c_word_w); -- store one I2C read data byte per MM word
+ -- store one I2C read data byte per MM word
+ nxt_data_arr(data_cnt) <= RESIZE_UVEC(result_wr_dat, c_word_w);
nxt_data_cnt <= data_cnt + 1;
end if;
end if;
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_commander_pkg.vhd
index 4048565c321bfbd061cd4e7aa1a76fe0ac0a1058..f4adda6d7b64cc9510a6a386509319a1ce84ef45 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander_pkg.vhd
@@ -28,26 +28,36 @@ use work.i2c_smbus_pkg.all;
package i2c_commander_pkg is
-- I2C commander settings
--
- constant c_i2c_cmdr_state_idle : natural := 0; -- no protocol active
- constant c_i2c_cmdr_state_pending : natural := 1; -- protocol pending by write event, but not yet activated by sync
- constant c_i2c_cmdr_state_busy : natural := 2; -- protocol I2C accesses are busy
- constant c_i2c_cmdr_state_done : natural := 3; -- protocol I2C accesses finished
+ -- no protocol active
+ constant c_i2c_cmdr_state_idle : natural := 0;
+ -- protocol pending by write event, but not yet activated by sync
+ constant c_i2c_cmdr_state_pending : natural := 1;
+ -- protocol I2C accesses are busy
+ constant c_i2c_cmdr_state_busy : natural := 2;
+ -- protocol I2C accesses finished
+ constant c_i2c_cmdr_state_done : natural := 3;
constant c_i2c_cmdr_state_max : natural := 3;
constant c_i2c_cmdr_state_w : natural := ceil_log2(c_i2c_cmdr_state_max);
- constant c_i2c_cmdr_max_nof_protocols : natural := 16; -- fixed maximum number of protocol lists that t_c_i2cmdr record can support
- constant c_i2c_cmdr_result_cnt_w : natural := 16; -- more than sufficiently large range for most practical cases
- constant c_i2c_cmdr_nof_read_byte_max : natural := 8; -- Assume 8 read bytes per protocol list are sufficent, so c_i2c_cmdr_nof_read_byte_max=8 and use t_i2c_cmdr_natural_arr with range 0 to 7
+ -- fixed maximum number of protocol lists that t_c_i2cmdr record can support
+ constant c_i2c_cmdr_max_nof_protocols : natural := 16;
+ -- more than sufficiently large range for most practical cases
+ constant c_i2c_cmdr_result_cnt_w : natural := 16;
+ -- Assume 8 read bytes per protocol list are sufficent, so c_i2c_cmdr_nof_read_byte_max=8 and use t_i2c_cmdr_natural_arr with range 0 to 7
+ constant c_i2c_cmdr_nof_read_byte_max : natural := 8;
type t_i2c_cmdr_natural_arr is array (integer range 0 to c_i2c_cmdr_nof_read_byte_max - 1) of natural;
type t_i2c_cmdr_natural_mat is array (integer range <>) of t_i2c_cmdr_natural_arr;
type t_c_i2c_cmdr_commander is record
- nof_protocols : natural; -- must be <= c_i2cmdr_max_nof_protocols
+ -- must be <= c_i2cmdr_max_nof_protocols
+ nof_protocols : natural;
protocol_offset_arr : t_natural_arr(0 to c_i2c_cmdr_max_nof_protocols - 1);
result_expected_arr : t_slv_32_arr(0 to c_i2c_cmdr_max_nof_protocols - 1);
- result_cnt_w : natural; -- the nof result bytes that a protocol list may yield is <= 2**c_i2c_protocol_adr_w
- nof_result_data_max : natural; -- nof data bytes that a protocol list may maximally read
+ -- the nof result bytes that a protocol list may yield is <= 2**c_i2c_protocol_adr_w
+ result_cnt_w : natural;
+ -- nof data bytes that a protocol list may maximally read
+ nof_result_data_max : natural;
end record;
function func_i2c_cmdr_mm_reg_nof_dat(rec : t_c_i2c_cmdr_commander) return natural;
@@ -75,13 +85,15 @@ package i2c_commander_pkg is
constant c_i2c_cmdr_nof_result_data_read_one_byte : natural := 1;
constant c_i2c_cmdr_nof_result_data_read_one_word : natural := 2;
- constant c_i2c_cmdr_expected_x : natural := 254; -- do not use 255, because that matches pull-up all ones
+ -- do not use 255, because that matches pull-up all ones
+ constant c_i2c_cmdr_expected_x : natural := 254;
constant c_i2c_cmdr_expected_data_none_arr : t_i2c_cmdr_natural_arr := (c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x,
c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x,
c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x,
c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x);
- constant c_i2c_cmdr_mem_block_sz : natural := 1024; -- assign t_c_mem.nof_dat in blocks of 1024 = 1 M9K
+ -- assign t_c_mem.nof_dat in blocks of 1024 = 1 M9K
+ constant c_i2c_cmdr_mem_block_sz : natural := 1024;
end i2c_commander_pkg;
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander_reg.vhd b/libraries/io/i2c/src/vhdl/i2c_commander_reg.vhd
index 818be9fceaae95202943b901972a1ebf7a708c5f..cec6c6e736df4e4a8d4258f57d93abe9fe54d82f 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander_reg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander_reg.vhd
@@ -40,12 +40,16 @@ entity i2c_commander_reg is
);
port (
-- Clocks and reset
- rst : in std_logic; -- reset synchronous with clk
- clk : in std_logic; -- memory-mapped bus clock
+ -- reset synchronous with clk
+ rst : in std_logic;
+ -- memory-mapped bus clock
+ clk : in std_logic;
-- Memory Mapped Slave
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers
protocol_wr : out std_logic;
@@ -61,7 +65,8 @@ end i2c_commander_reg;
architecture rtl of i2c_commander_reg is
-- Use shorter aliases for some generic constants
- constant c_nof_protocols : natural := g_i2c_cmdr.nof_protocols; -- must be <= c_i2c_max_nof_protocols to fit the t_c_i2c_cmdr_commander record
+ -- must be <= c_i2c_max_nof_protocols to fit the t_c_i2c_cmdr_commander record
+ constant c_nof_protocols : natural := g_i2c_cmdr.nof_protocols;
constant c_nof_result_data_max : natural := g_i2c_cmdr.nof_result_data_max;
constant c_protocol_adr_w : natural := g_i2c_mm.protocol_adr_w;
@@ -89,7 +94,8 @@ architecture rtl of i2c_commander_reg is
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => c_mm_reg_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => c_mm_reg_nof_dat,
init_sl => '0');
@@ -164,8 +170,10 @@ begin
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case v_address is
-- Read offset address per commander protocol
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander_unb2_pmbus_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_commander_unb2_pmbus_pkg.vhd
index e63ef8691cf5705c7fdb97e2a872be4fce61857d..1369ef6b6e6baad384ce299c54bdc33c3ad5d330 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander_unb2_pmbus_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander_unb2_pmbus_pkg.vhd
@@ -132,12 +132,15 @@ package i2c_commander_unb2_pmbus_pkg is
-- RAM sizes
constant k_protocol_ram_nof_dat : natural := ceil_div(k_protocol_ram_init'LENGTH, c_i2c_cmdr_mem_block_sz) * c_i2c_cmdr_mem_block_sz;
constant k_protocol_ram_adr_w : natural := ceil_log2(k_protocol_ram_nof_dat);
- constant k_result_adr_w : natural := k_protocol_ram_adr_w - 1; -- assume < 1 result byte per 2 protocol bytes
+ -- assume < 1 result byte per 2 protocol bytes
+ constant k_result_adr_w : natural := k_protocol_ram_adr_w - 1;
constant k_result_nof_dat : natural := 2**k_result_adr_w;
-- Commander settings
- constant k_nof_protocols : natural := 2; -- Must be >= actually used nof protocol lists in k_protocol_ram_init and <= c_i2c_cmdr_max_nof_protocols=16 protocols.
- constant k_nof_result_data_max : natural := 32; -- Must be >= the maximum nof read bytes in any protocol list in k_protocol_ram_init
+ -- Must be >= actually used nof protocol lists in k_protocol_ram_init and <= c_i2c_cmdr_max_nof_protocols=16 protocols.
+ constant k_nof_protocols : natural := 2;
+ -- Must be >= the maximum nof read bytes in any protocol list in k_protocol_ram_init
+ constant k_nof_result_data_max : natural := 32;
constant k_result_cnt_w : natural := k_result_adr_w;
------------------------------------------------------------------------------
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander_unb2_sens_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_commander_unb2_sens_pkg.vhd
index 0a140460876ec70a9e53f379412f3d3045cc1a42..9e8613f42b4736e072c36c71f849adc13c6f5384 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander_unb2_sens_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander_unb2_sens_pkg.vhd
@@ -30,7 +30,8 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use work.i2c_pkg.all;
use work.i2c_commander_pkg.all;
-use work.i2c_dev_unb2_pkg.all; -- slave addresses and commands for all unb2 i2c interfaces
+-- slave addresses and commands for all unb2 i2c interfaces
+use work.i2c_dev_unb2_pkg.all;
package i2c_commander_unb2_sens_pkg is
------------------------------------------------------------------------------
@@ -132,12 +133,15 @@ package i2c_commander_unb2_sens_pkg is
-- RAM sizes
constant k_protocol_ram_nof_dat : natural := ceil_div(k_protocol_ram_init'LENGTH, c_i2c_cmdr_mem_block_sz) * c_i2c_cmdr_mem_block_sz;
constant k_protocol_ram_adr_w : natural := ceil_log2(k_protocol_ram_nof_dat);
- constant k_result_adr_w : natural := k_protocol_ram_adr_w - 1; -- assume < 1 result byte per 2 protocol bytes
+ -- assume < 1 result byte per 2 protocol bytes
+ constant k_result_adr_w : natural := k_protocol_ram_adr_w - 1;
constant k_result_nof_dat : natural := 2**k_result_adr_w;
-- Commander settings
- constant k_nof_protocols : natural := 3; -- Must be >= actually used nof protocol lists in k_protocol_ram_init and <= c_i2c_cmdr_max_nof_protocols=16 protocols.
- constant k_nof_result_data_max : natural := 32; -- Must be >= the maximum nof read bytes in any protocol list in k_protocol_ram_init
+ -- Must be >= actually used nof protocol lists in k_protocol_ram_init and <= c_i2c_cmdr_max_nof_protocols=16 protocols.
+ constant k_nof_protocols : natural := 3;
+ -- Must be >= the maximum nof read bytes in any protocol list in k_protocol_ram_init
+ constant k_nof_result_data_max : natural := 32;
constant k_result_cnt_w : natural := k_result_adr_w;
------------------------------------------------------------------------------
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander_unbh_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_commander_unbh_pkg.vhd
index 61a54ef3fd8434061ed2a81bb7ad1c83a75dccd5..293c5647ab1ec39092fb81d9b00fc270651ee3be 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander_unbh_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander_unbh_pkg.vhd
@@ -40,7 +40,8 @@ package i2c_commander_unbh_pkg is
-- Define the protocol lists for the commander (c_i2c_cmdr_max_nof_protocols=16)
constant k_protocol_list_0 : t_nat_natural_arr := c_i2c_unb_max1617_protocol_list_read_temp;
constant k_protocol_list_1 : t_nat_natural_arr := c_i2c_unb_max6652_protocol_list_read_config;
- constant k_protocol_list_2 : t_nat_natural_arr := c_i2c_cmdr_protocol_list_end; -- use SMBUS_C_END for not used protocol lists
+ -- use SMBUS_C_END for not used protocol lists
+ constant k_protocol_list_2 : t_nat_natural_arr := c_i2c_cmdr_protocol_list_end;
constant k_protocol_list_3 : t_nat_natural_arr := c_i2c_cmdr_protocol_list_end;
constant k_protocol_list_4 : t_nat_natural_arr := c_i2c_cmdr_protocol_list_end;
constant k_protocol_list_5 : t_nat_natural_arr := c_i2c_cmdr_protocol_list_end;
@@ -180,12 +181,15 @@ package i2c_commander_unbh_pkg is
-- RAM sizes
constant k_protocol_ram_nof_dat : natural := ceil_div(k_protocol_ram_init'LENGTH, c_i2c_cmdr_mem_block_sz) * c_i2c_cmdr_mem_block_sz;
constant k_protocol_ram_adr_w : natural := ceil_log2(k_protocol_ram_nof_dat);
- constant k_result_adr_w : natural := k_protocol_ram_adr_w - 1; -- assume < 1 result byte per 2 protocol bytes
+ -- assume < 1 result byte per 2 protocol bytes
+ constant k_result_adr_w : natural := k_protocol_ram_adr_w - 1;
constant k_result_nof_dat : natural := 2**k_result_adr_w;
-- Commander settings
- constant k_nof_protocols : natural := 2; -- Must be >= actually used nof protocol lists in k_protocol_ram_init and <= c_i2c_cmdr_max_nof_protocols=16 protocols.
- constant k_nof_result_data_max : natural := 4; -- Must be >= the maximum nof read bytes in any protocol list in k_protocol_ram_init
+ -- Must be >= actually used nof protocol lists in k_protocol_ram_init and <= c_i2c_cmdr_max_nof_protocols=16 protocols.
+ constant k_nof_protocols : natural := 2;
+ -- Must be >= the maximum nof read bytes in any protocol list in k_protocol_ram_init
+ constant k_nof_result_data_max : natural := 4;
constant k_result_cnt_w : natural := k_result_adr_w;
------------------------------------------------------------------------------
diff --git a/libraries/io/i2c/src/vhdl/i2c_dev_adu_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_dev_adu_pkg.vhd
index ce9c30ba209608e9e1af18b5596e10f3f501216b..7bf946def18c632980e80272a61b6fee0d89de8e 100644
--- a/libraries/io/i2c/src/vhdl/i2c_dev_adu_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_dev_adu_pkg.vhd
@@ -28,8 +28,10 @@ use work.i2c_commander_pkg.all;
package i2c_dev_adu_pkg is
-- I2C slave addresses of the devices on the I2C bus on ADU
- constant I2C_ADU_MAX1617_ADR : natural := MAX1617_ADR_LOW_LOW; -- temperature sensor, slave address is "0011000"
- constant I2C_ADU_PCA9555_ADR : natural := 16#20#; -- IO expander, slave address is "0100" & A[2:0], A[2:0]= "000"
+ -- temperature sensor, slave address is "0011000"
+ constant I2C_ADU_MAX1617_ADR : natural := MAX1617_ADR_LOW_LOW;
+ -- IO expander, slave address is "0100" & A[2:0], A[2:0]= "000"
+ constant I2C_ADU_PCA9555_ADR : natural := 16#20#;
-- Commander protocol lists for ADU control
diff --git a/libraries/io/i2c/src/vhdl/i2c_dev_ltc4260_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_dev_ltc4260_pkg.vhd
index 1b02b98698c07ce9c2c7e59709df978c441d3c24..d36c2162ac615dea0d91a3161949197737a88fcd 100644
--- a/libraries/io/i2c/src/vhdl/i2c_dev_ltc4260_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_dev_ltc4260_pkg.vhd
@@ -22,8 +22,10 @@
package i2c_dev_ltc4260_pkg is
-- Positive High Voltage Hot Swap Controller with I2C Compatible Monitoring
- constant LTC4260_ADR_MW : natural := 2#1011111#; -- Mass write (broadcast)
- constant LTC4260_ADR_AR : natural := 2#0001100#; -- Alert response
+ -- Mass write (broadcast)
+ constant LTC4260_ADR_MW : natural := 2#1011111#;
+ -- Alert response
+ constant LTC4260_ADR_AR : natural := 2#0001100#;
constant LTC4260_ADR_LOW_LOW_LOW : natural := 2#1000100#;
-- Use SMBUS Write Byte or Read Byte to access the command registers
@@ -35,11 +37,15 @@ package i2c_dev_ltc4260_pkg is
constant LTC4260_CMD_SOURCE : natural := 5;
constant LTC4260_CMD_ADIN : natural := 6;
- constant LTC4260_V_UNIT_SENSE : real := 0.0003; -- 0.3 mV over Rs (e.g. 10 mOhm) for current sense
- constant LTC4260_V_UNIT_SOURCE : real := 0.4; -- 400 mV supply voltage (e.g +48 V)
- constant LTC4260_V_UNIT_ADIN : real := 0.01; -- 10 mV ADC
+ -- 0.3 mV over Rs (e.g. 10 mOhm) for current sense
+ constant LTC4260_V_UNIT_SENSE : real := 0.0003;
+ -- 400 mV supply voltage (e.g +48 V)
+ constant LTC4260_V_UNIT_SOURCE : real := 0.4;
+ -- 10 mV ADC
+ constant LTC4260_V_UNIT_ADIN : real := 0.01;
- constant LTC4260_CONTROL_DEFAULT : natural := 2#00011011#; -- 00 = power good
+ -- 00 = power good
+ constant LTC4260_CONTROL_DEFAULT : natural := 2#00011011#;
-- & 0 = disable test mode
-- & 1 = Enable massa write
-- & 1 = turn FET On
diff --git a/libraries/io/i2c/src/vhdl/i2c_dev_unb2_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_dev_unb2_pkg.vhd
index d5d2e4237df93e7ff9e5d7de9f99aeb2bff2688c..64090a3858eb5603af56449f419ec34209ddce89 100644
--- a/libraries/io/i2c/src/vhdl/i2c_dev_unb2_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_dev_unb2_pkg.vhd
@@ -31,41 +31,66 @@ use work.i2c_commander_pkg.all;
package i2c_dev_unb2_pkg is
-- I2C slave addresses of the devices on the I2C sens bus on UniBoard2
- constant I2C_UNB2_SENS_TEMP_MAX1617_ADR : natural := MAX1617_ADR_MID_LOW; -- temperature sensor, slave address is 0x29
- constant I2C_UNB2_SENS_DCDC_BMR456_ADR : natural := 16#2C#; -- dc/dc converter, slave address is 0x2c
- constant I2C_UNB2_SENS_PIM_PIM4328PD_ADR : natural := 16#2b#; -- power input module, slave address is 0x2b
- constant I2C_UNB2_SENS_1V2_BMR461_ADR : natural := 16#0f#; -- 1.2V power supply, slave address is 0x0f (CHECKED OK: ONLY on FN2)
- constant I2C_UNB2_SENS_3V3_BMR461_ADR : natural := 16#0e#; -- 3.3V power supply, slave address is 0x0e (CHECKED OK: ONLY on FN2)
- constant I2C_UNB2_SENS_CLK_BMR461_ADR : natural := 16#0d#; -- clock power supply, slave address is 0x0d (CHECKED OK: ONLY on FN2)
- constant I2C_UNB2_SENS_QSFP0_BMR464_ADR : natural := 16#01#; -- qsfp0 power supply, slave address is 0x01 (CHECKED OK: ONLY on FN2)
- constant I2C_UNB2_SENS_QSFP1_BMR464_ADR : natural := 16#02#; -- qsfp1 power supply, slave address is 0x02 (CHECKED OK: ONLY on FN2)
- constant I2C_UNB2_SENS_EEPROM_CAT24C02_ADR : natural := 16#50#; -- eeprom , slave address is 0x50 (CHECKED OK: on all nodes)
- constant I2C_UNB2_SENS_TEMP_TMP451_ADR : natural := 16#4c#; -- temperature sensor, slave address is 0x4c (CHECKED OK: ONLY on FN2)
+ -- temperature sensor, slave address is 0x29
+ constant I2C_UNB2_SENS_TEMP_MAX1617_ADR : natural := MAX1617_ADR_MID_LOW;
+ -- dc/dc converter, slave address is 0x2c
+ constant I2C_UNB2_SENS_DCDC_BMR456_ADR : natural := 16#2C#;
+ -- power input module, slave address is 0x2b
+ constant I2C_UNB2_SENS_PIM_PIM4328PD_ADR : natural := 16#2b#;
+ -- 1.2V power supply, slave address is 0x0f (CHECKED OK: ONLY on FN2)
+ constant I2C_UNB2_SENS_1V2_BMR461_ADR : natural := 16#0f#;
+ -- 3.3V power supply, slave address is 0x0e (CHECKED OK: ONLY on FN2)
+ constant I2C_UNB2_SENS_3V3_BMR461_ADR : natural := 16#0e#;
+ -- clock power supply, slave address is 0x0d (CHECKED OK: ONLY on FN2)
+ constant I2C_UNB2_SENS_CLK_BMR461_ADR : natural := 16#0d#;
+ -- qsfp0 power supply, slave address is 0x01 (CHECKED OK: ONLY on FN2)
+ constant I2C_UNB2_SENS_QSFP0_BMR464_ADR : natural := 16#01#;
+ -- qsfp1 power supply, slave address is 0x02 (CHECKED OK: ONLY on FN2)
+ constant I2C_UNB2_SENS_QSFP1_BMR464_ADR : natural := 16#02#;
+ -- eeprom , slave address is 0x50 (CHECKED OK: on all nodes)
+ constant I2C_UNB2_SENS_EEPROM_CAT24C02_ADR : natural := 16#50#;
+ -- temperature sensor, slave address is 0x4c (CHECKED OK: ONLY on FN2)
+ constant I2C_UNB2_SENS_TEMP_TMP451_ADR : natural := 16#4c#;
-- I2C slave addresses of the devices on the I2C pm bus on UniBoard2
- constant I2C_UNB2_PMB_CORE_BMR464_ADR : natural := 16#01#; -- core supply, slave address is 0x01 (CHECKED OK)
- constant I2C_UNB2_PMB_VCCRAM_BMR461_ADR : natural := 16#0d#; -- vcc ram supply, slave address is 0x0d (CHECKED OK)
- constant I2C_UNB2_PMB_TCVR0_BMR461_ADR : natural := 16#0e#; -- transceiver0 supply, slave address is 0x0e (CHECKED OK)
- constant I2C_UNB2_PMB_TCVR1_BMR461_ADR : natural := 16#0f#; -- transceiver1 supply, slave address is 0x0f (CHECKED OK)
- constant I2C_UNB2_PMB_CTRL_BMR461_ADR : natural := 16#10#; -- control supply, slave address is 0x10 (CHECKED OK)
- constant I2C_UNB2_PMB_FPGAIO_BMR461_ADR : natural := 16#11#; -- fpga io supply, slave address is 0x11 (CHECKED OK)
+ -- core supply, slave address is 0x01 (CHECKED OK)
+ constant I2C_UNB2_PMB_CORE_BMR464_ADR : natural := 16#01#;
+ -- vcc ram supply, slave address is 0x0d (CHECKED OK)
+ constant I2C_UNB2_PMB_VCCRAM_BMR461_ADR : natural := 16#0d#;
+ -- transceiver0 supply, slave address is 0x0e (CHECKED OK)
+ constant I2C_UNB2_PMB_TCVR0_BMR461_ADR : natural := 16#0e#;
+ -- transceiver1 supply, slave address is 0x0f (CHECKED OK)
+ constant I2C_UNB2_PMB_TCVR1_BMR461_ADR : natural := 16#0f#;
+ -- control supply, slave address is 0x10 (CHECKED OK)
+ constant I2C_UNB2_PMB_CTRL_BMR461_ADR : natural := 16#10#;
+ -- fpga io supply, slave address is 0x11 (CHECKED OK)
+ constant I2C_UNB2_PMB_FPGAIO_BMR461_ADR : natural := 16#11#;
-- I2C slave addresses of the devices on the I2C ddr4 memory bus on UniBoard2
- constant I2C_UNB2_MB_I_DDR4_ADR : natural := 16#18#; -- ddr4 module I, slave address is 0x18
- constant I2C_UNB2_MB_II_DDR4_ADR : natural := 16#19#; -- ddr4 module II, slave address is 0x19
+ -- ddr4 module I, slave address is 0x18
+ constant I2C_UNB2_MB_I_DDR4_ADR : natural := 16#18#;
+ -- ddr4 module II, slave address is 0x19
+ constant I2C_UNB2_MB_II_DDR4_ADR : natural := 16#19#;
constant c_i2c_unb_temp_high : natural := 85;
-- commands
-- these can later go into device specific packages
- constant PMBUS_REG_READ_VOUT_MODE : natural := 16#20#; -- common to all PMB devices (CHECKED OK)
- constant PMBUS_REG_READ_VIN : natural := 16#88#; -- common to all PMB devices
- constant PMBUS_REG_READ_VCAP : natural := 16#8a#; -- used in the PIM4328PD
- constant PMBUS_REG_READ_VOUT : natural := 16#8b#; -- common to all PMB devices (CHECKED OK)
- constant PMBUS_REG_READ_IOUT : natural := 16#8c#; -- common to all PMB devices (CHECKED OK)
- constant PMBUS_REG_READ_TEMP : natural := 16#8d#; -- common to all PMB devices (CHECKED OK)
+ -- common to all PMB devices (CHECKED OK)
+ constant PMBUS_REG_READ_VOUT_MODE : natural := 16#20#;
+ -- common to all PMB devices
+ constant PMBUS_REG_READ_VIN : natural := 16#88#;
+ -- used in the PIM4328PD
+ constant PMBUS_REG_READ_VCAP : natural := 16#8a#;
+ -- common to all PMB devices (CHECKED OK)
+ constant PMBUS_REG_READ_VOUT : natural := 16#8b#;
+ -- common to all PMB devices (CHECKED OK)
+ constant PMBUS_REG_READ_IOUT : natural := 16#8c#;
+ -- common to all PMB devices (CHECKED OK)
+ constant PMBUS_REG_READ_TEMP : natural := 16#8d#;
- constant c_i2c_unb2_nof_protocol_lists : natural := 4; -- for now we allow four protocol lists for each i2c interface
+ -- for now we allow four protocol lists for each i2c interface
+ constant c_i2c_unb2_nof_protocol_lists : natural := 4;
-- Commander protocol lists for UNB sens bus
diff --git a/libraries/io/i2c/src/vhdl/i2c_dev_unb_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_dev_unb_pkg.vhd
index fd7b8dacf9f1069549faa1b5e7f7eebe9e5cd00d..998d3e31be6d6774ea6c9e1774cc079690281602 100644
--- a/libraries/io/i2c/src/vhdl/i2c_dev_unb_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_dev_unb_pkg.vhd
@@ -29,8 +29,10 @@ use work.i2c_commander_pkg.all;
package i2c_dev_unb_pkg is
-- I2C slave addresses of the devices on the I2C bus on UniBoard
- constant I2C_UNB_MAX1617_ADR : natural := MAX1617_ADR_LOW_LOW; -- temperature sensor, slave address is "0011000"
- constant I2C_UNB_MAX6652_ADR : natural := MAX6652_ADR_GND; -- temperature-voltage sensor, slave address is "0010100"
+ -- temperature sensor, slave address is "0011000"
+ constant I2C_UNB_MAX1617_ADR : natural := MAX1617_ADR_LOW_LOW;
+ -- temperature-voltage sensor, slave address is "0010100"
+ constant I2C_UNB_MAX6652_ADR : natural := MAX6652_ADR_GND;
constant c_i2c_unb_temp_high : natural := 85;
diff --git a/libraries/io/i2c/src/vhdl/i2c_master.vhd b/libraries/io/i2c/src/vhdl/i2c_master.vhd
index 668aea77ac905d5fbf22335b22622944e047bd63..f56b9f509bcec214e2fb7cd482e8635c51f739b1 100644
--- a/libraries/io/i2c/src/vhdl/i2c_master.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_master.vhd
@@ -47,19 +47,22 @@ entity i2c_master is
mms_control_address : in std_logic_vector(g_i2c_mm.control_adr_w - 1 downto 0);
mms_control_write : in std_logic;
mms_control_read : in std_logic;
- mms_control_writedata : in std_logic_vector(c_word_w - 1 downto 0); -- use default MM bus width for control
+ -- use default MM bus width for control
+ mms_control_writedata : in std_logic_vector(c_word_w - 1 downto 0);
mms_control_readdata : out std_logic_vector(c_word_w - 1 downto 0);
-- MM slave I2C protocol register
mms_protocol_address : in std_logic_vector(g_i2c_mm.protocol_adr_w - 1 downto 0);
mms_protocol_write : in std_logic;
mms_protocol_read : in std_logic;
- mms_protocol_writedata : in std_logic_vector(c_byte_w - 1 downto 0); -- define MM bus data has same width as SMBus data
+ -- define MM bus data has same width as SMBus data
+ mms_protocol_writedata : in std_logic_vector(c_byte_w - 1 downto 0);
mms_protocol_readdata : out std_logic_vector(c_byte_w - 1 downto 0);
-- MM slave I2C result register
mms_result_address : in std_logic_vector(g_i2c_mm.result_adr_w - 1 downto 0);
mms_result_write : in std_logic;
mms_result_read : in std_logic;
- mms_result_writedata : in std_logic_vector(c_byte_w - 1 downto 0); -- define MM bus data has same width as SMBus data
+ -- define MM bus data has same width as SMBus data
+ mms_result_writedata : in std_logic_vector(c_byte_w - 1 downto 0);
mms_result_readdata : out std_logic_vector(c_byte_w - 1 downto 0);
-- Interrupt
ins_result_rdy : out std_logic;
@@ -67,8 +70,10 @@ entity i2c_master is
---------------------------------------------------------------------------
-- I2C interface
---------------------------------------------------------------------------
- scl : inout std_logic; -- I2C Serial Clock Line
- sda : inout std_logic -- I2C Serial Data Line
+ -- I2C Serial Clock Line
+ scl : inout std_logic;
+ -- I2C Serial Data Line
+ sda : inout std_logic
);
end i2c_master;
diff --git a/libraries/io/i2c/src/vhdl/i2c_mm.vhd b/libraries/io/i2c/src/vhdl/i2c_mm.vhd
index 08e9d24c2ba9351e92e2c16f06c98eb9a60a68ec..1cf992ebc306118c918a0b84ff07f5abf88c6a2e 100644
--- a/libraries/io/i2c/src/vhdl/i2c_mm.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_mm.vhd
@@ -43,19 +43,22 @@ entity i2c_mm is
mms_control_address : in std_logic_vector(g_i2c_mm.control_adr_w - 1 downto 0);
mms_control_write : in std_logic;
mms_control_read : in std_logic;
- mms_control_writedata : in std_logic_vector(c_word_w - 1 downto 0); -- use default MM bus width for control
+ -- use default MM bus width for control
+ mms_control_writedata : in std_logic_vector(c_word_w - 1 downto 0);
mms_control_readdata : out std_logic_vector(c_word_w - 1 downto 0);
-- MM slave I2C protocol register
mms_protocol_address : in std_logic_vector(g_i2c_mm.protocol_adr_w - 1 downto 0);
mms_protocol_write : in std_logic;
mms_protocol_read : in std_logic;
- mms_protocol_writedata : in std_logic_vector(c_byte_w - 1 downto 0); -- define MM bus data has same width as SMBus data
+ -- define MM bus data has same width as SMBus data
+ mms_protocol_writedata : in std_logic_vector(c_byte_w - 1 downto 0);
mms_protocol_readdata : out std_logic_vector(c_byte_w - 1 downto 0);
-- MM slave I2C result register
mms_result_address : in std_logic_vector(g_i2c_mm.result_adr_w - 1 downto 0);
mms_result_write : in std_logic;
mms_result_read : in std_logic;
- mms_result_writedata : in std_logic_vector(c_byte_w - 1 downto 0); -- define MM bus data has same width as SMBus data
+ -- define MM bus data has same width as SMBus data
+ mms_result_writedata : in std_logic_vector(c_byte_w - 1 downto 0);
mms_result_readdata : out std_logic_vector(c_byte_w - 1 downto 0);
-- Interrupt
ins_result_rdy : out std_logic;
@@ -72,8 +75,10 @@ entity i2c_mm is
result_wr_adr : in std_logic_vector(g_i2c_mm.result_adr_w - 1 downto 0);
result_wr_dat : in std_logic_vector(c_byte_w - 1 downto 0);
- protocol_activate_evt : out std_logic; -- pulse indicating new protocol list
- result_ready_evt : in std_logic -- pulse indicating new result is available
+ -- pulse indicating new protocol list
+ protocol_activate_evt : out std_logic;
+ -- pulse indicating new result is available
+ result_ready_evt : in std_logic
);
end i2c_mm;
@@ -129,7 +134,8 @@ begin
clk => clk,
rst => rst,
switch_high => result_ready_evt,
- switch_low => mms_control_read, -- read clear ready bit
+ -- read clear ready bit
+ switch_low => mms_control_read,
out_level => result_ready
);
diff --git a/libraries/io/i2c/src/vhdl/i2c_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_pkg.vhd
index 12105da3ca31d4726f95e80d4e38b700b81bd2ea..bbc56dbc17efb042d07774a090f48edb5d89bc11 100644
--- a/libraries/io/i2c/src/vhdl/i2c_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_pkg.vhd
@@ -26,14 +26,18 @@ use common_lib.common_pkg.all;
package i2c_pkg is
-- I2C register size settings
--
- constant c_i2c_control_adr_w : natural := 1; -- fixed
- constant c_i2c_protocol_adr_w : natural := 10; -- 2*10 = 1 kByte is sufficient and fits in 1 M9K RAM block
+ -- fixed
+ constant c_i2c_control_adr_w : natural := 1;
+ -- 2*10 = 1 kByte is sufficient and fits in 1 M9K RAM block
+ constant c_i2c_protocol_adr_w : natural := 10;
constant c_i2c_result_adr_w : natural := 10;
- constant c_i2c_dat_w : natural := 8; -- bytes
+ -- bytes
+ constant c_i2c_dat_w : natural := 8;
type t_c_i2c_mm is record
- control_adr_w : natural; -- = 1, fixed
+ -- = 1, fixed
+ control_adr_w : natural;
protocol_adr_w : natural;
protocol_nof_dat : natural;
result_adr_w : natural;
@@ -45,13 +49,17 @@ package i2c_pkg is
-- I2C clock rate and comma time settings
--
type t_c_i2c_phy is record
- clk_cnt : natural; -- minimal clk_cnt >= 2 when comma_w > 0, when comma_w=0 then minimum clk_cnt = 1
- comma_w : natural; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet, 0 for no comma time
+ -- minimal clk_cnt >= 2 when comma_w > 0, when comma_w=0 then minimum clk_cnt = 1
+ clk_cnt : natural;
+ -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet, 0 for no comma time
+ comma_w : natural;
end record;
- constant c_i2c_bit_rate : natural := 50; -- fixed default I2C bit rate in kbps
+ -- fixed default I2C bit rate in kbps
+ constant c_i2c_bit_rate : natural := 50;
constant c_i2c_comma_w_dis : natural := 0;
- constant c_i2c_clk_cnt_sim : natural := 2; -- suits also comma_w > 0
+ -- suits also comma_w > 0
+ constant c_i2c_clk_cnt_sim : natural := 2;
constant c_i2c_phy_sim : t_c_i2c_phy := (1, c_i2c_comma_w_dis);
-- Calculate clk_cnt from system_clock_freq_in_MHz
diff --git a/libraries/io/i2c/src/vhdl/i2c_smbus.vhd b/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
index 725394f4f1118906c9393cbb2c6b9e80320b74d2..2c5e7a8812294a30a85494ece2fb956bc2932636 100644
--- a/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
@@ -89,9 +89,11 @@ architecture rtl of i2c_smbus is
-- Insert comma after start and after each octet to support slow I2C slave
signal scl_cnt : integer range 0 to c_i2c_octet_sz;
signal nxt_scl_cnt : integer range 0 to c_i2c_octet_sz;
- signal scl_m : std_logic; -- master driven scl, used to detect scl edge change independent of slow scl
+ -- master driven scl, used to detect scl edge change independent of slow scl
+ signal scl_m : std_logic;
signal nxt_scl_m : std_logic;
- signal sda_m : std_logic; -- master driven sda, used to detect scl edge change independent of slow sda
+ -- master driven sda, used to detect scl edge change independent of slow sda
+ signal sda_m : std_logic;
signal nxt_sda_m : std_logic;
signal scl_m_dly : std_logic;
signal sda_m_dly : std_logic;
@@ -103,8 +105,10 @@ architecture rtl of i2c_smbus is
signal comma_dly : std_logic;
signal comma_evt : std_logic;
signal comma_sc_low : std_logic;
- signal comma_sc_low_yes : std_logic; -- drives comma_sc_low when comma time is supported
- signal comma_sc_low_no : std_logic; -- drives comma_sc_low when comma time is not supported
+ -- drives comma_sc_low when comma time is supported
+ signal comma_sc_low_yes : std_logic;
+ -- drives comma_sc_low when comma time is not supported
+ signal comma_sc_low_no : std_logic;
signal i2c_start : std_logic;
signal i2c_stop : std_logic;
@@ -153,8 +157,10 @@ begin
scl_oe <= not scl_oen;
sda_oe <= not sda_oen;
- scl <= scl_o when scl_oe_comma_reg = '1' else 'Z'; -- note scl_o is fixed '0' in i2c_bit
- sda <= sda_o when sda_oe_reg = '1' else 'Z'; -- note sda_o is fixed '0' in i2c_bit
+ -- note scl_o is fixed '0' in i2c_bit
+ scl <= scl_o when scl_oe_comma_reg = '1' else 'Z';
+ -- note sda_o is fixed '0' in i2c_bit
+ sda <= sda_o when sda_oe_reg = '1' else 'Z';
-- Use internal scl to avoid edge detection problems in i2c_byte which may occur due to large speed difference
-- between the system clock (200 MHz) and the rising edge of the I2C pull up. This effectively also disables
@@ -184,7 +190,8 @@ begin
srst <= '0' & srst(0 to srst'high - 1);
scl_oe_comma_reg <= scl_oe or comma_sc_low;
sda_oe_reg <= sda_oe;
- sda_i_reg <= sda_i; -- sample SDA line
+ -- sample SDA line
+ sda_i_reg <= sda_i;
end if;
end process;
@@ -287,7 +294,8 @@ begin
p_in => comma_evt,
ep_out => comma_sc_low_yes
);
- end generate; -- gen_comma
+ -- gen_comma
+ end generate;
regs : process(rst, clk)
begin
@@ -384,7 +392,8 @@ begin
when OP_RD_SDA =>
if in_req = '1' then
- nxt_out_err <= not To_X01(sda_i_reg); -- expect pull up
+ -- expect pull up
+ nxt_out_err <= not To_X01(sda_i_reg);
rdy <= '1';
end if;
diff --git a/libraries/io/i2c/src/vhdl/i2c_smbus_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_smbus_pkg.vhd
index be84b90a3d9b57e42166378ca26f4500b1944099..d068dc65eae3d3609ef81b8d782df455a61c0868 100644
--- a/libraries/io/i2c/src/vhdl/i2c_smbus_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_smbus_pkg.vhd
@@ -27,23 +27,39 @@ package i2c_smbus_pkg is
-- Opcodes used in protocol definitions
type OPCODE is (
-- I2C opcodes
- OP_LD_ADR, -- LOAD ADDRESS REGISTER
- OP_LD_CNT, -- LOAD COUNTER REGISTER
- OP_WR_CNT, -- WRITE COUNTER REGISTER
- OP_WR_ADR_WR, -- WRITE ADDRESS FOR WRTTE
- OP_WR_ADR_RD, -- WRITE ADDRESS FOR READ
- OP_WR_DAT, -- WRITE BYTE OF DATA
- OP_WR_BLOCK, -- WRITE BLOCK OF DATA
- OP_RD_ACK, -- READ BYTE OF DATA AND ACKNOWLEDGE
- OP_RD_NACK, -- READ BYTE DATA AND DO NOT ACKNOWLEDGE
- OP_RD_BLOCK, -- READ BLOCK OF DATA
- OP_STOP, -- STOP
+ -- LOAD ADDRESS REGISTER
+ OP_LD_ADR,
+ -- LOAD COUNTER REGISTER
+ OP_LD_CNT,
+ -- WRITE COUNTER REGISTER
+ OP_WR_CNT,
+ -- WRITE ADDRESS FOR WRTTE
+ OP_WR_ADR_WR,
+ -- WRITE ADDRESS FOR READ
+ OP_WR_ADR_RD,
+ -- WRITE BYTE OF DATA
+ OP_WR_DAT,
+ -- WRITE BLOCK OF DATA
+ OP_WR_BLOCK,
+ -- READ BYTE OF DATA AND ACKNOWLEDGE
+ OP_RD_ACK,
+ -- READ BYTE DATA AND DO NOT ACKNOWLEDGE
+ OP_RD_NACK,
+ -- READ BLOCK OF DATA
+ OP_RD_BLOCK,
+ -- STOP
+ OP_STOP,
-- Control opcodes
- OP_IDLE, -- IDLE
- OP_END, -- END OF LIST OF PROTOCOLS
- OP_LD_TIMEOUT, -- LOAD TIMEOUT VALUE
- OP_WAIT, -- WAIT FOR TIMEOUT TIME UNITS
- OP_RD_SDA -- SAMPLE SDA LINE
+ -- IDLE
+ OP_IDLE,
+ -- END OF LIST OF PROTOCOLS
+ OP_END,
+ -- LOAD TIMEOUT VALUE
+ OP_LD_TIMEOUT,
+ -- WAIT FOR TIMEOUT TIME UNITS
+ OP_WAIT,
+ -- SAMPLE SDA LINE
+ OP_RD_SDA
);
-- SMBUS protocol definitions
@@ -148,28 +164,49 @@ package i2c_smbus_pkg is
-- This maps a protocol identifier to the corresponding protocol
constant SMBUS_PROTOCOLS : PROTOCOL_ARRAY := (
-- Official SMBus protocols
- PROTOCOL_RESERVED, -- 00
- PROTOCOL_RESERVED, -- 01
- PROTOCOL_WRITE_QUICK, -- 02
- PROTOCOL_READ_QUICK, -- 03
- PROTOCOL_SEND_BYTE, -- 04
- PROTOCOL_RECEIVE_BYTE, -- 05
- PROTOCOL_WRITE_BYTE, -- 06
- PROTOCOL_READ_BYTE, -- 07
- PROTOCOL_WRITE_WORD, -- 08
- PROTOCOL_READ_WORD, -- 09
- PROTOCOL_WRITE_BLOCK, -- 0A
- PROTOCOL_READ_BLOCK, -- 0B
- PROTOCOL_PROCESS_CALL, -- 0C
+ -- 00
+ PROTOCOL_RESERVED,
+ -- 01
+ PROTOCOL_RESERVED,
+ -- 02
+ PROTOCOL_WRITE_QUICK,
+ -- 03
+ PROTOCOL_READ_QUICK,
+ -- 04
+ PROTOCOL_SEND_BYTE,
+ -- 05
+ PROTOCOL_RECEIVE_BYTE,
+ -- 06
+ PROTOCOL_WRITE_BYTE,
+ -- 07
+ PROTOCOL_READ_BYTE,
+ -- 08
+ PROTOCOL_WRITE_WORD,
+ -- 09
+ PROTOCOL_READ_WORD,
+ -- 0A
+ PROTOCOL_WRITE_BLOCK,
+ -- 0B
+ PROTOCOL_READ_BLOCK,
+ -- 0C
+ PROTOCOL_PROCESS_CALL,
-- Additional custom protocols
- PROTOCOL_C_WRITE_BLOCK_NO_CNT, -- 0D
- PROTOCOL_C_READ_BLOCK_NO_CNT, -- 0E
- PROTOCOL_C_SEND_BLOCK, -- 0F
- PROTOCOL_C_RECEIVE_BLOCK, -- 10
- PROTOCOL_C_NOP, -- 11
- PROTOCOL_C_WAIT, -- 12
- PROTOCOL_C_END, -- 13
- PROTOCOL_C_SAMPLE_SDA -- 14
+ -- 0D
+ PROTOCOL_C_WRITE_BLOCK_NO_CNT,
+ -- 0E
+ PROTOCOL_C_READ_BLOCK_NO_CNT,
+ -- 0F
+ PROTOCOL_C_SEND_BLOCK,
+ -- 10
+ PROTOCOL_C_RECEIVE_BLOCK,
+ -- 11
+ PROTOCOL_C_NOP,
+ -- 12
+ PROTOCOL_C_WAIT,
+ -- 13
+ PROTOCOL_C_END,
+ -- 14
+ PROTOCOL_C_SAMPLE_SDA
);
-- SMBUS protocol identifiers.
@@ -197,9 +234,12 @@ package i2c_smbus_pkg is
constant SMBUS_C_END : natural := 16#13#;
constant SMBUS_C_SAMPLE_SDA : natural := 16#14#;
- constant c_smbus_unknown_protocol : natural := 16#14#; -- Equal to largest valid SMBUS protocol ID
+ -- Equal to largest valid SMBUS protocol ID
+ constant c_smbus_unknown_protocol : natural := 16#14#;
- constant c_smbus_timeout_nof_byte : natural := 4; -- Four byte timeout value set via OP_LD_TIMEOUT
+ -- Four byte timeout value set via OP_LD_TIMEOUT
+ constant c_smbus_timeout_nof_byte : natural := 4;
constant c_smbus_timeout_word_w : natural := c_smbus_timeout_nof_byte * 8;
- constant c_smbus_timeout_w : natural := 28; -- Only use 28 bits for actual timeout counter, 2^28 > 200M cycles in 1 sec
+ -- Only use 28 bits for actual timeout counter, 2^28 > 200M cycles in 1 sec
+ constant c_smbus_timeout_w : natural := 28;
end package;
diff --git a/libraries/io/i2c/src/vhdl/i2cslave.vhd b/libraries/io/i2c/src/vhdl/i2cslave.vhd
index 47e65a0c3ec93cb3272c7a7eed7685bbc2065eaf..e0f1e585e82ccaef3cd87a4859ff278b61d2d649 100644
--- a/libraries/io/i2c/src/vhdl/i2cslave.vhd
+++ b/libraries/io/i2c/src/vhdl/i2cslave.vhd
@@ -30,16 +30,24 @@ use ieee.std_logic_arith.all;
entity i2cslave is
generic (
- g_rx_filter : boolean := true; -- when TRUE enable I2C input SCL/SDA signal filtering
- g_address : std_logic_vector(6 downto 0) := "0000001"; -- Slave I2C address
- g_nof_ctrl_bytes : natural := 3 -- size of control register in bytes
+ -- when TRUE enable I2C input SCL/SDA signal filtering
+ g_rx_filter : boolean := true;
+ -- Slave I2C address
+ g_address : std_logic_vector(6 downto 0) := "0000001";
+ -- size of control register in bytes
+ g_nof_ctrl_bytes : natural := 3
);
port(
- clk : in std_logic; -- system clock (clk freq >> SCL freq)
- SDA : inout std_logic; -- I2C Serial Data Line
- SCL : in std_logic; -- I2C Serial Clock Line
- RST : in std_logic; -- optional reset bit
- CTRL_REG : out std_logic_vector(8 * g_nof_ctrl_bytes - 1 downto 0) -- ctrl for RCU control
+ -- system clock (clk freq >> SCL freq)
+ clk : in std_logic;
+ -- I2C Serial Data Line
+ SDA : inout std_logic;
+ -- I2C Serial Clock Line
+ SCL : in std_logic;
+ -- optional reset bit
+ RST : in std_logic;
+ -- ctrl for RCU control
+ CTRL_REG : out std_logic_vector(8 * g_nof_ctrl_bytes - 1 downto 0)
);
end i2cslave;
@@ -58,9 +66,12 @@ architecture rtl of i2cslave is
type state is (reset,read_addr,read_data,write_data,acknowledge,nacknowledge,wacknowledge,wnacknowledge);
-- Start of g_rx_filter related declarations
- constant c_meta_len : natural := 3; -- use 3 FF to tackle meta stability between SCL and clk domain
- constant c_clk_cnt_w : natural := 5; -- use lower effective clk rate
- constant c_line_len : natural := 7; -- use FF line to filter SCL
+ -- use 3 FF to tackle meta stability between SCL and clk domain
+ constant c_meta_len : natural := 3;
+ -- use lower effective clk rate
+ constant c_clk_cnt_w : natural := 5;
+ -- use FF line to filter SCL
+ constant c_line_len : natural := 7;
-- The maximum bit rate is 100 kbps, so 10 us SCL period. The pullup rise time
-- of SCL and SDA is worst case (10k pullup) about 2 us, so a line_len of about
-- 1 us suffices. At 200 MHz the line covers is 2^5 * 7 * 5 ns = 1.12 us of SCL,
@@ -98,21 +109,32 @@ architecture rtl of i2cslave is
signal start : std_logic;
signal stop : std_logic;
- signal streset : std_logic; -- bit to reset the start and stop flip flops
+ -- bit to reset the start and stop flip flops
+ signal streset : std_logic;
signal latch_ctrl : std_logic;
signal latch_ctrl_dly : std_logic;
- signal ctrl_tmp : std_logic_vector(8 * g_nof_ctrl_bytes - 1 downto 0); -- register to read and write to temporarily
- signal i_ctrl_reg : std_logic_vector(8 * g_nof_ctrl_bytes - 1 downto 0); -- output register
- signal rw : std_logic; -- bit to indicate a read or a write
- signal ctrladr : std_logic_vector(6 downto 0); -- I2C address register
- signal bitcnt : natural range 0 to 7; -- bitcnt for reading bits
- signal bytecnt : natural range 0 to g_nof_ctrl_bytes - 1; -- bytenct for reading bytes
+ -- register to read and write to temporarily
+ signal ctrl_tmp : std_logic_vector(8 * g_nof_ctrl_bytes - 1 downto 0);
+ -- output register
+ signal i_ctrl_reg : std_logic_vector(8 * g_nof_ctrl_bytes - 1 downto 0);
+ -- bit to indicate a read or a write
+ signal rw : std_logic;
+ -- I2C address register
+ signal ctrladr : std_logic_vector(6 downto 0);
+ -- bitcnt for reading bits
+ signal bitcnt : natural range 0 to 7;
+ -- bytenct for reading bytes
+ signal bytecnt : natural range 0 to g_nof_ctrl_bytes - 1;
signal current_state : state;
- signal tri_en : std_logic; -- signal to enable the tristate buffer for the SDA line
- signal sda_int : std_logic; -- internal SDA line to drive the SDA pin
- signal wbitcnt : natural range 0 to 8; -- bitcnt for writing bits
- signal wbytecnt : natural range 0 to g_nof_ctrl_bytes - 1; -- bytenct for writing bytes
+ -- signal to enable the tristate buffer for the SDA line
+ signal tri_en : std_logic;
+ -- internal SDA line to drive the SDA pin
+ signal sda_int : std_logic;
+ -- bitcnt for writing bits
+ signal wbitcnt : natural range 0 to 8;
+ -- bytenct for writing bytes
+ signal wbytecnt : natural range 0 to g_nof_ctrl_bytes - 1;
signal zeroedge_state : state;
begin
CTRL_REG <= i_ctrl_reg;
@@ -207,7 +229,8 @@ begin
end if;
end process;
- control: process(RST, scl_rx) -- i2c slave
+ -- i2c slave
+ control: process(RST, scl_rx)
begin
if RST = '1' then
--reset input connected to bit 17 of CTRL register, hence default for CTRL[17] must be '0' so RST will act as a spike.
@@ -246,7 +269,8 @@ begin
-- Latch CTRL register
latch_ctrl_dly <= latch_ctrl;
- if latch_ctrl_dly = '1' then -- latch ctrl register after ack
+ -- latch ctrl register after ack
+ if latch_ctrl_dly = '1' then
i_ctrl_reg <= ctrl_tmp;
i_ctrl_reg(23 downto 20) <= c_version;
end if;
@@ -258,25 +282,32 @@ begin
bitcnt <= 0;
current_state <= zeroedge_state;
if start = '1' then
- streset <= '1'; -- reset start bit
- ctrladr <= ctrladr(5 downto 0) & sda_rx; -- first commands of read_addr state should immediately be executed
+ -- reset start bit
+ streset <= '1';
+ -- first commands of read_addr state should immediately be executed
+ ctrladr <= ctrladr(5 downto 0) & sda_rx;
bitcnt <= 1;
bytecnt <= 0;
current_state <= read_addr;
- elsif stop = '1' then -- only recognized if there occurs an SCL edge between I2C Stop and Start
- streset <= '1'; -- reset stop bit
+ -- only recognized if there occurs an SCL edge between I2C Stop and Start
+ elsif stop = '1' then
+ -- reset stop bit
+ streset <= '1';
bytecnt <= 0;
current_state <= reset;
else
case zeroedge_state is
- when reset => null; -- only a Start gets the statemachines out of reset, all SCL edges are ignored until then
+ -- only a Start gets the statemachines out of reset, all SCL edges are ignored until then
+ when reset => null;
when read_addr =>
if bitcnt < 7 then
- ctrladr <= ctrladr(5 downto 0) & sda_rx; -- shift the data to the left
+ -- shift the data to the left
+ ctrladr <= ctrladr(5 downto 0) & sda_rx;
--shift a new bit in (MSB first)
bitcnt <= bitcnt + 1;
else
- rw <= sda_rx; -- last bit indicates a read or a write
+ -- last bit indicates a read or a write
+ rw <= sda_rx;
if ctrladr = g_address then
current_state <= acknowledge;
else
@@ -285,25 +316,37 @@ begin
end if;
when read_data =>
if bitcnt < 7 then
- ctrl_tmp(8 * g_nof_ctrl_bytes - 1 downto 1) <= ctrl_tmp(8 * g_nof_ctrl_bytes - 2 downto 0); -- shift the data to the left
- ctrl_tmp(0) <= sda_rx; -- shift a new bit in (MSB first)
+ -- shift the data to the left
+ ctrl_tmp(8 * g_nof_ctrl_bytes - 1 downto 1) <= ctrl_tmp(8 * g_nof_ctrl_bytes - 2 downto 0);
+ -- shift a new bit in (MSB first)
+ ctrl_tmp(0) <= sda_rx;
bitcnt <= bitcnt + 1;
- else -- reading the last bit and going immediately to the ack state
- ctrl_tmp(8 * g_nof_ctrl_bytes - 1 downto 1) <= ctrl_tmp(8 * g_nof_ctrl_bytes - 2 downto 0); -- shift the data to the left
- ctrl_tmp(0) <= sda_rx; -- shift a new bit in (MSB first)
- if bytecnt < g_nof_ctrl_bytes - 1 then -- first bytes
+ -- reading the last bit and going immediately to the ack state
+ else
+ -- shift the data to the left
+ ctrl_tmp(8 * g_nof_ctrl_bytes - 1 downto 1) <= ctrl_tmp(8 * g_nof_ctrl_bytes - 2 downto 0);
+ -- shift a new bit in (MSB first)
+ ctrl_tmp(0) <= sda_rx;
+ -- first bytes
+ if bytecnt < g_nof_ctrl_bytes - 1 then
bytecnt <= bytecnt + 1;
- current_state <= acknowledge; -- acknowledge the successfull read of a byte
- else -- last byte
- latch_ctrl <= '1'; -- latch at g_nof_ctrl_bytes-th byte (or a multiple of that, due to bytecnt wrap)
- bytecnt <= 0; -- wrap byte count
- current_state <= acknowledge; -- acknowledge also for the last byte
+ -- acknowledge the successfull read of a byte
+ current_state <= acknowledge;
+ -- last byte
+ else
+ -- latch at g_nof_ctrl_bytes-th byte (or a multiple of that, due to bytecnt wrap)
+ latch_ctrl <= '1';
+ -- wrap byte count
+ bytecnt <= 0;
+ -- acknowledge also for the last byte
+ current_state <= acknowledge;
end if;
end if;
when write_data => null;
when acknowledge =>
if rw = '0' then
- current_state <= read_data; -- acknowledge state is one clock period active
+ -- acknowledge state is one clock period active
+ current_state <= read_data;
else
current_state <= write_data;
end if;
@@ -313,21 +356,25 @@ begin
--reached.
when wacknowledge =>
if sda_rx = '0' then
- current_state <= write_data; -- write went OK, continue writing bytes to the master
+ -- write went OK, continue writing bytes to the master
+ current_state <= write_data;
else
- current_state <= reset; -- write failed, so abort the transfer
+ -- write failed, so abort the transfer
+ current_state <= reset;
end if;
when wnacknowledge =>
--NACK is used to signal the end of a master read access. The slave can not known whether
--the write transfer to the master was succesful and it does not need to know anyway.
if sda_rx = '1' then
- current_state <= reset; -- last write went OK, no more bytes to write to the master
+ -- last write went OK, no more bytes to write to the master
+ current_state <= reset;
else
--By making current_state <= reset the CTRL register can only be read once in one transfer.
--If more bytes are read then the master will see them as 0xFF (due to SDA pull up). By
--making current_state <= write_data the CTRL register wraps if it is read more than once.
--current_state <= reset; --last write went OK, abort further transfer
- current_state <= write_data; -- last write went OK, wrap and continue writing bytes to the master
+ -- last write went OK, wrap and continue writing bytes to the master
+ current_state <= write_data;
end if;
when others =>
current_state <= reset;
@@ -345,7 +392,8 @@ begin
if start = '1' then
wbytecnt <= 0;
zeroedge_state <= reset;
- elsif stop = '1' then -- only recognized if there occurs an SCL edge between I2C Stop and Start
+ -- only recognized if there occurs an SCL edge between I2C Stop and Start
+ elsif stop = '1' then
wbytecnt <= 0;
zeroedge_state <= reset;
else
@@ -355,23 +403,32 @@ begin
when read_data => null;
when write_data =>
if wbitcnt < 8 then
- tri_en <= '1'; -- enable tri-state buffer to write SDA
+ -- enable tri-state buffer to write SDA
+ tri_en <= '1';
if i_ctrl_reg(8 * g_nof_ctrl_bytes - 1 - (8 * wbytecnt + wbitcnt)) = '0' then
- sda_int <= '0'; -- copy one bit to SDA (MSB first), else default to 'H'
+ -- copy one bit to SDA (MSB first), else default to 'H'
+ sda_int <= '0';
end if;
wbitcnt <= wbitcnt + 1;
else
- if wbytecnt < g_nof_ctrl_bytes - 1 then -- first bytes
+ -- first bytes
+ if wbytecnt < g_nof_ctrl_bytes - 1 then
wbytecnt <= wbytecnt + 1;
- zeroedge_state <= wacknowledge; -- wait till master acknowledges the successfull read of a byte
- else -- last byte
- wbytecnt <= 0; -- wrap byte count
- zeroedge_state <= wnacknowledge; -- wait till master nacknowledges the successfull read of a byte
+ -- wait till master acknowledges the successfull read of a byte
+ zeroedge_state <= wacknowledge;
+ -- last byte
+ else
+ -- wrap byte count
+ wbytecnt <= 0;
+ -- wait till master nacknowledges the successfull read of a byte
+ zeroedge_state <= wnacknowledge;
end if;
end if;
when acknowledge =>
- tri_en <= '1'; -- enable tri-state buffer to write SDA
- sda_int <= '0'; -- acknowledge data
+ -- enable tri-state buffer to write SDA
+ tri_en <= '1';
+ -- acknowledge data
+ sda_int <= '0';
when nacknowledge => null;
--This state is never reached.
--To answer an NACK the tri_en can remain '0', because the default SDA is 'H' due to the pull up.
diff --git a/libraries/io/i2c/tb/vhdl/dev_ltc4260.vhd b/libraries/io/i2c/tb/vhdl/dev_ltc4260.vhd
index 923f63a046590863e439fcbab87bf005333c3dde..1744175d6cb4723d1c54b3c442263505ae3bd329 100644
--- a/libraries/io/i2c/tb/vhdl/dev_ltc4260.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_ltc4260.vhd
@@ -27,11 +27,13 @@ use work.i2c_dev_ltc4260_pkg.all;
entity dev_ltc4260 is
generic(
- g_address : std_logic_vector(c_byte_w - 2 downto 0); -- 7 bit address, so without R/Wn bit
+ -- 7 bit address, so without R/Wn bit
+ g_address : std_logic_vector(c_byte_w - 2 downto 0);
g_R_sense : real := 0.01
);
port(
- scl : inout std_logic := 'H'; -- Default output 'H' (instead of 'X' !)
+ -- Default output 'H' (instead of 'X' !)
+ scl : inout std_logic := 'H';
sda : inout std_logic;
ana_current_sense : in real;
ana_volt_source : in real;
@@ -41,7 +43,8 @@ end dev_ltc4260;
architecture beh of dev_ltc4260 is
-- Convert V sense into I sense
- constant c_I_unit_sense : real := LTC4260_V_UNIT_SENSE / g_R_sense; -- = 0.3 mV / 10 mOhm
+ -- = 0.3 mV / 10 mOhm
+ constant c_I_unit_sense : real := LTC4260_V_UNIT_SENSE / g_R_sense;
-- Digitized values
signal dig_current_sense : integer;
@@ -49,22 +52,29 @@ architecture beh of dev_ltc4260 is
signal dig_volt_adin : integer;
-- I2C control
- signal enable : std_logic; -- new access, may be write command or write data
- signal stop : std_logic; -- end of access
- signal wr_dat : std_logic_vector(c_byte_w - 1 downto 0); -- I2C write data
+ -- new access, may be write command or write data
+ signal enable : std_logic;
+ -- end of access
+ signal stop : std_logic;
+ -- I2C write data
+ signal wr_dat : std_logic_vector(c_byte_w - 1 downto 0);
signal wr_val : std_logic;
- signal rd_dat : std_logic_vector(c_byte_w - 1 downto 0); -- I2C read data
+ -- I2C read data
+ signal rd_dat : std_logic_vector(c_byte_w - 1 downto 0);
signal rd_req : std_logic;
signal cmd_en : std_logic := '0';
- signal cmd : std_logic_vector(c_byte_w - 1 downto 0); -- device command
+ -- device command
+ signal cmd : std_logic_vector(c_byte_w - 1 downto 0);
-- LTC4260 registers (with power up defaults)
signal control_reg : std_logic_vector(c_byte_w - 1 downto 0) := std_logic_vector(to_unsigned(LTC4260_CONTROL_DEFAULT, c_byte_w));
begin
-- Digitize the measured current and voltages
- dig_current_sense <= integer(ana_current_sense / c_I_unit_sense); -- e.g. 5.0 A / 0.03 = 166
- dig_volt_source <= integer(ana_volt_source / LTC4260_V_UNIT_SOURCE); -- e.g. 48.0 V / 0.4 = 120
+ -- e.g. 5.0 A / 0.03 = 166
+ dig_current_sense <= integer(ana_current_sense / c_I_unit_sense);
+ -- e.g. 48.0 V / 0.4 = 120
+ dig_volt_source <= integer(ana_volt_source / LTC4260_V_UNIT_SOURCE);
dig_volt_adin <= integer(ana_volt_adin / LTC4260_V_UNIT_ADIN);
i2c_slv_device : entity work.i2c_slv_device
@@ -83,7 +93,8 @@ begin
);
-- Support PROTOCOL_WRITE_BYTE
- p_write : process (enable, wr_val) -- first write byte is treated as command
+ -- first write byte is treated as command
+ p_write : process (enable, wr_val)
begin
if rising_edge(enable) then
cmd_en <= '1';
@@ -97,7 +108,8 @@ begin
else
case to_integer(unsigned(cmd)) is
when LTC4260_CMD_CONTROL => control_reg <= wr_dat;
- when others => null; -- no further model for write access
+ -- no further model for write access
+ when others => null;
end case;
end if;
end if;
@@ -107,7 +119,8 @@ begin
p_read : process (rd_req)
begin
if rising_edge(rd_req) then
- case to_integer(unsigned(cmd)) is -- only model read I and V
+ -- only model read I and V
+ case to_integer(unsigned(cmd)) is
when LTC4260_CMD_CONTROL => rd_dat <= control_reg;
when LTC4260_CMD_ALERT => rd_dat <= (others => '1');
when LTC4260_CMD_STATUS => rd_dat <= (others => '1');
diff --git a/libraries/io/i2c/tb/vhdl/dev_max1618.vhd b/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
index 1b7e84b0e8f82a03c95af3a162dea3c0205b92c6..2328235b5d05289139ec3ac05553ba7a7d727bd4 100644
--- a/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
@@ -36,15 +36,20 @@ entity dev_max1618 is
end dev_max1618;
architecture beh of dev_max1618 is
- signal enable : std_logic; -- enable
- signal stop : std_logic; -- stop
- signal wr_dat : std_logic_vector(7 downto 0); -- I2C write data
+ -- enable
+ signal enable : std_logic;
+ -- stop
+ signal stop : std_logic;
+ -- I2C write data
+ signal wr_dat : std_logic_vector(7 downto 0);
signal wr_val : std_logic;
- signal rd_dat : std_logic_vector(7 downto 0); -- I2C read data
+ -- I2C read data
+ signal rd_dat : std_logic_vector(7 downto 0);
signal rd_req : std_logic;
signal cmd_en : std_logic := '0';
- signal cmd : natural; -- device command
+ -- device command
+ signal cmd : natural;
signal config_reg : std_logic_vector(7 downto 0) := "00001000";
signal status_reg : std_logic_vector(7 downto 0) := (others => '0');
@@ -67,10 +72,13 @@ begin
);
-- Model only config thermostat mode
- status_reg(MAX1617_STATUS_RHIGH_BI) <= '1' when temp >= unsigned(temp_hi_reg) else '0' when temp <= unsigned(temp_lo_reg); -- ELSE latch
- status_reg(MAX1617_STATUS_RLOW_BI) <= '1' when temp <= unsigned(temp_lo_reg) else '0' when temp >= unsigned(temp_hi_reg); -- ELSE latch
+ -- ELSE latch
+ status_reg(MAX1617_STATUS_RHIGH_BI) <= '1' when temp >= unsigned(temp_hi_reg) else '0' when temp <= unsigned(temp_lo_reg);
+ -- ELSE latch
+ status_reg(MAX1617_STATUS_RLOW_BI) <= '1' when temp <= unsigned(temp_lo_reg) else '0' when temp >= unsigned(temp_hi_reg);
- p_write : process (enable, wr_val) -- first write byte is treated as command
+ -- first write byte is treated as command
+ p_write : process (enable, wr_val)
begin
if rising_edge(enable) then
cmd_en <= '1';
@@ -82,7 +90,8 @@ begin
if cmd_en = '1' then
cmd <= to_integer(unsigned(wr_dat));
else
- case cmd is -- only model some write cmd
+ -- only model some write cmd
+ case cmd is
when MAX1617_CMD_WRITE_CONFIG => config_reg <= wr_dat;
when MAX1617_CMD_WRITE_REMOTE_HIGH => temp_hi_reg <= wr_dat;
when MAX1617_CMD_WRITE_REMOTE_LOW => temp_lo_reg <= wr_dat;
@@ -95,7 +104,8 @@ begin
p_read : process (rd_req)
begin
if rising_edge(rd_req) then
- case cmd is -- only model some read cmd
+ -- only model some read cmd
+ case cmd is
when MAX1617_CMD_READ_REMOTE_TEMP => rd_dat <= std_logic_vector(to_signed(temp,8));
when MAX1617_CMD_READ_CONFIG => rd_dat <= config_reg;
when MAX1617_CMD_READ_STATUS => rd_dat <= status_reg;
diff --git a/libraries/io/i2c/tb/vhdl/dev_max6652.vhd b/libraries/io/i2c/tb/vhdl/dev_max6652.vhd
index 02ddc416d49acd6c94d6e782d873cfe966bb4670..c94b88a76929c450040bcf6a1097f277798bb477 100644
--- a/libraries/io/i2c/tb/vhdl/dev_max6652.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_max6652.vhd
@@ -30,11 +30,16 @@ entity dev_max6652 is
port(
scl : in std_logic;
sda : inout std_logic;
- volt_2v5 : in integer; -- unit 13 mV
- volt_3v3 : in integer; -- unit 17 mV
- volt_12v : in integer; -- unit 62 mV
- volt_vcc : in integer; -- unit 26 mV
- temp : in integer -- unit degrees C
+ -- unit 13 mV
+ volt_2v5 : in integer;
+ -- unit 17 mV
+ volt_3v3 : in integer;
+ -- unit 62 mV
+ volt_12v : in integer;
+ -- unit 26 mV
+ volt_vcc : in integer;
+ -- unit degrees C
+ temp : in integer
);
end dev_max6652;
@@ -46,15 +51,20 @@ architecture beh of dev_max6652 is
constant c_cmd_read_temp : std_logic_vector(7 downto 0) := "00100111";
constant c_cmd_config : std_logic_vector(7 downto 0) := "01000000";
- signal enable : std_logic; -- new access, may be write command or write data
- signal stop : std_logic; -- end of access
- signal wr_dat : std_logic_vector(7 downto 0); -- I2C write data
+ -- new access, may be write command or write data
+ signal enable : std_logic;
+ -- end of access
+ signal stop : std_logic;
+ -- I2C write data
+ signal wr_dat : std_logic_vector(7 downto 0);
signal wr_val : std_logic;
- signal rd_dat : std_logic_vector(7 downto 0); -- I2C read data
+ -- I2C read data
+ signal rd_dat : std_logic_vector(7 downto 0);
signal rd_req : std_logic;
signal cmd_en : std_logic := '0';
- signal cmd : std_logic_vector(7 downto 0); -- device command
+ -- device command
+ signal cmd : std_logic_vector(7 downto 0);
signal config_reg : std_logic_vector(7 downto 0) := "00001000";
begin
i2c_slv_device : entity work.i2c_slv_device
@@ -72,7 +82,8 @@ begin
rd_dat => rd_dat
);
- p_write : process (enable, wr_val) -- first write byte is treated as command
+ -- first write byte is treated as command
+ p_write : process (enable, wr_val)
begin
if rising_edge(enable) then
cmd_en <= '1';
@@ -86,7 +97,8 @@ begin
else
case cmd is
when c_cmd_config => config_reg <= wr_dat;
- when others => null; -- no further model for write access
+ -- no further model for write access
+ when others => null;
end case;
end if;
end if;
@@ -95,7 +107,8 @@ begin
p_read : process (rd_req)
begin
if rising_edge(rd_req) then
- case cmd is -- only model read V and read temp
+ -- only model read V and read temp
+ case cmd is
when c_cmd_read_2v5 => rd_dat <= std_logic_vector(to_unsigned(volt_2v5,8));
when c_cmd_read_12v => rd_dat <= std_logic_vector(to_unsigned(volt_12v,8));
when c_cmd_read_3v3 => rd_dat <= std_logic_vector(to_unsigned(volt_3v3,8));
diff --git a/libraries/io/i2c/tb/vhdl/dev_pca9555.vhd b/libraries/io/i2c/tb/vhdl/dev_pca9555.vhd
index d80181f2f455acf898bb0af163d696899f32f2f7..787b8c6def05b494d756a42a21e445af58b6202e 100644
--- a/libraries/io/i2c/tb/vhdl/dev_pca9555.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_pca9555.vhd
@@ -25,7 +25,8 @@ use IEEE.numeric_std.all;
entity dev_pca9555 is
generic(
- g_address : std_logic_vector(6 downto 0) -- PCA9555 slave address is "0100" & A2 & A1 & A0
+ -- PCA9555 slave address is "0100" & A2 & A1 & A0
+ g_address : std_logic_vector(6 downto 0)
);
port(
scl : in std_logic;
@@ -45,18 +46,25 @@ architecture beh of dev_pca9555 is
constant c_cmd_config_0 : natural := 6;
constant c_cmd_config_1 : natural := 7;
- signal enable : std_logic; -- new access, may be write command or write data
- signal stop : std_logic; -- end of access
- signal wr_dat : std_logic_vector(7 downto 0); -- I2C write data
+ -- new access, may be write command or write data
+ signal enable : std_logic;
+ -- end of access
+ signal stop : std_logic;
+ -- I2C write data
+ signal wr_dat : std_logic_vector(7 downto 0);
signal wr_val : std_logic;
- signal rd_dat : std_logic_vector(7 downto 0); -- I2C read data
+ -- I2C read data
+ signal rd_dat : std_logic_vector(7 downto 0);
signal rd_req : std_logic;
signal cmd_en : std_logic := '0';
- signal wr_cmd : natural; -- device write command
- signal rd_cmd : natural; -- device read command
+ -- device write command
+ signal wr_cmd : natural;
+ -- device read command
+ signal rd_cmd : natural;
- signal input_reg0 : std_logic_vector(7 downto 0); -- device registers with powerup default value
+ -- device registers with powerup default value
+ signal input_reg0 : std_logic_vector(7 downto 0);
signal input_reg1 : std_logic_vector(7 downto 0);
signal output_reg0 : std_logic_vector(7 downto 0) := (others => '1');
signal output_reg1 : std_logic_vector(7 downto 0) := (others => '1');
diff --git a/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd b/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
index 65a3f2c7bcfd3786a0b46597a5911e9d03c716a1..1d429d4ab5c41cfa9ccf960208a0def8074f00c1 100644
--- a/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
@@ -41,15 +41,20 @@ entity dev_pmbus is
end dev_pmbus;
architecture beh of dev_pmbus is
- signal enable : std_logic; -- enable
- signal stop : std_logic; -- stop
- signal wr_dat : std_logic_vector(7 downto 0); -- I2C write data
+ -- enable
+ signal enable : std_logic;
+ -- stop
+ signal stop : std_logic;
+ -- I2C write data
+ signal wr_dat : std_logic_vector(7 downto 0);
signal wr_val : std_logic;
- signal rd_dat : std_logic_vector(7 downto 0); -- I2C read data
+ -- I2C read data
+ signal rd_dat : std_logic_vector(7 downto 0);
signal rd_req : std_logic;
signal cmd_en : std_logic := '0';
- signal cmd : natural; -- device command
+ -- device command
+ signal cmd : natural;
signal config_reg : std_logic_vector(7 downto 0) := "00001000";
signal status_reg : std_logic_vector(7 downto 0) := (others => '0');
@@ -71,7 +76,8 @@ begin
rd_dat => rd_dat
);
- p_write : process (enable, wr_val) -- first write byte is treated as command
+ -- first write byte is treated as command
+ p_write : process (enable, wr_val)
begin
if rising_edge(enable) then
cmd_en <= '1';
@@ -83,7 +89,8 @@ begin
if cmd_en = '1' then
cmd <= to_integer(unsigned(wr_dat));
else
- case cmd is -- add write cmd later
+ -- add write cmd later
+ case cmd is
when others => null;
end case;
end if;
@@ -93,7 +100,8 @@ begin
p_read : process (rd_req)
begin
if rising_edge(rd_req) then
- case cmd is -- only model some read cmd
+ -- only model some read cmd
+ case cmd is
when PMBUS_REG_READ_VOUT_MODE => rd_dat <= std_logic_vector(to_signed(vout_mode,8));
when PMBUS_REG_READ_VIN => rd_dat <= std_logic_vector(to_signed(vin,8));
when PMBUS_REG_READ_VOUT => rd_dat <= std_logic_vector(to_signed(vout,8));
diff --git a/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd b/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
index 89472e640474856072cbbdda960b356f12ff9f69..60dc0230ef907a55e14f7981b1d82311256bc79e 100644
--- a/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
+++ b/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
@@ -25,16 +25,23 @@ use IEEE.std_logic_arith.all;
entity i2c_slv_device is
generic (
- g_address : std_logic_vector(6 downto 0) -- Slave I2C address
+ -- Slave I2C address
+ g_address : std_logic_vector(6 downto 0)
);
port (
- scl : in std_logic; -- I2C Serial Clock Line
- sda : inout std_logic; -- I2C Serial Data Line
- en : out std_logic; -- '1' : new access, wr_dat may be a cmd byte, '0' : wr_dat is a data byte,
- p : out std_logic; -- rising edge indicates end of access (stop)
+ -- I2C Serial Clock Line
+ scl : in std_logic;
+ -- I2C Serial Data Line
+ sda : inout std_logic;
+ -- '1' : new access, wr_dat may be a cmd byte, '0' : wr_dat is a data byte,
+ en : out std_logic;
+ -- rising edge indicates end of access (stop)
+ p : out std_logic;
wr_dat : out std_logic_vector(7 downto 0);
- wr_val : out std_logic; -- rising edge indicates valid wr_dat
- rd_req : out std_logic; -- rising edge request new rd_dat
+ -- rising edge indicates valid wr_dat
+ wr_val : out std_logic;
+ -- rising edge request new rd_dat
+ rd_req : out std_logic;
rd_dat : in std_logic_vector(7 downto 0)
);
end i2c_slv_device;
@@ -62,37 +69,59 @@ architecture beh of i2c_slv_device is
ST_READ_DATA
);
- signal rs : std_logic; -- behavioral restart
- signal prev_rw : std_logic := '0'; -- behavioral
- signal rd_first : std_logic := '0'; -- behavioral
- signal rd_next : std_logic := '0'; -- behavioral
- signal dev_state : t_dev_state := ST_IDLE; -- behavioral
+ -- behavioral restart
+ signal rs : std_logic;
+ -- behavioral
+ signal prev_rw : std_logic := '0';
+ -- behavioral
+ signal rd_first : std_logic := '0';
+ -- behavioral
+ signal rd_next : std_logic := '0';
+ -- behavioral
+ signal dev_state : t_dev_state := ST_IDLE;
type state is (reset,read_addr,read_data,write_data,acknowledge,nacknowledge,wacknowledge,wnacknowledge);
- signal RST : std_logic; -- behavioral
+ -- behavioral
+ signal RST : std_logic;
signal CTRL_REG : std_logic_vector(8 * g_nof_ctrl_bytes - 1 downto 0);
- signal start : std_logic := '0'; -- behavioral
- signal stop : std_logic := '1'; -- behavioral
-
- signal am : std_logic := '0'; -- behavioral address match
-
- signal streset : std_logic; -- bit to reset the start and stop flip flops
- signal latch_ctrl : std_logic := '0'; -- behavioral
- signal latch_ctrl_dly : std_logic := '0'; -- behavioral
- signal ctrl_tmp : std_logic_vector(8 * g_nof_ctrl_bytes - 1 downto 0); -- register to read and write to temporarily
- signal i_ctrl_reg : std_logic_vector(8 * g_nof_ctrl_bytes - 1 downto 0); -- output register
- signal rw : std_logic := '0'; -- bit to indicate a read or a write, behavioral
- signal ctrladr : std_logic_vector(6 downto 0); -- I2C address register
- signal bitcnt : natural range 0 to 7; -- bitcnt for reading bits
- signal bytecnt : natural range 0 to g_nof_ctrl_bytes - 1; -- bytenct for reading bytes
+ -- behavioral
+ signal start : std_logic := '0';
+ -- behavioral
+ signal stop : std_logic := '1';
+
+ -- behavioral address match
+ signal am : std_logic := '0';
+
+ -- bit to reset the start and stop flip flops
+ signal streset : std_logic;
+ -- behavioral
+ signal latch_ctrl : std_logic := '0';
+ -- behavioral
+ signal latch_ctrl_dly : std_logic := '0';
+ -- register to read and write to temporarily
+ signal ctrl_tmp : std_logic_vector(8 * g_nof_ctrl_bytes - 1 downto 0);
+ -- output register
+ signal i_ctrl_reg : std_logic_vector(8 * g_nof_ctrl_bytes - 1 downto 0);
+ -- bit to indicate a read or a write, behavioral
+ signal rw : std_logic := '0';
+ -- I2C address register
+ signal ctrladr : std_logic_vector(6 downto 0);
+ -- bitcnt for reading bits
+ signal bitcnt : natural range 0 to 7;
+ -- bytenct for reading bytes
+ signal bytecnt : natural range 0 to g_nof_ctrl_bytes - 1;
signal current_state : state;
- signal tri_en : std_logic; -- signal to enable the tristate buffer for the SDA line
- signal sda_int : std_logic; -- internal SDA line to drive the SDA pin
- signal wbitcnt : natural range 0 to 8; -- bitcnt for writing bits
- signal wbytecnt : natural range 0 to g_nof_ctrl_bytes - 1; -- bytenct for writing bytes
+ -- signal to enable the tristate buffer for the SDA line
+ signal tri_en : std_logic;
+ -- internal SDA line to drive the SDA pin
+ signal sda_int : std_logic;
+ -- bitcnt for writing bits
+ signal wbitcnt : natural range 0 to 8;
+ -- bytenct for writing bytes
+ signal wbytecnt : natural range 0 to g_nof_ctrl_bytes - 1;
signal zeroedge_state : state;
begin
-- Mostly behavioral code:
@@ -121,23 +150,29 @@ begin
case dev_state is
when ST_IDLE =>
if rising_edge(am) then
- dev_state <= ST_CMD_OR_DATA; -- address match so expect cmd or data
+ -- address match so expect cmd or data
+ dev_state <= ST_CMD_OR_DATA;
end if;
when ST_CMD_OR_DATA =>
if rising_edge(stop) then
- dev_state <= ST_IDLE; -- end of direct data access (write with or without cmd, or read without cmd)
+ -- end of direct data access (write with or without cmd, or read without cmd)
+ dev_state <= ST_IDLE;
elsif falling_edge(rs) then
- dev_state <= ST_READ_CMD; -- read cmd so continue with address
+ -- read cmd so continue with address
+ dev_state <= ST_READ_CMD;
end if;
when ST_READ_CMD =>
if rising_edge(am) then
- dev_state <= ST_READ_DATA; -- address match so continue with read data
+ -- address match so continue with read data
+ dev_state <= ST_READ_DATA;
elsif rising_edge(stop) then
- dev_state <= ST_IDLE; -- no address match occured
+ -- no address match occured
+ dev_state <= ST_IDLE;
end if;
when ST_READ_DATA =>
if rising_edge(stop) then
- dev_state <= ST_IDLE; -- end of cmd read data access
+ -- end of cmd read data access
+ dev_state <= ST_IDLE;
end if;
end case;
end process;
@@ -146,7 +181,8 @@ begin
en <= '1' when dev_state = ST_CMD_OR_DATA else '0';
wr_val <= latch_ctrl_dly when dev_state = ST_CMD_OR_DATA else '0';
rd_req <= rd_first or rd_next when dev_state = ST_CMD_OR_DATA or dev_state = ST_READ_DATA else '0';
- p <= stop; -- output p is can be used to distinghuis beteen direct write data or cmd write data.
+ -- output p is can be used to distinghuis beteen direct write data or cmd write data.
+ p <= stop;
-- if at p n bytes were written, then it was a direct write,
-- else if at p 1+n bytes were written then it the first byte was the cmd.
@@ -186,7 +222,8 @@ begin
end if;
end process;
- control: -- i2c slave
+ -- i2c slave
+ control:
process(SCL,RST)
begin
if RST = '1' then
@@ -219,7 +256,8 @@ begin
-- Latch CTRL register
latch_ctrl_dly <= latch_ctrl;
i_ctrl_reg <= rd_dat;
- if latch_ctrl = '1' then -- latch ctrl register
+ -- latch ctrl register
+ if latch_ctrl = '1' then
i_ctrl_reg <= ctrl_tmp;
end if;
@@ -231,25 +269,32 @@ begin
current_state <= zeroedge_state;
am <= '0';
if start = '1' then
- streset <= '1'; -- reset start bit
- ctrladr <= ctrladr(5 downto 0) & strong(SDA); -- first commands of read_addr state should immediately be executed
+ -- reset start bit
+ streset <= '1';
+ -- first commands of read_addr state should immediately be executed
+ ctrladr <= ctrladr(5 downto 0) & strong(SDA);
bitcnt <= 1;
bytecnt <= 0;
current_state <= read_addr;
- elsif stop = '1' then -- only recognized if there occurs an SCL edge between I2C Stop and Start
- streset <= '1'; -- reset stop bit
+ -- only recognized if there occurs an SCL edge between I2C Stop and Start
+ elsif stop = '1' then
+ -- reset stop bit
+ streset <= '1';
bytecnt <= 0;
current_state <= reset;
else
case zeroedge_state is
- when reset => null; -- only a Start gets the statemachines out of reset, all SCL edges are ignored until then
+ -- only a Start gets the statemachines out of reset, all SCL edges are ignored until then
+ when reset => null;
when read_addr =>
if bitcnt < 7 then
- ctrladr <= ctrladr(5 downto 0) & strong(SDA); -- shift the data to the left
+ -- shift the data to the left
+ ctrladr <= ctrladr(5 downto 0) & strong(SDA);
--shift a new bit in (MSB first)
bitcnt <= bitcnt + 1;
else
- rw <= strong(SDA); -- last bit indicates a read or a write
+ -- last bit indicates a read or a write
+ rw <= strong(SDA);
if ctrladr = g_address then
am <= '1';
current_state <= acknowledge;
@@ -259,25 +304,37 @@ begin
end if;
when read_data =>
if bitcnt < 7 then
- ctrl_tmp(8 * g_nof_ctrl_bytes - 1 downto 1) <= ctrl_tmp(8 * g_nof_ctrl_bytes - 2 downto 0); -- shift the data to the left
- ctrl_tmp(0) <= strong(SDA); -- shift a new bit in (MSB first)
+ -- shift the data to the left
+ ctrl_tmp(8 * g_nof_ctrl_bytes - 1 downto 1) <= ctrl_tmp(8 * g_nof_ctrl_bytes - 2 downto 0);
+ -- shift a new bit in (MSB first)
+ ctrl_tmp(0) <= strong(SDA);
bitcnt <= bitcnt + 1;
- else -- reading the last bit and going immediately to the ack state
- ctrl_tmp(8 * g_nof_ctrl_bytes - 1 downto 1) <= ctrl_tmp(8 * g_nof_ctrl_bytes - 2 downto 0); -- shift the data to the left
- ctrl_tmp(0) <= strong(SDA); -- shift a new bit in (MSB first)
- if bytecnt < g_nof_ctrl_bytes - 1 then -- first bytes
+ -- reading the last bit and going immediately to the ack state
+ else
+ -- shift the data to the left
+ ctrl_tmp(8 * g_nof_ctrl_bytes - 1 downto 1) <= ctrl_tmp(8 * g_nof_ctrl_bytes - 2 downto 0);
+ -- shift a new bit in (MSB first)
+ ctrl_tmp(0) <= strong(SDA);
+ -- first bytes
+ if bytecnt < g_nof_ctrl_bytes - 1 then
bytecnt <= bytecnt + 1;
- current_state <= acknowledge; -- acknowledge the successfull read of a byte
- else -- last byte
- latch_ctrl <= '1'; -- latch at g_nof_ctrl_bytes-th byte (or a multiple of that, due to bytecnt wrap)
- bytecnt <= 0; -- wrap byte count
- current_state <= acknowledge; -- acknowledge also for the last byte
+ -- acknowledge the successfull read of a byte
+ current_state <= acknowledge;
+ -- last byte
+ else
+ -- latch at g_nof_ctrl_bytes-th byte (or a multiple of that, due to bytecnt wrap)
+ latch_ctrl <= '1';
+ -- wrap byte count
+ bytecnt <= 0;
+ -- acknowledge also for the last byte
+ current_state <= acknowledge;
end if;
end if;
when write_data => null;
when acknowledge =>
if rw = '0' then
- current_state <= read_data; -- acknowledge state is one clock period active
+ -- acknowledge state is one clock period active
+ current_state <= read_data;
else
current_state <= write_data;
end if;
@@ -287,21 +344,25 @@ begin
--reached.
when wacknowledge =>
if strong(SDA) = '0' then
- current_state <= write_data; -- write went OK, continue writing bytes to the master
+ -- write went OK, continue writing bytes to the master
+ current_state <= write_data;
else
- current_state <= reset; -- write failed, so abort the transfer
+ -- write failed, so abort the transfer
+ current_state <= reset;
end if;
when wnacknowledge =>
--NACK is used to signal the end of a master read access. The slave can not known whether
--the write transfer to the master was succesful and it does not need to know anyway.
if strong(SDA) = '1' then
- current_state <= reset; -- last write went OK, no more bytes to write to the master
+ -- last write went OK, no more bytes to write to the master
+ current_state <= reset;
else
--By making current_state <= reset the CTRL register can only be read once in one transfer.
--If more bytes are read then the master will see them as 0xFF (due to SDA pull up). By
--making current_state <= write_data the CTRL register wraps if it is read more than once.
--current_state <= reset; --last write went OK, abort further transfer
- current_state <= write_data; -- last write went OK, wrap and continue writing bytes to the master
+ -- last write went OK, wrap and continue writing bytes to the master
+ current_state <= write_data;
end if;
when others =>
current_state <= reset;
@@ -320,7 +381,8 @@ begin
if start = '1' then
wbytecnt <= 0;
zeroedge_state <= reset;
- elsif stop = '1' then -- only recognized if there occurs an SCL edge between I2C Stop and Start
+ -- only recognized if there occurs an SCL edge between I2C Stop and Start
+ elsif stop = '1' then
wbytecnt <= 0;
zeroedge_state <= reset;
else
@@ -330,24 +392,33 @@ begin
when read_data => null;
when write_data =>
if wbitcnt < 8 then
- tri_en <= '1'; -- enable tri-state buffer to write SDA
+ -- enable tri-state buffer to write SDA
+ tri_en <= '1';
if i_ctrl_reg(8 * g_nof_ctrl_bytes - 1 - (8 * wbytecnt + wbitcnt)) = '0' then
- sda_int <= '0'; -- copy one bit to SDA (MSB first), else default to 'H'
+ -- copy one bit to SDA (MSB first), else default to 'H'
+ sda_int <= '0';
end if;
wbitcnt <= wbitcnt + 1;
else
- if wbytecnt < g_nof_ctrl_bytes - 1 then -- first bytes
+ -- first bytes
+ if wbytecnt < g_nof_ctrl_bytes - 1 then
wbytecnt <= wbytecnt + 1;
- zeroedge_state <= wacknowledge; -- wait till master acknowledges the successfull read of a byte
- else -- last byte
+ -- wait till master acknowledges the successfull read of a byte
+ zeroedge_state <= wacknowledge;
+ -- last byte
+ else
rd_next <= '1';
- wbytecnt <= 0; -- wrap byte count
- zeroedge_state <= wnacknowledge; -- wait till master nacknowledges the successfull read of a byte
+ -- wrap byte count
+ wbytecnt <= 0;
+ -- wait till master nacknowledges the successfull read of a byte
+ zeroedge_state <= wnacknowledge;
end if;
end if;
when acknowledge =>
- tri_en <= '1'; -- enable tri-state buffer to write SDA
- sda_int <= '0'; -- acknowledge data
+ -- enable tri-state buffer to write SDA
+ tri_en <= '1';
+ -- acknowledge data
+ sda_int <= '0';
when nacknowledge => null;
--This state is never reached.
--To answer an NACK the tri_en can remain '0', because the default SDA is 'H' due to the pull up.
diff --git a/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd b/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd
index 10a8d997b3d72b622df0b38e5b167af4011a3dc9..9b2fa6b44e419da990a93fbe4d861a25d0da46c7 100644
--- a/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd
@@ -36,28 +36,50 @@ architecture tb of tb_avs_i2c_master is
g_comma_w : natural := 0
);
port (
- coe_gs_sim_export : in std_logic := 'X'; -- gs_sim.export
- coe_sync_export : in std_logic := 'X'; -- sync.export
- coe_i2c_scl_export : inout std_logic := 'X'; -- i2c_scl.export
- coe_i2c_sda_export : inout std_logic := 'X'; -- i2c_sda.export
- csi_system_reset : in std_logic := 'X'; -- system.reset
- csi_system_clk : in std_logic := 'X'; -- .clk
- avs_control_address : in std_logic := 'X'; -- control.address
- avs_control_write : in std_logic := 'X'; -- .write
- avs_control_read : in std_logic := 'X'; -- .read
- avs_control_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- .writedata
- avs_control_readdata : out std_logic_vector(31 downto 0); -- .readdata
- avs_protocol_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- protocol.address
- avs_protocol_write : in std_logic := 'X'; -- .write
- avs_protocol_read : in std_logic := 'X'; -- .read
- avs_protocol_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- .writedata
- avs_protocol_readdata : out std_logic_vector(7 downto 0); -- .readdata
- avs_result_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- result.address
- avs_result_write : in std_logic := 'X'; -- .write
- avs_result_read : in std_logic := 'X'; -- .read
- avs_result_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- .writedata
- avs_result_readdata : out std_logic_vector(7 downto 0); -- .readdata
- ins_interrupt_irq : out std_logic -- interrupt.irq
+ -- gs_sim.export
+ coe_gs_sim_export : in std_logic := 'X';
+ -- sync.export
+ coe_sync_export : in std_logic := 'X';
+ -- i2c_scl.export
+ coe_i2c_scl_export : inout std_logic := 'X';
+ -- i2c_sda.export
+ coe_i2c_sda_export : inout std_logic := 'X';
+ -- system.reset
+ csi_system_reset : in std_logic := 'X';
+ -- .clk
+ csi_system_clk : in std_logic := 'X';
+ -- control.address
+ avs_control_address : in std_logic := 'X';
+ -- .write
+ avs_control_write : in std_logic := 'X';
+ -- .read
+ avs_control_read : in std_logic := 'X';
+ -- .writedata
+ avs_control_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- .readdata
+ avs_control_readdata : out std_logic_vector(31 downto 0);
+ -- protocol.address
+ avs_protocol_address : in std_logic_vector(9 downto 0) := (others => 'X');
+ -- .write
+ avs_protocol_write : in std_logic := 'X';
+ -- .read
+ avs_protocol_read : in std_logic := 'X';
+ -- .writedata
+ avs_protocol_writedata : in std_logic_vector(7 downto 0) := (others => 'X');
+ -- .readdata
+ avs_protocol_readdata : out std_logic_vector(7 downto 0);
+ -- result.address
+ avs_result_address : in std_logic_vector(9 downto 0) := (others => 'X');
+ -- .write
+ avs_result_write : in std_logic := 'X';
+ -- .read
+ avs_result_read : in std_logic := 'X';
+ -- .writedata
+ avs_result_writedata : in std_logic_vector(7 downto 0) := (others => 'X');
+ -- .readdata
+ avs_result_readdata : out std_logic_vector(7 downto 0);
+ -- interrupt.irq
+ ins_interrupt_irq : out std_logic
);
end component avs_i2c_master;
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd
index 9a20f6b1672db7acfcfefa9f48a8943ab46c1def..75af6c4d4d633027bd66b4357e78152cdc35dc6e 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd
@@ -54,7 +54,8 @@
entity tb_i2c_commander is
generic (
- g_board : string := "adu" -- else default to "unb"
+ -- else default to "unb"
+ g_board : string := "adu"
--g_board : STRING := "unb"
);
end tb_i2c_commander;
@@ -80,9 +81,11 @@ architecture tb of tb_i2c_commander is
constant c_use_result_ram : boolean := true;
- constant c_sim : boolean := true; -- FALSE
+ -- FALSE
+ constant c_sim : boolean := true;
--CONSTANT c_sim : BOOLEAN := FALSE;
- constant c_clk_freq_in_MHz : natural := 100; -- 100 MHz
+ -- 100 MHz
+ constant c_clk_freq_in_MHz : natural := 100;
constant c_clk_period : time := (10**3 / c_clk_freq_in_MHz) * 1 ns;
constant c_rst_period : time := 4 * c_clk_period;
@@ -93,18 +96,25 @@ architecture tb of tb_i2c_commander is
constant ADR_MAX1617 : natural := sel_a_b(g_board = "adu", I2C_ADU_MAX1617_ADR, I2C_UNB_MAX1617_ADR);
constant ADR_PCA9555 : natural := sel_a_b(g_board = "adu", I2C_ADU_PCA9555_ADR, 0);
- constant c_sens_volt_address : std_logic_vector := TO_UVEC(ADR_MAX6652, 7); -- MAX6652 address GND
- constant c_max6652_volt_1v2 : natural := 92; -- 92 * 2.5/192 = 1.2
- constant c_max6652_volt_2v5 : natural := 147; -- 147 * 3.3/192 = 2.5
- constant c_max6652_volt_nc : natural := 13; -- 13 * 12 /192 = 0.1
- constant c_max6652_volt_3v3 : natural := 127; -- 127 * 5.0/192 = 3.3
+ -- MAX6652 address GND
+ constant c_sens_volt_address : std_logic_vector := TO_UVEC(ADR_MAX6652, 7);
+ -- 92 * 2.5/192 = 1.2
+ constant c_max6652_volt_1v2 : natural := 92;
+ -- 147 * 3.3/192 = 2.5
+ constant c_max6652_volt_2v5 : natural := 147;
+ -- 13 * 12 /192 = 0.1
+ constant c_max6652_volt_nc : natural := 13;
+ -- 127 * 5.0/192 = 3.3
+ constant c_max6652_volt_3v3 : natural := 127;
constant c_max6652_temp : natural := 40;
--CONSTANT c_sens_temp_address : STD_LOGIC_VECTOR := TO_UVEC(MAX1617_ADR_LOW_MID, 7); -- use other slave address to force I2C errors
- constant c_sens_temp_address : std_logic_vector := TO_UVEC(ADR_MAX1617, 7); -- MAX1618 address MID MID
+ -- MAX1618 address MID MID
+ constant c_sens_temp_address : std_logic_vector := TO_UVEC(ADR_MAX1617, 7);
constant c_max1618_temp : integer := 60;
- constant c_io_expander_address : std_logic_vector := TO_UVEC(ADR_PCA9555, 7); -- ADR_PCA9555 address
+ -- ADR_PCA9555 address
+ constant c_io_expander_address : std_logic_vector := TO_UVEC(ADR_PCA9555, 7);
-- Select the expected read data arrays for the result data (the read data values are tb dependent, so therefore they are not obtained from a package)
constant c_max1618_expected_data_read_temp_arr : t_i2c_cmdr_natural_arr := (c_max1618_temp, c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x,
@@ -214,15 +224,18 @@ begin
clk <= (not clk) or tb_end after c_clk_period / 2;
-- I2C bus
- scl <= 'H'; -- model I2C pull up
- sda <= 'H'; -- model I2C pull up, use '0' and '1' to verify SDA forced low or high error
+ -- model I2C pull up
+ scl <= 'H';
+ -- model I2C pull up, use '0' and '1' to verify SDA forced low or high error
+ sda <= 'H';
scl <= scl_stretch;
sens_clk_stretch : process (scl)
begin
if falling_edge(scl) then
- scl_stretch <= '0', 'Z' after 50 ns; -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ scl_stretch <= '0', 'Z' after 50 ns;
end if;
end process;
@@ -257,10 +270,12 @@ begin
if c_protocol_ram_init_file = "UNUSED" then
-- Write
for I in 0 to c_protocol_ram_init'length - 1 loop
- proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, protocol_miso, protocol_mosi); -- fill u_protocol_ram
+ -- fill u_protocol_ram
+ proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, protocol_miso, protocol_mosi);
end loop;
for I in c_protocol_ram_init'length to c_mem_i2c.protocol_nof_dat - 1 loop
- proc_mem_mm_bus_wr(I, SMBUS_C_END, clk, protocol_miso, protocol_mosi); -- fill remainder of u_protocol_ram with default
+ -- fill remainder of u_protocol_ram with default
+ proc_mem_mm_bus_wr(I, SMBUS_C_END, clk, protocol_miso, protocol_mosi);
end loop;
else
@@ -290,10 +305,12 @@ begin
----------------------------------------------------------------------------
for I in 0 to c_protocol_ram_init'length - 1 loop
- proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, file_miso, file_mosi); -- fill u_protocol_ram_init_file
+ -- fill u_protocol_ram_init_file
+ proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, file_miso, file_mosi);
end loop;
for I in c_protocol_ram_init'length to c_mem_i2c.protocol_nof_dat - 1 loop
- proc_mem_mm_bus_wr(I, SMBUS_C_END, clk, file_miso, file_mosi); -- fill remainder of u_protocol_ram_init_file with default
+ -- fill remainder of u_protocol_ram_init_file with default
+ proc_mem_mm_bus_wr(I, SMBUS_C_END, clk, file_miso, file_mosi);
end loop;
proc_common_wait_some_cycles(clk, 10);
@@ -393,7 +410,8 @@ begin
);
-- I2C slaves
- u_sens_volt : entity work.dev_max6652 -- only on "unb"
+ -- only on "unb"
+ u_sens_volt : entity work.dev_max6652
generic map (
g_address => c_sens_volt_address
)
@@ -407,7 +425,8 @@ begin
temp => c_max6652_temp
);
- u_sens_temp : entity work.dev_max1618 -- both on "unb" and on "adu"
+ -- both on "unb" and on "adu"
+ u_sens_temp : entity work.dev_max1618
generic map (
g_address => c_sens_temp_address
)
@@ -417,7 +436,8 @@ begin
temp => c_max1618_temp
);
- u_io_expander : entity work.dev_pca9555 -- only on "adu"
+ -- only on "adu"
+ u_io_expander : entity work.dev_pca9555
generic map (
g_address => c_io_expander_address
)
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd
index 352690a6f633776d6c6c86a4e47b101fb9cabcf3..dc8523ed7cc0950c398270b8bd62c581b6021c83 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd
@@ -57,7 +57,8 @@
entity tb_i2c_commander_unb2_pmbus is
generic (
- g_board : string := "unb2" -- only works with UniBoard2
+ -- only works with UniBoard2
+ g_board : string := "unb2"
);
end tb_i2c_commander_unb2_pmbus;
@@ -73,16 +74,20 @@ use work.i2c_dev_unb2_pkg.all;
use work.i2c_pkg.all;
use work.i2c_commander_pkg.all;
use work.i2c_commander_unb2_sens_pkg.all;
-use work.i2c_commander_unb2_pmbus_pkg.all; -- in case we can add the PMBUS later
+-- in case we can add the PMBUS later
+use work.i2c_commander_unb2_pmbus_pkg.all;
architecture tb of tb_i2c_commander_unb2_pmbus is
--CONSTANT c_protocol_ram_init_file : STRING := "data/unb2_sens_protocol_ram_init.hex";
--CONSTANT c_protocol_ram_init_file : STRING := "data/unb2_pmbus_protocol_ram_init.hex";
- constant c_protocol_ram_init_file : string := "UNUSED"; -- start with this, then make a hex file from the txt file?
+ -- start with this, then make a hex file from the txt file?
+ constant c_protocol_ram_init_file : string := "UNUSED";
constant c_use_result_ram : boolean := true;
- constant c_sim : boolean := true; -- FALSE
- constant c_clk_freq_in_MHz : natural := 100; -- 100 MHz
+ -- FALSE
+ constant c_sim : boolean := true;
+ -- 100 MHz
+ constant c_clk_freq_in_MHz : natural := 100;
constant c_clk_period : time := (10**3 / c_clk_freq_in_MHz) * 1 ns;
constant c_rst_period : time := 4 * c_clk_period;
@@ -99,7 +104,8 @@ architecture tb of tb_i2c_commander_unb2_pmbus is
-- Select the expected read data arrays for the result data (the read data values are tb dependent, so therefore they are not obtained from a package)
- type t_i2c_unb2_natural_arr is array (integer range 0 to 31) of natural; -- needto test some long protocol lists
+ -- needto test some long protocol lists
+ type t_i2c_unb2_natural_arr is array (integer range 0 to 31) of natural;
type t_i2c_unb2_natural_mat is array (integer range <>) of t_i2c_unb2_natural_arr;
constant c_default_expected_data_arr : t_i2c_unb2_natural_arr := ( others => 254);
@@ -157,15 +163,18 @@ begin
clk <= (not clk) or tb_end after c_clk_period / 2;
-- I2C bus
- scl <= 'H'; -- model I2C pull up
- sda <= 'H'; -- model I2C pull up, use '0' and '1' to verify SDA forced low or high error
+ -- model I2C pull up
+ scl <= 'H';
+ -- model I2C pull up, use '0' and '1' to verify SDA forced low or high error
+ sda <= 'H';
scl <= scl_stretch;
sens_clk_stretch : process (scl)
begin
if falling_edge(scl) then
- scl_stretch <= '0', 'Z' after 50 ns; -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ scl_stretch <= '0', 'Z' after 50 ns;
end if;
end process;
@@ -200,10 +209,12 @@ begin
if c_protocol_ram_init_file = "UNUSED" then
-- Write
for I in 0 to c_protocol_ram_init'length - 1 loop
- proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, protocol_miso, protocol_mosi); -- fill u_protocol_ram
+ -- fill u_protocol_ram
+ proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, protocol_miso, protocol_mosi);
end loop;
for I in c_protocol_ram_init'length to c_mem_i2c.protocol_nof_dat - 1 loop
- proc_mem_mm_bus_wr(I, SMBUS_C_END, clk, protocol_miso, protocol_mosi); -- fill remainder of u_protocol_ram with default
+ -- fill remainder of u_protocol_ram with default
+ proc_mem_mm_bus_wr(I, SMBUS_C_END, clk, protocol_miso, protocol_mosi);
end loop;
else
@@ -233,10 +244,12 @@ begin
----------------------------------------------------------------------------
for I in 0 to c_protocol_ram_init'length - 1 loop
- proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, file_miso, file_mosi); -- fill u_protocol_ram_init_file
+ -- fill u_protocol_ram_init_file
+ proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, file_miso, file_mosi);
end loop;
for I in c_protocol_ram_init'length to c_mem_i2c.protocol_nof_dat - 1 loop
- proc_mem_mm_bus_wr(I, SMBUS_C_END, clk, file_miso, file_mosi); -- fill remainder of u_protocol_ram_init_file with default
+ -- fill remainder of u_protocol_ram_init_file with default
+ proc_mem_mm_bus_wr(I, SMBUS_C_END, clk, file_miso, file_mosi);
end loop;
proc_common_wait_some_cycles(clk, 10);
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd
index 065b2c384d3845dd74d1fda8abe5455abc792910..457d146ec3bafe0c33dc9651b4ebf864c0f187cf 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd
@@ -57,7 +57,8 @@
entity tb_i2c_commander_unb2_sens is
generic (
- g_board : string := "unb2" -- only works with UniBoard2
+ -- only works with UniBoard2
+ g_board : string := "unb2"
);
end tb_i2c_commander_unb2_sens;
@@ -73,16 +74,20 @@ use work.i2c_dev_unb2_pkg.all;
use work.i2c_pkg.all;
use work.i2c_commander_pkg.all;
use work.i2c_commander_unb2_sens_pkg.all;
-use work.i2c_commander_unb2_pmbus_pkg.all; -- in case we can add the PMBUS later
+-- in case we can add the PMBUS later
+use work.i2c_commander_unb2_pmbus_pkg.all;
architecture tb of tb_i2c_commander_unb2_sens is
--CONSTANT c_protocol_ram_init_file : STRING := "data/unb2_sens_protocol_ram_init.hex";
--CONSTANT c_protocol_ram_init_file : STRING := "data/unb2_pmbus_protocol_ram_init.hex";
- constant c_protocol_ram_init_file : string := "UNUSED"; -- start with this, then make a hex file from the txt file?
+ -- start with this, then make a hex file from the txt file?
+ constant c_protocol_ram_init_file : string := "UNUSED";
constant c_use_result_ram : boolean := true;
- constant c_sim : boolean := true; -- FALSE
- constant c_clk_freq_in_MHz : natural := 100; -- 100 MHz
+ -- FALSE
+ constant c_sim : boolean := true;
+ -- 100 MHz
+ constant c_clk_freq_in_MHz : natural := 100;
constant c_clk_period : time := (10**3 / c_clk_freq_in_MHz) * 1 ns;
constant c_rst_period : time := 4 * c_clk_period;
@@ -103,7 +108,8 @@ architecture tb of tb_i2c_commander_unb2_sens is
-- Select the expected read data arrays for the result data (the read data values are tb dependent, so therefore they are not obtained from a package)
- type t_i2c_unb2_natural_arr is array (integer range 0 to 31) of natural; -- needto test some long protocol lists
+ -- needto test some long protocol lists
+ type t_i2c_unb2_natural_arr is array (integer range 0 to 31) of natural;
type t_i2c_unb2_natural_mat is array (integer range <>) of t_i2c_unb2_natural_arr;
constant c_max1618_expected_data_read_temp_arr : t_i2c_unb2_natural_arr := (c_max1618_temp, others => 254);
@@ -162,15 +168,18 @@ begin
clk <= (not clk) or tb_end after c_clk_period / 2;
-- I2C bus
- scl <= 'H'; -- model I2C pull up
- sda <= 'H'; -- model I2C pull up, use '0' and '1' to verify SDA forced low or high error
+ -- model I2C pull up
+ scl <= 'H';
+ -- model I2C pull up, use '0' and '1' to verify SDA forced low or high error
+ sda <= 'H';
scl <= scl_stretch;
sens_clk_stretch : process (scl)
begin
if falling_edge(scl) then
- scl_stretch <= '0', 'Z' after 50 ns; -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ scl_stretch <= '0', 'Z' after 50 ns;
end if;
end process;
@@ -205,10 +214,12 @@ begin
if c_protocol_ram_init_file = "UNUSED" then
-- Write
for I in 0 to c_protocol_ram_init'length - 1 loop
- proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, protocol_miso, protocol_mosi); -- fill u_protocol_ram
+ -- fill u_protocol_ram
+ proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, protocol_miso, protocol_mosi);
end loop;
for I in c_protocol_ram_init'length to c_mem_i2c.protocol_nof_dat - 1 loop
- proc_mem_mm_bus_wr(I, SMBUS_C_END, clk, protocol_miso, protocol_mosi); -- fill remainder of u_protocol_ram with default
+ -- fill remainder of u_protocol_ram with default
+ proc_mem_mm_bus_wr(I, SMBUS_C_END, clk, protocol_miso, protocol_mosi);
end loop;
else
@@ -238,10 +249,12 @@ begin
----------------------------------------------------------------------------
for I in 0 to c_protocol_ram_init'length - 1 loop
- proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, file_miso, file_mosi); -- fill u_protocol_ram_init_file
+ -- fill u_protocol_ram_init_file
+ proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, file_miso, file_mosi);
end loop;
for I in c_protocol_ram_init'length to c_mem_i2c.protocol_nof_dat - 1 loop
- proc_mem_mm_bus_wr(I, SMBUS_C_END, clk, file_miso, file_mosi); -- fill remainder of u_protocol_ram_init_file with default
+ -- fill remainder of u_protocol_ram_init_file with default
+ proc_mem_mm_bus_wr(I, SMBUS_C_END, clk, file_miso, file_mosi);
end loop;
proc_common_wait_some_cycles(clk, 10);
@@ -439,7 +452,8 @@ begin
temp => 40
);
- u_sens_temp : entity work.dev_max1618 -- both on "unb" and on "adu"
+ -- both on "unb" and on "adu"
+ u_sens_temp : entity work.dev_max1618
generic map (
g_address => c_sens_temp_address
)
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
index 436888b8d3a79181214f690079912fd20ddede55..c223b26f2f9159c885a02e55aa868effe8d1d340 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
@@ -34,15 +34,18 @@ use work.i2c_dev_max6652_pkg.all;
use work.i2c_pkg.all;
architecture tb of tb_i2c_master is
- constant c_sim : boolean := true; -- FALSE
- constant c_clk_freq_in_MHz : natural := 100; -- 100 MHz
+ -- FALSE
+ constant c_sim : boolean := true;
+ -- 100 MHz
+ constant c_clk_freq_in_MHz : natural := 100;
constant c_clk_period : time := (10**3 / c_clk_freq_in_MHz) * 1 ns;
constant c_rst_period : time := 4 * c_clk_period;
constant c_phy_i2c : t_c_i2c_phy := func_i2c_sel_a_b(c_sim, c_i2c_phy_sim, func_i2c_calculate_phy(c_clk_freq_in_MHz));
constant c_bus_dat_w : natural := 8;
- constant c_sens_temp_volt_sz : natural := 9; -- Should match nof read bytes via I2C in the sens_ctrl SEQUENCE list
+ -- Should match nof read bytes via I2C in the sens_ctrl SEQUENCE list
+ constant c_sens_temp_volt_sz : natural := 9;
-- Model I2C sensor slaves as on the LOFAR RSP board
constant ADR_MAX6652 : natural := MAX6652_ADR_GND;
@@ -52,21 +55,31 @@ architecture tb of tb_i2c_master is
constant ADR_MAX1617_AP2 : natural := MAX1617_ADR_HIGH_LOW;
constant ADR_MAX1617_AP3 : natural := MAX1617_ADR_HIGH_HIGH;
- constant c_bp_volt_address : std_logic_vector := TO_UVEC(ADR_MAX6652, 7); -- MAX6652 address GND
- constant c_bp_temp_address : std_logic_vector := TO_UVEC(ADR_MAX1617_BP, 7); -- MAX1618 address MID MID
- constant c_ap0_temp_address : std_logic_vector := TO_UVEC(ADR_MAX1617_AP0, 7); -- MAX1618 address LOW LOW
- constant c_ap1_temp_address : std_logic_vector := TO_UVEC(ADR_MAX1617_AP1, 7); -- MAX1618 address LOW HIGH
- constant c_ap2_temp_address : std_logic_vector := TO_UVEC(ADR_MAX1617_AP2, 7); -- MAX1618 address HIGH LOW
- constant c_ap3_temp_address : std_logic_vector := TO_UVEC(ADR_MAX1617_AP3, 7); -- MAX1618 address HIGH HIGH
+ -- MAX6652 address GND
+ constant c_bp_volt_address : std_logic_vector := TO_UVEC(ADR_MAX6652, 7);
+ -- MAX1618 address MID MID
+ constant c_bp_temp_address : std_logic_vector := TO_UVEC(ADR_MAX1617_BP, 7);
+ -- MAX1618 address LOW LOW
+ constant c_ap0_temp_address : std_logic_vector := TO_UVEC(ADR_MAX1617_AP0, 7);
+ -- MAX1618 address LOW HIGH
+ constant c_ap1_temp_address : std_logic_vector := TO_UVEC(ADR_MAX1617_AP1, 7);
+ -- MAX1618 address HIGH LOW
+ constant c_ap2_temp_address : std_logic_vector := TO_UVEC(ADR_MAX1617_AP2, 7);
+ -- MAX1618 address HIGH HIGH
+ constant c_ap3_temp_address : std_logic_vector := TO_UVEC(ADR_MAX1617_AP3, 7);
constant c_bp_temp : integer := 60;
constant c_ap0_temp : integer := 70;
constant c_ap1_temp : integer := 71;
constant c_ap2_temp : integer := 72;
constant c_ap3_temp : integer := 73;
- constant c_volt_1v2 : natural := 92; -- 92 * 2.5/192 = 1.2
- constant c_volt_2v5 : natural := 147; -- 147 * 3.3/192 = 2.5
- constant c_volt_nc : natural := 13; -- 13 * 12 /192 = 0.1
- constant c_volt_3v3 : natural := 127; -- 127 * 5.0/192 = 3.3
+ -- 92 * 2.5/192 = 1.2
+ constant c_volt_1v2 : natural := 92;
+ -- 147 * 3.3/192 = 2.5
+ constant c_volt_2v5 : natural := 147;
+ -- 13 * 12 /192 = 0.1
+ constant c_volt_nc : natural := 13;
+ -- 127 * 5.0/192 = 3.3
+ constant c_volt_3v3 : natural := 127;
constant c_temp_pcb : natural := 40;
constant c_temp_high : natural := 127;
@@ -173,15 +186,18 @@ begin
clk <= (not clk) or tb_end after c_clk_period / 2;
-- I2C bus
- scl <= 'H'; -- model I2C pull up
- sda <= 'H'; -- model I2C pull up
+ -- model I2C pull up
+ scl <= 'H';
+ -- model I2C pull up
+ sda <= 'H';
scl <= scl_stretch;
sens_clk_stretch : process (scl)
begin
if falling_edge(scl) then
- scl_stretch <= '0', 'Z' after 50 ns; -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ scl_stretch <= '0', 'Z' after 50 ns;
end if;
end process;
@@ -210,7 +226,8 @@ begin
-- WHILE control_status='0' LOOP
proc_common_wait_until_high(clk, control_interrupt);
--WHILE control_status='0' LOOP
- proc_mem_mm_bus_rd(0, clk, control_miso, control_mosi); -- read result available in control_status
+ -- read result available in control_status
+ proc_mem_mm_bus_rd(0, clk, control_miso, control_mosi);
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, clk);
control_status <= control_miso.rddata(c_control_ready_bi);
proc_common_wait_some_cycles(clk, 1);
@@ -218,7 +235,8 @@ begin
-- Read result list
for I in 0 to c_expected_mask'length - 1 loop
- proc_mem_mm_bus_rd(I, clk, result_miso, result_mosi); -- read result available in result_data
+ -- read result available in result_data
+ proc_mem_mm_bus_rd(I, clk, result_miso, result_mosi);
end loop;
proc_common_wait_some_cycles(clk, 100);
@@ -281,19 +299,22 @@ begin
mms_control_address => control_mosi.address(c_i2c_mm.control_adr_w - 1 downto 0),
mms_control_write => control_mosi.wr,
mms_control_read => control_mosi.rd,
- mms_control_writedata => control_mosi.wrdata(c_word_w - 1 downto 0), -- use default MM bus width for control
+ -- use default MM bus width for control
+ mms_control_writedata => control_mosi.wrdata(c_word_w - 1 downto 0),
mms_control_readdata => control_miso.rddata(c_word_w - 1 downto 0),
-- MM slave I2C protocol register
mms_protocol_address => protocol_mosi.address(c_i2c_mm.protocol_adr_w - 1 downto 0),
mms_protocol_write => protocol_mosi.wr,
mms_protocol_read => protocol_mosi.rd,
- mms_protocol_writedata => protocol_mosi.wrdata(c_byte_w - 1 downto 0), -- define MM bus data has same width as SMBus data
+ -- define MM bus data has same width as SMBus data
+ mms_protocol_writedata => protocol_mosi.wrdata(c_byte_w - 1 downto 0),
mms_protocol_readdata => protocol_miso.rddata(c_byte_w - 1 downto 0),
-- MM slave I2C result register
mms_result_address => result_mosi.address(c_i2c_mm.result_adr_w - 1 downto 0),
mms_result_write => result_mosi.wr,
mms_result_read => result_mosi.rd,
- mms_result_writedata => result_mosi.wrdata(c_byte_w - 1 downto 0), -- define MM bus data has same width as SMBus data
+ -- define MM bus data has same width as SMBus data
+ mms_result_writedata => result_mosi.wrdata(c_byte_w - 1 downto 0),
mms_result_readdata => result_miso.rddata(c_byte_w - 1 downto 0),
-- Interrupt
ins_result_rdy => control_interrupt,
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd b/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd
index 1307590caddc8ce3bc549c28c6640277698e9711..270856f59cb4a59148e1e5505ef9c47a81f12fb2 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd
@@ -34,7 +34,8 @@ end tb_i2cslave;
architecture tb of tb_i2cslave is
constant c_period : time := 25 ns;
- constant c_address : std_logic_vector(6 downto 0) := "0000001"; -- Slave I2C address
+ -- Slave I2C address
+ constant c_address : std_logic_vector(6 downto 0) := "0000001";
constant c_nof_ctrl_bytes : integer := 3;
component i2cslave
@@ -52,10 +53,14 @@ architecture tb of tb_i2cslave is
);
end component;
- signal SDA : std_logic; -- I2C Serial Data Line
- signal SCL : std_logic; -- I2C Serial Clock Line
- signal RST : std_logic; -- optional reset bit
- signal CTRL_REG : std_logic_vector(8 * c_nof_ctrl_bytes - 1 downto 0); -- ctrl for RCU control
+ -- I2C Serial Data Line
+ signal SDA : std_logic;
+ -- I2C Serial Clock Line
+ signal SCL : std_logic;
+ -- optional reset bit
+ signal RST : std_logic;
+ -- ctrl for RCU control
+ signal CTRL_REG : std_logic_vector(8 * c_nof_ctrl_bytes - 1 downto 0);
begin
uut: i2cslave
generic map (
@@ -90,33 +95,49 @@ tbctrl : process
tbsda : process
begin
SDA <= 'Z';
- wait for 200 ns; -- initial time to let the fpga set up things
+ -- initial time to let the fpga set up things
+ wait for 200 ns;
RST <= '1', '0' after 100 ns;
- wait for 200 ns; -- initial time to let the fpga set up things
+ -- initial time to let the fpga set up things
+ wait for 200 ns;
--I2C write sequence (from master to slave)
SDA <= 'H', '0' after 30 ns, '0' after 60 ns,'0' after 110 ns,'0' after 160 ns,'0' after 210 ns,'0' after 260 ns,'0' after 310 ns,'H' after 360 ns,'0' after 410 ns;
-- start sent address: 0000001, sent rw=0
--the previous is evaluated at time = 0
- wait for 452 ns; -- next lines are evaluated 450 ns later
- SDA <= 'Z'; -- time for slave to acknowledge
- wait for 50 ns; -- WAIT 1 clk cycle
- SDA <= 'Z','H' after 10 ns, '0' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, 'H' after 260 ns, 'H' after 310 ns, '0' after 360 ns; -- sent first data byte
+ -- next lines are evaluated 450 ns later
+ wait for 452 ns;
+ -- time for slave to acknowledge
+ SDA <= 'Z';
+ -- WAIT 1 clk cycle
+ wait for 50 ns;
+ -- sent first data byte
+ SDA <= 'Z','H' after 10 ns, '0' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, 'H' after 260 ns, 'H' after 310 ns, '0' after 360 ns;
wait for 400 ns;
- SDA <= 'Z'; -- time for slave to acknowledge
- wait for 50 ns; -- WAIT 1 clk cycle
- SDA <= 'Z','0' after 10 ns, 'H' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, '0' after 260 ns, 'H' after 310 ns, 'H' after 360 ns; -- sent second data byte
+ -- time for slave to acknowledge
+ SDA <= 'Z';
+ -- WAIT 1 clk cycle
+ wait for 50 ns;
+ -- sent second data byte
+ SDA <= 'Z','0' after 10 ns, 'H' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, '0' after 260 ns, 'H' after 310 ns, 'H' after 360 ns;
wait for 400 ns;
- SDA <= 'Z'; -- time for slave to acknowledge
- wait for 50 ns; -- WAIT 1 clk cycle
- SDA <= 'Z','0' after 10 ns, 'H' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, '0' after 260 ns, 'H' after 310 ns, 'H' after 360 ns; -- sent third data byte
+ -- time for slave to acknowledge
+ SDA <= 'Z';
+ -- WAIT 1 clk cycle
+ wait for 50 ns;
+ -- sent third data byte
+ SDA <= 'Z','0' after 10 ns, 'H' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, '0' after 260 ns, 'H' after 310 ns, 'H' after 360 ns;
wait for 400 ns;
- SDA <= 'Z'; -- time for slave to nacknowledge
- wait for 70 ns; -- WAIT 1.5 clk cycle
- SDA <= '0'; -- stop
- wait for 30 ns; -- to get in line with falling clk edge
+ -- time for slave to nacknowledge
+ SDA <= 'Z';
+ -- WAIT 1.5 clk cycle
+ wait for 70 ns;
+ -- stop
+ SDA <= '0';
+ -- to get in line with falling clk edge
+ wait for 30 ns;
--reset slave
RST <= '1';
@@ -127,20 +148,29 @@ tbsda : process
--I2C read sequence (from slave to master)
SDA <= 'H', '0' after 30 ns, '0' after 60 ns,'0' after 110 ns,'0' after 160 ns,'0' after 210 ns,'0' after 260 ns,'0' after 310 ns,'H' after 360 ns,'H' after 410 ns;
-- start sent address: 0000001 sent rw=1
- wait for 450 ns; -- next lines are evaluated 450 ns later
- SDA <= 'Z'; -- time for slave to acknowledge address
+ -- next lines are evaluated 450 ns later
+ wait for 450 ns;
+ -- time for slave to acknowledge address
+ SDA <= 'Z';
wait for 505 ns;
- SDA <= '0','Z' after 30 ns; -- acknowledge first byte
+ -- acknowledge first byte
+ SDA <= '0','Z' after 30 ns;
wait for 500 ns;
- SDA <= '0','Z' after 30 ns; -- acknowledge second byte
+ -- acknowledge second byte
+ SDA <= '0','Z' after 30 ns;
--time is 2455ns + 450ns
- wait for 505 ns; -- on purpose the nack is given 100 ns later
- SDA <= 'H','Z' after 50 ns; -- nacknowledge third byte
- wait for 125 ns; -- WAIT 2.5 clk to give stop command
- SDA <= 'H'; -- stop
- wait for 15 ns; -- to get in line with falling clk edge
+ -- on purpose the nack is given 100 ns later
+ wait for 505 ns;
+ -- nacknowledge third byte
+ SDA <= 'H','Z' after 50 ns;
+ -- WAIT 2.5 clk to give stop command
+ wait for 125 ns;
+ -- stop
+ SDA <= 'H';
+ -- to get in line with falling clk edge
+ wait for 15 ns;
--time is 3115
wait for 200 ns;
@@ -156,18 +186,29 @@ tbsda : process
SDA <= 'H', '0' after 30 ns, 'H' after 60 ns,'0' after 110 ns,'0' after 160 ns,'0' after 210 ns,'0' after 260 ns,'0' after 310 ns,'0' after 360 ns,'0' after 410 ns;
-- start sent address: 0000001, sent rw=0
--the previous is evaluated at time = 0
- wait for 450 ns; -- next lines are evaluated 450 ns later
- SDA <= 'Z'; -- time for slave to acknowledge
- wait for 50 ns; -- WAIT 1 clk cycle
- SDA <= 'Z','0' after 10 ns, '0' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, 'H' after 260 ns, 'H' after 310 ns, '0' after 360 ns; -- sent first data byte
+ -- next lines are evaluated 450 ns later
+ wait for 450 ns;
+ -- time for slave to acknowledge
+ SDA <= 'Z';
+ -- WAIT 1 clk cycle
+ wait for 50 ns;
+ -- sent first data byte
+ SDA <= 'Z','0' after 10 ns, '0' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, 'H' after 260 ns, 'H' after 310 ns, '0' after 360 ns;
wait for 400 ns;
- SDA <= 'Z'; -- time for slave to acknowledge
- wait for 50 ns; -- WAIT 1 clk cycle
- SDA <= 'Z','0' after 10 ns, 'H' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, '0' after 260 ns, 'H' after 310 ns, 'H' after 360 ns; -- sent second data byte
+ -- time for slave to acknowledge
+ SDA <= 'Z';
+ -- WAIT 1 clk cycle
+ wait for 50 ns;
+ -- sent second data byte
+ SDA <= 'Z','0' after 10 ns, 'H' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, '0' after 260 ns, 'H' after 310 ns, 'H' after 360 ns;
wait for 400 ns;
- SDA <= 'Z'; -- time for slave to nacknowledge
- wait for 80 ns; -- WAIT 1.5 clk cycle
- SDA <= '0'; -- stop
- wait for 20 ns; -- to get in line with falling clk edge
+ -- time for slave to nacknowledge
+ SDA <= 'Z';
+ -- WAIT 1.5 clk cycle
+ wait for 80 ns;
+ -- stop
+ SDA <= '0';
+ -- to get in line with falling clk edge
+ wait for 20 ns;
end process;
end;
diff --git a/libraries/io/i2c/tb/vhdl/tb_tb_i2c_commander.vhd b/libraries/io/i2c/tb/vhdl/tb_tb_i2c_commander.vhd
index 8bc60ed08ef6fdd173441a26974a2c22bb42137d..ed1f021a48ab0ab27ab3013fc9c1cc58e8c42a3d 100644
--- a/libraries/io/i2c/tb/vhdl/tb_tb_i2c_commander.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_tb_i2c_commander.vhd
@@ -34,7 +34,8 @@ entity tb_tb_i2c_commander is
end tb_tb_i2c_commander;
architecture tb of tb_tb_i2c_commander is
- signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+ signal tb_end : std_logic := '0';
begin
-- g_board : STRING := "adu" -- else default to "unb"
diff --git a/libraries/io/mac_10g/io_mac_10g.vhd b/libraries/io/mac_10g/io_mac_10g.vhd
index 0327504a1c3626098ff08be39735eaa5f895b0dc..c0bc0fede4b8aa3d8a8abbd8c3aea9e4655a047e 100644
--- a/libraries/io/mac_10g/io_mac_10g.vhd
+++ b/libraries/io/mac_10g/io_mac_10g.vhd
@@ -53,26 +53,36 @@ entity io_mac_10g is
-- MM
mm_clk : in std_logic;
mm_rst : in std_logic;
- mac_mosi : in t_mem_mosi; -- CSR = control status register
+ -- CSR = control status register
+ mac_mosi : in t_mem_mosi;
mac_miso : out t_mem_miso;
-- ST
- tx_clk_312 : in std_logic := '0'; -- 312.5 MHz
- tx_clk_156 : in std_logic; -- 156.25 MHz local reference
+ -- 312.5 MHz
+ tx_clk_312 : in std_logic := '0';
+ -- 156.25 MHz local reference
+ tx_clk_156 : in std_logic;
tx_rst : in std_logic;
- tx_snk_in : in t_dp_sosi; -- 64 bit data
+ -- 64 bit data
+ tx_snk_in : in t_dp_sosi;
tx_snk_out : out t_dp_siso;
- rx_clk_312 : in std_logic := '0'; -- 312.5 MHz
- rx_clk_156 : in std_logic; -- 156.25 MHz from rx phy
+ -- 312.5 MHz
+ rx_clk_312 : in std_logic := '0';
+ -- 156.25 MHz from rx phy
+ rx_clk_156 : in std_logic;
rx_rst : in std_logic;
- rx_src_out : out t_dp_sosi; -- 64 bit data
+ -- 64 bit data
+ rx_src_out : out t_dp_sosi;
rx_src_in : in t_dp_siso;
-- XGMII
- xgmii_link_status : out std_logic_vector(c_tech_mac_10g_link_status_w - 1 downto 0); -- 2 bit
- xgmii_tx_data : out std_logic_vector(c_xgmii_w - 1 downto 0); -- 72 bit
- xgmii_rx_data : in std_logic_vector(c_xgmii_w - 1 downto 0) -- 72 bit
+ -- 2 bit
+ xgmii_link_status : out std_logic_vector(c_tech_mac_10g_link_status_w - 1 downto 0);
+ -- 72 bit
+ xgmii_tx_data : out std_logic_vector(c_xgmii_w - 1 downto 0);
+ -- 72 bit
+ xgmii_rx_data : in std_logic_vector(c_xgmii_w - 1 downto 0)
);
end io_mac_10g;
@@ -94,13 +104,15 @@ begin
tx_clk_312 => tx_clk_312,
tx_clk_156 => tx_clk_156,
tx_rst => tx_rst,
- tx_snk_in => tx_snk_in, -- 64 bit data
+ -- 64 bit data
+ tx_snk_in => tx_snk_in,
tx_snk_out => tx_snk_out,
rx_clk_312 => rx_clk_312,
rx_clk_156 => rx_clk_156,
rx_rst => rx_rst,
- rx_src_out => rx_src_out, -- 64 bit data
+ -- 64 bit data
+ rx_src_out => rx_src_out,
rx_src_in => rx_src_in,
-- XGMII
diff --git a/libraries/io/mdio/src/vhdl/avs_mdio.vhd b/libraries/io/mdio/src/vhdl/avs_mdio.vhd
index c5885093709a02dbdf0642becd49cb030566d2c7..bb4a8ec289fb55da7d47b77c1b560a7cb519350d 100644
--- a/libraries/io/mdio/src/vhdl/avs_mdio.vhd
+++ b/libraries/io/mdio/src/vhdl/avs_mdio.vhd
@@ -48,7 +48,8 @@ use work.mdio_pkg.all;
entity avs_mdio is
generic (
-- g_mdio_phy
- g_mdc_period : natural := c_mdio_phy_mdc_period; -- must be a power of 2
+ -- must be a power of 2
+ g_mdc_period : natural := c_mdio_phy_mdc_period;
g_hold_time : natural := c_mdio_phy_hold_time;
g_setup_time : natural := c_mdio_phy_setup_time
);
@@ -60,9 +61,12 @@ entity avs_mdio is
coe_gs_sim_export : in std_logic := '0';
-- MDIO interface
- coe_mdio_phy_mdc_export : out std_logic; -- MDIO PHY serial clock line
- coe_mdio_phy_mdat_in_export : in std_logic; -- MDIO PHY serial data in from line
- coe_mdio_phy_mdat_oen_export : out std_logic; -- MDIO PHY serial data out pull low to line
+ -- MDIO PHY serial clock line
+ coe_mdio_phy_mdc_export : out std_logic;
+ -- MDIO PHY serial data in from line
+ coe_mdio_phy_mdat_in_export : in std_logic;
+ -- MDIO PHY serial data out pull low to line
+ coe_mdio_phy_mdat_oen_export : out std_logic;
---------------------------------------------------------------------------
-- Avalon Clock Input interface: csi_*
@@ -77,13 +81,15 @@ entity avs_mdio is
avs_header_address : in std_logic;
avs_header_write : in std_logic;
avs_header_read : in std_logic;
- avs_header_writedata : in std_logic_vector(c_halfword_w - 1 downto 0); -- use half MM bus width for mdio register
+ -- use half MM bus width for mdio register
+ avs_header_writedata : in std_logic_vector(c_halfword_w - 1 downto 0);
avs_header_readdata : out std_logic_vector(c_halfword_w - 1 downto 0);
-- MM slave MDIO data register
avs_data_address : in std_logic;
avs_data_write : in std_logic;
avs_data_read : in std_logic;
- avs_data_writedata : in std_logic_vector(c_halfword_w - 1 downto 0); -- use half MM bus width for mdio register
+ -- use half MM bus width for mdio register
+ avs_data_writedata : in std_logic_vector(c_halfword_w - 1 downto 0);
avs_data_readdata : out std_logic_vector(c_halfword_w - 1 downto 0);
---------------------------------------------------------------------------
-- Avalon Interrupt Sender interface: ins_*
diff --git a/libraries/io/mdio/src/vhdl/mdio.vhd b/libraries/io/mdio/src/vhdl/mdio.vhd
index 3414cf531d03ac76bac8adb305702acd8de47e42..3f02f62402047d80c5a7fa85cf3a1cbd3b5716e8 100644
--- a/libraries/io/mdio/src/vhdl/mdio.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio.vhd
@@ -42,13 +42,15 @@ entity mdio is
mms_header_address : in std_logic_vector(0 downto 0);
mms_header_write : in std_logic;
mms_header_read : in std_logic;
- mms_header_writedata: in std_logic_vector(c_halfword_w - 1 downto 0); -- 16-bit
+ -- 16-bit
+ mms_header_writedata: in std_logic_vector(c_halfword_w - 1 downto 0);
mms_header_readdata : out std_logic_vector(c_halfword_w - 1 downto 0);
-- MM slave mdio data register
mms_data_address : in std_logic_vector(0 downto 0);
mms_data_write : in std_logic;
mms_data_read : in std_logic;
- mms_data_writedata : in std_logic_vector(c_halfword_w - 1 downto 0); -- 16-bit
+ -- 16-bit
+ mms_data_writedata : in std_logic_vector(c_halfword_w - 1 downto 0);
mms_data_readdata : out std_logic_vector(c_halfword_w - 1 downto 0);
-- Interrupt
ins_mdio_rdy : out std_logic;
@@ -57,8 +59,10 @@ entity mdio is
-- MDIO interface
---------------------------------------------------------------------------
mdc : out std_logic;
- mdat_in : in std_logic; -- tristate buffer input from line
- mdat_oen : out std_logic -- tristate buffer output to line enable
+ -- tristate buffer input from line
+ mdat_in : in std_logic;
+ -- tristate buffer output to line enable
+ mdat_oen : out std_logic
);
end mdio;
diff --git a/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd b/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd
index 4c9e5def3024890c445e8b8da1f2ea674fdf18f6..b017e73ee1e0f05fa707e964ad4b26d9524fc738 100644
--- a/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd
@@ -29,9 +29,12 @@ entity mdio_ctlr is
generic (
g_mdio_prtad : std_logic_vector(c_mdio_phy_hdr_prtad_len - 1 downto 0);
g_mdio_cmd_arr : t_mdio_cmd_arr;
- g_mdio_rst_level : std_logic; -- Active level of MDIO device's reset input
- g_mdio_rst_cycles : natural; -- Number of clock cycles when reset is active
- g_mdio_post_rst_cycles : natural -- Number of post-reset clock cycles before FSM starts command execution
+ -- Active level of MDIO device's reset input
+ g_mdio_rst_level : std_logic;
+ -- Number of clock cycles when reset is active
+ g_mdio_rst_cycles : natural;
+ -- Number of post-reset clock cycles before FSM starts command execution
+ g_mdio_post_rst_cycles : natural
);
port (
rst : in std_logic;
diff --git a/libraries/io/mdio/src/vhdl/mdio_mm.vhd b/libraries/io/mdio/src/vhdl/mdio_mm.vhd
index 676c286d001db22c91d0610c8ec06fa56e4e74ca..10d1eba8222a6bfcf1d28003a6dded8575af199b 100644
--- a/libraries/io/mdio/src/vhdl/mdio_mm.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_mm.vhd
@@ -37,13 +37,15 @@ entity mdio_mm is
mms_header_address : in std_logic_vector(0 downto 0);
mms_header_write : in std_logic;
mms_header_read : in std_logic;
- mms_header_writedata: in std_logic_vector(c_halfword_w - 1 downto 0); -- 16-bit
+ -- 16-bit
+ mms_header_writedata: in std_logic_vector(c_halfword_w - 1 downto 0);
mms_header_readdata : out std_logic_vector(c_halfword_w - 1 downto 0);
-- MM slave mdio data register
mms_data_address : in std_logic_vector(0 downto 0);
mms_data_write : in std_logic;
mms_data_read : in std_logic;
- mms_data_writedata : in std_logic_vector(c_halfword_w - 1 downto 0); -- 16-bit
+ -- 16-bit
+ mms_data_writedata : in std_logic_vector(c_halfword_w - 1 downto 0);
mms_data_readdata : out std_logic_vector(c_halfword_w - 1 downto 0);
-- Interrupt
ins_mdio_rdy : out std_logic;
@@ -52,8 +54,10 @@ entity mdio_mm is
-- MDIO PHY control interface
---------------------------------------------------------------------------
-- MDIO access control
- mdio_en_evt : out std_logic; -- pulse to start new MDIO access
- mdio_done_evt : in std_logic; -- pulse from MDIO access finished
+ -- pulse to start new MDIO access
+ mdio_en_evt : out std_logic;
+ -- pulse from MDIO access finished
+ mdio_done_evt : in std_logic;
-- MDIO header and tx/rx data
mdio_hdr : out std_logic_vector(c_halfword_w - 1 downto 0);
mdio_tx_dat : out std_logic_vector(c_halfword_w - 1 downto 0);
@@ -69,8 +73,10 @@ architecture str of mdio_mm is
nof_dat => 1,
init_sl => 'X');
- signal header_write : std_logic; -- used to issue mdio access enable
- signal data_read : std_logic; -- used to clear mdio access ready interrupt
+ -- used to issue mdio access enable
+ signal header_write : std_logic;
+ -- used to clear mdio access ready interrupt
+ signal data_read : std_logic;
signal reg_header : std_logic_vector(c_halfword_w - 1 downto 0);
signal reg_data : std_logic_vector(c_halfword_w - 1 downto 0);
@@ -78,7 +84,8 @@ architecture str of mdio_mm is
begin
-- MDIO access enable when the MDIO header register is written.
-- Hence for a MDIO write the MDIO data register needs to have been written first.
- header_write <= mms_header_write; -- only one reg, so no need to check mms_header_address
+ -- only one reg, so no need to check mms_header_address
+ header_write <= mms_header_write;
u_mdio_en : entity common_lib.common_request
port map (
@@ -90,7 +97,8 @@ begin
-- MDIO ready interrupt when the MDIO PHY access has been done
-- Clear the interrupt by reading the MDIO data register
- data_read <= mms_data_read; -- only one reg, so no need to check mms_data_address
+ -- only one reg, so no need to check mms_data_address
+ data_read <= mms_data_read;
u_mdio_done : entity common_lib.common_switch
port map (
@@ -105,7 +113,8 @@ begin
mdio_hdr <= reg_header;
mdio_tx_dat <= reg_data;
- reg_data_rd <= mdio_rx_dat; -- always read rx_dat
+ -- always read rx_dat
+ reg_data_rd <= mdio_rx_dat;
u_reg_header : entity common_lib.common_reg_r_w
generic map (
diff --git a/libraries/io/mdio/src/vhdl/mdio_phy.vhd b/libraries/io/mdio/src/vhdl/mdio_phy.vhd
index 3f6b278be998fd3fde9f34dfe3bd4a9797ee1c95..0d8ae9863f7de3eb225c9f792e25e6e786833da0 100644
--- a/libraries/io/mdio/src/vhdl/mdio_phy.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_phy.vhd
@@ -40,9 +40,12 @@ entity mdio_phy is
rst : in std_logic;
clk : in std_logic;
- mdio_en_evt : in std_logic; -- going high starts the MDC/MDIO access, then low to prepare for next enable,
- mdio_done_evt : out std_logic; -- ingores next enable until MDC/MDIO access done pulse has happened
- mdio_done : out std_logic; -- Same as mdio_done_evt but remains high until acknowledged
+ -- going high starts the MDC/MDIO access, then low to prepare for next enable,
+ mdio_en_evt : in std_logic;
+ -- ingores next enable until MDC/MDIO access done pulse has happened
+ mdio_done_evt : out std_logic;
+ -- Same as mdio_done_evt but remains high until acknowledged
+ mdio_done : out std_logic;
mdio_done_ack_evt : in std_logic := '0';
hdr : in std_logic_vector(c_halfword_w - 1 downto 0);
@@ -51,15 +54,18 @@ entity mdio_phy is
-- External clock and serial data.
mdc : out std_logic;
- mdat_in : in std_logic; -- tristate buffer input from line
- mdat_oen : out std_logic -- tristate buffer output to line enable
+ -- tristate buffer input from line
+ mdat_in : in std_logic;
+ -- tristate buffer output to line enable
+ mdat_oen : out std_logic
-- no need for mdat_out, only enable for output '0', else rely on external pull up for output '1'
);
end mdio_phy;
architecture rtl of mdio_phy is
-- Simulation constants for when gs_sim=TRUE
- constant c_sim_mdc_period : natural := 8; -- must be a power of 2 and <= g_mdio_phy.mdc_period
+ -- must be a power of 2 and <= g_mdio_phy.mdc_period
+ constant c_sim_mdc_period : natural := 8;
constant c_sim_mdc_cnt_high : natural := ceil_log2(c_sim_mdc_period) - 1;
constant c_sim_hold_time : natural := 3;
constant c_sim_setup_time : natural := 2;
@@ -69,7 +75,8 @@ architecture rtl of mdio_phy is
constant c_read_msg_length : natural := 14;
constant c_receive_msg_length : natural := 19;
- constant c_hdr_rd_bit : natural := 13; -- hdr[15: 0] = st(2) & op(2) & prtad(5) & devad(5) & ta(2)
+ -- hdr[15: 0] = st(2) & op(2) & prtad(5) & devad(5) & ta(2)
+ constant c_hdr_rd_bit : natural := 13;
-- hdr[13:12] = op[1:0] and op[1]='1' indicates read access
constant c_ta : std_logic_vector := "10";
@@ -214,7 +221,8 @@ begin
end if;
when s_add_mdc =>
- bit_cnt_rst <= '1'; --
+ --
+ bit_cnt_rst <= '1';
if tx_en = '1' then
nxt_state <= s_done;
end if;
diff --git a/libraries/io/mdio/src/vhdl/mdio_phy_reg.vhd b/libraries/io/mdio/src/vhdl/mdio_phy_reg.vhd
index c516148bc7f820b7664493eb4b56fa3ca918420a..4e546f77f4eef106b57c504702501a92473cedcb 100644
--- a/libraries/io/mdio/src/vhdl/mdio_phy_reg.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_phy_reg.vhd
@@ -34,8 +34,10 @@ entity mdio_phy_reg is
mdio_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in mdio_clk domain
mdio_en_evt : out std_logic;
@@ -51,7 +53,8 @@ end mdio_phy_reg;
architecture rtl of mdio_phy_reg is
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(5),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 5,
init_sl => '0');
-- Registers in mm_clk domain
@@ -100,20 +103,24 @@ begin
mm_tx_dat <= sla_in.wrdata(c_halfword_w - 1 downto 0);
when 4 =>
mm_done_ack_evt <= sla_in.wrdata(0);
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read Block Sync
when 2 =>
sla_out.rddata(c_halfword_w - 1 downto 0) <= mm_rx_dat;
when 3 =>
sla_out.rddata(0) <= mm_done;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/libraries/io/mdio/src/vhdl/mdio_pkg.vhd b/libraries/io/mdio/src/vhdl/mdio_pkg.vhd
index a684ac0bb7adce068edd1c8b81d954b1fc308f97..47b94502330ccc03daa154f648039e71ee21598a 100644
--- a/libraries/io/mdio/src/vhdl/mdio_pkg.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_pkg.vhd
@@ -44,16 +44,25 @@ package mdio_pkg is
c_mdio_phy_hdr_devad_len +
c_mdio_phy_hdr_ta_len;
- constant c_mdio_phy_hdr_st : std_logic_vector(c_mdio_phy_hdr_st_len - 1 downto 0) := "00"; -- start of frame
- constant c_mdio_phy_hdr_op_addr : std_logic_vector(c_mdio_phy_hdr_op_addr_len - 1 downto 0) := "00"; -- operation code address
- constant c_mdio_phy_hdr_op_wr : std_logic_vector(c_mdio_phy_hdr_op_wr_len - 1 downto 0) := "01"; -- operation code write
- constant c_mdio_phy_hdr_op_rd : std_logic_vector(c_mdio_phy_hdr_op_rd_len - 1 downto 0) := "11"; -- operation code read
- constant c_mdio_phy_hdr_op_rd_incr : std_logic_vector(c_mdio_phy_hdr_op_rd_incr_len - 1 downto 0) := "10"; -- operation code read increment
- constant c_mdio_phy_hdr_prtad : std_logic_vector(c_mdio_phy_hdr_prtad_len - 1 downto 0) := "00000"; -- port address (example)
- constant c_mdio_phy_hdr_devad : std_logic_vector(c_mdio_phy_hdr_devad_len - 1 downto 0) := "00001"; -- device address (example)
- constant c_mdio_phy_hdr_ta : std_logic_vector(c_mdio_phy_hdr_ta_len - 1 downto 0) := "10"; -- turn around
-
- constant c_mdio_phy_mdc_period : natural := 256; -- must be a power of 2
+ -- start of frame
+ constant c_mdio_phy_hdr_st : std_logic_vector(c_mdio_phy_hdr_st_len - 1 downto 0) := "00";
+ -- operation code address
+ constant c_mdio_phy_hdr_op_addr : std_logic_vector(c_mdio_phy_hdr_op_addr_len - 1 downto 0) := "00";
+ -- operation code write
+ constant c_mdio_phy_hdr_op_wr : std_logic_vector(c_mdio_phy_hdr_op_wr_len - 1 downto 0) := "01";
+ -- operation code read
+ constant c_mdio_phy_hdr_op_rd : std_logic_vector(c_mdio_phy_hdr_op_rd_len - 1 downto 0) := "11";
+ -- operation code read increment
+ constant c_mdio_phy_hdr_op_rd_incr : std_logic_vector(c_mdio_phy_hdr_op_rd_incr_len - 1 downto 0) := "10";
+ -- port address (example)
+ constant c_mdio_phy_hdr_prtad : std_logic_vector(c_mdio_phy_hdr_prtad_len - 1 downto 0) := "00000";
+ -- device address (example)
+ constant c_mdio_phy_hdr_devad : std_logic_vector(c_mdio_phy_hdr_devad_len - 1 downto 0) := "00001";
+ -- turn around
+ constant c_mdio_phy_hdr_ta : std_logic_vector(c_mdio_phy_hdr_ta_len - 1 downto 0) := "10";
+
+ -- must be a power of 2
+ constant c_mdio_phy_mdc_period : natural := 256;
constant c_mdio_phy_hold_time : natural := 10;
constant c_mdio_phy_setup_time : natural := 2;
@@ -70,9 +79,12 @@ package mdio_pkg is
type t_mdio_cmd_arr is array (integer range <>) of t_mdio_cmd;
type t_c_mdio_phy is record
- mdc_period : natural; -- clk period * 256 /2 = mdc period, MDIO slave acts on rising edge
- hold_time : natural; -- clk period * 10 = write hold time, must be > 10 ns, choose some larger margin
- setup_time : natural; -- read mdat_in is stable within 300 ns of rising mdc edge, therefore
+ -- clk period * 256 /2 = mdc period, MDIO slave acts on rising edge
+ mdc_period : natural;
+ -- clk period * 10 = write hold time, must be > 10 ns, choose some larger margin
+ hold_time : natural;
+ -- read mdat_in is stable within 300 ns of rising mdc edge, therefore
+ setup_time : natural;
-- choose g_setup_time to fit (mdc period/2) + g_setup_time > 300 ns.
-- typically choose mdc period > 2*300 ns, then g_setup_time can be 0.
end record;
diff --git a/libraries/io/mdio/src/vhdl/mdio_vitesse_vsc8486_pkg.vhd b/libraries/io/mdio/src/vhdl/mdio_vitesse_vsc8486_pkg.vhd
index 5bbe7c3651be99d0c9826334efb10331bd00f11d..83520382a71b5c81561fa9c4b8453e1dc39cf2da 100644
--- a/libraries/io/mdio/src/vhdl/mdio_vitesse_vsc8486_pkg.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_vitesse_vsc8486_pkg.vhd
@@ -38,42 +38,60 @@ package mdio_vitesse_vsc8486_pkg is
-- XAUI LOOPBACK B
-- ===============
- constant c_mdio_vsc8486_lpbk_xaui_b_dev4 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"800E"; -- bit 13 of this reg.
- constant c_mdio_vsc8486_lpbk_xaui_b_dev4_en : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"3800"; -- b'00111000 00000000
- constant c_mdio_vsc8486_lpbk_xaui_b_dev4_dis : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"1800"; -- b'00011000 00000000
+ -- bit 13 of this reg.
+ constant c_mdio_vsc8486_lpbk_xaui_b_dev4 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"800E";
+ -- b'00111000 00000000
+ constant c_mdio_vsc8486_lpbk_xaui_b_dev4_en : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"3800";
+ -- b'00011000 00000000
+ constant c_mdio_vsc8486_lpbk_xaui_b_dev4_dis : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"1800";
-- XAUI LOOPBACK C
-- ===============mdio_vitesse_vsc8486_pkg
- constant c_mdio_vsc8486_lpbk_xaui_c_dev4 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"800F"; -- bit 2 of this reg.
- constant c_mdio_vsc8486_lpbk_xaui_c_dev4_en : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0664"; -- b'00000110 01100100
- constant c_mdio_vsc8486_lpbk_xaui_c_dev4_dis : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0660"; -- b'00000110 01100000
+ -- bit 2 of this reg.
+ constant c_mdio_vsc8486_lpbk_xaui_c_dev4 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"800F";
+ -- b'00000110 01100100
+ constant c_mdio_vsc8486_lpbk_xaui_c_dev4_en : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0664";
+ -- b'00000110 01100000
+ constant c_mdio_vsc8486_lpbk_xaui_c_dev4_dis : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0660";
-- XAUI LOOPBACK E
-- ===============
- constant c_mdio_vsc8486_lpbk_xaui_e_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8005"; -- bit 2 of this reg.
- constant c_mdio_vsc8486_lpbk_xaui_e_dev3_en : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0004"; -- b'00000000 00000100
- constant c_mdio_vsc8486_lpbk_xaui_e_dev3_dis : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0000"; -- b'00000000 00000000
+ -- bit 2 of this reg.
+ constant c_mdio_vsc8486_lpbk_xaui_e_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8005";
+ -- b'00000000 00000100
+ constant c_mdio_vsc8486_lpbk_xaui_e_dev3_en : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0004";
+ -- b'00000000 00000000
+ constant c_mdio_vsc8486_lpbk_xaui_e_dev3_dis : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0000";
-- XAUI LOOPBACK G
-- ===============
- constant c_mdio_vsc8486_lpbk_xaui_g_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0000"; -- bit 14 of this reg.
- constant c_mdio_vsc8486_lpbk_xaui_g_dev3_en : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"6200"; -- b'01100010 00000000
- constant c_mdio_vsc8486_lpbk_xaui_g_dev3_dis : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"2200"; -- b'00100010 00000000
+ -- bit 14 of this reg.
+ constant c_mdio_vsc8486_lpbk_xaui_g_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0000";
+ -- b'01100010 00000000
+ constant c_mdio_vsc8486_lpbk_xaui_g_dev3_en : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"6200";
+ -- b'00100010 00000000
+ constant c_mdio_vsc8486_lpbk_xaui_g_dev3_dis : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"2200";
-- XAUI LOOPBACK J
-- ===============
- constant c_mdio_vsc8486_lpbk_xaui_j_dev2 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0000"; -- bit 14 of this reg.
- constant c_mdio_vsc8486_lpbk_xaui_j_dev2_en : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"6040"; -- b'01100000 01000000
- constant c_mdio_vsc8486_lpbk_xaui_j_dev2_dis : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"2040"; -- b'00100000 01000000
+ -- bit 14 of this reg.
+ constant c_mdio_vsc8486_lpbk_xaui_j_dev2 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0000";
+ -- b'01100000 01000000
+ constant c_mdio_vsc8486_lpbk_xaui_j_dev2_en : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"6040";
+ -- b'00100000 01000000
+ constant c_mdio_vsc8486_lpbk_xaui_j_dev2_dis : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"2040";
-- XFI loopbacks, closest to XFI side first: K, H, F, D, A
-- ========================================================
-- XFI LOOPBACK K
-- ==============
- constant c_mdio_vsc8486_lpbk_xfi_k_dev1 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8000"; -- bit 8 of this reg. (0 to enable)
- constant c_mdio_vsc8486_lpbk_xfi_k_dev1_en : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"B4DF"; -- b'10110100 11011111
- constant c_mdio_vsc8486_lpbk_xfi_k_dev1_dis : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"B5DF"; -- b'10110101 11011111
+ -- bit 8 of this reg. (0 to enable)
+ constant c_mdio_vsc8486_lpbk_xfi_k_dev1 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8000";
+ -- b'10110100 11011111
+ constant c_mdio_vsc8486_lpbk_xfi_k_dev1_en : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"B4DF";
+ -- b'10110101 11011111
+ constant c_mdio_vsc8486_lpbk_xfi_k_dev1_dis : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"B5DF";
-- RX EQUALIZATION
-- ===============
@@ -82,9 +100,12 @@ package mdio_vitesse_vsc8486_pkg is
-- EPCS
-- ====
- constant c_mdio_vsc8486_epcs_ovr_frc_dev1 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"E605"; -- bit 11 to override pin value, bit 10 to enable EPCS
- constant c_mdio_vsc8486_epcs_ovr_frc_dev1_en : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0C00"; -- b'00001100 00000000
- constant c_mdio_vsc8486_epcs_ovr_frc_dev1_dis : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0000"; -- b'00000000 00000000
+ -- bit 11 to override pin value, bit 10 to enable EPCS
+ constant c_mdio_vsc8486_epcs_ovr_frc_dev1 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"E605";
+ -- b'00001100 00000000
+ constant c_mdio_vsc8486_epcs_ovr_frc_dev1_en : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0C00";
+ -- b'00000000 00000000
+ constant c_mdio_vsc8486_epcs_ovr_frc_dev1_dis : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"0000";
-- LEDs
-- ====
@@ -111,12 +132,18 @@ package mdio_vitesse_vsc8486_pkg is
constant c_mdio_vsc8486_pcs_rx_drop_cnt_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"800F";
-- PCS (PMA clock domain = read side of TX FIFO = write side of RX FIFO)
- constant c_mdio_vsc8486_pcs_tx_seqerr_cnt_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8010"; -- PCS TX sequencing error count
- constant c_mdio_vsc8486_pcs_rx_seqerr_cnt_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8011"; -- PCS RX sequencing error count
- constant c_mdio_vsc8486_pcs_tx_blkerr_cnt_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8012"; -- PCS TX block encode error count
- constant c_mdio_vsc8486_pcs_rx_blkerr_cnt_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8013"; -- PCS RX block decode error count
- constant c_mdio_vsc8486_pcs_tx_charerr_cnt_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8014"; -- PCS TX char encode error count
- constant c_mdio_vsc8486_pcs_rx_charerr_cnt_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8015"; -- PCS RX char decode error count
+ -- PCS TX sequencing error count
+ constant c_mdio_vsc8486_pcs_tx_seqerr_cnt_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8010";
+ -- PCS RX sequencing error count
+ constant c_mdio_vsc8486_pcs_rx_seqerr_cnt_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8011";
+ -- PCS TX block encode error count
+ constant c_mdio_vsc8486_pcs_tx_blkerr_cnt_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8012";
+ -- PCS RX block decode error count
+ constant c_mdio_vsc8486_pcs_rx_blkerr_cnt_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8013";
+ -- PCS TX char encode error count
+ constant c_mdio_vsc8486_pcs_tx_charerr_cnt_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8014";
+ -- PCS RX char decode error count
+ constant c_mdio_vsc8486_pcs_rx_charerr_cnt_dev3 : std_logic_vector(c_mdio_phy_data_width - 1 downto 0) := x"8015";
-- PHY XS STATUS 3
-- ===============
diff --git a/libraries/io/mdio/tb/vhdl/mmd_slave.vhd b/libraries/io/mdio/tb/vhdl/mmd_slave.vhd
index 9f0b403713febb4ed344527953ee6221177e5d2f..950658d033c628b26bf60c94344e97b31028c274 100644
--- a/libraries/io/mdio/tb/vhdl/mmd_slave.vhd
+++ b/libraries/io/mdio/tb/vhdl/mmd_slave.vhd
@@ -28,22 +28,28 @@ entity mmd_slave is
g_st : std_logic_vector(1 downto 0) := "00";
g_prtad : std_logic_vector(4 downto 0) := "00000";
g_devad : std_logic_vector(4 downto 0) := "00001";
- g_quick : boolean := false; -- TRUE to support MDIO quick access using devad[4:0] as register address
- g_reg_addr : natural := 16#A001#; -- support only this one PHY register address
- g_reg_dat : natural := 16#1234#; -- initial PHY register value
+ -- TRUE to support MDIO quick access using devad[4:0] as register address
+ g_quick : boolean := false;
+ -- support only this one PHY register address
+ g_reg_addr : natural := 16#A001#;
+ -- initial PHY register value
+ g_reg_dat : natural := 16#1234#;
g_reg_w : natural := 16
);
port(
mdc : in std_logic;
mdio : inout std_logic;
- addr : out std_logic_vector(g_reg_w - 1 downto 0); -- access address
- reg_dat : out std_logic_vector(g_reg_w - 1 downto 0) -- the one data register
+ -- access address
+ addr : out std_logic_vector(g_reg_w - 1 downto 0);
+ -- the one data register
+ reg_dat : out std_logic_vector(g_reg_w - 1 downto 0)
);
end mmd_slave;
architecture beh of mmd_slave is
constant c_preamble_len : natural := 32;
- constant c_preamble_timeout : natural := 1; -- >= 0
+ -- >= 0
+ constant c_preamble_timeout : natural := 1;
constant c_header_st_len : natural := 2;
constant c_header_op_len : natural := 2 + 2;
constant c_header_prtad_len : natural := 2 + 2 + 5;
@@ -51,10 +57,14 @@ architecture beh of mmd_slave is
constant c_header_ta_len : natural := 2 + 2 + 5 + 5 + 2;
constant c_data_len : natural := 16;
- constant c_hdr_op_addr : std_logic_vector(1 downto 0) := "00"; -- operation code address (typically not used when g_quick = TRUE)
- constant c_hdr_op_wr : std_logic_vector(1 downto 0) := "01"; -- operation code write
- constant c_hdr_op_rd : std_logic_vector(1 downto 0) := "11"; -- operation code read
- constant c_hdr_op_rd_incr : std_logic_vector(1 downto 0) := "10"; -- operation code read increment
+ -- operation code address (typically not used when g_quick = TRUE)
+ constant c_hdr_op_addr : std_logic_vector(1 downto 0) := "00";
+ -- operation code write
+ constant c_hdr_op_wr : std_logic_vector(1 downto 0) := "01";
+ -- operation code read
+ constant c_hdr_op_rd : std_logic_vector(1 downto 0) := "11";
+ -- operation code read increment
+ constant c_hdr_op_rd_incr : std_logic_vector(1 downto 0) := "10";
type t_mdio_state is (s_idle, s_preamble, s_st, s_header, s_header_ta_rd, s_write, s_read);
@@ -71,7 +81,8 @@ begin
addr <= i_addr;
reg_dat <= i_reg_dat;
- mdin <= not(not(mdio)); -- force 'L' to '0' and 'H' to '1' to ensure proper value interpretation
+ -- force 'L' to '0' and 'H' to '1' to ensure proper value interpretation
+ mdin <= not(not(mdio));
p_mmd : process (mdc)
variable v_bit_cnt : natural := 0;
@@ -143,7 +154,8 @@ begin
when c_hdr_op_addr => op_ad <= '1';
when c_hdr_op_wr => op_wr <= '1';
when c_hdr_op_rd => op_rd <= '1';
- when others => op_rd <= '1'; -- no support for op rd incr
+ -- no support for op rd incr
+ when others => op_rd <= '1';
end case;
when c_header_prtad_len =>
if v_prtad /= g_prtad then
@@ -165,7 +177,8 @@ begin
when c_header_ta_len =>
v_bit_cnt := 0;
state <= s_write;
- when others => null; -- nothing to do, continue
+ -- nothing to do, continue
+ when others => null;
end case;
end if;
@@ -186,7 +199,8 @@ begin
if v_bit_cnt = c_data_len then
if op_ad = '1' then
i_addr <= v_dat;
- else -- op_wr='1'
+ -- op_wr='1'
+ else
if g_quick = false then
if unsigned(i_addr) = to_unsigned(g_reg_addr, g_reg_w) then
i_reg_dat <= v_dat;
@@ -212,7 +226,8 @@ begin
end if;
end if;
- when others => -- can not occur
+ -- can not occur
+ when others =>
assert false report "Unknown MDIO state." severity FAILURE;
end case;
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio.vhd
index 1822ffda1130061ed60360d7d5af3f48ce1bd347..c870e2c6c994b58eed13668ccdda496bd418a17c 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio.vhd
@@ -39,8 +39,10 @@ architecture tb of tb_mdio is
constant c_op_wr : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_op_wr;
constant c_op_rd : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_op_rd;
constant c_op_rd_incr : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_op_rd_incr;
- constant c_prtad : std_logic_vector(4 downto 0) := "00000"; -- port address (example)
- constant c_devad : std_logic_vector(4 downto 0) := "00001"; -- device address (example)
+ -- port address (example)
+ constant c_prtad : std_logic_vector(4 downto 0) := "00000";
+ -- device address (example)
+ constant c_devad : std_logic_vector(4 downto 0) := "00001";
constant c_ta : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_ta;
constant c_hdr_addr : std_logic_vector(c_halfword_w - 1 downto 0) := c_st & c_op_addr & c_prtad & c_devad & c_ta;
@@ -79,26 +81,32 @@ architecture tb of tb_mdio is
constant c_slave_reg_addr : natural := 16#A001#;
constant c_slave_reg_data : natural := 16#1234#;
- signal slave_addr : std_logic_vector(c_halfword_w - 1 downto 0); -- MDIO access address
- signal slave_reg_addr : std_logic_vector(c_halfword_w - 1 downto 0); -- the one data register address
- signal slave_reg_dat : std_logic_vector(c_halfword_w - 1 downto 0); -- the one data register data value
+ -- MDIO access address
+ signal slave_addr : std_logic_vector(c_halfword_w - 1 downto 0);
+ -- the one data register address
+ signal slave_reg_addr : std_logic_vector(c_halfword_w - 1 downto 0);
+ -- the one data register data value
+ signal slave_reg_dat : std_logic_vector(c_halfword_w - 1 downto 0);
begin
-- run 50 us
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 3;
- mdio <= 'H'; -- pull up
+ -- pull up
+ mdio <= 'H';
-- run 1 us
p_in_stimuli : process
begin
- mms_header_address <= (others => '0'); -- = "0"
+ -- = "0"
+ mms_header_address <= (others => '0');
mms_header_write <= '0';
mms_header_read <= '0';
mms_header_writedata <= (others => '0');
- mms_data_address <= (others => '0'); -- = "0"
+ -- = "0"
+ mms_data_address <= (others => '0');
mms_data_write <= '0';
mms_data_read <= '0';
mms_data_writedata <= (others => '0');
@@ -109,31 +117,37 @@ begin
-- write_MMD
----------------------------------------------------------------------------
-- write PHY register address
- mms_data_writedata <= c_phy_addr; -- first write data (PHY address)
+ -- first write data (PHY address)
+ mms_data_writedata <= c_phy_addr;
mms_data_write <= '1';
wait until rising_edge(clk);
mms_data_write <= '0';
- mms_header_writedata <= c_hdr_addr; -- then write header (op=addr), enables the MDIO access
+ -- then write header (op=addr), enables the MDIO access
+ mms_header_writedata <= c_hdr_addr;
mms_header_write <= '1';
wait until rising_edge(clk);
mms_header_write <= '0';
while ins_mdio_rdy = '0' loop wait until rising_edge(clk); end loop;
- mms_data_read <= '1'; -- read data to acknowledge MDIO done interrupt
+ -- read data to acknowledge MDIO done interrupt
+ mms_data_read <= '1';
wait until rising_edge(clk);
mms_data_read <= '0';
for I in 0 to c_delay loop wait until rising_edge(clk); end loop;
-- write PHY register data
- mms_data_writedata <= c_phy_data; -- first write data (PHY data)
+ -- first write data (PHY data)
+ mms_data_writedata <= c_phy_data;
mms_data_write <= '1';
wait until rising_edge(clk);
mms_data_write <= '0';
- mms_header_writedata <= c_hdr_wr; -- then write header (op=wr), enables the MDIO access
+ -- then write header (op=wr), enables the MDIO access
+ mms_header_writedata <= c_hdr_wr;
mms_header_write <= '1';
wait until rising_edge(clk);
mms_header_write <= '0';
while ins_mdio_rdy = '0' loop wait until rising_edge(clk); end loop;
- mms_data_read <= '1'; -- read data to acknowledge the MDIO done interrupt
+ -- read data to acknowledge the MDIO done interrupt
+ mms_data_read <= '1';
wait until rising_edge(clk);
mms_data_read <= '0';
for I in 0 to c_delay loop wait until rising_edge(clk); end loop;
@@ -142,27 +156,32 @@ begin
-- read_MMD
----------------------------------------------------------------------------
-- write PHY register address
- mms_data_writedata <= c_phy_addr; -- first write data (PHY address)
+ -- first write data (PHY address)
+ mms_data_writedata <= c_phy_addr;
mms_data_write <= '1';
wait until rising_edge(clk);
mms_data_write <= '0';
- mms_header_writedata <= c_hdr_addr; -- then write header (op=addr), enables the MDIO access
+ -- then write header (op=addr), enables the MDIO access
+ mms_header_writedata <= c_hdr_addr;
mms_header_write <= '1';
wait until rising_edge(clk);
mms_header_write <= '0';
while ins_mdio_rdy = '0' loop wait until rising_edge(clk); end loop;
- mms_data_read <= '1'; -- read data to acknowledge the MDIO done interrupt
+ -- read data to acknowledge the MDIO done interrupt
+ mms_data_read <= '1';
wait until rising_edge(clk);
mms_data_read <= '0';
for I in 0 to c_delay loop wait until rising_edge(clk); end loop;
-- read PHY register data
- mms_header_writedata <= c_hdr_rd; -- write header (op=rd) to enable the read PHY data access
+ -- write header (op=rd) to enable the read PHY data access
+ mms_header_writedata <= c_hdr_rd;
mms_header_write <= '1';
wait until rising_edge(clk);
mms_header_write <= '0';
while ins_mdio_rdy = '0' loop wait until rising_edge(clk); end loop;
- mms_data_read <= '1'; -- read data to acknowledge the interrupt
+ -- read data to acknowledge the interrupt
+ mms_data_read <= '1';
wait until rising_edge(clk);
mms_data_read <= '0';
for I in 0 to c_delay loop wait until rising_edge(clk); end loop;
@@ -179,7 +198,8 @@ begin
wait;
end process;
- phy_readdata <= mms_data_readdata; -- capture read PHY data
+ -- capture read PHY data
+ phy_readdata <= mms_data_readdata;
-- MDIO master
u_mdio : entity work.mdio
@@ -214,8 +234,10 @@ begin
port map (
dat_inout => mdio,
dat_in_from_line => mdat_in,
- dat_out_to_line => '0', -- for output '1' rely on external pull up, only
- dat_out_en => mdat_oen -- pull low when mdat_oen (so implicitely mdat_out='0')
+ -- for output '1' rely on external pull up, only
+ dat_out_to_line => '0',
+ -- pull low when mdat_oen (so implicitely mdat_out='0')
+ dat_out_en => mdat_oen
);
-- MDIO slave
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd
index f6974791671f9991419df444531bc808879e0ba2..f16ab3e22e8a6fe47dc4acfaa2a7ed6b9c1b3f78 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd
@@ -39,8 +39,10 @@ architecture tb of tb_mdio_phy is
constant c_op_wr : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_op_wr;
constant c_op_rd : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_op_rd;
constant c_op_rd_incr : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_op_rd_incr;
- constant c_prtad : std_logic_vector(4 downto 0) := "00000"; -- port address (example)
- constant c_devad : std_logic_vector(4 downto 0) := "00001"; -- device address (example)
+ -- port address (example)
+ constant c_prtad : std_logic_vector(4 downto 0) := "00000";
+ -- device address (example)
+ constant c_devad : std_logic_vector(4 downto 0) := "00001";
constant c_ta : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_ta;
constant c_hdr_wraddr : std_logic_vector(c_halfword_w - 1 downto 0) := c_st & c_op_addr & c_prtad & c_devad & c_ta;
@@ -69,16 +71,20 @@ architecture tb of tb_mdio_phy is
constant c_slave_reg_addr : natural := 16#A001#;
constant c_slave_reg_data : natural := 16#1234#;
- signal slave_addr : std_logic_vector(c_halfword_w - 1 downto 0); -- MDIO access address
- signal slave_reg_addr : std_logic_vector(c_halfword_w - 1 downto 0); -- the one data register address
- signal slave_reg_dat : std_logic_vector(c_halfword_w - 1 downto 0); -- the one data register data value
+ -- MDIO access address
+ signal slave_addr : std_logic_vector(c_halfword_w - 1 downto 0);
+ -- the one data register address
+ signal slave_reg_addr : std_logic_vector(c_halfword_w - 1 downto 0);
+ -- the one data register data value
+ signal slave_reg_dat : std_logic_vector(c_halfword_w - 1 downto 0);
begin
-- run 50 us
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 3;
- mdio <= 'H'; -- pull up
+ -- pull up
+ mdio <= 'H';
-- run 1 us
p_in_stimuli : process
@@ -200,8 +206,10 @@ begin
port map (
dat_inout => mdio,
dat_in_from_line => mdat_in,
- dat_out_to_line => '0', -- for output '1' rely on external pull up, only
- dat_out_en => mdat_oen -- pull low when mdat_oen (so implicitely mdat_out='0')
+ -- for output '1' rely on external pull up, only
+ dat_out_to_line => '0',
+ -- pull low when mdat_oen (so implicitely mdat_out='0')
+ dat_out_en => mdat_oen
);
-- MDIO slave
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd
index 9b5a2bcdd29f38359e869f3fe86dd780455a5e49..91628cb28b78fccb4cd08fedc280d4cf43ced154 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd
@@ -39,8 +39,10 @@ architecture tb of tb_mdio_phy_ctlr is
constant c_op_wr : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_op_wr;
constant c_op_rd : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_op_rd;
constant c_op_rd_incr : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_op_rd_incr;
- constant c_prtad : std_logic_vector(4 downto 0) := "00000"; -- port address (example)
- constant c_devad : std_logic_vector(4 downto 0) := "00001"; -- device address (example)
+ -- port address (example)
+ constant c_prtad : std_logic_vector(4 downto 0) := "00000";
+ -- device address (example)
+ constant c_devad : std_logic_vector(4 downto 0) := "00001";
constant c_ta : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_ta;
constant c_hdr_wraddr : std_logic_vector(c_halfword_w - 1 downto 0) := c_st & c_op_addr & c_prtad & c_devad & c_ta;
@@ -71,9 +73,12 @@ architecture tb of tb_mdio_phy_ctlr is
constant c_slave_reg_addr : natural := 16#A001#;
constant c_slave_reg_data : natural := 16#1234#;
- signal slave_addr : std_logic_vector(c_halfword_w - 1 downto 0); -- MDIO access address
- signal slave_reg_addr : std_logic_vector(c_halfword_w - 1 downto 0); -- the one data register address
- signal slave_reg_dat : std_logic_vector(c_halfword_w - 1 downto 0); -- the one data register data value
+ -- MDIO access address
+ signal slave_addr : std_logic_vector(c_halfword_w - 1 downto 0);
+ -- the one data register address
+ signal slave_reg_addr : std_logic_vector(c_halfword_w - 1 downto 0);
+ -- the one data register data value
+ signal slave_reg_dat : std_logic_vector(c_halfword_w - 1 downto 0);
-- Command sequence for mdio_ctlr to auto execute
-- ==============================================
@@ -87,7 +92,8 @@ begin
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 3;
- mdio <= 'H'; -- pull up
+ -- pull up
+ mdio <= 'H';
p_verify : process
begin
@@ -155,8 +161,10 @@ begin
port map (
dat_inout => mdio,
dat_in_from_line => mdat_in,
- dat_out_to_line => '0', -- for output '1' rely on external pull up, only
- dat_out_en => mdat_oen -- pull low when mdat_oen (so implicitely mdat_out='0')
+ -- for output '1' rely on external pull up, only
+ dat_out_to_line => '0',
+ -- pull low when mdat_oen (so implicitely mdat_out='0')
+ dat_out_en => mdat_oen
);
-- MDIO slave
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd
index 0ce05943aca1e8e0aa2376752ac60b358be77e7d..00ae3865284f4284bd3c6355378b5ccfc8ac5a72 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd
@@ -42,8 +42,10 @@ architecture tb of tb_mdio_phy_reg is
constant c_op_wr : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_op_wr;
constant c_op_rd : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_op_rd;
constant c_op_rd_incr : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_op_rd_incr;
- constant c_prtad : std_logic_vector(4 downto 0) := "00000"; -- port address (example)
- constant c_devad : std_logic_vector(4 downto 0) := "00001"; -- device address (example)
+ -- port address (example)
+ constant c_prtad : std_logic_vector(4 downto 0) := "00000";
+ -- device address (example)
+ constant c_devad : std_logic_vector(4 downto 0) := "00001";
constant c_ta : std_logic_vector(1 downto 0) := c_mdio_phy_hdr_ta;
constant c_hdr_addr : std_logic_vector(c_halfword_w - 1 downto 0) := c_st & c_op_addr & c_prtad & c_devad & c_ta;
@@ -75,9 +77,12 @@ architecture tb of tb_mdio_phy_reg is
constant c_slave_reg_addr : natural := 16#A001#;
constant c_slave_reg_data : natural := 16#1234#;
- signal slave_addr : std_logic_vector(c_halfword_w - 1 downto 0); -- MDIO access address
- signal slave_reg_addr : std_logic_vector(c_halfword_w - 1 downto 0); -- the one data register address
- signal slave_reg_dat : std_logic_vector(c_halfword_w - 1 downto 0); -- the one data register data value
+ -- MDIO access address
+ signal slave_addr : std_logic_vector(c_halfword_w - 1 downto 0);
+ -- the one data register address
+ signal slave_reg_addr : std_logic_vector(c_halfword_w - 1 downto 0);
+ -- the one data register data value
+ signal slave_reg_dat : std_logic_vector(c_halfword_w - 1 downto 0);
signal mdio_mosi : t_mem_mosi;
signal mdio_miso : t_mem_miso;
@@ -95,7 +100,8 @@ begin
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 3;
- mdio <= 'H'; -- pull up
+ -- pull up
+ mdio <= 'H';
p_in_stimuli : process
begin
@@ -108,50 +114,62 @@ begin
-- write_MMD
----------------------------------------------------------------------------
-- write PHY register address
- proc_mem_mm_bus_wr(c_ofs_tx_dat, c_phy_addr, clk, mdio_mosi); -- Write data (PHY address)
+ -- Write data (PHY address)
+ proc_mem_mm_bus_wr(c_ofs_tx_dat, c_phy_addr, clk, mdio_mosi);
proc_common_wait_some_cycles(clk, 10);
- proc_mem_mm_bus_wr(c_ofs_hdr, c_hdr_addr, clk, mdio_mosi); -- then write header (op=addr), enables the MDIO access
+ -- then write header (op=addr), enables the MDIO access
+ proc_mem_mm_bus_wr(c_ofs_hdr, c_hdr_addr, clk, mdio_mosi);
proc_common_wait_some_cycles(clk, 10);
while done = '0' loop wait until rising_edge(clk); end loop;
- proc_mem_mm_bus_wr(c_ofs_done_ack_evt, 1, clk, mdio_mosi); -- Acknowledge done
+ -- Acknowledge done
+ proc_mem_mm_bus_wr(c_ofs_done_ack_evt, 1, clk, mdio_mosi);
proc_common_wait_some_cycles(clk, 10);
-- write PHY register data
- proc_mem_mm_bus_wr(c_ofs_tx_dat, c_phy_data, clk, mdio_mosi); -- Write data (PHY data)
+ -- Write data (PHY data)
+ proc_mem_mm_bus_wr(c_ofs_tx_dat, c_phy_data, clk, mdio_mosi);
proc_common_wait_some_cycles(clk, 10);
- proc_mem_mm_bus_wr(c_ofs_hdr, c_hdr_wr, clk, mdio_mosi); -- then write header (op=wr), enables the MDIO access
+ -- then write header (op=wr), enables the MDIO access
+ proc_mem_mm_bus_wr(c_ofs_hdr, c_hdr_wr, clk, mdio_mosi);
proc_common_wait_some_cycles(clk, 10);
while done = '0' loop wait until rising_edge(clk); end loop;
- proc_mem_mm_bus_wr(c_ofs_done_ack_evt, 1, clk, mdio_mosi); -- Acknowledge done
+ -- Acknowledge done
+ proc_mem_mm_bus_wr(c_ofs_done_ack_evt, 1, clk, mdio_mosi);
proc_common_wait_some_cycles(clk, 10);
----------------------------------------------------------------------------
-- read_MMD
----------------------------------------------------------------------------
-- write PHY register address
- proc_mem_mm_bus_wr(c_ofs_tx_dat, c_phy_addr, clk, mdio_mosi); -- Write data (PHY address)
+ -- Write data (PHY address)
+ proc_mem_mm_bus_wr(c_ofs_tx_dat, c_phy_addr, clk, mdio_mosi);
proc_common_wait_some_cycles(clk, 10);
- proc_mem_mm_bus_wr(c_ofs_hdr, c_hdr_addr, clk, mdio_mosi); -- then write header (op=addr), enables the MDIO access
+ -- then write header (op=addr), enables the MDIO access
+ proc_mem_mm_bus_wr(c_ofs_hdr, c_hdr_addr, clk, mdio_mosi);
proc_common_wait_some_cycles(clk, 10);
while done = '0' loop wait until rising_edge(clk); end loop;
- proc_mem_mm_bus_wr(c_ofs_done_ack_evt, 1, clk, mdio_mosi); -- Acknowledge done
+ -- Acknowledge done
+ proc_mem_mm_bus_wr(c_ofs_done_ack_evt, 1, clk, mdio_mosi);
proc_common_wait_some_cycles(clk, 10);
-- read PHY register data
- proc_mem_mm_bus_wr(c_ofs_tx_dat, c_phy_data, clk, mdio_mosi); -- Write data (PHY data)
+ -- Write data (PHY data)
+ proc_mem_mm_bus_wr(c_ofs_tx_dat, c_phy_data, clk, mdio_mosi);
proc_common_wait_some_cycles(clk, 10);
- proc_mem_mm_bus_wr(c_ofs_hdr, c_hdr_rd, clk, mdio_mosi); -- then write header (op=rd), enables the MDIO access
+ -- then write header (op=rd), enables the MDIO access
+ proc_mem_mm_bus_wr(c_ofs_hdr, c_hdr_rd, clk, mdio_mosi);
proc_common_wait_some_cycles(clk, 10);
while done = '0' loop wait until rising_edge(clk); end loop;
- proc_mem_mm_bus_wr(c_ofs_done_ack_evt, 1, clk, mdio_mosi); -- Acknowledge done
+ -- Acknowledge done
+ proc_mem_mm_bus_wr(c_ofs_done_ack_evt, 1, clk, mdio_mosi);
proc_common_wait_some_cycles(clk, 10);
proc_common_wait_some_cycles(clk, c_delay);
@@ -222,8 +240,10 @@ begin
port map (
dat_inout => mdio,
dat_in_from_line => mdat_in,
- dat_out_to_line => '0', -- for output '1' rely on external pull up, only
- dat_out_en => mdat_oen -- pull low when mdat_oen (so implicitely mdat_out='0')
+ -- for output '1' rely on external pull up, only
+ dat_out_to_line => '0',
+ -- pull low when mdat_oen (so implicitely mdat_out='0')
+ dat_out_en => mdat_oen
);
-- MDIO slave
diff --git a/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd b/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd
index 0eabcfe6ead66301f0a9e626b85ca3ab4fcebf96..cb4480e09aacce9e55611747b54911841dbfde22 100644
--- a/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd
+++ b/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd
@@ -43,14 +43,20 @@ entity nw_10GbE is
generic (
g_technology : natural := c_tech_select_default;
g_sim : boolean;
- g_sim_level : natural := 1; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 1;
g_nof_macs : natural;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_use_mdio : boolean := false;
- g_mdio_epcs_dis : boolean := false; -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
- g_tx_fifo_fill : natural := 10; -- Release tx packet only when sufficiently data is available such that no data gaps are introduced.
- g_tx_fifo_size : natural := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
- g_rx_fifo_size : natural := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
+ g_mdio_epcs_dis : boolean := false;
+ -- Release tx packet only when sufficiently data is available such that no data gaps are introduced.
+ g_tx_fifo_fill : natural := 10;
+ -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ g_tx_fifo_size : natural := 256;
+ -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ g_rx_fifo_size : natural := 256;
g_word_alignment_padding : boolean := false;
g_xon_backpressure : boolean := false;
g_arp_period_s : natural := 30;
@@ -58,13 +64,18 @@ entity nw_10GbE is
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_644 : in std_logic := '0'; -- 644.531250 MHz for 10GBASE-R
- tr_ref_clk_312 : in std_logic := '0'; -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 : in std_logic := '0'; -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 : in std_logic := '0'; -- for 10GBASE-R or for XAUI
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 : in std_logic := '0';
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 : in std_logic := '0';
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 : in std_logic := '0';
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 : in std_logic := '0';
-- Calibration & reconfig clock
- cal_rec_clk : in std_logic := '0'; -- for XAUI;
+ -- for XAUI;
+ cal_rec_clk : in std_logic := '0';
-- MM interface
mm_rst : in std_logic;
@@ -76,7 +87,8 @@ entity nw_10GbE is
xaui_mosi : in t_mem_mosi := c_mem_mosi_rst;
xaui_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi := c_mem_mosi_rst; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_eth10g_miso : out t_mem_miso;
mdio_mosi_arr : in t_mem_mosi_arr(g_nof_macs - 1 downto 0) := (others => c_mem_mosi_rst);
@@ -198,8 +210,10 @@ begin
generic map (
g_nof_input => c_nof_mux_streams,
g_sel_ctrl_invert => true,
- g_fifo_size => array_init(0,c_nof_mux_streams), -- no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_nof_mux_streams) -- no FIFO used but must match g_nof_input
+ -- no FIFO used but must match g_nof_input
+ g_fifo_size => array_init(0,c_nof_mux_streams),
+ -- no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0,c_nof_mux_streams)
)
port map (
clk => dp_clk,
@@ -234,12 +248,16 @@ begin
port map (
-- Transceiver PLL reference clock
tr_ref_clk_644 => tr_ref_clk_644,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => tr_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => tr_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156,
-- Calibration & reconfig clock
- cal_rec_clk => cal_rec_clk, -- for XAUI;
+ -- for XAUI;
+ cal_rec_clk => cal_rec_clk,
-- MM interface
mm_rst => mm_rst,
diff --git a/libraries/io/nw_10GbE/src/vhdl/nw_arp_request.vhd b/libraries/io/nw_10GbE/src/vhdl/nw_arp_request.vhd
index b1bad94e019bbed9e4d77718826f53d766893275..903ebd760bf3ad93c5469f75637097b87ceb8171 100644
--- a/libraries/io/nw_10GbE/src/vhdl/nw_arp_request.vhd
+++ b/libraries/io/nw_10GbE/src/vhdl/nw_arp_request.vhd
@@ -58,18 +58,30 @@ architecture rtl of nw_arp_request is
constant c_data_w : natural := c_xgmii_data_w;
constant c_nof_hdr_fields : natural := 12;
constant c_hdr_field_sel : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := (others => '0');
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(c_network_eth_bc_mac) ), -- broadcast address
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ), -- same as arp_sha
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0806") ), -- ARP type
- ( field_name_pad("arp_htype" ), "RW", 16, field_default(1) ), -- eth type
- ( field_name_pad("arp_ptype" ), "RW", 16, field_default(x"0800") ), -- IP type
- ( field_name_pad("arp_hlen" ), "RW", 8, field_default(6) ), -- Mac length is 6 bytes
- ( field_name_pad("arp_plen" ), "RW", 8, field_default(4) ), -- IP length is 4 bytes
- ( field_name_pad("arp_operation" ), "RW", 16, field_default(1) ), -- operation is request
- ( field_name_pad("arp_sha" ), "RW", 48, field_default(0) ), -- set later
- ( field_name_pad("arp_spa" ), "RW", 32, field_default(0) ), -- set later
- ( field_name_pad("arp_tha" ), "RW", 48, field_default(0) ), -- set to 0
- ( field_name_pad("arp_tpa" ), "RW", 32, field_default(0) )); -- set later
+ -- broadcast address
+ constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(c_network_eth_bc_mac) ),
+ -- same as arp_sha
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ -- ARP type
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0806") ),
+ -- eth type
+ ( field_name_pad("arp_htype" ), "RW", 16, field_default(1) ),
+ -- IP type
+ ( field_name_pad("arp_ptype" ), "RW", 16, field_default(x"0800") ),
+ -- Mac length is 6 bytes
+ ( field_name_pad("arp_hlen" ), "RW", 8, field_default(6) ),
+ -- IP length is 4 bytes
+ ( field_name_pad("arp_plen" ), "RW", 8, field_default(4) ),
+ -- operation is request
+ ( field_name_pad("arp_operation" ), "RW", 16, field_default(1) ),
+ -- set later
+ ( field_name_pad("arp_sha" ), "RW", 48, field_default(0) ),
+ -- set later
+ ( field_name_pad("arp_spa" ), "RW", 32, field_default(0) ),
+ -- set to 0
+ ( field_name_pad("arp_tha" ), "RW", 48, field_default(0) ),
+ -- set later
+ ( field_name_pad("arp_tpa" ), "RW", 32, field_default(0) ));
constant c_dp_field_blk_snk_data_w : natural := field_slv_len(c_hdr_field_arr);
constant c_dp_field_blk_src_data_w : natural := c_data_w;
diff --git a/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd b/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd
index 8ac3fed9ca7866758fa272180339a59b80b0e779..ff44358ab3256104c8c10be8e15b43e4c7549f8a 100644
--- a/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd
+++ b/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd
@@ -60,7 +60,8 @@ architecture rtl of nw_ping_response is
constant c_dp_fifo_size : natural := 16;
constant c_cin_w : natural := 4;
- constant c_pipeline : natural := c_network_total_header_64b_nof_words + 5; -- Header length and 5 more pipeline cycles to allow for the other states
+ -- Header length and 5 more pipeline cycles to allow for the other states
+ constant c_pipeline : natural := c_network_total_header_64b_nof_words + 5;
type t_state is (s_idle, s_capture, s_check, s_sum, s_output, s_wait);
@@ -100,14 +101,16 @@ begin
case r.state is
- when s_idle => -- Wait for valid SOP
+ -- Wait for valid SOP
+ when s_idle =>
if snk_in.sop = '1' and snk_in.valid = '1' then
v.state := s_capture;
v.hdr_words_arr(r.word_cnt) := snk_in.data(c_data_w - 1 downto 0);
v.word_cnt := r.word_cnt + 1;
end if;
- when s_capture => -- Capture header
+ -- Capture header
+ when s_capture =>
if snk_in.valid = '1' and r.word_cnt < c_network_total_header_64b_nof_words then
v.word_cnt := r.word_cnt + 1;
v.hdr_words_arr(r.word_cnt) := snk_in.data(c_data_w - 1 downto 0);
@@ -121,7 +124,8 @@ begin
v.hdr_fields.icmp := func_network_total_header_no_align_extract_icmp( r.hdr_words_arr);
end if;
- when s_check => -- Check if packet is ICMP echo request, create response header if it is the case.
+ -- Check if packet is ICMP echo request, create response header if it is the case.
+ when s_check =>
if TO_UINT(r.hdr_fields.eth.eth_type) = c_network_eth_type_ip and
TO_UINT(r.hdr_fields.ip.protocol) = c_network_ip_protocol_icmp and
TO_UINT(r.hdr_fields.icmp.msg_type) = c_network_icmp_msg_type_request then
@@ -131,29 +135,43 @@ begin
v := c_r_rst;
end if;
- when s_sum => -- Sum halfwords of headers for checksum
+ -- Sum halfwords of headers for checksum
+ when s_sum =>
v.state := s_output;
v.ip_sum := r.ip_sum
- + unsigned(r.hdr_response(1)(c_halfword_w - 1 downto 0)) -- ip_version, ip_header_length, ip_services
- + unsigned(r.hdr_response(2)(c_halfword_w * 4 - 1 downto c_halfword_w * 3)) -- ip_total_length
- + unsigned(r.hdr_response(2)(c_halfword_w * 3 - 1 downto c_halfword_w * 2)) -- ip_identification
- + unsigned(r.hdr_response(2)(c_halfword_w * 2 - 1 downto c_halfword_w)) -- ip_flags, ip_fragment_offset
- + unsigned(r.hdr_response(2)(c_halfword_w - 1 downto 0)) -- ip_time_to_live, ip_protocol
- + unsigned(r.hdr_response(3)(c_halfword_w * 3 - 1 downto c_halfword_w * 2)) -- ip_src_addr(1/2)
- + unsigned(r.hdr_response(3)(c_halfword_w * 2 - 1 downto c_halfword_w)) -- ip_src_addr(2/2)
- + unsigned(r.hdr_response(3)(c_halfword_w - 1 downto 0)) -- ip_dst_addr(1/2)
- + unsigned(r.hdr_response(4)(c_halfword_w * 4 - 1 downto c_halfword_w * 3)); -- ip_dst_addr(2/2)
-
- when s_output => -- Send out ICMP response
+ -- ip_version, ip_header_length, ip_services
+ + unsigned(r.hdr_response(1)(c_halfword_w - 1 downto 0))
+ -- ip_total_length
+ + unsigned(r.hdr_response(2)(c_halfword_w * 4 - 1 downto c_halfword_w * 3))
+ -- ip_identification
+ + unsigned(r.hdr_response(2)(c_halfword_w * 3 - 1 downto c_halfword_w * 2))
+ -- ip_flags, ip_fragment_offset
+ + unsigned(r.hdr_response(2)(c_halfword_w * 2 - 1 downto c_halfword_w))
+ -- ip_time_to_live, ip_protocol
+ + unsigned(r.hdr_response(2)(c_halfword_w - 1 downto 0))
+ -- ip_src_addr(1/2)
+ + unsigned(r.hdr_response(3)(c_halfword_w * 3 - 1 downto c_halfword_w * 2))
+ -- ip_src_addr(2/2)
+ + unsigned(r.hdr_response(3)(c_halfword_w * 2 - 1 downto c_halfword_w))
+ -- ip_dst_addr(1/2)
+ + unsigned(r.hdr_response(3)(c_halfword_w - 1 downto 0))
+ -- ip_dst_addr(2/2)
+ + unsigned(r.hdr_response(4)(c_halfword_w * 4 - 1 downto c_halfword_w * 3));
+
+ -- Send out ICMP response
+ when s_output =>
v.src_out := dp_pipeline_src_out;
if dp_pipeline_src_out.valid = '1' then
case r.word_cnt is
when 0 =>
-- Also perform final checksum calculation
- if dp_pipeline_src_out.sop = '1' then -- Wait for SOP
+ -- Wait for SOP
+ if dp_pipeline_src_out.sop = '1' then
v.src_out.data(c_data_w - 1 downto 0) := r.hdr_response(r.word_cnt);
- v.ip_checksum := not(std_logic_vector(r.ip_sum(c_halfword_w - 1 downto 0) + r.ip_sum(r.ip_sum'high downto c_halfword_w))); -- checksum = inverted (sum + carry)
- v.icmp_checksum := TO_UVEC((2048 + TO_UINT(r.hdr_fields.icmp.checksum)), c_halfword_w); -- checksum = original checksum + 0x0800 (incremental update)
+ -- checksum = inverted (sum + carry)
+ v.ip_checksum := not(std_logic_vector(r.ip_sum(c_halfword_w - 1 downto 0) + r.ip_sum(r.ip_sum'high downto c_halfword_w)));
+ -- checksum = original checksum + 0x0800 (incremental update)
+ v.icmp_checksum := TO_UVEC((2048 + TO_UINT(r.hdr_fields.icmp.checksum)), c_halfword_w);
v.word_cnt := r.word_cnt + 1;
else
v.src_out := c_dp_sosi_rst;
@@ -178,7 +196,8 @@ begin
when s_wait =>
v.src_out := c_dp_sosi_rst;
- if dp_fifo_sc_rd_emp = '1' then -- Wait until ping response has left the fifo
+ -- Wait until ping response has left the fifo
+ if dp_fifo_sc_rd_emp = '1' then
v := c_r_rst;
end if;
end case;
diff --git a/libraries/io/nw_10GbE/tb/vhdl/tb_nw_10GbE.vhd b/libraries/io/nw_10GbE/tb/vhdl/tb_nw_10GbE.vhd
index 544e1970373f10f97e8f45b3cd56b52a8b5e2a2b..bbcb208204176d6ba56ecf86bec3f901f7f9b78a 100644
--- a/libraries/io/nw_10GbE/tb/vhdl/tb_nw_10GbE.vhd
+++ b/libraries/io/nw_10GbE/tb/vhdl/tb_nw_10GbE.vhd
@@ -63,14 +63,21 @@ entity tb_nw_10GbE is
-- Test bench control parameters
generic (
g_technology : natural := c_tech_select_default;
- g_tb_end : boolean := true; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
- g_no_dut : boolean := false; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
- g_dp_clk_period : time := 5 ns; -- must be ~< 9000/(9000-c_tx_fifo_fill) * g_ref_clk_156_period
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
+ -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ g_tb_end : boolean := true;
+ -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
+ g_no_dut : boolean := false;
+ -- must be ~< 9000/(9000-c_tx_fifo_fill) * g_ref_clk_156_period
+ g_dp_clk_period : time := 5 ns;
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
- g_ref_clk_644_period : time := tech_pll_clk_644_period; -- for 10GBASE-R
- g_ref_clk_156_period : time := 6.4 ns; -- for XAUI
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
+ -- for 10GBASE-R
+ g_ref_clk_644_period : time := tech_pll_clk_644_period;
+ -- for XAUI
+ g_ref_clk_156_period : time := 6.4 ns;
g_data_type : natural := c_tb_tech_mac_10g_data_type_symbols;
g_verify_link_recovery : boolean := true
);
@@ -80,16 +87,19 @@ entity tb_nw_10GbE is
end tb_nw_10GbE;
architecture tb of tb_nw_10GbE is
- constant c_sim : boolean := true; -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation
+ -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation
+ constant c_sim : boolean := true;
- constant cal_clk_period : time := 25 ns; -- 40 MHz
+ -- 40 MHz
+ constant cal_clk_period : time := 25 ns;
constant phy_delay : time := sel_a_b(g_sim_level = 0, 0 ns, 0 ns);
constant c_tx_rx_loopback : boolean := g_direction /= "TX_ONLY";
constant c_tx_fifo_fill : natural := 100;
- constant c_pkt_length_arr1 : t_nat_natural_arr := array_init(0, 50, 1) & (1472, 1473) & 9000; -- frame longer than 1518-46 = 1472 is received with rx_sosi.err = 8
+ -- frame longer than 1518-46 = 1472 is received with rx_sosi.err = 8
+ constant c_pkt_length_arr1 : t_nat_natural_arr := array_init(0, 50, 1) & (1472, 1473) & 9000;
-- jumbo frame is 9018-46 = 8972
constant c_pkt_length_arr2 : t_nat_natural_arr := array_init(46, 10, 139) & 1472;
constant c_pkt_length_arr : t_nat_natural_arr := c_pkt_length_arr1 & c_pkt_length_arr2;
@@ -98,7 +108,8 @@ architecture tb of tb_nw_10GbE is
constant c_nof_pkt : natural := sel_a_b(g_verify_link_recovery, c_nof_pkt1 + c_nof_pkt2, c_nof_pkt1);
constant c_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"10FA01020300";
- constant c_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ -- = 12-34-56-78-9A-BC
+ constant c_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"123456789ABC";
constant c_src_mac_tx : std_logic_vector(c_network_eth_mac_slv'range) := c_src_mac;
--CONSTANT c_src_mac_tx : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"100056789ABC"; -- = 10-00-56-78-9A-BC
constant c_ethertype : std_logic_vector(c_network_eth_type_slv'range) := X"10FA";
@@ -108,7 +119,8 @@ architecture tb of tb_nw_10GbE is
constant c_eth_header_ethertype : t_network_eth_header := (c_dst_mac, c_src_mac_tx, c_ethertype);
constant c_eth_header_etherlen : t_network_eth_header := (c_dst_mac, c_src_mac_tx, c_etherlen);
- signal total_header : t_network_total_header := c_network_total_header_ones; -- default fill all fields with value 1
+ -- default fill all fields with value 1
+ signal total_header : t_network_total_header := c_network_total_header_ones;
constant c_ip_hdr_field_arr : t_common_field_arr(3 + 12 - 1 downto 0) := ( ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"ffffffffffff") ),
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(x"e840f2acff78") ),
@@ -129,37 +141,52 @@ architecture tb of tb_nw_10GbE is
signal tx_end_arr : std_logic_vector(g_nof_channels - 1 downto 0);
signal tx_end : std_logic;
signal rx_end : std_logic;
- signal cal_clk : std_logic := '1'; -- calibration clock
- signal mm_clk : std_logic; -- memory-mapped bus clock
- signal mm_rst : std_logic; -- reset synchronous with mm_clk
- signal dp_clk : std_logic := '1'; -- data path clock
- signal dp_pps : std_logic := '0'; -- data path clock
- signal dp_rst : std_logic; -- reset synchronous with dp_clk
+ -- calibration clock
+ signal cal_clk : std_logic := '1';
+ -- memory-mapped bus clock
+ signal mm_clk : std_logic;
+ -- reset synchronous with mm_clk
+ signal mm_rst : std_logic;
+ -- data path clock
+ signal dp_clk : std_logic := '1';
+ -- data path clock
+ signal dp_pps : std_logic := '0';
+ -- reset synchronous with dp_clk
+ signal dp_rst : std_logic;
-- External reference clocks
- signal tr_ref_clk_644 : std_logic := '1'; -- 10GBASE-R
- signal tr_ref_clk_312 : std_logic; -- 10GBASE-R
- signal tr_ref_clk_156 : std_logic := '1'; -- 10GBASE-R or XAUI
- signal tr_ref_rst_156 : std_logic; -- 10GBASE-R or XAUI
+ -- 10GBASE-R
+ signal tr_ref_clk_644 : std_logic := '1';
+ -- 10GBASE-R
+ signal tr_ref_clk_312 : std_logic;
+ -- 10GBASE-R or XAUI
+ signal tr_ref_clk_156 : std_logic := '1';
+ -- 10GBASE-R or XAUI
+ signal tr_ref_rst_156 : std_logic;
-- MAC 10G control interface
signal mm_init : std_logic;
- signal mac_mosi_wrdata : std_logic_vector(c_word_w - 1 downto 0); -- for channel 0, 32 bit
+ -- for channel 0, 32 bit
+ signal mac_mosi_wrdata : std_logic_vector(c_word_w - 1 downto 0);
signal mac_mosi : t_mem_mosi;
signal mac_miso : t_mem_miso;
- signal mac_miso_rdval : std_logic; -- for channel 0
- signal mac_miso_rddata : std_logic_vector(c_word_w - 1 downto 0); -- for channel 0, 32 bit
+ -- for channel 0
+ signal mac_miso_rdval : std_logic;
+ -- for channel 0, 32 bit
+ signal mac_miso_rddata : std_logic_vector(c_word_w - 1 downto 0);
-- MAC 10G transmit interface
signal tx_en : std_logic := '1';
signal tx_siso_arr : t_dp_siso_arr(g_nof_channels - 1 downto 0);
signal tx_sosi_arr : t_dp_sosi_arr(g_nof_channels - 1 downto 0);
- signal tx_sosi_data : std_logic_vector(c_tech_mac_10g_data_w - 1 downto 0); -- for channel 0, 64 bit
+ -- for channel 0, 64 bit
+ signal tx_sosi_data : std_logic_vector(c_tech_mac_10g_data_w - 1 downto 0);
-- MAC 10G receive interface
signal rx_siso_arr : t_dp_siso_arr(g_nof_channels - 1 downto 0);
signal rx_sosi_arr : t_dp_sosi_arr(g_nof_channels - 1 downto 0);
- signal rx_sosi_data : std_logic_vector(c_tech_mac_10g_data_w - 1 downto 0); -- for channel 0, 64 bit
+ -- for channel 0, 64 bit
+ signal rx_sosi_data : std_logic_vector(c_tech_mac_10g_data_w - 1 downto 0);
-- PHY XAUI serial I/O
signal xaui_tx_arr : t_xaui_arr(g_nof_channels - 1 downto 0);
@@ -175,17 +202,21 @@ architecture tb of tb_nw_10GbE is
-- Verification
signal tx_pkt_cnt_arr : t_natural_arr(g_nof_channels - 1 downto 0) := (others => 0);
signal rx_pkt_cnt_arr : t_natural_arr(g_nof_channels - 1 downto 0) := (others => 0);
- signal rx_toggle_arr : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0'); -- toggle after every received packet
+ -- toggle after every received packet
+ signal rx_toggle_arr : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0');
begin
- cal_clk <= not cal_clk after cal_clk_period / 2; -- Calibration clock
+ -- Calibration clock
+ cal_clk <= not cal_clk after cal_clk_period / 2;
- dp_clk <= not dp_clk after g_dp_clk_period / 2; -- DP clock
+ -- DP clock
+ dp_clk <= not dp_clk after g_dp_clk_period / 2;
dp_rst <= '1', '0' after g_dp_clk_period * 10;
-- debug signals to ease monitoring in wave window
mac_mosi_wrdata <= mac_mosi.wrdata(c_word_w - 1 downto 0);
mac_miso_rddata <= mac_miso.rddata(c_word_w - 1 downto 0);
- mac_miso_rdval <= '1' when mac_mosi.rd = '1' and mac_miso.waitrequest = '0' else '0'; -- c_rd_latency = 1
+ -- c_rd_latency = 1
+ mac_miso_rdval <= '1' when mac_mosi.rd = '1' and mac_miso.waitrequest = '0' else '0';
tx_sosi_data <= tx_sosi_arr(0).data(c_tech_mac_10g_data_w - 1 downto 0);
rx_sosi_data <= rx_sosi_arr(0).data(c_tech_mac_10g_data_w - 1 downto 0);
@@ -264,11 +295,13 @@ begin
generic map (
g_technology => g_technology,
g_sim => c_sim,
- g_sim_level => g_sim_level, -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level => g_sim_level,
g_nof_macs => g_nof_channels,
g_direction => g_direction,
g_use_mdio => true,
- g_mdio_epcs_dis => true, -- TRUE disables Enhanced PCS on init; e.g. to target a 10GbE card in PC that does not support it
+ -- TRUE disables Enhanced PCS on init; e.g. to target a 10GbE card in PC that does not support it
+ g_mdio_epcs_dis => true,
g_tx_fifo_fill => c_tx_fifo_fill,
g_tx_fifo_size => 256,
g_word_alignment_padding => true,
@@ -276,10 +309,14 @@ begin
)
port map (
-- Transceiver PLL reference clock
- tr_ref_clk_644 => tr_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 => tr_ref_clk_644,
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => tr_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => tr_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156,
-- Calibration & reconfig clock
cal_rec_clk => cal_clk,
@@ -333,15 +370,18 @@ begin
g_link_delay => phy_delay
)
port map (
- link_fault => link_fault_arr(I), -- when '1' then forces rx_serial_arr(0)='0'
+ -- when '1' then forces rx_serial_arr(0)='0'
+ link_fault => link_fault_arr(I),
-- 10GBASE-R serial layer connect
serial_tx => serial_tx_arr(I),
- serial_rx => serial_rx_arr(I), -- connects to delayed tx_serial when g_loopback=TRUE
+ -- connects to delayed tx_serial when g_loopback=TRUE
+ serial_rx => serial_rx_arr(I),
-- XAUI serial layer connect
xaui_tx => xaui_tx_arr(I),
- xaui_rx => xaui_rx_arr(I) -- connects to delayed xaui_tx when g_loopback=TRUE
+ -- connects to delayed xaui_tx when g_loopback=TRUE
+ xaui_rx => xaui_rx_arr(I)
);
end generate;
diff --git a/libraries/io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd b/libraries/io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd
index f5af904d95c524dcb02aaea3a81634c9d43fc988..94b36b6c799b4f027a4d1f34a2016b8700683632 100644
--- a/libraries/io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd
+++ b/libraries/io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd
@@ -44,7 +44,8 @@ architecture tb of tb_tb_nw_10GbE is
constant c_data_type : natural := c_tb_tech_mac_10g_data_type_symbols;
constant c_tb_end_vec : std_logic_vector(7 downto 0) := (others => '1');
- signal tb_end_vec : std_logic_vector(7 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ -- sufficiently long to fit all tb instances
+ signal tb_end_vec : std_logic_vector(7 downto 0) := c_tb_end_vec;
signal tb_end : std_logic := '0';
begin
-- g_technology : NATURAL := c_tech_select_default;
diff --git a/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd b/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd
index 4fb564836913db5c44b2b99ff2ab5c8696025b06..40e451b5e719218219b36698cfa1cc1a6ba17585 100644
--- a/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd
@@ -31,20 +31,25 @@ use technology_lib.technology_select_pkg.all;
entity mm_ppsh is
generic (
g_technology : natural := c_tech_select_default;
- g_ext_clk_freq : natural := 200 * 10**6 -- clock frequency of clk in Hz
+ -- clock frequency of clk in Hz
+ g_ext_clk_freq : natural := 200 * 10**6
);
port (
ext_rst : in std_logic;
ext_clk : in std_logic;
ext_pps : in std_logic;
ext_capture_edge : in std_logic := '0';
- pps_pulse : out std_logic; -- pps pulse one clock cycle in ext_clk domain (i.e. 1 Hz pulse)
- pps_toggle : out std_logic; -- pps toggle in ext_clk domain (i.e. 0.5 Hz square wave)
+ -- pps pulse one clock cycle in ext_clk domain (i.e. 1 Hz pulse)
+ pps_pulse : out std_logic;
+ -- pps toggle in ext_clk domain (i.e. 0.5 Hz square wave)
+ pps_toggle : out std_logic;
-- MM control
mm_rst : in std_logic;
mm_clk : in std_logic;
- mm_pps_pulse : out std_logic; -- pps_pulse in mm_clk domain
- mm_pps_toggle : out std_logic; -- pps_toggle in mm_clk domain
+ -- pps_pulse in mm_clk domain
+ mm_pps_pulse : out std_logic;
+ -- pps_toggle in mm_clk domain
+ mm_pps_toggle : out std_logic;
mm_pps_capture_cnt : out std_logic_vector(ceil_log2(g_ext_clk_freq) - 1 downto 0)
);
end mm_ppsh;
diff --git a/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd b/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
index 8844056f9e0fc6cbef3df452e5116b1c39236eef..abfcd29336a535950adab403d70bfde6372958db 100644
--- a/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
@@ -32,26 +32,36 @@ use technology_lib.technology_select_pkg.all;
entity mms_ppsh is
generic (
g_technology : natural := c_tech_select_default;
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_st_clk_freq : natural := 200 * 10**6 -- clk frequency in Hz
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
+ -- clk frequency in Hz
+ g_st_clk_freq : natural := 200 * 10**6
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- streaming clock domain clock
- pps_ext : in std_logic; -- with unknown but constant phase to st_clk
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- streaming clock domain clock
+ st_clk : in std_logic;
+ -- with unknown but constant phase to st_clk
+ pps_ext : in std_logic;
-- Memory-mapped clock domain
- reg_mosi : in t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
- reg_miso : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ reg_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ -- actual ranges defined by c_mm_reg
+ reg_miso : out t_mem_miso;
-- PIO support (for backwards compatibility with pin_pps on ctrl_unb_common)
pin_pps : out std_logic_vector(c_word_w - 1 downto 0);
-- Streaming clock domain
- pps_sys : out std_logic -- pps pulse in st_clk domain (i.e. 1 clk cycle pulse per second)
+ -- pps pulse in st_clk domain (i.e. 1 clk cycle pulse per second)
+ pps_sys : out std_logic
);
end mms_ppsh;
@@ -62,13 +72,16 @@ architecture str of mms_ppsh is
-- MM registers in st_clk domain
signal st_pps_toggle : std_logic;
signal st_pps_stable : std_logic;
- signal st_capture_cnt : std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0); -- counts the number of clk clock cycles between subsequent pps_ext pulses
- signal st_offset_cnt : std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0); -- counts the number of clk clock cycles between now and last pps_ext pulse
+ -- counts the number of clk clock cycles between subsequent pps_ext pulses
+ signal st_capture_cnt : std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0);
+ -- counts the number of clk clock cycles between now and last pps_ext pulse
+ signal st_offset_cnt : std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0);
signal st_pps_stable_ack : std_logic;
signal st_capture_edge : std_logic;
- signal st_expected_cnt : std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0); -- expected number of clk clock cycles between subsequent pps_ext pulses
+ -- expected number of clk clock cycles between subsequent pps_ext pulses
+ signal st_expected_cnt : std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0);
-- MM registers in mm_clk domaim for pin_pps support
signal mm_pps_toggle : std_logic;
@@ -159,5 +172,6 @@ begin
nxt_mm_pps_toggle <= st_pps_toggle when mm_pps_sys = '1' else mm_pps_toggle;
nxt_mm_capture_cnt <= st_capture_cnt when mm_pps_sys = '1' else mm_capture_cnt;
- pin_pps <= mm_pps_toggle & '0' & RESIZE_UVEC(mm_capture_cnt, 30); -- pin_pps did not support pps_stable yet
+ -- pin_pps did not support pps_stable yet
+ pin_pps <= mm_pps_toggle & '0' & RESIZE_UVEC(mm_capture_cnt, 30);
end str;
diff --git a/libraries/io/ppsh/src/vhdl/ppsh.vhd b/libraries/io/ppsh/src/vhdl/ppsh.vhd
index ce1c41eb55f0b5b36d91965001012d1a26ea35c1..3952c42a5b37b350c2582435ee64031754f9ea94 100644
--- a/libraries/io/ppsh/src/vhdl/ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/ppsh.vhd
@@ -56,22 +56,32 @@ use technology_lib.technology_select_pkg.all;
entity ppsh is
generic (
g_technology : natural := c_tech_select_default;
- g_clk_freq : natural := 200 * 10**6 -- clock frequency of clk in Hz
+ -- clock frequency of clk in Hz
+ g_clk_freq : natural := 200 * 10**6
);
port (
rst : in std_logic;
clk : in std_logic;
-- PPS
- pps_ext : in std_logic; -- with unknown but constant phase to clk
- pps_sys : out std_logic; -- pps pulse in clk domain (i.e. 1 clk cycle pulse per second)
+ -- with unknown but constant phase to clk
+ pps_ext : in std_logic;
+ -- pps pulse in clk domain (i.e. 1 clk cycle pulse per second)
+ pps_sys : out std_logic;
-- MM control
- pps_toggle : out std_logic; -- pps toggle level signal in clk domain (i.e. 0.5 Hz square wave)
- pps_stable : out std_logic; -- pps stable signal in clk domain
- capture_cnt : out std_logic_vector(ceil_log2(g_clk_freq) - 1 downto 0); -- counts the number of clk clock cycles between subsequent pps_ext pulses
- offset_cnt : out std_logic_vector(ceil_log2(g_clk_freq) - 1 downto 0); -- counts the number of clk clock cycles between now and last pps_ext pulse
- pps_stable_ack : in std_logic := '0'; -- pps stable acknowledge in clk domain
- capture_edge : in std_logic := '0'; -- when '0' then clock pps_ext on rising edge of clk, else use falling edge of clk
- expected_cnt : in std_logic_vector(ceil_log2(g_clk_freq) - 1 downto 0) := (others => '1') -- expected number of clk clock cycles between subsequent pps_ext pulses
+ -- pps toggle level signal in clk domain (i.e. 0.5 Hz square wave)
+ pps_toggle : out std_logic;
+ -- pps stable signal in clk domain
+ pps_stable : out std_logic;
+ -- counts the number of clk clock cycles between subsequent pps_ext pulses
+ capture_cnt : out std_logic_vector(ceil_log2(g_clk_freq) - 1 downto 0);
+ -- counts the number of clk clock cycles between now and last pps_ext pulse
+ offset_cnt : out std_logic_vector(ceil_log2(g_clk_freq) - 1 downto 0);
+ -- pps stable acknowledge in clk domain
+ pps_stable_ack : in std_logic := '0';
+ -- when '0' then clock pps_ext on rising edge of clk, else use falling edge of clk
+ capture_edge : in std_logic := '0';
+ -- expected number of clk clock cycles between subsequent pps_ext pulses
+ expected_cnt : in std_logic_vector(ceil_log2(g_clk_freq) - 1 downto 0) := (others => '1')
);
end ppsh;
@@ -101,7 +111,8 @@ begin
capture_cnt <= i_capture_cnt;
pps_toggle <= i_pps_toggle;
- pps_ext_delayed(0) <= pps_ext; -- no input delay support
+ -- no input delay support
+ pps_ext_delayed(0) <= pps_ext;
u_in : entity common_lib.common_ddio_in
generic map(
@@ -111,12 +122,14 @@ begin
port map(
in_dat => pps_ext_delayed,
in_clk => clk,
- rst => '0', -- no need to use rst, this eases timing closure
+ -- no need to use rst, this eases timing closure
+ rst => '0',
out_dat_hi => pps_ext_rising,
out_dat_lo => pps_ext_falling
);
- nxt_pps_ext_cap <= pps_ext_rising(0) when capture_edge = '0' else pps_ext_falling(0); -- captured ext_sync
+ -- captured ext_sync
+ nxt_pps_ext_cap <= pps_ext_rising(0) when capture_edge = '0' else pps_ext_falling(0);
p_clk : process (clk, rst)
begin
diff --git a/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd b/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
index b7d28c187909e180a4cd529b2ad5486d3d16389d..f2a40b7d1d3cadaf7351c6d1c9db8273271a0030 100644
--- a/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
+++ b/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
@@ -54,30 +54,41 @@ use common_lib.common_mem_pkg.all;
entity ppsh_reg is
generic (
- g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_st_clk_freq : natural := 200 * 10**6 -- clock frequency of st_clk in Hz
+ -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_cross_clock_domain : boolean := true;
+ -- clock frequency of st_clk in Hz
+ g_st_clk_freq : natural := 200 * 10**6
);
port (
-- Clocks and reset
- mm_rst : in std_logic; -- reset synchronous with mm_clk
- mm_clk : in std_logic; -- memory-mapped bus clock
- st_rst : in std_logic; -- reset synchronous with st_clk
- st_clk : in std_logic; -- other clock domain clock
+ -- reset synchronous with mm_clk
+ mm_rst : in std_logic;
+ -- memory-mapped bus clock
+ mm_clk : in std_logic;
+ -- reset synchronous with st_clk
+ st_rst : in std_logic;
+ -- other clock domain clock
+ st_clk : in std_logic;
-- Memory Mapped Slave in mm_clk domain
- sla_in : in t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
+ -- actual ranges defined by c_mm_reg
+ sla_in : in t_mem_mosi;
+ -- actual ranges defined by c_mm_reg
+ sla_out : out t_mem_miso;
-- MM registers in st_clk domain
st_pps_toggle : in std_logic;
st_pps_stable : in std_logic;
- st_capture_cnt : in std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0); -- counts the number of clk clock cycles between subsequent pps_ext pulses
- st_offset_cnt : in std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0); -- counts the number of clk clock cycles between now and last pps_ext pulse
+ -- counts the number of clk clock cycles between subsequent pps_ext pulses
+ st_capture_cnt : in std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0);
+ -- counts the number of clk clock cycles between now and last pps_ext pulse
+ st_offset_cnt : in std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0);
st_pps_stable_ack : out std_logic;
st_capture_edge : out std_logic;
- st_expected_cnt : out std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0) -- expected number of clk clock cycles between subsequent pps_ext pulses
+ -- expected number of clk clock cycles between subsequent pps_ext pulses
+ st_expected_cnt : out std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0)
);
end ppsh_reg;
@@ -85,7 +96,8 @@ architecture rtl of ppsh_reg is
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(4),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 4,
init_sl => '0');
@@ -117,7 +129,8 @@ begin
-- Access event, register values
mm_pps_stable_ack <= '0';
- mm_capture_edge <= '0'; -- default rising edge
+ -- default rising edge
+ mm_capture_edge <= '0';
mm_expected_cnt <= TO_UVEC(g_st_clk_freq, mm_expected_cnt'length);
elsif rising_edge(mm_clk) then
@@ -134,13 +147,16 @@ begin
-- Write PPSH control
mm_capture_edge <= sla_in.wrdata(31);
mm_expected_cnt <= sla_in.wrdata(mm_expected_cnt'range);
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
when 0 =>
-- Read PPSH status
@@ -155,7 +171,8 @@ begin
when 2 =>
-- Read PPSH offset count
sla_out.rddata(29 downto 0) <= RESIZE_UVEC(mm_offset_cnt, 30);
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
end if;
end if;
@@ -178,7 +195,8 @@ begin
-- signals if it is necessary (to avoid using more logic than necessary).
------------------------------------------------------------------------------
- no_cross : if g_cross_clock_domain = false generate -- so mm_clk = st_clk
+ -- so mm_clk = st_clk
+ no_cross : if g_cross_clock_domain = false generate
mm_pps_toggle <= st_pps_toggle;
mm_pps_stable <= st_pps_stable;
mm_capture_cnt <= st_capture_cnt;
@@ -188,7 +206,8 @@ begin
st_capture_edge <= mm_capture_edge;
st_expected_cnt <= mm_expected_cnt;
- end generate; -- no_cross
+ -- no_cross
+ end generate;
gen_cross : if g_cross_clock_domain = true generate
-- ST --> MM
@@ -272,6 +291,7 @@ begin
out_dat => st_expected_cnt,
out_new => open
);
- end generate; -- gen_cross
+ -- gen_cross
+ end generate;
end rtl;
diff --git a/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd b/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
index 65be3c0f2ff972aef51dbcd77cd42b9984e8a098..b98742fd12452c0fe0f920c8c3b2eb72c47a0046 100644
--- a/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
+++ b/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
@@ -31,10 +31,13 @@ entity tb_mms_ppsh is
end tb_mms_ppsh;
architecture tb of tb_mms_ppsh is
- constant c_st_clk_freq : natural := 1000; -- clock frequency in Hz
+ -- clock frequency in Hz
+ constant c_st_clk_freq : natural := 1000;
constant c_st_clk_period : time := 1000000 us / c_st_clk_freq;
- constant c_mm_clk_period : time := c_st_clk_period * 3; -- somewhat slower mm_clk
- constant c_pps_period : natural := c_st_clk_freq; -- 1 s takes c_clk_freq clk cycles
+ -- somewhat slower mm_clk
+ constant c_mm_clk_period : time := c_st_clk_period * 3;
+ -- 1 s takes c_clk_freq clk cycles
+ constant c_pps_period : natural := c_st_clk_freq;
constant c_cnt_w : natural := ceil_log2(c_st_clk_freq);
@@ -52,7 +55,8 @@ architecture tb of tb_mms_ppsh is
signal reg_miso : t_mem_miso;
-- Verify
- signal bsn : natural; -- block sequence number counts seconds
+ -- block sequence number counts seconds
+ signal bsn : natural;
signal pps_toggle : std_logic;
signal pps_stable : std_logic;
signal capture_cnt : natural;
@@ -98,11 +102,15 @@ begin
p_mm_stimuli : process
variable v_word : std_logic_vector(c_word_w - 1 downto 0);
begin
- proc_common_wait_until_low(st_clk, st_rst); -- Wait until reset has finished
- proc_common_wait_until_low(mm_clk, mm_rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(mm_clk, 10); -- Wait an additional amount of cycles
-
- v_word := '0' & TO_UVEC(c_pps_period, 31); -- capture_edge = '0' = at rising edge
+ -- Wait until reset has finished
+ proc_common_wait_until_low(st_clk, st_rst);
+ -- Wait until reset has finished
+ proc_common_wait_until_low(mm_clk, mm_rst);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(mm_clk, 10);
+
+ -- capture_edge = '0' = at rising edge
+ v_word := '0' & TO_UVEC(c_pps_period, 31);
-- expected_cnt = c_pps_period = 1000
proc_mem_mm_bus_wr(1, v_word, mm_clk, reg_mosi);
@@ -135,10 +143,13 @@ begin
p_verify : process
begin
- proc_common_wait_until_low(st_clk, st_rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(st_clk, 10); -- Wait an additional amount of cycles
+ -- Wait until reset has finished
+ proc_common_wait_until_low(st_clk, st_rst);
+ -- Wait an additional amount of cycles
+ proc_common_wait_some_cycles(st_clk, 10);
- proc_common_wait_some_cycles(st_clk, c_pps_period / 2); -- Verification offset
+ -- Verification offset
+ proc_common_wait_some_cycles(st_clk, c_pps_period / 2);
-- 1
proc_common_wait_some_cycles(st_clk, c_pps_period * 10);
assert pps_stable = '0' report "1) Wrong pps_stable" severity ERROR;
diff --git a/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd b/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
index e54dd7851d3a0e0063223c87b278837e48f7cfa0..df060fccf31f5509c9ab3141366739945cbc5da4 100644
--- a/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
+++ b/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
@@ -28,9 +28,11 @@ entity tb_ppsh is
end tb_ppsh;
architecture tb of tb_ppsh is
- constant c_clk_freq : natural := 1000; -- clock frequency in Hz
+ -- clock frequency in Hz
+ constant c_clk_freq : natural := 1000;
constant c_clk_period : time := 1000000 us / c_clk_freq;
- constant c_pps_default_period : natural := c_clk_freq; -- 1 s takes c_clk_freq clk cycles
+ -- 1 s takes c_clk_freq clk cycles
+ constant c_pps_default_period : natural := c_clk_freq;
constant c_pps_skew : time := 7 * c_clk_period / 10;
constant c_cnt_w : natural := ceil_log2(c_clk_freq);
@@ -62,7 +64,8 @@ architecture tb of tb_ppsh is
signal expected_cnt : std_logic_vector(c_cnt_w - 1 downto 0);
-- Verify
- signal verify_s : real := 0.0; -- provides time line marker for p_verify in Wave Window
+ -- provides time line marker for p_verify in Wave Window
+ signal verify_s : real := 0.0;
begin
-- Usage: 'run -all', observe unsigned capture_cnt, there should occur no
-- REPORT errors.
@@ -79,7 +82,8 @@ begin
begin
capture_edge <= '0';
wait for 5000 ms;
- capture_edge <= '1'; -- will be verified by p_verify
+ -- will be verified by p_verify
+ capture_edge <= '1';
wait for 2000 ms;
capture_edge <= '0';
wait;
@@ -88,7 +92,8 @@ begin
p_verify_pps_stable : process
begin
pps_stable_ack <= '0';
- wait for 9000 ms; -- wait until p_capture_edge is done
+ -- wait until p_capture_edge is done
+ wait for 9000 ms;
if pps_stable /= '0' then
report "PPSH : Unexpected pps_stable, should be 0." severity ERROR;
end if;
@@ -100,7 +105,8 @@ begin
if pps_stable /= '1' then
report "PPSH : Unexpected pps_stable, should be 1." severity ERROR;
end if;
- wait for 13000 ms; -- wait until first loop in p_pps_default_period is done
+ -- wait until first loop in p_pps_default_period is done
+ wait for 13000 ms;
if pps_stable /= '0' then
report "PPSH : Unexpected pps_stable, should have become 0." severity ERROR;
end if;
@@ -115,40 +121,46 @@ begin
expected_cnt <= TO_UVEC(c_pps_default_period, c_cnt_w);
wait until rst = '0';
wait for 10 * c_clk_period;
- wait until rising_edge(clk); -- get synchronous to clk
+ -- get synchronous to clk
+ wait until rising_edge(clk);
-- Correct PPS period
tb_state <= s_default_period;
for I in 1 to 20 loop
pps <= '1';
- wait for I * c_clk_period; -- the PPS pulse width is arbitrary, only the timing of the rising edge is relevant
+ -- the PPS pulse width is arbitrary, only the timing of the rising edge is relevant
+ wait for I * c_clk_period;
pps <= '0';
wait for (c_pps_default_period - I) * c_clk_period;
end loop;
-- One too short PPS period
tb_state <= s_shorter_period;
pps <= '1';
- wait for (c_pps_default_period / 4) * c_clk_period; -- the PPS pulse width is arbitrary, only the timing of the rising edge is relevant
+ -- the PPS pulse width is arbitrary, only the timing of the rising edge is relevant
+ wait for (c_pps_default_period / 4) * c_clk_period;
pps <= '0';
wait for (c_pps_default_period - c_pps_default_period / 4 - 1) * c_clk_period;
-- Some correct PPS periods
tb_state <= s_default_period;
for I in 1 to 5 loop
pps <= '1';
- wait for I * c_clk_period; -- the PPS pulse width is arbitrary, only the timing of the rising edge is relevant
+ -- the PPS pulse width is arbitrary, only the timing of the rising edge is relevant
+ wait for I * c_clk_period;
pps <= '0';
wait for (c_pps_default_period - I) * c_clk_period;
end loop;
-- One too long PPS period
tb_state <= s_longer_period;
pps <= '1';
- wait for (c_pps_default_period / 4) * c_clk_period; -- the PPS pulse width is arbitrary, only the timing of the rising edge is relevant
+ -- the PPS pulse width is arbitrary, only the timing of the rising edge is relevant
+ wait for (c_pps_default_period / 4) * c_clk_period;
pps <= '0';
wait for (c_pps_default_period - c_pps_default_period / 4 + 1) * c_clk_period;
-- Some correct PPS periods
tb_state <= s_default_period;
for I in 1 to 5 loop
pps <= '1';
- wait for I * c_clk_period; -- the PPS pulse width is arbitrary, only the timing of the rising edge is relevant
+ -- the PPS pulse width is arbitrary, only the timing of the rising edge is relevant
+ wait for I * c_clk_period;
pps <= '0';
wait for (c_pps_default_period - I) * c_clk_period;
end loop;
@@ -159,7 +171,8 @@ begin
tb_state <= s_default_period;
for I in 1 to 5 loop
pps <= '1';
- wait for I * c_clk_period; -- the PPS pulse width is arbitrary, only the timing of the rising edge is relevant
+ -- the PPS pulse width is arbitrary, only the timing of the rising edge is relevant
+ wait for I * c_clk_period;
pps <= '0';
wait for (c_pps_default_period - I) * c_clk_period;
end loop;
diff --git a/libraries/io/remu/src/vhdl/remu_reg.vhd b/libraries/io/remu/src/vhdl/remu_reg.vhd
index 6080750d1d68b0b606aa7436aa4a1429d1d9867a..8062019cdb693b907f72c24dc82c232b0b3ac3db 100644
--- a/libraries/io/remu/src/vhdl/remu_reg.vhd
+++ b/libraries/io/remu/src/vhdl/remu_reg.vhd
@@ -73,12 +73,14 @@ end remu_reg;
architecture rtl of remu_reg is
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(7),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ -- Use MM bus data width = c_word_w = 32 for all MM registers
+ dat_w => c_word_w,
nof_dat => 7,
init_sl => '0');
-- For safety, some commands require specific words to be written
- constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
+ -- "Boot factory"
+ constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7";
signal mm_reconfigure : std_logic;
signal mm_read_param : std_logic;
@@ -125,19 +127,23 @@ begin
mm_write_param <= sla_in.wrdata(0);
when 5 =>
mm_data_in <= sla_in.wrdata(g_data_w - 1 downto 0);
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
when 4 =>
sla_out.rddata(g_data_w - 1 downto 0) <= mm_data_out;
when 6 =>
sla_out.rddata(0) <= mm_busy;
- when others => null; -- unused MM addresses
+ -- unused MM addresses
+ when others => null;
end case;
end if;
end if;
diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
index 85c4d7da1208fa90f8b00c5271a66f1b4bd6054a..cc3d2c74f28ae825497c5cc462f18d7f500e40aa 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
@@ -75,27 +75,38 @@ entity tr_10GbE is
generic (
g_technology : natural := c_tech_select_default;
g_sim : boolean;
- g_sim_level : natural := 1; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 1;
g_nof_macs : natural;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_use_loopback : boolean := false;
g_use_mdio : boolean := false;
- g_mdio_epcs_dis : boolean := false; -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
- g_tx_fifo_fill : natural := 10; -- Release tx packet only when sufficiently data is available,
- g_tx_fifo_size : natural := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
- g_rx_fifo_size : natural := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
+ g_mdio_epcs_dis : boolean := false;
+ -- Release tx packet only when sufficiently data is available,
+ g_tx_fifo_fill : natural := 10;
+ -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ g_tx_fifo_size : natural := 256;
+ -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ g_rx_fifo_size : natural := 256;
g_word_alignment_padding : boolean := false;
g_xon_backpressure : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_644 : in std_logic := '0'; -- 644.531250 MHz for 10GBASE-R
- tr_ref_clk_312 : in std_logic := '0'; -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 : in std_logic := '0'; -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 : in std_logic := '0'; -- for 10GBASE-R or for XAUI
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 : in std_logic := '0';
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 : in std_logic := '0';
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 : in std_logic := '0';
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 : in std_logic := '0';
-- Calibration & reconfig clock
- cal_rec_clk : in std_logic := '0'; -- for XAUI;
+ -- for XAUI;
+ cal_rec_clk : in std_logic := '0';
-- MM interface
mm_rst : in std_logic;
@@ -107,7 +118,8 @@ entity tr_10GbE is
xaui_mosi : in t_mem_mosi := c_mem_mosi_rst;
xaui_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi := c_mem_mosi_rst; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_eth10g_miso : out t_mem_miso;
mdio_mosi_arr : in t_mem_mosi_arr(g_nof_macs - 1 downto 0) := (others => c_mem_mosi_rst);
@@ -173,8 +185,10 @@ architecture str of tr_10GbE is
component tr_xaui_mdio is
generic (
g_sim : boolean := false;
- g_nof_xaui : natural := 1; -- Up to 3 (hard XAUI only) supported
- g_mdio_epcs_dis : boolean := false -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
+ -- Up to 3 (hard XAUI only) supported
+ g_nof_xaui : natural := 1;
+ -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
+ g_mdio_epcs_dis : boolean := false
);
port (
-- Transceiver PLL reference clock
@@ -311,7 +325,8 @@ begin
generic map (
g_technology => g_technology,
g_sim => g_sim,
- g_sim_level => g_sim_level, -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level => g_sim_level,
g_nof_channels => g_nof_macs,
g_direction => g_direction,
g_use_loopback => g_use_loopback,
@@ -319,42 +334,54 @@ begin
)
port map (
-- Transceiver PLL reference clock
- tr_ref_clk_644 => eth_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
- tr_ref_clk_312 => eth_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => eth_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => eth_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 => eth_ref_clk_644,
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => eth_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => eth_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => eth_ref_rst_156,
-- Calibration & reconfig clock
- cal_rec_clk => cal_rec_clk, -- for XAUI;
+ -- for XAUI;
+ cal_rec_clk => cal_rec_clk,
-- XAUI clocks
- tx_clk_arr_in => eth_tx_clk_arr, -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
+ -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
+ tx_clk_arr_in => eth_tx_clk_arr,
tx_rst_arr_out => tx_rst_arr_out,
rx_clk_arr_out => rx_clk_arr_out,
- rx_clk_arr_in => eth_rx_clk_arr, -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ rx_clk_arr_in => eth_rx_clk_arr,
rx_rst_arr_out => rx_rst_arr_out,
-- MM
mm_clk => mm_clk,
mm_rst => mm_rst,
- mac_mosi => reg_mac_mosi, -- MAG_10G (CSR), aggregated for all g_nof_channels
+ -- MAG_10G (CSR), aggregated for all g_nof_channels
+ mac_mosi => reg_mac_mosi,
mac_miso => reg_mac_miso,
- xaui_mosi => xaui_mosi, -- XAUI control
+ -- XAUI control
+ xaui_mosi => xaui_mosi,
xaui_miso => xaui_miso,
- reg_eth10g_mosi => reg_eth10g_mosi, -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi => reg_eth10g_mosi,
reg_eth10g_miso => reg_eth10g_miso,
reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
-- ST
- tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr, -- 64 bit data @ 156 MHz
+ -- 64 bit data @ 156 MHz
+ tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr,
tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr ,
- rx_src_out_arr => mac_10g_src_out_arr, -- 64 bit data @ 156 MHz
+ -- 64 bit data @ 156 MHz
+ rx_src_out_arr => mac_10g_src_out_arr,
rx_src_in_arr => mac_10g_src_in_arr,
-- PHY serial IO
@@ -371,7 +398,8 @@ begin
-- MDIO
---------------------------------------------------------------------------
gen_mdio: if g_use_mdio = true generate
- u_tr_xaui_mdio : tr_xaui_mdio -- ENTITY tr_xaui_lib.tr_xaui_mdio
+ -- ENTITY tr_xaui_lib.tr_xaui_mdio
+ u_tr_xaui_mdio : tr_xaui_mdio
generic map (
g_sim => g_sim,
g_nof_xaui => g_nof_macs,
diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd
index b2627f65513f6f29b508d2c955a5481241cb0755..cef325e4cb0dd630e71a256bd11c8aa788c03aed 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd
@@ -49,7 +49,8 @@ entity tr_10GbE_ip_checksum is
end tr_10GbE_ip_checksum;
architecture rtl of tr_10GbE_ip_checksum is
- constant c_cin_w : natural := 4; -- bit width of carry
+ -- bit width of carry
+ constant c_cin_w : natural := 4;
constant c_pipeline_delay : natural := 2;
signal sum : unsigned(c_halfword_w + c_cin_w - 1 downto 0) := (others => '0');
@@ -73,19 +74,30 @@ begin
elsif cnt_en = '1' then
case TO_UINT(count) is
- when 0 => -- 0 is the cycle after the sop due to the common_counter latency
- sum <= sum + unsigned(snk_in.data(c_halfword_w - 1 downto 0)); -- ip_version, ip_header_length, ip_services
+ -- 0 is the cycle after the sop due to the common_counter latency
+ when 0 =>
+ -- ip_version, ip_header_length, ip_services
+ sum <= sum + unsigned(snk_in.data(c_halfword_w - 1 downto 0));
when 1 =>
- sum <= sum + unsigned(snk_in.data(c_halfword_w * 4 - 1 downto c_halfword_w * 3)) -- ip_total_length
- + unsigned(snk_in.data(c_halfword_w * 3 - 1 downto c_halfword_w * 2)) -- ip_identification
- + unsigned(snk_in.data(c_halfword_w * 2 - 1 downto c_halfword_w)) -- ip_flags, ip_fragment_offset
- + unsigned(snk_in.data(c_halfword_w - 1 downto 0)); -- ip_time_to_live, ip_protocol
- when 2 => -- skip ip_header_checksum
- sum <= sum + unsigned(snk_in.data(c_halfword_w * 3 - 1 downto c_halfword_w * 2)) -- ip_src_addr(1/2)
- + unsigned(snk_in.data(c_halfword_w * 2 - 1 downto c_halfword_w)) -- ip_src_addr(2/2)
- + unsigned(snk_in.data(c_halfword_w - 1 downto 0)); -- ip_dst_addr(1/2)
+ -- ip_total_length
+ sum <= sum + unsigned(snk_in.data(c_halfword_w * 4 - 1 downto c_halfword_w * 3))
+ -- ip_identification
+ + unsigned(snk_in.data(c_halfword_w * 3 - 1 downto c_halfword_w * 2))
+ -- ip_flags, ip_fragment_offset
+ + unsigned(snk_in.data(c_halfword_w * 2 - 1 downto c_halfword_w))
+ -- ip_time_to_live, ip_protocol
+ + unsigned(snk_in.data(c_halfword_w - 1 downto 0));
+ -- skip ip_header_checksum
+ when 2 =>
+ -- ip_src_addr(1/2)
+ sum <= sum + unsigned(snk_in.data(c_halfword_w * 3 - 1 downto c_halfword_w * 2))
+ -- ip_src_addr(2/2)
+ + unsigned(snk_in.data(c_halfword_w * 2 - 1 downto c_halfword_w))
+ -- ip_dst_addr(1/2)
+ + unsigned(snk_in.data(c_halfword_w - 1 downto 0));
when 3 =>
- sum <= sum + unsigned(snk_in.data(c_halfword_w * 4 - 1 downto c_halfword_w * 3)); -- ip_dst_addr(2/2)
+ -- ip_dst_addr(2/2)
+ sum <= sum + unsigned(snk_in.data(c_halfword_w * 4 - 1 downto c_halfword_w * 3));
when others =>
end case;
@@ -96,7 +108,8 @@ begin
---------------------------------------------------
-- process to insert checksum in outgoing stream --
---------------------------------------------------
- checksum <= not(std_logic_vector(sum(c_halfword_w - 1 downto 0) + sum(sum'high downto c_halfword_w))); -- checksum = inverted (sum + carry)
+ -- checksum = inverted (sum + carry)
+ checksum <= not(std_logic_vector(sum(c_halfword_w - 1 downto 0) + sum(sum'high downto c_halfword_w)));
p_insert_chksum : process(dp_pipeline_src_out, checksum, count_p)
begin
src_out <= dp_pipeline_src_out;
@@ -108,8 +121,10 @@ begin
------------------------------------------------------------------------------------------
-- using common_counter to keep track of the word alignment during checksum calculation --
------------------------------------------------------------------------------------------
- cnt_en <= snk_in.valid; -- only count when valid
- cnt_clr <= snk_in.sop; -- restart counter on sop
+ -- only count when valid
+ cnt_en <= snk_in.valid;
+ -- restart counter on sop
+ cnt_clr <= snk_in.sop;
u_calc_counter : entity common_lib.common_counter
port map (
@@ -122,8 +137,10 @@ begin
----------------------------------------------------------------------------------------
-- using common_counter to keep track of the word alignment during checksum insertion --
----------------------------------------------------------------------------------------
- cnt_p_en <= dp_pipeline_src_out.valid; -- only count when valid
- cnt_p_clr <= dp_pipeline_src_out.sop; -- restart counter on sop
+ -- only count when valid
+ cnt_p_en <= dp_pipeline_src_out.valid;
+ -- restart counter on sop
+ cnt_p_clr <= dp_pipeline_src_out.sop;
u_pipe_counter : entity common_lib.common_counter
port map (
diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_statistics.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_statistics.vhd
index 3d6158d99a0124a171b73dbd9ca66a2a329a2020..b43527258740132bb1b954002a5ac26824aa851f 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_statistics.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_statistics.vhd
@@ -38,36 +38,47 @@ use tech_pll_lib.tech_pll_component_pkg.all;
entity tr_10GbE_statistics is
generic (
g_technology : natural := c_tech_select_default;
- g_dp_clk_freq_khz : natural := 200000; -- default dp_clk 200 MHz, 5 ns period
- g_runtime_nof_packets : natural; -- Run the test bench for nof_packets before asserting tb_end
- g_runtime_timeout : time; -- Report Failure if g_runtime_nof_packets is not reached before this time
- g_check_nof_valid : boolean := false; -- True enables valid count checking at tb_end. Reports Failure in case of mismatch.
- g_check_nof_valid_ref : natural := 0 -- Reference (= expected) valid count
+ -- default dp_clk 200 MHz, 5 ns period
+ g_dp_clk_freq_khz : natural := 200000;
+ -- Run the test bench for nof_packets before asserting tb_end
+ g_runtime_nof_packets : natural;
+ -- Report Failure if g_runtime_nof_packets is not reached before this time
+ g_runtime_timeout : time;
+ -- True enables valid count checking at tb_end. Reports Failure in case of mismatch.
+ g_check_nof_valid : boolean := false;
+ -- Reference (= expected) valid count
+ g_check_nof_valid_ref : natural := 0
);
port (
xaui_in : in std_logic_vector(3 downto 0) := (others => '0');
serial_in : in std_logic := '0';
- tb_end : out std_logic -- To be used to stop test-bench generated clocks
+ -- To be used to stop test-bench generated clocks
+ tb_end : out std_logic
);
end tr_10GbE_statistics;
architecture str of tr_10GbE_statistics is
- constant c_eth_clk_freq_khz : natural := 156250; -- not used, because dp_statistics operates in dp_clk domain
+ -- not used, because dp_statistics operates in dp_clk domain
+ constant c_eth_clk_freq_khz : natural := 156250;
constant c_eth_word_w : natural := 64;
constant c_dp_word_w : natural := c_eth_word_w;
- constant c_dp_clk_period : time := 10**9 / g_dp_clk_freq_khz * 1 ps; -- 200MHz
+ -- 200MHz
+ constant c_dp_clk_period : time := 10**9 / g_dp_clk_freq_khz * 1 ps;
constant c_eth_clk_period : time := 6.4 ns;
- constant c_cal_rec_clk_period : time := 25 ns; -- 40MHz
+ -- 40MHz
+ constant c_cal_rec_clk_period : time := 25 ns;
- constant c_mm_clk_period : time := 20 ns; -- 50MHz
+ -- 50MHz
+ constant c_mm_clk_period : time := 20 ns;
constant c_sa_clk_period : time := tech_pll_clk_644_period;
signal dp_clk : std_logic := '1';
signal dp_rst : std_logic;
- signal eth_clk : std_logic := '1'; -- Start high to match sim model generated clock
+ -- Start high to match sim model generated clock
+ signal eth_clk : std_logic := '1';
signal eth_rst : std_logic := '0';
signal cal_rec_clk : std_logic := '0';
@@ -161,9 +172,12 @@ begin
port map (
-- Transceiver PLL reference clock
tr_ref_clk_644 => sa_clk,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => tr_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => tr_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156,
-- MM interface
mm_rst => mm_rst,
diff --git a/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd b/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
index a07ba8b66f4684549c70e186a354e8400878bdff..d6bc40d610ceffdf8562e42492f72e4b9ea5ea27 100644
--- a/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
@@ -42,7 +42,8 @@ architecture tb of tb_tb_tr_10GbE is
constant c_data_type : natural := c_tb_tech_mac_10g_data_type_symbols;
constant c_tb_end_vec : std_logic_vector(7 downto 0) := (others => '1');
- signal tb_end_vec : std_logic_vector(7 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ -- sufficiently long to fit all tb instances
+ signal tb_end_vec : std_logic_vector(7 downto 0) := c_tb_end_vec;
signal tb_end : std_logic := '0';
begin
-- g_technology : NATURAL := c_tech_select_default;
diff --git a/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd b/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
index aa75e5580c6018356571b6bff4da345dce33218c..14025b5e2ab16b875a06fea3ad0413ff0f8f6b92 100644
--- a/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
@@ -60,14 +60,21 @@ entity tb_tr_10GbE is
-- Test bench control parameters
generic (
g_technology : natural := c_tech_select_default;
- g_tb_end : boolean := true; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
- g_no_dut : boolean := false; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
- g_dp_clk_period : time := 5 ns; -- must be ~< 9000/(9000-c_tx_fifo_fill) * g_ref_clk_156_period
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
+ -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ g_tb_end : boolean := true;
+ -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
+ g_no_dut : boolean := false;
+ -- must be ~< 9000/(9000-c_tx_fifo_fill) * g_ref_clk_156_period
+ g_dp_clk_period : time := 5 ns;
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
- g_ref_clk_644_period : time := tech_pll_clk_644_period; -- for 10GBASE-R
- g_ref_clk_156_period : time := 6.4 ns; -- for XAUI
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
+ -- for 10GBASE-R
+ g_ref_clk_644_period : time := tech_pll_clk_644_period;
+ -- for XAUI
+ g_ref_clk_156_period : time := 6.4 ns;
g_data_type : natural := c_tb_tech_mac_10g_data_type_symbols;
g_verify_link_recovery : boolean := true
);
@@ -77,16 +84,19 @@ entity tb_tr_10GbE is
end tb_tr_10GbE;
architecture tb of tb_tr_10GbE is
- constant c_sim : boolean := true; -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation
+ -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation
+ constant c_sim : boolean := true;
- constant cal_clk_period : time := 25 ns; -- 40 MHz
+ -- 40 MHz
+ constant cal_clk_period : time := 25 ns;
constant phy_delay : time := sel_a_b(g_sim_level = 0, 0 ns, 0 ns);
constant c_tx_rx_loopback : boolean := g_direction /= "TX_ONLY";
constant c_tx_fifo_fill : natural := 100;
- constant c_pkt_length_arr1 : t_nat_natural_arr := array_init(0, 50, 1) & (1472, 1473) & 9000; -- frame longer than 1518-46 = 1472 is received with rx_sosi.err = 8
+ -- frame longer than 1518-46 = 1472 is received with rx_sosi.err = 8
+ constant c_pkt_length_arr1 : t_nat_natural_arr := array_init(0, 50, 1) & (1472, 1473) & 9000;
-- jumbo frame is 9018-46 = 8972
constant c_pkt_length_arr2 : t_nat_natural_arr := array_init(46, 10, 139) & 1472;
constant c_pkt_length_arr : t_nat_natural_arr := c_pkt_length_arr1 & c_pkt_length_arr2;
@@ -95,7 +105,8 @@ architecture tb of tb_tr_10GbE is
constant c_nof_pkt : natural := sel_a_b(g_verify_link_recovery, c_nof_pkt1 + c_nof_pkt2, c_nof_pkt1);
constant c_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"10FA01020300";
- constant c_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ -- = 12-34-56-78-9A-BC
+ constant c_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"123456789ABC";
constant c_src_mac_tx : std_logic_vector(c_network_eth_mac_slv'range) := c_src_mac;
--CONSTANT c_src_mac_tx : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"100056789ABC"; -- = 10-00-56-78-9A-BC
constant c_ethertype : std_logic_vector(c_network_eth_type_slv'range) := X"10FA";
@@ -105,42 +116,57 @@ architecture tb of tb_tr_10GbE is
constant c_eth_header_ethertype : t_network_eth_header := (c_dst_mac, c_src_mac_tx, c_ethertype);
constant c_eth_header_etherlen : t_network_eth_header := (c_dst_mac, c_src_mac_tx, c_etherlen);
- signal total_header : t_network_total_header := c_network_total_header_ones; -- default fill all fields with value 1
+ -- default fill all fields with value 1
+ signal total_header : t_network_total_header := c_network_total_header_ones;
-- Clocks and reset
signal tx_end_arr : std_logic_vector(g_nof_channels - 1 downto 0);
signal tx_end : std_logic;
signal rx_end : std_logic;
- signal cal_clk : std_logic := '1'; -- calibration clock
- signal mm_clk : std_logic; -- memory-mapped bus clock
- signal mm_rst : std_logic; -- reset synchronous with mm_clk
- signal dp_clk : std_logic := '1'; -- data path clock
- signal dp_rst : std_logic; -- reset synchronous with dp_clk
+ -- calibration clock
+ signal cal_clk : std_logic := '1';
+ -- memory-mapped bus clock
+ signal mm_clk : std_logic;
+ -- reset synchronous with mm_clk
+ signal mm_rst : std_logic;
+ -- data path clock
+ signal dp_clk : std_logic := '1';
+ -- reset synchronous with dp_clk
+ signal dp_rst : std_logic;
-- External reference clocks
- signal tr_ref_clk_644 : std_logic := '1'; -- 10GBASE-R
- signal tr_ref_clk_312 : std_logic; -- 10GBASE-R
- signal tr_ref_clk_156 : std_logic := '1'; -- 10GBASE-R or XAUI
- signal tr_ref_rst_156 : std_logic; -- 10GBASE-R or XAUI
+ -- 10GBASE-R
+ signal tr_ref_clk_644 : std_logic := '1';
+ -- 10GBASE-R
+ signal tr_ref_clk_312 : std_logic;
+ -- 10GBASE-R or XAUI
+ signal tr_ref_clk_156 : std_logic := '1';
+ -- 10GBASE-R or XAUI
+ signal tr_ref_rst_156 : std_logic;
-- MAC 10G control interface
signal mm_init : std_logic;
- signal mac_mosi_wrdata : std_logic_vector(c_word_w - 1 downto 0); -- for channel 0, 32 bit
+ -- for channel 0, 32 bit
+ signal mac_mosi_wrdata : std_logic_vector(c_word_w - 1 downto 0);
signal mac_mosi : t_mem_mosi;
signal mac_miso : t_mem_miso;
- signal mac_miso_rdval : std_logic; -- for channel 0
- signal mac_miso_rddata : std_logic_vector(c_word_w - 1 downto 0); -- for channel 0, 32 bit
+ -- for channel 0
+ signal mac_miso_rdval : std_logic;
+ -- for channel 0, 32 bit
+ signal mac_miso_rddata : std_logic_vector(c_word_w - 1 downto 0);
-- MAC 10G transmit interface
signal tx_en : std_logic := '1';
signal tx_siso_arr : t_dp_siso_arr(g_nof_channels - 1 downto 0);
signal tx_sosi_arr : t_dp_sosi_arr(g_nof_channels - 1 downto 0);
- signal tx_sosi_data : std_logic_vector(c_tech_mac_10g_data_w - 1 downto 0); -- for channel 0, 64 bit
+ -- for channel 0, 64 bit
+ signal tx_sosi_data : std_logic_vector(c_tech_mac_10g_data_w - 1 downto 0);
-- MAC 10G receive interface
signal rx_siso_arr : t_dp_siso_arr(g_nof_channels - 1 downto 0);
signal rx_sosi_arr : t_dp_sosi_arr(g_nof_channels - 1 downto 0);
- signal rx_sosi_data : std_logic_vector(c_tech_mac_10g_data_w - 1 downto 0); -- for channel 0, 64 bit
+ -- for channel 0, 64 bit
+ signal rx_sosi_data : std_logic_vector(c_tech_mac_10g_data_w - 1 downto 0);
-- PHY XAUI serial I/O
signal xaui_tx_arr : t_xaui_arr(g_nof_channels - 1 downto 0);
@@ -156,17 +182,21 @@ architecture tb of tb_tr_10GbE is
-- Verification
signal tx_pkt_cnt_arr : t_natural_arr(g_nof_channels - 1 downto 0) := (others => 0);
signal rx_pkt_cnt_arr : t_natural_arr(g_nof_channels - 1 downto 0) := (others => 0);
- signal rx_toggle_arr : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0'); -- toggle after every received packet
+ -- toggle after every received packet
+ signal rx_toggle_arr : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0');
begin
- cal_clk <= not cal_clk after cal_clk_period / 2; -- Calibration clock
+ -- Calibration clock
+ cal_clk <= not cal_clk after cal_clk_period / 2;
- dp_clk <= not dp_clk after g_dp_clk_period / 2; -- DP clock
+ -- DP clock
+ dp_clk <= not dp_clk after g_dp_clk_period / 2;
dp_rst <= '1', '0' after g_dp_clk_period * 10;
-- debug signals to ease monitoring in wave window
mac_mosi_wrdata <= mac_mosi.wrdata(c_word_w - 1 downto 0);
mac_miso_rddata <= mac_miso.rddata(c_word_w - 1 downto 0);
- mac_miso_rdval <= '1' when mac_mosi.rd = '1' and mac_miso.waitrequest = '0' else '0'; -- c_rd_latency = 1
+ -- c_rd_latency = 1
+ mac_miso_rdval <= '1' when mac_mosi.rd = '1' and mac_miso.waitrequest = '0' else '0';
tx_sosi_data <= tx_sosi_arr(0).data(c_tech_mac_10g_data_w - 1 downto 0);
rx_sosi_data <= rx_sosi_arr(0).data(c_tech_mac_10g_data_w - 1 downto 0);
@@ -245,21 +275,27 @@ begin
generic map (
g_technology => g_technology,
g_sim => c_sim,
- g_sim_level => g_sim_level, -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level => g_sim_level,
g_nof_macs => g_nof_channels,
g_direction => g_direction,
g_use_mdio => true,
- g_mdio_epcs_dis => true, -- TRUE disables Enhanced PCS on init; e.g. to target a 10GbE card in PC that does not support it
+ -- TRUE disables Enhanced PCS on init; e.g. to target a 10GbE card in PC that does not support it
+ g_mdio_epcs_dis => true,
g_tx_fifo_fill => c_tx_fifo_fill,
g_tx_fifo_size => 256,
g_word_alignment_padding => true
)
port map (
-- Transceiver PLL reference clock
- tr_ref_clk_644 => tr_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 => tr_ref_clk_644,
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 => tr_ref_clk_312,
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 => tr_ref_clk_156,
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156,
-- Calibration & reconfig clock
cal_rec_clk => cal_clk,
@@ -310,15 +346,18 @@ begin
g_link_delay => phy_delay
)
port map (
- link_fault => link_fault_arr(I), -- when '1' then forces rx_serial_arr(0)='0'
+ -- when '1' then forces rx_serial_arr(0)='0'
+ link_fault => link_fault_arr(I),
-- 10GBASE-R serial layer connect
serial_tx => serial_tx_arr(I),
- serial_rx => serial_rx_arr(I), -- connects to delayed tx_serial when g_loopback=TRUE
+ -- connects to delayed tx_serial when g_loopback=TRUE
+ serial_rx => serial_rx_arr(I),
-- XAUI serial layer connect
xaui_tx => xaui_tx_arr(I),
- xaui_rx => xaui_rx_arr(I) -- connects to delayed xaui_tx when g_loopback=TRUE
+ -- connects to delayed xaui_tx when g_loopback=TRUE
+ xaui_rx => xaui_rx_arr(I)
);
end generate;
diff --git a/libraries/io/tr_nonbonded/src/vhdl/mms_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/src/vhdl/mms_tr_nonbonded.vhd
index 080b2833fc184981953ff0dd67fafe0751ad2331..1c429ad26ff8d1a1802a68783f47eecb339f116a 100644
--- a/libraries/io/tr_nonbonded/src/vhdl/mms_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/src/vhdl/mms_tr_nonbonded.vhd
@@ -33,20 +33,25 @@ use technology_lib.technology_select_pkg.all;
entity mms_tr_nonbonded is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 0; -- Default: 0 = simulate IP. 1 = use fast behavioural model
+ -- Default: 0 = simulate IP. 1 = use fast behavioural model
+ g_sim_level : natural := 0;
g_technology : natural := c_tech_select_default;
g_data_w : natural := 32;
g_nof_gx : natural;
- g_mbps : natural := 6250; -- Supported: 6250, 5000, 3125, 2500
+ -- Supported: 6250, 5000, 3125, 2500
+ g_mbps : natural := 6250;
g_tx : boolean := true;
g_rx : boolean := true;
- g_tx_fifo_depth : natural := c_bram_m9k_fifo_depth; -- = 256 * 32b = 1 M9K, because g_data_w=32b, functionally a depth of c_meta_fifo_depth=16 is sufficient to cross the clock domain
- g_rx_fifo_depth : natural := c_bram_m9k_fifo_depth; -- = 256 * 32b = 1 M9K, because g_data_w=32b, functionally a depth of c_meta_fifo_depth=16 is sufficient to cross the clock domain
+ -- = 256 * 32b = 1 M9K, because g_data_w=32b, functionally a depth of c_meta_fifo_depth=16 is sufficient to cross the clock domain
+ g_tx_fifo_depth : natural := c_bram_m9k_fifo_depth;
+ -- = 256 * 32b = 1 M9K, because g_data_w=32b, functionally a depth of c_meta_fifo_depth=16 is sufficient to cross the clock domain
+ g_rx_fifo_depth : natural := c_bram_m9k_fifo_depth;
g_rx_use_data_buf : boolean := false;
g_rx_data_buf_nof_words : natural := 1024
);
port (
- tb_end : in std_logic := '0'; -- in simulation stop internal clocks when tb_end='1' to support 'run -all'
+ -- in simulation stop internal clocks when tb_end='1' to support 'run -all'
+ tb_end : in std_logic := '0';
-- System
mm_rst : in std_logic;
@@ -55,7 +60,8 @@ entity mms_tr_nonbonded is
st_clk : in std_logic := '0';
tr_clk : in std_logic;
cal_rec_clk : in std_logic;
- gp_out : out std_logic_vector(2 * g_nof_gx - 1 downto 0); -- FIFO full monitoring
+ -- FIFO full monitoring
+ gp_out : out std_logic_vector(2 * g_nof_gx - 1 downto 0);
-- Serial data I/O
tx_dataout : out std_logic_vector(g_nof_gx - 1 downto 0);
@@ -267,7 +273,8 @@ begin
generic map (
g_technology => g_technology,
-- Mux
- g_sel_ctrl_invert => true, -- We're using DOWNTO ranges in our streaming arrays, so we must invert the selection input
+ -- We're using DOWNTO ranges in our streaming arrays, so we must invert the selection input
+ g_sel_ctrl_invert => true,
g_mode => 2,
g_nof_input => c_nof_select,
g_append_channel_lo => false,
@@ -292,7 +299,8 @@ begin
u_dp_demux : entity dp_lib.dp_demux
generic map (
- g_sel_ctrl_invert => true, -- We're using DOWNTO ranges in our streaming arrays, so we must invert the selection input
+ -- We're using DOWNTO ranges in our streaming arrays, so we must invert the selection input
+ g_sel_ctrl_invert => true,
g_mode => 2,
g_nof_output => c_nof_select,
g_remove_channel_lo => false,
diff --git a/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd b/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd
index f148977a494aeecd11b2aa63765cca5aec5dbdc2..8475902832ff89a8c25ccb8d8772dbb95c1e9e86 100644
--- a/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd
@@ -34,7 +34,8 @@ entity tr_nonbonded is
g_technology : natural := c_tech_select_default;
g_data_w : natural := 32;
g_nof_gx : natural := 12;
- g_mbps : natural := 6250; -- Supported: 6250, 5000, 3125, 2500
+ -- Supported: 6250, 5000, 3125, 2500
+ g_mbps : natural := 6250;
------------------------------------------------------------------------------------------------
-- | g_sim | g_sim_level | Description
-- |--------------------------------------------------------------------------------------------
@@ -47,12 +48,16 @@ entity tr_nonbonded is
------------------------------------------------------------------------------------------------
g_tx : boolean := true;
g_rx : boolean := true;
- g_fifos : boolean := false; -- When TRUE use dp_clk and clock domain crossing FIFO for dp->tx and for rx->dp, when FALSE use rx_clk stream and tx_clk stream
- g_tx_fifo_depth : natural := c_bram_m9k_fifo_depth; -- = 256 * 32b = 1 M9K, because g_data_w=32b, functionally a depth of c_meta_fifo_depth=16 is sufficient to cross the clock domain
- g_rx_fifo_depth : natural := c_bram_m9k_fifo_depth -- = 256 * 32b = 1 M9K, because g_data_w=32b, functionally a depth of c_meta_fifo_depth=16 is sufficient to cross the clock domain
+ -- When TRUE use dp_clk and clock domain crossing FIFO for dp->tx and for rx->dp, when FALSE use rx_clk stream and tx_clk stream
+ g_fifos : boolean := false;
+ -- = 256 * 32b = 1 M9K, because g_data_w=32b, functionally a depth of c_meta_fifo_depth=16 is sufficient to cross the clock domain
+ g_tx_fifo_depth : natural := c_bram_m9k_fifo_depth;
+ -- = 256 * 32b = 1 M9K, because g_data_w=32b, functionally a depth of c_meta_fifo_depth=16 is sufficient to cross the clock domain
+ g_rx_fifo_depth : natural := c_bram_m9k_fifo_depth
);
port (
- tb_end : in std_logic := '0'; -- in simulation stop internal clocks when tb_end='1' to support 'run -all'
+ -- in simulation stop internal clocks when tb_end='1' to support 'run -all'
+ tb_end : in std_logic := '0';
-- DP clock domain (only used when g_fifos=TRUE)
st_rst : in std_logic;
@@ -197,8 +202,10 @@ begin
gen_i : for i in 0 to g_nof_gx - 1 generate
no_tx_fifo : if g_fifos = false generate
- tx_fifo_sosi_arr(i) <= tx_sosi_arr(i); -- for tx_fifo_sosi_arr it is needed to select between tx_sosi_arr and dp_tx_sosi_arr
- tx_siso_arr(i) <= tx_fifo_siso_arr(i); -- could default connect tx_siso_arr, but for clarity only connect tx_siso_arr when g_fifos = FALSE, else leave it 'X'
+ -- for tx_fifo_sosi_arr it is needed to select between tx_sosi_arr and dp_tx_sosi_arr
+ tx_fifo_sosi_arr(i) <= tx_sosi_arr(i);
+ -- could default connect tx_siso_arr, but for clarity only connect tx_siso_arr when g_fifos = FALSE, else leave it 'X'
+ tx_siso_arr(i) <= tx_fifo_siso_arr(i);
end generate;
gen_tx_fifo : if g_fifos = true generate
@@ -227,9 +234,12 @@ begin
src_in => tx_fifo_siso_arr(i),
src_out => tx_fifo_sosi_arr(i)
);
- end generate; -- gen_tx_fifo
- end generate; -- gen_i
- end generate; -- gen_tx
+ -- gen_tx_fifo
+ end generate;
+ -- gen_i
+ end generate;
+ -- gen_tx
+ end generate;
-- === RX === RX === RX === RX === RX === RX === RX === RX === RX === RX === RX === RX === RX === RX === RX === RX
gen_rx : if g_rx = true generate
@@ -240,8 +250,10 @@ begin
rx_dataout(i)(g_data_w - 1 downto 0) <= rx_fifo_sosi_arr(i).data(g_data_w - 1 downto 0);
no_rx_fifo : if g_fifos = false generate
- rx_sosi_arr(i) <= rx_fifo_sosi_arr(i); -- could default connect rx_sosi_arr, but for clarity only connect rx_sosi_arr when g_fifos = FALSE, else leave it 'X'
- rx_fifo_siso_arr(i) <= rx_siso_arr(i); -- for rx_fifo_siso_arr it is needed to select between rx_siso_arr and dp_rx_siso_arr
+ -- could default connect rx_sosi_arr, but for clarity only connect rx_sosi_arr when g_fifos = FALSE, else leave it 'X'
+ rx_sosi_arr(i) <= rx_fifo_sosi_arr(i);
+ -- for rx_fifo_siso_arr it is needed to select between rx_siso_arr and dp_rx_siso_arr
+ rx_fifo_siso_arr(i) <= rx_siso_arr(i);
end generate;
gen_rx_fifo : if g_fifos = true generate
@@ -270,7 +282,10 @@ begin
src_in => dp_rx_siso_arr(i),
src_out => dp_rx_sosi_arr(i)
);
- end generate; -- gen_rx_fifo
- end generate; -- gen_i
- end generate; -- gen_rx
+ -- gen_rx_fifo
+ end generate;
+ -- gen_i
+ end generate;
+ -- gen_rx
+ end generate;
end str;
diff --git a/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded_reg.vhd b/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded_reg.vhd
index 62aa54ca01956ace978f341f0ebf9d4a24e6c864..36d75251ba7f01943df3efb9795f720fe1b18990 100644
--- a/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded_reg.vhd
+++ b/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded_reg.vhd
@@ -99,13 +99,16 @@ begin
when 2 =>
mm_rx_align_en(g_nof_gx - 1 downto 0) <= sla_in.wrdata(g_nof_gx - 1 downto 0);
- when others => null; -- not used MM addresses
+ -- not used MM addresses
+ when others => null;
end case;
-- Read access: get register value
elsif sla_in.rd = '1' then
- sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+ -- set unused rddata bits to '0' when read
+ sla_out <= c_mem_miso_rst;
+ -- c_mm_reg.latency = 1
+ sla_out.rdval <= '1';
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
-- Read Block Sync
when 1 =>
diff --git a/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
index 1f7f9a16d2eb452ff541299741fd04fb9190c103..e19aa69a3ba3528139c5a8f4d68e52cad40f6489 100644
--- a/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
@@ -35,7 +35,8 @@ end tb_tb_tr_nonbonded;
architecture tb of tb_tb_tr_nonbonded is
constant c_tb_end_vec : std_logic_vector(7 downto 0) := (others => '1');
- signal tb_end_vec : std_logic_vector(7 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ -- sufficiently long to fit all tb instances
+ signal tb_end_vec : std_logic_vector(7 downto 0) := c_tb_end_vec;
signal tb_end : std_logic := '0';
begin
-- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
diff --git a/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
index 623b6e66aafb742a6ce6e74d63837c9d56a8c4c1..31d874ae77045dc7e0f0fe68490bb7e3c9d4a4ad 100644
--- a/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
@@ -70,7 +70,8 @@ use dp_lib.dp_stream_pkg.all;
entity tb_tr_nonbonded is
generic (
- g_tb_end : boolean := true; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ g_tb_end : boolean := true;
g_data_w : natural := 32;
g_sim_level : natural := 1
);
@@ -84,10 +85,13 @@ architecture str of tb_tr_nonbonded is
constant c_nof_gx : natural := 1;
constant c_mbps : natural := 6250;
- constant tr_clk_period : time := 6.4 ns; -- 156.25 MHz
- constant st_clk_period : time := 5 ns; -- 200 MHz
+ -- 156.25 MHz
+ constant tr_clk_period : time := 6.4 ns;
+ -- 200 MHz
+ constant st_clk_period : time := 5 ns;
- constant cal_rec_clk_period : time := 25 ns; -- 40 MHz
+ -- 40 MHz
+ constant cal_rec_clk_period : time := 25 ns;
signal cal_rec_clk : std_logic := '0';
signal fn_tr_clk : std_logic := '0';
@@ -134,7 +138,8 @@ begin
begin
bn_clk_en <= '0';
if g_sim_level = 0 then
- wait for 1.6 ns; -- with PHY use bn_tr_clk 1/4 cycle behind fn_tr_clk, with sim model the all tr_clk must have the same phase
+ -- with PHY use bn_tr_clk 1/4 cycle behind fn_tr_clk, with sim model the all tr_clk must have the same phase
+ wait for 1.6 ns;
end if;
bn_clk_en <= '1';
wait;
diff --git a/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd b/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd
index a2423241e25de40ef94f81bf2aebc7ade5021cb6..eef25e8591a860ec635acf184ed3b11be8b4a341 100644
--- a/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd
@@ -34,12 +34,14 @@ entity mms_tr_xaui is
generic (
g_sim : boolean := false;
g_technology : natural := c_tech_select_default;
- g_nof_xaui : natural := 1; -- Up to 3 (hard XAUI only) supported
+ -- Up to 3 (hard XAUI only) supported
+ g_nof_xaui : natural := 1;
g_use_mdio : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_clk : in std_logic; -- 156.25 MHz
+ -- 156.25 MHz
+ tr_clk : in std_logic;
tr_rst : in std_logic;
-- Calibration & reconfiguration clock
@@ -59,14 +61,17 @@ entity mms_tr_xaui is
mdio_miso_arr : out t_mem_miso_arr(g_nof_xaui - 1 downto 0);
-- Streaming TX interfaces
- tx_clk_arr : in std_logic_vector(g_nof_xaui - 1 downto 0); -- 156.25 MHz, externally connect tr_clk to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
+ -- 156.25 MHz, externally connect tr_clk to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
+ tx_clk_arr : in std_logic_vector(g_nof_xaui - 1 downto 0);
tx_rst_arr : out std_logic_vector(g_nof_xaui - 1 downto 0);
tx_sosi_arr : in t_dp_sosi_arr(g_nof_xaui - 1 downto 0) := (others => c_dp_sosi_rst);
tx_siso_arr : out t_dp_siso_arr(g_nof_xaui - 1 downto 0);
-- Streaming RX interfaces
- rx_clk_arr_out : out std_logic_vector(g_nof_xaui - 1 downto 0); -- recovered clock per XAUI
- rx_clk_arr_in : in std_logic_vector(g_nof_xaui - 1 downto 0); -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ -- recovered clock per XAUI
+ rx_clk_arr_out : out std_logic_vector(g_nof_xaui - 1 downto 0);
+ -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ rx_clk_arr_in : in std_logic_vector(g_nof_xaui - 1 downto 0);
rx_rst_arr : out std_logic_vector(g_nof_xaui - 1 downto 0);
rx_sosi_arr : out t_dp_sosi_arr(g_nof_xaui - 1 downto 0);
rx_siso_arr : in t_dp_siso_arr(g_nof_xaui - 1 downto 0) := (others => c_dp_siso_rst);
@@ -225,7 +230,8 @@ begin
u_dp_mux : entity dp_lib.dp_mux
generic map (
-- Mux
- g_sel_ctrl_invert => true, -- We're using DOWNTO ranges in out streaming arrays, so we must invert the selection input
+ -- We're using DOWNTO ranges in out streaming arrays, so we must invert the selection input
+ g_sel_ctrl_invert => true,
g_mode => 2,
g_nof_input => c_nof_select,
g_append_channel_lo => false,
@@ -259,7 +265,8 @@ begin
u_dp_demux : entity dp_lib.dp_demux
generic map (
- g_sel_ctrl_invert => true, -- We're using DOWNTO ranges in out streaming arrays, so we must invert the selection input
+ -- We're using DOWNTO ranges in out streaming arrays, so we must invert the selection input
+ g_sel_ctrl_invert => true,
g_mode => 2,
g_nof_output => c_nof_select,
g_remove_channel_lo => false,
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
index b93a840b0650b4fabb4d6344b09ba86f568ee5b6..30e59c2ffc0f9420b1530ceb23c06f8f7a74abce 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
@@ -34,15 +34,20 @@ entity tr_xaui is
generic (
g_technology : natural := c_tech_select_default;
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
- g_use_xgmii : boolean := false; -- Don't use streaming I/O but XGMII (e.g. conenct to 10GbE MAC)
- g_nof_xaui : natural := 1; -- Up to 3 (hard XAUI only) supported
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
+ -- Don't use streaming I/O but XGMII (e.g. conenct to 10GbE MAC)
+ g_use_xgmii : boolean := false;
+ -- Up to 3 (hard XAUI only) supported
+ g_nof_xaui : natural := 1;
g_use_mdio : boolean := false;
- g_mdio_epcs_dis : boolean := false -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
+ -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
+ g_mdio_epcs_dis : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_clk : in std_logic; -- 156.25 MHz
+ -- 156.25 MHz
+ tr_clk : in std_logic;
tr_rst : in std_logic;
-- Calibration & reconfiguration clock
@@ -59,14 +64,18 @@ entity tr_xaui is
mdio_miso_arr : out t_mem_miso_arr(g_nof_xaui - 1 downto 0);
-- Streaming TX interfaces
- tx_clk_arr : in std_logic_vector(g_nof_xaui - 1 downto 0); -- 156.25 MHz, externally connect tr_clk to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
- tx_rst_arr : out std_logic_vector(g_nof_xaui - 1 downto 0); -- tx_rst release depends on XAUI ready
+ -- 156.25 MHz, externally connect tr_clk to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
+ tx_clk_arr : in std_logic_vector(g_nof_xaui - 1 downto 0);
+ -- tx_rst release depends on XAUI ready
+ tx_rst_arr : out std_logic_vector(g_nof_xaui - 1 downto 0);
tx_sosi_arr : in t_dp_sosi_arr(g_nof_xaui - 1 downto 0) := (others => c_dp_sosi_rst);
tx_siso_arr : out t_dp_siso_arr(g_nof_xaui - 1 downto 0);
-- Streaming RX interfaces
- rx_clk_arr_out : out std_logic_vector(g_nof_xaui - 1 downto 0); -- recovered clock per XAUI
- rx_clk_arr_in : in std_logic_vector(g_nof_xaui - 1 downto 0); -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ -- recovered clock per XAUI
+ rx_clk_arr_out : out std_logic_vector(g_nof_xaui - 1 downto 0);
+ -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ rx_clk_arr_in : in std_logic_vector(g_nof_xaui - 1 downto 0);
rx_rst_arr : out std_logic_vector(g_nof_xaui - 1 downto 0);
rx_sosi_arr : out t_dp_sosi_arr(g_nof_xaui - 1 downto 0);
rx_siso_arr : in t_dp_siso_arr(g_nof_xaui - 1 downto 0) := (others => c_dp_siso_rst);
@@ -195,7 +204,8 @@ begin
src_out => rx_sosi_arr(i)
);
- end generate; -- g_nof_xaui
+ -- g_nof_xaui
+ end generate;
end generate;
---------------------------------------------------------------------------
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui_deframer.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui_deframer.vhd
index 75a6f90acaba2e7c023fb842b76b06a15dc0f850..5e505a9fa097fb1983df93a3806442ff54999f89 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui_deframer.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui_deframer.vhd
@@ -39,12 +39,15 @@ entity tr_xaui_deframer is
end tr_xaui_deframer;
architecture rtl of tr_xaui_deframer is
- constant c_xgmii_c_start_lo : std_logic_vector(c_xgmii_nof_lanes / 2 - 1 downto 0) := c_xgmii_c_start(c_xgmii_nof_lanes / 2 - 1 downto 0); -- 0x1
- constant c_xgmii_c_term_lo : std_logic_vector(c_xgmii_nof_lanes / 2 - 1 downto 0) := c_xgmii_c_term (c_xgmii_nof_lanes / 2 - 1 downto 0); -- 0x8
+ -- 0x1
+ constant c_xgmii_c_start_lo : std_logic_vector(c_xgmii_nof_lanes / 2 - 1 downto 0) := c_xgmii_c_start(c_xgmii_nof_lanes / 2 - 1 downto 0);
+ -- 0x8
+ constant c_xgmii_c_term_lo : std_logic_vector(c_xgmii_nof_lanes / 2 - 1 downto 0) := c_xgmii_c_term (c_xgmii_nof_lanes / 2 - 1 downto 0);
-- We need to look at the data when we receive the c_xgmii_c_start_lo as control, as the control bits happen to be the same during lane alignment.
-- In that case, the incoming data word is 0x01000009C on both the LS and MS word, and we don't want to mistake that for data.
- constant c_xgmii_d_start_lo : std_logic_vector(c_xgmii_data_w / 2 - 1 downto 0) := c_xgmii_d_start(c_xgmii_data_w / 2 - 1 downto 0); -- 0x000000FB
+ -- 0x000000FB
+ constant c_xgmii_d_start_lo : std_logic_vector(c_xgmii_data_w / 2 - 1 downto 0) := c_xgmii_d_start(c_xgmii_data_w / 2 - 1 downto 0);
type t_state_enum is (s_init, s_gap, s_data, s_data_misaligned);
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui_framer.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui_framer.vhd
index 5b678cd51c515fb4be7b4098e4573d7bd8887d2e..82eba60119d6b9bcb48792c7cf05166446cbaa36 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui_framer.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui_framer.vhd
@@ -28,8 +28,10 @@ use dp_lib.dp_stream_pkg.all;
entity tr_xaui_framer is
generic (
- g_dat_len : natural := 1000000; -- Max number of cycles carrying user data
- g_gap_len : natural := 5 -- Gap length, including 2 cycles for the START and TERMINATE words
+ -- Max number of cycles carrying user data
+ g_dat_len : natural := 1000000;
+ -- Gap length, including 2 cycles for the START and TERMINATE words
+ g_gap_len : natural := 5
);
port (
tx_clk : in std_logic;
@@ -86,7 +88,8 @@ begin
src_out => gap_sosi
);
- gap_siso <= c_dp_siso_rdy; -- no flow control
+ -- no flow control
+ gap_siso <= c_dp_siso_rdy;
-- As the dp_gap takes care of the frame length and the gap length, all our FSM needs
-- to do is to take care of xgmii data and control words:
@@ -137,14 +140,16 @@ begin
nxt_xgmii_tx_c <= c_xgmii_c_start;
end if;
- when s_data => -- Forward the data stored in prev_gap_sosi
+ -- Forward the data stored in prev_gap_sosi
+ when s_data =>
nxt_xgmii_tx_d <= prev_gap_sosi.data(c_xgmii_data_w - 1 downto 0);
nxt_xgmii_tx_c <= c_xgmii_c_data;
if gap_sosi.valid = '0' then
nxt_state <= s_gap;
end if;
- when others => -- s_init
+ -- s_init
+ when others =>
nxt_state <= s_gap;
nxt_xgmii_tx_d <= c_xgmii_d_idle;
nxt_xgmii_tx_c <= c_xgmii_c_idle;
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd
index 532e735e4bd768c56a538e47e9303b511071db8c..463c0531948cd4be9769c5df8e24f0203bab5c3a 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd
@@ -30,8 +30,10 @@ use mdio_lib.mdio_vitesse_vsc8486_pkg.all;
entity tr_xaui_mdio is
generic (
g_sim : boolean := false;
- g_nof_xaui : natural := 1; -- Up to 3 (hard XAUI only) supported
- g_mdio_epcs_dis : boolean := false -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
+ -- Up to 3 (hard XAUI only) supported
+ g_nof_xaui : natural := 1;
+ -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
+ g_mdio_epcs_dis : boolean := false
);
port (
-- Transceiver PLL reference clock
@@ -55,7 +57,8 @@ entity tr_xaui_mdio is
end tr_xaui_mdio;
architecture str of tr_xaui_mdio is
- constant c_mdio_xaui_phy_mdc_period : natural := 256; -- must be a power of 2
+ -- must be a power of 2
+ constant c_mdio_xaui_phy_mdc_period : natural := 256;
constant c_mdio_xaui_phy_hold_time : natural := 10;
constant c_mdio_xaui_phy_setup_time : natural := 2;
diff --git a/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd b/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd
index efe6772df5f67cf30c86aa0602ef24e64bafc3d3..ea330c842975228cbc682be7c871382ebcff8dbd 100644
--- a/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd
+++ b/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd
@@ -35,7 +35,8 @@ end tb_tb_tr_xaui;
architecture tb of tb_tb_tr_xaui is
constant c_tb_end_vec : std_logic_vector(31 downto 0) := (others => '1');
- signal tb_end_vec : std_logic_vector(31 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ -- sufficiently long to fit all tb instances
+ signal tb_end_vec : std_logic_vector(31 downto 0) := c_tb_end_vec;
signal tb_end : std_logic := '0';
begin
-- g_technology : NATURAL := c_tech_stratixiv;
diff --git a/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd b/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd
index ba35ff1c89f7487e8c49996137ac0ec24b9fbe47..c68f9984c9bcb0fb2d2791a85ea8a6dbf4d555dd 100644
--- a/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd
+++ b/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd
@@ -39,8 +39,10 @@ use technology_lib.technology_pkg.all;
entity tb_tr_xaui is
generic (
g_technology : natural := c_tech_stratixiv;
- g_tb_end : boolean := true; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
- g_sim_level : natural := 0 -- 0 = use IP; 1 = use fast serdes model
+ -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ g_tb_end : boolean := true;
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0
);
port (
tb_end : out std_logic
@@ -48,14 +50,20 @@ entity tb_tr_xaui is
end entity tb_tr_xaui;
architecture str of tb_tr_xaui is
- constant c_sim : boolean := true; -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation
+ -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation
+ constant c_sim : boolean := true;
- constant tr_clk_period : time := 6.4 ns; -- 156.25 MHz
- constant tx_clk_period : time := 6.4 ns; -- 156.25 MHz
- constant mm_clk_period : time := 25 ns; -- 40 MHz
- constant cal_rec_clk_period : time := 25 ns; -- 40 MHz
+ -- 156.25 MHz
+ constant tr_clk_period : time := 6.4 ns;
+ -- 156.25 MHz
+ constant tx_clk_period : time := 6.4 ns;
+ -- 40 MHz
+ constant mm_clk_period : time := 25 ns;
+ -- 40 MHz
+ constant cal_rec_clk_period : time := 25 ns;
- constant phy_delay : time := sel_a_b(g_sim_level > 0, tr_clk_period * 1, 1 ns); -- the sim_xaui only works without unit PHY delays
+ -- the sim_xaui only works without unit PHY delays
+ constant phy_delay : time := sel_a_b(g_sim_level > 0, tr_clk_period * 1, 1 ns);
constant c_nof_streams : natural := 1;
constant c_xgmii_data_w : natural := 64;
@@ -105,21 +113,27 @@ begin
snk_diag_en <= (others => '0');
src_diag_en <= (others => '0');
verify_en <= '0';
- wait for 2 us; -- use e.g. wait for 1800 ns to check that p_verify indeed detects errors
+ -- use e.g. wait for 1800 ns to check that p_verify indeed detects errors
+ wait for 2 us;
-- verify link
proc_common_wait_until_low(rx_clk, rx_rst);
proc_common_wait_some_cycles(tx_clk, 20);
- src_diag_en <= (others => '1'); -- first enable Tx seq
+ -- first enable Tx seq
+ src_diag_en <= (others => '1');
proc_common_wait_some_cycles(rx_clk, 20);
- snk_diag_en <= (others => '1'); -- then enable Rx seq
+ -- then enable Rx seq
+ snk_diag_en <= (others => '1');
proc_common_wait_some_cycles(rx_clk, 50);
- verify_en <= '1'; -- p_verify that Rx seq result is OK
+ -- p_verify that Rx seq result is OK
+ verify_en <= '1';
wait for 5 us;
-- model link fault
- verify_en <= '0'; -- p_verify stop
- snk_diag_en <= (others => '0'); -- disable Rx seq to avoid Error due to link_fault, keep Tx seq enabled
+ -- p_verify stop
+ verify_en <= '0';
+ -- disable Rx seq to avoid Error due to link_fault, keep Tx seq enabled
+ snk_diag_en <= (others => '0');
link_fault <= '1';
wait for 1 us;
@@ -128,9 +142,11 @@ begin
wait for 1 us;
proc_common_wait_until_low(rx_clk, rx_rst);
proc_common_wait_some_cycles(rx_clk, 20);
- snk_diag_en <= (others => '1'); -- enable Rx seq again
+ -- enable Rx seq again
+ snk_diag_en <= (others => '1');
proc_common_wait_some_cycles(rx_clk, 50);
- verify_en <= '1'; -- p_verify that Rx seq result is OK
+ -- p_verify that Rx seq result is OK
+ verify_en <= '1';
wait for 5 us;
-- Stop the simulation
diff --git a/libraries/technology/10gbase_r/sim_10gbase_r.vhd b/libraries/technology/10gbase_r/sim_10gbase_r.vhd
index 2c3e4959cf2e0cdf4860e3b5d384005d80a1e5b9..d65349a82def0d4cbe46d5312314c9df1dcb4fe6 100644
--- a/libraries/technology/10gbase_r/sim_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/sim_10gbase_r.vhd
@@ -41,17 +41,23 @@ entity sim_10gbase_r is
);
port (
-- Transceiver ATX PLL reference clock
- tr_ref_clk_644 : in std_logic; -- 644.531250 MHz
+ -- 644.531250 MHz
+ tr_ref_clk_644 : in std_logic;
-- XGMII clocks
- clk_156 : in std_logic; -- 156.25 MHz
+ -- 156.25 MHz
+ clk_156 : in std_logic;
rst_156 : in std_logic;
-- XGMII interface
- xgmii_tx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0); -- can be used for xon flow control
- xgmii_rx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0); -- typically leave not connected
- xgmii_tx_dc_arr : in t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
- xgmii_rx_dc_arr : out t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
+ -- can be used for xon flow control
+ xgmii_tx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
+ -- typically leave not connected
+ xgmii_rx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ xgmii_tx_dc_arr : in t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ xgmii_rx_dc_arr : out t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
-- PHY serial IO
tx_serial_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
@@ -60,10 +66,13 @@ entity sim_10gbase_r is
end sim_10gbase_r;
architecture str of sim_10gbase_r is
- constant c_tr_clk_period : time := tech_pll_clk_156_period; -- 6.400020 ns ~= 156.25 MHz --> model line rate : 156.25 MHz * 10/8 (encoding) * 64b (data width) = 12500 Mbps / lane
+ -- 6.400020 ns ~= 156.25 MHz --> model line rate : 156.25 MHz * 10/8 (encoding) * 64b (data width) = 12500 Mbps / lane
+ constant c_tr_clk_period : time := tech_pll_clk_156_period;
- constant c_serdes_data_w : natural := c_xgmii_data_w; -- 64 b
- constant c_serdes_ctrl_w : natural := c_xgmii_ctrl_w; -- 8 b
+ -- 64 b
+ constant c_serdes_data_w : natural := c_xgmii_data_w;
+ -- 8 b
+ constant c_serdes_ctrl_w : natural := c_xgmii_ctrl_w;
-- XGMII control bits (one for each XGMII lane):
signal xgmii_tx_c_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0);
diff --git a/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd b/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
index 1ca8d66bf7b673cfa60b1c624cea621ff52cc2b8..e2dfa9e50b53062faaae9dc5f67177163941b448 100644
--- a/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
@@ -54,7 +54,8 @@ end tb_tech_10gbase_r;
architecture tb of tb_tech_10gbase_r is
constant c_sim : boolean := true;
- constant c_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model (not useful here, because no proper xgmii_tx_dc_arr stimuli)
+ -- 0 = use IP; 1 = use fast serdes model (not useful here, because no proper xgmii_tx_dc_arr stimuli)
+ constant c_sim_level : natural := 0;
constant phy_loopback_delay : time := sel_a_b(c_sim_level = 0, 1 ns, 0 ns);
signal tb_end : std_logic := '0';
@@ -65,7 +66,8 @@ architecture tb of tb_tech_10gbase_r is
-- XGMII interface
signal xgmii_tx_ready_arr : std_logic_vector(g_nof_channels - 1 downto 0);
signal xgmii_rx_ready_arr : std_logic_vector(g_nof_channels - 1 downto 0);
- signal xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0) := (others => (others => '0')); -- '0', '1'
+ -- '0', '1'
+ signal xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0) := (others => (others => '0'));
signal xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
-- PHY serial interface
@@ -153,7 +155,8 @@ begin
begin
rx_serial_arr <= tx_serial_arr_dly;
if link_fault = '1' then
- rx_serial_arr(0) <= '0'; -- model link fault only for channel 0
+ -- model link fault only for channel 0
+ rx_serial_arr(0) <= '0';
end if;
end process;
end tb;
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r.vhd b/libraries/technology/10gbase_r/tech_10gbase_r.vhd
index f2bfdc6e44ad7c9b00f26661875840ce34eee2d6..ab15878a2326dce63695a5a924a4a9df92d09d30 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r.vhd
@@ -32,7 +32,8 @@ entity tech_10gbase_r is
generic (
g_technology : natural := c_tech_select_default;
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1
);
port (
@@ -46,17 +47,23 @@ entity tech_10gbase_r is
reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_ip_arria10_e2sg_phy_10gbase_r_24_miso : out t_mem_miso;
-- Transceiver ATX PLL reference clock
- tr_ref_clk_644 : in std_logic; -- 644.531250 MHz
+ -- 644.531250 MHz
+ tr_ref_clk_644 : in std_logic;
-- XGMII clocks
- clk_156 : in std_logic; -- 156.25 MHz
+ -- 156.25 MHz
+ clk_156 : in std_logic;
rst_156 : in std_logic;
-- XGMII interface
- xgmii_tx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0); -- can be used for xon flow control
- xgmii_rx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0); -- typically leave not connected
- xgmii_tx_dc_arr : in t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
- xgmii_rx_dc_arr : out t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
+ -- can be used for xon flow control
+ xgmii_tx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
+ -- typically leave not connected
+ xgmii_rx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ xgmii_tx_dc_arr : in t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ xgmii_rx_dc_arr : out t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
-- PHY serial IO
tx_serial_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
index f106ec2d00a625f32cd321a3bdd7d2c41fde0a25..890b1932b3f126b2053585b42ccf53dadca05b0e 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
@@ -47,17 +47,23 @@ entity tech_10gbase_r_arria10 is
);
port (
-- Transceiver ATX PLL reference clock
- tr_ref_clk_644 : in std_logic; -- 644.531250 MHz
+ -- 644.531250 MHz
+ tr_ref_clk_644 : in std_logic;
-- XGMII clocks
- clk_156 : in std_logic; -- 156.25 MHz
+ -- 156.25 MHz
+ clk_156 : in std_logic;
rst_156 : in std_logic;
-- XGMII interface
- xgmii_tx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0); -- can be used for xon flow control
- xgmii_rx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0); -- typically leave not connected
- xgmii_tx_dc_arr : in t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
- xgmii_rx_dc_arr : out t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
+ -- can be used for xon flow control
+ xgmii_tx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
+ -- typically leave not connected
+ xgmii_rx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ xgmii_tx_dc_arr : in t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ xgmii_rx_dc_arr : out t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
-- PHY serial IO
tx_serial_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
@@ -72,7 +78,8 @@ architecture str of tech_10gbase_r_arria10 is
--CONSTANT c_nof_channels_per_ip : NATURAL := 24 WHEN g_nof_channels=24 ELSE 12 WHEN g_nof_channels=12 ELSE 1;
constant c_nof_channels_per_ip : natural := g_nof_channels;
- constant IP_SIZE : natural := c_nof_channels_per_ip; -- short constant name alias to improve index readability
+ -- short constant name alias to improve index readability
+ constant IP_SIZE : natural := c_nof_channels_per_ip;
constant IP_SIZE_DATA : natural := IP_SIZE * c_xgmii_data_w;
constant IP_SIZE_CONTROL : natural := IP_SIZE * c_xgmii_nof_lanes;
@@ -80,18 +87,26 @@ architecture str of tech_10gbase_r_arria10 is
signal tr_coreclkin : std_logic_vector(0 downto 0);
- signal tx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0); -- 64 bit
- signal rx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0); -- 64 bit
- signal tx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0); -- 8 bit
- signal rx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0); -- 8 bit
+ -- 64 bit
+ signal tx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0);
+ -- 64 bit
+ signal rx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0);
+ -- 8 bit
+ signal tx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0);
+ -- 8 bit
+ signal rx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0);
-- IP block SLV signals
signal tx_serial_clk_slv : std_logic_vector(g_nof_channels - 1 downto 0);
signal tr_coreclkin_slv : std_logic_vector(g_nof_channels - 1 downto 0);
- signal tx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0); -- 64 bit
- signal rx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0); -- 64 bit
- signal tx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0); -- 8 bit
- signal rx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0); -- 8 bit
+ -- 64 bit
+ signal tx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0);
+ -- 64 bit
+ signal rx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0);
+ -- 8 bit
+ signal tx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0);
+ -- 8 bit
+ signal rx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0);
-- transceiver reset controller
signal tx_analogreset_arr : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '1');
@@ -152,8 +167,10 @@ begin
rx_is_lockedtoref => OPEN,
rx_is_lockedtodata => rx_is_lockedtodata_arr(I downto I),
- tx_coreclkin => tr_coreclkin, -- 156.25 MHz
- rx_coreclkin => tr_coreclkin, -- 156.25 MHz
+ -- 156.25 MHz
+ tx_coreclkin => tr_coreclkin,
+ -- 156.25 MHz
+ rx_coreclkin => tr_coreclkin,
tx_parallel_data => tx_parallel_data_arr(I),
rx_parallel_data => rx_parallel_data_arr(I),
@@ -190,7 +207,8 @@ begin
tx_digitalreset => tx_digitalreset_arr(I downto I),
tx_ready => xgmii_tx_ready_arr(I downto I),
pll_locked => atx_pll_locked_arr(I downto I),
- pll_select => "0", -- set to zero when using one PLL
+ -- set to zero when using one PLL
+ pll_select => "0",
tx_cal_busy => cal_busy_arr(I downto I),
rx_analogreset => rx_analogreset_arr(I downto I),
rx_digitalreset => rx_digitalreset_arr(I downto I),
@@ -215,28 +233,45 @@ begin
u_ip_arria10_phy_10gbase_r_4 : ip_arria10_phy_10gbase_r_4
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -265,20 +300,34 @@ begin
u_ip_arria10_transceiver_reset_controller_4 : ip_arria10_transceiver_reset_controller_4
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
@@ -296,28 +345,45 @@ begin
u_ip_arria10_phy_10gbase_r_12 : ip_arria10_phy_10gbase_r_12
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -346,20 +412,34 @@ begin
u_ip_arria10_transceiver_reset_controller_12 : ip_arria10_transceiver_reset_controller_12
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
@@ -377,28 +457,45 @@ begin
u_ip_arria10_phy_10gbase_r_24 : ip_arria10_phy_10gbase_r_24
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -427,20 +524,34 @@ begin
u_ip_arria10_transceiver_reset_controller_24 : ip_arria10_transceiver_reset_controller_24
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
@@ -458,28 +569,45 @@ begin
u_ip_arria10_phy_10gbase_r_48 : ip_arria10_phy_10gbase_r_48
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -508,27 +636,42 @@ begin
u_ip_arria10_transceiver_reset_controller_48 : ip_arria10_transceiver_reset_controller_48
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
-- ATX PLL
u_ip_arria10_transceiver_pll_10g : ip_arria10_transceiver_pll_10g
port map (
- pll_powerdown => atx_pll_powerdown_arr(0), -- only use reset controller 0 for ATX PLL power down, leave others not used
+ -- only use reset controller 0 for ATX PLL power down, leave others not used
+ pll_powerdown => atx_pll_powerdown_arr(0),
pll_refclk0 => tr_ref_clk_644,
pll_locked => atx_pll_locked,
pll_cal_busy => atx_pll_cal_busy,
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
index b69ecf769b7f83c1c57ffa17e339b5e6fdc9b0f8..8f4d88a38dbdfdc55d71d821d9d023e6175efa11 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
@@ -55,17 +55,23 @@ entity tech_10gbase_r_arria10_e1sg is
reg_ip_arria10_e1sg_phy_10gbase_r_24_miso : out t_mem_miso;
-- Transceiver ATX PLL reference clock
- tr_ref_clk_644 : in std_logic; -- 644.531250 MHz
+ -- 644.531250 MHz
+ tr_ref_clk_644 : in std_logic;
-- XGMII clocks
- clk_156 : in std_logic; -- 156.25 MHz
+ -- 156.25 MHz
+ clk_156 : in std_logic;
rst_156 : in std_logic;
-- XGMII interface
- xgmii_tx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0); -- can be used for xon flow control
- xgmii_rx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0); -- typically leave not connected
- xgmii_tx_dc_arr : in t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
- xgmii_rx_dc_arr : out t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
+ -- can be used for xon flow control
+ xgmii_tx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
+ -- typically leave not connected
+ xgmii_rx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ xgmii_tx_dc_arr : in t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ xgmii_rx_dc_arr : out t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
-- PHY serial IO
tx_serial_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
@@ -80,7 +86,8 @@ architecture str of tech_10gbase_r_arria10_e1sg is
--CONSTANT c_nof_channels_per_ip : NATURAL := 24 WHEN g_nof_channels=24 ELSE 12 WHEN g_nof_channels=12 ELSE 1;
constant c_nof_channels_per_ip : natural := g_nof_channels;
- constant IP_SIZE : natural := c_nof_channels_per_ip; -- short constant name alias to improve index readability
+ -- short constant name alias to improve index readability
+ constant IP_SIZE : natural := c_nof_channels_per_ip;
constant IP_SIZE_DATA : natural := IP_SIZE * c_xgmii_data_w;
constant IP_SIZE_CONTROL : natural := IP_SIZE * c_xgmii_nof_lanes;
@@ -88,18 +95,26 @@ architecture str of tech_10gbase_r_arria10_e1sg is
signal tr_coreclkin : std_logic_vector(0 downto 0);
- signal tx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0); -- 64 bit
- signal rx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0); -- 64 bit
- signal tx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0); -- 8 bit
- signal rx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0); -- 8 bit
+ -- 64 bit
+ signal tx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0);
+ -- 64 bit
+ signal rx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0);
+ -- 8 bit
+ signal tx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0);
+ -- 8 bit
+ signal rx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0);
-- IP block SLV signals
signal tx_serial_clk_slv : std_logic_vector(g_nof_channels - 1 downto 0);
signal tr_coreclkin_slv : std_logic_vector(g_nof_channels - 1 downto 0);
- signal tx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0); -- 64 bit
- signal rx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0); -- 64 bit
- signal tx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0); -- 8 bit
- signal rx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0); -- 8 bit
+ -- 64 bit
+ signal tx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0);
+ -- 64 bit
+ signal rx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0);
+ -- 8 bit
+ signal tx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0);
+ -- 8 bit
+ signal rx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0);
-- transceiver reset controller
signal tx_analogreset_arr : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '1');
@@ -160,8 +175,10 @@ begin
rx_is_lockedtoref => OPEN,
rx_is_lockedtodata => rx_is_lockedtodata_arr(I downto I),
- tx_coreclkin => tr_coreclkin, -- 156.25 MHz
- rx_coreclkin => tr_coreclkin, -- 156.25 MHz
+ -- 156.25 MHz
+ tx_coreclkin => tr_coreclkin,
+ -- 156.25 MHz
+ rx_coreclkin => tr_coreclkin,
tx_parallel_data => tx_parallel_data_arr(I),
rx_parallel_data => rx_parallel_data_arr(I),
@@ -198,7 +215,8 @@ begin
tx_digitalreset => tx_digitalreset_arr(I downto I),
tx_ready => xgmii_tx_ready_arr(I downto I),
pll_locked => atx_pll_locked_arr(I downto I),
- pll_select => "0", -- set to zero when using one PLL
+ -- set to zero when using one PLL
+ pll_select => "0",
tx_cal_busy => cal_busy_arr(I downto I),
rx_analogreset => rx_analogreset_arr(I downto I),
rx_digitalreset => rx_digitalreset_arr(I downto I),
@@ -223,28 +241,45 @@ begin
u_ip_arria10_e1sg_phy_10gbase_r_3 : ip_arria10_e1sg_phy_10gbase_r_3
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -273,20 +308,34 @@ begin
u_ip_arria10_e1sg_transceiver_reset_controller_3 : ip_arria10_e1sg_transceiver_reset_controller_3
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
@@ -304,28 +353,45 @@ begin
u_ip_arria10_e1sg_phy_10gbase_r_4 : ip_arria10_e1sg_phy_10gbase_r_4
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -354,20 +420,34 @@ begin
u_ip_arria10_e1sg_transceiver_reset_controller_4 : ip_arria10_e1sg_transceiver_reset_controller_4
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
@@ -385,28 +465,45 @@ begin
u_ip_arria10_e1sg_phy_10gbase_r_12 : ip_arria10_e1sg_phy_10gbase_r_12
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -435,20 +532,34 @@ begin
u_ip_arria10_e1sg_transceiver_reset_controller_12 : ip_arria10_e1sg_transceiver_reset_controller_12
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
@@ -466,37 +577,61 @@ begin
u_ip_arria10_e1sg_phy_10gbase_r_24 : ip_arria10_e1sg_phy_10gbase_r_24
port map (
- reconfig_write(0) => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi.wr, -- in std_logic_vector(0 downto 0)
- reconfig_read(0) => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi.rd, -- in std_logic_vector(0 downto 0)
- reconfig_address => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi.address(14 downto 0), -- in std_logic_vector(14 downto 0)
- reconfig_writedata => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi.wrdata(c_word_w - 1 downto 0), -- in std_logic_vector(31 downto 0)
- reconfig_readdata => reg_ip_arria10_e1sg_phy_10gbase_r_24_miso.rddata(c_word_w - 1 downto 0), -- out std_logic_vector(31 downto 0);
- reconfig_waitrequest(0) => reg_ip_arria10_e1sg_phy_10gbase_r_24_miso.waitrequest, -- out std_logic_vector(0 downto 0);
- reconfig_clk(0) => mm_clk, -- in std_logic_vector(0 downto 0)
+ -- in std_logic_vector(0 downto 0)
+ reconfig_write(0) => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi.wr,
+ -- in std_logic_vector(0 downto 0)
+ reconfig_read(0) => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi.rd,
+ -- in std_logic_vector(14 downto 0)
+ reconfig_address => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi.address(14 downto 0),
+ -- in std_logic_vector(31 downto 0)
+ reconfig_writedata => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi.wrdata(c_word_w - 1 downto 0),
+ -- out std_logic_vector(31 downto 0);
+ reconfig_readdata => reg_ip_arria10_e1sg_phy_10gbase_r_24_miso.rddata(c_word_w - 1 downto 0),
+ -- out std_logic_vector(0 downto 0);
+ reconfig_waitrequest(0) => reg_ip_arria10_e1sg_phy_10gbase_r_24_miso.waitrequest,
+ -- in std_logic_vector(0 downto 0)
+ reconfig_clk(0) => mm_clk,
reconfig_reset(0) => mm_rst,
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -525,20 +660,34 @@ begin
u_ip_arria10_e1sg_transceiver_reset_controller_24 : ip_arria10_e1sg_transceiver_reset_controller_24
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
@@ -556,28 +705,45 @@ begin
u_ip_arria10_e1sg_phy_10gbase_r_48 : ip_arria10_e1sg_phy_10gbase_r_48
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -606,27 +772,42 @@ begin
u_ip_arria10_e1sg_transceiver_reset_controller_48 : ip_arria10_e1sg_transceiver_reset_controller_48
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
-- ATX PLL
u_ip_arria10_e1sg_transceiver_pll_10g : ip_arria10_e1sg_transceiver_pll_10g
port map (
- pll_powerdown => atx_pll_powerdown_arr(0), -- only use reset controller 0 for ATX PLL power down, leave others not used
+ -- only use reset controller 0 for ATX PLL power down, leave others not used
+ pll_powerdown => atx_pll_powerdown_arr(0),
pll_refclk0 => tr_ref_clk_644,
pll_locked => atx_pll_locked,
pll_cal_busy => atx_pll_cal_busy,
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
index 2b3c08f784ffb676f6e66d4392cef61e9bcb4224..6c9aca7dcaf4dda1007f877f2cf9b24f307d8364 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
@@ -55,17 +55,23 @@ entity tech_10gbase_r_arria10_e2sg is
reg_ip_arria10_e2sg_phy_10gbase_r_24_miso : out t_mem_miso;
-- Transceiver ATX PLL reference clock
- tr_ref_clk_644 : in std_logic; -- 644.531250 MHz
+ -- 644.531250 MHz
+ tr_ref_clk_644 : in std_logic;
-- XGMII clocks
- clk_156 : in std_logic; -- 156.25 MHz
+ -- 156.25 MHz
+ clk_156 : in std_logic;
rst_156 : in std_logic;
-- XGMII interface
- xgmii_tx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0); -- can be used for xon flow control
- xgmii_rx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0); -- typically leave not connected
- xgmii_tx_dc_arr : in t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
- xgmii_rx_dc_arr : out t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
+ -- can be used for xon flow control
+ xgmii_tx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
+ -- typically leave not connected
+ xgmii_rx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ xgmii_tx_dc_arr : in t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ xgmii_rx_dc_arr : out t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
-- PHY serial IO
tx_serial_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
@@ -80,7 +86,8 @@ architecture str of tech_10gbase_r_arria10_e2sg is
--CONSTANT c_nof_channels_per_ip : NATURAL := 24 WHEN g_nof_channels=24 ELSE 12 WHEN g_nof_channels=12 ELSE 1;
constant c_nof_channels_per_ip : natural := g_nof_channels;
- constant IP_SIZE : natural := c_nof_channels_per_ip; -- short constant name alias to improve index readability
+ -- short constant name alias to improve index readability
+ constant IP_SIZE : natural := c_nof_channels_per_ip;
constant IP_SIZE_DATA : natural := IP_SIZE * c_xgmii_data_w;
constant IP_SIZE_CONTROL : natural := IP_SIZE * c_xgmii_nof_lanes;
@@ -88,18 +95,26 @@ architecture str of tech_10gbase_r_arria10_e2sg is
signal tr_coreclkin : std_logic_vector(0 downto 0);
- signal tx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0); -- 64 bit
- signal rx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0); -- 64 bit
- signal tx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0); -- 8 bit
- signal rx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0); -- 8 bit
+ -- 64 bit
+ signal tx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0);
+ -- 64 bit
+ signal rx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0);
+ -- 8 bit
+ signal tx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0);
+ -- 8 bit
+ signal rx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0);
-- IP block SLV signals
signal tx_serial_clk_slv : std_logic_vector(g_nof_channels - 1 downto 0);
signal tr_coreclkin_slv : std_logic_vector(g_nof_channels - 1 downto 0);
- signal tx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0); -- 64 bit
- signal rx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0); -- 64 bit
- signal tx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0); -- 8 bit
- signal rx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0); -- 8 bit
+ -- 64 bit
+ signal tx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0);
+ -- 64 bit
+ signal rx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0);
+ -- 8 bit
+ signal tx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0);
+ -- 8 bit
+ signal rx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0);
-- transceiver reset controller
signal tx_analogreset_arr : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '1');
@@ -160,8 +175,10 @@ begin
rx_is_lockedtoref => OPEN,
rx_is_lockedtodata => rx_is_lockedtodata_arr(I downto I),
- tx_coreclkin => tr_coreclkin, -- 156.25 MHz
- rx_coreclkin => tr_coreclkin, -- 156.25 MHz
+ -- 156.25 MHz
+ tx_coreclkin => tr_coreclkin,
+ -- 156.25 MHz
+ rx_coreclkin => tr_coreclkin,
tx_parallel_data => tx_parallel_data_arr(I),
rx_parallel_data => rx_parallel_data_arr(I),
@@ -198,7 +215,8 @@ begin
tx_digitalreset => tx_digitalreset_arr(I downto I),
tx_ready => xgmii_tx_ready_arr(I downto I),
pll_locked => atx_pll_locked_arr(I downto I),
- pll_select => "0", -- set to zero when using one PLL
+ -- set to zero when using one PLL
+ pll_select => "0",
tx_cal_busy => cal_busy_arr(I downto I),
rx_analogreset => rx_analogreset_arr(I downto I),
rx_digitalreset => rx_digitalreset_arr(I downto I),
@@ -223,28 +241,45 @@ begin
u_ip_arria10_e2sg_phy_10gbase_r_3 : ip_arria10_e2sg_phy_10gbase_r_3
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -273,20 +308,34 @@ begin
u_ip_arria10_e2sg_transceiver_reset_controller_3 : ip_arria10_e2sg_transceiver_reset_controller_3
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
@@ -304,28 +353,45 @@ begin
u_ip_arria10_e2sg_phy_10gbase_r_4 : ip_arria10_e2sg_phy_10gbase_r_4
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -354,20 +420,34 @@ begin
u_ip_arria10_e2sg_transceiver_reset_controller_4 : ip_arria10_e2sg_transceiver_reset_controller_4
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
@@ -385,28 +465,45 @@ begin
u_ip_arria10_e2sg_phy_10gbase_r_12 : ip_arria10_e2sg_phy_10gbase_r_12
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -435,20 +532,34 @@ begin
u_ip_arria10_e2sg_transceiver_reset_controller_12 : ip_arria10_e2sg_transceiver_reset_controller_12
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
@@ -466,37 +577,61 @@ begin
u_ip_arria10_e2sg_phy_10gbase_r_24 : ip_arria10_e2sg_phy_10gbase_r_24
port map (
- reconfig_write(0) => reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi.wr, -- in std_logic_vector(0 downto 0)
- reconfig_read(0) => reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi.rd, -- in std_logic_vector(0 downto 0)
- reconfig_address => reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi.address(14 downto 0), -- in std_logic_vector(14 downto 0)
- reconfig_writedata => reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi.wrdata(c_word_w - 1 downto 0), -- in std_logic_vector(31 downto 0)
- reconfig_readdata => reg_ip_arria10_e2sg_phy_10gbase_r_24_miso.rddata(c_word_w - 1 downto 0), -- out std_logic_vector(31 downto 0);
- reconfig_waitrequest(0) => reg_ip_arria10_e2sg_phy_10gbase_r_24_miso.waitrequest, -- out std_logic_vector(0 downto 0);
- reconfig_clk(0) => mm_clk, -- in std_logic_vector(0 downto 0)
+ -- in std_logic_vector(0 downto 0)
+ reconfig_write(0) => reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi.wr,
+ -- in std_logic_vector(0 downto 0)
+ reconfig_read(0) => reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi.rd,
+ -- in std_logic_vector(14 downto 0)
+ reconfig_address => reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi.address(14 downto 0),
+ -- in std_logic_vector(31 downto 0)
+ reconfig_writedata => reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi.wrdata(c_word_w - 1 downto 0),
+ -- out std_logic_vector(31 downto 0);
+ reconfig_readdata => reg_ip_arria10_e2sg_phy_10gbase_r_24_miso.rddata(c_word_w - 1 downto 0),
+ -- out std_logic_vector(0 downto 0);
+ reconfig_waitrequest(0) => reg_ip_arria10_e2sg_phy_10gbase_r_24_miso.waitrequest,
+ -- in std_logic_vector(0 downto 0)
+ reconfig_clk(0) => mm_clk,
reconfig_reset(0) => mm_rst,
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -525,20 +660,34 @@ begin
u_ip_arria10_e2sg_transceiver_reset_controller_24 : ip_arria10_e2sg_transceiver_reset_controller_24
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
@@ -556,28 +705,45 @@ begin
u_ip_arria10_e2sg_phy_10gbase_r_48 : ip_arria10_e2sg_phy_10gbase_r_48
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -606,27 +772,42 @@ begin
u_ip_arria10_e2sg_transceiver_reset_controller_48 : ip_arria10_e2sg_transceiver_reset_controller_48
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
-- ATX PLL
u_ip_arria10_e2sg_transceiver_pll_10g : ip_arria10_e2sg_transceiver_pll_10g
port map (
- pll_powerdown => atx_pll_powerdown_arr(0), -- only use reset controller 0 for ATX PLL power down, leave others not used
+ -- only use reset controller 0 for ATX PLL power down, leave others not used
+ pll_powerdown => atx_pll_powerdown_arr(0),
pll_refclk0 => tr_ref_clk_644,
pll_locked => atx_pll_locked,
pll_cal_busy => atx_pll_cal_busy,
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e3sge3.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e3sge3.vhd
index 6881254db1d2fecacccb4b246ad305ac09155046..e473c318ac954621dd9c91b4dfe366f06147ba24 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e3sge3.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e3sge3.vhd
@@ -54,17 +54,23 @@ entity tech_10gbase_r_arria10_e3sge3 is
reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso : out t_mem_miso;
-- Transceiver ATX PLL reference clock
- tr_ref_clk_644 : in std_logic; -- 644.531250 MHz
+ -- 644.531250 MHz
+ tr_ref_clk_644 : in std_logic;
-- XGMII clocksi
- clk_156 : in std_logic; -- 156.25 MHz
+ -- 156.25 MHz
+ clk_156 : in std_logic;
rst_156 : in std_logic;
-- XGMII interface
- xgmii_tx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0); -- can be used for xon flow control
- xgmii_rx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0); -- typically leave not connected
- xgmii_tx_dc_arr : in t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
- xgmii_rx_dc_arr : out t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
+ -- can be used for xon flow control
+ xgmii_tx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
+ -- typically leave not connected
+ xgmii_rx_ready_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ xgmii_tx_dc_arr : in t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ xgmii_rx_dc_arr : out t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
-- PHY serial IO
tx_serial_arr : out std_logic_vector(g_nof_channels - 1 downto 0);
@@ -79,7 +85,8 @@ architecture str of tech_10gbase_r_arria10_e3sge3 is
--CONSTANT c_nof_channels_per_ip : NATURAL := 24 WHEN g_nof_channels=24 ELSE 12 WHEN g_nof_channels=12 ELSE 1;
constant c_nof_channels_per_ip : natural := g_nof_channels;
- constant IP_SIZE : natural := c_nof_channels_per_ip; -- short constant name alias to improve index readability
+ -- short constant name alias to improve index readability
+ constant IP_SIZE : natural := c_nof_channels_per_ip;
constant IP_SIZE_DATA : natural := IP_SIZE * c_xgmii_data_w;
constant IP_SIZE_CONTROL : natural := IP_SIZE * c_xgmii_nof_lanes;
@@ -87,18 +94,26 @@ architecture str of tech_10gbase_r_arria10_e3sge3 is
signal tr_coreclkin : std_logic_vector(0 downto 0);
- signal tx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0); -- 64 bit
- signal rx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0); -- 64 bit
- signal tx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0); -- 8 bit
- signal rx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0); -- 8 bit
+ -- 64 bit
+ signal tx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0);
+ -- 64 bit
+ signal rx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0);
+ -- 8 bit
+ signal tx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0);
+ -- 8 bit
+ signal rx_control_arr : t_xgmii_c_arr(g_nof_channels - 1 downto 0);
-- IP block SLV signals
signal tx_serial_clk_slv : std_logic_vector(g_nof_channels - 1 downto 0);
signal tr_coreclkin_slv : std_logic_vector(g_nof_channels - 1 downto 0);
- signal tx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0); -- 64 bit
- signal rx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0); -- 64 bit
- signal tx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0); -- 8 bit
- signal rx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0); -- 8 bit
+ -- 64 bit
+ signal tx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0);
+ -- 64 bit
+ signal rx_parallel_data_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_data_w - 1 downto 0);
+ -- 8 bit
+ signal tx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0);
+ -- 8 bit
+ signal rx_control_arr_slv : std_logic_vector(g_nof_channels * c_xgmii_nof_lanes - 1 downto 0);
-- transceiver reset controller
signal tx_analogreset_arr : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '1');
@@ -159,8 +174,10 @@ begin
rx_is_lockedtoref => OPEN,
rx_is_lockedtodata => rx_is_lockedtodata_arr(I downto I),
- tx_coreclkin => tr_coreclkin, -- 156.25 MHz
- rx_coreclkin => tr_coreclkin, -- 156.25 MHz
+ -- 156.25 MHz
+ tx_coreclkin => tr_coreclkin,
+ -- 156.25 MHz
+ rx_coreclkin => tr_coreclkin,
tx_parallel_data => tx_parallel_data_arr(I),
rx_parallel_data => rx_parallel_data_arr(I),
@@ -197,7 +214,8 @@ begin
tx_digitalreset => tx_digitalreset_arr(I downto I),
tx_ready => xgmii_tx_ready_arr(I downto I),
pll_locked => atx_pll_locked_arr(I downto I),
- pll_select => "0", -- set to zero when using one PLL
+ -- set to zero when using one PLL
+ pll_select => "0",
tx_cal_busy => cal_busy_arr(I downto I),
rx_analogreset => rx_analogreset_arr(I downto I),
rx_digitalreset => rx_digitalreset_arr(I downto I),
@@ -222,28 +240,45 @@ begin
u_ip_arria10_e3sge3_phy_10gbase_r_4 : ip_arria10_e3sge3_phy_10gbase_r_4
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -272,20 +307,34 @@ begin
u_ip_arria10_e3sge3_transceiver_reset_controller_4 : ip_arria10_e3sge3_transceiver_reset_controller_4
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
@@ -303,28 +352,45 @@ begin
u_ip_arria10_e3sge3_phy_10gbase_r_12 : ip_arria10_e3sge3_phy_10gbase_r_12
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -353,20 +419,34 @@ begin
u_ip_arria10_e3sge3_transceiver_reset_controller_12 : ip_arria10_e3sge3_transceiver_reset_controller_12
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
@@ -384,37 +464,62 @@ begin
u_ip_arria10_e3sge3_phy_10gbase_r_24 : ip_arria10_e3sge3_phy_10gbase_r_24
port map (
- reconfig_write(0) => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi.wr, -- in std_logic_vector(0 downto 0)
- reconfig_read(0) => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi.rd, -- in std_logic_vector(0 downto 0)
- reconfig_address => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi.address(14 downto 0), -- in std_logic_vector(14 downto 0)
- reconfig_writedata => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi.wrdata(c_word_w - 1 downto 0), -- in std_logic_vector(31 downto 0)
- reconfig_readdata => reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso.rddata(c_word_w - 1 downto 0), -- out std_logic_vector(31 downto 0);
- reconfig_waitrequest(0) => reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso.waitrequest, -- out std_logic_vector(0 downto 0);
- reconfig_clk(0) => mm_clk, -- in std_logic_vector(0 downto 0)
- reconfig_reset(0) => mm_rst, -- in std_logic_vector(0 downto 0)
-
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(0 downto 0)
+ reconfig_write(0) => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi.wr,
+ -- in std_logic_vector(0 downto 0)
+ reconfig_read(0) => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi.rd,
+ -- in std_logic_vector(14 downto 0)
+ reconfig_address => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi.address(14 downto 0),
+ -- in std_logic_vector(31 downto 0)
+ reconfig_writedata => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi.wrdata(c_word_w - 1 downto 0),
+ -- out std_logic_vector(31 downto 0);
+ reconfig_readdata => reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso.rddata(c_word_w - 1 downto 0),
+ -- out std_logic_vector(0 downto 0);
+ reconfig_waitrequest(0) => reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso.waitrequest,
+ -- in std_logic_vector(0 downto 0)
+ reconfig_clk(0) => mm_clk,
+ -- in std_logic_vector(0 downto 0)
+ reconfig_reset(0) => mm_rst,
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -443,20 +548,34 @@ begin
u_ip_arria10_e3sge3_transceiver_reset_controller_24 : ip_arria10_e3sge3_transceiver_reset_controller_24
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
@@ -474,28 +593,45 @@ begin
u_ip_arria10_e3sge3_phy_10gbase_r_48 : ip_arria10_e3sge3_phy_10gbase_r_48
port map (
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-
- tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 downto 0),
+ -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 downto 0),
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-
- tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-
- tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+ -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 downto 0),
+
+ -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA - 1 downto 0),
+ -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0),
+ -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL - 1 downto 0)
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
@@ -524,27 +660,42 @@ begin
u_ip_arria10_e3sge3_transceiver_reset_controller_48 : ip_arria10_e3sge3_transceiver_reset_controller_48
port map (
- clock => clk_156, -- : in std_logic := '0'; -- clock.clk
- pll_locked => atx_pll_locked_arr(0 downto 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown => atx_pll_powerdown_arr(0 downto 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset => rst_156, -- : in std_logic := '0'; -- reset.reset
- rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- : in std_logic := '0'; -- clock.clk
+ clock => clk_156,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_locked => atx_pll_locked_arr(0 downto 0),
+ -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_powerdown => atx_pll_powerdown_arr(0 downto 0),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ pll_select => "0",
+ -- : in std_logic := '0'; -- reset.reset
+ reset => rst_156,
+ -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 downto 0),
+ -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 downto 0),
+ -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 downto 0)
);
end generate;
-- ATX PLL
u_ip_arria10_e3sge3_transceiver_pll_10g : ip_arria10_e3sge3_transceiver_pll_10g
port map (
- pll_powerdown => atx_pll_powerdown_arr(0), -- only use reset controller 0 for ATX PLL power down, leave others not used
+ -- only use reset controller 0 for ATX PLL power down, leave others not used
+ pll_powerdown => atx_pll_powerdown_arr(0),
pll_refclk0 => tr_ref_clk_644,
pll_locked => atx_pll_locked,
pll_cal_busy => atx_pll_cal_busy,
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
index a8c8d20b50041cc02ac6832370421b749e0361bb..035274f3c6d7cc5fd2da2d0e10cb58d015091f35 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
@@ -31,280 +31,529 @@ package tech_10gbase_r_component_pkg is
component ip_arria10_phy_10gbase_r is
port (
- tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
- tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_coreclkin.clk
- tx_clkout : out std_logic_vector(0 downto 0); -- tx_clkout.clk
- rx_clkout : out std_logic_vector(0 downto 0); -- rx_clkout.clk
- tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data : out std_logic_vector(63 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_pma_div_clkout : out std_logic_vector(0 downto 0); -- tx_pma_div_clkout.clk
- tx_control : in std_logic_vector(7 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins
- unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- unused_tx_parallel_data.unused_tx_parallel_data
- unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- rx_control : out std_logic_vector(7 downto 0); -- rx_control.rx_control
- unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control
- tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_enh_blk_lock : out std_logic_vector(0 downto 0) -- rx_enh_blk_lock.rx_enh_blk_lock
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(0 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(0 downto 0);
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(0 downto 0);
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(0 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(0 downto 0);
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(0 downto 0);
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(0 downto 0);
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0');
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(63 downto 0);
+ -- tx_pma_div_clkout.clk
+ tx_pma_div_clkout : out std_logic_vector(0 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(7 downto 0) := (others => '0');
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic := '0';
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0');
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0');
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(7 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(63 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(11 downto 0);
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(0 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(0 downto 0);
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(0 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(0 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(0 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(0 downto 0);
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(0 downto 0)
);
end component;
component ip_arria10_phy_10gbase_r_4
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(11 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(3 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(3 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(31 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(3 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(3 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(3 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(3 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(3 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(3 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(3 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(255 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(3 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(3 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(3 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(3 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(31 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(3 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(3 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(3 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(3 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(3 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(47 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(255 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(35 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(3 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(3 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(31 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(3 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(3 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(3 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(3 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(3 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(255 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(3 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(3 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(3 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(3 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(31 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(3 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(3 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(3 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(3 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(3 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(47 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(255 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(35 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0')
);
end component;
component ip_arria10_phy_10gbase_r_12
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(13 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(95 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(767 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(11 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(11 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(95 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(143 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(767 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(107 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(13 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(11 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(11 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(95 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(11 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(11 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(11 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(11 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(11 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(767 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(11 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(11 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(11 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(11 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(95 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(11 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(11 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(11 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(11 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(11 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(143 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(767 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(107 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0')
);
end component;
component ip_arria10_phy_10gbase_r_24
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(14 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(23 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(191 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(23 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(23 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(23 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(23 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(23 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(23 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(23 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(23 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(23 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(23 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(14 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(23 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(23 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(191 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(23 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(23 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(23 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(23 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(23 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(1535 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(23 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(23 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(23 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(23 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(191 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(23 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(23 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(23 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(23 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(23 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(287 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(1535 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0')
);
end component;
component ip_arria10_phy_10gbase_r_48
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(15 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(47 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(47 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(383 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(47 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(47 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(47 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(47 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(47 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(47 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(47 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(47 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(47 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(3071 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(47 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(47 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(47 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(47 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(383 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(47 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(47 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(47 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(47 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(47 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(575 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(3071 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(431 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(15 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(47 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(47 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(383 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(47 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(47 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(47 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(47 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(47 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(3071 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(47 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(47 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(47 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(47 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(383 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(47 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(47 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(47 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(47 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(47 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(575 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(3071 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(431 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0')
);
end component;
component ip_arria10_transceiver_pll_10g is
port (
- mcgb_rst : in std_logic := '0'; -- mcgb_rst.mcgb_rst
- mcgb_serial_clk : out std_logic; -- mcgb_serial_clk.clk
- pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
- pll_locked : out std_logic; -- pll_locked.pll_locked
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
- pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
- reconfig_write0 : in std_logic := '0'; -- reconfig_avmm0.write
- reconfig_read0 : in std_logic := '0'; -- .read
- reconfig_address0 : in std_logic_vector(9 downto 0) := (others => '0'); -- .address
- reconfig_writedata0 : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata0 : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest0 : out std_logic; -- .waitrequest
- reconfig_clk0 : in std_logic := '0'; -- reconfig_clk0.clk
- reconfig_reset0 : in std_logic := '0'; -- reconfig_reset0.reset
- tx_serial_clk : out std_logic -- tx_serial_clk.clk
+ -- mcgb_rst.mcgb_rst
+ mcgb_rst : in std_logic := '0';
+ -- mcgb_serial_clk.clk
+ mcgb_serial_clk : out std_logic;
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy : out std_logic;
+ -- pll_locked.pll_locked
+ pll_locked : out std_logic;
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : in std_logic := '0';
+ -- pll_refclk0.clk
+ pll_refclk0 : in std_logic := '0';
+ -- reconfig_avmm0.write
+ reconfig_write0 : in std_logic := '0';
+ -- .read
+ reconfig_read0 : in std_logic := '0';
+ -- .address
+ reconfig_address0 : in std_logic_vector(9 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata0 : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata0 : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest0 : out std_logic;
+ -- reconfig_clk0.clk
+ reconfig_clk0 : in std_logic := '0';
+ -- reconfig_reset0.reset
+ reconfig_reset0 : in std_logic := '0';
+ -- tx_serial_clk.clk
+ tx_serial_clk : out std_logic
-- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
-- pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
-- pll_locked : out std_logic; -- pll_locked.pll_locked
@@ -316,96 +565,166 @@ package tech_10gbase_r_component_pkg is
component ip_arria10_transceiver_reset_controller_1 is
port (
- clock : in std_logic := '0'; -- clock.clk
- reset : in std_logic := '0'; -- reset.reset
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- tx_analogreset : out std_logic_vector(0 downto 0); -- tx_analogreset.tx_analogreset
- tx_digitalreset : out std_logic_vector(0 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(0 downto 0); -- tx_ready.tx_ready
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- tx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset.rx_analogreset
- rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_ready : out std_logic_vector(0 downto 0); -- rx_ready.rx_ready
- rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0') -- rx_cal_busy.rx_cal_busy
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(0 downto 0);
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(0 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(0 downto 0);
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(0 downto 0);
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(0 downto 0);
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(0 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0')
);
end component;
component ip_arria10_transceiver_reset_controller_4
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(3 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(3 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(3 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(3 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(3 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(3 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(3 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(3 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(3 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(3 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(3 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(3 downto 0)
);
end component;
component ip_arria10_transceiver_reset_controller_12
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(11 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(11 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(11 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(11 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(11 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(11 downto 0)
);
end component;
component ip_arria10_transceiver_reset_controller_24
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(23 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(23 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(23 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(23 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(23 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(23 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(23 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(23 downto 0)
);
end component;
component ip_arria10_transceiver_reset_controller_48
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(47 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(47 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(47 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(47 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(47 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(47 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(47 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(47 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(47 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(47 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(47 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(47 downto 0)
);
end component;
@@ -415,280 +734,529 @@ package tech_10gbase_r_component_pkg is
component ip_arria10_e3sge3_phy_10gbase_r is
port (
- tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
- tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data.tx_serial_data
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_coreclkin.clk
- rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_coreclkin.clk
- tx_clkout : out std_logic_vector(0 downto 0); -- tx_clkout.clk
- rx_clkout : out std_logic_vector(0 downto 0); -- rx_clkout.clk
- tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- rx_parallel_data : out std_logic_vector(63 downto 0); -- rx_parallel_data.rx_parallel_data
- tx_pma_div_clkout : out std_logic_vector(0 downto 0); -- tx_pma_div_clkout.clk
- tx_control : in std_logic_vector(7 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins
- unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- unused_tx_parallel_data.unused_tx_parallel_data
- unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- rx_control : out std_logic_vector(7 downto 0); -- rx_control.rx_control
- unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control
- tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_enh_blk_lock : out std_logic_vector(0 downto 0) -- rx_enh_blk_lock.rx_enh_blk_lock
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(0 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(0 downto 0);
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(0 downto 0);
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(0 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(0 downto 0);
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(0 downto 0);
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(0 downto 0);
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0');
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(63 downto 0);
+ -- tx_pma_div_clkout.clk
+ tx_pma_div_clkout : out std_logic_vector(0 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(7 downto 0) := (others => '0');
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic := '0';
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0');
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0');
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(7 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(63 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(11 downto 0);
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(0 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(0 downto 0);
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(0 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(0 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(0 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(0 downto 0);
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(0 downto 0)
);
end component;
component ip_arria10_e3sge3_phy_10gbase_r_4
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(11 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(3 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(3 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(31 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(3 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(3 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(3 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(3 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(3 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(3 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(3 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(255 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(3 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(3 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(3 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(3 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(31 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(3 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(3 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(3 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(3 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(3 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(47 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(255 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(35 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(3 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(3 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(31 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(3 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(3 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(3 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(3 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(3 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(255 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(3 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(3 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(3 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(3 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(31 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(3 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(3 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(3 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(3 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(3 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(47 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(255 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(35 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0')
);
end component;
component ip_arria10_e3sge3_phy_10gbase_r_12
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(13 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(95 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(767 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(11 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(11 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(95 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(143 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(767 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(107 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(13 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(11 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(11 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(95 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(11 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(11 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(11 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(11 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(11 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(767 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(11 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(11 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(11 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(11 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(95 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(11 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(11 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(11 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(11 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(11 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(143 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(767 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(107 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0')
);
end component;
component ip_arria10_e3sge3_phy_10gbase_r_24
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(14 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(23 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(191 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(23 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(23 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(23 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(23 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(23 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(23 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(23 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(23 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(23 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(23 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(14 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(23 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(23 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(191 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(23 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(23 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(23 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(23 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(23 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(1535 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(23 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(23 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(23 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(23 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(191 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(23 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(23 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(23 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(23 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(23 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(287 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(1535 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0')
);
end component;
component ip_arria10_e3sge3_phy_10gbase_r_48
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(15 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(47 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(47 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(383 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(47 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(47 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(47 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(47 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(47 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(47 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(47 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(47 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(47 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(3071 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(47 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(47 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(47 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(47 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(383 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(47 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(47 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(47 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(47 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(47 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(575 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(3071 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(431 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(15 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(47 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(47 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(383 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(47 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(47 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(47 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(47 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(47 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(3071 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(47 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(47 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(47 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(47 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(383 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(47 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(47 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(47 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(47 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(47 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(575 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(3071 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(431 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0')
);
end component;
component ip_arria10_e3sge3_transceiver_pll_10g is
port (
- mcgb_rst : in std_logic := '0'; -- mcgb_rst.mcgb_rst
- mcgb_serial_clk : out std_logic; -- mcgb_serial_clk.clk
- pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
- pll_locked : out std_logic; -- pll_locked.pll_locked
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
- pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
- reconfig_write0 : in std_logic := '0'; -- reconfig_avmm0.write
- reconfig_read0 : in std_logic := '0'; -- .read
- reconfig_address0 : in std_logic_vector(9 downto 0) := (others => '0'); -- .address
- reconfig_writedata0 : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata0 : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest0 : out std_logic; -- .waitrequest
- reconfig_clk0 : in std_logic := '0'; -- reconfig_clk0.clk
- reconfig_reset0 : in std_logic := '0'; -- reconfig_reset0.reset
- tx_serial_clk : out std_logic -- tx_serial_clk.clk
+ -- mcgb_rst.mcgb_rst
+ mcgb_rst : in std_logic := '0';
+ -- mcgb_serial_clk.clk
+ mcgb_serial_clk : out std_logic;
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy : out std_logic;
+ -- pll_locked.pll_locked
+ pll_locked : out std_logic;
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : in std_logic := '0';
+ -- pll_refclk0.clk
+ pll_refclk0 : in std_logic := '0';
+ -- reconfig_avmm0.write
+ reconfig_write0 : in std_logic := '0';
+ -- .read
+ reconfig_read0 : in std_logic := '0';
+ -- .address
+ reconfig_address0 : in std_logic_vector(9 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata0 : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata0 : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest0 : out std_logic;
+ -- reconfig_clk0.clk
+ reconfig_clk0 : in std_logic := '0';
+ -- reconfig_reset0.reset
+ reconfig_reset0 : in std_logic := '0';
+ -- tx_serial_clk.clk
+ tx_serial_clk : out std_logic
-- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
-- pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
-- pll_locked : out std_logic; -- pll_locked.pll_locked
@@ -700,96 +1268,166 @@ package tech_10gbase_r_component_pkg is
component ip_arria10_e3sge3_transceiver_reset_controller_1 is
port (
- clock : in std_logic := '0'; -- clock.clk
- reset : in std_logic := '0'; -- reset.reset
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- tx_analogreset : out std_logic_vector(0 downto 0); -- tx_analogreset.tx_analogreset
- tx_digitalreset : out std_logic_vector(0 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(0 downto 0); -- tx_ready.tx_ready
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- tx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset.rx_analogreset
- rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_ready : out std_logic_vector(0 downto 0); -- rx_ready.rx_ready
- rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0') -- rx_cal_busy.rx_cal_busy
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(0 downto 0);
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(0 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(0 downto 0);
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(0 downto 0);
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(0 downto 0);
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(0 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0')
);
end component;
component ip_arria10_e3sge3_transceiver_reset_controller_4
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(3 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(3 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(3 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(3 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(3 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(3 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(3 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(3 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(3 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(3 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(3 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(3 downto 0)
);
end component;
component ip_arria10_e3sge3_transceiver_reset_controller_12
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(11 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(11 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(11 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(11 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(11 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(11 downto 0)
);
end component;
component ip_arria10_e3sge3_transceiver_reset_controller_24
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(23 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(23 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(23 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(23 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(23 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(23 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(23 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(23 downto 0)
);
end component;
component ip_arria10_e3sge3_transceiver_reset_controller_48
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(47 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(47 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(47 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(47 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(47 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(47 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(47 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(47 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(47 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(47 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(47 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(47 downto 0)
);
end component;
@@ -799,337 +1437,638 @@ package tech_10gbase_r_component_pkg is
component ip_arria10_e1sg_phy_10gbase_r is
port (
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(0 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(7 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(0 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(63 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(0 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(0 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(0 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(7 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(0 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(0 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(7 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(0 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(0 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(0 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(0 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(0 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(63 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(0 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(0 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(0 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(0 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(7 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(0 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(0 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(0 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(0 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic := '0';
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(0 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(11 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(63 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0')
);
end component;
component ip_arria10_e1sg_phy_10gbase_r_3 is
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- read
- reconfig_address : in std_logic_vector(11 downto 0) := (others => '0'); -- address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reset
- rx_analogreset : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(2 downto 0); -- rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- clk
- rx_clkout : out std_logic_vector(2 downto 0); -- clk
- rx_control : out std_logic_vector(23 downto 0); -- rx_control
- rx_coreclkin : in std_logic_vector(2 downto 0) := (others => '0'); -- clk
- rx_digitalreset : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(2 downto 0); -- rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(2 downto 0); -- rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(2 downto 0); -- rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(2 downto 0); -- rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(2 downto 0); -- rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(2 downto 0); -- rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(2 downto 0); -- rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(2 downto 0); -- rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(2 downto 0); -- rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(191 downto 0); -- rx_parallel_data
- rx_prbs_done : out std_logic_vector(2 downto 0); -- rx_prbs_done
- rx_prbs_err : out std_logic_vector(2 downto 0); -- rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_serial_data
- rx_seriallpbken : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_seriallpbken
- tx_analogreset : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_analogreset
- tx_cal_busy : out std_logic_vector(2 downto 0); -- tx_cal_busy
- tx_clkout : out std_logic_vector(2 downto 0); -- clk
- tx_control : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_control
- tx_coreclkin : in std_logic_vector(2 downto 0) := (others => '0'); -- clk
- tx_digitalreset : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(2 downto 0); -- tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(2 downto 0); -- tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(2 downto 0); -- tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(2 downto 0); -- tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_err_ins
- tx_parallel_data : in std_logic_vector(191 downto 0) := (others => '0'); -- tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(2 downto 0) := (others => '0'); -- clk
- tx_serial_data : out std_logic_vector(2 downto 0); -- tx_serial_data
- unused_rx_control : out std_logic_vector(35 downto 0); -- unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(191 downto 0); -- unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(26 downto 0) := (others => '0'); -- unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(191 downto 0) := (others => '0') -- unused_tx_parallel_data
+ -- write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- address
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => '0');
+ -- writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset
+ rx_analogreset : in std_logic_vector(2 downto 0) := (others => '0');
+ -- rx_cal_busy
+ rx_cal_busy : out std_logic_vector(2 downto 0);
+ -- clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- clk
+ rx_clkout : out std_logic_vector(2 downto 0);
+ -- rx_control
+ rx_control : out std_logic_vector(23 downto 0);
+ -- clk
+ rx_coreclkin : in std_logic_vector(2 downto 0) := (others => '0');
+ -- rx_digitalreset
+ rx_digitalreset : in std_logic_vector(2 downto 0) := (others => '0');
+ -- rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(2 downto 0);
+ -- rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(2 downto 0);
+ -- rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(2 downto 0);
+ -- rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(2 downto 0);
+ -- rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(2 downto 0);
+ -- rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(2 downto 0);
+ -- rx_enh_highber
+ rx_enh_highber : out std_logic_vector(2 downto 0);
+ -- rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(2 downto 0);
+ -- rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(2 downto 0);
+ -- rx_parallel_data
+ rx_parallel_data : out std_logic_vector(191 downto 0);
+ -- rx_prbs_done
+ rx_prbs_done : out std_logic_vector(2 downto 0);
+ -- rx_prbs_err
+ rx_prbs_err : out std_logic_vector(2 downto 0);
+ -- rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(2 downto 0) := (others => '0');
+ -- rx_serial_data
+ rx_serial_data : in std_logic_vector(2 downto 0) := (others => '0');
+ -- rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_analogreset
+ tx_analogreset : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_cal_busy
+ tx_cal_busy : out std_logic_vector(2 downto 0);
+ -- clk
+ tx_clkout : out std_logic_vector(2 downto 0);
+ -- tx_control
+ tx_control : in std_logic_vector(23 downto 0) := (others => '0');
+ -- clk
+ tx_coreclkin : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_digitalreset
+ tx_digitalreset : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(2 downto 0);
+ -- tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(2 downto 0);
+ -- tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(2 downto 0);
+ -- tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(2 downto 0);
+ -- tx_err_ins
+ tx_err_ins : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_parallel_data
+ tx_parallel_data : in std_logic_vector(191 downto 0) := (others => '0');
+ -- clk
+ tx_serial_clk0 : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_serial_data
+ tx_serial_data : out std_logic_vector(2 downto 0);
+ -- unused_rx_control
+ unused_rx_control : out std_logic_vector(35 downto 0);
+ -- unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(191 downto 0);
+ -- unused_tx_control
+ unused_tx_control : in std_logic_vector(26 downto 0) := (others => '0');
+ -- unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(191 downto 0) := (others => '0')
);
end component ip_arria10_e1sg_phy_10gbase_r_3;
component ip_arria10_e1sg_phy_10gbase_r_4
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(11 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(3 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(3 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(31 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(3 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(3 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(3 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(3 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(3 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(3 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(3 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(255 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(3 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(3 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(3 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(3 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(31 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(3 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(3 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(3 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(3 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(3 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(47 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(255 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(35 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(3 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(3 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(31 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(3 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(3 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(3 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(3 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(3 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(255 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(3 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(3 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(3 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(3 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(31 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(3 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(3 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(3 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(3 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(3 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(47 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(255 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(35 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0')
);
end component;
component ip_arria10_e1sg_phy_10gbase_r_12
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(13 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(95 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(767 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(11 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(11 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(95 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(143 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(767 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(107 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(13 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(11 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(11 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(95 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(11 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(11 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(11 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(11 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(11 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(767 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(11 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(11 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(11 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(11 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(95 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(11 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(11 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(11 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(11 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(11 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(143 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(767 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(107 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0')
);
end component;
component ip_arria10_e1sg_phy_10gbase_r_24
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(14 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(23 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(191 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(23 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(23 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(23 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(23 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(23 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(23 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(23 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(23 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(23 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(23 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(14 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(23 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(23 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(191 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(23 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(23 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(23 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(23 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(23 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(1535 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(23 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(23 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(23 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(23 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(191 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(23 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(23 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(23 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(23 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(23 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(287 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(1535 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0')
);
end component;
component ip_arria10_e1sg_phy_10gbase_r_48
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(15 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(47 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(47 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(383 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(47 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(47 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(47 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(47 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(47 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(47 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(47 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(47 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(47 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(3071 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(47 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(47 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(47 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(47 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(383 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(47 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(47 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(47 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(47 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(47 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(575 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(3071 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(431 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(15 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(47 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(47 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(383 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(47 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(47 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(47 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(47 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(47 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(3071 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(47 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(47 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(47 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(47 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(383 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(47 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(47 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(47 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(47 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(47 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(575 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(3071 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(431 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0')
);
end component;
component ip_arria10_e1sg_transceiver_pll_10g is
port (
- mcgb_rst : in std_logic := '0'; -- mcgb_rst.mcgb_rst
- mcgb_serial_clk : out std_logic; -- mcgb_serial_clk.clk
- pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
- pll_locked : out std_logic; -- pll_locked.pll_locked
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
- pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
- reconfig_write0 : in std_logic := '0'; -- reconfig_avmm0.write
- reconfig_read0 : in std_logic := '0'; -- .read
- reconfig_address0 : in std_logic_vector(9 downto 0) := (others => '0'); -- .address
- reconfig_writedata0 : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata0 : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest0 : out std_logic; -- .waitrequest
- reconfig_clk0 : in std_logic := '0'; -- reconfig_clk0.clk
- reconfig_reset0 : in std_logic := '0'; -- reconfig_reset0.reset
- tx_serial_clk : out std_logic -- tx_serial_clk.clk
+ -- mcgb_rst.mcgb_rst
+ mcgb_rst : in std_logic := '0';
+ -- mcgb_serial_clk.clk
+ mcgb_serial_clk : out std_logic;
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy : out std_logic;
+ -- pll_locked.pll_locked
+ pll_locked : out std_logic;
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : in std_logic := '0';
+ -- pll_refclk0.clk
+ pll_refclk0 : in std_logic := '0';
+ -- reconfig_avmm0.write
+ reconfig_write0 : in std_logic := '0';
+ -- .read
+ reconfig_read0 : in std_logic := '0';
+ -- .address
+ reconfig_address0 : in std_logic_vector(9 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata0 : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata0 : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest0 : out std_logic;
+ -- reconfig_clk0.clk
+ reconfig_clk0 : in std_logic := '0';
+ -- reconfig_reset0.reset
+ reconfig_reset0 : in std_logic := '0';
+ -- tx_serial_clk.clk
+ tx_serial_clk : out std_logic
-- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
-- pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
-- pll_locked : out std_logic; -- pll_locked.pll_locked
@@ -1141,115 +2080,199 @@ package tech_10gbase_r_component_pkg is
component ip_arria10_e1sg_transceiver_reset_controller_1 is
port (
- clock : in std_logic := '0'; -- clock.clk
- reset : in std_logic := '0'; -- reset.reset
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- tx_analogreset : out std_logic_vector(0 downto 0); -- tx_analogreset.tx_analogreset
- tx_digitalreset : out std_logic_vector(0 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(0 downto 0); -- tx_ready.tx_ready
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- tx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset.rx_analogreset
- rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_ready : out std_logic_vector(0 downto 0); -- rx_ready.rx_ready
- rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0') -- rx_cal_busy.rx_cal_busy
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(0 downto 0);
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(0 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(0 downto 0);
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(0 downto 0);
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(0 downto 0);
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(0 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0')
);
end component;
component ip_arria10_e1sg_transceiver_reset_controller_3 is
port (
- clock : in std_logic := '0'; -- clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select
- reset : in std_logic := '0'; -- reset
- rx_analogreset : out std_logic_vector(2 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_cal_busy
- rx_digitalreset : out std_logic_vector(2 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_is_lockedtodata
- rx_ready : out std_logic_vector(2 downto 0); -- rx_ready
- tx_analogreset : out std_logic_vector(2 downto 0); -- tx_analogreset
- tx_cal_busy : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_cal_busy
- tx_digitalreset : out std_logic_vector(2 downto 0); -- tx_digitalreset
- tx_ready : out std_logic_vector(2 downto 0) -- tx_ready
+ -- clk
+ clock : in std_logic := '0';
+ -- pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset
+ reset : in std_logic := '0';
+ -- rx_analogreset
+ rx_analogreset : out std_logic_vector(2 downto 0);
+ -- rx_cal_busy
+ rx_cal_busy : in std_logic_vector(2 downto 0) := (others => '0');
+ -- rx_digitalreset
+ rx_digitalreset : out std_logic_vector(2 downto 0);
+ -- rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => '0');
+ -- rx_ready
+ rx_ready : out std_logic_vector(2 downto 0);
+ -- tx_analogreset
+ tx_analogreset : out std_logic_vector(2 downto 0);
+ -- tx_cal_busy
+ tx_cal_busy : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_digitalreset
+ tx_digitalreset : out std_logic_vector(2 downto 0);
+ -- tx_ready
+ tx_ready : out std_logic_vector(2 downto 0)
);
end component ip_arria10_e1sg_transceiver_reset_controller_3;
component ip_arria10_e1sg_transceiver_reset_controller_4
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(3 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(3 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(3 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(3 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(3 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(3 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(3 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(3 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(3 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(3 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(3 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(3 downto 0)
);
end component;
component ip_arria10_e1sg_transceiver_reset_controller_12
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(11 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(11 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(11 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(11 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(11 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(11 downto 0)
);
end component;
component ip_arria10_e1sg_transceiver_reset_controller_24
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(23 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(23 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(23 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(23 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(23 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(23 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(23 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(23 downto 0)
);
end component;
component ip_arria10_e1sg_transceiver_reset_controller_48
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(47 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(47 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(47 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(47 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(47 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(47 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(47 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(47 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(47 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(47 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(47 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(47 downto 0)
);
end component;
@@ -1259,337 +2282,638 @@ package tech_10gbase_r_component_pkg is
component ip_arria10_e2sg_phy_10gbase_r is
port (
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(0 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(7 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(0 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(63 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(0 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(0 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(0 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(7 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(0 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(0 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(7 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(0 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(0 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(0 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(0 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(0 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(0 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(63 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(0 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(0 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(0 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(0 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(7 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(0 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(0 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(0 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(0 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic := '0';
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(0 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(11 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(63 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0')
);
end component;
component ip_arria10_e2sg_phy_10gbase_r_3 is
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- read
- reconfig_address : in std_logic_vector(11 downto 0) := (others => '0'); -- address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reset
- rx_analogreset : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(2 downto 0); -- rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- clk
- rx_clkout : out std_logic_vector(2 downto 0); -- clk
- rx_control : out std_logic_vector(23 downto 0); -- rx_control
- rx_coreclkin : in std_logic_vector(2 downto 0) := (others => '0'); -- clk
- rx_digitalreset : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(2 downto 0); -- rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(2 downto 0); -- rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(2 downto 0); -- rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(2 downto 0); -- rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(2 downto 0); -- rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(2 downto 0); -- rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(2 downto 0); -- rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(2 downto 0); -- rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(2 downto 0); -- rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(191 downto 0); -- rx_parallel_data
- rx_prbs_done : out std_logic_vector(2 downto 0); -- rx_prbs_done
- rx_prbs_err : out std_logic_vector(2 downto 0); -- rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_serial_data
- rx_seriallpbken : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_seriallpbken
- tx_analogreset : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_analogreset
- tx_cal_busy : out std_logic_vector(2 downto 0); -- tx_cal_busy
- tx_clkout : out std_logic_vector(2 downto 0); -- clk
- tx_control : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_control
- tx_coreclkin : in std_logic_vector(2 downto 0) := (others => '0'); -- clk
- tx_digitalreset : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(2 downto 0); -- tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(2 downto 0); -- tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(2 downto 0); -- tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(2 downto 0); -- tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_err_ins
- tx_parallel_data : in std_logic_vector(191 downto 0) := (others => '0'); -- tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(2 downto 0) := (others => '0'); -- clk
- tx_serial_data : out std_logic_vector(2 downto 0); -- tx_serial_data
- unused_rx_control : out std_logic_vector(35 downto 0); -- unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(191 downto 0); -- unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(26 downto 0) := (others => '0'); -- unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(191 downto 0) := (others => '0') -- unused_tx_parallel_data
+ -- write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- address
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => '0');
+ -- writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset
+ rx_analogreset : in std_logic_vector(2 downto 0) := (others => '0');
+ -- rx_cal_busy
+ rx_cal_busy : out std_logic_vector(2 downto 0);
+ -- clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- clk
+ rx_clkout : out std_logic_vector(2 downto 0);
+ -- rx_control
+ rx_control : out std_logic_vector(23 downto 0);
+ -- clk
+ rx_coreclkin : in std_logic_vector(2 downto 0) := (others => '0');
+ -- rx_digitalreset
+ rx_digitalreset : in std_logic_vector(2 downto 0) := (others => '0');
+ -- rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(2 downto 0);
+ -- rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(2 downto 0);
+ -- rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(2 downto 0);
+ -- rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(2 downto 0);
+ -- rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(2 downto 0);
+ -- rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(2 downto 0);
+ -- rx_enh_highber
+ rx_enh_highber : out std_logic_vector(2 downto 0);
+ -- rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(2 downto 0);
+ -- rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(2 downto 0);
+ -- rx_parallel_data
+ rx_parallel_data : out std_logic_vector(191 downto 0);
+ -- rx_prbs_done
+ rx_prbs_done : out std_logic_vector(2 downto 0);
+ -- rx_prbs_err
+ rx_prbs_err : out std_logic_vector(2 downto 0);
+ -- rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(2 downto 0) := (others => '0');
+ -- rx_serial_data
+ rx_serial_data : in std_logic_vector(2 downto 0) := (others => '0');
+ -- rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_analogreset
+ tx_analogreset : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_cal_busy
+ tx_cal_busy : out std_logic_vector(2 downto 0);
+ -- clk
+ tx_clkout : out std_logic_vector(2 downto 0);
+ -- tx_control
+ tx_control : in std_logic_vector(23 downto 0) := (others => '0');
+ -- clk
+ tx_coreclkin : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_digitalreset
+ tx_digitalreset : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(2 downto 0);
+ -- tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(2 downto 0);
+ -- tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(2 downto 0);
+ -- tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(2 downto 0);
+ -- tx_err_ins
+ tx_err_ins : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_parallel_data
+ tx_parallel_data : in std_logic_vector(191 downto 0) := (others => '0');
+ -- clk
+ tx_serial_clk0 : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_serial_data
+ tx_serial_data : out std_logic_vector(2 downto 0);
+ -- unused_rx_control
+ unused_rx_control : out std_logic_vector(35 downto 0);
+ -- unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(191 downto 0);
+ -- unused_tx_control
+ unused_tx_control : in std_logic_vector(26 downto 0) := (others => '0');
+ -- unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(191 downto 0) := (others => '0')
);
end component;
component ip_arria10_e2sg_phy_10gbase_r_4
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(11 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(3 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(3 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(31 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(3 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(3 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(3 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(3 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(3 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(3 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(3 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(255 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(3 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(3 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(3 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(3 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(31 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(3 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(3 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(3 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(3 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(3 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(47 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(255 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(35 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(3 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(3 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(31 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(3 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(3 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(3 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(3 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(3 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(3 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(255 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(3 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(3 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(3 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(3 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(31 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(3 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(3 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(3 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(3 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(3 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(47 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(255 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(35 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0')
);
end component;
component ip_arria10_e2sg_phy_10gbase_r_12
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(13 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(95 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(767 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(11 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(11 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(95 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(143 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(767 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(107 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(13 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(11 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(11 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(95 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(11 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(11 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(11 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(11 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(11 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(11 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(767 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(11 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(11 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(11 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(11 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(95 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(11 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(11 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(11 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(11 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(11 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(143 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(767 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(107 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0')
);
end component;
component ip_arria10_e2sg_phy_10gbase_r_24
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(14 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(23 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(191 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(23 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(23 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(23 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(23 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(23 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(23 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(23 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(23 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(23 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(23 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(14 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(23 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(23 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(191 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(23 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(23 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(23 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(23 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(23 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(23 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(1535 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(23 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(23 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(23 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(23 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(191 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(23 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(23 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(23 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(23 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(23 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(287 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(1535 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0')
);
end component;
component ip_arria10_e2sg_phy_10gbase_r_48
port (
- reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
- reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
- reconfig_address : in std_logic_vector(15 downto 0) := (others => '0'); -- .address
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
- rx_analogreset : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(47 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(47 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(383 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(47 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(47 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(47 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(47 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(47 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(47 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(47 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(47 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(47 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(3071 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(47 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(47 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(47 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(47 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(383 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(47 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(47 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(47 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(47 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(47 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(575 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(3071 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(431 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ -- reconfig_avmm.write
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .read
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .address
+ reconfig_address : in std_logic_vector(15 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest : out std_logic_vector(0 downto 0);
+ -- reconfig_clk.clk
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reconfig_reset.reset
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : out std_logic_vector(47 downto 0);
+ -- rx_cdr_refclk0.clk
+ rx_cdr_refclk0 : in std_logic := '0';
+ -- rx_clkout.clk
+ rx_clkout : out std_logic_vector(47 downto 0);
+ -- rx_control.rx_control
+ rx_control : out std_logic_vector(383 downto 0);
+ -- rx_coreclkin.clk
+ rx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_blk_lock : out std_logic_vector(47 downto 0);
+ -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_del : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_empty : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_full : out std_logic_vector(47 downto 0);
+ -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_fifo_insert : out std_logic_vector(47 downto 0);
+ -- rx_enh_highber.rx_enh_highber
+ rx_enh_highber : out std_logic_vector(47 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : out std_logic_vector(47 downto 0);
+ -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref : out std_logic_vector(47 downto 0);
+ -- rx_parallel_data.rx_parallel_data
+ rx_parallel_data : out std_logic_vector(3071 downto 0);
+ -- rx_prbs_done.rx_prbs_done
+ rx_prbs_done : out std_logic_vector(47 downto 0);
+ -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err : out std_logic_vector(47 downto 0);
+ -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_prbs_err_clr : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_serial_data.rx_serial_data
+ rx_serial_data : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_seriallpbken.rx_seriallpbken
+ rx_seriallpbken : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : out std_logic_vector(47 downto 0);
+ -- tx_clkout.clk
+ tx_clkout : out std_logic_vector(47 downto 0);
+ -- tx_control.tx_control
+ tx_control : in std_logic_vector(383 downto 0) := (others => '0');
+ -- tx_coreclkin.clk
+ tx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_empty : out std_logic_vector(47 downto 0);
+ -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_full : out std_logic_vector(47 downto 0);
+ -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pempty : out std_logic_vector(47 downto 0);
+ -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_enh_fifo_pfull : out std_logic_vector(47 downto 0);
+ -- tx_err_ins.tx_err_ins
+ tx_err_ins : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_parallel_data.tx_parallel_data
+ tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0');
+ -- tx_serial_clk0.clk
+ tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_serial_data.tx_serial_data
+ tx_serial_data : out std_logic_vector(47 downto 0);
+ -- unused_rx_control.unused_rx_control
+ unused_rx_control : out std_logic_vector(575 downto 0);
+ -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_rx_parallel_data : out std_logic_vector(3071 downto 0);
+ -- unused_tx_control.unused_tx_control
+ unused_tx_control : in std_logic_vector(431 downto 0) := (others => '0');
+ -- unused_tx_parallel_data.unused_tx_parallel_data
+ unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0')
);
end component;
component ip_arria10_e2sg_transceiver_pll_10g is
port (
- mcgb_rst : in std_logic := '0'; -- mcgb_rst.mcgb_rst
- mcgb_serial_clk : out std_logic; -- mcgb_serial_clk.clk
- pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
- pll_locked : out std_logic; -- pll_locked.pll_locked
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
- pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
- reconfig_write0 : in std_logic := '0'; -- reconfig_avmm0.write
- reconfig_read0 : in std_logic := '0'; -- .read
- reconfig_address0 : in std_logic_vector(9 downto 0) := (others => '0'); -- .address
- reconfig_writedata0 : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reconfig_readdata0 : out std_logic_vector(31 downto 0); -- .readdata
- reconfig_waitrequest0 : out std_logic; -- .waitrequest
- reconfig_clk0 : in std_logic := '0'; -- reconfig_clk0.clk
- reconfig_reset0 : in std_logic := '0'; -- reconfig_reset0.reset
- tx_serial_clk : out std_logic -- tx_serial_clk.clk
+ -- mcgb_rst.mcgb_rst
+ mcgb_rst : in std_logic := '0';
+ -- mcgb_serial_clk.clk
+ mcgb_serial_clk : out std_logic;
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy : out std_logic;
+ -- pll_locked.pll_locked
+ pll_locked : out std_logic;
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : in std_logic := '0';
+ -- pll_refclk0.clk
+ pll_refclk0 : in std_logic := '0';
+ -- reconfig_avmm0.write
+ reconfig_write0 : in std_logic := '0';
+ -- .read
+ reconfig_read0 : in std_logic := '0';
+ -- .address
+ reconfig_address0 : in std_logic_vector(9 downto 0) := (others => '0');
+ -- .writedata
+ reconfig_writedata0 : in std_logic_vector(31 downto 0) := (others => '0');
+ -- .readdata
+ reconfig_readdata0 : out std_logic_vector(31 downto 0);
+ -- .waitrequest
+ reconfig_waitrequest0 : out std_logic;
+ -- reconfig_clk0.clk
+ reconfig_clk0 : in std_logic := '0';
+ -- reconfig_reset0.reset
+ reconfig_reset0 : in std_logic := '0';
+ -- tx_serial_clk.clk
+ tx_serial_clk : out std_logic
-- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
-- pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
-- pll_locked : out std_logic; -- pll_locked.pll_locked
@@ -1601,115 +2925,199 @@ package tech_10gbase_r_component_pkg is
component ip_arria10_e2sg_transceiver_reset_controller_1 is
port (
- clock : in std_logic := '0'; -- clock.clk
- reset : in std_logic := '0'; -- reset.reset
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- tx_analogreset : out std_logic_vector(0 downto 0); -- tx_analogreset.tx_analogreset
- tx_digitalreset : out std_logic_vector(0 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(0 downto 0); -- tx_ready.tx_ready
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- tx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset.rx_analogreset
- rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_ready : out std_logic_vector(0 downto 0); -- rx_ready.rx_ready
- rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0') -- rx_cal_busy.rx_cal_busy
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(0 downto 0);
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(0 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(0 downto 0);
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(0 downto 0);
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(0 downto 0);
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(0 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => '0');
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0')
);
end component;
component ip_arria10_e2sg_transceiver_reset_controller_3 is
port (
- clock : in std_logic := '0'; -- clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select
- reset : in std_logic := '0'; -- reset
- rx_analogreset : out std_logic_vector(2 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_cal_busy
- rx_digitalreset : out std_logic_vector(2 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => '0'); -- rx_is_lockedtodata
- rx_ready : out std_logic_vector(2 downto 0); -- rx_ready
- tx_analogreset : out std_logic_vector(2 downto 0); -- tx_analogreset
- tx_cal_busy : in std_logic_vector(2 downto 0) := (others => '0'); -- tx_cal_busy
- tx_digitalreset : out std_logic_vector(2 downto 0); -- tx_digitalreset
- tx_ready : out std_logic_vector(2 downto 0) -- tx_ready
+ -- clk
+ clock : in std_logic := '0';
+ -- pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset
+ reset : in std_logic := '0';
+ -- rx_analogreset
+ rx_analogreset : out std_logic_vector(2 downto 0);
+ -- rx_cal_busy
+ rx_cal_busy : in std_logic_vector(2 downto 0) := (others => '0');
+ -- rx_digitalreset
+ rx_digitalreset : out std_logic_vector(2 downto 0);
+ -- rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => '0');
+ -- rx_ready
+ rx_ready : out std_logic_vector(2 downto 0);
+ -- tx_analogreset
+ tx_analogreset : out std_logic_vector(2 downto 0);
+ -- tx_cal_busy
+ tx_cal_busy : in std_logic_vector(2 downto 0) := (others => '0');
+ -- tx_digitalreset
+ tx_digitalreset : out std_logic_vector(2 downto 0);
+ -- tx_ready
+ tx_ready : out std_logic_vector(2 downto 0)
);
end component;
component ip_arria10_e2sg_transceiver_reset_controller_4
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(3 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(3 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(3 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(3 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(3 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(3 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(3 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(3 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(3 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(3 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(3 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(3 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(3 downto 0)
);
end component;
component ip_arria10_e2sg_transceiver_reset_controller_12
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(11 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(11 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(11 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(11 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(11 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(11 downto 0)
);
end component;
component ip_arria10_e2sg_transceiver_reset_controller_24
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(23 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(23 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(23 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(23 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(23 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(23 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(23 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(23 downto 0)
);
end component;
component ip_arria10_e2sg_transceiver_reset_controller_48
port (
- clock : in std_logic := '0'; -- clock.clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
- reset : in std_logic := '0'; -- reset.reset
- rx_analogreset : out std_logic_vector(47 downto 0); -- rx_analogreset.rx_analogreset
- rx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
- rx_digitalreset : out std_logic_vector(47 downto 0); -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready : out std_logic_vector(47 downto 0); -- rx_ready.rx_ready
- tx_analogreset : out std_logic_vector(47 downto 0); -- tx_analogreset.tx_analogreset
- tx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
- tx_digitalreset : out std_logic_vector(47 downto 0); -- tx_digitalreset.tx_digitalreset
- tx_ready : out std_logic_vector(47 downto 0) -- tx_ready.tx_ready
+ -- clock.clk
+ clock : in std_logic := '0';
+ -- pll_locked.pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0');
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select.pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0');
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset : out std_logic_vector(47 downto 0);
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset : out std_logic_vector(47 downto 0);
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => '0');
+ -- rx_ready.rx_ready
+ rx_ready : out std_logic_vector(47 downto 0);
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset : out std_logic_vector(47 downto 0);
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0');
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset : out std_logic_vector(47 downto 0);
+ -- tx_ready.tx_ready
+ tx_ready : out std_logic_vector(47 downto 0)
);
end component;
diff --git a/libraries/technology/clkbuf/tech_clkbuf.vhd b/libraries/technology/clkbuf/tech_clkbuf.vhd
index ccb8eb551dc32f6bac7d4f5cac5e8c6d4fb6a6c4..da8410139372c07fb1b685bf2f7a00a34e5c09a1 100644
--- a/libraries/technology/clkbuf/tech_clkbuf.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf.vhd
@@ -51,8 +51,10 @@ begin
gen_ip_arria10 : if g_technology = c_tech_arria10_proto and g_clock_net = "GLOBAL" generate
u0 : ip_arria10_clkbuf_global
port map (
- inclk => inclk, -- inclk
- outclk => outclk -- outclk
+ -- inclk
+ inclk => inclk,
+ -- outclk
+ outclk => outclk
);
end generate;
@@ -63,8 +65,10 @@ begin
gen_ip_arria10_e3sge3 : if g_technology = c_tech_arria10_e3sge3 and g_clock_net = "GLOBAL" generate
u0 : ip_arria10_e3sge3_clkbuf_global
port map (
- inclk => inclk, -- inclk
- outclk => outclk -- outclk
+ -- inclk
+ inclk => inclk,
+ -- outclk
+ outclk => outclk
);
end generate;
@@ -75,8 +79,10 @@ begin
gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg and g_clock_net = "GLOBAL" generate
u0 : ip_arria10_e1sg_clkbuf_global
port map (
- inclk => inclk, -- inclk
- outclk => outclk -- outclk
+ -- inclk
+ inclk => inclk,
+ -- outclk
+ outclk => outclk
);
end generate;
@@ -87,8 +93,10 @@ begin
gen_ip_arria10_e2sg : if g_technology = c_tech_arria10_e2sg and g_clock_net = "GLOBAL" generate
u0 : ip_arria10_e2sg_clkbuf_global
port map (
- inclk => inclk, -- inclk
- outclk => outclk -- outclk
+ -- inclk
+ inclk => inclk,
+ -- outclk
+ outclk => outclk
);
end generate;
diff --git a/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd b/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
index 11debb90e497181403d8842d5c1f5978c4337665..ef4438a38257abe04eb0b9dded351322da6fb1c4 100644
--- a/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
@@ -31,8 +31,10 @@ package tech_clkbuf_component_pkg is
component ip_arria10_clkbuf_global is
port (
- inclk : in std_logic := '0'; -- altclkctrl_input.inclk
- outclk : out std_logic -- altclkctrl_output.outclk
+ -- altclkctrl_input.inclk
+ inclk : in std_logic := '0';
+ -- altclkctrl_output.outclk
+ outclk : out std_logic
);
end component;
@@ -42,8 +44,10 @@ package tech_clkbuf_component_pkg is
component ip_arria10_e3sge3_clkbuf_global is
port (
- inclk : in std_logic := '0'; -- altclkctrl_input.inclk
- outclk : out std_logic -- altclkctrl_output.outclk
+ -- altclkctrl_input.inclk
+ inclk : in std_logic := '0';
+ -- altclkctrl_output.outclk
+ outclk : out std_logic
);
end component;
@@ -53,8 +57,10 @@ package tech_clkbuf_component_pkg is
component ip_arria10_e1sg_clkbuf_global is
port (
- inclk : in std_logic := '0'; -- altclkctrl_input.inclk
- outclk : out std_logic -- altclkctrl_output.outclk
+ -- altclkctrl_input.inclk
+ inclk : in std_logic := '0';
+ -- altclkctrl_output.outclk
+ outclk : out std_logic
);
end component;
@@ -64,8 +70,10 @@ package tech_clkbuf_component_pkg is
component ip_arria10_e2sg_clkbuf_global is
port (
- inclk : in std_logic := '0'; -- altclkctrl_input.inclk
- outclk : out std_logic -- altclkctrl_output.outclk
+ -- altclkctrl_input.inclk
+ inclk : in std_logic := '0';
+ -- altclkctrl_output.outclk
+ outclk : out std_logic
);
end component;
diff --git a/libraries/technology/ddr/sim_ddr.vhd b/libraries/technology/ddr/sim_ddr.vhd
index 5d719ed9d9f770ec3def88939edfe9088297ccf5..12fdb726a3c51f6b4fa2bbb4cc6107a18a0cd0ee 100644
--- a/libraries/technology/ddr/sim_ddr.vhd
+++ b/libraries/technology/ddr/sim_ddr.vhd
@@ -93,8 +93,10 @@ end sim_ddr;
architecture str of sim_ddr is
-- DDR size and controller data width
- constant c_nof_addr : natural := 2**func_tech_ddr_ctlr_address_w(g_tech_ddr); -- 8192;
- constant c_dat_w : natural := func_tech_ddr_ctlr_data_w(g_tech_ddr); -- 256;
+ -- 8192;
+ constant c_nof_addr : natural := 2**func_tech_ddr_ctlr_address_w(g_tech_ddr);
+ -- 256;
+ constant c_dat_w : natural := func_tech_ddr_ctlr_data_w(g_tech_ddr);
-- DDR memory
type t_mem_arr is array(0 to c_nof_addr - 1) of std_logic_vector(c_dat_w - 1 downto 0);
@@ -102,11 +104,16 @@ architecture str of sim_ddr is
type t_mem_state is record
address : natural;
burst_size : natural;
- burst_cnt : natural; -- = 0
- wr_bursting : boolean; -- = FALSE
- rd_bursting : boolean; -- = FALSE
- pending_wr : boolean; -- = FALSE
- pending_rd : boolean; -- = FALSE
+ -- = 0
+ burst_cnt : natural;
+ -- = FALSE
+ wr_bursting : boolean;
+ -- = FALSE
+ rd_bursting : boolean;
+ -- = FALSE
+ pending_wr : boolean;
+ -- = FALSE
+ pending_rd : boolean;
pending_address : natural;
pending_burst_size : natural;
end record;
@@ -172,7 +179,8 @@ begin
-- Pending write burst begin, after read burst
if v.pending_wr = true and v.rd_bursting = false then
v.pending_wr := false;
- if ctlr_mosi.wr = '1' then -- require that user has kept wr still active
+ -- require that user has kept wr still active
+ if ctlr_mosi.wr = '1' then
v.wr_bursting := true;
v.address := v.pending_address;
v.burst_size := v.pending_burst_size;
@@ -183,7 +191,8 @@ begin
-- Pending read burst begin, after read burst
if v.pending_rd = true and v.rd_bursting = false then
v.pending_rd := false;
- if ctlr_mosi.rd = '1' then -- require that user has kept rd still active
+ -- require that user has kept rd still active
+ if ctlr_mosi.rd = '1' then
v.rd_bursting := true;
v.address := v.pending_address;
v.burst_size := v.pending_burst_size;
diff --git a/libraries/technology/ddr/tech_ddr.vhd b/libraries/technology/ddr/tech_ddr.vhd
index e15ba40ef64495f7c64b282e72a75875e96aea95..ef6ecf931738cc0899d6df9fc7198efc93cadd57 100644
--- a/libraries/technology/ddr/tech_ddr.vhd
+++ b/libraries/technology/ddr/tech_ddr.vhd
@@ -35,7 +35,8 @@ use work.tech_ddr_pkg.all;
entity tech_ddr is
generic (
- g_sim_model : boolean := false; -- when FALSE use IP and external DDR3 model, else when TRUE: use fast behavioural model, requires no external memory (uses memory array).
+ -- when FALSE use IP and external DDR3 model, else when TRUE: use fast behavioural model, requires no external memory (uses memory array).
+ g_sim_model : boolean := false;
g_technology : natural := c_tech_select_default;
g_tech_ddr : t_c_tech_ddr
);
diff --git a/libraries/technology/ddr/tech_ddr_arria10.vhd b/libraries/technology/ddr/tech_ddr_arria10.vhd
index 0bf13a950e7a03dd6332747af1d46a9a58d0580c..294e17ef0a537e001c383ae734fb175f5acb309a 100644
--- a/libraries/technology/ddr/tech_ddr_arria10.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10.vhd
@@ -70,8 +70,10 @@ end tech_ddr_arria10;
architecture str of tech_ddr_arria10 is
constant c_gigabytes : integer := func_tech_ddr_module_gigabytes(g_tech_ddr);
- constant c_ctlr_address_w : natural := 26; -- func_tech_ddr_ctlr_address_w(g_tech_ddr);
- constant c_ctlr_data_w : natural := 576; -- func_tech_ddr_ctlr_data_w( g_tech_ddr);
+ -- func_tech_ddr_ctlr_address_w(g_tech_ddr);
+ constant c_ctlr_address_w : natural := 26;
+ -- func_tech_ddr_ctlr_data_w( g_tech_ddr);
+ constant c_ctlr_data_w : natural := 576;
signal i_ctlr_gen_clk : std_logic;
signal ref_rst_n : std_logic;
@@ -92,38 +94,70 @@ begin
u_ip_arria10_ddr4_4g_2000 : ip_arria10_ddr4_4g_2000
port map (
- amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => ctlr_mosi.rd, -- .read
- amm_write_0 => ctlr_mosi.wr, -- .write
- amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0), -- .readdata
- amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0), -- .writedata
- amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- amm_byteenable_0 => (others => '1'), -- .byteenable
- amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
- emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => phy_ou.par, -- .mem_par
- mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => ctlr_miso.waitrequest_n,
+ -- .read
+ amm_read_0 => ctlr_mosi.rd,
+ -- .write
+ amm_write_0 => ctlr_mosi.wr,
+ -- .address
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdata
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0),
+ -- .writedata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0),
+ -- .burstcount
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- .byteenable
+ amm_byteenable_0 => (others => '1'),
+ -- .readdatavalid
+ amm_readdatavalid_0 => ctlr_miso.rdval,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => i_ctlr_gen_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => ctlr_gen_rst_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => phy_ou.act_n,
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => phy_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => phy_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(phy_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => phy_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
@@ -147,38 +181,70 @@ begin
u_ip_arria10_ddr4_4g_1600 : ip_arria10_ddr4_4g_1600
port map (
- amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => ctlr_mosi.rd, -- .read
- amm_write_0 => ctlr_mosi.wr, -- .write
- amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0), -- .readdata
- amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0), -- .writedata
- amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- amm_byteenable_0 => (others => '1'), -- .byteenable
- amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
- emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => phy_ou.par, -- .mem_par
- mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => ctlr_miso.waitrequest_n,
+ -- .read
+ amm_read_0 => ctlr_mosi.rd,
+ -- .write
+ amm_write_0 => ctlr_mosi.wr,
+ -- .address
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdata
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0),
+ -- .writedata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0),
+ -- .burstcount
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- .byteenable
+ amm_byteenable_0 => (others => '1'),
+ -- .readdatavalid
+ amm_readdatavalid_0 => ctlr_miso.rdval,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => i_ctlr_gen_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => ctlr_gen_rst_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => phy_ou.act_n,
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => phy_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => phy_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(phy_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => phy_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
index ab1bb6058ef7ddbfa90f8021c2947b5a8cdbc81e..c4ecb3edb7e3e46c9ad61fe0490e1d6090a8b68b 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
@@ -74,7 +74,8 @@ architecture str of tech_ddr_arria10_e1sg is
constant c_gigabytes : integer := func_tech_ddr_module_gigabytes(g_tech_ddr);
constant c_ctlr_address_w : natural := func_tech_ddr_ctlr_address_w(g_tech_ddr);
- constant c_ctlr_data_w : natural := 576; -- func_tech_ddr_ctlr_data_w( g_tech_ddr);
+ -- func_tech_ddr_ctlr_data_w( g_tech_ddr);
+ constant c_ctlr_data_w : natural := 576;
signal i_ctlr_gen_clk : std_logic;
signal ref_rst_n : std_logic;
@@ -95,38 +96,70 @@ begin
u_ip_arria10_e1sg_ddr4_4g_2000 : ip_arria10_e1sg_ddr4_4g_2000
port map (
- amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => ctlr_mosi.rd, -- .read
- amm_write_0 => ctlr_mosi.wr, -- .write
- amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0), -- .readdata
- amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0), -- .writedata
- amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- amm_byteenable_0 => (others => '1'), -- .byteenable
- amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
- emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => phy_ou.par, -- .mem_par
- mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => ctlr_miso.waitrequest_n,
+ -- .read
+ amm_read_0 => ctlr_mosi.rd,
+ -- .write
+ amm_write_0 => ctlr_mosi.wr,
+ -- .address
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdata
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0),
+ -- .writedata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0),
+ -- .burstcount
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- .byteenable
+ amm_byteenable_0 => (others => '1'),
+ -- .readdatavalid
+ amm_readdatavalid_0 => ctlr_miso.rdval,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => i_ctlr_gen_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => ctlr_gen_rst_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => phy_ou.act_n,
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => phy_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => phy_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(phy_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => phy_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
@@ -150,38 +183,70 @@ begin
u_ip_arria10_e1sg_ddr4_4g_1600 : ip_arria10_e1sg_ddr4_4g_1600
port map (
- amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => ctlr_mosi.rd, -- .read
- amm_write_0 => ctlr_mosi.wr, -- .write
- amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0), -- .readdata
- amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0), -- .writedata
- amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- amm_byteenable_0 => (others => '1'), -- .byteenable
- amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
- emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => phy_ou.par, -- .mem_par
- mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => ctlr_miso.waitrequest_n,
+ -- .read
+ amm_read_0 => ctlr_mosi.rd,
+ -- .write
+ amm_write_0 => ctlr_mosi.wr,
+ -- .address
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdata
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0),
+ -- .writedata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0),
+ -- .burstcount
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- .byteenable
+ amm_byteenable_0 => (others => '1'),
+ -- .readdatavalid
+ amm_readdatavalid_0 => ctlr_miso.rdval,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => i_ctlr_gen_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => ctlr_gen_rst_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => phy_ou.act_n,
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => phy_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => phy_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(phy_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => phy_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
@@ -201,38 +266,70 @@ begin
gen_ip_arria10_e1sg_ddr4_8g_1600 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 8 and g_tech_ddr.mts = 1600 generate
u_ip_arria10_e1sg_ddr4_8g_1600 : ip_arria10_e1sg_ddr4_8g_1600
port map (
- amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => ctlr_mosi.rd, -- .read
- amm_write_0 => ctlr_mosi.wr, -- .write
- amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0), -- .readdata
- amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0), -- .writedata
- amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- amm_byteenable_0 => (others => '1'), -- .byteenable
- amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
- emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => phy_ou.par, -- .mem_par
- mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => ctlr_miso.waitrequest_n,
+ -- .read
+ amm_read_0 => ctlr_mosi.rd,
+ -- .write
+ amm_write_0 => ctlr_mosi.wr,
+ -- .address
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdata
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0),
+ -- .writedata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0),
+ -- .burstcount
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- .byteenable
+ amm_byteenable_0 => (others => '1'),
+ -- .readdatavalid
+ amm_readdatavalid_0 => ctlr_miso.rdval,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => i_ctlr_gen_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => ctlr_gen_rst_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => phy_ou.act_n,
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => phy_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => phy_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(phy_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => phy_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
@@ -252,38 +349,70 @@ begin
gen_ip_arria10_e1sg_ddr4_16g_1600 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 16 and g_tech_ddr.mts = 1600 generate
u_ip_arria10_e1sg_ddr4_16g_1600 : ip_arria10_e1sg_ddr4_16g_1600
port map (
- amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => ctlr_mosi.rd, -- .read
- amm_write_0 => ctlr_mosi.wr, -- .write
- amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0), -- .readdata
- amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0), -- .writedata
- amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- amm_byteenable_0 => (others => '1'), -- .byteenable
- amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
- emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => phy_ou.par, -- .mem_par
- mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => ctlr_miso.waitrequest_n,
+ -- .read
+ amm_read_0 => ctlr_mosi.rd,
+ -- .write
+ amm_write_0 => ctlr_mosi.wr,
+ -- .address
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdata
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0),
+ -- .writedata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0),
+ -- .burstcount
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- .byteenable
+ amm_byteenable_0 => (others => '1'),
+ -- .readdatavalid
+ amm_readdatavalid_0 => ctlr_miso.rdval,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => i_ctlr_gen_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => ctlr_gen_rst_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => phy_ou.act_n,
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => phy_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => phy_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(phy_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => phy_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
index 0f98ab5202f0e934d570596b80d1b31c68050b95..01e407adabd654bae67e89c5227ab8fff7cab0a0 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
@@ -94,38 +94,70 @@ begin
gen_ip_arria10_e2sg_ddr4_8g_1600 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 8 and g_tech_ddr.mts = 1600 generate
u_ip_arria10_e2sg_ddr4_8g_1600 : ip_arria10_e2sg_ddr4_8g_1600
port map (
- amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => ctlr_mosi.rd, -- .read
- amm_write_0 => ctlr_mosi.wr, -- .write
- amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- amm_readdata_0 => ctlr_miso.rddata(c_ctlr_ip_data_w - 1 downto 0), -- .readdata
- amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_ip_data_w - 1 downto 0), -- .writedata
- amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- amm_byteenable_0 => (others => '1'), -- .byteenable
- amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
- emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => phy_ou.par, -- .mem_par
- mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => ctlr_miso.waitrequest_n,
+ -- .read
+ amm_read_0 => ctlr_mosi.rd,
+ -- .write
+ amm_write_0 => ctlr_mosi.wr,
+ -- .address
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdata
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_ip_data_w - 1 downto 0),
+ -- .writedata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_ip_data_w - 1 downto 0),
+ -- .burstcount
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- .byteenable
+ amm_byteenable_0 => (others => '1'),
+ -- .readdatavalid
+ amm_readdatavalid_0 => ctlr_miso.rdval,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => i_ctlr_gen_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => ctlr_gen_rst_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => phy_ou.act_n,
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => phy_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => phy_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(phy_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => phy_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
@@ -145,38 +177,70 @@ begin
gen_ip_arria10_e2sg_ddr4_8g_2400 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 8 and g_tech_ddr.mts = 2400 generate
u_ip_arria10_e2sg_ddr4_8g_2400 : ip_arria10_e2sg_ddr4_8g_2400
port map (
- amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => ctlr_mosi.rd, -- .read
- amm_write_0 => ctlr_mosi.wr, -- .write
- amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- amm_readdata_0 => ctlr_miso.rddata(c_ctlr_ip_data_w - 1 downto 0), -- .readdata
- amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_ip_data_w - 1 downto 0), -- .writedata
- amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- amm_byteenable_0 => (others => '1'), -- .byteenable
- amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
- emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => phy_ou.par, -- .mem_par
- mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => ctlr_miso.waitrequest_n,
+ -- .read
+ amm_read_0 => ctlr_mosi.rd,
+ -- .write
+ amm_write_0 => ctlr_mosi.wr,
+ -- .address
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdata
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_ip_data_w - 1 downto 0),
+ -- .writedata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_ip_data_w - 1 downto 0),
+ -- .burstcount
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- .byteenable
+ amm_byteenable_0 => (others => '1'),
+ -- .readdatavalid
+ amm_readdatavalid_0 => ctlr_miso.rdval,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => i_ctlr_gen_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => ctlr_gen_rst_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => phy_ou.act_n,
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => phy_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => phy_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(phy_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => phy_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
@@ -196,38 +260,70 @@ begin
gen_ip_arria10_e2sg_ddr4_16g_1600_64b : if g_tech_ddr.name = "DDR4" and c_gigabytes = 16 and g_tech_ddr.mts = 1600 and g_tech_ddr.dq_w = 64 generate
u_ip_arria10_e2sg_ddr4_16g_1600_64b : ip_arria10_e2sg_ddr4_16g_1600_64b
port map (
- amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => ctlr_mosi.rd, -- .read
- amm_write_0 => ctlr_mosi.wr, -- .write
- amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- amm_readdata_0 => ctlr_miso.rddata(c_ctlr_ip_data_w - 1 downto 0), -- .readdata
- amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_ip_data_w - 1 downto 0), -- .writedata
- amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- amm_byteenable_0 => (others => '1'), -- .byteenable
- amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
- emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => phy_ou.par, -- .mem_par
- mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => ctlr_miso.waitrequest_n,
+ -- .read
+ amm_read_0 => ctlr_mosi.rd,
+ -- .write
+ amm_write_0 => ctlr_mosi.wr,
+ -- .address
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdata
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_ip_data_w - 1 downto 0),
+ -- .writedata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_ip_data_w - 1 downto 0),
+ -- .burstcount
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- .byteenable
+ amm_byteenable_0 => (others => '1'),
+ -- .readdatavalid
+ amm_readdatavalid_0 => ctlr_miso.rdval,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => i_ctlr_gen_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => ctlr_gen_rst_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => phy_ou.act_n,
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => phy_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => phy_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(phy_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => phy_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
@@ -247,38 +343,70 @@ begin
gen_ip_arria10_e2sg_ddr4_16g_1600_72b : if g_tech_ddr.name = "DDR4" and c_gigabytes = 16 and g_tech_ddr.mts = 1600 and g_tech_ddr.dq_w = 72 generate
u_ip_arria10_e2sg_ddr4_16g_1600_72b : ip_arria10_e2sg_ddr4_16g_1600_72b
port map (
- amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => ctlr_mosi.rd, -- .read
- amm_write_0 => ctlr_mosi.wr, -- .write
- amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- amm_readdata_0 => amm_readdata, -- .readdata
- amm_writedata_0 => amm_writedata, -- .writedata
- amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- amm_byteenable_0 => (others => '1'), -- .byteenable
- amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
- emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => phy_ou.par, -- .mem_par
- mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => ctlr_miso.waitrequest_n,
+ -- .read
+ amm_read_0 => ctlr_mosi.rd,
+ -- .write
+ amm_write_0 => ctlr_mosi.wr,
+ -- .address
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdata
+ amm_readdata_0 => amm_readdata,
+ -- .writedata
+ amm_writedata_0 => amm_writedata,
+ -- .burstcount
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- .byteenable
+ amm_byteenable_0 => (others => '1'),
+ -- .readdatavalid
+ amm_readdatavalid_0 => ctlr_miso.rdval,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => i_ctlr_gen_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => ctlr_gen_rst_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => phy_ou.act_n,
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => phy_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => phy_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(phy_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => phy_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
@@ -290,7 +418,8 @@ begin
-- local_init_done = ctlr_init_done originally and mapped to ctlr_miso.done for the DDR3 IP. For the DDR4 IP the local_cal_success and
-- NOT local_cal_fail seem to serve as local_init_done
- gen_rewire_data : if g_tech_ddr.mem_dq_w < g_tech_ddr.dq_w generate -- Used when 64 bit modules are used in unb2c slot II as it only supports 72 bit IP (not 64 bit IP).
+ -- Used when 64 bit modules are used in unb2c slot II as it only supports 72 bit IP (not 64 bit IP).
+ gen_rewire_data : if g_tech_ddr.mem_dq_w < g_tech_ddr.dq_w generate
ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0) <= func_tech_ddr_rewire_72b_to_64b(g_tech_ddr, amm_readdata);
amm_writedata <= func_tech_ddr_rewire_64b_to_72b(g_tech_ddr, ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0));
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd b/libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd
index c7dd3c97dc1b666a02f87466c5419cf782b4140f..fc345adf087019b9b1a33b1e714338c9778d8af1 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd
@@ -73,7 +73,8 @@ architecture str of tech_ddr_arria10_e3sge3 is
constant c_gigabytes : integer := func_tech_ddr_module_gigabytes(g_tech_ddr);
constant c_ctlr_address_w : natural := func_tech_ddr_ctlr_address_w(g_tech_ddr);
- constant c_ctlr_data_w : natural := 576; -- func_tech_ddr_ctlr_data_w( g_tech_ddr);
+ -- func_tech_ddr_ctlr_data_w( g_tech_ddr);
+ constant c_ctlr_data_w : natural := 576;
signal i_ctlr_gen_clk : std_logic;
signal ref_rst_n : std_logic;
@@ -94,38 +95,70 @@ begin
u_ip_arria10_e3sge3_ddr4_4g_2000 : ip_arria10_e3sge3_ddr4_4g_2000
port map (
- amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => ctlr_mosi.rd, -- .read
- amm_write_0 => ctlr_mosi.wr, -- .write
- amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0), -- .readdata
- amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0), -- .writedata
- amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- amm_byteenable_0 => (others => '1'), -- .byteenable
- amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
- emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => phy_ou.par, -- .mem_par
- mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => ctlr_miso.waitrequest_n,
+ -- .read
+ amm_read_0 => ctlr_mosi.rd,
+ -- .write
+ amm_write_0 => ctlr_mosi.wr,
+ -- .address
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdata
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0),
+ -- .writedata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0),
+ -- .burstcount
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- .byteenable
+ amm_byteenable_0 => (others => '1'),
+ -- .readdatavalid
+ amm_readdatavalid_0 => ctlr_miso.rdval,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => i_ctlr_gen_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => ctlr_gen_rst_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => phy_ou.act_n,
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => phy_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => phy_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(phy_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => phy_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
@@ -149,38 +182,70 @@ begin
u_ip_arria10_e3sge3_ddr4_4g_1600 : ip_arria10_e3sge3_ddr4_4g_1600
port map (
- amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => ctlr_mosi.rd, -- .read
- amm_write_0 => ctlr_mosi.wr, -- .write
- amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0), -- .readdata
- amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0), -- .writedata
- amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- amm_byteenable_0 => (others => '1'), -- .byteenable
- amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
- emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => phy_ou.par, -- .mem_par
- mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => ctlr_miso.waitrequest_n,
+ -- .read
+ amm_read_0 => ctlr_mosi.rd,
+ -- .write
+ amm_write_0 => ctlr_mosi.wr,
+ -- .address
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdata
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0),
+ -- .writedata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0),
+ -- .burstcount
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- .byteenable
+ amm_byteenable_0 => (others => '1'),
+ -- .readdatavalid
+ amm_readdatavalid_0 => ctlr_miso.rdval,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => i_ctlr_gen_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => ctlr_gen_rst_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => phy_ou.act_n,
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => phy_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => phy_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(phy_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => phy_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
@@ -200,38 +265,70 @@ begin
gen_ip_arria10_e3sge3_ddr4_8g_1600 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 8 and g_tech_ddr.mts = 1600 generate
u_ip_arria10_e3sge3_ddr4_8g_1600 : ip_arria10_e3sge3_ddr4_8g_1600
port map (
- amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => ctlr_mosi.rd, -- .read
- amm_write_0 => ctlr_mosi.wr, -- .write
- amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0), -- .readdata
- amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0), -- .writedata
- amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- amm_byteenable_0 => (others => '1'), -- .byteenable
- amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
- emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => phy_ou.par, -- .mem_par
- mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => ctlr_miso.waitrequest_n,
+ -- .read
+ amm_read_0 => ctlr_mosi.rd,
+ -- .write
+ amm_write_0 => ctlr_mosi.wr,
+ -- .address
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdata
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0),
+ -- .writedata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0),
+ -- .burstcount
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- .byteenable
+ amm_byteenable_0 => (others => '1'),
+ -- .readdatavalid
+ amm_readdatavalid_0 => ctlr_miso.rdval,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => i_ctlr_gen_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => ctlr_gen_rst_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => ref_rst_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_act_n
+ sl(mem_act_n) => phy_ou.act_n,
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ sl(mem_reset_n) => phy_ou.reset_n,
+ -- .mem_par
+ sl(mem_par) => phy_ou.par,
+ -- .mem_alert_n
+ mem_alert_n => slv(phy_in.alert_n),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0),
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => phy_in.oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => local_cal_fail
);
-- Signals in DDR3 that are not available with DDR4:
diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
index fb1f0bf99002831f2659b41cd0d0a6d60291c365..cbc40bbad8d4fe837d55d48a66fd3510ac42b284 100644
--- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -33,52 +33,98 @@ package tech_ddr_component_pkg is
-- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
component ip_stratixiv_ddr3_uphy_4g_800_master is
port (
- pll_ref_clk : in std_logic; -- pll_ref_clk.clk
- global_reset_n : in std_logic; -- global_reset.reset_n
- soft_reset_n : in std_logic; -- soft_reset.reset_n
- afi_clk : out std_logic; -- afi_clk.clk
- afi_half_clk : out std_logic; -- afi_half_clk.clk
- afi_reset_n : out std_logic; -- afi_reset.reset_n
- mem_a : out std_logic_vector(14 downto 0); -- memory.mem_a
- mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
- mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
- mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
- mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
- mem_ras_n : out std_logic; -- .mem_ras_n
- mem_cas_n : out std_logic; -- .mem_cas_n
- mem_we_n : out std_logic; -- .mem_we_n
- mem_reset_n : out std_logic; -- .mem_reset_n
- mem_dq : inout std_logic_vector(63 downto 0); -- .mem_dq
- mem_dqs : inout std_logic_vector(7 downto 0); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(7 downto 0); -- .mem_dqs_n
- mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
- avl_ready : out std_logic; -- avl.waitrequest_n
- avl_burstbegin : in std_logic; -- .beginbursttransfer
- avl_addr : in std_logic_vector(26 downto 0); -- .address
- avl_rdata_valid : out std_logic; -- .readdatavalid
- avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
- avl_wdata : in std_logic_vector(255 downto 0); -- .writedata
- avl_be : in std_logic_vector(31 downto 0); -- .byteenable
- avl_read_req : in std_logic; -- .read
- avl_write_req : in std_logic; -- .write
- avl_size : in std_logic_vector(6 downto 0); -- .burstcount
- local_init_done : out std_logic; -- status.local_init_done
- local_cal_success : out std_logic; -- .local_cal_success
- local_cal_fail : out std_logic; -- .local_cal_fail
- oct_rdn : in std_logic; -- oct.rdn
- oct_rup : in std_logic; -- .rup
- seriesterminationcontrol : out std_logic_vector(13 downto 0); -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol : out std_logic_vector(13 downto 0); -- .parallelterminationcontrol
- pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
- pll_write_clk : out std_logic; -- .pll_write_clk
- pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
- pll_locked : out std_logic; -- .pll_locked
- pll_avl_clk : out std_logic; -- .pll_avl_clk
- pll_config_clk : out std_logic; -- .pll_config_clk
- dll_delayctrl : out std_logic_vector(5 downto 0) -- dll_sharing.dll_delayctrl
+ -- pll_ref_clk.clk
+ pll_ref_clk : in std_logic;
+ -- global_reset.reset_n
+ global_reset_n : in std_logic;
+ -- soft_reset.reset_n
+ soft_reset_n : in std_logic;
+ -- afi_clk.clk
+ afi_clk : out std_logic;
+ -- afi_half_clk.clk
+ afi_half_clk : out std_logic;
+ -- afi_reset.reset_n
+ afi_reset_n : out std_logic;
+ -- memory.mem_a
+ mem_a : out std_logic_vector(14 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(2 downto 0);
+ -- .mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- .mem_dm
+ mem_dm : out std_logic_vector(7 downto 0);
+ -- .mem_ras_n
+ mem_ras_n : out std_logic;
+ -- .mem_cas_n
+ mem_cas_n : out std_logic;
+ -- .mem_we_n
+ mem_we_n : out std_logic;
+ -- .mem_reset_n
+ mem_reset_n : out std_logic;
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(63 downto 0);
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(7 downto 0);
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(7 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- avl.waitrequest_n
+ avl_ready : out std_logic;
+ -- .beginbursttransfer
+ avl_burstbegin : in std_logic;
+ -- .address
+ avl_addr : in std_logic_vector(26 downto 0);
+ -- .readdatavalid
+ avl_rdata_valid : out std_logic;
+ -- .readdata
+ avl_rdata : out std_logic_vector(255 downto 0);
+ -- .writedata
+ avl_wdata : in std_logic_vector(255 downto 0);
+ -- .byteenable
+ avl_be : in std_logic_vector(31 downto 0);
+ -- .read
+ avl_read_req : in std_logic;
+ -- .write
+ avl_write_req : in std_logic;
+ -- .burstcount
+ avl_size : in std_logic_vector(6 downto 0);
+ -- status.local_init_done
+ local_init_done : out std_logic;
+ -- .local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic;
+ -- oct.rdn
+ oct_rdn : in std_logic;
+ -- .rup
+ oct_rup : in std_logic;
+ -- oct_sharing.seriesterminationcontrol
+ seriesterminationcontrol : out std_logic_vector(13 downto 0);
+ -- .parallelterminationcontrol
+ parallelterminationcontrol : out std_logic_vector(13 downto 0);
+ -- pll_sharing.pll_mem_clk
+ pll_mem_clk : out std_logic;
+ -- .pll_write_clk
+ pll_write_clk : out std_logic;
+ -- .pll_write_clk_pre_phy_clk
+ pll_write_clk_pre_phy_clk : out std_logic;
+ -- .pll_addr_cmd_clk
+ pll_addr_cmd_clk : out std_logic;
+ -- .pll_locked
+ pll_locked : out std_logic;
+ -- .pll_avl_clk
+ pll_avl_clk : out std_logic;
+ -- .pll_config_clk
+ pll_config_clk : out std_logic;
+ -- dll_sharing.dll_delayctrl
+ dll_delayctrl : out std_logic_vector(5 downto 0)
);
end component;
@@ -86,102 +132,192 @@ package tech_ddr_component_pkg is
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
component ip_stratixiv_ddr3_uphy_4g_800_slave is
port (
- pll_ref_clk : in std_logic; -- pll_ref_clk.clk
- global_reset_n : in std_logic; -- global_reset.reset_n
- soft_reset_n : in std_logic; -- soft_reset.reset_n
- afi_clk : out std_logic; -- afi_clk.clk
- afi_half_clk : out std_logic; -- afi_half_clk.clk
- afi_reset_n : out std_logic; -- afi_reset.reset_n
- mem_a : out std_logic_vector(14 downto 0); -- memory.mem_a
- mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
- mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
- mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
- mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
- mem_ras_n : out std_logic; -- .mem_ras_n
- mem_cas_n : out std_logic; -- .mem_cas_n
- mem_we_n : out std_logic; -- .mem_we_n
- mem_reset_n : out std_logic; -- .mem_reset_n
- mem_dq : inout std_logic_vector(63 downto 0); -- .mem_dq
- mem_dqs : inout std_logic_vector(7 downto 0); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(7 downto 0); -- .mem_dqs_n
- mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
- avl_ready : out std_logic; -- avl.waitrequest_n
- avl_burstbegin : in std_logic; -- .beginbursttransfer
- avl_addr : in std_logic_vector(26 downto 0); -- .address
- avl_rdata_valid : out std_logic; -- .readdatavalid
- avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
- avl_wdata : in std_logic_vector(255 downto 0); -- .writedata
- avl_be : in std_logic_vector(31 downto 0); -- .byteenable
- avl_read_req : in std_logic; -- .read
- avl_write_req : in std_logic; -- .write
- avl_size : in std_logic_vector(6 downto 0); -- .burstcount
- local_init_done : out std_logic; -- status.local_init_done
- local_cal_success : out std_logic; -- .local_cal_success
- local_cal_fail : out std_logic; -- .local_cal_fail
- seriesterminationcontrol : in std_logic_vector(13 downto 0); -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol : in std_logic_vector(13 downto 0); -- .parallelterminationcontrol
- pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
- pll_write_clk : out std_logic; -- .pll_write_clk
- pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
- pll_locked : out std_logic; -- .pll_locked
- pll_avl_clk : out std_logic; -- .pll_avl_clk
- pll_config_clk : out std_logic; -- .pll_config_clk
- dll_delayctrl : out std_logic_vector(5 downto 0) -- dll_sharing.dll_delayctrl
+ -- pll_ref_clk.clk
+ pll_ref_clk : in std_logic;
+ -- global_reset.reset_n
+ global_reset_n : in std_logic;
+ -- soft_reset.reset_n
+ soft_reset_n : in std_logic;
+ -- afi_clk.clk
+ afi_clk : out std_logic;
+ -- afi_half_clk.clk
+ afi_half_clk : out std_logic;
+ -- afi_reset.reset_n
+ afi_reset_n : out std_logic;
+ -- memory.mem_a
+ mem_a : out std_logic_vector(14 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(2 downto 0);
+ -- .mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- .mem_dm
+ mem_dm : out std_logic_vector(7 downto 0);
+ -- .mem_ras_n
+ mem_ras_n : out std_logic;
+ -- .mem_cas_n
+ mem_cas_n : out std_logic;
+ -- .mem_we_n
+ mem_we_n : out std_logic;
+ -- .mem_reset_n
+ mem_reset_n : out std_logic;
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(63 downto 0);
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(7 downto 0);
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(7 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- avl.waitrequest_n
+ avl_ready : out std_logic;
+ -- .beginbursttransfer
+ avl_burstbegin : in std_logic;
+ -- .address
+ avl_addr : in std_logic_vector(26 downto 0);
+ -- .readdatavalid
+ avl_rdata_valid : out std_logic;
+ -- .readdata
+ avl_rdata : out std_logic_vector(255 downto 0);
+ -- .writedata
+ avl_wdata : in std_logic_vector(255 downto 0);
+ -- .byteenable
+ avl_be : in std_logic_vector(31 downto 0);
+ -- .read
+ avl_read_req : in std_logic;
+ -- .write
+ avl_write_req : in std_logic;
+ -- .burstcount
+ avl_size : in std_logic_vector(6 downto 0);
+ -- status.local_init_done
+ local_init_done : out std_logic;
+ -- .local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic;
+ -- oct_sharing.seriesterminationcontrol
+ seriesterminationcontrol : in std_logic_vector(13 downto 0);
+ -- .parallelterminationcontrol
+ parallelterminationcontrol : in std_logic_vector(13 downto 0);
+ -- pll_sharing.pll_mem_clk
+ pll_mem_clk : out std_logic;
+ -- .pll_write_clk
+ pll_write_clk : out std_logic;
+ -- .pll_write_clk_pre_phy_clk
+ pll_write_clk_pre_phy_clk : out std_logic;
+ -- .pll_addr_cmd_clk
+ pll_addr_cmd_clk : out std_logic;
+ -- .pll_locked
+ pll_locked : out std_logic;
+ -- .pll_avl_clk
+ pll_avl_clk : out std_logic;
+ -- .pll_config_clk
+ pll_config_clk : out std_logic;
+ -- dll_sharing.dll_delayctrl
+ dll_delayctrl : out std_logic_vector(5 downto 0)
);
end component;
-- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
component ip_stratixiv_ddr3_uphy_4g_single_rank_800_master is
port (
- pll_ref_clk : in std_logic; -- pll_ref_clk.clk
- global_reset_n : in std_logic; -- global_reset.reset_n
- soft_reset_n : in std_logic; -- soft_reset.reset_n
- afi_clk : out std_logic; -- afi_clk.clk
- afi_half_clk : out std_logic; -- afi_half_clk.clk
- afi_reset_n : out std_logic; -- afi_reset.reset_n
- mem_a : out std_logic_vector(15 downto 0); -- memory.mem_a
- mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
- mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
- mem_cke : out std_logic; -- .mem_cke
- mem_cs_n : out std_logic; -- .mem_cs_n
- mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
- mem_ras_n : out std_logic; -- .mem_ras_n
- mem_cas_n : out std_logic; -- .mem_cas_n
- mem_we_n : out std_logic; -- .mem_we_n
- mem_reset_n : out std_logic; -- .mem_reset_n
- mem_dq : inout std_logic_vector(63 downto 0); -- .mem_dq
- mem_dqs : inout std_logic_vector(7 downto 0); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(7 downto 0); -- .mem_dqs_n
- mem_odt : out std_logic; -- .mem_odt
- avl_ready : out std_logic; -- avl.waitrequest_n
- avl_burstbegin : in std_logic; -- .beginbursttransfer
- avl_addr : in std_logic_vector(26 downto 0); -- .address
- avl_rdata_valid : out std_logic; -- .readdatavalid
- avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
- avl_wdata : in std_logic_vector(255 downto 0); -- .writedata
- avl_be : in std_logic_vector(31 downto 0); -- .byteenable
- avl_read_req : in std_logic; -- .read
- avl_write_req : in std_logic; -- .write
- avl_size : in std_logic_vector(6 downto 0); -- .burstcount
- local_init_done : out std_logic; -- status.local_init_done
- local_cal_success : out std_logic; -- .local_cal_success
- local_cal_fail : out std_logic; -- .local_cal_fail
- oct_rdn : in std_logic; -- oct.rdn
- oct_rup : in std_logic; -- .rup
- seriesterminationcontrol : out std_logic_vector(13 downto 0); -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol : out std_logic_vector(13 downto 0); -- .parallelterminationcontrol
- pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
- pll_write_clk : out std_logic; -- .pll_write_clk
- pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
- pll_locked : out std_logic; -- .pll_locked
- pll_avl_clk : out std_logic; -- .pll_avl_clk
- pll_config_clk : out std_logic; -- .pll_config_clk
- dll_delayctrl : out std_logic_vector(5 downto 0) -- dll_sharing.dll_delayctrl
+ -- pll_ref_clk.clk
+ pll_ref_clk : in std_logic;
+ -- global_reset.reset_n
+ global_reset_n : in std_logic;
+ -- soft_reset.reset_n
+ soft_reset_n : in std_logic;
+ -- afi_clk.clk
+ afi_clk : out std_logic;
+ -- afi_half_clk.clk
+ afi_half_clk : out std_logic;
+ -- afi_reset.reset_n
+ afi_reset_n : out std_logic;
+ -- memory.mem_a
+ mem_a : out std_logic_vector(15 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(2 downto 0);
+ -- .mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic;
+ -- .mem_cs_n
+ mem_cs_n : out std_logic;
+ -- .mem_dm
+ mem_dm : out std_logic_vector(7 downto 0);
+ -- .mem_ras_n
+ mem_ras_n : out std_logic;
+ -- .mem_cas_n
+ mem_cas_n : out std_logic;
+ -- .mem_we_n
+ mem_we_n : out std_logic;
+ -- .mem_reset_n
+ mem_reset_n : out std_logic;
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(63 downto 0);
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(7 downto 0);
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(7 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic;
+ -- avl.waitrequest_n
+ avl_ready : out std_logic;
+ -- .beginbursttransfer
+ avl_burstbegin : in std_logic;
+ -- .address
+ avl_addr : in std_logic_vector(26 downto 0);
+ -- .readdatavalid
+ avl_rdata_valid : out std_logic;
+ -- .readdata
+ avl_rdata : out std_logic_vector(255 downto 0);
+ -- .writedata
+ avl_wdata : in std_logic_vector(255 downto 0);
+ -- .byteenable
+ avl_be : in std_logic_vector(31 downto 0);
+ -- .read
+ avl_read_req : in std_logic;
+ -- .write
+ avl_write_req : in std_logic;
+ -- .burstcount
+ avl_size : in std_logic_vector(6 downto 0);
+ -- status.local_init_done
+ local_init_done : out std_logic;
+ -- .local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic;
+ -- oct.rdn
+ oct_rdn : in std_logic;
+ -- .rup
+ oct_rup : in std_logic;
+ -- oct_sharing.seriesterminationcontrol
+ seriesterminationcontrol : out std_logic_vector(13 downto 0);
+ -- .parallelterminationcontrol
+ parallelterminationcontrol : out std_logic_vector(13 downto 0);
+ -- pll_sharing.pll_mem_clk
+ pll_mem_clk : out std_logic;
+ -- .pll_write_clk
+ pll_write_clk : out std_logic;
+ -- .pll_write_clk_pre_phy_clk
+ pll_write_clk_pre_phy_clk : out std_logic;
+ -- .pll_addr_cmd_clk
+ pll_addr_cmd_clk : out std_logic;
+ -- .pll_locked
+ pll_locked : out std_logic;
+ -- .pll_avl_clk
+ pll_avl_clk : out std_logic;
+ -- .pll_config_clk
+ pll_config_clk : out std_logic;
+ -- dll_sharing.dll_delayctrl
+ dll_delayctrl : out std_logic_vector(5 downto 0)
);
end component;
@@ -189,102 +325,192 @@ package tech_ddr_component_pkg is
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
component ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave is
port (
- pll_ref_clk : in std_logic; -- pll_ref_clk.clk
- global_reset_n : in std_logic; -- global_reset.reset_n
- soft_reset_n : in std_logic; -- soft_reset.reset_n
- afi_clk : out std_logic; -- afi_clk_in.clk
- afi_half_clk : out std_logic; -- afi_half_clk_in.clk
- afi_reset_n : out std_logic; -- afi_reset_in.reset_n
- mem_a : out std_logic_vector(15 downto 0); -- memory.mem_a
- mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
- mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
- mem_cke : out std_logic; -- .mem_cke
- mem_cs_n : out std_logic; -- .mem_cs_n
- mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
- mem_ras_n : out std_logic; -- .mem_ras_n
- mem_cas_n : out std_logic; -- .mem_cas_n
- mem_we_n : out std_logic; -- .mem_we_n
- mem_reset_n : out std_logic; -- .mem_reset_n
- mem_dq : inout std_logic_vector(63 downto 0); -- .mem_dq
- mem_dqs : inout std_logic_vector(7 downto 0); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(7 downto 0); -- .mem_dqs_n
- mem_odt : out std_logic; -- .mem_odt
- avl_ready : out std_logic; -- avl.waitrequest_n
- avl_burstbegin : in std_logic; -- .beginbursttransfer
- avl_addr : in std_logic_vector(26 downto 0); -- .address
- avl_rdata_valid : out std_logic; -- .readdatavalid
- avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
- avl_wdata : in std_logic_vector(255 downto 0); -- .writedata
- avl_be : in std_logic_vector(31 downto 0); -- .byteenable
- avl_read_req : in std_logic; -- .read
- avl_write_req : in std_logic; -- .write
- avl_size : in std_logic_vector(6 downto 0); -- .burstcount
- local_init_done : out std_logic; -- status.local_init_done
- local_cal_success : out std_logic; -- .local_cal_success
- local_cal_fail : out std_logic; -- .local_cal_fail
- seriesterminationcontrol : in std_logic_vector(13 downto 0); -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol : in std_logic_vector(13 downto 0); -- .parallelterminationcontrol
- pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
- pll_write_clk : out std_logic; -- .pll_write_clk
- pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
- pll_locked : out std_logic; -- .pll_locked
- pll_avl_clk : out std_logic; -- .pll_avl_clk
- pll_config_clk : out std_logic; -- .pll_config_clk
- dll_delayctrl : out std_logic_vector(5 downto 0) -- dll_sharing.dll_delayctrl
+ -- pll_ref_clk.clk
+ pll_ref_clk : in std_logic;
+ -- global_reset.reset_n
+ global_reset_n : in std_logic;
+ -- soft_reset.reset_n
+ soft_reset_n : in std_logic;
+ -- afi_clk_in.clk
+ afi_clk : out std_logic;
+ -- afi_half_clk_in.clk
+ afi_half_clk : out std_logic;
+ -- afi_reset_in.reset_n
+ afi_reset_n : out std_logic;
+ -- memory.mem_a
+ mem_a : out std_logic_vector(15 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(2 downto 0);
+ -- .mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic;
+ -- .mem_cs_n
+ mem_cs_n : out std_logic;
+ -- .mem_dm
+ mem_dm : out std_logic_vector(7 downto 0);
+ -- .mem_ras_n
+ mem_ras_n : out std_logic;
+ -- .mem_cas_n
+ mem_cas_n : out std_logic;
+ -- .mem_we_n
+ mem_we_n : out std_logic;
+ -- .mem_reset_n
+ mem_reset_n : out std_logic;
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(63 downto 0);
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(7 downto 0);
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(7 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic;
+ -- avl.waitrequest_n
+ avl_ready : out std_logic;
+ -- .beginbursttransfer
+ avl_burstbegin : in std_logic;
+ -- .address
+ avl_addr : in std_logic_vector(26 downto 0);
+ -- .readdatavalid
+ avl_rdata_valid : out std_logic;
+ -- .readdata
+ avl_rdata : out std_logic_vector(255 downto 0);
+ -- .writedata
+ avl_wdata : in std_logic_vector(255 downto 0);
+ -- .byteenable
+ avl_be : in std_logic_vector(31 downto 0);
+ -- .read
+ avl_read_req : in std_logic;
+ -- .write
+ avl_write_req : in std_logic;
+ -- .burstcount
+ avl_size : in std_logic_vector(6 downto 0);
+ -- status.local_init_done
+ local_init_done : out std_logic;
+ -- .local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic;
+ -- oct_sharing.seriesterminationcontrol
+ seriesterminationcontrol : in std_logic_vector(13 downto 0);
+ -- .parallelterminationcontrol
+ parallelterminationcontrol : in std_logic_vector(13 downto 0);
+ -- pll_sharing.pll_mem_clk
+ pll_mem_clk : out std_logic;
+ -- .pll_write_clk
+ pll_write_clk : out std_logic;
+ -- .pll_write_clk_pre_phy_clk
+ pll_write_clk_pre_phy_clk : out std_logic;
+ -- .pll_addr_cmd_clk
+ pll_addr_cmd_clk : out std_logic;
+ -- .pll_locked
+ pll_locked : out std_logic;
+ -- .pll_avl_clk
+ pll_avl_clk : out std_logic;
+ -- .pll_config_clk
+ pll_config_clk : out std_logic;
+ -- dll_sharing.dll_delayctrl
+ dll_delayctrl : out std_logic_vector(5 downto 0)
);
end component;
-- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
component ip_stratixiv_ddr3_uphy_16g_dual_rank_800 is
port (
- pll_ref_clk : in std_logic; -- pll_ref_clk.clk
- global_reset_n : in std_logic; -- global_reset.reset_n
- soft_reset_n : in std_logic; -- soft_reset.reset_n
- afi_clk : out std_logic; -- afi_clk.clk
- afi_half_clk : out std_logic; -- afi_half_clk.clk
- afi_reset_n : out std_logic; -- afi_reset.reset_n
- mem_a : out std_logic_vector(15 downto 0); -- memory.mem_a
- mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
- mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
- mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
- mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
- mem_ras_n : out std_logic; -- .mem_ras_n
- mem_cas_n : out std_logic; -- .mem_cas_n
- mem_we_n : out std_logic; -- .mem_we_n
- mem_reset_n : out std_logic; -- .mem_reset_n
- mem_dq : inout std_logic_vector(63 downto 0); -- .mem_dq
- mem_dqs : inout std_logic_vector(7 downto 0); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(7 downto 0); -- .mem_dqs_n
- mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
- avl_ready : out std_logic; -- avl.waitrequest_n
- avl_burstbegin : in std_logic; -- .beginbursttransfer
- avl_addr : in std_logic_vector(28 downto 0); -- .address
- avl_rdata_valid : out std_logic; -- .readdatavalid
- avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
- avl_wdata : in std_logic_vector(255 downto 0); -- .writedata
- avl_be : in std_logic_vector(31 downto 0); -- .byteenable
- avl_read_req : in std_logic; -- .read
- avl_write_req : in std_logic; -- .write
- avl_size : in std_logic_vector(6 downto 0); -- .burstcount
- local_init_done : out std_logic; -- status.local_init_done
- local_cal_success : out std_logic; -- .local_cal_success
- local_cal_fail : out std_logic; -- .local_cal_fail
- oct_rdn : in std_logic; -- oct.rdn
- oct_rup : in std_logic; -- .rup
- seriesterminationcontrol : out std_logic_vector(13 downto 0); -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol : out std_logic_vector(13 downto 0); -- .parallelterminationcontrol
- pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
- pll_write_clk : out std_logic; -- .pll_write_clk
- pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
- pll_locked : out std_logic; -- .pll_locked
- pll_avl_clk : out std_logic; -- .pll_avl_clk
- pll_config_clk : out std_logic; -- .pll_config_clk
- dll_delayctrl : out std_logic_vector(5 downto 0) -- dll_sharing.dll_delayctrl
+ -- pll_ref_clk.clk
+ pll_ref_clk : in std_logic;
+ -- global_reset.reset_n
+ global_reset_n : in std_logic;
+ -- soft_reset.reset_n
+ soft_reset_n : in std_logic;
+ -- afi_clk.clk
+ afi_clk : out std_logic;
+ -- afi_half_clk.clk
+ afi_half_clk : out std_logic;
+ -- afi_reset.reset_n
+ afi_reset_n : out std_logic;
+ -- memory.mem_a
+ mem_a : out std_logic_vector(15 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(2 downto 0);
+ -- .mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- .mem_dm
+ mem_dm : out std_logic_vector(7 downto 0);
+ -- .mem_ras_n
+ mem_ras_n : out std_logic;
+ -- .mem_cas_n
+ mem_cas_n : out std_logic;
+ -- .mem_we_n
+ mem_we_n : out std_logic;
+ -- .mem_reset_n
+ mem_reset_n : out std_logic;
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(63 downto 0);
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(7 downto 0);
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(7 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- avl.waitrequest_n
+ avl_ready : out std_logic;
+ -- .beginbursttransfer
+ avl_burstbegin : in std_logic;
+ -- .address
+ avl_addr : in std_logic_vector(28 downto 0);
+ -- .readdatavalid
+ avl_rdata_valid : out std_logic;
+ -- .readdata
+ avl_rdata : out std_logic_vector(255 downto 0);
+ -- .writedata
+ avl_wdata : in std_logic_vector(255 downto 0);
+ -- .byteenable
+ avl_be : in std_logic_vector(31 downto 0);
+ -- .read
+ avl_read_req : in std_logic;
+ -- .write
+ avl_write_req : in std_logic;
+ -- .burstcount
+ avl_size : in std_logic_vector(6 downto 0);
+ -- status.local_init_done
+ local_init_done : out std_logic;
+ -- .local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic;
+ -- oct.rdn
+ oct_rdn : in std_logic;
+ -- .rup
+ oct_rup : in std_logic;
+ -- oct_sharing.seriesterminationcontrol
+ seriesterminationcontrol : out std_logic_vector(13 downto 0);
+ -- .parallelterminationcontrol
+ parallelterminationcontrol : out std_logic_vector(13 downto 0);
+ -- pll_sharing.pll_mem_clk
+ pll_mem_clk : out std_logic;
+ -- .pll_write_clk
+ pll_write_clk : out std_logic;
+ -- .pll_write_clk_pre_phy_clk
+ pll_write_clk_pre_phy_clk : out std_logic;
+ -- .pll_addr_cmd_clk
+ pll_addr_cmd_clk : out std_logic;
+ -- .pll_locked
+ pll_locked : out std_logic;
+ -- .pll_avl_clk
+ pll_avl_clk : out std_logic;
+ -- .pll_config_clk
+ pll_config_clk : out std_logic;
+ -- dll_sharing.dll_delayctrl
+ dll_delayctrl : out std_logic_vector(5 downto 0)
);
end component;
@@ -295,76 +521,140 @@ package tech_ddr_component_pkg is
-- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_1600.vhd
component ip_arria10_ddr4_4g_1600 is
port (
- amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 : in std_logic := '0'; -- .read
- amm_write_0 : in std_logic := '0'; -- .write
- amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
- amm_readdatavalid_0 : out std_logic; -- .readdatavalid
- emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
- global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
- mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
- mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- .mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
- mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
- mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- .mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
- oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
- local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
- local_cal_fail : out std_logic -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- .read
+ amm_read_0 : in std_logic := '0';
+ -- .write
+ amm_write_0 : in std_logic := '0';
+ -- .address
+ amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0');
+ -- .readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- .writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0');
+ -- .burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0');
+ -- .byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0');
+ -- .readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk : out std_logic;
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n : out std_logic;
+ -- global_reset_reset_sink.reset_n
+ global_reset_n : in std_logic := '0';
+ -- mem_conduit_end.mem_ck
+ mem_ck : out std_logic_vector(0 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(0 downto 0);
+ -- .mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- .mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- .mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(0 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(0 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(0 downto 0);
+ -- .mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- .mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- .mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0');
+ -- .mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin : in std_logic := '0';
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk : in std_logic := '0';
+ -- status_conduit_end.local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic
);
end component;
-- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_2000.vhd
component ip_arria10_ddr4_4g_2000 is
port (
- amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 : in std_logic := '0'; -- .read
- amm_write_0 : in std_logic := '0'; -- .write
- amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
- amm_readdatavalid_0 : out std_logic; -- .readdatavalid
- emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
- global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
- mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
- mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- .mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
- mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
- mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- .mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
- oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
- local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
- local_cal_fail : out std_logic -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- .read
+ amm_read_0 : in std_logic := '0';
+ -- .write
+ amm_write_0 : in std_logic := '0';
+ -- .address
+ amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0');
+ -- .readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- .writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0');
+ -- .burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0');
+ -- .byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0');
+ -- .readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk : out std_logic;
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n : out std_logic;
+ -- global_reset_reset_sink.reset_n
+ global_reset_n : in std_logic := '0';
+ -- mem_conduit_end.mem_ck
+ mem_ck : out std_logic_vector(0 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(0 downto 0);
+ -- .mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- .mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- .mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(0 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(0 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(0 downto 0);
+ -- .mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- .mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- .mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0');
+ -- .mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin : in std_logic := '0';
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk : in std_logic := '0';
+ -- status_conduit_end.local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic
);
end component;
@@ -375,114 +665,210 @@ package tech_ddr_component_pkg is
-- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
component ip_arria10_e3sge3_ddr4_4g_1600 is
port (
- amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 : in std_logic := '0'; -- .read
- amm_write_0 : in std_logic := '0'; -- .write
- amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
- amm_readdatavalid_0 : out std_logic; -- .readdatavalid
- emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
- global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
- mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
- mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- .mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
- mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
- mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- .mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
- oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
- local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
- local_cal_fail : out std_logic -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- .read
+ amm_read_0 : in std_logic := '0';
+ -- .write
+ amm_write_0 : in std_logic := '0';
+ -- .address
+ amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0');
+ -- .readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- .writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0');
+ -- .burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0');
+ -- .byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0');
+ -- .readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk : out std_logic;
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n : out std_logic;
+ -- global_reset_reset_sink.reset_n
+ global_reset_n : in std_logic := '0';
+ -- mem_conduit_end.mem_ck
+ mem_ck : out std_logic_vector(0 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(0 downto 0);
+ -- .mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- .mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- .mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(0 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(0 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(0 downto 0);
+ -- .mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- .mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- .mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0');
+ -- .mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin : in std_logic := '0';
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk : in std_logic := '0';
+ -- status_conduit_end.local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic
);
end component;
-- Dual rank version of ip_arria10_e3sge3_ddr4_4g_1600.vhd
component ip_arria10_e3sge3_ddr4_8g_1600 is
port (
- amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 : in std_logic := '0'; -- .read
- amm_write_0 : in std_logic := '0'; -- .write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0'); -- .address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
- amm_readdatavalid_0 : out std_logic; -- .readdatavalid
- emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
- global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_conduit_end.mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- .mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- .mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
- oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
- local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
- local_cal_fail : out std_logic -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- .read
+ amm_read_0 : in std_logic := '0';
+ -- .write
+ amm_write_0 : in std_logic := '0';
+ -- .address
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0');
+ -- .readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- .writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0');
+ -- .burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0');
+ -- .byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0');
+ -- .readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk : out std_logic;
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n : out std_logic;
+ -- global_reset_reset_sink.reset_n
+ global_reset_n : in std_logic := '0';
+ -- mem_conduit_end.mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- .mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- .mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- .mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- .mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- .mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- .mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0');
+ -- .mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin : in std_logic := '0';
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk : in std_logic := '0';
+ -- status_conduit_end.local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic
);
end component;
-- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
component ip_arria10_e3sge3_ddr4_4g_2000 is
port (
- amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 : in std_logic := '0'; -- .read
- amm_write_0 : in std_logic := '0'; -- .write
- amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
- amm_readdatavalid_0 : out std_logic; -- .readdatavalid
- emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
- global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
- mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
- mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- .mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
- mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
- mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- .mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
- oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
- local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
- local_cal_fail : out std_logic -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- .read
+ amm_read_0 : in std_logic := '0';
+ -- .write
+ amm_write_0 : in std_logic := '0';
+ -- .address
+ amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0');
+ -- .readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- .writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0');
+ -- .burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0');
+ -- .byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0');
+ -- .readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk : out std_logic;
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n : out std_logic;
+ -- global_reset_reset_sink.reset_n
+ global_reset_n : in std_logic := '0';
+ -- mem_conduit_end.mem_ck
+ mem_ck : out std_logic_vector(0 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(0 downto 0);
+ -- .mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- .mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- .mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(0 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(0 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(0 downto 0);
+ -- .mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- .mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- .mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0');
+ -- .mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin : in std_logic := '0';
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk : in std_logic := '0';
+ -- status_conduit_end.local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic
);
end component;
@@ -493,300 +879,556 @@ package tech_ddr_component_pkg is
-- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
component ip_arria10_e1sg_ddr4_4g_1600 is
port (
- amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 : in std_logic := '0'; -- .read
- amm_write_0 : in std_logic := '0'; -- .write
- amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
- amm_readdatavalid_0 : out std_logic; -- .readdatavalid
- emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
- global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
- mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
- mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- .mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
- mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
- mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- .mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
- oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
- local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
- local_cal_fail : out std_logic -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- .read
+ amm_read_0 : in std_logic := '0';
+ -- .write
+ amm_write_0 : in std_logic := '0';
+ -- .address
+ amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0');
+ -- .readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- .writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0');
+ -- .burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0');
+ -- .byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0');
+ -- .readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk : out std_logic;
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n : out std_logic;
+ -- global_reset_reset_sink.reset_n
+ global_reset_n : in std_logic := '0';
+ -- mem_conduit_end.mem_ck
+ mem_ck : out std_logic_vector(0 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(0 downto 0);
+ -- .mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- .mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- .mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(0 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(0 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(0 downto 0);
+ -- .mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- .mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- .mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0');
+ -- .mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin : in std_logic := '0';
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk : in std_logic := '0';
+ -- status_conduit_end.local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic
);
end component;
-- Dual rank version of ip_arria10_e1sg_ddr4_4g_1600.vhd
component ip_arria10_e1sg_ddr4_8g_1600 is
port (
- amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 : in std_logic := '0'; -- .read
- amm_write_0 : in std_logic := '0'; -- .write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0'); -- .address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
- amm_readdatavalid_0 : out std_logic; -- .readdatavalid
- emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
- global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_conduit_end.mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- .mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- .mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
- oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
- local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
- local_cal_fail : out std_logic -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- .read
+ amm_read_0 : in std_logic := '0';
+ -- .write
+ amm_write_0 : in std_logic := '0';
+ -- .address
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0');
+ -- .readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- .writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0');
+ -- .burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0');
+ -- .byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0');
+ -- .readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk : out std_logic;
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n : out std_logic;
+ -- global_reset_reset_sink.reset_n
+ global_reset_n : in std_logic := '0';
+ -- mem_conduit_end.mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- .mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- .mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- .mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- .mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- .mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- .mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0');
+ -- .mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin : in std_logic := '0';
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk : in std_logic := '0';
+ -- status_conduit_end.local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic
);
end component;
component ip_arria10_e1sg_ddr4_16g_1600 is
port (
- amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 : in std_logic := '0'; -- .read
- amm_write_0 : in std_logic := '0'; -- .write
- amm_address_0 : in std_logic_vector(27 downto 0) := (others => '0'); -- .address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
- amm_readdatavalid_0 : out std_logic; -- .readdatavalid
- emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
- global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_conduit_end.mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- .mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- .mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
- oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
- local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
- local_cal_fail : out std_logic -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- .read
+ amm_read_0 : in std_logic := '0';
+ -- .write
+ amm_write_0 : in std_logic := '0';
+ -- .address
+ amm_address_0 : in std_logic_vector(27 downto 0) := (others => '0');
+ -- .readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- .writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0');
+ -- .burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0');
+ -- .byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0');
+ -- .readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk : out std_logic;
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n : out std_logic;
+ -- global_reset_reset_sink.reset_n
+ global_reset_n : in std_logic := '0';
+ -- mem_conduit_end.mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- .mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- .mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- .mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- .mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- .mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- .mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0');
+ -- .mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin : in std_logic := '0';
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk : in std_logic := '0';
+ -- status_conduit_end.local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic
);
end component;
-- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
component ip_arria10_e1sg_ddr4_4g_2000 is
port (
- amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 : in std_logic := '0'; -- .read
- amm_write_0 : in std_logic := '0'; -- .write
- amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
- amm_readdatavalid_0 : out std_logic; -- .readdatavalid
- emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
- global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
- mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
- mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- .mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
- mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
- mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- .mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
- oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
- local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
- local_cal_fail : out std_logic -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- .read
+ amm_read_0 : in std_logic := '0';
+ -- .write
+ amm_write_0 : in std_logic := '0';
+ -- .address
+ amm_address_0 : in std_logic_vector(25 downto 0) := (others => '0');
+ -- .readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- .writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0');
+ -- .burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0');
+ -- .byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0');
+ -- .readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk : out std_logic;
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n : out std_logic;
+ -- global_reset_reset_sink.reset_n
+ global_reset_n : in std_logic := '0';
+ -- mem_conduit_end.mem_ck
+ mem_ck : out std_logic_vector(0 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(0 downto 0);
+ -- .mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- .mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- .mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(0 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(0 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(0 downto 0);
+ -- .mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- .mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- .mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0');
+ -- .mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin : in std_logic := '0';
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk : in std_logic := '0';
+ -- status_conduit_end.local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic
);
end component;
-- Dual rank version for e2sg
component ip_arria10_e2sg_ddr4_8g_1600 is
port (
- amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 : in std_logic := '0'; -- .read
- amm_write_0 : in std_logic := '0'; -- .write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0'); -- .address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
- amm_readdatavalid_0 : out std_logic; -- .readdatavalid
- emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
- global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_conduit_end.mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- .mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- .mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
- oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
- local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
- local_cal_fail : out std_logic -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- .read
+ amm_read_0 : in std_logic := '0';
+ -- .write
+ amm_write_0 : in std_logic := '0';
+ -- .address
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0');
+ -- .readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- .writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0');
+ -- .burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0');
+ -- .byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0');
+ -- .readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk : out std_logic;
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n : out std_logic;
+ -- global_reset_reset_sink.reset_n
+ global_reset_n : in std_logic := '0';
+ -- mem_conduit_end.mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- .mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- .mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- .mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- .mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- .mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- .mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0');
+ -- .mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin : in std_logic := '0';
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk : in std_logic := '0';
+ -- status_conduit_end.local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic
);
end component;
component ip_arria10_e2sg_ddr4_8g_2400 is
port (
- amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 : in std_logic := '0'; -- .read
- amm_write_0 : in std_logic := '0'; -- .write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0'); -- .address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
- amm_readdatavalid_0 : out std_logic; -- .readdatavalid
- emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
- global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_conduit_end.mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- .mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- .mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
- oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
- local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
- local_cal_fail : out std_logic -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- .read
+ amm_read_0 : in std_logic := '0';
+ -- .write
+ amm_write_0 : in std_logic := '0';
+ -- .address
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0');
+ -- .readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- .writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0');
+ -- .burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0');
+ -- .byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0');
+ -- .readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk : out std_logic;
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n : out std_logic;
+ -- global_reset_reset_sink.reset_n
+ global_reset_n : in std_logic := '0';
+ -- mem_conduit_end.mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- .mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- .mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- .mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- .mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- .mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- .mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0');
+ -- .mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin : in std_logic := '0';
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk : in std_logic := '0';
+ -- status_conduit_end.local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic
);
end component;
component ip_arria10_e2sg_ddr4_16g_1600_64b is
port (
- amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 : in std_logic := '0'; -- .read
- amm_write_0 : in std_logic := '0'; -- .write
- amm_address_0 : in std_logic_vector(27 downto 0) := (others => '0'); -- .address
- amm_readdata_0 : out std_logic_vector(511 downto 0); -- .readdata
- amm_writedata_0 : in std_logic_vector(511 downto 0) := (others => '0'); -- .writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
- amm_byteenable_0 : in std_logic_vector(63 downto 0) := (others => '0'); -- .byteenable
- amm_readdatavalid_0 : out std_logic; -- .readdatavalid
- emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
- global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
- mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
- mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- .mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
- mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
- mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- .mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dbi_n
- oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
- local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
- local_cal_fail : out std_logic -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- .read
+ amm_read_0 : in std_logic := '0';
+ -- .write
+ amm_write_0 : in std_logic := '0';
+ -- .address
+ amm_address_0 : in std_logic_vector(27 downto 0) := (others => '0');
+ -- .readdata
+ amm_readdata_0 : out std_logic_vector(511 downto 0);
+ -- .writedata
+ amm_writedata_0 : in std_logic_vector(511 downto 0) := (others => '0');
+ -- .burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0');
+ -- .byteenable
+ amm_byteenable_0 : in std_logic_vector(63 downto 0) := (others => '0');
+ -- .readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk : out std_logic;
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n : out std_logic;
+ -- global_reset_reset_sink.reset_n
+ global_reset_n : in std_logic := '0';
+ -- mem_conduit_end.mem_ck
+ mem_ck : out std_logic_vector(0 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(0 downto 0);
+ -- .mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- .mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- .mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(0 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(0 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(0 downto 0);
+ -- .mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- .mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- .mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0');
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0');
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(63 downto 0) := (others => '0');
+ -- .mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(7 downto 0) := (others => '0');
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin : in std_logic := '0';
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk : in std_logic := '0';
+ -- status_conduit_end.local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic
);
end component;
component ip_arria10_e2sg_ddr4_16g_1600_72b is
port (
- amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 : in std_logic := '0'; -- .read
- amm_write_0 : in std_logic := '0'; -- .write
- amm_address_0 : in std_logic_vector(27 downto 0) := (others => '0'); -- .address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
- amm_readdatavalid_0 : out std_logic; -- .readdatavalid
- emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
- global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
- mem_ck : out std_logic_vector(0 downto 0); -- mem_conduit_end.mem_ck
- mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- .mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
- mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
- mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
- mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- .mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
- oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
- local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
- local_cal_fail : out std_logic -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- .read
+ amm_read_0 : in std_logic := '0';
+ -- .write
+ amm_write_0 : in std_logic := '0';
+ -- .address
+ amm_address_0 : in std_logic_vector(27 downto 0) := (others => '0');
+ -- .readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- .writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0');
+ -- .burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0');
+ -- .byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0');
+ -- .readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk : out std_logic;
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n : out std_logic;
+ -- global_reset_reset_sink.reset_n
+ global_reset_n : in std_logic := '0';
+ -- mem_conduit_end.mem_ck
+ mem_ck : out std_logic_vector(0 downto 0);
+ -- .mem_ck_n
+ mem_ck_n : out std_logic_vector(0 downto 0);
+ -- .mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- .mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- .mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- .mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- .mem_cke
+ mem_cke : out std_logic_vector(0 downto 0);
+ -- .mem_cs_n
+ mem_cs_n : out std_logic_vector(0 downto 0);
+ -- .mem_odt
+ mem_odt : out std_logic_vector(0 downto 0);
+ -- .mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- .mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- .mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0');
+ -- .mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin : in std_logic := '0';
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk : in std_logic := '0';
+ -- status_conduit_end.local_cal_success
+ local_cal_success : out std_logic;
+ -- .local_cal_fail
+ local_cal_fail : out std_logic
);
end component;
diff --git a/libraries/technology/ddr/tech_ddr_mem_model.vhd b/libraries/technology/ddr/tech_ddr_mem_model.vhd
index dcdb187b78702ac100ebc6c233ac2b8e71ddddea..0585c512522c84b0d0d16dcce9648014053cb58b 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model.vhd
@@ -71,7 +71,8 @@ begin
MEM_IF_ROW_ADDR_WIDTH => g_tech_ddr.a_row_w,
MEM_IF_COL_ADDR_WIDTH => g_tech_ddr.a_col_w,
MEM_IF_CS_WIDTH => g_tech_ddr.cs_w,
- MEM_IF_CONTROL_WIDTH => 1, -- cas_n, ras_n, we_n
+ -- cas_n, ras_n, we_n
+ MEM_IF_CONTROL_WIDTH => 1,
MEM_IF_ODT_WIDTH => g_tech_ddr.odt_w,
DEVICE_DEPTH => 1,
DEVICE_WIDTH => 1,
@@ -91,43 +92,73 @@ begin
MEM_VERBOSE => 1
)
port map (
- mem_a => mem3_in.a(g_tech_ddr.a_w - 1 downto 0), -- MEM_IF_ADDR_WIDTH
- mem_ba => mem3_in.ba(g_tech_ddr.ba_w - 1 downto 0), -- MEM_IF_BANKADDR_WIDTH
- mem_ck => mem3_in.ck(g_tech_ddr.ck_w - 1 downto 0), -- MEM_IF_CK_WIDTH
- mem_ck_n => mem3_in.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- MEM_IF_CK_WIDTH
- mem_cke => mem3_in.cke(g_tech_ddr.cke_w - 1 downto 0), -- MEM_IF_CLK_EN_WIDTH
- mem_cs_n => mem3_in.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- MEM_IF_CS_WIDTH
- mem_ras_n => slv(mem3_in.ras_n), -- MEM_IF_CONTROL_WIDTH
- mem_cas_n => slv(mem3_in.cas_n), -- MEM_IF_CONTROL_WIDTH
- mem_we_n => slv(mem3_in.we_n), -- MEM_IF_CONTROL_WIDTH
+ -- MEM_IF_ADDR_WIDTH
+ mem_a => mem3_in.a(g_tech_ddr.a_w - 1 downto 0),
+ -- MEM_IF_BANKADDR_WIDTH
+ mem_ba => mem3_in.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- MEM_IF_CK_WIDTH
+ mem_ck => mem3_in.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- MEM_IF_CK_WIDTH
+ mem_ck_n => mem3_in.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- MEM_IF_CLK_EN_WIDTH
+ mem_cke => mem3_in.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- MEM_IF_CS_WIDTH
+ mem_cs_n => mem3_in.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- MEM_IF_CONTROL_WIDTH
+ mem_ras_n => slv(mem3_in.ras_n),
+ -- MEM_IF_CONTROL_WIDTH
+ mem_cas_n => slv(mem3_in.cas_n),
+ -- MEM_IF_CONTROL_WIDTH
+ mem_we_n => slv(mem3_in.we_n),
mem_reset_n => mem3_in.reset_n,
- mem_dm => mem3_in.dm(g_tech_ddr.dqs_w - 1 downto 0), -- MEM_IF_DQS_WIDTH
- mem_dq => mem3_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- MEM_IF_DQ_WIDTH
- mem_dqs => mem3_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- MEM_IF_DQS_WIDTH
- mem_dqs_n => mem3_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- MEM_IF_DQS_WIDTH
- mem_odt => mem3_in.odt(g_tech_ddr.odt_w - 1 downto 0) -- MEM_IF_ODT_WIDTH
+ -- MEM_IF_DQS_WIDTH
+ mem_dm => mem3_in.dm(g_tech_ddr.dqs_w - 1 downto 0),
+ -- MEM_IF_DQ_WIDTH
+ mem_dq => mem3_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- MEM_IF_DQS_WIDTH
+ mem_dqs => mem3_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- MEM_IF_DQS_WIDTH
+ mem_dqs_n => mem3_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- MEM_IF_ODT_WIDTH
+ mem_odt => mem3_in.odt(g_tech_ddr.odt_w - 1 downto 0)
);
end generate;
gen_ip_arria10_ddr_memory_model : if g_tech_ddr.name = "DDR4" and c_gigabytes = 4 generate
u_ip_arria10_ddr_memory_model : ed_sim_altera_emif_mem_model_141_z3tvrmq
port map (
- mem_ck => mem4_in.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => mem4_in.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => mem4_in.a(g_tech_ddr.a_w - 1 downto 0), -- .mem_a
- mem_act_n => slv(mem4_in.act_n), -- .mem_act_n
- mem_ba => mem4_in.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => mem4_in.bg(g_tech_ddr.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => mem4_in.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => mem4_in.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => mem4_in.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- mem_reset_n => slv(mem4_in.reset_n), -- .mem_reset_n
- mem_par => slv(mem4_in.par), -- .mem_par
- sl(mem_alert_n) => mem4_ou.alert_n, -- .mem_alert_n
- mem_dqs => mem4_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => mem4_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => mem4_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => mem4_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0) -- .mem_dbi_n
+ -- mem_conduit_end.mem_ck
+ mem_ck => mem4_in.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => mem4_in.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_a
+ mem_a => mem4_in.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_act_n
+ mem_act_n => slv(mem4_in.act_n),
+ -- .mem_ba
+ mem_ba => mem4_in.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_bg
+ mem_bg => mem4_in.bg(g_tech_ddr.bg_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => mem4_in.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => mem4_in.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => mem4_in.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- .mem_reset_n
+ mem_reset_n => slv(mem4_in.reset_n),
+ -- .mem_par
+ mem_par => slv(mem4_in.par),
+ -- .mem_alert_n
+ sl(mem_alert_n) => mem4_ou.alert_n,
+ -- .mem_dqs
+ mem_dqs => mem4_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => mem4_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dq
+ mem_dq => mem4_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dbi_n
+ mem_dbi_n => mem4_io.dbi_n(g_tech_ddr.dbi_w - 1 downto 0)
);
end generate;
diff --git a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
index 65a8e2493f0a0351fde3803f1cfe973e43c56c9b..e8a07909282e8aedb95c2c7ad89bc549a83e38c4 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
@@ -88,22 +88,38 @@ package tech_ddr_mem_model_component_pkg is
-- $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/sim
component ed_sim_altera_emif_mem_model_141_z3tvrmq is
port (
- mem_ck : in std_logic_vector(0 downto 0) := (others => '0'); -- mem_conduit_end.mem_ck
- mem_ck_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_ck_n
- mem_a : in std_logic_vector(16 downto 0) := (others => '0'); -- .mem_a
- mem_act_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_act_n
- mem_ba : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_ba
- mem_bg : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_bg
- mem_cke : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_cke
- mem_cs_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_cs_n
- mem_odt : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_odt
- mem_reset_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_reset_n
- mem_par : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_par
- mem_alert_n : out std_logic_vector(0 downto 0); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0') -- .mem_dbi_n
+ -- mem_conduit_end.mem_ck
+ mem_ck : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_ck_n
+ mem_ck_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_a
+ mem_a : in std_logic_vector(16 downto 0) := (others => '0');
+ -- .mem_act_n
+ mem_act_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_ba
+ mem_ba : in std_logic_vector(1 downto 0) := (others => '0');
+ -- .mem_bg
+ mem_bg : in std_logic_vector(1 downto 0) := (others => '0');
+ -- .mem_cke
+ mem_cke : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_cs_n
+ mem_cs_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_odt
+ mem_odt : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_reset_n
+ mem_reset_n : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_par
+ mem_par : in std_logic_vector(0 downto 0) := (others => '0');
+ -- .mem_alert_n
+ mem_alert_n : out std_logic_vector(0 downto 0);
+ -- .mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0');
+ -- .mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0');
+ -- .mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0')
);
end component ed_sim_altera_emif_mem_model_141_z3tvrmq;
diff --git a/libraries/technology/ddr/tech_ddr_pkg.vhd b/libraries/technology/ddr/tech_ddr_pkg.vhd
index 8dd9f402e491b7f46abe85d2ab5bbd657fd64677..fe4b77e02341840b5e76570cbe3ef84eb1e6847c 100644
--- a/libraries/technology/ddr/tech_ddr_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_pkg.vhd
@@ -29,43 +29,74 @@ package tech_ddr_pkg is
-- Gather all DDR parameters in one record
type t_c_tech_ddr is record
-- PHY variant within a technology
- name : string(1 to 4); -- = "DDR3" or "DDR4"
- mts : natural; -- = 800 access rate in mega transfers per second
- master : boolean; -- = TRUE TRUE = uniphy master, FALSE = uniphy slave regarding OCT and terminationcontrol for DDR3
- rank : string(1 to 6); -- = "SINGLE" or "DUAL "
+ -- = "DDR3" or "DDR4"
+ name : string(1 to 4);
+ -- = 800 access rate in mega transfers per second
+ mts : natural;
+ -- = TRUE TRUE = uniphy master, FALSE = uniphy slave regarding OCT and terminationcontrol for DDR3
+ master : boolean;
+ -- = "SINGLE" or "DUAL "
+ rank : string(1 to 6);
-- PHY external FPGA IO
- a_w : natural; -- = 16
- a_row_w : natural; -- = 16 = a_w, row address width, via a_w lines
- a_col_w : natural; -- = 10 <= a_w, col address width, via a_w lines
- ba_w : natural; -- = 3
- dq_w : natural; -- = 64
- dqs_w : natural; -- = 8 = dq_w / nof_dq_per_dqs
- dm_w : natural; -- = 8
- dbi_w : natural; -- = 8
- bg_w : natural; -- = 2
- ck_w : natural; -- = 2
- cke_w : natural; -- = 2
- cs_w : natural; -- = 2 = number of chip select lines
- cs_w_w : natural; -- = 1 = true_log2(cs_w), use when the number of chip select lines is converted to a logical address
- odt_w : natural; -- = 2
+ -- = 16
+ a_w : natural;
+ -- = 16 = a_w, row address width, via a_w lines
+ a_row_w : natural;
+ -- = 10 <= a_w, col address width, via a_w lines
+ a_col_w : natural;
+ -- = 3
+ ba_w : natural;
+ -- = 64
+ dq_w : natural;
+ -- = 8 = dq_w / nof_dq_per_dqs
+ dqs_w : natural;
+ -- = 8
+ dm_w : natural;
+ -- = 8
+ dbi_w : natural;
+ -- = 2
+ bg_w : natural;
+ -- = 2
+ ck_w : natural;
+ -- = 2
+ cke_w : natural;
+ -- = 2 = number of chip select lines
+ cs_w : natural;
+ -- = 1 = true_log2(cs_w), use when the number of chip select lines is converted to a logical address
+ cs_w_w : natural;
+ -- = 2
+ odt_w : natural;
-- PHY internal FPGA IO
- terminationcontrol_w : natural; -- = 14 internal bus in FPGA
+ -- = 14 internal bus in FPGA
+ terminationcontrol_w : natural;
-- Controller
- rsl : natural; -- = 4 = 2 (use both PHY clock edges) * 2 (PHY transfer at double rate), resolution
- rsl_w : natural; -- = 2 = ceil_log2(rsl)
- command_queue_depth : natural; -- = 8
- maxburstsize : natural; -- = 64
- maxburstsize_w : natural; -- = 7 = ceil_log2(maxburstsize+1)
- mem_dq_w : natural; -- = 64 dq connected to the memory module, can be = dq_w or 64 whenn dq_w = 72
+ -- = 4 = 2 (use both PHY clock edges) * 2 (PHY transfer at double rate), resolution
+ rsl : natural;
+ -- = 2 = ceil_log2(rsl)
+ rsl_w : natural;
+ -- = 8
+ command_queue_depth : natural;
+ -- = 64
+ maxburstsize : natural;
+ -- = 7 = ceil_log2(maxburstsize+1)
+ maxburstsize_w : natural;
+ -- = 64 dq connected to the memory module, can be = dq_w or 64 whenn dq_w = 72
+ mem_dq_w : natural;
end record;
- function func_tech_sel_ddr(g_technology : natural; g_ddr3, g_ddr4 : t_c_tech_ddr) return t_c_tech_ddr; -- Select DDR3 or DDR4 dependent on the technology
- function func_tech_sel_ddr(g_sel : boolean; a, b : t_c_tech_ddr) return t_c_tech_ddr; -- Select DDR dependent on the boolean
+ -- Select DDR3 or DDR4 dependent on the technology
+ function func_tech_sel_ddr(g_technology : natural; g_ddr3, g_ddr4 : t_c_tech_ddr) return t_c_tech_ddr;
+ -- Select DDR dependent on the boolean
+ function func_tech_sel_ddr(g_sel : boolean; a, b : t_c_tech_ddr) return t_c_tech_ddr;
- function func_tech_ddr_dq_address_w( c_ddr : t_c_tech_ddr) return natural; -- return DDR address width for the DQ data at the PHY mts rate
- function func_tech_ddr_ctlr_address_w(c_ddr : t_c_tech_ddr) return natural; -- return DDR address width for the controller data at the by rsl=4 reduced rate
- function func_tech_ddr_ctlr_data_w( c_ddr : t_c_tech_ddr) return natural; -- return DDR data width for the controller data at the by rsl=4 reduced rate
- function func_tech_ddr_ctlr_ip_data_w(c_ddr : t_c_tech_ddr) return natural; -- return DDR data width for the controller data at the by rsl=4 reduced rate
+ -- return DDR address width for the DQ data at the PHY mts rate
+ function func_tech_ddr_dq_address_w( c_ddr : t_c_tech_ddr) return natural;
+ -- return DDR address width for the controller data at the by rsl=4 reduced rate
+ function func_tech_ddr_ctlr_address_w(c_ddr : t_c_tech_ddr) return natural;
+ -- return DDR data width for the controller data at the by rsl=4 reduced rate
+ function func_tech_ddr_ctlr_data_w( c_ddr : t_c_tech_ddr) return natural;
+ -- return DDR data width for the controller data at the by rsl=4 reduced rate
+ function func_tech_ddr_ctlr_ip_data_w(c_ddr : t_c_tech_ddr) return natural;
-- return DDR module size in log2(number of bytes), because 2**nofbytes_w may not fit in 31 bit NATURAL
function func_tech_ddr_module_nofbytes_w(c_ddr : t_c_tech_ddr) return natural;
@@ -73,19 +104,25 @@ package tech_ddr_pkg is
-- return size as negative value to indicate 2**value fraction of 1GByte which is typical in simulation
function func_tech_ddr_module_gigabytes(c_ddr : t_c_tech_ddr) return integer;
- function func_tech_ddr_sim_size(c_ddr : t_c_tech_ddr; sim_ctrl_addr_w : natural) return t_c_tech_ddr; -- derive sim_ddr from c_ddr (or alternatively use predefined c_tech_ddr*_sim)
+ -- derive sim_ddr from c_ddr (or alternatively use predefined c_tech_ddr*_sim)
+ function func_tech_ddr_sim_size(c_ddr : t_c_tech_ddr; sim_ctrl_addr_w : natural) return t_c_tech_ddr;
function func_tech_ddr_rewire_64b_to_72b(c_ddr : t_c_tech_ddr; vec_64b : std_logic_vector) return std_logic_vector;
function func_tech_ddr_rewire_72b_to_64b(c_ddr : t_c_tech_ddr; vec_72b : std_logic_vector) return std_logic_vector;
-- a a cs cs
-- name mts master rank a row col ba dq dqs dm dbi bg ck cke w w_w odt term rsl rsl_w cqd burst burst_w mem_dq_w
- constant c_tech_ddr3_max : t_c_tech_ddr := ("none", 800, true, "DUAL ", 16, 16, 11, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64); -- maximum ranges for record field definitions
+ -- maximum ranges for record field definitions
+ constant c_tech_ddr3_max : t_c_tech_ddr := ("none", 800, true, "DUAL ", 16, 16, 11, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64);
-- use predefined c_tech_ddr3_sim or derive it using func_tech_ddr_sim_size()
- constant c_tech_ddr3_sim_8k : t_c_tech_ddr := ("DDR3", 800, true, "DUAL ", 10, 1, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
- constant c_tech_ddr3_sim_16k : t_c_tech_ddr := ("DDR3", 800, true, "DUAL ", 10, 2, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
- constant c_tech_ddr3_sim_128k : t_c_tech_ddr := ("DDR3", 800, true, "DUAL ", 10, 5, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
- constant c_tech_ddr3_sim_1m : t_c_tech_ddr := ("DDR3", 800, true, "DUAL ", 10, 8, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
+ -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
+ constant c_tech_ddr3_sim_8k : t_c_tech_ddr := ("DDR3", 800, true, "DUAL ", 10, 1, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64);
+ -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
+ constant c_tech_ddr3_sim_16k : t_c_tech_ddr := ("DDR3", 800, true, "DUAL ", 10, 2, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64);
+ -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
+ constant c_tech_ddr3_sim_128k : t_c_tech_ddr := ("DDR3", 800, true, "DUAL ", 10, 5, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64);
+ -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col - rsl_w)
+ constant c_tech_ddr3_sim_1m : t_c_tech_ddr := ("DDR3", 800, true, "DUAL ", 10, 8, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64);
constant c_tech_ddr3_16g_dual_rank_800m : t_c_tech_ddr := ("DDR3", 800, true, "DUAL ", 16, 16, 11, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64);
constant c_tech_ddr3_4g_800m_master : t_c_tech_ddr := ("DDR3", 800, true, "DUAL ", 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7, 64);
@@ -94,78 +131,128 @@ package tech_ddr_pkg is
constant c_tech_ddr3_4g_single_rank_800m_slave : t_c_tech_ddr := ("DDR3", 800, false, "SINGLE", 16, 16, 10, 3, 64, 8, 8, 0, 0, 2, 1, 1, 0, 1, 14, 4, 2, 4, 64, 7, 64);
--CONSTANT c_tech_ddr4_max : t_c_tech_ddr := ("none", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72); -- maximum ranges for record field definitions
- constant c_tech_ddr4_max : t_c_tech_ddr := ("none", 1600, true, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 2, 2, 2, 1, 2, 0, 8, 3, 8, 64, 7, 72); -- maximum ranges for record field definitions
+ -- maximum ranges for record field definitions
+ constant c_tech_ddr4_max : t_c_tech_ddr := ("none", 1600, true, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 2, 2, 2, 1, 2, 0, 8, 3, 8, 64, 7, 72);
-- use predefined c_tech_ddr4_sim or derive it using func_tech_ddr_sim_size()
- constant c_tech_ddr4_sim_4k : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 10, 1, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
- constant c_tech_ddr4_sim_8k : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 10, 2, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
- constant c_tech_ddr4_sim_16k : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 10, 3, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
- constant c_tech_ddr4_sim_128k : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 10, 6, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
- constant c_tech_ddr4_sim_1m : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 10, 9, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72); -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
+ -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
+ constant c_tech_ddr4_sim_4k : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 10, 1, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72);
+ -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
+ constant c_tech_ddr4_sim_8k : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 10, 2, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72);
+ -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
+ constant c_tech_ddr4_sim_16k : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 10, 3, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72);
+ -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
+ constant c_tech_ddr4_sim_128k : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 10, 6, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72);
+ -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
+ constant c_tech_ddr4_sim_1m : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 10, 9, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72);
constant c_tech_ddr4_4g_1600m : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72);
constant c_tech_ddr4_8g_1600m : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 2, 2, 2, 1, 2, 0, 8, 3, 8, 64, 7, 72);
constant c_tech_ddr4_8g_1600m_64 : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 17, 15, 10, 2, 64, 8, 0, 8, 2, 2, 2, 2, 1, 2, 0, 8, 3, 8, 64, 7, 64);
- constant c_tech_ddr4_16g_1600m_72_64 : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 17, 16, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 1, 1, 0, 8, 3, 8, 64, 7, 64); -- 72b connection from IP, 64b to memory module (used for unb2c slot II with 64 bit modules)
+ -- 72b connection from IP, 64b to memory module (used for unb2c slot II with 64 bit modules)
+ constant c_tech_ddr4_16g_1600m_72_64 : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 17, 16, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 1, 1, 0, 8, 3, 8, 64, 7, 64);
constant c_tech_ddr4_16g_1600m_64 : t_c_tech_ddr := ("DDR4", 1600, true, "DUAL ", 17, 16, 10, 2, 64, 8, 0, 8, 2, 1, 1, 1, 1, 1, 0, 8, 3, 8, 64, 7, 64);
constant c_tech_ddr4_4g_2000m : t_c_tech_ddr := ("DDR4", 2000, true, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7, 72);
constant c_tech_ddr4_8g_2400m : t_c_tech_ddr := ("DDR4", 2400, true, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 2, 2, 2, 1, 2, 0, 8, 3, 8, 64, 7, 72);
-- PHY in, inout and out signal records
- type t_tech_ddr3_phy_in is record -- DDR3 Description
- evt : std_logic; -- event signal is Not Connected to DDR3 PHY
- oct_rup : std_logic; -- only master DDR3 PHY has On Chip Termination OCT inputs
- oct_rdn : std_logic; -- only master DDR3 PHY has On Chip Termination OCT inputs
+ -- DDR3 Description
+ type t_tech_ddr3_phy_in is record
+ -- event signal is Not Connected to DDR3 PHY
+ evt : std_logic;
+ -- only master DDR3 PHY has On Chip Termination OCT inputs
+ oct_rup : std_logic;
+ -- only master DDR3 PHY has On Chip Termination OCT inputs
+ oct_rdn : std_logic;
end record;
- type t_tech_ddr4_phy_in is record -- DDR4 Description
+ -- DDR4 Description
+ type t_tech_ddr4_phy_in is record
--evt : STD_LOGIC; -- event signal
- alert_n : std_logic; -- alert signal
- oct_rzqin : std_logic; -- PHY has On Chip Termination OCT inputs
+ -- alert signal
+ alert_n : std_logic;
+ -- PHY has On Chip Termination OCT inputs
+ oct_rzqin : std_logic;
end record;
- type t_tech_ddr3_phy_io is record -- DDR3 Description
- dq : std_logic_vector(c_tech_ddr3_max.dq_w - 1 downto 0); -- data bus
- dqs : std_logic_vector(c_tech_ddr3_max.dqs_w - 1 downto 0); -- data strobe bus
- dqs_n : std_logic_vector(c_tech_ddr3_max.dqs_w - 1 downto 0); -- data strobe bus negative
- scl : std_logic; -- I2C clock
- sda : std_logic; -- I2C data
+ -- DDR3 Description
+ type t_tech_ddr3_phy_io is record
+ -- data bus
+ dq : std_logic_vector(c_tech_ddr3_max.dq_w - 1 downto 0);
+ -- data strobe bus
+ dqs : std_logic_vector(c_tech_ddr3_max.dqs_w - 1 downto 0);
+ -- data strobe bus negative
+ dqs_n : std_logic_vector(c_tech_ddr3_max.dqs_w - 1 downto 0);
+ -- I2C clock
+ scl : std_logic;
+ -- I2C data
+ sda : std_logic;
end record;
- type t_tech_ddr4_phy_io is record -- DDR4 Description
- dq : std_logic_vector(c_tech_ddr4_max.dq_w - 1 downto 0); -- data bus
- dqs : std_logic_vector(c_tech_ddr4_max.dqs_w - 1 downto 0); -- data strobe bus
- dqs_n : std_logic_vector(c_tech_ddr4_max.dqs_w - 1 downto 0); -- data strobe bus negative
- dbi_n : std_logic_vector(c_tech_ddr4_max.dbi_w - 1 downto 0); -- data bus inversion
+ -- DDR4 Description
+ type t_tech_ddr4_phy_io is record
+ -- data bus
+ dq : std_logic_vector(c_tech_ddr4_max.dq_w - 1 downto 0);
+ -- data strobe bus
+ dqs : std_logic_vector(c_tech_ddr4_max.dqs_w - 1 downto 0);
+ -- data strobe bus negative
+ dqs_n : std_logic_vector(c_tech_ddr4_max.dqs_w - 1 downto 0);
+ -- data bus inversion
+ dbi_n : std_logic_vector(c_tech_ddr4_max.dbi_w - 1 downto 0);
end record;
- type t_tech_ddr3_phy_ou is record -- DDR3 Description
- a : std_logic_vector(c_tech_ddr3_max.a_w - 1 downto 0); -- row and column address
- ba : std_logic_vector(c_tech_ddr3_max.ba_w - 1 downto 0); -- bank address
- dm : std_logic_vector(c_tech_ddr3_max.dm_w - 1 downto 0); -- data mask bus
- ras_n : std_logic; -- row address strobe
- cas_n : std_logic; -- column address strobe
- we_n : std_logic; -- write enable signal
- reset_n : std_logic; -- reset signal
- ck : std_logic_vector(c_tech_ddr3_max.ck_w - 1 downto 0); -- clock, positive edge clock
- ck_n : std_logic_vector(c_tech_ddr3_max.ck_w - 1 downto 0); -- clock, negative edge clock
- cke : std_logic_vector(c_tech_ddr3_max.cke_w - 1 downto 0); -- clock enable
- cs_n : std_logic_vector(c_tech_ddr3_max.cs_w - 1 downto 0); -- chip select
- odt : std_logic_vector(c_tech_ddr3_max.odt_w - 1 downto 0); -- on-die termination control signal
+ -- DDR3 Description
+ type t_tech_ddr3_phy_ou is record
+ -- row and column address
+ a : std_logic_vector(c_tech_ddr3_max.a_w - 1 downto 0);
+ -- bank address
+ ba : std_logic_vector(c_tech_ddr3_max.ba_w - 1 downto 0);
+ -- data mask bus
+ dm : std_logic_vector(c_tech_ddr3_max.dm_w - 1 downto 0);
+ -- row address strobe
+ ras_n : std_logic;
+ -- column address strobe
+ cas_n : std_logic;
+ -- write enable signal
+ we_n : std_logic;
+ -- reset signal
+ reset_n : std_logic;
+ -- clock, positive edge clock
+ ck : std_logic_vector(c_tech_ddr3_max.ck_w - 1 downto 0);
+ -- clock, negative edge clock
+ ck_n : std_logic_vector(c_tech_ddr3_max.ck_w - 1 downto 0);
+ -- clock enable
+ cke : std_logic_vector(c_tech_ddr3_max.cke_w - 1 downto 0);
+ -- chip select
+ cs_n : std_logic_vector(c_tech_ddr3_max.cs_w - 1 downto 0);
+ -- on-die termination control signal
+ odt : std_logic_vector(c_tech_ddr3_max.odt_w - 1 downto 0);
end record;
- type t_tech_ddr4_phy_ou is record -- DDR4 Description
- a : std_logic_vector(c_tech_ddr4_max.a_w - 1 downto 0); -- row and column address (note eg. a[16]=ras_n, a[15]=cas_n, a[14]=we_n)
- ba : std_logic_vector(c_tech_ddr4_max.ba_w - 1 downto 0); -- bank address
- bg : std_logic_vector(c_tech_ddr4_max.bg_w - 1 downto 0); -- bank group
- act_n : std_logic; -- activate signal
- par : std_logic; -- parity signal
- reset_n : std_logic; -- reset signal
- ck : std_logic_vector(c_tech_ddr4_max.ck_w - 1 downto 0); -- clock, positive edge clock
- ck_n : std_logic_vector(c_tech_ddr4_max.ck_w - 1 downto 0); -- clock, negative edge clock
- cke : std_logic_vector(c_tech_ddr4_max.cke_w - 1 downto 0); -- clock enable
- cs_n : std_logic_vector(c_tech_ddr4_max.cs_w - 1 downto 0); -- chip select
- odt : std_logic_vector(c_tech_ddr4_max.odt_w - 1 downto 0); -- on-die termination control signal
+ -- DDR4 Description
+ type t_tech_ddr4_phy_ou is record
+ -- row and column address (note eg. a[16]=ras_n, a[15]=cas_n, a[14]=we_n)
+ a : std_logic_vector(c_tech_ddr4_max.a_w - 1 downto 0);
+ -- bank address
+ ba : std_logic_vector(c_tech_ddr4_max.ba_w - 1 downto 0);
+ -- bank group
+ bg : std_logic_vector(c_tech_ddr4_max.bg_w - 1 downto 0);
+ -- activate signal
+ act_n : std_logic;
+ -- parity signal
+ par : std_logic;
+ -- reset signal
+ reset_n : std_logic;
+ -- clock, positive edge clock
+ ck : std_logic_vector(c_tech_ddr4_max.ck_w - 1 downto 0);
+ -- clock, negative edge clock
+ ck_n : std_logic_vector(c_tech_ddr4_max.ck_w - 1 downto 0);
+ -- clock enable
+ cke : std_logic_vector(c_tech_ddr4_max.cke_w - 1 downto 0);
+ -- chip select
+ cs_n : std_logic_vector(c_tech_ddr4_max.cs_w - 1 downto 0);
+ -- on-die termination control signal
+ odt : std_logic_vector(c_tech_ddr4_max.odt_w - 1 downto 0);
end record;
type t_tech_ddr3_phy_in_arr is array(natural range <>) of t_tech_ddr3_phy_in;
@@ -176,9 +263,12 @@ package tech_ddr_pkg is
type t_tech_ddr4_phy_io_arr is array(natural range <>) of t_tech_ddr4_phy_io;
type t_tech_ddr4_phy_ou_arr is array(natural range <>) of t_tech_ddr4_phy_ou;
- type t_tech_ddr3_phy_terminationcontrol is record -- DDR3 Termination control
- seriesterminationcontrol : std_logic_vector(c_tech_ddr3_max.terminationcontrol_w - 1 downto 0); -- termination control from master to slave DDR3 PHY (internal signal in FPGA)
- parallelterminationcontrol : std_logic_vector(c_tech_ddr3_max.terminationcontrol_w - 1 downto 0); -- termination control from master to slave DDR3 PHY (internal signal in FPGA)
+ -- DDR3 Termination control
+ type t_tech_ddr3_phy_terminationcontrol is record
+ -- termination control from master to slave DDR3 PHY (internal signal in FPGA)
+ seriesterminationcontrol : std_logic_vector(c_tech_ddr3_max.terminationcontrol_w - 1 downto 0);
+ -- termination control from master to slave DDR3 PHY (internal signal in FPGA)
+ parallelterminationcontrol : std_logic_vector(c_tech_ddr3_max.terminationcontrol_w - 1 downto 0);
pll_mem_clk : std_logic;
pll_write_clk : std_logic;
pll_write_clk_pre_phy_clk : std_logic;
@@ -206,11 +296,16 @@ package body tech_ddr_pkg is
function func_tech_sel_ddr(g_technology : natural; g_ddr3, g_ddr4 : t_c_tech_ddr) return t_c_tech_ddr is
begin
case g_technology is
- when c_tech_stratixiv => return g_ddr3; -- unb1
- when c_tech_arria10_proto => return g_ddr4; -- unb2
- when c_tech_arria10_e3sge3 => return g_ddr4; -- unb2
- when c_tech_arria10_e1sg => return g_ddr4; -- unb2b
- when c_tech_arria10_e2sg => return g_ddr4; -- unb2c
+ -- unb1
+ when c_tech_stratixiv => return g_ddr3;
+ -- unb2
+ when c_tech_arria10_proto => return g_ddr4;
+ -- unb2
+ when c_tech_arria10_e3sge3 => return g_ddr4;
+ -- unb2b
+ when c_tech_arria10_e1sg => return g_ddr4;
+ -- unb2c
+ when c_tech_arria10_e2sg => return g_ddr4;
when others => return g_ddr3;
end case;
@@ -223,24 +318,29 @@ package body tech_ddr_pkg is
function func_tech_ddr_dq_address_w(c_ddr : t_c_tech_ddr) return natural is
begin
- if c_ddr.name = "DDR3" then return c_ddr.cs_w_w + c_ddr.ba_w + c_ddr.a_row_w + c_ddr.a_col_w; end if; -- PHY address
- if c_ddr.name = "DDR4" then return c_ddr.cs_w_w + c_ddr.ba_w + c_ddr.a_row_w + c_ddr.a_col_w + c_ddr.bg_w; end if; -- PHY address
+ -- PHY address
+ if c_ddr.name = "DDR3" then return c_ddr.cs_w_w + c_ddr.ba_w + c_ddr.a_row_w + c_ddr.a_col_w; end if;
+ -- PHY address
+ if c_ddr.name = "DDR4" then return c_ddr.cs_w_w + c_ddr.ba_w + c_ddr.a_row_w + c_ddr.a_col_w + c_ddr.bg_w; end if;
end;
function func_tech_ddr_ctlr_address_w(c_ddr : t_c_tech_ddr) return natural is
constant c_dq_address_w : natural := func_tech_ddr_dq_address_w(c_ddr);
begin
- return c_dq_address_w - c_ddr.rsl_w; -- CTLR address
+ -- CTLR address
+ return c_dq_address_w - c_ddr.rsl_w;
end;
function func_tech_ddr_ctlr_data_w(c_ddr : t_c_tech_ddr) return natural is
begin
- return c_ddr.mem_dq_w * c_ddr.rsl; -- CTLR data
+ -- CTLR data
+ return c_ddr.mem_dq_w * c_ddr.rsl;
end;
function func_tech_ddr_ctlr_ip_data_w(c_ddr : t_c_tech_ddr) return natural is
begin
- return c_ddr.dq_w * c_ddr.rsl; -- CTLR data
+ -- CTLR data
+ return c_ddr.dq_w * c_ddr.rsl;
end;
function func_tech_ddr_sim_size(c_ddr : t_c_tech_ddr; sim_ctrl_addr_w : natural) return t_c_tech_ddr is
@@ -258,7 +358,8 @@ package body tech_ddr_pkg is
function func_tech_ddr_module_nofbytes_w(c_ddr : t_c_tech_ddr) return natural is
constant c_dq_address_w : natural := func_tech_ddr_dq_address_w(c_ddr);
- constant c_dq_nof_bytes : natural := 8; -- both dw_q = 64 and 72 are regarded as having 8 bytes (either with 8 or 9 bits per byte)
+ -- both dw_q = 64 and 72 are regarded as having 8 bytes (either with 8 or 9 bits per byte)
+ constant c_dq_nof_bytes : natural := 8;
constant c_dq_nof_bytes_w : natural := ceil_log2(c_dq_nof_bytes);
constant c_module_nof_bytes_w : natural := c_dq_address_w + c_dq_nof_bytes_w;
begin
diff --git a/libraries/technology/ddr/tech_ddr_stratixiv.vhd b/libraries/technology/ddr/tech_ddr_stratixiv.vhd
index b4713542562502c913ebef831a4cc0883e35ecf5..da2360723d085d2e430bb013ae35c1530340ec98 100644
--- a/libraries/technology/ddr/tech_ddr_stratixiv.vhd
+++ b/libraries/technology/ddr/tech_ddr_stratixiv.vhd
@@ -93,154 +93,290 @@ begin
gen_ip_stratixiv_ddr3_uphy_4g_800_master : if g_tech_ddr.name = "DDR3" and c_gigabytes = 4 and g_tech_ddr.mts = 800 and g_tech_ddr.master = true and g_tech_ddr.rank = "DUAL " generate
u_ip_stratixiv_ddr3_uphy_4g_800_master : ip_stratixiv_ddr3_uphy_4g_800_master
port map (
- pll_ref_clk => ref_clk, -- pll_ref_clk.clk
- global_reset_n => ref_rst_n, -- global_reset.reset_n
- soft_reset_n => '1', -- soft_reset.reset_n
- afi_clk => ctlr_gen_clk, -- afi_clk.clk
- afi_half_clk => OPEN, -- afi_half_clk.clk
- afi_reset_n => ctlr_gen_rst_n, -- afi_reset.reset_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- memory.mem_a
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_dm => phy_ou.dm(g_tech_ddr.dm_w - 1 downto 0), -- .mem_dm
- mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
- mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
- mem_we_n => phy_ou.we_n, -- .mem_we_n
- mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- avl_ready => ctlr_miso.waitrequest_n, -- avl.waitrequest_n
- avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
- avl_addr => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- avl_rdata_valid => ctlr_miso.rdval, -- .readdatavalid
- avl_rdata => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0), -- .readdata
- avl_wdata => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0), -- .writedata
- avl_be => (others => '1'), -- .byteenable
- avl_read_req => ctlr_mosi.rd, -- .read
- avl_write_req => ctlr_mosi.wr, -- .write
- avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- local_init_done => ctlr_miso.done, -- status.local_init_done
- local_cal_success => ctlr_miso.cal_ok, -- .local_cal_success
- local_cal_fail => ctlr_miso.cal_fail, -- .local_cal_fail
- oct_rdn => phy_in.oct_rdn, -- oct.rdn
- oct_rup => phy_in.oct_rup, -- .rup
- seriesterminationcontrol => term_ctrl_out.seriesterminationcontrol, -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol => term_ctrl_out.parallelterminationcontrol, -- .parallelterminationcontrol
- pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
- pll_write_clk => OPEN, -- .pll_write_clk
- pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
- pll_locked => OPEN, -- .pll_locked
- pll_avl_clk => OPEN, -- .pll_avl_clk
- pll_config_clk => OPEN, -- .pll_config_clk
- dll_delayctrl => open -- dll_sharing.dll_delayctrl
+ -- pll_ref_clk.clk
+ pll_ref_clk => ref_clk,
+ -- global_reset.reset_n
+ global_reset_n => ref_rst_n,
+ -- soft_reset.reset_n
+ soft_reset_n => '1',
+ -- afi_clk.clk
+ afi_clk => ctlr_gen_clk,
+ -- afi_half_clk.clk
+ afi_half_clk => OPEN,
+ -- afi_reset.reset_n
+ afi_reset_n => ctlr_gen_rst_n,
+ -- memory.mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_dm
+ mem_dm => phy_ou.dm(g_tech_ddr.dm_w - 1 downto 0),
+ -- .mem_ras_n
+ mem_ras_n => phy_ou.ras_n,
+ -- .mem_cas_n
+ mem_cas_n => phy_ou.cas_n,
+ -- .mem_we_n
+ mem_we_n => phy_ou.we_n,
+ -- .mem_reset_n
+ mem_reset_n => phy_ou.reset_n,
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- avl.waitrequest_n
+ avl_ready => ctlr_miso.waitrequest_n,
+ -- .beginbursttransfer
+ avl_burstbegin => ctlr_mosi.burstbegin,
+ -- .address
+ avl_addr => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdatavalid
+ avl_rdata_valid => ctlr_miso.rdval,
+ -- .readdata
+ avl_rdata => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0),
+ -- .writedata
+ avl_wdata => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0),
+ -- .byteenable
+ avl_be => (others => '1'),
+ -- .read
+ avl_read_req => ctlr_mosi.rd,
+ -- .write
+ avl_write_req => ctlr_mosi.wr,
+ -- .burstcount
+ avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- status.local_init_done
+ local_init_done => ctlr_miso.done,
+ -- .local_cal_success
+ local_cal_success => ctlr_miso.cal_ok,
+ -- .local_cal_fail
+ local_cal_fail => ctlr_miso.cal_fail,
+ -- oct.rdn
+ oct_rdn => phy_in.oct_rdn,
+ -- .rup
+ oct_rup => phy_in.oct_rup,
+ -- oct_sharing.seriesterminationcontrol
+ seriesterminationcontrol => term_ctrl_out.seriesterminationcontrol,
+ -- .parallelterminationcontrol
+ parallelterminationcontrol => term_ctrl_out.parallelterminationcontrol,
+ -- pll_sharing.pll_mem_clk
+ pll_mem_clk => i_ctlr_gen_clk_2x,
+ -- .pll_write_clk
+ pll_write_clk => OPEN,
+ -- .pll_write_clk_pre_phy_clk
+ pll_write_clk_pre_phy_clk => OPEN,
+ -- .pll_addr_cmd_clk
+ pll_addr_cmd_clk => OPEN,
+ -- .pll_locked
+ pll_locked => OPEN,
+ -- .pll_avl_clk
+ pll_avl_clk => OPEN,
+ -- .pll_config_clk
+ pll_config_clk => OPEN,
+ -- dll_sharing.dll_delayctrl
+ dll_delayctrl => open
);
end generate;
gen_ip_stratixiv_ddr3_uphy_4g_800_slave : if g_tech_ddr.name = "DDR3" and c_gigabytes = 4 and g_tech_ddr.mts = 800 and g_tech_ddr.master = false and g_tech_ddr.rank = "DUAL " generate
u_ip_stratixiv_ddr3_uphy_4g_800_slave : ip_stratixiv_ddr3_uphy_4g_800_slave
port map (
- pll_ref_clk => ref_clk, -- pll_ref_clk.clk
- global_reset_n => ref_rst_n, -- global_reset.reset_n
- soft_reset_n => '1', -- soft_reset.reset_n
- afi_clk => ctlr_gen_clk, -- afi_clk.clk
- afi_half_clk => OPEN, -- afi_half_clk.clk
- afi_reset_n => ctlr_gen_rst_n, -- afi_reset.reset_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- memory.mem_a
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_dm => phy_ou.dm(g_tech_ddr.dm_w - 1 downto 0), -- .mem_dm
- mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
- mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
- mem_we_n => phy_ou.we_n, -- .mem_we_n
- mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- avl_ready => ctlr_miso.waitrequest_n, -- avl.waitrequest_n
- avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
- avl_addr => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- avl_rdata_valid => ctlr_miso.rdval, -- .readdatavalid
- avl_rdata => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0), -- .readdata
- avl_wdata => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0), -- .writedata
- avl_be => (others => '1'), -- .byteenable
- avl_read_req => ctlr_mosi.rd, -- .read
- avl_write_req => ctlr_mosi.wr, -- .write
- avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- local_init_done => ctlr_miso.done, -- status.local_init_done
- local_cal_success => OPEN, -- .local_cal_success
- local_cal_fail => OPEN, -- .local_cal_fail
- seriesterminationcontrol => term_ctrl_in.seriesterminationcontrol, -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol => term_ctrl_in.parallelterminationcontrol, -- .parallelterminationcontrol
- pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
- pll_write_clk => OPEN, -- .pll_write_clk
- pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
- pll_locked => OPEN, -- .pll_locked
- pll_avl_clk => OPEN, -- .pll_avl_clk
- pll_config_clk => OPEN, -- .pll_config_clk
- dll_delayctrl => open -- dll_sharing.dll_delayctrl
+ -- pll_ref_clk.clk
+ pll_ref_clk => ref_clk,
+ -- global_reset.reset_n
+ global_reset_n => ref_rst_n,
+ -- soft_reset.reset_n
+ soft_reset_n => '1',
+ -- afi_clk.clk
+ afi_clk => ctlr_gen_clk,
+ -- afi_half_clk.clk
+ afi_half_clk => OPEN,
+ -- afi_reset.reset_n
+ afi_reset_n => ctlr_gen_rst_n,
+ -- memory.mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_dm
+ mem_dm => phy_ou.dm(g_tech_ddr.dm_w - 1 downto 0),
+ -- .mem_ras_n
+ mem_ras_n => phy_ou.ras_n,
+ -- .mem_cas_n
+ mem_cas_n => phy_ou.cas_n,
+ -- .mem_we_n
+ mem_we_n => phy_ou.we_n,
+ -- .mem_reset_n
+ mem_reset_n => phy_ou.reset_n,
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- avl.waitrequest_n
+ avl_ready => ctlr_miso.waitrequest_n,
+ -- .beginbursttransfer
+ avl_burstbegin => ctlr_mosi.burstbegin,
+ -- .address
+ avl_addr => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdatavalid
+ avl_rdata_valid => ctlr_miso.rdval,
+ -- .readdata
+ avl_rdata => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0),
+ -- .writedata
+ avl_wdata => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0),
+ -- .byteenable
+ avl_be => (others => '1'),
+ -- .read
+ avl_read_req => ctlr_mosi.rd,
+ -- .write
+ avl_write_req => ctlr_mosi.wr,
+ -- .burstcount
+ avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- status.local_init_done
+ local_init_done => ctlr_miso.done,
+ -- .local_cal_success
+ local_cal_success => OPEN,
+ -- .local_cal_fail
+ local_cal_fail => OPEN,
+ -- oct_sharing.seriesterminationcontrol
+ seriesterminationcontrol => term_ctrl_in.seriesterminationcontrol,
+ -- .parallelterminationcontrol
+ parallelterminationcontrol => term_ctrl_in.parallelterminationcontrol,
+ -- pll_sharing.pll_mem_clk
+ pll_mem_clk => i_ctlr_gen_clk_2x,
+ -- .pll_write_clk
+ pll_write_clk => OPEN,
+ -- .pll_write_clk_pre_phy_clk
+ pll_write_clk_pre_phy_clk => OPEN,
+ -- .pll_addr_cmd_clk
+ pll_addr_cmd_clk => OPEN,
+ -- .pll_locked
+ pll_locked => OPEN,
+ -- .pll_avl_clk
+ pll_avl_clk => OPEN,
+ -- .pll_config_clk
+ pll_config_clk => OPEN,
+ -- dll_sharing.dll_delayctrl
+ dll_delayctrl => open
);
end generate;
gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master : if g_tech_ddr.name = "DDR3" and c_gigabytes = 4 and g_tech_ddr.mts = 800 and g_tech_ddr.master = true and g_tech_ddr.rank = "SINGLE" generate
u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master : ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
port map (
- pll_ref_clk => ref_clk, -- pll_ref_clk.clk
- global_reset_n => ref_rst_n, -- global_reset.reset_n
- soft_reset_n => '1', -- soft_reset.reset_n
- afi_clk => ctlr_gen_clk, -- afi_clk.clk
- afi_half_clk => OPEN, -- afi_half_clk.clk
- afi_reset_n => ctlr_gen_rst_n, -- afi_reset.reset_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- memory.mem_a
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_cke => i_mem_cke, -- .mem_cke
- mem_cs_n => i_mem_cs_n, -- .mem_cs_n
- mem_dm => phy_ou.dm(g_tech_ddr.dm_w - 1 downto 0), -- .mem_dm
- mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
- mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
- mem_we_n => phy_ou.we_n, -- .mem_we_n
- mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_odt => i_mem_odt, -- .mem_odt
- avl_ready => ctlr_miso.waitrequest_n, -- avl.waitrequest_n
- avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
- avl_addr => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- avl_rdata_valid => ctlr_miso.rdval, -- .readdatavalid
- avl_rdata => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0), -- .readdata
- avl_wdata => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0), -- .writedata
- avl_be => (others => '1'), -- .byteenable
- avl_read_req => ctlr_mosi.rd, -- .read
- avl_write_req => ctlr_mosi.wr, -- .write
- avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- local_init_done => ctlr_miso.done, -- status.local_init_done
- local_cal_success => ctlr_miso.cal_ok, -- .local_cal_success
- local_cal_fail => ctlr_miso.cal_fail, -- .local_cal_fail
- oct_rdn => phy_in.oct_rdn, -- oct.rdn
- oct_rup => phy_in.oct_rup, -- .rup
- seriesterminationcontrol => term_ctrl_out.seriesterminationcontrol, -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol => term_ctrl_out.parallelterminationcontrol, -- .parallelterminationcontrol
- pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
- pll_write_clk => OPEN, -- .pll_write_clk
- pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
- pll_locked => OPEN, -- .pll_locked
- pll_avl_clk => OPEN, -- .pll_avl_clk
- pll_config_clk => OPEN, -- .pll_config_clk
- dll_delayctrl => open -- dll_sharing.dll_delayctrl
+ -- pll_ref_clk.clk
+ pll_ref_clk => ref_clk,
+ -- global_reset.reset_n
+ global_reset_n => ref_rst_n,
+ -- soft_reset.reset_n
+ soft_reset_n => '1',
+ -- afi_clk.clk
+ afi_clk => ctlr_gen_clk,
+ -- afi_half_clk.clk
+ afi_half_clk => OPEN,
+ -- afi_reset.reset_n
+ afi_reset_n => ctlr_gen_rst_n,
+ -- memory.mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => i_mem_cke,
+ -- .mem_cs_n
+ mem_cs_n => i_mem_cs_n,
+ -- .mem_dm
+ mem_dm => phy_ou.dm(g_tech_ddr.dm_w - 1 downto 0),
+ -- .mem_ras_n
+ mem_ras_n => phy_ou.ras_n,
+ -- .mem_cas_n
+ mem_cas_n => phy_ou.cas_n,
+ -- .mem_we_n
+ mem_we_n => phy_ou.we_n,
+ -- .mem_reset_n
+ mem_reset_n => phy_ou.reset_n,
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => i_mem_odt,
+ -- avl.waitrequest_n
+ avl_ready => ctlr_miso.waitrequest_n,
+ -- .beginbursttransfer
+ avl_burstbegin => ctlr_mosi.burstbegin,
+ -- .address
+ avl_addr => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdatavalid
+ avl_rdata_valid => ctlr_miso.rdval,
+ -- .readdata
+ avl_rdata => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0),
+ -- .writedata
+ avl_wdata => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0),
+ -- .byteenable
+ avl_be => (others => '1'),
+ -- .read
+ avl_read_req => ctlr_mosi.rd,
+ -- .write
+ avl_write_req => ctlr_mosi.wr,
+ -- .burstcount
+ avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- status.local_init_done
+ local_init_done => ctlr_miso.done,
+ -- .local_cal_success
+ local_cal_success => ctlr_miso.cal_ok,
+ -- .local_cal_fail
+ local_cal_fail => ctlr_miso.cal_fail,
+ -- oct.rdn
+ oct_rdn => phy_in.oct_rdn,
+ -- .rup
+ oct_rup => phy_in.oct_rup,
+ -- oct_sharing.seriesterminationcontrol
+ seriesterminationcontrol => term_ctrl_out.seriesterminationcontrol,
+ -- .parallelterminationcontrol
+ parallelterminationcontrol => term_ctrl_out.parallelterminationcontrol,
+ -- pll_sharing.pll_mem_clk
+ pll_mem_clk => i_ctlr_gen_clk_2x,
+ -- .pll_write_clk
+ pll_write_clk => OPEN,
+ -- .pll_write_clk_pre_phy_clk
+ pll_write_clk_pre_phy_clk => OPEN,
+ -- .pll_addr_cmd_clk
+ pll_addr_cmd_clk => OPEN,
+ -- .pll_locked
+ pll_locked => OPEN,
+ -- .pll_avl_clk
+ pll_avl_clk => OPEN,
+ -- .pll_config_clk
+ pll_config_clk => OPEN,
+ -- dll_sharing.dll_delayctrl
+ dll_delayctrl => open
);
phy_ou.cke(0) <= i_mem_cke;
@@ -251,50 +387,94 @@ begin
gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave : if g_tech_ddr.name = "DDR3" and c_gigabytes = 4 and g_tech_ddr.mts = 800 and g_tech_ddr.master = false and g_tech_ddr.rank = "SINGLE" generate
u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave : ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
port map (
- pll_ref_clk => ref_clk, -- pll_ref_clk.clk
- global_reset_n => ref_rst_n, -- global_reset.reset_n
- soft_reset_n => '1', -- soft_reset.reset_n
- afi_clk => ctlr_gen_clk, -- afi_clk.clk
- afi_half_clk => OPEN, -- afi_half_clk.clk
- afi_reset_n => ctlr_gen_rst_n, -- afi_reset.reset_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- memory.mem_a
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_cke => i_mem_cke, -- .mem_cke
- mem_cs_n => i_mem_cs_n, -- .mem_cs_n
- mem_dm => phy_ou.dm(g_tech_ddr.dm_w - 1 downto 0), -- .mem_dm
- mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
- mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
- mem_we_n => phy_ou.we_n, -- .mem_we_n
- mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_odt => i_mem_odt, -- .mem_odt
- avl_ready => ctlr_miso.waitrequest_n, -- avl.waitrequest_n
- avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
- avl_addr => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- avl_rdata_valid => ctlr_miso.rdval, -- .readdatavalid
- avl_rdata => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0), -- .readdata
- avl_wdata => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0), -- .writedata
- avl_be => (others => '1'), -- .byteenable
- avl_read_req => ctlr_mosi.rd, -- .read
- avl_write_req => ctlr_mosi.wr, -- .write
- avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- local_init_done => ctlr_miso.done, -- status.local_init_done
- local_cal_success => OPEN, -- .local_cal_success
- local_cal_fail => OPEN, -- .local_cal_fail
- seriesterminationcontrol => term_ctrl_in.seriesterminationcontrol, -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol => term_ctrl_in.parallelterminationcontrol, -- .parallelterminationcontrol
- pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
- pll_write_clk => OPEN, -- .pll_write_clk
- pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
- pll_locked => OPEN, -- .pll_locked
- pll_avl_clk => OPEN, -- .pll_avl_clk
- pll_config_clk => OPEN, -- .pll_config_clk
- dll_delayctrl => open -- dll_sharing.dll_delayctrl
+ -- pll_ref_clk.clk
+ pll_ref_clk => ref_clk,
+ -- global_reset.reset_n
+ global_reset_n => ref_rst_n,
+ -- soft_reset.reset_n
+ soft_reset_n => '1',
+ -- afi_clk.clk
+ afi_clk => ctlr_gen_clk,
+ -- afi_half_clk.clk
+ afi_half_clk => OPEN,
+ -- afi_reset.reset_n
+ afi_reset_n => ctlr_gen_rst_n,
+ -- memory.mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => i_mem_cke,
+ -- .mem_cs_n
+ mem_cs_n => i_mem_cs_n,
+ -- .mem_dm
+ mem_dm => phy_ou.dm(g_tech_ddr.dm_w - 1 downto 0),
+ -- .mem_ras_n
+ mem_ras_n => phy_ou.ras_n,
+ -- .mem_cas_n
+ mem_cas_n => phy_ou.cas_n,
+ -- .mem_we_n
+ mem_we_n => phy_ou.we_n,
+ -- .mem_reset_n
+ mem_reset_n => phy_ou.reset_n,
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => i_mem_odt,
+ -- avl.waitrequest_n
+ avl_ready => ctlr_miso.waitrequest_n,
+ -- .beginbursttransfer
+ avl_burstbegin => ctlr_mosi.burstbegin,
+ -- .address
+ avl_addr => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdatavalid
+ avl_rdata_valid => ctlr_miso.rdval,
+ -- .readdata
+ avl_rdata => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0),
+ -- .writedata
+ avl_wdata => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0),
+ -- .byteenable
+ avl_be => (others => '1'),
+ -- .read
+ avl_read_req => ctlr_mosi.rd,
+ -- .write
+ avl_write_req => ctlr_mosi.wr,
+ -- .burstcount
+ avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- status.local_init_done
+ local_init_done => ctlr_miso.done,
+ -- .local_cal_success
+ local_cal_success => OPEN,
+ -- .local_cal_fail
+ local_cal_fail => OPEN,
+ -- oct_sharing.seriesterminationcontrol
+ seriesterminationcontrol => term_ctrl_in.seriesterminationcontrol,
+ -- .parallelterminationcontrol
+ parallelterminationcontrol => term_ctrl_in.parallelterminationcontrol,
+ -- pll_sharing.pll_mem_clk
+ pll_mem_clk => i_ctlr_gen_clk_2x,
+ -- .pll_write_clk
+ pll_write_clk => OPEN,
+ -- .pll_write_clk_pre_phy_clk
+ pll_write_clk_pre_phy_clk => OPEN,
+ -- .pll_addr_cmd_clk
+ pll_addr_cmd_clk => OPEN,
+ -- .pll_locked
+ pll_locked => OPEN,
+ -- .pll_avl_clk
+ pll_avl_clk => OPEN,
+ -- .pll_config_clk
+ pll_config_clk => OPEN,
+ -- dll_sharing.dll_delayctrl
+ dll_delayctrl => open
);
phy_ou.cke(0) <= i_mem_cke;
@@ -305,52 +485,98 @@ begin
gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800 : if g_tech_ddr.name = "DDR3" and c_gigabytes = 16 and g_tech_ddr.mts = 800 and g_tech_ddr.master = true and g_tech_ddr.rank = "DUAL " generate
u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800 : ip_stratixiv_ddr3_uphy_16g_dual_rank_800
port map (
- pll_ref_clk => ref_clk, -- pll_ref_clk.clk
- global_reset_n => ref_rst_n, -- global_reset.reset_n
- soft_reset_n => '1', -- soft_reset.reset_n
- afi_clk => ctlr_gen_clk, -- afi_clk.clk
- afi_half_clk => OPEN, -- afi_half_clk.clk
- afi_reset_n => ctlr_gen_rst_n, -- afi_reset.reset_n
- mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0), -- memory.mem_a
- mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0), -- .mem_ba
- mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck
- mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0), -- .mem_ck_n
- mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_dm => phy_ou.dm(g_tech_ddr.dm_w - 1 downto 0), -- .mem_dm
- mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
- mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
- mem_we_n => phy_ou.we_n, -- .mem_we_n
- mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
- mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0), -- .mem_dq
- mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0), -- .mem_odt
- avl_ready => ctlr_miso.waitrequest_n, -- avl.waitrequest_n
- avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
- avl_addr => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0), -- .address
- avl_rdata_valid => ctlr_miso.rdval, -- .readdatavalid
- avl_rdata => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0), -- .readdata
- avl_wdata => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0), -- .writedata
- avl_be => (others => '1'), -- .byteenable
- avl_read_req => ctlr_mosi.rd, -- .read
- avl_write_req => ctlr_mosi.wr, -- .write
- avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0), -- .burstcount
- local_init_done => ctlr_miso.done, -- status.local_init_done
- local_cal_success => ctlr_miso.cal_ok, -- .local_cal_success
- local_cal_fail => ctlr_miso.cal_fail, -- .local_cal_fail
- oct_rdn => phy_in.oct_rdn, -- oct.rdn
- oct_rup => phy_in.oct_rup, -- .rup
- seriesterminationcontrol => term_ctrl_out.seriesterminationcontrol, -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol => term_ctrl_out.parallelterminationcontrol, -- .parallelterminationcontrol
- pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
- pll_write_clk => OPEN, -- .pll_write_clk
- pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
- pll_locked => OPEN, -- .pll_locked
- pll_avl_clk => OPEN, -- .pll_avl_clk
- pll_config_clk => OPEN, -- .pll_config_clk
- dll_delayctrl => open -- dll_sharing.dll_delayctrl
+ -- pll_ref_clk.clk
+ pll_ref_clk => ref_clk,
+ -- global_reset.reset_n
+ global_reset_n => ref_rst_n,
+ -- soft_reset.reset_n
+ soft_reset_n => '1',
+ -- afi_clk.clk
+ afi_clk => ctlr_gen_clk,
+ -- afi_half_clk.clk
+ afi_half_clk => OPEN,
+ -- afi_reset.reset_n
+ afi_reset_n => ctlr_gen_rst_n,
+ -- memory.mem_a
+ mem_a => phy_ou.a(g_tech_ddr.a_w - 1 downto 0),
+ -- .mem_ba
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w - 1 downto 0),
+ -- .mem_ck
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_ck_n
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ -- .mem_cke
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w - 1 downto 0),
+ -- .mem_cs_n
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ -- .mem_dm
+ mem_dm => phy_ou.dm(g_tech_ddr.dm_w - 1 downto 0),
+ -- .mem_ras_n
+ mem_ras_n => phy_ou.ras_n,
+ -- .mem_cas_n
+ mem_cas_n => phy_ou.cas_n,
+ -- .mem_we_n
+ mem_we_n => phy_ou.we_n,
+ -- .mem_reset_n
+ mem_reset_n => phy_ou.reset_n,
+ -- .mem_dq
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w - 1 downto 0),
+ -- .mem_dqs
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_dqs_n
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ -- .mem_odt
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w - 1 downto 0),
+ -- avl.waitrequest_n
+ avl_ready => ctlr_miso.waitrequest_n,
+ -- .beginbursttransfer
+ avl_burstbegin => ctlr_mosi.burstbegin,
+ -- .address
+ avl_addr => ctlr_mosi.address(c_ctlr_address_w - 1 downto 0),
+ -- .readdatavalid
+ avl_rdata_valid => ctlr_miso.rdval,
+ -- .readdata
+ avl_rdata => ctlr_miso.rddata(c_ctlr_data_w - 1 downto 0),
+ -- .writedata
+ avl_wdata => ctlr_mosi.wrdata(c_ctlr_data_w - 1 downto 0),
+ -- .byteenable
+ avl_be => (others => '1'),
+ -- .read
+ avl_read_req => ctlr_mosi.rd,
+ -- .write
+ avl_write_req => ctlr_mosi.wr,
+ -- .burstcount
+ avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w - 1 downto 0),
+ -- status.local_init_done
+ local_init_done => ctlr_miso.done,
+ -- .local_cal_success
+ local_cal_success => ctlr_miso.cal_ok,
+ -- .local_cal_fail
+ local_cal_fail => ctlr_miso.cal_fail,
+ -- oct.rdn
+ oct_rdn => phy_in.oct_rdn,
+ -- .rup
+ oct_rup => phy_in.oct_rup,
+ -- oct_sharing.seriesterminationcontrol
+ seriesterminationcontrol => term_ctrl_out.seriesterminationcontrol,
+ -- .parallelterminationcontrol
+ parallelterminationcontrol => term_ctrl_out.parallelterminationcontrol,
+ -- pll_sharing.pll_mem_clk
+ pll_mem_clk => i_ctlr_gen_clk_2x,
+ -- .pll_write_clk
+ pll_write_clk => OPEN,
+ -- .pll_write_clk_pre_phy_clk
+ pll_write_clk_pre_phy_clk => OPEN,
+ -- .pll_addr_cmd_clk
+ pll_addr_cmd_clk => OPEN,
+ -- .pll_locked
+ pll_locked => OPEN,
+ -- .pll_avl_clk
+ pll_avl_clk => OPEN,
+ -- .pll_config_clk
+ pll_config_clk => OPEN,
+ -- dll_sharing.dll_delayctrl
+ dll_delayctrl => open
);
end generate;
diff --git a/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd b/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd
index 5922075d48a3726aa8ab93702d41d22114c58a0f..20907241803146a205aa56f023ee13e3fc5d937c 100644
--- a/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd
@@ -42,7 +42,8 @@ architecture tb of tb_tb_tech_eth_10g is
constant c_data_type : natural := c_tb_tech_mac_10g_data_type_symbols;
constant c_tb_end_vec : std_logic_vector(7 downto 0) := (others => '1');
- signal tb_end_vec : std_logic_vector(7 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ -- sufficiently long to fit all tb instances
+ signal tb_end_vec : std_logic_vector(7 downto 0) := c_tb_end_vec;
signal tb_end : std_logic := '0';
begin
-- g_technology : NATURAL := c_tech_select_default;
diff --git a/libraries/technology/eth_10g/tb_tech_eth_10g.vhd b/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
index 7cd775e11e755268a9a5bc733621e67ec0412c12..b7906e98c4f16cd98f89aa762bab69f02a16489a 100644
--- a/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
@@ -47,36 +47,48 @@ entity tb_tech_eth_10g is
-- Test bench control parameters
generic (
g_technology : natural := c_tech_select_default;
- g_tb_end : boolean := true; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
- g_no_dut : boolean := false; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
- g_sim_level : natural := 1; -- 0 = use IP; 1 = use fast serdes model
- g_ref_clk_644_period : time := tech_pll_clk_644_period; -- for 10GBASE-R
- g_ref_clk_156_period : time := 6.4 ns; -- for XAUI
+ -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ g_tb_end : boolean := true;
+ -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
+ g_no_dut : boolean := false;
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 1;
+ -- for 10GBASE-R
+ g_ref_clk_644_period : time := tech_pll_clk_644_period;
+ -- for XAUI
+ g_ref_clk_156_period : time := 6.4 ns;
g_data_type : natural := c_tb_tech_mac_10g_data_type_symbols;
g_verify_link_recovery : boolean := true;
- g_use_serial_rx_in : boolean := false -- default FALSE when this tb is ran standalone, else use TRUE to simulate a link between two instances of this tb
+ -- default FALSE when this tb is ran standalone, else use TRUE to simulate a link between two instances of this tb
+ g_use_serial_rx_in : boolean := false
);
port (
tb_end : out std_logic;
-- PHY 10gbase_r
- serial_tx_out : out std_logic; -- 1 lane
+ -- 1 lane
+ serial_tx_out : out std_logic;
serial_rx_in : in std_logic := 'X';
-- PHY XAUI
- xaui_tx_out : out std_logic_vector(c_nof_xaui_lanes - 1 downto 0); -- 4 lanes
+ -- 4 lanes
+ xaui_tx_out : out std_logic_vector(c_nof_xaui_lanes - 1 downto 0);
xaui_rx_in : in std_logic_vector(c_nof_xaui_lanes - 1 downto 0) := (others => 'X')
);
end tb_tech_eth_10g;
architecture tb of tb_tech_eth_10g is
- constant c_sim : boolean := true; -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation
- constant c_nof_channels : natural := 1; -- fixed in this tb
+ -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation
+ constant c_sim : boolean := true;
+ -- fixed in this tb
+ constant c_nof_channels : natural := 1;
- constant cal_clk_period : time := 25 ns; -- 40 MHz
+ -- 40 MHz
+ constant cal_clk_period : time := 25 ns;
constant phy_delay : time := 0 ns;
constant c_phy_loopback : boolean := not g_use_serial_rx_in;
- constant c_pkt_length_arr1 : t_nat_natural_arr := array_init(0, 50, 1) & (1472, 1473) & 9000; -- frame longer than 1518-46 = 1472 is received with rx_sosi.err = 8
+ -- frame longer than 1518-46 = 1472 is received with rx_sosi.err = 8
+ constant c_pkt_length_arr1 : t_nat_natural_arr := array_init(0, 50, 1) & (1472, 1473) & 9000;
-- jumbo frame is 9018-46 = 8972
constant c_pkt_length_arr2 : t_nat_natural_arr := array_init(46, 10, 139) & 1472;
constant c_pkt_length_arr : t_nat_natural_arr := c_pkt_length_arr1 & c_pkt_length_arr2;
@@ -85,7 +97,8 @@ architecture tb of tb_tech_eth_10g is
constant c_nof_pkt : natural := sel_a_b(g_verify_link_recovery, c_nof_pkt1 + c_nof_pkt2, c_nof_pkt1);
constant c_dst_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"10FA01020300";
- constant c_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ -- = 12-34-56-78-9A-BC
+ constant c_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"123456789ABC";
constant c_src_mac_tx : std_logic_vector(c_network_eth_mac_slv'range) := c_src_mac;
--CONSTANT c_src_mac_tx : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"100056789ABC"; -- = 10-00-56-78-9A-BC
constant c_ethertype : std_logic_vector(c_network_eth_type_slv'range) := X"10FA";
@@ -95,20 +108,28 @@ architecture tb of tb_tech_eth_10g is
constant c_eth_header_ethertype : t_network_eth_header := (c_dst_mac, c_src_mac_tx, c_ethertype);
constant c_eth_header_etherlen : t_network_eth_header := (c_dst_mac, c_src_mac_tx, c_etherlen);
- signal total_header : t_network_total_header := c_network_total_header_ones; -- default fill all fields with value 1
+ -- default fill all fields with value 1
+ signal total_header : t_network_total_header := c_network_total_header_ones;
-- Clocks and reset
signal tx_end : std_logic := '0';
signal rx_end : std_logic := '0';
- signal cal_clk : std_logic := '1'; -- calibration clock
- signal mm_clk : std_logic := '0'; -- memory-mapped bus clock
- signal mm_rst : std_logic; -- reset synchronous with mm_clk
+ -- calibration clock
+ signal cal_clk : std_logic := '1';
+ -- memory-mapped bus clock
+ signal mm_clk : std_logic := '0';
+ -- reset synchronous with mm_clk
+ signal mm_rst : std_logic;
-- External reference clocks
- signal tr_ref_clk_644 : std_logic := '1'; -- 10GBASE-R
- signal tr_ref_clk_312 : std_logic; -- 10GBASE-R
- signal tr_ref_clk_156 : std_logic := '1'; -- 10GBASE-R or XAUI
- signal tr_ref_rst_156 : std_logic; -- 10GBASE-R or XAUI
+ -- 10GBASE-R
+ signal tr_ref_clk_644 : std_logic := '1';
+ -- 10GBASE-R
+ signal tr_ref_clk_312 : std_logic;
+ -- 10GBASE-R or XAUI
+ signal tr_ref_clk_156 : std_logic := '1';
+ -- 10GBASE-R or XAUI
+ signal tr_ref_rst_156 : std_logic;
-- XAUI clocks
signal tx_rst_arr_out : std_logic_vector(0 downto 0);
@@ -128,22 +149,26 @@ architecture tb of tb_tech_eth_10g is
-- 10G MAC control interface
signal mm_init : std_logic := '1';
signal mac_mosi : t_mem_mosi;
- signal mac_mosi_wrdata : std_logic_vector(c_word_w - 1 downto 0); -- 32 bit;
+ -- 32 bit;
+ signal mac_mosi_wrdata : std_logic_vector(c_word_w - 1 downto 0);
signal mac_miso : t_mem_miso;
signal mac_miso_rdval : std_logic;
- signal mac_miso_rddata : std_logic_vector(c_word_w - 1 downto 0); -- 32 bit;
+ -- 32 bit;
+ signal mac_miso_rddata : std_logic_vector(c_word_w - 1 downto 0);
-- 10G MAC transmit interface
-- . The tb is the ST source
signal tx_siso : t_dp_siso;
signal tx_sosi : t_dp_sosi;
- signal tx_sosi_data : std_logic_vector(c_tech_mac_10g_data_w - 1 downto 0); -- 64 bit
+ -- 64 bit
+ signal tx_sosi_data : std_logic_vector(c_tech_mac_10g_data_w - 1 downto 0);
-- 10G MAC receive interface
-- . The tb is the ST sink
signal rx_siso : t_dp_siso;
signal rx_sosi : t_dp_sosi;
- signal rx_sosi_data : std_logic_vector(c_tech_mac_10g_data_w - 1 downto 0); -- 64 bit
+ -- 64 bit
+ signal rx_sosi_data : std_logic_vector(c_tech_mac_10g_data_w - 1 downto 0);
-- PHY serial IO
-- . 10GBASE-R (single lane)
@@ -160,14 +185,17 @@ architecture tb of tb_tech_eth_10g is
-- Verification
signal tx_pkt_cnt : natural := 0;
signal rx_pkt_cnt : natural := 0;
- signal rx_toggle : std_logic; -- toggle after every received packet
+ -- toggle after every received packet
+ signal rx_toggle : std_logic;
begin
- cal_clk <= not cal_clk after cal_clk_period / 2; -- Calibration clock
+ -- Calibration clock
+ cal_clk <= not cal_clk after cal_clk_period / 2;
-- debug signals to ease monitoring in wave window
mac_mosi_wrdata <= mac_mosi.wrdata(c_word_w - 1 downto 0);
mac_miso_rddata <= mac_miso.rddata(c_word_w - 1 downto 0);
- mac_miso_rdval <= '1' when mac_mosi.rd = '1' and mac_miso.waitrequest = '0' else '0'; -- c_rd_latency = 1
+ -- c_rd_latency = 1
+ mac_miso_rdval <= '1' when mac_mosi.rd = '1' and mac_miso.waitrequest = '0' else '0';
tx_sosi_data <= tx_sosi.data(c_tech_mac_10g_data_w - 1 downto 0);
rx_sosi_data <= rx_sosi.data(c_tech_mac_10g_data_w - 1 downto 0);
@@ -292,27 +320,33 @@ begin
tr_ref_rst_156 => tb_ref_rst_156,
-- Calibration & reconfig clock
- cal_rec_clk => cal_clk, -- for XAUI
+ -- for XAUI
+ cal_rec_clk => cal_clk,
-- MM
mm_clk => mm_clk,
mm_rst => mm_rst,
- mac_mosi => mac_mosi, -- CSR = control status register
+ -- CSR = control status register
+ mac_mosi => mac_mosi,
mac_miso => mac_miso,
-- XAUI clocks
- tx_clk_arr_in(0) => tb_tx_clk, -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
+ -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
+ tx_clk_arr_in(0) => tb_tx_clk,
tx_rst_arr_out => tx_rst_arr_out,
rx_clk_arr_out => rx_clk_arr_out,
- rx_clk_arr_in(0) => tb_rx_clk, -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ rx_clk_arr_in(0) => tb_rx_clk,
rx_rst_arr_out => rx_rst_arr_out,
-- ST
- tx_snk_in_arr(0) => tx_sosi, -- 64 bit data @ 156 tb_tx_clk
+ -- 64 bit data @ 156 tb_tx_clk
+ tx_snk_in_arr(0) => tx_sosi,
tx_snk_out_arr(0) => tx_siso,
- rx_src_out_arr(0) => rx_sosi, -- 64 bit data @ 156 tb_rx_clk
+ -- 64 bit data @ 156 tb_rx_clk
+ rx_src_out_arr(0) => rx_sosi,
rx_src_in_arr(0) => rx_siso,
-- PHY serial IO
@@ -328,23 +362,31 @@ begin
u_link_connect : entity tech_mac_10g_lib.tb_tech_mac_10g_link_connect
generic map (
- g_loopback => c_phy_loopback, -- default TRUE for loopback tx to rx, else use FALSE to connect tx-tx, rx-rx between two tb devices
+ -- default TRUE for loopback tx to rx, else use FALSE to connect tx-tx, rx-rx between two tb devices
+ g_loopback => c_phy_loopback,
g_link_delay => phy_delay
)
port map (
- link_fault => link_fault, -- when '1' then forces rx_serial_arr(0)='0'
+ -- when '1' then forces rx_serial_arr(0)='0'
+ link_fault => link_fault,
-- 10GBASE-R serial layer connect
serial_tx => serial_tx_arr(0),
- serial_rx => serial_rx_arr(0), -- connects to delayed tx_serial_arr(0) when g_loopback=TRUE else to rx_serial_in
- serial_tx_out => serial_tx_out, -- connects to delayed tx_serial_arr(0)
- serial_rx_in => serial_rx_in, -- used when g_loopback=FALSE
+ -- connects to delayed tx_serial_arr(0) when g_loopback=TRUE else to rx_serial_in
+ serial_rx => serial_rx_arr(0),
+ -- connects to delayed tx_serial_arr(0)
+ serial_tx_out => serial_tx_out,
+ -- used when g_loopback=FALSE
+ serial_rx_in => serial_rx_in,
-- XAUI serial layer connect
xaui_tx => xaui_tx_arr(0),
- xaui_rx => xaui_rx_arr(0), -- connects to delayed xaui_tx_arr(0) when g_loopback=TRUE else to xaui_rx_in
- xaui_tx_out => xaui_tx_out, -- connects to delayed xaui_tx_arr(0)
- xaui_rx_in => xaui_rx_in -- used when g_loopback=FALSE
+ -- connects to delayed xaui_tx_arr(0) when g_loopback=TRUE else to xaui_rx_in
+ xaui_rx => xaui_rx_arr(0),
+ -- connects to delayed xaui_tx_arr(0)
+ xaui_tx_out => xaui_tx_out,
+ -- used when g_loopback=FALSE
+ xaui_rx_in => xaui_rx_in
);
-- Packet receiver
diff --git a/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd b/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
index 2f83f74fcb89b1743949f3a015763b7090746e38..dfc8e251fd169688cbc27b10a5c6293d21fe0ca7 100644
--- a/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
+++ b/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
@@ -43,17 +43,20 @@ entity tb_tech_eth_10g_ppm is
-- Test bench control parameters
generic (
g_technology : natural := c_tech_select_default;
- g_nof_10ppm : integer := 1 -- use /= 0 to verify XO ppm offset between two devices
+ -- use /= 0 to verify XO ppm offset between two devices
+ g_nof_10ppm : integer := 1
);
end tb_tech_eth_10g_ppm;
architecture tb of tb_tech_eth_10g_ppm is
-- PHY 10gbase_r
- signal serial_tx_0 : std_logic; -- 1 lane
+ -- 1 lane
+ signal serial_tx_0 : std_logic;
signal serial_tx_1 : std_logic;
-- PHY XAUI
- signal xaui_tx_0 : std_logic_vector(c_nof_xaui_lanes - 1 downto 0); -- 4 lanes
+ -- 4 lanes
+ signal xaui_tx_0 : std_logic_vector(c_nof_xaui_lanes - 1 downto 0);
signal xaui_tx_1 : std_logic_vector(c_nof_xaui_lanes - 1 downto 0);
begin
u_tb_tech_eth_10g_0 : entity work.tb_tech_eth_10g
diff --git a/libraries/technology/eth_10g/tech_eth_10g.vhd b/libraries/technology/eth_10g/tech_eth_10g.vhd
index fa7502cef39091424edc574eb00964e5bb9a20d0..e9abbf7f574bab1ca0748d9c2b89bbde36b592da 100644
--- a/libraries/technology/eth_10g/tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g.vhd
@@ -72,50 +72,64 @@ entity tech_eth_10g is
generic (
g_technology : natural := c_tech_select_default;
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_use_loopback : boolean := false;
g_pre_header_padding : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_644 : in std_logic := '0'; -- 644.531250 MHz for 10GBASE-R
- tr_ref_clk_312 : in std_logic := '0'; -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 : in std_logic := '0'; -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 : in std_logic := '0'; -- for 10GBASE-R or for XAUI
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 : in std_logic := '0';
+ -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_312 : in std_logic := '0';
+ -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_clk_156 : in std_logic := '0';
+ -- for 10GBASE-R or for XAUI
+ tr_ref_rst_156 : in std_logic := '0';
-- Calibration & reconfig clock
- cal_rec_clk : in std_logic := '0'; -- for XAUI;
+ -- for XAUI;
+ cal_rec_clk : in std_logic := '0';
-- XAUI clocks
- tx_clk_arr_in : in std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0'); -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr_in or connect rx_clk_arr to tx_clk_arr_in
+ -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr_in or connect rx_clk_arr to tx_clk_arr_in
+ tx_clk_arr_in : in std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0');
tx_rst_arr_out : out std_logic_vector(g_nof_channels - 1 downto 0);
rx_clk_arr_out : out std_logic_vector(g_nof_channels - 1 downto 0);
- rx_clk_arr_in : in std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0'); -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ rx_clk_arr_in : in std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0');
rx_rst_arr_out : out std_logic_vector(g_nof_channels - 1 downto 0);
-- MM
mm_clk : in std_logic;
mm_rst : in std_logic;
- mac_mosi : in t_mem_mosi := c_mem_mosi_rst; -- MAG_10G (CSR), aggregated for all g_nof_channels
+ -- MAG_10G (CSR), aggregated for all g_nof_channels
+ mac_mosi : in t_mem_mosi := c_mem_mosi_rst;
mac_miso : out t_mem_miso;
- xaui_mosi : in t_mem_mosi := c_mem_mosi_rst; -- XAUI control
+ -- XAUI control
+ xaui_mosi : in t_mem_mosi := c_mem_mosi_rst;
xaui_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi := c_mem_mosi_rst; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_eth10g_miso : out t_mem_miso;
reg_10gbase_r_24_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_10gbase_r_24_miso : out t_mem_miso;
-- ST
- tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ 156 MHz
+ -- 64 bit data @ 156 MHz
+ tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0);
tx_snk_out_arr : out t_dp_siso_arr(g_nof_channels - 1 downto 0);
- rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ 156 MHz
+ -- 64 bit data @ 156 MHz
+ rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0);
rx_src_in_arr : in t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- PHY serial IO
@@ -166,10 +180,12 @@ begin
xaui_miso => xaui_miso,
-- ST
- tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ tx_clk_arr_in (156.25 MHz)
+ -- 64 bit data @ tx_clk_arr_in (156.25 MHz)
+ tx_snk_in_arr => tx_snk_in_arr,
tx_snk_out_arr => tx_snk_out_arr,
- rx_src_out_arr => rx_src_out_arr, -- 64 bit data @ rx_clk_arr (156.25 MHz)
+ -- 64 bit data @ rx_clk_arr (156.25 MHz)
+ rx_src_out_arr => rx_src_out_arr,
rx_src_in_arr => rx_src_in_arr,
-- Serial IO
@@ -207,10 +223,12 @@ begin
reg_eth10g_miso => reg_eth10g_miso,
-- ST
- tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ tr_ref_clk_156
+ -- 64 bit data @ tr_ref_clk_156
+ tx_snk_in_arr => tx_snk_in_arr,
tx_snk_out_arr => tx_snk_out_arr,
- rx_src_out_arr => rx_src_out_arr, -- 64 bit data @ tr_ref_clk_156
+ -- 64 bit data @ tr_ref_clk_156
+ rx_src_out_arr => rx_src_out_arr,
rx_src_in_arr => rx_src_in_arr,
-- Serial
@@ -251,10 +269,12 @@ begin
reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso => reg_10gbase_r_24_miso,
-- ST
- tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ tr_ref_clk_156
+ -- 64 bit data @ tr_ref_clk_156
+ tx_snk_in_arr => tx_snk_in_arr,
tx_snk_out_arr => tx_snk_out_arr,
- rx_src_out_arr => rx_src_out_arr, -- 64 bit data @ tr_ref_clk_156
+ -- 64 bit data @ tr_ref_clk_156
+ rx_src_out_arr => rx_src_out_arr,
rx_src_in_arr => rx_src_in_arr,
-- Serial
@@ -296,10 +316,12 @@ begin
reg_ip_arria10_e1sg_phy_10gbase_r_24_miso => reg_10gbase_r_24_miso,
-- ST
- tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ tr_ref_clk_156
+ -- 64 bit data @ tr_ref_clk_156
+ tx_snk_in_arr => tx_snk_in_arr,
tx_snk_out_arr => tx_snk_out_arr,
- rx_src_out_arr => rx_src_out_arr, -- 64 bit data @ tr_ref_clk_156
+ -- 64 bit data @ tr_ref_clk_156
+ rx_src_out_arr => rx_src_out_arr,
rx_src_in_arr => rx_src_in_arr,
-- Serial
@@ -341,10 +363,12 @@ begin
reg_ip_arria10_e2sg_phy_10gbase_r_24_miso => reg_10gbase_r_24_miso,
-- ST
- tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ tr_ref_clk_156
+ -- 64 bit data @ tr_ref_clk_156
+ tx_snk_in_arr => tx_snk_in_arr,
tx_snk_out_arr => tx_snk_out_arr,
- rx_src_out_arr => rx_src_out_arr, -- 64 bit data @ tr_ref_clk_156
+ -- 64 bit data @ tr_ref_clk_156
+ rx_src_out_arr => rx_src_out_arr,
rx_src_in_arr => rx_src_in_arr,
-- Serial
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd
index e24a5253edfcd33d3c2feda336b69c23ac56c335..d4370dd567e8c0917afe871e94062ca454c23996 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd
@@ -95,14 +95,17 @@ use work.tech_eth_10g_component_pkg.all;
entity tech_eth_10g_arria10 is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_pre_header_padding : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_644 : in std_logic := '0'; -- 644.531250 MHz for 10GBASE-R
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 : in std_logic := '0';
-- Data clocks
clk_312 : in std_logic := '0';
@@ -113,17 +116,21 @@ entity tech_eth_10g_arria10 is
mm_clk : in std_logic;
mm_rst : in std_logic;
- mac_mosi : in t_mem_mosi; -- MAG_10G (CSR)
+ -- MAG_10G (CSR)
+ mac_mosi : in t_mem_mosi;
mac_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi;
reg_eth10g_miso : out t_mem_miso;
-- ST
- tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0);
tx_snk_out_arr : out t_dp_siso_arr(g_nof_channels - 1 downto 0);
- rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0);
rx_src_in_arr : in t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- Serial
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd
index 2d23b34659fa8b9172bcf05a6038670d365e1a03..e51100462267f6200530c0f93548a8893da63f64 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd
@@ -95,15 +95,18 @@ use work.tech_eth_10g_component_pkg.all;
entity tech_eth_10g_arria10_e1sg is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_use_loopback : boolean := false;
g_pre_header_padding : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_644 : in std_logic := '0'; -- 644.531250 MHz for 10GBASE-R
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 : in std_logic := '0';
-- Data clocks
clk_312 : in std_logic := '0';
@@ -114,20 +117,24 @@ entity tech_eth_10g_arria10_e1sg is
mm_clk : in std_logic;
mm_rst : in std_logic;
- mac_mosi : in t_mem_mosi; -- MAG_10G (CSR)
+ -- MAG_10G (CSR)
+ mac_mosi : in t_mem_mosi;
mac_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi;
reg_eth10g_miso : out t_mem_miso;
reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_ip_arria10_e1sg_phy_10gbase_r_24_miso : out t_mem_miso;
-- ST
- tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0);
tx_snk_out_arr : out t_dp_siso_arr(g_nof_channels - 1 downto 0);
- rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0);
rx_src_in_arr : in t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- Serial
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10_e2sg.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10_e2sg.vhd
index e9d80d791d33f9c0d1964840b07eaf1c793acdf4..1e7ffb160cc0183450469650e81cda61b1c35cdb 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_arria10_e2sg.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10_e2sg.vhd
@@ -95,15 +95,18 @@ use work.tech_eth_10g_component_pkg.all;
entity tech_eth_10g_arria10_e2sg is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_use_loopback : boolean := false;
g_pre_header_padding : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_644 : in std_logic := '0'; -- 644.531250 MHz for 10GBASE-R
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 : in std_logic := '0';
-- Data clocks
clk_312 : in std_logic := '0';
@@ -114,20 +117,24 @@ entity tech_eth_10g_arria10_e2sg is
mm_clk : in std_logic;
mm_rst : in std_logic;
- mac_mosi : in t_mem_mosi; -- MAG_10G (CSR)
+ -- MAG_10G (CSR)
+ mac_mosi : in t_mem_mosi;
mac_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi;
reg_eth10g_miso : out t_mem_miso;
reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_ip_arria10_e2sg_phy_10gbase_r_24_miso : out t_mem_miso;
-- ST
- tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0);
tx_snk_out_arr : out t_dp_siso_arr(g_nof_channels - 1 downto 0);
- rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0);
rx_src_in_arr : in t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- Serial
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd
index fea1119601766b539b77af28bee4134d539762fc..1dd73b05b2a005f9fbc8bd29d35a57fd2ef72592 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd
@@ -95,14 +95,17 @@ use work.tech_eth_10g_component_pkg.all;
entity tech_eth_10g_arria10_e3sge3 is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_pre_header_padding : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_644 : in std_logic := '0'; -- 644.531250 MHz for 10GBASE-R
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 : in std_logic := '0';
-- Data clocks
clk_312 : in std_logic := '0';
@@ -113,20 +116,24 @@ entity tech_eth_10g_arria10_e3sge3 is
mm_clk : in std_logic;
mm_rst : in std_logic;
- mac_mosi : in t_mem_mosi; -- MAG_10G (CSR)
+ -- MAG_10G (CSR)
+ mac_mosi : in t_mem_mosi;
mac_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi;
reg_eth10g_miso : out t_mem_miso;
reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso : out t_mem_miso;
-- ST
- tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0);
tx_snk_out_arr : out t_dp_siso_arr(g_nof_channels - 1 downto 0);
- rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0);
rx_src_in_arr : in t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- Serial
diff --git a/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd b/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
index 0ccadb8a9b19a1b39a6393eee4b73d708e1bbe21..da391e7785b7d4840b87dc50ec0f112ccfdbbd7c 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
@@ -39,10 +39,14 @@ entity tech_eth_10g_clocks is
port (
-- Input clocks
-- . Reference
- tr_ref_clk_644 : in std_logic := 'X'; -- 10GBASE-R
- tr_ref_clk_312 : in std_logic := 'X'; -- 10GBASE-R
- tr_ref_clk_156 : in std_logic := 'X'; -- 10GBASE-R or XAUI
- tr_ref_rst_156 : in std_logic := 'X'; -- 10GBASE-R or XAUI
+ -- 10GBASE-R
+ tr_ref_clk_644 : in std_logic := 'X';
+ -- 10GBASE-R
+ tr_ref_clk_312 : in std_logic := 'X';
+ -- 10GBASE-R or XAUI
+ tr_ref_clk_156 : in std_logic := 'X';
+ -- 10GBASE-R or XAUI
+ tr_ref_rst_156 : in std_logic := 'X';
-- . XAUI
tx_rst_arr : in std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0');
diff --git a/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd b/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd
index 072c427e9cf4ec454f820899105722cf5889ecdc..9d62836870b6b8f1f445587c7e4f45acaf718f1e 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd
@@ -37,41 +37,50 @@ package tech_eth_10g_component_pkg is
component ip_stratixiv_eth_10g is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use XAUI IP; 1 = use fast serdes model
+ -- 0 = use XAUI IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_pre_header_padding : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_156 : in std_logic; -- 156.25 MHz for XAUI
+ -- 156.25 MHz for XAUI
+ tr_ref_clk_156 : in std_logic;
tr_ref_rst_156 : in std_logic;
-- Calibration & reconfig clock
cal_rec_clk : in std_logic;
-- Data clocks
- tx_clk_arr_in : in std_logic_vector(g_nof_channels - 1 downto 0); -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr_in or connect rx_clk_arr to tx_clk_arr_in
+ -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr_in or connect rx_clk_arr to tx_clk_arr_in
+ tx_clk_arr_in : in std_logic_vector(g_nof_channels - 1 downto 0);
tx_rst_arr_out : out std_logic_vector(g_nof_channels - 1 downto 0);
rx_clk_arr_out : out std_logic_vector(g_nof_channels - 1 downto 0);
- rx_clk_arr_in : in std_logic_vector(g_nof_channels - 1 downto 0); -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ rx_clk_arr_in : in std_logic_vector(g_nof_channels - 1 downto 0);
rx_rst_arr_out : out std_logic_vector(g_nof_channels - 1 downto 0);
-- MM
mm_clk : in std_logic;
mm_rst : in std_logic;
- mac_mosi : in t_mem_mosi; -- MAG_10G (CSR)
+ -- MAG_10G (CSR)
+ mac_mosi : in t_mem_mosi;
mac_miso : out t_mem_miso;
- xaui_mosi : in t_mem_mosi := c_mem_mosi_rst; -- XAUI control
+ -- XAUI control
+ xaui_mosi : in t_mem_mosi := c_mem_mosi_rst;
xaui_miso : out t_mem_miso;
-- ST
- tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ 156 MHz tx_clk_arr_in
+ -- 64 bit data @ 156 MHz tx_clk_arr_in
+ tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0);
tx_snk_out_arr : out t_dp_siso_arr(g_nof_channels - 1 downto 0);
- rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ 156 MHz rx_clk_arr_in
+ -- 64 bit data @ 156 MHz rx_clk_arr_in
+ rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0);
rx_src_in_arr : in t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- XAUI serial IO
@@ -87,14 +96,17 @@ package tech_eth_10g_component_pkg is
component ip_arria10_eth_10g is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_pre_header_padding : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_644 : in std_logic := '0'; -- 644.531250 MHz for 10GBASE-R
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 : in std_logic := '0';
-- Data clocks
clk_312 : in std_logic := '0';
@@ -105,17 +117,21 @@ package tech_eth_10g_component_pkg is
mm_clk : in std_logic;
mm_rst : in std_logic;
- mac_mosi : in t_mem_mosi; -- MAG_10G (CSR)
+ -- MAG_10G (CSR)
+ mac_mosi : in t_mem_mosi;
mac_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi;
reg_eth10g_miso : out t_mem_miso;
-- ST
- tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0);
tx_snk_out_arr : out t_dp_siso_arr(g_nof_channels - 1 downto 0);
- rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0);
rx_src_in_arr : in t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- Serial
@@ -130,14 +146,17 @@ package tech_eth_10g_component_pkg is
component ip_arria10_e3sge3_eth_10g is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_pre_header_padding : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_644 : in std_logic := '0'; -- 644.531250 MHz for 10GBASE-R
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 : in std_logic := '0';
-- Data clocks
clk_312 : in std_logic := '0';
@@ -148,20 +167,24 @@ package tech_eth_10g_component_pkg is
mm_clk : in std_logic;
mm_rst : in std_logic;
- mac_mosi : in t_mem_mosi; -- MAG_10G (CSR)
+ -- MAG_10G (CSR)
+ mac_mosi : in t_mem_mosi;
mac_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi;
reg_eth10g_miso : out t_mem_miso;
reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso : out t_mem_miso;
-- ST
- tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0);
tx_snk_out_arr : out t_dp_siso_arr(g_nof_channels - 1 downto 0);
- rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0);
rx_src_in_arr : in t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- Serial
@@ -177,15 +200,18 @@ package tech_eth_10g_component_pkg is
component ip_arria10_e1sg_eth_10g is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_use_loopback : boolean := false;
g_pre_header_padding : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_644 : in std_logic := '0'; -- 644.531250 MHz for 10GBASE-R
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 : in std_logic := '0';
-- Data clocks
clk_312 : in std_logic := '0';
@@ -196,20 +222,24 @@ package tech_eth_10g_component_pkg is
mm_clk : in std_logic;
mm_rst : in std_logic;
- mac_mosi : in t_mem_mosi; -- MAG_10G (CSR)
+ -- MAG_10G (CSR)
+ mac_mosi : in t_mem_mosi;
mac_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi;
reg_eth10g_miso : out t_mem_miso;
reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_ip_arria10_e1sg_phy_10gbase_r_24_miso : out t_mem_miso;
-- ST
- tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0);
tx_snk_out_arr : out t_dp_siso_arr(g_nof_channels - 1 downto 0);
- rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0);
rx_src_in_arr : in t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- Serial
@@ -225,15 +255,18 @@ package tech_eth_10g_component_pkg is
component ip_arria10_e2sg_eth_10g is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_use_loopback : boolean := false;
g_pre_header_padding : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_644 : in std_logic := '0'; -- 644.531250 MHz for 10GBASE-R
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 : in std_logic := '0';
-- Data clocks
clk_312 : in std_logic := '0';
@@ -244,20 +277,24 @@ package tech_eth_10g_component_pkg is
mm_clk : in std_logic;
mm_rst : in std_logic;
- mac_mosi : in t_mem_mosi; -- MAG_10G (CSR)
+ -- MAG_10G (CSR)
+ mac_mosi : in t_mem_mosi;
mac_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi;
reg_eth10g_miso : out t_mem_miso;
reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_ip_arria10_e2sg_phy_10gbase_r_24_miso : out t_mem_miso;
-- ST
- tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0);
tx_snk_out_arr : out t_dp_siso_arr(g_nof_channels - 1 downto 0);
- rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0);
rx_src_in_arr : in t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- Serial
diff --git a/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd b/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
index 39d77831af1a00069b3c41ab43095fbe2941f305..84946b4b6543806503e9392f06ced8ada8e55085 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
@@ -87,41 +87,50 @@ use work.tech_eth_10g_component_pkg.all;
entity tech_eth_10g_stratixiv is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use XAUI IP; 1 = use fast serdes model
+ -- 0 = use XAUI IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_pre_header_padding : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_156 : in std_logic; -- 156.25 MHz for XAUI
+ -- 156.25 MHz for XAUI
+ tr_ref_clk_156 : in std_logic;
tr_ref_rst_156 : in std_logic;
-- Calibration & reconfig clock
cal_rec_clk : in std_logic;
-- Data clocks
- tx_clk_arr_in : in std_logic_vector(g_nof_channels - 1 downto 0); -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr_in or connect rx_clk_arr to tx_clk_arr_in
+ -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr_in or connect rx_clk_arr to tx_clk_arr_in
+ tx_clk_arr_in : in std_logic_vector(g_nof_channels - 1 downto 0);
tx_rst_arr_out : out std_logic_vector(g_nof_channels - 1 downto 0);
rx_clk_arr_out : out std_logic_vector(g_nof_channels - 1 downto 0);
- rx_clk_arr_in : in std_logic_vector(g_nof_channels - 1 downto 0); -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ rx_clk_arr_in : in std_logic_vector(g_nof_channels - 1 downto 0);
rx_rst_arr_out : out std_logic_vector(g_nof_channels - 1 downto 0);
-- MM
mm_clk : in std_logic;
mm_rst : in std_logic;
- mac_mosi : in t_mem_mosi; -- MAG_10G (CSR)
+ -- MAG_10G (CSR)
+ mac_mosi : in t_mem_mosi;
mac_miso : out t_mem_miso;
- xaui_mosi : in t_mem_mosi := c_mem_mosi_rst; -- XAUI control
+ -- XAUI control
+ xaui_mosi : in t_mem_mosi := c_mem_mosi_rst;
xaui_miso : out t_mem_miso;
-- ST
- tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ 156 MHz tx_clk_arr_in
+ -- 64 bit data @ 156 MHz tx_clk_arr_in
+ tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0);
tx_snk_out_arr : out t_dp_siso_arr(g_nof_channels - 1 downto 0);
- rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ 156 MHz rx_clk_arr_in
+ -- 64 bit data @ 156 MHz rx_clk_arr_in
+ rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0);
rx_src_in_arr : in t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- XAUI serial IO
diff --git a/libraries/technology/fifo/tech_fifo_component_pkg.vhd b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
index d57f837edd08425727af72d22f2bdb0465058844..ead2546a23e41e3d8b2ad252d13ccf24e565c826 100644
--- a/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+++ b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
@@ -71,7 +71,8 @@ package tech_fifo_component_pkg is
component ip_stratixiv_fifo_dc_mixed_widths is
generic (
- g_nof_words : natural; -- FIFO size in nof wr_dat words
+ -- FIFO size in nof wr_dat words
+ g_nof_words : natural;
g_wrdat_w : natural;
g_rddat_w : natural
);
@@ -136,7 +137,8 @@ package tech_fifo_component_pkg is
component ip_arria10_fifo_dc_mixed_widths is
generic (
- g_nof_words : natural := 1024; -- FIFO size in nof wr_dat words
+ -- FIFO size in nof wr_dat words
+ g_nof_words : natural := 1024;
g_wrdat_w : natural := 20;
g_rddat_w : natural := 10
);
@@ -201,7 +203,8 @@ package tech_fifo_component_pkg is
component ip_arria10_e3sge3_fifo_dc_mixed_widths is
generic (
- g_nof_words : natural := 1024; -- FIFO size in nof wr_dat words
+ -- FIFO size in nof wr_dat words
+ g_nof_words : natural := 1024;
g_wrdat_w : natural := 20;
g_rddat_w : natural := 10
);
@@ -266,7 +269,8 @@ package tech_fifo_component_pkg is
component ip_arria10_e1sg_fifo_dc_mixed_widths is
generic (
- g_nof_words : natural := 1024; -- FIFO size in nof wr_dat words
+ -- FIFO size in nof wr_dat words
+ g_nof_words : natural := 1024;
g_wrdat_w : natural := 20;
g_rddat_w : natural := 10
);
@@ -331,7 +335,8 @@ package tech_fifo_component_pkg is
component ip_arria10_e2sg_fifo_dc_mixed_widths is
generic (
- g_nof_words : natural := 1024; -- FIFO size in nof wr_dat words
+ -- FIFO size in nof wr_dat words
+ g_nof_words : natural := 1024;
g_wrdat_w : natural := 20;
g_rddat_w : natural := 10
);
@@ -394,7 +399,8 @@ package tech_fifo_component_pkg is
component ip_ultrascale_fifo_dc_mixed_widths is
generic (
- g_nof_words : natural := 1024; -- FIFO size in nof wr_dat words
+ -- FIFO size in nof wr_dat words
+ g_nof_words : natural := 1024;
g_wrdat_w : natural := 20;
g_rddat_w : natural := 10
);
diff --git a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
index 502fb8bb3928f4cd7d919eb00534df44cfbe993b..62ab6708aca7f6700e4de7d4101da9d4a59be185 100644
--- a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
@@ -36,7 +36,8 @@ library ip_ultrascale_fifo_lib;
entity tech_fifo_dc_mixed_widths is
generic (
g_technology : natural := c_tech_select_default;
- g_nof_words : natural; -- FIFO size in nof wr_dat words
+ -- FIFO size in nof wr_dat words
+ g_nof_words : natural;
g_wrdat_w : natural;
g_rddat_w : natural
);
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
index c1a0615bb10603daafbcbbfceecb5cd6c38bed4d..9c6b5c3db3059dfa551d72d83a02b663a1eef5b0 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
@@ -37,10 +37,14 @@ entity tech_fpga_temp_sens is
g_technology : natural := c_tech_select_default
);
port (
- corectl : in std_logic := '0'; -- corectl.corectl
- eoc : out std_logic; -- eoc.eoc
- reset : in std_logic := '0'; -- reset.reset
- tempout : out std_logic_vector(9 downto 0) -- tempout.tempout
+ -- corectl.corectl
+ corectl : in std_logic := '0';
+ -- eoc.eoc
+ eoc : out std_logic;
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- tempout.tempout
+ tempout : out std_logic_vector(9 downto 0)
);
end tech_fpga_temp_sens;
@@ -49,40 +53,56 @@ begin
gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
u0 : ip_arria10_temp_sense
port map (
- corectl => corectl, -- corectl.corectl
- reset => reset, -- reset.reset
- tempout => tempout, -- tempout.tempout
- eoc => eoc -- eoc.eoc
+ -- corectl.corectl
+ corectl => corectl,
+ -- reset.reset
+ reset => reset,
+ -- tempout.tempout
+ tempout => tempout,
+ -- eoc.eoc
+ eoc => eoc
);
end generate;
gen_ip_arria10_e3sge3 : if g_technology = c_tech_arria10_e3sge3 generate
u0 : ip_arria10_e3sge3_temp_sense
port map (
- corectl => corectl, -- corectl.corectl
- reset => reset, -- reset.reset
- tempout => tempout, -- tempout.tempout
- eoc => eoc -- eoc.eoc
+ -- corectl.corectl
+ corectl => corectl,
+ -- reset.reset
+ reset => reset,
+ -- tempout.tempout
+ tempout => tempout,
+ -- eoc.eoc
+ eoc => eoc
);
end generate;
gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg generate
u0 : ip_arria10_e1sg_temp_sense
port map (
- corectl => corectl, -- corectl.corectl
- reset => reset, -- reset.reset
- tempout => tempout, -- tempout.tempout
- eoc => eoc -- eoc.eoc
+ -- corectl.corectl
+ corectl => corectl,
+ -- reset.reset
+ reset => reset,
+ -- tempout.tempout
+ tempout => tempout,
+ -- eoc.eoc
+ eoc => eoc
);
end generate;
gen_ip_arria10_e2sg : if g_technology = c_tech_arria10_e2sg generate
u0 : ip_arria10_e2sg_temp_sense
port map (
- corectl => corectl, -- corectl.corectl
- reset => reset, -- reset.reset
- tempout => tempout, -- tempout.tempout
- eoc => eoc -- eoc.eoc
+ -- corectl.corectl
+ corectl => corectl,
+ -- reset.reset
+ reset => reset,
+ -- tempout.tempout
+ tempout => tempout,
+ -- eoc.eoc
+ eoc => eoc
);
end generate;
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
index 8cf7fbc8d139f4031a7e20e0bf621e8509bb59a5..03a888ef323fe98f1db7a42b401a49fc6bb1f675 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
@@ -27,37 +27,53 @@ use IEEE.std_logic_1164.all;
package tech_fpga_temp_sens_component_pkg is
component ip_arria10_temp_sense is
port (
- corectl : in std_logic := '0'; -- corectl.corectl
- eoc : out std_logic; -- eoc.eoc
- reset : in std_logic := '0'; -- reset.reset
- tempout : out std_logic_vector(9 downto 0) -- tempout.tempout
+ -- corectl.corectl
+ corectl : in std_logic := '0';
+ -- eoc.eoc
+ eoc : out std_logic;
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- tempout.tempout
+ tempout : out std_logic_vector(9 downto 0)
);
end component;
component ip_arria10_e3sge3_temp_sense is
port (
- corectl : in std_logic := '0'; -- corectl.corectl
- eoc : out std_logic; -- eoc.eoc
- reset : in std_logic := '0'; -- reset.reset
- tempout : out std_logic_vector(9 downto 0) -- tempout.tempout
+ -- corectl.corectl
+ corectl : in std_logic := '0';
+ -- eoc.eoc
+ eoc : out std_logic;
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- tempout.tempout
+ tempout : out std_logic_vector(9 downto 0)
);
end component;
component ip_arria10_e1sg_temp_sense is
port (
- corectl : in std_logic := '0'; -- corectl.corectl
- eoc : out std_logic; -- eoc.eoc
- reset : in std_logic := '0'; -- reset.reset
- tempout : out std_logic_vector(9 downto 0) -- tempout.tempout
+ -- corectl.corectl
+ corectl : in std_logic := '0';
+ -- eoc.eoc
+ eoc : out std_logic;
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- tempout.tempout
+ tempout : out std_logic_vector(9 downto 0)
);
end component;
component ip_arria10_e2sg_temp_sense is
port (
- corectl : in std_logic := '0'; -- corectl.corectl
- eoc : out std_logic; -- eoc.eoc
- reset : in std_logic := '0'; -- reset.reset
- tempout : out std_logic_vector(9 downto 0) -- tempout.tempout
+ -- corectl.corectl
+ corectl : in std_logic := '0';
+ -- eoc.eoc
+ eoc : out std_logic;
+ -- reset.reset
+ reset : in std_logic := '0';
+ -- tempout.tempout
+ tempout : out std_logic_vector(9 downto 0)
);
end component;
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index 8b567885cdfd462038e41c4239fe8803077fec6a..402aaf1891c251b98ff5491c60d9eb588e3b5090 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -37,11 +37,16 @@ entity tech_fractional_pll_clk125 is
);
port (
areset : in std_logic := '0';
- inclk0 : in std_logic := '0'; -- 125 MHz
- c0 : out std_logic; -- 20 MHz
- c1 : out std_logic; -- 50 MHz
- c2 : out std_logic; -- 100 MHz
- c3 : out std_logic; -- 125 MHz
+ -- 125 MHz
+ inclk0 : in std_logic := '0';
+ -- 20 MHz
+ c0 : out std_logic;
+ -- 50 MHz
+ c1 : out std_logic;
+ -- 100 MHz
+ c2 : out std_logic;
+ -- 125 MHz
+ c3 : out std_logic;
locked : out std_logic
);
end tech_fractional_pll_clk125;
@@ -51,56 +56,88 @@ begin
gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
u0 : ip_arria10_fractional_pll_clk125
port map (
- outclk0 => c0, -- outclk0.clk
- outclk1 => c1, -- outclk1.clk
- outclk2 => c2, -- outclk2.clk
- outclk3 => c3, -- outclk3.clk
- pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
- pll_locked => locked, -- pll_locked.pll_locked
- pll_powerdown => areset, -- pll_powerdown.pll_powerdown
- pll_refclk0 => inclk0 -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 => c0,
+ -- outclk1.clk
+ outclk1 => c1,
+ -- outclk2.clk
+ outclk2 => c2,
+ -- outclk3.clk
+ outclk3 => c3,
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy => OPEN,
+ -- pll_locked.pll_locked
+ pll_locked => locked,
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown => areset,
+ -- pll_refclk0.clk
+ pll_refclk0 => inclk0
);
end generate;
gen_ip_arria10_e3sge3 : if g_technology = c_tech_arria10_e3sge3 generate
u0 : ip_arria10_e3sge3_fractional_pll_clk125
port map (
- outclk0 => c0, -- outclk0.clk
- outclk1 => c1, -- outclk1.clk
- outclk2 => c2, -- outclk2.clk
- outclk3 => c3, -- outclk3.clk
- pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
- pll_locked => locked, -- pll_locked.pll_locked
- pll_powerdown => areset, -- pll_powerdown.pll_powerdown
- pll_refclk0 => inclk0 -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 => c0,
+ -- outclk1.clk
+ outclk1 => c1,
+ -- outclk2.clk
+ outclk2 => c2,
+ -- outclk3.clk
+ outclk3 => c3,
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy => OPEN,
+ -- pll_locked.pll_locked
+ pll_locked => locked,
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown => areset,
+ -- pll_refclk0.clk
+ pll_refclk0 => inclk0
);
end generate;
gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg generate
u0 : ip_arria10_e1sg_fractional_pll_clk125
port map (
- outclk0 => c0, -- outclk0.clk
- outclk1 => c1, -- outclk1.clk
- outclk2 => c2, -- outclk2.clk
- outclk3 => c3, -- outclk3.clk
- pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
- pll_locked => locked, -- pll_locked.pll_locked
- pll_powerdown => areset, -- pll_powerdown.pll_powerdown
- pll_refclk0 => inclk0 -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 => c0,
+ -- outclk1.clk
+ outclk1 => c1,
+ -- outclk2.clk
+ outclk2 => c2,
+ -- outclk3.clk
+ outclk3 => c3,
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy => OPEN,
+ -- pll_locked.pll_locked
+ pll_locked => locked,
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown => areset,
+ -- pll_refclk0.clk
+ pll_refclk0 => inclk0
);
end generate;
gen_ip_arria10_e2sg : if g_technology = c_tech_arria10_e2sg generate
u0 : ip_arria10_e2sg_fractional_pll_clk125
port map (
- outclk0 => c0, -- outclk0.clk
- outclk1 => c1, -- outclk1.clk
- outclk2 => c2, -- outclk2.clk
- outclk3 => c3, -- outclk3.clk
- pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
- pll_locked => locked, -- pll_locked.pll_locked
- pll_powerdown => areset, -- pll_powerdown.pll_powerdown
- pll_refclk0 => inclk0 -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 => c0,
+ -- outclk1.clk
+ outclk1 => c1,
+ -- outclk2.clk
+ outclk2 => c2,
+ -- outclk3.clk
+ outclk3 => c3,
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy => OPEN,
+ -- pll_locked.pll_locked
+ pll_locked => locked,
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown => areset,
+ -- pll_refclk0.clk
+ pll_refclk0 => inclk0
);
end generate;
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index dde0319d8e1db86fb08217328ba7b05a5af32528..04412681eb98f16f1c6b71e5dd8fe2de1ef10698 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -37,10 +37,14 @@ entity tech_fractional_pll_clk200 is
);
port (
areset : in std_logic := '0';
- inclk0 : in std_logic := '0'; -- 200 MHz
- c0 : out std_logic; -- 200 MHz
- c1 : out std_logic; -- 200 MHz shifted 90 degrees
- c2 : out std_logic; -- 400 MHz
+ -- 200 MHz
+ inclk0 : in std_logic := '0';
+ -- 200 MHz
+ c0 : out std_logic;
+ -- 200 MHz shifted 90 degrees
+ c1 : out std_logic;
+ -- 400 MHz
+ c2 : out std_logic;
locked : out std_logic
);
end tech_fractional_pll_clk200;
@@ -50,52 +54,80 @@ begin
gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
u0 : ip_arria10_fractional_pll_clk200
port map (
- outclk0 => c0, -- outclk0.clk
- outclk1 => c1, -- outclk1.clk
- outclk2 => c2, -- outclk2.clk
- pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
- pll_locked => locked, -- pll_locked.pll_locked
- pll_powerdown => areset, -- pll_powerdown.pll_powerdown
- pll_refclk0 => inclk0 -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 => c0,
+ -- outclk1.clk
+ outclk1 => c1,
+ -- outclk2.clk
+ outclk2 => c2,
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy => OPEN,
+ -- pll_locked.pll_locked
+ pll_locked => locked,
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown => areset,
+ -- pll_refclk0.clk
+ pll_refclk0 => inclk0
);
end generate;
gen_ip_arria10_e3sge3 : if g_technology = c_tech_arria10_e3sge3 generate
u0 : ip_arria10_e3sge3_fractional_pll_clk200
port map (
- outclk0 => c0, -- outclk0.clk
- outclk1 => c1, -- outclk1.clk
- outclk2 => c2, -- outclk2.clk
- pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
- pll_locked => locked, -- pll_locked.pll_locked
- pll_powerdown => areset, -- pll_powerdown.pll_powerdown
- pll_refclk0 => inclk0 -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 => c0,
+ -- outclk1.clk
+ outclk1 => c1,
+ -- outclk2.clk
+ outclk2 => c2,
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy => OPEN,
+ -- pll_locked.pll_locked
+ pll_locked => locked,
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown => areset,
+ -- pll_refclk0.clk
+ pll_refclk0 => inclk0
);
end generate;
gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg generate
u0 : ip_arria10_e1sg_fractional_pll_clk200
port map (
- outclk0 => c0, -- outclk0.clk
- outclk1 => c1, -- outclk1.clk
- outclk2 => c2, -- outclk2.clk
- pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
- pll_locked => locked, -- pll_locked.pll_locked
- pll_powerdown => areset, -- pll_powerdown.pll_powerdown
- pll_refclk0 => inclk0 -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 => c0,
+ -- outclk1.clk
+ outclk1 => c1,
+ -- outclk2.clk
+ outclk2 => c2,
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy => OPEN,
+ -- pll_locked.pll_locked
+ pll_locked => locked,
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown => areset,
+ -- pll_refclk0.clk
+ pll_refclk0 => inclk0
);
end generate;
gen_ip_arria10_e2sg : if g_technology = c_tech_arria10_e2sg generate
u0 : ip_arria10_e2sg_fractional_pll_clk200
port map (
- outclk0 => c0, -- outclk0.clk
- outclk1 => c1, -- outclk1.clk
- outclk2 => c2, -- outclk2.clk
- pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
- pll_locked => locked, -- pll_locked.pll_locked
- pll_powerdown => areset, -- pll_powerdown.pll_powerdown
- pll_refclk0 => inclk0 -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 => c0,
+ -- outclk1.clk
+ outclk1 => c1,
+ -- outclk2.clk
+ outclk2 => c2,
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy => OPEN,
+ -- pll_locked.pll_locked
+ pll_locked => locked,
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown => areset,
+ -- pll_refclk0.clk
+ pll_refclk0 => inclk0
);
end generate;
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
index 15097276103c9e7b4003b2bc2111875d6f194cac..c77f27ff63abdc88cfda58a839913faa46dae281 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
@@ -32,27 +32,42 @@ package tech_fractional_pll_component_pkg is
component ip_arria10_fractional_pll_clk200 is
port
(
- outclk0 : out std_logic; -- outclk0.clk
- outclk1 : out std_logic; -- outclk1.clk
- outclk2 : out std_logic; -- outclk2.clk
- pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
- pll_locked : out std_logic; -- pll_locked.pll_locked
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
- pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 : out std_logic;
+ -- outclk1.clk
+ outclk1 : out std_logic;
+ -- outclk2.clk
+ outclk2 : out std_logic;
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy : out std_logic;
+ -- pll_locked.pll_locked
+ pll_locked : out std_logic;
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : in std_logic := '0';
+ -- pll_refclk0.clk
+ pll_refclk0 : in std_logic := '0'
);
end component;
component ip_arria10_fractional_pll_clk125 is
port
(
- outclk0 : out std_logic; -- outclk0.clk
- outclk1 : out std_logic; -- outclk1.clk
- outclk2 : out std_logic; -- outclk2.clk
- outclk3 : out std_logic; -- outclk2.clk
- pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
- pll_locked : out std_logic; -- pll_locked.pll_locked
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
- pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 : out std_logic;
+ -- outclk1.clk
+ outclk1 : out std_logic;
+ -- outclk2.clk
+ outclk2 : out std_logic;
+ -- outclk2.clk
+ outclk3 : out std_logic;
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy : out std_logic;
+ -- pll_locked.pll_locked
+ pll_locked : out std_logic;
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : in std_logic := '0';
+ -- pll_refclk0.clk
+ pll_refclk0 : in std_logic := '0'
);
end component;
@@ -63,27 +78,42 @@ package tech_fractional_pll_component_pkg is
component ip_arria10_e3sge3_fractional_pll_clk200 is
port
(
- outclk0 : out std_logic; -- outclk0.clk
- outclk1 : out std_logic; -- outclk1.clk
- outclk2 : out std_logic; -- outclk2.clk
- pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
- pll_locked : out std_logic; -- pll_locked.pll_locked
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
- pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 : out std_logic;
+ -- outclk1.clk
+ outclk1 : out std_logic;
+ -- outclk2.clk
+ outclk2 : out std_logic;
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy : out std_logic;
+ -- pll_locked.pll_locked
+ pll_locked : out std_logic;
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : in std_logic := '0';
+ -- pll_refclk0.clk
+ pll_refclk0 : in std_logic := '0'
);
end component;
component ip_arria10_e3sge3_fractional_pll_clk125 is
port
(
- outclk0 : out std_logic; -- outclk0.clk
- outclk1 : out std_logic; -- outclk1.clk
- outclk2 : out std_logic; -- outclk2.clk
- outclk3 : out std_logic; -- outclk2.clk
- pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
- pll_locked : out std_logic; -- pll_locked.pll_locked
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
- pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 : out std_logic;
+ -- outclk1.clk
+ outclk1 : out std_logic;
+ -- outclk2.clk
+ outclk2 : out std_logic;
+ -- outclk2.clk
+ outclk3 : out std_logic;
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy : out std_logic;
+ -- pll_locked.pll_locked
+ pll_locked : out std_logic;
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : in std_logic := '0';
+ -- pll_refclk0.clk
+ pll_refclk0 : in std_logic := '0'
);
end component;
@@ -94,27 +124,42 @@ package tech_fractional_pll_component_pkg is
component ip_arria10_e1sg_fractional_pll_clk200 is
port
(
- outclk0 : out std_logic; -- outclk0.clk
- outclk1 : out std_logic; -- outclk1.clk
- outclk2 : out std_logic; -- outclk2.clk
- pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
- pll_locked : out std_logic; -- pll_locked.pll_locked
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
- pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 : out std_logic;
+ -- outclk1.clk
+ outclk1 : out std_logic;
+ -- outclk2.clk
+ outclk2 : out std_logic;
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy : out std_logic;
+ -- pll_locked.pll_locked
+ pll_locked : out std_logic;
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : in std_logic := '0';
+ -- pll_refclk0.clk
+ pll_refclk0 : in std_logic := '0'
);
end component;
component ip_arria10_e1sg_fractional_pll_clk125 is
port
(
- outclk0 : out std_logic; -- outclk0.clk
- outclk1 : out std_logic; -- outclk1.clk
- outclk2 : out std_logic; -- outclk2.clk
- outclk3 : out std_logic; -- outclk2.clk
- pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
- pll_locked : out std_logic; -- pll_locked.pll_locked
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
- pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 : out std_logic;
+ -- outclk1.clk
+ outclk1 : out std_logic;
+ -- outclk2.clk
+ outclk2 : out std_logic;
+ -- outclk2.clk
+ outclk3 : out std_logic;
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy : out std_logic;
+ -- pll_locked.pll_locked
+ pll_locked : out std_logic;
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : in std_logic := '0';
+ -- pll_refclk0.clk
+ pll_refclk0 : in std_logic := '0'
);
end component;
@@ -125,27 +170,42 @@ package tech_fractional_pll_component_pkg is
component ip_arria10_e2sg_fractional_pll_clk200 is
port
(
- outclk0 : out std_logic; -- outclk0.clk
- outclk1 : out std_logic; -- outclk1.clk
- outclk2 : out std_logic; -- outclk2.clk
- pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
- pll_locked : out std_logic; -- pll_locked.pll_locked
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
- pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 : out std_logic;
+ -- outclk1.clk
+ outclk1 : out std_logic;
+ -- outclk2.clk
+ outclk2 : out std_logic;
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy : out std_logic;
+ -- pll_locked.pll_locked
+ pll_locked : out std_logic;
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : in std_logic := '0';
+ -- pll_refclk0.clk
+ pll_refclk0 : in std_logic := '0'
);
end component;
component ip_arria10_e2sg_fractional_pll_clk125 is
port
(
- outclk0 : out std_logic; -- outclk0.clk
- outclk1 : out std_logic; -- outclk1.clk
- outclk2 : out std_logic; -- outclk2.clk
- outclk3 : out std_logic; -- outclk2.clk
- pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
- pll_locked : out std_logic; -- pll_locked.pll_locked
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
- pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
+ -- outclk0.clk
+ outclk0 : out std_logic;
+ -- outclk1.clk
+ outclk1 : out std_logic;
+ -- outclk2.clk
+ outclk2 : out std_logic;
+ -- outclk2.clk
+ outclk3 : out std_logic;
+ -- pll_cal_busy.pll_cal_busy
+ pll_cal_busy : out std_logic;
+ -- pll_locked.pll_locked
+ pll_locked : out std_logic;
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown : in std_logic := '0';
+ -- pll_refclk0.clk
+ pll_refclk0 : in std_logic := '0'
);
end component;
diff --git a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
index fdae4b1c7207d6c56ef46ff17fc12afbfdc773df..1f4a352c0d77564328fe9c8e19e1222bc6df7a5b 100644
--- a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
@@ -70,7 +70,8 @@ package tech_iobuf_component_pkg is
port (
in_dat : in std_logic_vector(g_width - 1 downto 0);
in_clk : in std_logic;
- in_clk_en : in std_logic := '1'; -- Not Connected
+ -- Not Connected
+ in_clk_en : in std_logic := '1';
rst : in std_logic := '0';
out_dat_hi : out std_logic_vector(g_width - 1 downto 0);
out_dat_lo : out std_logic_vector(g_width - 1 downto 0)
@@ -84,7 +85,8 @@ package tech_iobuf_component_pkg is
port (
rst : in std_logic := '0';
in_clk : in std_logic;
- in_clk_en : in std_logic := '1'; -- Not Connected
+ -- Not Connected
+ in_clk_en : in std_logic := '1';
in_dat_hi : in std_logic_vector(g_width - 1 downto 0);
in_dat_lo : in std_logic_vector(g_width - 1 downto 0);
out_dat : out std_logic_vector(g_width - 1 downto 0)
@@ -102,7 +104,8 @@ package tech_iobuf_component_pkg is
port (
in_dat : in std_logic_vector(g_width - 1 downto 0);
in_clk : in std_logic;
- in_clk_en : in std_logic := '1'; -- Not Connected
+ -- Not Connected
+ in_clk_en : in std_logic := '1';
rst : in std_logic := '0';
out_dat_hi : out std_logic_vector(g_width - 1 downto 0);
out_dat_lo : out std_logic_vector(g_width - 1 downto 0)
@@ -116,7 +119,8 @@ package tech_iobuf_component_pkg is
port (
rst : in std_logic := '0';
in_clk : in std_logic;
- in_clk_en : in std_logic := '1'; -- Not Connected
+ -- Not Connected
+ in_clk_en : in std_logic := '1';
in_dat_hi : in std_logic_vector(g_width - 1 downto 0);
in_dat_lo : in std_logic_vector(g_width - 1 downto 0);
out_dat : out std_logic_vector(g_width - 1 downto 0)
@@ -134,7 +138,8 @@ package tech_iobuf_component_pkg is
port (
in_dat : in std_logic_vector(g_width - 1 downto 0);
in_clk : in std_logic;
- in_clk_en : in std_logic := '1'; -- Not Connected
+ -- Not Connected
+ in_clk_en : in std_logic := '1';
rst : in std_logic := '0';
out_dat_hi : out std_logic_vector(g_width - 1 downto 0);
out_dat_lo : out std_logic_vector(g_width - 1 downto 0)
@@ -148,7 +153,8 @@ package tech_iobuf_component_pkg is
port (
rst : in std_logic := '0';
in_clk : in std_logic;
- in_clk_en : in std_logic := '1'; -- Not Connected
+ -- Not Connected
+ in_clk_en : in std_logic := '1';
in_dat_hi : in std_logic_vector(g_width - 1 downto 0);
in_dat_lo : in std_logic_vector(g_width - 1 downto 0);
out_dat : out std_logic_vector(g_width - 1 downto 0)
@@ -166,7 +172,8 @@ package tech_iobuf_component_pkg is
port (
in_dat : in std_logic_vector(g_width - 1 downto 0);
in_clk : in std_logic;
- in_clk_en : in std_logic := '1'; -- Not Connected
+ -- Not Connected
+ in_clk_en : in std_logic := '1';
rst : in std_logic := '0';
out_dat_hi : out std_logic_vector(g_width - 1 downto 0);
out_dat_lo : out std_logic_vector(g_width - 1 downto 0)
@@ -180,7 +187,8 @@ package tech_iobuf_component_pkg is
port (
rst : in std_logic := '0';
in_clk : in std_logic;
- in_clk_en : in std_logic := '1'; -- Not Connected
+ -- Not Connected
+ in_clk_en : in std_logic := '1';
in_dat_hi : in std_logic_vector(g_width - 1 downto 0);
in_dat_lo : in std_logic_vector(g_width - 1 downto 0);
out_dat : out std_logic_vector(g_width - 1 downto 0)
diff --git a/libraries/technology/ip_arria10/complex_mult_rtl/ip_arria10_complex_mult_rtl.vhd b/libraries/technology/ip_arria10/complex_mult_rtl/ip_arria10_complex_mult_rtl.vhd
index 3cbb1f5c3d425824b1e1195c4a9f560f30e51eab..50365d99136eb7a7eea24da841a56de2b83a3c9f 100644
--- a/libraries/technology/ip_arria10/complex_mult_rtl/ip_arria10_complex_mult_rtl.vhd
+++ b/libraries/technology/ip_arria10/complex_mult_rtl/ip_arria10_complex_mult_rtl.vhd
@@ -41,12 +41,17 @@ entity ip_arria10_complex_mult_rtl is
generic (
g_in_a_w : positive;
g_in_b_w : positive;
- g_out_p_w : positive; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
+ -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
+ g_out_p_w : positive;
g_conjugate_b : boolean := false;
- g_pipeline_input : natural := 1; -- 0 or 1
- g_pipeline_product : natural := 0; -- 0 or 1
- g_pipeline_adder : natural := 1; -- 0 or 1
- g_pipeline_output : natural := 1 -- >= 0
+ -- 0 or 1
+ g_pipeline_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_product : natural := 0;
+ -- 0 or 1
+ g_pipeline_adder : natural := 1;
+ -- >= 0
+ g_pipeline_output : natural := 1
);
port (
rst : in std_logic := '0';
@@ -66,9 +71,11 @@ architecture str of ip_arria10_complex_mult_rtl is
begin
-- extend sign bit or keep LS part
if w > s'length then
- return resize(s, w); -- extend sign bit
+ -- extend sign bit
+ return resize(s, w);
else
- return signed(resize(unsigned(s), w)); -- keep LSbits (= vec[w-1:0])
+ -- keep LSbits (= vec[w-1:0])
+ return signed(resize(unsigned(s), w));
end if;
end;
@@ -83,9 +90,11 @@ architecture str of ip_arria10_complex_mult_rtl is
signal reg_ai : signed(g_in_a_w - 1 downto 0);
signal reg_br : signed(g_in_b_w - 1 downto 0);
signal reg_bi : signed(g_in_b_w - 1 downto 0);
- signal reg_prod_ar_br : signed(c_prod_w - 1 downto 0); -- re
+ -- re
+ signal reg_prod_ar_br : signed(c_prod_w - 1 downto 0);
signal reg_prod_ai_bi : signed(c_prod_w - 1 downto 0);
- signal reg_prod_ai_br : signed(c_prod_w - 1 downto 0); -- im
+ -- im
+ signal reg_prod_ai_br : signed(c_prod_w - 1 downto 0);
signal reg_prod_ar_bi : signed(c_prod_w - 1 downto 0);
signal reg_sum_re : signed(c_sum_w - 1 downto 0);
signal reg_sum_im : signed(c_sum_w - 1 downto 0);
@@ -97,9 +106,11 @@ architecture str of ip_arria10_complex_mult_rtl is
signal nxt_ai : signed(g_in_a_w - 1 downto 0);
signal nxt_br : signed(g_in_b_w - 1 downto 0);
signal nxt_bi : signed(g_in_b_w - 1 downto 0);
- signal nxt_prod_ar_br : signed(c_prod_w - 1 downto 0); -- re
+ -- re
+ signal nxt_prod_ar_br : signed(c_prod_w - 1 downto 0);
signal nxt_prod_ai_bi : signed(c_prod_w - 1 downto 0);
- signal nxt_prod_ai_br : signed(c_prod_w - 1 downto 0); -- im
+ -- im
+ signal nxt_prod_ai_br : signed(c_prod_w - 1 downto 0);
signal nxt_prod_ar_bi : signed(c_prod_w - 1 downto 0);
signal nxt_sum_re : signed(c_sum_w - 1 downto 0);
signal nxt_sum_im : signed(c_sum_w - 1 downto 0);
@@ -111,9 +122,11 @@ architecture str of ip_arria10_complex_mult_rtl is
signal ai : signed(g_in_a_w - 1 downto 0);
signal br : signed(g_in_b_w - 1 downto 0);
signal bi : signed(g_in_b_w - 1 downto 0);
- signal prod_ar_br : signed(c_prod_w - 1 downto 0); -- re
+ -- re
+ signal prod_ar_br : signed(c_prod_w - 1 downto 0);
signal prod_ai_bi : signed(c_prod_w - 1 downto 0);
- signal prod_ai_br : signed(c_prod_w - 1 downto 0); -- im
+ -- im
+ signal prod_ai_br : signed(c_prod_w - 1 downto 0);
signal prod_ar_bi : signed(c_prod_w - 1 downto 0);
signal sum_re : signed(c_sum_w - 1 downto 0);
signal sum_im : signed(c_sum_w - 1 downto 0);
@@ -141,17 +154,22 @@ begin
reg_result_re <= (others => '0');
reg_result_im <= (others => '0');
elsif clken = '1' then
- reg_ar <= nxt_ar; -- inputs
+ -- inputs
+ reg_ar <= nxt_ar;
reg_ai <= nxt_ai;
reg_br <= nxt_br;
reg_bi <= nxt_bi;
- reg_prod_ar_br <= nxt_prod_ar_br; -- products for re
+ -- products for re
+ reg_prod_ar_br <= nxt_prod_ar_br;
reg_prod_ai_bi <= nxt_prod_ai_bi;
- reg_prod_ai_br <= nxt_prod_ai_br; -- products for im
+ -- products for im
+ reg_prod_ai_br <= nxt_prod_ai_br;
reg_prod_ar_bi <= nxt_prod_ar_bi;
- reg_sum_re <= nxt_sum_re; -- sum
+ -- sum
+ reg_sum_re <= nxt_sum_re;
reg_sum_im <= nxt_sum_im;
- reg_result_re <= nxt_result_re; -- result sum after optional register stage
+ -- result sum after optional register stage
+ reg_result_re <= nxt_result_re;
reg_result_im <= nxt_result_im;
end if;
end if;
@@ -166,14 +184,16 @@ begin
nxt_br <= signed(in_br);
nxt_bi <= signed(in_bi);
- no_input_reg : if g_pipeline_input = 0 generate -- wired
+ -- wired
+ no_input_reg : if g_pipeline_input = 0 generate
ar <= nxt_ar;
ai <= nxt_ai;
br <= nxt_br;
bi <= nxt_bi;
end generate;
- gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ -- register input
+ gen_input_reg : if g_pipeline_input > 0 generate
ar <= reg_ar;
ai <= reg_ai;
br <= reg_br;
@@ -184,18 +204,22 @@ begin
-- Products
------------------------------------------------------------------------------
- nxt_prod_ar_br <= ar * br; -- products for re
+ -- products for re
+ nxt_prod_ar_br <= ar * br;
nxt_prod_ai_bi <= ai * bi;
- nxt_prod_ai_br <= ai * br; -- products for im
+ -- products for im
+ nxt_prod_ai_br <= ai * br;
nxt_prod_ar_bi <= ar * bi;
- no_product_reg : if g_pipeline_product = 0 generate -- wired
+ -- wired
+ no_product_reg : if g_pipeline_product = 0 generate
prod_ar_br <= nxt_prod_ar_br;
prod_ai_bi <= nxt_prod_ai_bi;
prod_ai_br <= nxt_prod_ai_br;
prod_ar_bi <= nxt_prod_ar_bi;
end generate;
- gen_product_reg : if g_pipeline_product > 0 generate -- register
+ -- register
+ gen_product_reg : if g_pipeline_product > 0 generate
prod_ar_br <= reg_prod_ar_br;
prod_ai_bi <= reg_prod_ai_bi;
prod_ai_br <= reg_prod_ai_br;
@@ -228,11 +252,13 @@ begin
nxt_sum_im <= RESIZE_NUM(prod_ai_br, c_sum_w) - prod_ar_bi;
end generate;
- no_adder_reg : if g_pipeline_adder = 0 generate -- wired
+ -- wired
+ no_adder_reg : if g_pipeline_adder = 0 generate
sum_re <= nxt_sum_re;
sum_im <= nxt_sum_im;
end generate;
- gen_adder_reg : if g_pipeline_adder > 0 generate -- register
+ -- register
+ gen_adder_reg : if g_pipeline_adder > 0 generate
sum_re <= reg_sum_re;
sum_im <= reg_sum_im;
end generate;
@@ -244,11 +270,13 @@ begin
nxt_result_re <= RESIZE_NUM(sum_re, g_out_p_w);
nxt_result_im <= RESIZE_NUM(sum_im, g_out_p_w);
- no_result_reg : if g_pipeline_output = 0 generate -- wired
+ -- wired
+ no_result_reg : if g_pipeline_output = 0 generate
result_re <= std_logic_vector(nxt_result_re);
result_im <= std_logic_vector(nxt_result_im);
end generate;
- gen_result_reg : if g_pipeline_output > 0 generate -- register
+ -- register
+ gen_result_reg : if g_pipeline_output > 0 generate
result_re <= std_logic_vector(reg_result_re);
result_im <= std_logic_vector(reg_result_im);
end generate;
diff --git a/libraries/technology/ip_arria10/complex_mult_rtl_canonical/ip_arria10_complex_mult_rtl_canonical.vhd b/libraries/technology/ip_arria10/complex_mult_rtl_canonical/ip_arria10_complex_mult_rtl_canonical.vhd
index 81d2df2351204a3c4006e3d91db51042707bf0c7..dfa6843aeabed4fe45ebcb965e3e58623fd5a476 100644
--- a/libraries/technology/ip_arria10/complex_mult_rtl_canonical/ip_arria10_complex_mult_rtl_canonical.vhd
+++ b/libraries/technology/ip_arria10/complex_mult_rtl_canonical/ip_arria10_complex_mult_rtl_canonical.vhd
@@ -37,12 +37,17 @@ entity ip_arria10_complex_mult_rtl_canonical is
generic (
g_in_a_w : positive;
g_in_b_w : positive;
- g_out_p_w : positive; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
+ -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
+ g_out_p_w : positive;
-- g_conjugate_b : BOOLEAN := FALSE;
- g_pipeline_input : natural := 1; -- 0 or 1
- g_pipeline_product : natural := 0; -- 0 or 1
- g_pipeline_adder : natural := 1; -- 0 or 1
- g_pipeline_output : natural := 1 -- >= 0
+ -- 0 or 1
+ g_pipeline_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_product : natural := 0;
+ -- 0 or 1
+ g_pipeline_adder : natural := 1;
+ -- >= 0
+ g_pipeline_output : natural := 1
);
port (
rst : in std_logic := '0';
@@ -62,9 +67,11 @@ architecture str of ip_arria10_complex_mult_rtl_canonical is
begin
-- extend sign bit or keep LS part
if w > s'length then
- return resize(s, w); -- extend sign bit
+ -- extend sign bit
+ return resize(s, w);
else
- return signed(resize(unsigned(s), w)); -- keep LSbits (= vec[w-1:0])
+ -- keep LSbits (= vec[w-1:0])
+ return signed(resize(unsigned(s), w));
end if;
end;
@@ -82,23 +89,38 @@ architecture str of ip_arria10_complex_mult_rtl_canonical is
-- . re = ((ar+ai)*(br-bi))+(ar*bi-ai*br)
-- im = ar*bi+ai*br
-----------------------------------------------------------------------------
- constant c_sum_ar_ai_w : natural := g_in_a_w + 1; -- sum_ar_ai
- constant c_sum_br_bi_w : natural := g_in_b_w + 1; -- sum_br_bi
- constant c_prod_w : natural := g_in_a_w + g_in_b_w; -- prod_ar_bi, prod_ai_br
- constant c_sum_prod_w : natural := c_prod_w + 1; -- sum_prod_ar_bi_prod_ai_br
- constant c_prod_sum_w : natural := c_sum_ar_ai_w + c_sum_br_bi_w; -- prod_sum_ar_ai_sum_br_bi
- constant c_sum_im_w : natural := c_prod_w + 1; -- sum_im
- constant c_sum_re_w : natural := largest(c_sum_prod_w, c_prod_sum_w) + 1; -- sum_re
-
- signal sum_ar_ai : signed(c_sum_ar_ai_w - 1 downto 0); -- ar+ai : used in re
- signal sum_br_bi : signed(c_sum_br_bi_w - 1 downto 0); -- br-bi : used in re
- signal sum_prod_ar_bi_prod_ai_br : signed(c_sum_prod_w - 1 downto 0); -- ar*bi-ai*br : used in re
- signal sum_im : signed(c_sum_im_w - 1 downto 0); -- ar*bi+ai*br : im
- signal sum_re : signed(c_sum_re_w - 1 downto 0); -- ((ar+ai)*(br-bi))+(ar*bi-ai*br) : re
-
- signal prod_ar_bi : signed(c_prod_w - 1 downto 0); -- ar*bi : used in re and im
- signal prod_ai_br : signed(c_prod_w - 1 downto 0); -- ai*br : used in re and im
- signal prod_sum_ar_ai_sum_br_bi : signed(c_prod_sum_w - 1 downto 0); -- (ar+ai)*(br-bi) : used in re
+ -- sum_ar_ai
+ constant c_sum_ar_ai_w : natural := g_in_a_w + 1;
+ -- sum_br_bi
+ constant c_sum_br_bi_w : natural := g_in_b_w + 1;
+ -- prod_ar_bi, prod_ai_br
+ constant c_prod_w : natural := g_in_a_w + g_in_b_w;
+ -- sum_prod_ar_bi_prod_ai_br
+ constant c_sum_prod_w : natural := c_prod_w + 1;
+ -- prod_sum_ar_ai_sum_br_bi
+ constant c_prod_sum_w : natural := c_sum_ar_ai_w + c_sum_br_bi_w;
+ -- sum_im
+ constant c_sum_im_w : natural := c_prod_w + 1;
+ -- sum_re
+ constant c_sum_re_w : natural := largest(c_sum_prod_w, c_prod_sum_w) + 1;
+
+ -- ar+ai : used in re
+ signal sum_ar_ai : signed(c_sum_ar_ai_w - 1 downto 0);
+ -- br-bi : used in re
+ signal sum_br_bi : signed(c_sum_br_bi_w - 1 downto 0);
+ -- ar*bi-ai*br : used in re
+ signal sum_prod_ar_bi_prod_ai_br : signed(c_sum_prod_w - 1 downto 0);
+ -- ar*bi+ai*br : im
+ signal sum_im : signed(c_sum_im_w - 1 downto 0);
+ -- ((ar+ai)*(br-bi))+(ar*bi-ai*br) : re
+ signal sum_re : signed(c_sum_re_w - 1 downto 0);
+
+ -- ar*bi : used in re and im
+ signal prod_ar_bi : signed(c_prod_w - 1 downto 0);
+ -- ai*br : used in re and im
+ signal prod_ai_br : signed(c_prod_w - 1 downto 0);
+ -- (ar+ai)*(br-bi) : used in re
+ signal prod_sum_ar_ai_sum_br_bi : signed(c_prod_sum_w - 1 downto 0);
-----------------------------------------------------------------------------
-- register signals
@@ -195,14 +217,16 @@ begin
nxt_br <= signed(in_br);
nxt_bi <= signed(in_bi);
- no_input_reg : if g_pipeline_input = 0 generate -- wired
+ -- wired
+ no_input_reg : if g_pipeline_input = 0 generate
ar <= nxt_ar;
ai <= nxt_ai;
br <= nxt_br;
bi <= nxt_bi;
end generate;
- gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ -- register input
+ gen_input_reg : if g_pipeline_input > 0 generate
ar <= reg_ar;
ai <= reg_ai;
br <= reg_br;
@@ -218,14 +242,16 @@ begin
nxt_sum_re <= RESIZE_NUM(prod_sum_ar_ai_sum_br_bi, c_prod_sum_w), sum_prod_ar_bi_prod_ai_br;
nxt_sum_im <= RESIZE_NUM(prod_ai_br, c_sum_im_w) + prod_ar_bi;
- no_adder_reg : if g_pipeline_adder = 0 generate -- wired
+ -- wired
+ no_adder_reg : if g_pipeline_adder = 0 generate
sum_ar_ai <= nxt_sum_ar_ai;
sum_br_bi <= nxt_sum_br_bi;
sum_prod_ar_bi_prod_ai_br <= nxt_sum_prod_ar_bi_prod_ai_br;
sum_re <= nxt_sum_re;
sum_im <= nxt_sum_im;
end generate;
- gen_adder_reg : if g_pipeline_adder > 0 generate -- register
+ -- register
+ gen_adder_reg : if g_pipeline_adder > 0 generate
sum_ar_ai <= reg_sum_ar_ai;
sum_br_bi <= reg_sum_br_bi;
sum_prod_ar_bi_prod_ai_br <= reg_sum_prod_ar_bi_prod_ai_br;
@@ -240,12 +266,14 @@ begin
nxt_prod_ai_br <= ai * br;
nxt_prod_sum_ar_ai_sum_br_bi <= sum_ar_ai * sum_br_bi;
- no_product_reg : if g_pipeline_product = 0 generate -- wired
+ -- wired
+ no_product_reg : if g_pipeline_product = 0 generate
prod_ar_bi <= nxt_prod_ar_bi;
prod_ai_br <= nxt_prod_ai_br;
prod_sum_ar_ai_sum_br_bi <= nxt_prod_sum_ar_ai_sum_br_bi;
end generate;
- gen_product_reg : if g_pipeline_product > 0 generate -- register
+ -- register
+ gen_product_reg : if g_pipeline_product > 0 generate
prod_ar_bi <= reg_prod_ar_bi;
prod_ai_br <= reg_prod_ai_br;
prod_sum_ar_ai_sum_br_bi <= reg_prod_sum_ar_ai_sum_br_bi;
@@ -258,11 +286,13 @@ begin
nxt_result_re <= RESIZE_NUM(sum_re, g_out_p_w);
nxt_result_im <= RESIZE_NUM(sum_im, g_out_p_w);
- no_result_reg : if g_pipeline_output = 0 generate -- wired
+ -- wired
+ no_result_reg : if g_pipeline_output = 0 generate
result_re <= std_logic_vector(nxt_result_re);
result_im <= std_logic_vector(nxt_result_im);
end generate;
- gen_result_reg : if g_pipeline_output > 0 generate -- register
+ -- register
+ gen_result_reg : if g_pipeline_output > 0 generate
result_re <= std_logic_vector(reg_result_re);
result_im <= std_logic_vector(reg_result_im);
end generate;
diff --git a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in.vhd b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in.vhd
index 7f7d4131f30810e479145aed1676b67f10987f72..0f7fcc808c1ffe029bb58d9e70c24a719a3b96a1 100644
--- a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in.vhd
+++ b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in.vhd
@@ -31,7 +31,8 @@ entity ip_arria10_ddio_in is
port (
in_dat : in std_logic_vector(g_width - 1 downto 0);
in_clk : in std_logic;
- in_clk_en : in std_logic := '1'; -- Not Connected
+ -- Not Connected
+ in_clk_en : in std_logic := '1';
rst : in std_logic := '0';
out_dat_hi : out std_logic_vector(g_width - 1 downto 0);
out_dat_lo : out std_logic_vector(g_width - 1 downto 0)
@@ -41,11 +42,16 @@ end ip_arria10_ddio_in;
architecture str of ip_arria10_ddio_in is
component ip_arria10_ddio_in_1 is
port (
- datain : in std_logic_vector(0 downto 0) := (others => '0'); -- pad_in.export
- inclock : in std_logic := '0'; -- ck.export
- aclr : in std_logic := '0'; -- aclr.export
- dataout_h : out std_logic_vector(0 downto 0); -- dataout_h.fragment
- dataout_l : out std_logic_vector(0 downto 0) -- dataout_l.fragment
+ -- pad_in.export
+ datain : in std_logic_vector(0 downto 0) := (others => '0');
+ -- ck.export
+ inclock : in std_logic := '0';
+ -- aclr.export
+ aclr : in std_logic := '0';
+ -- dataout_h.fragment
+ dataout_h : out std_logic_vector(0 downto 0);
+ -- dataout_l.fragment
+ dataout_l : out std_logic_vector(0 downto 0)
);
end component;
begin
diff --git a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out.vhd b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out.vhd
index 6b0f88ced42c69b1fe45b016ebcc85730ac237f1..1eb37dc26ee4bc02f9bc7415dd6d3baf078fd719 100644
--- a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out.vhd
+++ b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out.vhd
@@ -31,7 +31,8 @@ entity ip_arria10_ddio_out is
port (
rst : in std_logic := '0';
in_clk : in std_logic;
- in_clk_en : in std_logic := '1'; -- Not Connected
+ -- Not Connected
+ in_clk_en : in std_logic := '1';
in_dat_hi : in std_logic_vector(g_width - 1 downto 0);
in_dat_lo : in std_logic_vector(g_width - 1 downto 0);
out_dat : out std_logic_vector(g_width - 1 downto 0)
@@ -41,11 +42,16 @@ end ip_arria10_ddio_out;
architecture str of ip_arria10_ddio_out is
component ip_arria10_ddio_out_1 is
port (
- dataout : out std_logic_vector(0 downto 0); -- pad_out.export
- outclock : in std_logic := '0'; -- ck.export
- aclr : in std_logic := '0'; -- aclr.export
- datain_h : in std_logic_vector(0 downto 0) := (others => '0'); -- datain_h.fragment
- datain_l : in std_logic_vector(0 downto 0) := (others => '0') -- datain_l.fragment
+ -- pad_out.export
+ dataout : out std_logic_vector(0 downto 0);
+ -- ck.export
+ outclock : in std_logic := '0';
+ -- aclr.export
+ aclr : in std_logic := '0';
+ -- datain_h.fragment
+ datain_h : in std_logic_vector(0 downto 0) := (others => '0');
+ -- datain_l.fragment
+ datain_l : in std_logic_vector(0 downto 0) := (others => '0')
);
end component;
begin
diff --git a/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd b/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
index fc6617c765cf6177599a987ff14b82b243b2e408..2b024325a580645bae661adc458a5f0e628a2743 100644
--- a/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
+++ b/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
@@ -94,14 +94,17 @@ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
entity ip_arria10_eth_10g is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_pre_header_padding : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_644 : in std_logic := '0'; -- 644.531250 MHz for 10GBASE-R
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 : in std_logic := '0';
-- Data clocks
clk_312 : in std_logic := '0';
@@ -112,17 +115,21 @@ entity ip_arria10_eth_10g is
mm_clk : in std_logic;
mm_rst : in std_logic;
- mac_mosi : in t_mem_mosi; -- MAG_10G (CSR)
+ -- MAG_10G (CSR)
+ mac_mosi : in t_mem_mosi;
mac_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi;
reg_eth10g_miso : out t_mem_miso;
-- ST
- tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0);
tx_snk_out_arr : out t_dp_siso_arr(g_nof_channels - 1 downto 0);
- rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0);
rx_src_in_arr : in t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- Serial
@@ -146,11 +153,16 @@ architecture str of ip_arria10_eth_10g is
signal mac_snk_out_arr : t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- XGMII
- signal xgmii_link_status_arr : t_tech_mac_10g_xgmii_status_arr(g_nof_channels - 1 downto 0); -- 2 bit, from MAC_10g
- signal xgmii_tx_ready_arr : std_logic_vector(g_nof_channels - 1 downto 0); -- 1 bit, from PHY 10gbase_r
- signal xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
- signal xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
- signal xgmii_internal_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
+ -- 2 bit, from MAC_10g
+ signal xgmii_link_status_arr : t_tech_mac_10g_xgmii_status_arr(g_nof_channels - 1 downto 0);
+ -- 1 bit, from PHY 10gbase_r
+ signal xgmii_tx_ready_arr : std_logic_vector(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ signal xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ signal xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ signal xgmii_internal_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
-- Link status monitor
constant c_mem_reg_eth10g_adr_w : natural := 1;
@@ -166,7 +178,8 @@ begin
tx_snk_out_arr <= i_tx_snk_out_arr;
gen_mac : for I in 0 to g_nof_channels - 1 generate
- i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
+ -- pass on MAC cycle accurate backpressure
+ i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready;
p_xon_flow_control : process(clk_156)
variable v_xgmii_link_status : std_logic_vector(c_tech_mac_10g_link_status_w - 1 downto 0) := "00";
@@ -176,12 +189,14 @@ begin
i_tx_snk_out_arr(I).xon <= '0';
-- First gather all conditions that are enabled to affect xon. The default value is such that it enables xon when the condition is not checked.
- if c_check_link_status = true then v_xgmii_link_status := xgmii_link_status_arr(I); end if; -- check both remote fault [1] and local fault [0]
+ -- check both remote fault [1] and local fault [0]
+ if c_check_link_status = true then v_xgmii_link_status := xgmii_link_status_arr(I); end if;
if c_check_xgmii_tx_ready = true then v_xgmii_tx_ready := xgmii_tx_ready_arr(I); end if;
-- Now apply the conditions to xon
if v_xgmii_tx_ready = '1' and v_xgmii_link_status = "00" then
- i_tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
+ -- XON when Tx PHY is ready and XGMII is ok
+ i_tx_snk_out_arr(I).xon <= '1';
end if;
end if;
end process;
@@ -202,13 +217,15 @@ begin
tx_clk_312 => clk_312,
tx_clk_156 => clk_156,
tx_rst => rst_156,
- tx_snk_in => tx_snk_in_arr(I), -- 64 bit data
+ -- 64 bit data
+ tx_snk_in => tx_snk_in_arr(I),
tx_snk_out => mac_snk_out_arr(I),
rx_clk_312 => clk_312,
rx_clk_156 => clk_156,
rx_rst => rst_156,
- rx_src_out => rx_src_out_arr(I), -- 64 bit data
+ -- 64 bit data
+ rx_src_out => rx_src_out_arr(I),
rx_src_in => rx_src_in_arr(I),
-- XGMII
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd
index 89f1521773138d3276a043bf90a8fb37c02c9d54..8bcdbd98175a447dea6dc930eb0e8ef281e112ac 100644
--- a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd
@@ -34,7 +34,8 @@ use altera_mf.all;
entity ip_arria10_fifo_dc_mixed_widths is
generic (
- g_nof_words : natural := 1024; -- FIFO size in nof wr_dat words
+ -- FIFO size in nof wr_dat words
+ g_nof_words : natural := 1024;
g_wrdat_w : natural := 20;
g_rddat_w : natural := 10
);
diff --git a/libraries/technology/ip_arria10/mult/ip_arria10_mult.vhd b/libraries/technology/ip_arria10/mult/ip_arria10_mult.vhd
index 51fe57d1d22f8ee5d49ce21bd958de4068ffffcf..601c6b2c1dbeaeea05b52980e9f8eb373694cf18 100644
--- a/libraries/technology/ip_arria10/mult/ip_arria10_mult.vhd
+++ b/libraries/technology/ip_arria10/mult/ip_arria10_mult.vhd
@@ -11,15 +11,23 @@ use lpm.lpm_components.all;
-- . Strangely the MegaWizard does not support setting the rounding and saturation mode
entity ip_arria10_mult is
generic (
- g_in_a_w : positive := 18; -- Width of the data A port
- g_in_b_w : positive := 18; -- Width of the data B port
- g_out_p_w : positive := 36; -- Width of the result port
+ -- Width of the data A port
+ g_in_a_w : positive := 18;
+ -- Width of the data B port
+ g_in_b_w : positive := 18;
+ -- Width of the result port
+ g_out_p_w : positive := 36;
-- g_out_s_w : POSITIVE := 1; -- Width of the sum port (not used in current designs)
- g_nof_mult : positive := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
- g_pipeline_input : natural := 1; -- 0 or 1
- g_pipeline_product : natural := 1; -- 0 or 1
- g_pipeline_output : natural := 1; -- >= 0
- g_representation : string := "SIGNED" -- or "UNSIGNED"
+ -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+ g_nof_mult : positive := 1;
+ -- 0 or 1
+ g_pipeline_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_product : natural := 1;
+ -- >= 0
+ g_pipeline_output : natural := 1;
+ -- or "UNSIGNED"
+ g_representation : string := "SIGNED"
);
port (
clk : in std_logic;
@@ -44,7 +52,8 @@ begin
gen_mult : for I in 0 to g_nof_mult - 1 generate
m : lpm_mult
generic map (
- lpm_hint => "MAXIMIZE_SPEED=5", -- default "UNUSED"
+ -- default "UNUSED"
+ lpm_hint => "MAXIMIZE_SPEED=5",
lpm_pipeline => c_pipeline,
lpm_representation => g_representation,
lpm_type => "LPM_MULT",
diff --git a/libraries/technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd b/libraries/technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd
index d8ed3b0ed990455a47ea2eb759de52af74d8a52e..8de5c9b33f829a83279f4ddfbab8d3f9a1ede148 100644
--- a/libraries/technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd
+++ b/libraries/technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd
@@ -28,12 +28,18 @@ use IEEE.numeric_std.all;
generic (
g_in_a_w : positive := 18;
g_in_b_w : positive := 18;
- g_out_p_w : positive := 36; -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
- g_nof_mult : positive := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
- g_pipeline_input : natural := 1; -- 0 or 1
- g_pipeline_product : natural := 1; -- 0 or 1
- g_pipeline_output : natural := 1; -- >= 0
- g_representation : string := "SIGNED" -- or "UNSIGNED"
+ -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
+ g_out_p_w : positive := 36;
+ -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+ g_nof_mult : positive := 1;
+ -- 0 or 1
+ g_pipeline_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_product : natural := 1;
+ -- >= 0
+ g_pipeline_output : natural := 1;
+ -- or "UNSIGNED"
+ g_representation : string := "SIGNED"
);
port (
rst : in std_logic;
@@ -63,8 +69,10 @@ architecture str of ip_arria10_mult_rtl is
-- the active signals
signal inp_a : std_logic_vector(in_a'range);
signal inp_b : std_logic_vector(in_b'range);
- signal prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0); -- stage dependent on g_pipeline_product being 0 or 1
- signal result : std_logic_vector(out_p'range); -- stage dependent on g_pipeline_output being 0 or 1
+ -- stage dependent on g_pipeline_product being 0 or 1
+ signal prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0);
+ -- stage dependent on g_pipeline_output being 0 or 1
+ signal result : std_logic_vector(out_p'range);
begin
------------------------------------------------------------------------------
-- Registers
@@ -96,12 +104,14 @@ begin
nxt_a <= in_a;
nxt_b <= in_b;
- no_input_reg : if g_pipeline_input = 0 generate -- wired
+ -- wired
+ no_input_reg : if g_pipeline_input = 0 generate
inp_a <= nxt_a;
inp_b <= nxt_b;
end generate;
- gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ -- register input
+ gen_input_reg : if g_pipeline_input > 0 generate
inp_a <= reg_a;
inp_b <= reg_b;
end generate;
@@ -116,10 +126,12 @@ begin
std_logic_vector(unsigned(inp_a((I + 1) * g_in_a_w - 1 downto I * g_in_a_w)) * unsigned(inp_b((I + 1) * g_in_b_w - 1 downto I * g_in_b_w)));
end generate;
- no_product_reg : if g_pipeline_product = 0 generate -- wired
+ -- wired
+ no_product_reg : if g_pipeline_product = 0 generate
prod <= nxt_prod;
end generate;
- gen_product_reg : if g_pipeline_product > 0 generate -- register
+ -- register
+ gen_product_reg : if g_pipeline_product > 0 generate
prod <= reg_prod;
end generate;
@@ -128,10 +140,12 @@ begin
------------------------------------------------------------------------------
nxt_result <= prod;
- no_result_reg : if g_pipeline_output = 0 generate -- wired
+ -- wired
+ no_result_reg : if g_pipeline_output = 0 generate
result <= nxt_result;
end generate;
- gen_result_reg : if g_pipeline_output > 0 generate -- register
+ -- register
+ gen_result_reg : if g_pipeline_output > 0 generate
result <= reg_result;
end generate;
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
index 4b51cd15a06847f7c216cc4588813715153dd7f4..05298a515179eca39b4559ec922b4959d5826211 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
@@ -35,7 +35,8 @@ entity ip_arria10_ram_cr_cw is
g_adr_w : natural := 5;
g_dat_w : natural := 8;
g_nof_words : natural := 2**5;
- g_rd_latency : natural := 1; -- choose 1 or 2
+ -- choose 1 or 2
+ g_rd_latency : natural := 1;
g_init_file : string := "UNUSED"
);
port
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
index 2b65b1aa03ad78063c79c7caac67c07e644cd29f..32804fd786566e8601f1f768ee93a0f57ad88dc2 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
@@ -35,7 +35,8 @@ entity ip_arria10_ram_crw_crw is
g_adr_w : natural := 5;
g_dat_w : natural := 8;
g_nof_words : natural := 2**5;
- g_rd_latency : natural := 1; -- choose 1 or 2
+ -- choose 1 or 2
+ g_rd_latency : natural := 1;
g_init_file : string := "UNUSED"
);
port
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
index 48d8ca9c1122a36bbcf0930cb67116b249c7f532..551d43e51c7346adc32241c9d804affc73a6093d 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
@@ -25,7 +25,8 @@ entity ip_arria10_ram_crwk_crw is
g_dat_b_w : natural := 64;
g_nof_words_a : natural := 2**5;
g_nof_words_b : natural := 2**4;
- g_rd_latency : natural := 1; -- choose 1 or 2
+ -- choose 1 or 2
+ g_rd_latency : natural := 1;
g_init_file : string := "UNUSED"
);
port
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
index 0880d2e81bb6bf8a208c46adf00d3cd7c222fab5..2361d54dce04272e18d8146566c3d8b2a76ffe5f 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
@@ -35,7 +35,8 @@ entity ip_arria10_ram_r_w is
g_adr_w : natural := 5;
g_dat_w : natural := 8;
g_nof_words : natural := 2**5;
- g_rd_latency : natural := 1; -- choose 1 or 2
+ -- choose 1 or 2
+ g_rd_latency : natural := 1;
g_init_file : string := "UNUSED"
);
port (
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx.vhd b/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx.vhd
index cd1d8282ea9efc49c1ff24907b92285f04c5aafa..f695b75c1f3b8c0b363c6615a7f9a56b5ac20e5c 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx.vhd
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx.vhd
@@ -36,24 +36,37 @@ entity tb_ip_arria10_tse_sgmii_gx is
end tb_ip_arria10_tse_sgmii_gx;
architecture tb of tb_ip_arria10_tse_sgmii_gx is
- constant sys_clk_period : time := 10 ns; -- 100 MHz
- constant eth_clk_period : time := 8 ns; -- 125 MHz
- constant serial_clk_period : time := 800 ps; -- 1250 MHz ????
- constant cdr_clk_period : time := 8000 ps; -- 125 MHz ????
-
- constant c_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
+ -- 100 MHz
+ constant sys_clk_period : time := 10 ns;
+ -- 125 MHz
+ constant eth_clk_period : time := 8 ns;
+ -- 1250 MHz ????
+ constant serial_clk_period : time := 800 ps;
+ -- 125 MHz ????
+ constant cdr_clk_period : time := 8000 ps;
+
+ -- = max 256 MAC registers
+ constant c_tse_reg_addr_w : natural := 8;
constant c_tse_byte_addr_w : natural := c_tse_reg_addr_w + 2;
- constant c_tse_byte_addr_pcs_offset : natural := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
- constant c_tse_data_w : natural := c_word_w; -- = 32
-
- constant c_tse_symbol_w : natural := c_byte_w; -- = 8
- constant c_tse_symbol_max : natural := 2**c_tse_symbol_w - 1; -- = 255
- constant c_tse_symbols_per_beat : natural := c_tse_data_w / c_tse_symbol_w; -- = 4
-
- constant c_tse_pcs_reg_addr_w : natural := 5; -- = max 32 PCS registers
- constant c_tse_pcs_halfword_addr_w : natural := c_tse_pcs_reg_addr_w + 1; -- table 4.17 in ug_ethernet.pdf
+ -- table 4.8, 4.9 in ug_ethernet.pdf
+ constant c_tse_byte_addr_pcs_offset : natural := 16#200#;
+ -- = 32
+ constant c_tse_data_w : natural := c_word_w;
+
+ -- = 8
+ constant c_tse_symbol_w : natural := c_byte_w;
+ -- = 255
+ constant c_tse_symbol_max : natural := 2**c_tse_symbol_w - 1;
+ -- = 4
+ constant c_tse_symbols_per_beat : natural := c_tse_data_w / c_tse_symbol_w;
+
+ -- = max 32 PCS registers
+ constant c_tse_pcs_reg_addr_w : natural := 5;
+ -- table 4.17 in ug_ethernet.pdf
+ constant c_tse_pcs_halfword_addr_w : natural := c_tse_pcs_reg_addr_w + 1;
constant c_tse_pcs_byte_addr_w : natural := c_tse_pcs_reg_addr_w + 2;
- constant c_tse_pcs_data_w : natural := c_halfword_w; -- = 16;
+ -- = 16;
+ constant c_tse_pcs_data_w : natural := c_halfword_w;
constant c_tse_empty_w : natural := 2;
constant c_tse_tx_error_w : natural := 1;
@@ -62,18 +75,23 @@ architecture tb of tb_ip_arria10_tse_sgmii_gx is
constant c_tse_err_stat_w : natural := 18;
constant c_tse_frm_type_w : natural := 4;
- constant c_tse_tx_fifo_depth : natural := 256; -- nof words for Tx FIFO
- constant c_tse_rx_fifo_depth : natural := 256; -- nof words for Rx FIFO
+ -- nof words for Tx FIFO
+ constant c_tse_tx_fifo_depth : natural := 256;
+ -- nof words for Rx FIFO
+ constant c_tse_rx_fifo_depth : natural := 256;
constant c_tse_promis_en : boolean := false;
--CONSTANT c_tse_promis_en : BOOLEAN := TRUE;
- constant c_tx_data_type : natural := 1; -- 0 = symbols, 1 = counter
+ -- 0 = symbols, 1 = counter
+ constant c_tx_data_type : natural := 1;
constant c_tx_ready_latency : natural := 0;
- constant c_nof_tx_not_valid : natural := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ constant c_nof_tx_not_valid : natural := 0;
constant c_eth_dst_mac : std_logic_vector(47 downto 0) := X"10FA01020300";
- constant c_eth_src_mac : std_logic_vector(47 downto 0) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ -- = 12-34-56-78-9A-BC
+ constant c_eth_src_mac : std_logic_vector(47 downto 0) := X"123456789ABC";
constant c_eth_ethertype : std_logic_vector(15 downto 0) := X"10FA";
type t_mm_bus is record
@@ -241,7 +259,8 @@ architecture tb of tb_ip_arria10_tse_sgmii_gx is
procedure proc_tx_packet(constant dst_mac_addr : in std_logic_vector(c_eth_dst_mac'range);
constant src_mac_addr : in std_logic_vector(c_eth_src_mac'range);
constant ethertype : in std_logic_vector(c_eth_ethertype'range);
- constant data_len : in natural; -- in symbols = octets = bytes
+ -- in symbols = octets = bytes
+ constant data_len : in natural;
signal dp_clk : in std_logic;
signal dp_src_in : in t_tse_stream;
signal dp_src_out : out t_tse_stream) is
@@ -254,7 +273,8 @@ architecture tb of tb_ip_arria10_tse_sgmii_gx is
-- DST MAC
dp_src_out.empty <= std_logic_vector(to_unsigned(0, c_tse_empty_w));
dp_src_out.data <= (others => '0');
- dp_src_out.data(15 downto 0) <= hton(dst_mac_addr(15 downto 0)); -- send to itself
+ -- send to itself
+ dp_src_out.data(15 downto 0) <= hton(dst_mac_addr(15 downto 0));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '1', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
dp_src_out.data <= hton(dst_mac_addr(47 downto 16));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
@@ -382,7 +402,8 @@ architecture tb of tb_ip_arria10_tse_sgmii_gx is
end loop;
if c_tx_data_type = 0 then
-- data : X"01020304", X"05060708", X"090A0B0C", etc
- for J in c_tse_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
+ -- ignore CRC32 symbols in last data word
+ for J in c_tse_symbols_per_beat - 1 downto v_empty loop
v_sym := v_sym + 1;
assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
end loop;
@@ -390,7 +411,8 @@ architecture tb of tb_ip_arria10_tse_sgmii_gx is
-- data : X"00000001", X"00000002", X"00000003", etc
v_num := v_num + 1;
for J in v_empty - 1 downto 0 loop
- v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
+ -- force CRC32 symbols in last data word to 0
+ v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0');
end loop;
assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
end if;
@@ -409,10 +431,13 @@ architecture tb of tb_ip_arria10_tse_sgmii_gx is
-- TSE MAC control interface
signal mm_init : std_logic := '1';
- signal mm_miso : t_mm_bus; -- master in slave out
- signal mm_mosi : t_mm_bus; -- master out slave in
+ -- master in slave out
+ signal mm_miso : t_mm_bus;
+ -- master out slave in
+ signal mm_mosi : t_mm_bus;
- signal pcs_rddata : natural; -- [c_tse_pcs_data_w-1:0]
+ -- [c_tse_pcs_data_w-1:0]
+ signal pcs_rddata : natural;
signal tse_led_an : std_logic;
signal tse_led_link : std_logic;
@@ -456,8 +481,10 @@ architecture tb of tb_ip_arria10_tse_sgmii_gx is
signal dbg_ff_tx : t_tse_stream;
signal dbg_ff_rx : t_tse_stream;
begin
- eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
- sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
+ -- TSE reference clock
+ eth_clk <= not eth_clk after eth_clk_period / 2;
+ -- System clock
+ sys_clk <= not sys_clk after sys_clk_period / 2;
mm_clk <= sys_clk;
dp_clk <= sys_clk;
@@ -481,14 +508,20 @@ begin
for I in 0 to 9 loop wait until rising_edge(mm_clk); end loop;
-- PSC control
- proc_rd_pcs(16#22#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> 0x0901
- proc_wr_pcs(16#28#, 16#0008#, mm_clk, mm_miso, mm_mosi); -- IF_MODE <-- Force 1GbE, no autonegatiation
- proc_rd_pcs(16#00#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- CONTROL --> 0x1140
- proc_rd_pcs(16#02#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- STATUS --> 0x000D
- proc_wr_pcs(16#00#, 16#0140#, mm_clk, mm_miso, mm_mosi); -- CONTROL <-- Auto negotiate disable
+ -- REV --> 0x0901
+ proc_rd_pcs(16#22#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- IF_MODE <-- Force 1GbE, no autonegatiation
+ proc_wr_pcs(16#28#, 16#0008#, mm_clk, mm_miso, mm_mosi);
+ -- CONTROL --> 0x1140
+ proc_rd_pcs(16#00#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- STATUS --> 0x000D
+ proc_rd_pcs(16#02#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- CONTROL <-- Auto negotiate disable
+ proc_wr_pcs(16#00#, 16#0140#, mm_clk, mm_miso, mm_mosi);
-- MAC control
- proc_rd_mac(16#000#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> CUST_VERSION & 0x0901
+ -- REV --> CUST_VERSION & 0x0901
+ proc_rd_mac(16#000#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
if c_tse_promis_en = false then
proc_wr_mac(16#008#, 16#0100004B#, mm_clk, mm_miso, mm_mosi);
else
@@ -525,10 +558,14 @@ begin
-- [ 27] = DISABLE_RD_TIMEOUT = 0
-- [30-28] = RSVD = 000
-- [ 31] = CNT_RESET = 0, when 1 clear statistics
- proc_wr_mac(16#00C#, 16#56789ABC#, mm_clk, mm_miso, mm_mosi); -- MAC_0
- proc_wr_mac(16#010#, 16#00001234#, mm_clk, mm_miso, mm_mosi); -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
- proc_wr_mac(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi); -- TX_IPG_LENGTH <-- interpacket gap = 12
- proc_wr_mac(16#014#, 16#000005EE#, mm_clk, mm_miso, mm_mosi); -- FRM_LENGTH <-- receive max frame length = 1518
+ -- MAC_0
+ proc_wr_mac(16#00C#, 16#56789ABC#, mm_clk, mm_miso, mm_mosi);
+ -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
+ proc_wr_mac(16#010#, 16#00001234#, mm_clk, mm_miso, mm_mosi);
+ -- TX_IPG_LENGTH <-- interpacket gap = 12
+ proc_wr_mac(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi);
+ -- FRM_LENGTH <-- receive max frame length = 1518
+ proc_wr_mac(16#014#, 16#000005EE#, mm_clk, mm_miso, mm_mosi);
-- FIFO legenda:
-- . Tx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
@@ -550,17 +587,27 @@ begin
-- . c_tse_tx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Tx user respects ff_tx_rdy, to store a complete
-- ETH packet would require 1518 byte, so 2 M9K = 2k * 8b
-- . c_tse_rx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Rx user ff_rx_rdy is sufficiently active
- proc_wr_mac(16#01C#, c_tse_rx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
- proc_wr_mac(16#020#, 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_FULL <-- default 16
- proc_wr_mac(16#024#, c_tse_tx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
- proc_wr_mac(16#028#, 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
- proc_wr_mac(16#02C#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_EMPTY <-- default 8
- proc_wr_mac(16#030#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_FULL <-- default 8
- proc_wr_mac(16#034#, 8, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_EMPTY <-- default 8
- proc_wr_mac(16#038#, c_tx_ready_latency + 3, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_FULL <-- default 3
-
- proc_rd_mac(16#0E8#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
- proc_rd_mac(16#0EC#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+ -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#01C#, c_tse_rx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi);
+ -- RX_SECTION_FULL <-- default 16
+ proc_wr_mac(16#020#, 16, mm_clk, mm_miso, mm_mosi);
+ -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#024#, c_tse_tx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi);
+ -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
+ proc_wr_mac(16#028#, 16, mm_clk, mm_miso, mm_mosi);
+ -- RX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#02C#, 8, mm_clk, mm_miso, mm_mosi);
+ -- RX_ALMOST_FULL <-- default 8
+ proc_wr_mac(16#030#, 8, mm_clk, mm_miso, mm_mosi);
+ -- TX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#034#, 8, mm_clk, mm_miso, mm_mosi);
+ -- TX_ALMOST_FULL <-- default 3
+ proc_wr_mac(16#038#, c_tx_ready_latency + 3, mm_clk, mm_miso, mm_mosi);
+
+ -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
+ proc_rd_mac(16#0E8#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+ proc_rd_mac(16#0EC#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
wait until rising_edge(mm_clk);
mm_init <= '0';
@@ -592,7 +639,8 @@ begin
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1499, dp_clk, ff_tx_src_in, ff_tx_src_out); -- verify st empty
+ -- verify st empty
+ proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1499, dp_clk, ff_tx_src_in, ff_tx_src_out);
proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
@@ -637,30 +685,51 @@ begin
port map (
-- MAC transmit interface
-- . Avalon ST
- ff_tx_clk => dp_clk, -- : in std_logic := '0'; -- transmit_clock_connection.clk
- ff_tx_rdy => ff_tx_src_in.ready, -- : out std_logic; -- .ready
- ff_tx_data => ff_tx_src_out.data, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
- ff_tx_wren => ff_tx_src_out.valid, -- : in std_logic := '0'; -- .valid
- ff_tx_sop => ff_tx_src_out.sop, -- : in std_logic := '0'; -- .startofpacket
- ff_tx_eop => ff_tx_src_out.eop, -- : in std_logic := '0'; -- .endofpacket
- ff_tx_mod => ff_tx_src_out.empty, -- : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
- ff_tx_err => ff_tx_src_out.err(0), -- : in std_logic := '0'; -- .error
+ -- : in std_logic := '0'; -- transmit_clock_connection.clk
+ ff_tx_clk => dp_clk,
+ -- : out std_logic; -- .ready
+ ff_tx_rdy => ff_tx_src_in.ready,
+ -- : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_data => ff_tx_src_out.data,
+ -- : in std_logic := '0'; -- .valid
+ ff_tx_wren => ff_tx_src_out.valid,
+ -- : in std_logic := '0'; -- .startofpacket
+ ff_tx_sop => ff_tx_src_out.sop,
+ -- : in std_logic := '0'; -- .endofpacket
+ ff_tx_eop => ff_tx_src_out.eop,
+ -- : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_mod => ff_tx_src_out.empty,
+ -- : in std_logic := '0'; -- .error
+ ff_tx_err => ff_tx_src_out.err(0),
-- . MAC specific
- ff_tx_crc_fwd => ff_tx_crc_fwd, -- : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd -- when '0' MAC inserts CRC32 after eop
- ff_tx_septy => ff_tx_septy, -- : out std_logic; -- .ff_tx_septy -- when '0' then tx FIFO goes above section-empty threshold
- ff_tx_a_full => ff_tx_a_full, -- : out std_logic; -- .ff_tx_a_full -- when '1' then tx FIFO goes above almost-full threshold
- ff_tx_a_empty => ff_tx_a_empty, -- : out std_logic; -- .ff_tx_a_empty -- when '1' then tx FIFO goes below almost-empty threshold
- tx_ff_uflow => ff_tx_uflow, -- : out std_logic; -- .tx_ff_uflow -- when '1' then tx FIFO underflow
+ -- : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd -- when '0' MAC inserts CRC32 after eop
+ ff_tx_crc_fwd => ff_tx_crc_fwd,
+ -- : out std_logic; -- .ff_tx_septy -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_septy => ff_tx_septy,
+ -- : out std_logic; -- .ff_tx_a_full -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_full => ff_tx_a_full,
+ -- : out std_logic; -- .ff_tx_a_empty -- when '1' then tx FIFO goes below almost-empty threshold
+ ff_tx_a_empty => ff_tx_a_empty,
+ -- : out std_logic; -- .tx_ff_uflow -- when '1' then tx FIFO underflow
+ tx_ff_uflow => ff_tx_uflow,
-- MAC receive interface
-- . Avalon STs
- ff_rx_clk => dp_clk, -- : in std_logic := '0'; -- receive_clock_connection.clk
- ff_rx_rdy => ff_rx_snk_out.ready, -- : in std_logic := '0'; -- .ready
- ff_rx_data => ff_rx_snk_in.data, -- : out std_logic_vector(31 downto 0); -- receive.data
- ff_rx_dval => ff_rx_snk_in.valid, -- : out std_logic; -- .valid
- ff_rx_sop => ff_rx_snk_in.sop, -- : out std_logic; -- .startofpacket
- ff_rx_eop => ff_rx_snk_in.eop, -- : out std_logic; -- .endofpacket
- ff_rx_mod => ff_rx_snk_in.empty, -- : out std_logic_vector(1 downto 0); -- .empty
- rx_err => ff_rx_snk_in.err, -- : out std_logic_vector(5 downto 0); -- .error
+ -- : in std_logic := '0'; -- receive_clock_connection.clk
+ ff_rx_clk => dp_clk,
+ -- : in std_logic := '0'; -- .ready
+ ff_rx_rdy => ff_rx_snk_out.ready,
+ -- : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_data => ff_rx_snk_in.data,
+ -- : out std_logic; -- .valid
+ ff_rx_dval => ff_rx_snk_in.valid,
+ -- : out std_logic; -- .startofpacket
+ ff_rx_sop => ff_rx_snk_in.sop,
+ -- : out std_logic; -- .endofpacket
+ ff_rx_eop => ff_rx_snk_in.eop,
+ -- : out std_logic_vector(1 downto 0); -- .empty
+ ff_rx_mod => ff_rx_snk_in.empty,
+ -- : out std_logic_vector(5 downto 0); -- .error
+ rx_err => ff_rx_snk_in.err,
-- [5] collision error (can only occur in half duplex mode)
-- [4] PHY error on GMII
-- [3] receive frame truncated due to FIFO overflow
@@ -668,51 +737,88 @@ begin
-- [1] invalid length
-- [0] = OR of [1:5]
-- . MAC specific
- rx_err_stat => ff_rx_ethertype, -- : out std_logic_vector(17 downto 0); -- .rx_err_stat -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
- rx_frm_type => ff_rx_frm_type, -- : out std_logic_vector(3 downto 0); -- .rx_frm_type -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
- ff_rx_dsav => ff_rx_dsav, -- : out std_logic; -- .ff_rx_dsav -- rx frame available, but not necessarily a complete frame
- ff_rx_a_full => ff_rx_a_full, -- : out std_logic; -- .ff_rx_a_full -- when '1' then rx FIFO goes above almost-full threshold
- ff_rx_a_empty => ff_rx_a_empty, -- : out std_logic; -- .ff_rx_a_empty -- when '1' sthen rx FIFO goes below almost-empty threshold
+ -- : out std_logic_vector(17 downto 0); -- .rx_err_stat -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_err_stat => ff_rx_ethertype,
+ -- : out std_logic_vector(3 downto 0); -- .rx_frm_type -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ rx_frm_type => ff_rx_frm_type,
+ -- : out std_logic; -- .ff_rx_dsav -- rx frame available, but not necessarily a complete frame
+ ff_rx_dsav => ff_rx_dsav,
+ -- : out std_logic; -- .ff_rx_a_full -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_full => ff_rx_a_full,
+ -- : out std_logic; -- .ff_rx_a_empty -- when '1' sthen rx FIFO goes below almost-empty threshold
+ ff_rx_a_empty => ff_rx_a_empty,
-- Reset
- reset => mm_rst, -- : in std_logic := '0'; -- reset_connection.reset -- asynchronous reset (choose synchronous to mm_clk)
+ -- : in std_logic := '0'; -- reset_connection.reset -- asynchronous reset (choose synchronous to mm_clk)
+ reset => mm_rst,
-- MM control interface
- clk => mm_clk, -- : in std_logic := '0'; -- control_port_clock_connection.clk
- reg_addr => mm_mosi.address(c_tse_byte_addr_w - 1 downto 2), -- : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
- reg_data_out => mm_miso.rddata, -- : out std_logic_vector(31 downto 0); -- control_port.readdata
- reg_rd => mm_mosi.rd, -- : in std_logic := '0'; -- .read
- reg_data_in => mm_mosi.wrdata, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reg_wr => mm_mosi.wr, -- : in std_logic := '0'; -- .write
- reg_busy => mm_miso.waitreq, -- : out std_logic; -- .waitrequest
+ -- : in std_logic := '0'; -- control_port_clock_connection.clk
+ clk => mm_clk,
+ -- : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ reg_addr => mm_mosi.address(c_tse_byte_addr_w - 1 downto 2),
+ -- : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_data_out => mm_miso.rddata,
+ -- : in std_logic := '0'; -- .read
+ reg_rd => mm_mosi.rd,
+ -- : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_data_in => mm_mosi.wrdata,
+ -- : in std_logic := '0'; -- .write
+ reg_wr => mm_mosi.wr,
+ -- : out std_logic; -- .waitrequest
+ reg_busy => mm_miso.waitreq,
-- Status LEDs
- led_an => tse_led_an, -- : out std_logic; -- .an -- '1' = autonegation completed
- led_link => tse_led_link, -- : out std_logic; -- .link -- '1' = successful link synchronisation
- led_disp_err => OPEN, -- : out std_logic; -- .disp_err -- TBI character error
- led_char_err => OPEN, -- : out std_logic; -- .char_err -- TBI disparity errorreceived
- led_crs => OPEN, -- : out std_logic; -- status_led_connection.crs
- led_col => OPEN, -- : out std_logic; -- .col
+ -- : out std_logic; -- .an -- '1' = autonegation completed
+ led_an => tse_led_an,
+ -- : out std_logic; -- .link -- '1' = successful link synchronisation
+ led_link => tse_led_link,
+ -- : out std_logic; -- .disp_err -- TBI character error
+ led_disp_err => OPEN,
+ -- : out std_logic; -- .char_err -- TBI disparity errorreceived
+ led_char_err => OPEN,
+ -- : out std_logic; -- status_led_connection.crs
+ led_crs => OPEN,
+ -- : out std_logic; -- .col
+ led_col => OPEN,
-- Serial 1.25 Gbps
- rx_recovclkout => OPEN, -- : out std_logic; -- serdes_control_connection.export
- ref_clk => eth_clk, -- : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
- txp => eth_txp, -- : out std_logic -- .txp_0
- rxp => eth_rxp, -- : in std_logic := '0'; -- serial_connection.rxp_0
-
- tx_serial_clk => tx_serial_clk, -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk.clk
- rx_cdr_refclk => rx_cdr_refclk, -- : in std_logic := '0'; -- rx_cdr_refclk.clk
- tx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_set_locktodata => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
- rx_set_locktoref => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
- rx_is_lockedtoref => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => open -- : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
+ -- : out std_logic; -- serdes_control_connection.export
+ rx_recovclkout => OPEN,
+ -- : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ ref_clk => eth_clk,
+ -- : out std_logic -- .txp_0
+ txp => eth_txp,
+ -- : in std_logic := '0'; -- serial_connection.rxp_0
+ rxp => eth_rxp,
+
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk.clk
+ tx_serial_clk => tx_serial_clk,
+ -- : in std_logic := '0'; -- rx_cdr_refclk.clk
+ rx_cdr_refclk => rx_cdr_refclk,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => (others => '0'),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => (others => '0'),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => (others => '0'),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => (others => '0'),
+ -- : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => OPEN,
+ -- : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => OPEN,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
+ rx_set_locktodata => (others => '0'),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
+ rx_set_locktoref => (others => '0'),
+ -- : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref => OPEN,
+ -- : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => open
);
-- To be corrected
- tx_serial_clk(0) <= not tx_serial_clk(0) after serial_clk_period / 2; -- ????
- rx_cdr_refclk <= not rx_cdr_refclk after cdr_clk_period / 2; -- ????
+ -- ????
+ tx_serial_clk(0) <= not tx_serial_clk(0) after serial_clk_period / 2;
+ -- ????
+ rx_cdr_refclk <= not rx_cdr_refclk after cdr_clk_period / 2;
-- Loopback
eth_rxp <= eth_txp;
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd b/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd
index e5ad6682c9cd45a25d65ab62bbe391ccf2d6d96a..7da8e529082f6b68d0ac448dcf2f948c488520ed 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd
@@ -41,22 +41,33 @@ entity tb_ip_arria10_tse_sgmii_lvds is
end tb_ip_arria10_tse_sgmii_lvds;
architecture tb of tb_ip_arria10_tse_sgmii_lvds is
- constant sys_clk_period : time := 10 ns; -- 100 MHz
- constant eth_clk_period : time := 8 ns; -- 125 MHz
+ -- 100 MHz
+ constant sys_clk_period : time := 10 ns;
+ -- 125 MHz
+ constant eth_clk_period : time := 8 ns;
- constant c_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
+ -- = max 256 MAC registers
+ constant c_tse_reg_addr_w : natural := 8;
constant c_tse_byte_addr_w : natural := c_tse_reg_addr_w + 2;
- constant c_tse_byte_addr_pcs_offset : natural := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
- constant c_tse_data_w : natural := c_word_w; -- = 32
-
- constant c_tse_symbol_w : natural := c_byte_w; -- = 8
- constant c_tse_symbol_max : natural := 2**c_tse_symbol_w - 1; -- = 255
- constant c_tse_symbols_per_beat : natural := c_tse_data_w / c_tse_symbol_w; -- = 4
-
- constant c_tse_pcs_reg_addr_w : natural := 5; -- = max 32 PCS registers
- constant c_tse_pcs_halfword_addr_w : natural := c_tse_pcs_reg_addr_w + 1; -- table 4.17 in ug_ethernet.pdf
+ -- table 4.8, 4.9 in ug_ethernet.pdf
+ constant c_tse_byte_addr_pcs_offset : natural := 16#200#;
+ -- = 32
+ constant c_tse_data_w : natural := c_word_w;
+
+ -- = 8
+ constant c_tse_symbol_w : natural := c_byte_w;
+ -- = 255
+ constant c_tse_symbol_max : natural := 2**c_tse_symbol_w - 1;
+ -- = 4
+ constant c_tse_symbols_per_beat : natural := c_tse_data_w / c_tse_symbol_w;
+
+ -- = max 32 PCS registers
+ constant c_tse_pcs_reg_addr_w : natural := 5;
+ -- table 4.17 in ug_ethernet.pdf
+ constant c_tse_pcs_halfword_addr_w : natural := c_tse_pcs_reg_addr_w + 1;
constant c_tse_pcs_byte_addr_w : natural := c_tse_pcs_reg_addr_w + 2;
- constant c_tse_pcs_data_w : natural := c_halfword_w; -- = 16;
+ -- = 16;
+ constant c_tse_pcs_data_w : natural := c_halfword_w;
constant c_tse_empty_w : natural := 2;
constant c_tse_tx_error_w : natural := 1;
@@ -65,18 +76,23 @@ architecture tb of tb_ip_arria10_tse_sgmii_lvds is
constant c_tse_err_stat_w : natural := 18;
constant c_tse_frm_type_w : natural := 4;
- constant c_tse_tx_fifo_depth : natural := 256; -- nof words for Tx FIFO
- constant c_tse_rx_fifo_depth : natural := 256; -- nof words for Rx FIFO
+ -- nof words for Tx FIFO
+ constant c_tse_tx_fifo_depth : natural := 256;
+ -- nof words for Rx FIFO
+ constant c_tse_rx_fifo_depth : natural := 256;
constant c_tse_promis_en : boolean := false;
--CONSTANT c_tse_promis_en : BOOLEAN := TRUE;
- constant c_tx_data_type : natural := 1; -- 0 = symbols, 1 = counter
+ -- 0 = symbols, 1 = counter
+ constant c_tx_data_type : natural := 1;
constant c_tx_ready_latency : natural := 0;
- constant c_nof_tx_not_valid : natural := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ constant c_nof_tx_not_valid : natural := 0;
constant c_eth_dst_mac : std_logic_vector(47 downto 0) := X"10FA01020300";
- constant c_eth_src_mac : std_logic_vector(47 downto 0) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ -- = 12-34-56-78-9A-BC
+ constant c_eth_src_mac : std_logic_vector(47 downto 0) := X"123456789ABC";
constant c_eth_ethertype : std_logic_vector(15 downto 0) := X"10FA";
type t_mm_bus is record
@@ -244,7 +260,8 @@ architecture tb of tb_ip_arria10_tse_sgmii_lvds is
procedure proc_tx_packet(constant dst_mac_addr : in std_logic_vector(c_eth_dst_mac'range);
constant src_mac_addr : in std_logic_vector(c_eth_src_mac'range);
constant ethertype : in std_logic_vector(c_eth_ethertype'range);
- constant data_len : in natural; -- in symbols = octets = bytes
+ -- in symbols = octets = bytes
+ constant data_len : in natural;
signal dp_clk : in std_logic;
signal dp_src_in : in t_tse_stream;
signal dp_src_out : out t_tse_stream) is
@@ -257,7 +274,8 @@ architecture tb of tb_ip_arria10_tse_sgmii_lvds is
-- DST MAC
dp_src_out.empty <= std_logic_vector(to_unsigned(0, c_tse_empty_w));
dp_src_out.data <= (others => '0');
- dp_src_out.data(15 downto 0) <= hton(dst_mac_addr(15 downto 0)); -- send to itself
+ -- send to itself
+ dp_src_out.data(15 downto 0) <= hton(dst_mac_addr(15 downto 0));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '1', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
dp_src_out.data <= hton(dst_mac_addr(47 downto 16));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
@@ -385,7 +403,8 @@ architecture tb of tb_ip_arria10_tse_sgmii_lvds is
end loop;
if c_tx_data_type = 0 then
-- data : X"01020304", X"05060708", X"090A0B0C", etc
- for J in c_tse_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
+ -- ignore CRC32 symbols in last data word
+ for J in c_tse_symbols_per_beat - 1 downto v_empty loop
v_sym := v_sym + 1;
assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
end loop;
@@ -393,7 +412,8 @@ architecture tb of tb_ip_arria10_tse_sgmii_lvds is
-- data : X"00000001", X"00000002", X"00000003", etc
v_num := v_num + 1;
for J in v_empty - 1 downto 0 loop
- v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
+ -- force CRC32 symbols in last data word to 0
+ v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0');
end loop;
assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
end if;
@@ -412,10 +432,13 @@ architecture tb of tb_ip_arria10_tse_sgmii_lvds is
-- TSE MAC control interface
signal mm_init : std_logic := '1';
- signal mm_miso : t_mm_bus; -- master in slave out
- signal mm_mosi : t_mm_bus; -- master out slave in
+ -- master in slave out
+ signal mm_miso : t_mm_bus;
+ -- master out slave in
+ signal mm_mosi : t_mm_bus;
- signal pcs_rddata : natural; -- [c_tse_pcs_data_w-1:0]
+ -- [c_tse_pcs_data_w-1:0]
+ signal pcs_rddata : natural;
signal tse_led_an : std_logic;
signal tse_led_link : std_logic;
@@ -455,8 +478,10 @@ architecture tb of tb_ip_arria10_tse_sgmii_lvds is
signal dbg_ff_tx : t_tse_stream;
signal dbg_ff_rx : t_tse_stream;
begin
- eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
- sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
+ -- TSE reference clock
+ eth_clk <= not eth_clk after eth_clk_period / 2;
+ -- System clock
+ sys_clk <= not sys_clk after sys_clk_period / 2;
mm_clk <= sys_clk;
dp_clk <= sys_clk;
@@ -480,14 +505,20 @@ begin
for I in 0 to 9 loop wait until rising_edge(mm_clk); end loop;
-- PSC control
- proc_rd_pcs(16#22#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> 0x0901
- proc_wr_pcs(16#28#, 16#0008#, mm_clk, mm_miso, mm_mosi); -- IF_MODE <-- Force 1GbE, no autonegatiation
- proc_rd_pcs(16#00#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- CONTROL --> 0x1140
- proc_rd_pcs(16#02#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- STATUS --> 0x000D
- proc_wr_pcs(16#00#, 16#0140#, mm_clk, mm_miso, mm_mosi); -- CONTROL <-- Auto negotiate disable
+ -- REV --> 0x0901
+ proc_rd_pcs(16#22#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- IF_MODE <-- Force 1GbE, no autonegatiation
+ proc_wr_pcs(16#28#, 16#0008#, mm_clk, mm_miso, mm_mosi);
+ -- CONTROL --> 0x1140
+ proc_rd_pcs(16#00#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- STATUS --> 0x000D
+ proc_rd_pcs(16#02#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- CONTROL <-- Auto negotiate disable
+ proc_wr_pcs(16#00#, 16#0140#, mm_clk, mm_miso, mm_mosi);
-- MAC control
- proc_rd_mac(16#000#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> CUST_VERSION & 0x0901
+ -- REV --> CUST_VERSION & 0x0901
+ proc_rd_mac(16#000#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
if c_tse_promis_en = false then
proc_wr_mac(16#008#, 16#0100004B#, mm_clk, mm_miso, mm_mosi);
else
@@ -524,10 +555,14 @@ begin
-- [ 27] = DISABLE_RD_TIMEOUT = 0
-- [30-28] = RSVD = 000
-- [ 31] = CNT_RESET = 0, when 1 clear statistics
- proc_wr_mac(16#00C#, 16#56789ABC#, mm_clk, mm_miso, mm_mosi); -- MAC_0
- proc_wr_mac(16#010#, 16#00001234#, mm_clk, mm_miso, mm_mosi); -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
- proc_wr_mac(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi); -- TX_IPG_LENGTH <-- interpacket gap = 12
- proc_wr_mac(16#014#, 16#000005EE#, mm_clk, mm_miso, mm_mosi); -- FRM_LENGTH <-- receive max frame length = 1518
+ -- MAC_0
+ proc_wr_mac(16#00C#, 16#56789ABC#, mm_clk, mm_miso, mm_mosi);
+ -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
+ proc_wr_mac(16#010#, 16#00001234#, mm_clk, mm_miso, mm_mosi);
+ -- TX_IPG_LENGTH <-- interpacket gap = 12
+ proc_wr_mac(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi);
+ -- FRM_LENGTH <-- receive max frame length = 1518
+ proc_wr_mac(16#014#, 16#000005EE#, mm_clk, mm_miso, mm_mosi);
-- FIFO legenda:
-- . Tx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
@@ -549,17 +584,27 @@ begin
-- . c_tse_tx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Tx user respects ff_tx_rdy, to store a complete
-- ETH packet would require 1518 byte, so 2 M9K = 2k * 8b
-- . c_tse_rx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Rx user ff_rx_rdy is sufficiently active
- proc_wr_mac(16#01C#, c_tse_rx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
- proc_wr_mac(16#020#, 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_FULL <-- default 16
- proc_wr_mac(16#024#, c_tse_tx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
- proc_wr_mac(16#028#, 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
- proc_wr_mac(16#02C#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_EMPTY <-- default 8
- proc_wr_mac(16#030#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_FULL <-- default 8
- proc_wr_mac(16#034#, 8, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_EMPTY <-- default 8
- proc_wr_mac(16#038#, c_tx_ready_latency + 3, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_FULL <-- default 3
-
- proc_rd_mac(16#0E8#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
- proc_rd_mac(16#0EC#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+ -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#01C#, c_tse_rx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi);
+ -- RX_SECTION_FULL <-- default 16
+ proc_wr_mac(16#020#, 16, mm_clk, mm_miso, mm_mosi);
+ -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#024#, c_tse_tx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi);
+ -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
+ proc_wr_mac(16#028#, 16, mm_clk, mm_miso, mm_mosi);
+ -- RX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#02C#, 8, mm_clk, mm_miso, mm_mosi);
+ -- RX_ALMOST_FULL <-- default 8
+ proc_wr_mac(16#030#, 8, mm_clk, mm_miso, mm_mosi);
+ -- TX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#034#, 8, mm_clk, mm_miso, mm_mosi);
+ -- TX_ALMOST_FULL <-- default 3
+ proc_wr_mac(16#038#, c_tx_ready_latency + 3, mm_clk, mm_miso, mm_mosi);
+
+ -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
+ proc_rd_mac(16#0E8#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+ proc_rd_mac(16#0EC#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
wait until rising_edge(mm_clk);
mm_init <= '0';
@@ -591,7 +636,8 @@ begin
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1499, dp_clk, ff_tx_src_in, ff_tx_src_out); -- verify st empty
+ -- verify st empty
+ proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1499, dp_clk, ff_tx_src_in, ff_tx_src_out);
proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
@@ -636,30 +682,51 @@ begin
port map (
-- MAC transmit interface
-- . Avalon ST
- ff_tx_clk => dp_clk, -- : in std_logic := '0'; -- transmit_clock_connection.clk
- ff_tx_rdy => ff_tx_src_in.ready, -- : out std_logic; -- .ready
- ff_tx_data => ff_tx_src_out.data, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
- ff_tx_wren => ff_tx_src_out.valid, -- : in std_logic := '0'; -- .valid
- ff_tx_sop => ff_tx_src_out.sop, -- : in std_logic := '0'; -- .startofpacket
- ff_tx_eop => ff_tx_src_out.eop, -- : in std_logic := '0'; -- .endofpacket
- ff_tx_mod => ff_tx_src_out.empty, -- : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
- ff_tx_err => ff_tx_src_out.err(0), -- : in std_logic := '0'; -- .error
+ -- : in std_logic := '0'; -- transmit_clock_connection.clk
+ ff_tx_clk => dp_clk,
+ -- : out std_logic; -- .ready
+ ff_tx_rdy => ff_tx_src_in.ready,
+ -- : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_data => ff_tx_src_out.data,
+ -- : in std_logic := '0'; -- .valid
+ ff_tx_wren => ff_tx_src_out.valid,
+ -- : in std_logic := '0'; -- .startofpacket
+ ff_tx_sop => ff_tx_src_out.sop,
+ -- : in std_logic := '0'; -- .endofpacket
+ ff_tx_eop => ff_tx_src_out.eop,
+ -- : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_mod => ff_tx_src_out.empty,
+ -- : in std_logic := '0'; -- .error
+ ff_tx_err => ff_tx_src_out.err(0),
-- . MAC specific
- ff_tx_crc_fwd => ff_tx_crc_fwd, -- : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd -- when '0' MAC inserts CRC32 after eop
- ff_tx_septy => ff_tx_septy, -- : out std_logic; -- .ff_tx_septy -- when '0' then tx FIFO goes above section-empty threshold
- ff_tx_a_full => ff_tx_a_full, -- : out std_logic; -- .ff_tx_a_full -- when '1' then tx FIFO goes above almost-full threshold
- ff_tx_a_empty => ff_tx_a_empty, -- : out std_logic; -- .ff_tx_a_empty -- when '1' then tx FIFO goes below almost-empty threshold
- tx_ff_uflow => ff_tx_uflow, -- : out std_logic; -- .tx_ff_uflow -- when '1' then tx FIFO underflow
+ -- : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd -- when '0' MAC inserts CRC32 after eop
+ ff_tx_crc_fwd => ff_tx_crc_fwd,
+ -- : out std_logic; -- .ff_tx_septy -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_septy => ff_tx_septy,
+ -- : out std_logic; -- .ff_tx_a_full -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_full => ff_tx_a_full,
+ -- : out std_logic; -- .ff_tx_a_empty -- when '1' then tx FIFO goes below almost-empty threshold
+ ff_tx_a_empty => ff_tx_a_empty,
+ -- : out std_logic; -- .tx_ff_uflow -- when '1' then tx FIFO underflow
+ tx_ff_uflow => ff_tx_uflow,
-- MAC receive interface
-- . Avalon STs
- ff_rx_clk => dp_clk, -- : in std_logic := '0'; -- receive_clock_connection.clk
- ff_rx_rdy => ff_rx_snk_out.ready, -- : in std_logic := '0'; -- .ready
- ff_rx_data => ff_rx_snk_in.data, -- : out std_logic_vector(31 downto 0); -- receive.data
- ff_rx_dval => ff_rx_snk_in.valid, -- : out std_logic; -- .valid
- ff_rx_sop => ff_rx_snk_in.sop, -- : out std_logic; -- .startofpacket
- ff_rx_eop => ff_rx_snk_in.eop, -- : out std_logic; -- .endofpacket
- ff_rx_mod => ff_rx_snk_in.empty, -- : out std_logic_vector(1 downto 0); -- .empty
- rx_err => ff_rx_snk_in.err, -- : out std_logic_vector(5 downto 0); -- .error
+ -- : in std_logic := '0'; -- receive_clock_connection.clk
+ ff_rx_clk => dp_clk,
+ -- : in std_logic := '0'; -- .ready
+ ff_rx_rdy => ff_rx_snk_out.ready,
+ -- : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_data => ff_rx_snk_in.data,
+ -- : out std_logic; -- .valid
+ ff_rx_dval => ff_rx_snk_in.valid,
+ -- : out std_logic; -- .startofpacket
+ ff_rx_sop => ff_rx_snk_in.sop,
+ -- : out std_logic; -- .endofpacket
+ ff_rx_eop => ff_rx_snk_in.eop,
+ -- : out std_logic_vector(1 downto 0); -- .empty
+ ff_rx_mod => ff_rx_snk_in.empty,
+ -- : out std_logic_vector(5 downto 0); -- .error
+ rx_err => ff_rx_snk_in.err,
-- [5] collision error (can only occur in half duplex mode)
-- [4] PHY error on GMII
-- [3] receive frame truncated due to FIFO overflow
@@ -667,33 +734,56 @@ begin
-- [1] invalid length
-- [0] = OR of [1:5]
-- . MAC specific
- rx_err_stat => ff_rx_ethertype, -- : out std_logic_vector(17 downto 0); -- .rx_err_stat -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
- rx_frm_type => ff_rx_frm_type, -- : out std_logic_vector(3 downto 0); -- .rx_frm_type -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
- ff_rx_dsav => ff_rx_dsav, -- : out std_logic; -- .ff_rx_dsav -- rx frame available, but not necessarily a complete frame
- ff_rx_a_full => ff_rx_a_full, -- : out std_logic; -- .ff_rx_a_full -- when '1' then rx FIFO goes above almost-full threshold
- ff_rx_a_empty => ff_rx_a_empty, -- : out std_logic; -- .ff_rx_a_empty -- when '1' sthen rx FIFO goes below almost-empty threshold
+ -- : out std_logic_vector(17 downto 0); -- .rx_err_stat -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_err_stat => ff_rx_ethertype,
+ -- : out std_logic_vector(3 downto 0); -- .rx_frm_type -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ rx_frm_type => ff_rx_frm_type,
+ -- : out std_logic; -- .ff_rx_dsav -- rx frame available, but not necessarily a complete frame
+ ff_rx_dsav => ff_rx_dsav,
+ -- : out std_logic; -- .ff_rx_a_full -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_full => ff_rx_a_full,
+ -- : out std_logic; -- .ff_rx_a_empty -- when '1' sthen rx FIFO goes below almost-empty threshold
+ ff_rx_a_empty => ff_rx_a_empty,
-- Reset
- reset => mm_rst, -- : in std_logic := '0'; -- reset_connection.reset -- asynchronous reset (choose synchronous to mm_clk)
+ -- : in std_logic := '0'; -- reset_connection.reset -- asynchronous reset (choose synchronous to mm_clk)
+ reset => mm_rst,
-- MM control interface
- clk => mm_clk, -- : in std_logic := '0'; -- control_port_clock_connection.clk
- reg_addr => mm_mosi.address(c_tse_byte_addr_w - 1 downto 2), -- : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
- reg_data_out => mm_miso.rddata, -- : out std_logic_vector(31 downto 0); -- control_port.readdata
- reg_rd => mm_mosi.rd, -- : in std_logic := '0'; -- .read
- reg_data_in => mm_mosi.wrdata, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reg_wr => mm_mosi.wr, -- : in std_logic := '0'; -- .write
- reg_busy => mm_miso.waitreq, -- : out std_logic; -- .waitrequest
+ -- : in std_logic := '0'; -- control_port_clock_connection.clk
+ clk => mm_clk,
+ -- : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ reg_addr => mm_mosi.address(c_tse_byte_addr_w - 1 downto 2),
+ -- : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_data_out => mm_miso.rddata,
+ -- : in std_logic := '0'; -- .read
+ reg_rd => mm_mosi.rd,
+ -- : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_data_in => mm_mosi.wrdata,
+ -- : in std_logic := '0'; -- .write
+ reg_wr => mm_mosi.wr,
+ -- : out std_logic; -- .waitrequest
+ reg_busy => mm_miso.waitreq,
-- Status LEDs
- led_an => tse_led_an, -- : out std_logic; -- .an -- '1' = autonegation completed
- led_link => tse_led_link, -- : out std_logic; -- .link -- '1' = successful link synchronisation
- led_disp_err => OPEN, -- : out std_logic; -- .disp_err -- TBI character error
- led_char_err => OPEN, -- : out std_logic; -- .char_err -- TBI disparity errorreceived
- led_crs => OPEN, -- : out std_logic; -- status_led_connection.crs
- led_col => OPEN, -- : out std_logic; -- .col
+ -- : out std_logic; -- .an -- '1' = autonegation completed
+ led_an => tse_led_an,
+ -- : out std_logic; -- .link -- '1' = successful link synchronisation
+ led_link => tse_led_link,
+ -- : out std_logic; -- .disp_err -- TBI character error
+ led_disp_err => OPEN,
+ -- : out std_logic; -- .char_err -- TBI disparity errorreceived
+ led_char_err => OPEN,
+ -- : out std_logic; -- status_led_connection.crs
+ led_crs => OPEN,
+ -- : out std_logic; -- .col
+ led_col => OPEN,
-- Serial 1.25 Gbps
- rx_recovclkout => OPEN, -- : out std_logic; -- serdes_control_connection.export
- ref_clk => eth_clk, -- : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
- txp => eth_txp, -- : out std_logic -- .txp_0
- rxp => eth_rxp -- : in std_logic := '0'; -- serial_connection.rxp_0
+ -- : out std_logic; -- serdes_control_connection.export
+ rx_recovclkout => OPEN,
+ -- : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ ref_clk => eth_clk,
+ -- : out std_logic -- .txp_0
+ txp => eth_txp,
+ -- : in std_logic := '0'; -- serial_connection.rxp_0
+ rxp => eth_rxp
);
-- Loopback
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in.vhd b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in.vhd
index dcccc9b1c8b2e9b990741414a491ff0cacdf2be9..a64732bc5614b72a9a095291a8f086ef31c0c0d4 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in.vhd
@@ -31,7 +31,8 @@ entity ip_arria10_e1sg_ddio_in is
port (
in_dat : in std_logic_vector(g_width - 1 downto 0);
in_clk : in std_logic;
- in_clk_en : in std_logic := '1'; -- Not Connected
+ -- Not Connected
+ in_clk_en : in std_logic := '1';
rst : in std_logic := '0';
out_dat_hi : out std_logic_vector(g_width - 1 downto 0);
out_dat_lo : out std_logic_vector(g_width - 1 downto 0)
@@ -41,11 +42,16 @@ end ip_arria10_e1sg_ddio_in;
architecture str of ip_arria10_e1sg_ddio_in is
component ip_arria10_e1sg_ddio_in_1 is
port (
- datain : in std_logic_vector(0 downto 0) := (others => '0'); -- pad_in.export
- inclock : in std_logic := '0'; -- ck.export
- aclr : in std_logic := '0'; -- aclr.export
- dataout_h : out std_logic_vector(0 downto 0); -- dataout_h.fragment
- dataout_l : out std_logic_vector(0 downto 0) -- dataout_l.fragment
+ -- pad_in.export
+ datain : in std_logic_vector(0 downto 0) := (others => '0');
+ -- ck.export
+ inclock : in std_logic := '0';
+ -- aclr.export
+ aclr : in std_logic := '0';
+ -- dataout_h.fragment
+ dataout_h : out std_logic_vector(0 downto 0);
+ -- dataout_l.fragment
+ dataout_l : out std_logic_vector(0 downto 0)
);
end component;
begin
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out.vhd b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out.vhd
index 5d100fa091dc2e36c91b349f0b7fc3572882febb..16ff041d3ad1aced72a11e6c982ea047b1fd4b1b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out.vhd
@@ -31,7 +31,8 @@ entity ip_arria10_e1sg_ddio_out is
port (
rst : in std_logic := '0';
in_clk : in std_logic;
- in_clk_en : in std_logic := '1'; -- Not Connected
+ -- Not Connected
+ in_clk_en : in std_logic := '1';
in_dat_hi : in std_logic_vector(g_width - 1 downto 0);
in_dat_lo : in std_logic_vector(g_width - 1 downto 0);
out_dat : out std_logic_vector(g_width - 1 downto 0)
@@ -41,11 +42,16 @@ end ip_arria10_e1sg_ddio_out;
architecture str of ip_arria10_e1sg_ddio_out is
component ip_arria10_e1sg_ddio_out_1 is
port (
- dataout : out std_logic_vector(0 downto 0); -- pad_out.export
- outclock : in std_logic := '0'; -- ck.export
- aclr : in std_logic := '0'; -- aclr.export
- datain_h : in std_logic_vector(0 downto 0) := (others => '0'); -- datain_h.fragment
- datain_l : in std_logic_vector(0 downto 0) := (others => '0') -- datain_l.fragment
+ -- pad_out.export
+ dataout : out std_logic_vector(0 downto 0);
+ -- ck.export
+ outclock : in std_logic := '0';
+ -- aclr.export
+ aclr : in std_logic := '0';
+ -- datain_h.fragment
+ datain_h : in std_logic_vector(0 downto 0) := (others => '0');
+ -- datain_l.fragment
+ datain_l : in std_logic_vector(0 downto 0) := (others => '0')
);
end component;
begin
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd
index cc07d963c90b7fffc61cfd21e35ddc6887ae124b..72ef9fed9fd03fcec93ffb5f04883c3d7fc63ba0 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd
@@ -1,72 +1,136 @@
component ip_arria10_e1sg_ddr4_8g_2400 is
port (
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic; -- readdatavalid
- emif_usr_clk : out std_logic; -- clk
- emif_usr_reset_n : out std_logic; -- reset_n
- global_reset_n : in std_logic := 'X'; -- reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- pll_ref_clk : in std_logic := 'X'; -- clk
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic -- local_cal_fail
+ -- waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- read
+ amm_read_0 : in std_logic := 'X';
+ -- write
+ amm_write_0 : in std_logic := 'X';
+ -- address
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X');
+ -- readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X');
+ -- burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X');
+ -- byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X');
+ -- readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- clk
+ emif_usr_clk : out std_logic;
+ -- reset_n
+ emif_usr_reset_n : out std_logic;
+ -- reset_n
+ global_reset_n : in std_logic := 'X';
+ -- mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X');
+ -- mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- oct_rzqin
+ oct_rzqin : in std_logic := 'X';
+ -- clk
+ pll_ref_clk : in std_logic := 'X';
+ -- local_cal_success
+ local_cal_success : out std_logic;
+ -- local_cal_fail
+ local_cal_fail : out std_logic
);
end component ip_arria10_e1sg_ddr4_8g_2400;
u0 : component ip_arria10_e1sg_ddr4_8g_2400
port map (
- amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
- amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
- amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
- amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
- amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
- amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
- emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_reset_sink.reset_n
- mem_ck => CONNECTED_TO_mem_ck, -- mem_conduit_end.mem_ck
- mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
- mem_a => CONNECTED_TO_mem_a, -- .mem_a
- mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
- mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
- mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
- mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
- mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
- mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
- mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
- mem_par => CONNECTED_TO_mem_par, -- .mem_par
- mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
- mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
- mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
- mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
- mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
- oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => CONNECTED_TO_local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
+ -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_ready_0 => CONNECTED_TO_amm_ready_0,
+ -- .read
+ amm_read_0 => CONNECTED_TO_amm_read_0,
+ -- .write
+ amm_write_0 => CONNECTED_TO_amm_write_0,
+ -- .address
+ amm_address_0 => CONNECTED_TO_amm_address_0,
+ -- .readdata
+ amm_readdata_0 => CONNECTED_TO_amm_readdata_0,
+ -- .writedata
+ amm_writedata_0 => CONNECTED_TO_amm_writedata_0,
+ -- .burstcount
+ amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0,
+ -- .byteenable
+ amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0,
+ -- .readdatavalid
+ amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0,
+ -- emif_usr_clk_clock_source.clk
+ emif_usr_clk => CONNECTED_TO_emif_usr_clk,
+ -- emif_usr_reset_reset_source.reset_n
+ emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n,
+ -- global_reset_reset_sink.reset_n
+ global_reset_n => CONNECTED_TO_global_reset_n,
+ -- mem_conduit_end.mem_ck
+ mem_ck => CONNECTED_TO_mem_ck,
+ -- .mem_ck_n
+ mem_ck_n => CONNECTED_TO_mem_ck_n,
+ -- .mem_a
+ mem_a => CONNECTED_TO_mem_a,
+ -- .mem_act_n
+ mem_act_n => CONNECTED_TO_mem_act_n,
+ -- .mem_ba
+ mem_ba => CONNECTED_TO_mem_ba,
+ -- .mem_bg
+ mem_bg => CONNECTED_TO_mem_bg,
+ -- .mem_cke
+ mem_cke => CONNECTED_TO_mem_cke,
+ -- .mem_cs_n
+ mem_cs_n => CONNECTED_TO_mem_cs_n,
+ -- .mem_odt
+ mem_odt => CONNECTED_TO_mem_odt,
+ -- .mem_reset_n
+ mem_reset_n => CONNECTED_TO_mem_reset_n,
+ -- .mem_par
+ mem_par => CONNECTED_TO_mem_par,
+ -- .mem_alert_n
+ mem_alert_n => CONNECTED_TO_mem_alert_n,
+ -- .mem_dqs
+ mem_dqs => CONNECTED_TO_mem_dqs,
+ -- .mem_dqs_n
+ mem_dqs_n => CONNECTED_TO_mem_dqs_n,
+ -- .mem_dq
+ mem_dq => CONNECTED_TO_mem_dq,
+ -- .mem_dbi_n
+ mem_dbi_n => CONNECTED_TO_mem_dbi_n,
+ -- oct_conduit_end.oct_rzqin
+ oct_rzqin => CONNECTED_TO_oct_rzqin,
+ -- pll_ref_clk_clock_sink.clk
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk,
+ -- status_conduit_end.local_cal_success
+ local_cal_success => CONNECTED_TO_local_cal_success,
+ -- .local_cal_fail
+ local_cal_fail => CONNECTED_TO_local_cal_fail
);
diff --git a/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd b/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
index 647e77e35d41dd54ac94d3a24f3570e455abb9a0..60e31b0211316771dc525a441eac92ee43247a16 100644
--- a/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
+++ b/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
@@ -94,15 +94,18 @@ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
entity ip_arria10_e1sg_eth_10g is
generic (
g_sim : boolean := false;
- g_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model
+ -- 0 = use IP; 1 = use fast serdes model
+ g_sim_level : natural := 0;
g_nof_channels : natural := 1;
- g_direction : string := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "TX_RX";
g_use_loopback : boolean := false;
g_pre_header_padding : boolean := false
);
port (
-- Transceiver PLL reference clock
- tr_ref_clk_644 : in std_logic := '0'; -- 644.531250 MHz for 10GBASE-R
+ -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_644 : in std_logic := '0';
-- Data clocks
clk_312 : in std_logic := '0';
@@ -113,20 +116,24 @@ entity ip_arria10_e1sg_eth_10g is
mm_clk : in std_logic;
mm_rst : in std_logic;
- mac_mosi : in t_mem_mosi; -- MAG_10G (CSR)
+ -- MAG_10G (CSR)
+ mac_mosi : in t_mem_mosi;
mac_miso : out t_mem_miso;
- reg_eth10g_mosi : in t_mem_mosi; -- ETH10G (link status register)
+ -- ETH10G (link status register)
+ reg_eth10g_mosi : in t_mem_mosi;
reg_eth10g_miso : out t_mem_miso;
reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_ip_arria10_e1sg_phy_10gbase_r_24_miso : out t_mem_miso;
-- ST
- tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ tx_snk_in_arr : in t_dp_sosi_arr(g_nof_channels - 1 downto 0);
tx_snk_out_arr : out t_dp_siso_arr(g_nof_channels - 1 downto 0);
- rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0); -- 64 bit data @ clk_156
+ -- 64 bit data @ clk_156
+ rx_src_out_arr : out t_dp_sosi_arr(g_nof_channels - 1 downto 0);
rx_src_in_arr : in t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- Serial
@@ -137,8 +144,10 @@ end ip_arria10_e1sg_eth_10g;
architecture str of ip_arria10_e1sg_eth_10g is
-- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
- constant c_check_link_status : boolean := true; -- g_direction/="TX_ONLY";
- constant c_check_xgmii_tx_ready : boolean := true; -- g_direction/="RX_ONLY";
+ -- g_direction/="TX_ONLY";
+ constant c_check_link_status : boolean := true;
+ -- g_direction/="RX_ONLY";
+ constant c_check_xgmii_tx_ready : boolean := true;
signal i_tx_snk_out_arr : t_dp_siso_arr(g_nof_channels - 1 downto 0);
@@ -150,13 +159,20 @@ architecture str of ip_arria10_e1sg_eth_10g is
signal mac_snk_out_arr : t_dp_siso_arr(g_nof_channels - 1 downto 0);
-- XGMII
- signal xgmii_link_status_arr : t_tech_mac_10g_xgmii_status_arr(g_nof_channels - 1 downto 0); -- 2 bit, from MAC_10g
- signal xgmii_tx_ready_arr : std_logic_vector(g_nof_channels - 1 downto 0); -- 1 bit, from PHY 10gbase_r
- signal xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
- signal xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
- signal xgmii_tx_dc_arr_loopback : t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
- signal xgmii_rx_dc_arr_loopback : t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
- signal xgmii_internal_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
+ -- 2 bit, from MAC_10g
+ signal xgmii_link_status_arr : t_tech_mac_10g_xgmii_status_arr(g_nof_channels - 1 downto 0);
+ -- 1 bit, from PHY 10gbase_r
+ signal xgmii_tx_ready_arr : std_logic_vector(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ signal xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ signal xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ signal xgmii_tx_dc_arr_loopback : t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ signal xgmii_rx_dc_arr_loopback : t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
+ -- 72 bit
+ signal xgmii_internal_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0);
-- Link status monitor
constant c_mem_reg_eth10g_adr_w : natural := 1;
@@ -172,7 +188,8 @@ begin
tx_snk_out_arr <= i_tx_snk_out_arr;
gen_mac : for I in 0 to g_nof_channels - 1 generate
- i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
+ -- pass on MAC cycle accurate backpressure
+ i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready;
p_xon_flow_control : process(clk_156)
variable v_xgmii_link_status : std_logic_vector(c_tech_mac_10g_link_status_w - 1 downto 0) := "00";
@@ -182,12 +199,14 @@ begin
i_tx_snk_out_arr(I).xon <= '0';
-- First gather all conditions that are enabled to affect xon. The default value is such that it enables xon when the condition is not checked.
- if c_check_link_status = true then v_xgmii_link_status := xgmii_link_status_arr(I); end if; -- check both remote fault [1] and local fault [0]
+ -- check both remote fault [1] and local fault [0]
+ if c_check_link_status = true then v_xgmii_link_status := xgmii_link_status_arr(I); end if;
if c_check_xgmii_tx_ready = true then v_xgmii_tx_ready := xgmii_tx_ready_arr(I); end if;
-- Now apply the conditions to xon
if v_xgmii_tx_ready = '1' and v_xgmii_link_status = "00" then
- i_tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
+ -- XON when Tx PHY is ready and XGMII is ok
+ i_tx_snk_out_arr(I).xon <= '1';
end if;
end if;
end process;
@@ -208,13 +227,15 @@ begin
tx_clk_312 => clk_312,
tx_clk_156 => clk_156,
tx_rst => rst_156,
- tx_snk_in => tx_snk_in_arr(I), -- 64 bit data
+ -- 64 bit data
+ tx_snk_in => tx_snk_in_arr(I),
tx_snk_out => mac_snk_out_arr(I),
rx_clk_312 => clk_312,
rx_clk_156 => clk_156,
rx_rst => rst_156,
- rx_src_out => rx_src_out_arr(I), -- 64 bit data
+ -- 64 bit data
+ rx_src_out => rx_src_out_arr(I),
rx_src_in => rx_src_in_arr(I),
-- XGMII
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd
index ecea76e2bd81fe1af9db7e6cc7dd3381f0db988d..3e3e1098a2558a7a66c3c832ba224f79f511614e 100644
--- a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd
@@ -34,7 +34,8 @@ use altera_mf.all;
entity ip_arria10_e1sg_fifo_dc_mixed_widths is
generic (
- g_nof_words : natural := 1024; -- FIFO size in nof wr_dat words
+ -- FIFO size in nof wr_dat words
+ g_nof_words : natural := 1024;
g_wrdat_w : natural := 20;
g_rddat_w : natural := 10
);
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 554b93b24765987e6d81470ada650b9804adf087..ec99828016f3606d0b8f69e9bf44d46844420d10 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -41,31 +41,41 @@ entity ip_arria10_e1sg_jesd204b is
g_sim : boolean := false;
g_nof_streams : natural := 1;
g_nof_sync_n : natural := 1;
- g_direction : string := "RX_ONLY"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : string := "RX_ONLY";
g_jesd_freq : string := "200MHz"
);
port (
-- JESD204B external signals
- jesd204b_refclk : in std_logic := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
- jesd204b_sysref : in std_logic := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : out std_logic_vector(g_nof_sync_n - 1 downto 0); -- output to control ADC initialization/syncronization phase
+ -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
+ jesd204b_refclk : in std_logic := '0';
+ -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
+ jesd204b_sysref : in std_logic := '0';
+ -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : out std_logic_vector(g_nof_sync_n - 1 downto 0);
-- Data to fabric
- rx_src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data out to fabric
- rx_clk : out std_logic := '0'; -- Exported data clock (frame clock) to fabric
- rx_rst : out std_logic := '0'; -- Exported reset on rx_clk domain
- rx_sysref : out std_logic := '0'; -- Exported copy of sysref
+ -- Parallel data out to fabric
+ rx_src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ -- Exported data clock (frame clock) to fabric
+ rx_clk : out std_logic := '0';
+ -- Exported reset on rx_clk domain
+ rx_rst : out std_logic := '0';
+ -- Exported copy of sysref
+ rx_sysref : out std_logic := '0';
-- MM Control
mm_clk : in std_logic;
mm_rst : in std_logic;
jesd204b_disable_arr : in std_logic_vector(g_nof_streams - 1 downto 0);
- jesd204b_mosi : in t_mem_mosi; -- mm control
+ -- mm control
+ jesd204b_mosi : in t_mem_mosi;
jesd204b_miso : out t_mem_miso;
-- Serial connections to transceiver pins
- serial_tx_arr : out std_logic_vector(g_nof_streams - 1 downto 0); -- Not used for ADC
+ -- Not used for ADC
+ serial_tx_arr : out std_logic_vector(g_nof_streams - 1 downto 0);
serial_rx_arr : in std_logic_vector(g_nof_streams - 1 downto 0)
);
end ip_arria10_e1sg_jesd204b;
@@ -76,9 +86,12 @@ architecture str of ip_arria10_e1sg_jesd204b is
-- but using mm_addr_w = 8 and span = 256 words is fine too.
constant c_jesd204b_mm_addr_w : natural := 8;
constant c_jesd204b_rx_data_w : natural := 32;
- constant c_jesd204b_rx_framer_data_w : natural := c_jesd204b_rx_data_w / 2; -- IP outputs two samples in parallel
- constant c_jesd204b_rx_somf_w : natural := c_jesd204b_rx_data_w / 8; -- One somf bit per octet
- constant c_jesd204b_rx_framer_somf_w : natural := c_jesd204b_rx_somf_w / 2; -- IP outputs two samples in parallel
+ -- IP outputs two samples in parallel
+ constant c_jesd204b_rx_framer_data_w : natural := c_jesd204b_rx_data_w / 2;
+ -- One somf bit per octet
+ constant c_jesd204b_rx_somf_w : natural := c_jesd204b_rx_data_w / 8;
+ -- IP outputs two samples in parallel
+ constant c_jesd204b_rx_framer_somf_w : natural := c_jesd204b_rx_somf_w / 2;
constant c_nof_sync_n_per_group : natural := sel_a_b(g_nof_streams / g_nof_sync_n = 0, 1, g_nof_streams / g_nof_sync_n);
-- JESD204 control status registers
@@ -93,7 +106,8 @@ architecture str of ip_arria10_e1sg_jesd204b is
signal jesd204b_avs_clk : std_logic;
-- Reset and control signals
- signal dev_lane_aligned : std_logic_vector(g_nof_streams - 1 downto 0); -- 1 bit, each interface channel has 1 lane
+ -- 1 bit, each interface channel has 1 lane
+ signal dev_lane_aligned : std_logic_vector(g_nof_streams - 1 downto 0);
signal rx_analogreset_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rx_cal_busy_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rx_digitalreset_arr : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -127,107 +141,188 @@ architecture str of ip_arria10_e1sg_jesd204b is
signal jesd204b_rx_link_valid_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal jesd204b_rx_somf_arr : std_logic_vector(c_jesd204b_rx_somf_w * g_nof_streams - 1 downto 0);
- signal jesd204b_sync_n_internal_arr : std_logic_vector(g_nof_streams - 1 downto 0); -- output to control ADC initialization/syncronization phase
- signal jesd204b_sync_n_enabled_arr : std_logic_vector(g_nof_streams - 1 downto 0); -- output to control ADC initialization/syncronization phase
- signal jesd204b_sync_n_combined_arr : std_logic_vector(g_nof_sync_n - 1 downto 0); -- output to control ADC initialization/syncronization phase
+ -- output to control ADC initialization/syncronization phase
+ signal jesd204b_sync_n_internal_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ -- output to control ADC initialization/syncronization phase
+ signal jesd204b_sync_n_enabled_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ -- output to control ADC initialization/syncronization phase
+ signal jesd204b_sync_n_combined_arr : std_logic_vector(g_nof_sync_n - 1 downto 0);
-- Component declarations for the IP blocks
component ip_arria10_e1sg_jesd204b_rx_200MHz is
port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(c_jesd204b_mm_addr_w - 1 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(c_jesd204b_rx_data_w - 1 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(c_jesd204b_rx_somf_w - 1 downto 0); -- export
- sysref : in std_logic := 'X' -- export
+ -- export
+ alldev_lane_aligned : in std_logic := 'X';
+ -- export
+ csr_cf : out std_logic_vector(4 downto 0);
+ -- export
+ csr_cs : out std_logic_vector(1 downto 0);
+ -- export
+ csr_f : out std_logic_vector(7 downto 0);
+ -- export
+ csr_hd : out std_logic;
+ -- export
+ csr_k : out std_logic_vector(4 downto 0);
+ -- export
+ csr_l : out std_logic_vector(4 downto 0);
+ -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0);
+ -- export
+ csr_m : out std_logic_vector(7 downto 0);
+ -- export
+ csr_n : out std_logic_vector(4 downto 0);
+ -- export
+ csr_np : out std_logic_vector(4 downto 0);
+ -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0);
+ -- export
+ csr_s : out std_logic_vector(4 downto 0);
+ -- export
+ dev_lane_aligned : out std_logic;
+ -- export
+ dev_sync_n : out std_logic;
+ -- chipselect
+ jesd204_rx_avs_chipselect : in std_logic := 'X';
+ -- address
+ jesd204_rx_avs_address : in std_logic_vector(c_jesd204b_mm_addr_w - 1 downto 0) := (others => 'X');
+ -- read
+ jesd204_rx_avs_read : in std_logic := 'X';
+ -- readdata
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0);
+ -- waitrequest
+ jesd204_rx_avs_waitrequest : out std_logic;
+ -- write
+ jesd204_rx_avs_write : in std_logic := 'X';
+ -- writedata
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- clk
+ jesd204_rx_avs_clk : in std_logic := 'X';
+ -- reset_n
+ jesd204_rx_avs_rst_n : in std_logic := 'X';
+ -- export
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X');
+ -- export
+ jesd204_rx_frame_error : in std_logic := 'X';
+ -- irq
+ jesd204_rx_int : out std_logic;
+ -- data
+ jesd204_rx_link_data : out std_logic_vector(c_jesd204b_rx_data_w - 1 downto 0);
+ -- valid
+ jesd204_rx_link_valid : out std_logic;
+ -- ready
+ jesd204_rx_link_ready : in std_logic := 'X';
+ -- clk
+ pll_ref_clk : in std_logic := 'X';
+ -- rx_analogreset
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_cal_busy
+ rx_cal_busy : out std_logic_vector(0 downto 0);
+ -- rx_digitalreset
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- rx_is_lockedtodata
+ rx_islockedtodata : out std_logic_vector(0 downto 0);
+ -- rx_serial_data
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- clk
+ rxlink_clk : in std_logic := 'X';
+ -- reset_n
+ rxlink_rst_n_reset_n : in std_logic := 'X';
+ -- export
+ rxphy_clk : out std_logic_vector(0 downto 0);
+ -- export
+ sof : out std_logic_vector(3 downto 0);
+ -- export
+ somf : out std_logic_vector(c_jesd204b_rx_somf_w - 1 downto 0);
+ -- export
+ sysref : in std_logic := 'X'
);
end component ip_arria10_e1sg_jesd204b_rx_200MHz;
component ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz is
port (
- locked : out std_logic; -- export
- outclk_0 : out std_logic; -- clk
- outclk_1 : out std_logic; -- clk
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X' -- reset
+ -- export
+ locked : out std_logic;
+ -- clk
+ outclk_0 : out std_logic;
+ -- clk
+ outclk_1 : out std_logic;
+ -- clk
+ refclk : in std_logic := 'X';
+ -- reset
+ rst : in std_logic := 'X'
);
end component ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz;
component ip_arria10_e1sg_jesd204b_rx_reset_seq is
port (
- av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_read : in std_logic := 'X'; -- read
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_write : in std_logic := 'X'; -- write
- irq : out std_logic; -- irq
- clk : in std_logic := 'X'; -- clk
- csr_reset : in std_logic := 'X'; -- reset
- reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
- reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
- reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
- reset_in0 : in std_logic := 'X'; -- reset
- reset_out0 : out std_logic; -- reset
- reset_out1 : out std_logic; -- reset
- reset_out2 : out std_logic; -- reset
- reset_out3 : out std_logic; -- reset
- reset_out4 : out std_logic; -- reset
- reset_out5 : out std_logic; -- reset
- reset_out6 : out std_logic; -- reset
- reset_out7 : out std_logic -- reset
+ -- address
+ av_address : in std_logic_vector(7 downto 0) := (others => 'X');
+ -- readdata
+ av_readdata : out std_logic_vector(31 downto 0);
+ -- read
+ av_read : in std_logic := 'X';
+ -- writedata
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- write
+ av_write : in std_logic := 'X';
+ -- irq
+ irq : out std_logic;
+ -- clk
+ clk : in std_logic := 'X';
+ -- reset
+ csr_reset : in std_logic := 'X';
+ -- reset1_dsrt_qual
+ reset1_dsrt_qual : in std_logic := 'X';
+ -- reset2_dsrt_qual
+ reset2_dsrt_qual : in std_logic := 'X';
+ -- reset5_dsrt_qual
+ reset5_dsrt_qual : in std_logic := 'X';
+ -- reset
+ reset_in0 : in std_logic := 'X';
+ -- reset
+ reset_out0 : out std_logic;
+ -- reset
+ reset_out1 : out std_logic;
+ -- reset
+ reset_out2 : out std_logic;
+ -- reset
+ reset_out3 : out std_logic;
+ -- reset
+ reset_out4 : out std_logic;
+ -- reset
+ reset_out5 : out std_logic;
+ -- reset
+ reset_out6 : out std_logic;
+ -- reset
+ reset_out7 : out std_logic
);
end component ip_arria10_e1sg_jesd204b_rx_reset_seq;
component ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12 is
port (
- clock : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- rx_analogreset : out std_logic_vector(11 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(11 downto 0) := (others => 'X'); -- rx_cal_busy
- rx_digitalreset : out std_logic_vector(11 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_ready : out std_logic_vector(11 downto 0) -- rx_ready
+ -- clk
+ clock : in std_logic := 'X';
+ -- reset
+ reset : in std_logic := 'X';
+ -- rx_analogreset
+ rx_analogreset : out std_logic_vector(11 downto 0);
+ -- rx_cal_busy
+ rx_cal_busy : in std_logic_vector(11 downto 0) := (others => 'X');
+ -- rx_digitalreset
+ rx_digitalreset : out std_logic_vector(11 downto 0);
+ -- rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => 'X');
+ -- rx_ready
+ rx_ready : out std_logic_vector(11 downto 0)
);
end component ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
begin
@@ -280,25 +375,35 @@ begin
jesd204_rx_avs_writedata => jesd204b_mosi_arr(i).wrdata(31 downto 0),
jesd204_rx_avs_clk => jesd204b_avs_clk,
jesd204_rx_avs_rst_n => rx_avs_rst_n_arr(i),
- jesd204_rx_dlb_data => (others => '0'), -- debug/loopback testing
- jesd204_rx_dlb_data_valid => (others => '0'), -- debug/loopback testing
- jesd204_rx_dlb_disperr => (others => '0'), -- debug/loopback testing
- jesd204_rx_dlb_errdetect => (others => '0'), -- debug/loopback testing
- jesd204_rx_dlb_kchar_data => (others => '0'), -- debug/loopback testing
- jesd204_rx_frame_error => '0', -- jesd204_rx_frame_error.export
- jesd204_rx_int => OPEN, -- Connected to status IO in example design
+ -- debug/loopback testing
+ jesd204_rx_dlb_data => (others => '0'),
+ -- debug/loopback testing
+ jesd204_rx_dlb_data_valid => (others => '0'),
+ -- debug/loopback testing
+ jesd204_rx_dlb_disperr => (others => '0'),
+ -- debug/loopback testing
+ jesd204_rx_dlb_errdetect => (others => '0'),
+ -- debug/loopback testing
+ jesd204_rx_dlb_kchar_data => (others => '0'),
+ -- jesd204_rx_frame_error.export
+ jesd204_rx_frame_error => '0',
+ -- Connected to status IO in example design
+ jesd204_rx_int => OPEN,
jesd204_rx_link_data => jesd204b_rx_link_data_arr(i * c_jesd204b_rx_data_w + c_jesd204b_rx_data_w - 1 downto i * c_jesd204b_rx_data_w),
jesd204_rx_link_valid => jesd204b_rx_link_valid_arr(i),
jesd204_rx_link_ready => '1',
- pll_ref_clk => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63)
+ -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63)
+ pll_ref_clk => jesd204b_refclk,
rx_analogreset => rx_analogreset_arr(I downto I),
rx_cal_busy => rx_cal_busy_arr(I downto I),
rx_digitalreset => rx_digitalreset_arr(I downto I),
rx_islockedtodata => rx_islockedtodata_arr(I downto I),
rx_serial_data => serial_rx_arr(i downto i),
rxlink_clk => rxlink_clk,
- rxlink_rst_n_reset_n => rxlink_rst_n_arr(i), -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
- rxphy_clk => OPEN, -- Not used in Subclass 0 (Intel JESD204B-UG p63)
+ -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
+ rxlink_rst_n_reset_n => rxlink_rst_n_arr(i),
+ -- Not used in Subclass 0 (Intel JESD204B-UG p63)
+ rxphy_clk => OPEN,
sof => OPEN,
somf => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1 downto c_jesd204b_rx_somf_w * i),
sysref => jesd204b_sysref_2
@@ -319,15 +424,20 @@ begin
av_writedata => reset_seq_mosi_arr(i).wrdata(31 downto 0),
av_write => reset_seq_mosi_arr(i).wr,
irq => open,
- clk => mm_clk, -- use clk = mm_clk for av_* port
+ -- use clk = mm_clk for av_* port
+ clk => mm_clk,
csr_reset => mm_rst,
- reset1_dsrt_qual => mm_core_pll_locked_reg, -- core pll_locked synchronised to clk = mm_clk domain
- reset2_dsrt_qual => '1', -- Tied to '1' in example design. Tx xcvr is not used.
+ -- core pll_locked synchronised to clk = mm_clk domain
+ reset1_dsrt_qual => mm_core_pll_locked_reg,
+ -- Tied to '1' in example design. Tx xcvr is not used.
+ reset2_dsrt_qual => '1',
reset5_dsrt_qual => mm_rx_xcvr_ready_in_arr(i),
reset_in0 => mm_rst,
-- reset_out* signals are in mm_clk domain
- reset_out0 => pll_reset_async_arr(i), -- Use channel 0 to reset the core pll
- reset_out1 => xcvr_rst_arr(i), -- Use channel 1 to reset the transceiver reset controller
+ -- Use channel 0 to reset the core pll
+ reset_out0 => pll_reset_async_arr(i),
+ -- Use channel 1 to reset the transceiver reset controller
+ reset_out1 => xcvr_rst_arr(i),
reset_out2 => open,
reset_out3 => open,
reset_out4 => open,
@@ -364,7 +474,8 @@ begin
-- synchronize rx_xcvr_ready_in_arr to mm_clk
u_common_async_rx_xcvr_ready : entity common_lib.common_async
generic map (
- g_rst_level => '0' -- When in_rst is asserted, dout = '0'
+ -- When in_rst is asserted, dout = '0'
+ g_rst_level => '0'
)
port map (
rst => mm_rst,
@@ -407,7 +518,8 @@ begin
end if;
end if;
end process;
- end generate; -- gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ -- gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ end generate;
-----------------------------------------------------------------------------
-- Reclock sysref and the sync_n output
@@ -440,7 +552,8 @@ begin
rx_sysref <= '0';
else
if rising_edge(rxframe_clk) then
- jesd204b_sysref_frameclk_1 <= jesd204b_sysref_2; -- sysref from rxlink_clk domain
+ -- sysref from rxlink_clk domain
+ jesd204b_sysref_frameclk_1 <= jesd204b_sysref_2;
jesd204b_sysref_frameclk_2 <= jesd204b_sysref_frameclk_1;
if jesd204b_sysref_frameclk_1 = '1' and jesd204b_sysref_frameclk_2 = '0' then
rx_sysref <= '1';
@@ -456,16 +569,20 @@ begin
u_ip_arria10_e1sg_jesd204b_rx_corepll_200MHz : ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz
port map (
locked => core_pll_locked,
- outclk_0 => rxlink_clk, -- out 100 MHz
- outclk_1 => rxframe_clk, -- out 200 MHz
- refclk => jesd204b_refclk, -- in 200 MHz
+ -- out 100 MHz
+ outclk_0 => rxlink_clk,
+ -- out 200 MHz
+ outclk_1 => rxframe_clk,
+ -- in 200 MHz
+ refclk => jesd204b_refclk,
rst => pll_reset_arr(0)
);
end generate;
u_common_areset_pll_locked : entity common_lib.common_areset
generic map (
- g_in_rst_level => '0', -- synchronises the rising edge of input in_rst.
+ -- synchronises the rising edge of input in_rst.
+ g_in_rst_level => '0',
g_rst_level => '0'
)
port map (
@@ -480,14 +597,21 @@ begin
u_ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control : ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12
port map (
clock => rxlink_clk,
- reset => xcvr_rst_arr(0), -- From Reset Sequencer output1 as per example design, the reset input is synchronised internally.
- rx_analogreset => rx_analogreset_arr, -- output to reset RX PMA. Release before deasserting link and avs resets (Intel JESD204B-UG p70)
- rx_cal_busy => rx_cal_busy_arr, -- input from PHY
- rx_digitalreset => rx_digitalreset_arr, -- output to reset RX PCS. Release before deasserting link and avs resets (Intel JESD204B-UG p70)
- rx_is_lockedtodata => rx_islockedtodata_arr, -- input from PHY
- rx_ready => xcvr_rst_ctrl_rx_ready_arr -- From example design: gate with rx_csr_lane_powerdown to reset transceiver
+ -- From Reset Sequencer output1 as per example design, the reset input is synchronised internally.
+ reset => xcvr_rst_arr(0),
+ -- output to reset RX PMA. Release before deasserting link and avs resets (Intel JESD204B-UG p70)
+ rx_analogreset => rx_analogreset_arr,
+ -- input from PHY
+ rx_cal_busy => rx_cal_busy_arr,
+ -- output to reset RX PCS. Release before deasserting link and avs resets (Intel JESD204B-UG p70)
+ rx_digitalreset => rx_digitalreset_arr,
+ -- input from PHY
+ rx_is_lockedtodata => rx_islockedtodata_arr,
+ -- From example design: gate with rx_csr_lane_powerdown to reset transceiver
+ rx_ready => xcvr_rst_ctrl_rx_ready_arr
);
- end generate; -- gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
+ -- gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
+ end generate;
gen_enable_sync_n : for i in 0 to g_nof_streams - 1 generate
-- The sync_n_enabled output is active '0'. For disabled signal inputs the sync_n_enabled output is forced to '1', so that for the disabled (= inactive = not used)
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_component_pkg.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_component_pkg.vhd
index 34caad0fcfcdf69e98583acd436695420caaca11..7d0f8ab4ec1e1cef86924e34ffe26b3f71a271ec 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_component_pkg.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_component_pkg.vhd
@@ -36,53 +36,100 @@ package ip_arria10_e1sg_jesd204b_component_pkg is
component ip_arria10_e1sg_jesd204b_tx is
port (
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- csr_tx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_tx_testpattern_a : out std_logic_vector(31 downto 0); -- export
- csr_tx_testpattern_b : out std_logic_vector(31 downto 0); -- export
- csr_tx_testpattern_c : out std_logic_vector(31 downto 0); -- export
- csr_tx_testpattern_d : out std_logic_vector(31 downto 0); -- export
- dev_sync_n : out std_logic; -- export
- jesd204_tx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_tx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_tx_avs_read : in std_logic := 'X'; -- read
- jesd204_tx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_tx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_tx_avs_write : in std_logic := 'X'; -- write
- jesd204_tx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_tx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_tx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_tx_dlb_data : out std_logic_vector(31 downto 0); -- export
- jesd204_tx_dlb_kchar_data : out std_logic_vector(3 downto 0); -- export
- jesd204_tx_frame_error : in std_logic := 'X'; -- export
- jesd204_tx_frame_ready : out std_logic; -- export
- jesd204_tx_int : out std_logic; -- irq
- jesd204_tx_link_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
- jesd204_tx_link_valid : in std_logic := 'X'; -- valid
- jesd204_tx_link_ready : out std_logic; -- ready
- mdev_sync_n : in std_logic := 'X'; -- export
- pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
- somf : out std_logic_vector(3 downto 0); -- export
- sync_n : in std_logic := 'X'; -- export
- sysref : in std_logic := 'X'; -- export
- tx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_analogreset
- tx_bonding_clocks : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
- tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy
- tx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_digitalreset
- tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data
- txlink_clk : in std_logic := 'X'; -- clk
- txlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- txphy_clk : out std_logic_vector(0 downto 0) -- export
+ -- export
+ csr_cf : out std_logic_vector(4 downto 0);
+ -- export
+ csr_cs : out std_logic_vector(1 downto 0);
+ -- export
+ csr_f : out std_logic_vector(7 downto 0);
+ -- export
+ csr_hd : out std_logic;
+ -- export
+ csr_k : out std_logic_vector(4 downto 0);
+ -- export
+ csr_l : out std_logic_vector(4 downto 0);
+ -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0);
+ -- export
+ csr_m : out std_logic_vector(7 downto 0);
+ -- export
+ csr_n : out std_logic_vector(4 downto 0);
+ -- export
+ csr_np : out std_logic_vector(4 downto 0);
+ -- export
+ csr_s : out std_logic_vector(4 downto 0);
+ -- export
+ csr_tx_testmode : out std_logic_vector(3 downto 0);
+ -- export
+ csr_tx_testpattern_a : out std_logic_vector(31 downto 0);
+ -- export
+ csr_tx_testpattern_b : out std_logic_vector(31 downto 0);
+ -- export
+ csr_tx_testpattern_c : out std_logic_vector(31 downto 0);
+ -- export
+ csr_tx_testpattern_d : out std_logic_vector(31 downto 0);
+ -- export
+ dev_sync_n : out std_logic;
+ -- chipselect
+ jesd204_tx_avs_chipselect : in std_logic := 'X';
+ -- address
+ jesd204_tx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X');
+ -- read
+ jesd204_tx_avs_read : in std_logic := 'X';
+ -- readdata
+ jesd204_tx_avs_readdata : out std_logic_vector(31 downto 0);
+ -- waitrequest
+ jesd204_tx_avs_waitrequest : out std_logic;
+ -- write
+ jesd204_tx_avs_write : in std_logic := 'X';
+ -- writedata
+ jesd204_tx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- clk
+ jesd204_tx_avs_clk : in std_logic := 'X';
+ -- reset_n
+ jesd204_tx_avs_rst_n : in std_logic := 'X';
+ -- export
+ jesd204_tx_dlb_data : out std_logic_vector(31 downto 0);
+ -- export
+ jesd204_tx_dlb_kchar_data : out std_logic_vector(3 downto 0);
+ -- export
+ jesd204_tx_frame_error : in std_logic := 'X';
+ -- export
+ jesd204_tx_frame_ready : out std_logic;
+ -- irq
+ jesd204_tx_int : out std_logic;
+ -- data
+ jesd204_tx_link_data : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- valid
+ jesd204_tx_link_valid : in std_logic := 'X';
+ -- ready
+ jesd204_tx_link_ready : out std_logic;
+ -- export
+ mdev_sync_n : in std_logic := 'X';
+ -- pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- export
+ somf : out std_logic_vector(3 downto 0);
+ -- export
+ sync_n : in std_logic := 'X';
+ -- export
+ sysref : in std_logic := 'X';
+ -- tx_analogreset
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- clk
+ tx_bonding_clocks : in std_logic_vector(5 downto 0) := (others => 'X');
+ -- tx_cal_busy
+ tx_cal_busy : out std_logic_vector(0 downto 0);
+ -- tx_digitalreset
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- tx_serial_data
+ tx_serial_data : out std_logic_vector(0 downto 0);
+ -- clk
+ txlink_clk : in std_logic := 'X';
+ -- reset_n
+ txlink_rst_n_reset_n : in std_logic := 'X';
+ -- export
+ txphy_clk : out std_logic_vector(0 downto 0)
);
end component ip_arria10_e1sg_jesd204b_tx;
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add2/ip_arria10_e1sg_mult_add2_rtl.vhd b/libraries/technology/ip_arria10_e1sg/mult_add2/ip_arria10_e1sg_mult_add2_rtl.vhd
index fc7268d3e9c444cc2de06541c8ccabbc64ffcc05..c343a8eeff92fec35e815898674cb6dfb3de7203 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add2/ip_arria10_e1sg_mult_add2_rtl.vhd
+++ b/libraries/technology/ip_arria10_e1sg/mult_add2/ip_arria10_e1sg_mult_add2_rtl.vhd
@@ -36,14 +36,22 @@ entity ip_arria10_e1sg_mult_add2_rtl is
generic (
g_in_a_w : positive;
g_in_b_w : positive;
- g_res_w : positive; -- g_in_a_w + g_in_b_w + log2(2)
- g_force_dsp : boolean := true; -- when TRUE resize input width to >= 18
- g_add_sub : string := "ADD"; -- or "SUB"
- g_nof_mult : integer := 2; -- fixed
- g_pipeline_input : natural := 1; -- 0 or 1
- g_pipeline_product : natural := 0; -- 0 or 1
- g_pipeline_adder : natural := 1; -- 0 or 1
- g_pipeline_output : natural := 1 -- >= 0
+ -- g_in_a_w + g_in_b_w + log2(2)
+ g_res_w : positive;
+ -- when TRUE resize input width to >= 18
+ g_force_dsp : boolean := true;
+ -- or "SUB"
+ g_add_sub : string := "ADD";
+ -- fixed
+ g_nof_mult : integer := 2;
+ -- 0 or 1
+ g_pipeline_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_product : natural := 0;
+ -- 0 or 1
+ g_pipeline_adder : natural := 1;
+ -- >= 0
+ g_pipeline_output : natural := 1
);
port (
rst : in std_logic := '0';
@@ -111,14 +119,18 @@ begin
reg_sum <= (others => '0');
reg_result <= (others => '0');
elsif clken = '1' then
- reg_a0 <= nxt_a0; -- inputs
+ -- inputs
+ reg_a0 <= nxt_a0;
reg_b0 <= nxt_b0;
reg_a1 <= nxt_a1;
reg_b1 <= nxt_b1;
- reg_prod0 <= nxt_prod0; -- products
+ -- products
+ reg_prod0 <= nxt_prod0;
reg_prod1 <= nxt_prod1;
- reg_sum <= nxt_sum; -- sum
- reg_result <= nxt_result; -- result sum after optional rounding
+ -- sum
+ reg_sum <= nxt_sum;
+ -- result sum after optional rounding
+ reg_result <= nxt_result;
end if;
end if;
end process;
@@ -132,14 +144,16 @@ begin
nxt_a1 <= signed(in_a(2 * g_in_a_w - 1 downto g_in_a_w));
nxt_b1 <= signed(in_b(2 * g_in_b_w - 1 downto g_in_b_w));
- no_input_reg : if g_pipeline_input = 0 generate -- wired
+ -- wired
+ no_input_reg : if g_pipeline_input = 0 generate
a0 <= nxt_a0;
b0 <= nxt_b0;
a1 <= nxt_a1;
b1 <= nxt_b1;
end generate;
- gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ -- register input
+ gen_input_reg : if g_pipeline_input > 0 generate
a0 <= reg_a0;
b0 <= reg_b0;
a1 <= reg_a1;
@@ -153,11 +167,13 @@ begin
nxt_prod0 <= a0 * b0;
nxt_prod1 <= a1 * b1;
- no_product_reg : if g_pipeline_product = 0 generate -- wired
+ -- wired
+ no_product_reg : if g_pipeline_product = 0 generate
prod0 <= nxt_prod0;
prod1 <= nxt_prod1;
end generate;
- gen_product_reg : if g_pipeline_product > 0 generate -- register
+ -- register
+ gen_product_reg : if g_pipeline_product > 0 generate
prod0 <= reg_prod0;
prod1 <= reg_prod1;
end generate;
@@ -173,10 +189,12 @@ begin
nxt_sum <= RESIZE_NUM(prod0, c_sum_w) - prod1;
end generate;
- no_adder_reg : if g_pipeline_adder = 0 generate -- wired
+ -- wired
+ no_adder_reg : if g_pipeline_adder = 0 generate
sum <= nxt_sum;
end generate;
- gen_adder_reg : if g_pipeline_adder > 0 generate -- register
+ -- register
+ gen_adder_reg : if g_pipeline_adder > 0 generate
sum <= reg_sum;
end generate;
@@ -186,10 +204,12 @@ begin
nxt_result <= RESIZE_NUM(sum, g_res_w);
- no_result_reg : if g_pipeline_output = 0 generate -- wired
+ -- wired
+ no_result_reg : if g_pipeline_output = 0 generate
result <= nxt_result;
end generate;
- gen_result_reg : if g_pipeline_output > 0 generate -- register
+ -- register
+ gen_result_reg : if g_pipeline_output > 0 generate
result <= reg_result;
end generate;
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4_rtl.vhd b/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4_rtl.vhd
index 15194254d6fa8d95428031c115878884d44f36cc..4a1c5362f02b64f682d8d549c41cfc13212dd394 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4_rtl.vhd
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4_rtl.vhd
@@ -31,16 +31,26 @@ entity ip_arria10_e1sg_mult_add4_rtl is
generic (
g_in_a_w : positive;
g_in_b_w : positive;
- g_res_w : positive; -- g_in_a_w + g_in_b_w + log2(4)
- g_force_dsp : boolean := true; -- when TRUE resize input width to >= 18
- g_add_sub0 : string := "ADD"; -- or "SUB"
- g_add_sub1 : string := "ADD"; -- or "SUB"
- g_add_sub : string := "ADD"; -- or "SUB" only available with rtl architecture
- g_nof_mult : integer := 4; -- fixed
- g_pipeline_input : natural := 1; -- 0 or 1
- g_pipeline_product : natural := 0; -- 0 or 1
- g_pipeline_adder : natural := 1; -- 0 or 1, first sum
- g_pipeline_output : natural := 1 -- >= 0, second sum and optional rounding
+ -- g_in_a_w + g_in_b_w + log2(4)
+ g_res_w : positive;
+ -- when TRUE resize input width to >= 18
+ g_force_dsp : boolean := true;
+ -- or "SUB"
+ g_add_sub0 : string := "ADD";
+ -- or "SUB"
+ g_add_sub1 : string := "ADD";
+ -- or "SUB" only available with rtl architecture
+ g_add_sub : string := "ADD";
+ -- fixed
+ g_nof_mult : integer := 4;
+ -- 0 or 1
+ g_pipeline_input : natural := 1;
+ -- 0 or 1
+ g_pipeline_product : natural := 0;
+ -- 0 or 1, first sum
+ g_pipeline_adder : natural := 1;
+ -- >= 0, second sum and optional rounding
+ g_pipeline_output : natural := 1
);
port (
rst : in std_logic := '0';
@@ -134,7 +144,8 @@ begin
reg_sum1 <= (others => '0');
reg_result <= (others => '0');
elsif clken = '1' then
- reg_a0 <= nxt_a0; -- inputs
+ -- inputs
+ reg_a0 <= nxt_a0;
reg_b0 <= nxt_b0;
reg_a1 <= nxt_a1;
reg_b1 <= nxt_b1;
@@ -142,13 +153,16 @@ begin
reg_b2 <= nxt_b2;
reg_a3 <= nxt_a3;
reg_b3 <= nxt_b3;
- reg_prod0 <= nxt_prod0; -- products
+ -- products
+ reg_prod0 <= nxt_prod0;
reg_prod1 <= nxt_prod1;
reg_prod2 <= nxt_prod2;
reg_prod3 <= nxt_prod3;
- reg_sum0 <= nxt_sum0; -- first sum
+ -- first sum
+ reg_sum0 <= nxt_sum0;
reg_sum1 <= nxt_sum1;
- reg_result <= nxt_result; -- result second sum after optional rounding
+ -- result second sum after optional rounding
+ reg_result <= nxt_result;
end if;
end if;
end process;
@@ -166,7 +180,8 @@ begin
nxt_a3 <= signed(in_a(4 * g_in_a_w - 1 downto 3 * g_in_a_w));
nxt_b3 <= signed(in_b(4 * g_in_b_w - 1 downto 3 * g_in_b_w));
- no_input_reg : if g_pipeline_input = 0 generate -- wired
+ -- wired
+ no_input_reg : if g_pipeline_input = 0 generate
a0 <= nxt_a0;
b0 <= nxt_b0;
a1 <= nxt_a1;
@@ -177,7 +192,8 @@ begin
b3 <= nxt_b3;
end generate;
- gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ -- register input
+ gen_input_reg : if g_pipeline_input > 0 generate
a0 <= reg_a0;
b0 <= reg_b0;
a1 <= reg_a1;
@@ -197,13 +213,15 @@ begin
nxt_prod2 <= a2 * b2;
nxt_prod3 <= a3 * b3;
- no_product_reg : if g_pipeline_product = 0 generate -- wired
+ -- wired
+ no_product_reg : if g_pipeline_product = 0 generate
prod0 <= nxt_prod0;
prod1 <= nxt_prod1;
prod2 <= nxt_prod2;
prod3 <= nxt_prod3;
end generate;
- gen_product_reg : if g_pipeline_product > 0 generate -- register
+ -- register
+ gen_product_reg : if g_pipeline_product > 0 generate
prod0 <= reg_prod0;
prod1 <= reg_prod1;
prod2 <= reg_prod2;
@@ -230,11 +248,13 @@ begin
end generate;
-- Optinal first sum register
- no_adder_reg : if g_pipeline_adder = 0 generate -- wired
+ -- wired
+ no_adder_reg : if g_pipeline_adder = 0 generate
sum0 <= nxt_sum0;
sum1 <= nxt_sum1;
end generate;
- gen_adder_reg : if g_pipeline_adder > 0 generate -- register
+ -- register
+ gen_adder_reg : if g_pipeline_adder > 0 generate
sum0 <= reg_sum0;
sum1 <= reg_sum1;
end generate;
@@ -258,10 +278,12 @@ begin
nxt_result <= RESIZE_NUM(sum, res'length);
- no_result_reg : if g_pipeline_output = 0 generate -- wired
+ -- wired
+ no_result_reg : if g_pipeline_output = 0 generate
result <= nxt_result;
end generate;
- gen_result_reg : if g_pipeline_output > 0 generate -- register
+ -- register
+ gen_result_reg : if g_pipeline_output > 0 generate
result <= reg_result;
end generate;
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
index 604b4da043e9b3dc2ff0ee6a7e54bc19fbb53a16..95d9c568a5bb2153c212c0c34bec2506906ee2b2 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
@@ -35,7 +35,8 @@ entity ip_arria10_e1sg_ram_cr_cw is
g_adr_w : natural := 5;
g_dat_w : natural := 8;
g_nof_words : natural := 2**5;
- g_rd_latency : natural := 1; -- choose 1 or 2
+ -- choose 1 or 2
+ g_rd_latency : natural := 1;
g_init_file : string := "UNUSED"
);
port
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
index 3335b480bba324a51cde55b65c2248a71afe36b9..6cb4ac74082fe61706ab58325668c12de62b9817 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
@@ -35,7 +35,8 @@ entity ip_arria10_e1sg_ram_crw_crw is
g_adr_w : natural := 5;
g_dat_w : natural := 8;
g_nof_words : natural := 2**5;
- g_rd_latency : natural := 1; -- choose 1 or 2
+ -- choose 1 or 2
+ g_rd_latency : natural := 1;
g_init_file : string := "UNUSED"
);
port
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
index 8adae627db1858f16fa621d56a95bd906f97e783..b3787ac72b2a37725ff0f810c6c376a2ea887d61 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
@@ -25,7 +25,8 @@ entity ip_arria10_e1sg_ram_crwk_crw is
g_dat_b_w : natural := 64;
g_nof_words_a : natural := 2**5;
g_nof_words_b : natural := 2**4;
- g_rd_latency : natural := 1; -- choose 1 or 2
+ -- choose 1 or 2
+ g_rd_latency : natural := 1;
g_init_file : string := "UNUSED"
);
port
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd
index d6f8e5d7c4e426f455ee85725d61eb4b9ceeebe8..8d5d3a155e591f43d67fb505286dede21f0c01a6 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd
@@ -1,32 +1,56 @@
component ip_arria10_e1sg_ram_crwk_crw is
port (
- data_a : in std_logic_vector(31 downto 0) := (others => 'X'); -- datain_a
- data_b : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_b
- address_a : in std_logic_vector(7 downto 0) := (others => 'X'); -- address_a
- address_b : in std_logic_vector(9 downto 0) := (others => 'X'); -- address_b
- wren_a : in std_logic := 'X'; -- wren_a
- wren_b : in std_logic := 'X'; -- wren_b
- clock_a : in std_logic := 'X'; -- clock_a
- clock_b : in std_logic := 'X'; -- clock_b
- rden_a : in std_logic := 'X'; -- rden_a
- rden_b : in std_logic := 'X'; -- rden_b
- q_a : out std_logic_vector(31 downto 0); -- dataout_a
- q_b : out std_logic_vector(7 downto 0) -- dataout_b
+ -- datain_a
+ data_a : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- datain_b
+ data_b : in std_logic_vector(7 downto 0) := (others => 'X');
+ -- address_a
+ address_a : in std_logic_vector(7 downto 0) := (others => 'X');
+ -- address_b
+ address_b : in std_logic_vector(9 downto 0) := (others => 'X');
+ -- wren_a
+ wren_a : in std_logic := 'X';
+ -- wren_b
+ wren_b : in std_logic := 'X';
+ -- clock_a
+ clock_a : in std_logic := 'X';
+ -- clock_b
+ clock_b : in std_logic := 'X';
+ -- rden_a
+ rden_a : in std_logic := 'X';
+ -- rden_b
+ rden_b : in std_logic := 'X';
+ -- dataout_a
+ q_a : out std_logic_vector(31 downto 0);
+ -- dataout_b
+ q_b : out std_logic_vector(7 downto 0)
);
end component ip_arria10_e1sg_ram_crwk_crw;
u0 : component ip_arria10_e1sg_ram_crwk_crw
port map (
- data_a => CONNECTED_TO_data_a, -- ram_input.datain_a
- data_b => CONNECTED_TO_data_b, -- .datain_b
- address_a => CONNECTED_TO_address_a, -- .address_a
- address_b => CONNECTED_TO_address_b, -- .address_b
- wren_a => CONNECTED_TO_wren_a, -- .wren_a
- wren_b => CONNECTED_TO_wren_b, -- .wren_b
- clock_a => CONNECTED_TO_clock_a, -- .clock_a
- clock_b => CONNECTED_TO_clock_b, -- .clock_b
- rden_a => CONNECTED_TO_rden_a, -- .rden_a
- rden_b => CONNECTED_TO_rden_b, -- .rden_b
- q_a => CONNECTED_TO_q_a, -- ram_output.dataout_a
- q_b => CONNECTED_TO_q_b -- .dataout_b
+ -- ram_input.datain_a
+ data_a => CONNECTED_TO_data_a,
+ -- .datain_b
+ data_b => CONNECTED_TO_data_b,
+ -- .address_a
+ address_a => CONNECTED_TO_address_a,
+ -- .address_b
+ address_b => CONNECTED_TO_address_b,
+ -- .wren_a
+ wren_a => CONNECTED_TO_wren_a,
+ -- .wren_b
+ wren_b => CONNECTED_TO_wren_b,
+ -- .clock_a
+ clock_a => CONNECTED_TO_clock_a,
+ -- .clock_b
+ clock_b => CONNECTED_TO_clock_b,
+ -- .rden_a
+ rden_a => CONNECTED_TO_rden_a,
+ -- .rden_b
+ rden_b => CONNECTED_TO_rden_b,
+ -- ram_output.dataout_a
+ q_a => CONNECTED_TO_q_a,
+ -- .dataout_b
+ q_b => CONNECTED_TO_q_b
);
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
index 6cf10c4b343c813eda054b30486357a231fe740c..6496f0353fbeb85089def56fd6b04a8b88674692 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
@@ -35,7 +35,8 @@ entity ip_arria10_e1sg_ram_r_w is
g_adr_w : natural := 5;
g_dat_w : natural := 8;
g_nof_words : natural := 2**5;
- g_rd_latency : natural := 1; -- choose 1 or 2
+ -- choose 1 or 2
+ g_rd_latency : natural := 1;
g_init_file : string := "UNUSED"
);
port (
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd
index 340470c1754886571c8d2ec237c9c2b81c18873f..03f70106f8b6e00a2b22b2111fce5db03aa4e53d 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd
@@ -1,36 +1,64 @@
component ip_arria10_e1sg_transceiver_reset_controller_3 is
port (
- clock : in std_logic := 'X'; -- clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
- reset : in std_logic := 'X'; -- reset
- rx_analogreset : out std_logic_vector(2 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_cal_busy
- rx_digitalreset : out std_logic_vector(2 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_ready : out std_logic_vector(2 downto 0); -- rx_ready
- tx_analogreset : out std_logic_vector(2 downto 0); -- tx_analogreset
- tx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_cal_busy
- tx_digitalreset : out std_logic_vector(2 downto 0); -- tx_digitalreset
- tx_ready : out std_logic_vector(2 downto 0) -- tx_ready
+ -- clk
+ clock : in std_logic := 'X';
+ -- pll_locked
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- pll_powerdown
+ pll_powerdown : out std_logic_vector(0 downto 0);
+ -- pll_select
+ pll_select : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- reset
+ reset : in std_logic := 'X';
+ -- rx_analogreset
+ rx_analogreset : out std_logic_vector(2 downto 0);
+ -- rx_cal_busy
+ rx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X');
+ -- rx_digitalreset
+ rx_digitalreset : out std_logic_vector(2 downto 0);
+ -- rx_is_lockedtodata
+ rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => 'X');
+ -- rx_ready
+ rx_ready : out std_logic_vector(2 downto 0);
+ -- tx_analogreset
+ tx_analogreset : out std_logic_vector(2 downto 0);
+ -- tx_cal_busy
+ tx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X');
+ -- tx_digitalreset
+ tx_digitalreset : out std_logic_vector(2 downto 0);
+ -- tx_ready
+ tx_ready : out std_logic_vector(2 downto 0)
);
end component ip_arria10_e1sg_transceiver_reset_controller_3;
u0 : component ip_arria10_e1sg_transceiver_reset_controller_3
port map (
- clock => CONNECTED_TO_clock, -- clock.clk
- pll_locked => CONNECTED_TO_pll_locked, -- pll_locked.pll_locked
- pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
- pll_select => CONNECTED_TO_pll_select, -- pll_select.pll_select
- reset => CONNECTED_TO_reset, -- reset.reset
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => CONNECTED_TO_rx_ready, -- rx_ready.rx_ready
- tx_analogreset => CONNECTED_TO_tx_analogreset, -- tx_analogreset.tx_analogreset
- tx_cal_busy => CONNECTED_TO_tx_cal_busy, -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => CONNECTED_TO_tx_digitalreset, -- tx_digitalreset.tx_digitalreset
- tx_ready => CONNECTED_TO_tx_ready -- tx_ready.tx_ready
+ -- clock.clk
+ clock => CONNECTED_TO_clock,
+ -- pll_locked.pll_locked
+ pll_locked => CONNECTED_TO_pll_locked,
+ -- pll_powerdown.pll_powerdown
+ pll_powerdown => CONNECTED_TO_pll_powerdown,
+ -- pll_select.pll_select
+ pll_select => CONNECTED_TO_pll_select,
+ -- reset.reset
+ reset => CONNECTED_TO_reset,
+ -- rx_analogreset.rx_analogreset
+ rx_analogreset => CONNECTED_TO_rx_analogreset,
+ -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy,
+ -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset,
+ -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata,
+ -- rx_ready.rx_ready
+ rx_ready => CONNECTED_TO_rx_ready,
+ -- tx_analogreset.tx_analogreset
+ tx_analogreset => CONNECTED_TO_tx_analogreset,
+ -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => CONNECTED_TO_tx_cal_busy,
+ -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => CONNECTED_TO_tx_digitalreset,
+ -- tx_ready.tx_ready
+ tx_ready => CONNECTED_TO_tx_ready
);
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd
index 5a53d30972078b5c9e7e765fcf201319dd6c4631..8d4ffcf8ca5c23ab8612dfeb91fbc35fc938f4c0 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd
@@ -36,24 +36,37 @@ entity tb_ip_arria10_e1sg_tse_sgmii_gx is
end tb_ip_arria10_e1sg_tse_sgmii_gx;
architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
- constant sys_clk_period : time := 10 ns; -- 100 MHz
- constant eth_clk_period : time := 8 ns; -- 125 MHz
- constant serial_clk_period : time := 800 ps; -- 1250 MHz ????
- constant cdr_clk_period : time := 8000 ps; -- 125 MHz ????
-
- constant c_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
+ -- 100 MHz
+ constant sys_clk_period : time := 10 ns;
+ -- 125 MHz
+ constant eth_clk_period : time := 8 ns;
+ -- 1250 MHz ????
+ constant serial_clk_period : time := 800 ps;
+ -- 125 MHz ????
+ constant cdr_clk_period : time := 8000 ps;
+
+ -- = max 256 MAC registers
+ constant c_tse_reg_addr_w : natural := 8;
constant c_tse_byte_addr_w : natural := c_tse_reg_addr_w + 2;
- constant c_tse_byte_addr_pcs_offset : natural := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
- constant c_tse_data_w : natural := c_word_w; -- = 32
-
- constant c_tse_symbol_w : natural := c_byte_w; -- = 8
- constant c_tse_symbol_max : natural := 2**c_tse_symbol_w - 1; -- = 255
- constant c_tse_symbols_per_beat : natural := c_tse_data_w / c_tse_symbol_w; -- = 4
-
- constant c_tse_pcs_reg_addr_w : natural := 5; -- = max 32 PCS registers
- constant c_tse_pcs_halfword_addr_w : natural := c_tse_pcs_reg_addr_w + 1; -- table 4.17 in ug_ethernet.pdf
+ -- table 4.8, 4.9 in ug_ethernet.pdf
+ constant c_tse_byte_addr_pcs_offset : natural := 16#200#;
+ -- = 32
+ constant c_tse_data_w : natural := c_word_w;
+
+ -- = 8
+ constant c_tse_symbol_w : natural := c_byte_w;
+ -- = 255
+ constant c_tse_symbol_max : natural := 2**c_tse_symbol_w - 1;
+ -- = 4
+ constant c_tse_symbols_per_beat : natural := c_tse_data_w / c_tse_symbol_w;
+
+ -- = max 32 PCS registers
+ constant c_tse_pcs_reg_addr_w : natural := 5;
+ -- table 4.17 in ug_ethernet.pdf
+ constant c_tse_pcs_halfword_addr_w : natural := c_tse_pcs_reg_addr_w + 1;
constant c_tse_pcs_byte_addr_w : natural := c_tse_pcs_reg_addr_w + 2;
- constant c_tse_pcs_data_w : natural := c_halfword_w; -- = 16;
+ -- = 16;
+ constant c_tse_pcs_data_w : natural := c_halfword_w;
constant c_tse_empty_w : natural := 2;
constant c_tse_tx_error_w : natural := 1;
@@ -62,18 +75,23 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
constant c_tse_err_stat_w : natural := 18;
constant c_tse_frm_type_w : natural := 4;
- constant c_tse_tx_fifo_depth : natural := 256; -- nof words for Tx FIFO
- constant c_tse_rx_fifo_depth : natural := 256; -- nof words for Rx FIFO
+ -- nof words for Tx FIFO
+ constant c_tse_tx_fifo_depth : natural := 256;
+ -- nof words for Rx FIFO
+ constant c_tse_rx_fifo_depth : natural := 256;
constant c_tse_promis_en : boolean := false;
--CONSTANT c_tse_promis_en : BOOLEAN := TRUE;
- constant c_tx_data_type : natural := 1; -- 0 = symbols, 1 = counter
+ -- 0 = symbols, 1 = counter
+ constant c_tx_data_type : natural := 1;
constant c_tx_ready_latency : natural := 0;
- constant c_nof_tx_not_valid : natural := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ constant c_nof_tx_not_valid : natural := 0;
constant c_eth_dst_mac : std_logic_vector(47 downto 0) := X"10FA01020300";
- constant c_eth_src_mac : std_logic_vector(47 downto 0) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ -- = 12-34-56-78-9A-BC
+ constant c_eth_src_mac : std_logic_vector(47 downto 0) := X"123456789ABC";
constant c_eth_ethertype : std_logic_vector(15 downto 0) := X"10FA";
type t_mm_bus is record
@@ -241,7 +259,8 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
procedure proc_tx_packet(constant dst_mac_addr : in std_logic_vector(c_eth_dst_mac'range);
constant src_mac_addr : in std_logic_vector(c_eth_src_mac'range);
constant ethertype : in std_logic_vector(c_eth_ethertype'range);
- constant data_len : in natural; -- in symbols = octets = bytes
+ -- in symbols = octets = bytes
+ constant data_len : in natural;
signal dp_clk : in std_logic;
signal dp_src_in : in t_tse_stream;
signal dp_src_out : out t_tse_stream) is
@@ -254,7 +273,8 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
-- DST MAC
dp_src_out.empty <= std_logic_vector(to_unsigned(0, c_tse_empty_w));
dp_src_out.data <= (others => '0');
- dp_src_out.data(15 downto 0) <= hton(dst_mac_addr(15 downto 0)); -- send to itself
+ -- send to itself
+ dp_src_out.data(15 downto 0) <= hton(dst_mac_addr(15 downto 0));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '1', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
dp_src_out.data <= hton(dst_mac_addr(47 downto 16));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
@@ -382,7 +402,8 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
end loop;
if c_tx_data_type = 0 then
-- data : X"01020304", X"05060708", X"090A0B0C", etc
- for J in c_tse_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
+ -- ignore CRC32 symbols in last data word
+ for J in c_tse_symbols_per_beat - 1 downto v_empty loop
v_sym := v_sym + 1;
assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
end loop;
@@ -390,7 +411,8 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
-- data : X"00000001", X"00000002", X"00000003", etc
v_num := v_num + 1;
for J in v_empty - 1 downto 0 loop
- v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
+ -- force CRC32 symbols in last data word to 0
+ v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0');
end loop;
assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
end if;
@@ -409,10 +431,13 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
-- TSE MAC control interface
signal mm_init : std_logic := '1';
- signal mm_miso : t_mm_bus; -- master in slave out
- signal mm_mosi : t_mm_bus; -- master out slave in
+ -- master in slave out
+ signal mm_miso : t_mm_bus;
+ -- master out slave in
+ signal mm_mosi : t_mm_bus;
- signal pcs_rddata : natural; -- [c_tse_pcs_data_w-1:0]
+ -- [c_tse_pcs_data_w-1:0]
+ signal pcs_rddata : natural;
signal tse_led_an : std_logic;
signal tse_led_link : std_logic;
@@ -456,8 +481,10 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
signal dbg_ff_tx : t_tse_stream;
signal dbg_ff_rx : t_tse_stream;
begin
- eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
- sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
+ -- TSE reference clock
+ eth_clk <= not eth_clk after eth_clk_period / 2;
+ -- System clock
+ sys_clk <= not sys_clk after sys_clk_period / 2;
mm_clk <= sys_clk;
dp_clk <= sys_clk;
@@ -481,14 +508,20 @@ begin
for I in 0 to 9 loop wait until rising_edge(mm_clk); end loop;
-- PSC control
- proc_rd_pcs(16#22#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> 0x0901
- proc_wr_pcs(16#28#, 16#0008#, mm_clk, mm_miso, mm_mosi); -- IF_MODE <-- Force 1GbE, no autonegatiation
- proc_rd_pcs(16#00#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- CONTROL --> 0x1140
- proc_rd_pcs(16#02#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- STATUS --> 0x000D
- proc_wr_pcs(16#00#, 16#0140#, mm_clk, mm_miso, mm_mosi); -- CONTROL <-- Auto negotiate disable
+ -- REV --> 0x0901
+ proc_rd_pcs(16#22#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- IF_MODE <-- Force 1GbE, no autonegatiation
+ proc_wr_pcs(16#28#, 16#0008#, mm_clk, mm_miso, mm_mosi);
+ -- CONTROL --> 0x1140
+ proc_rd_pcs(16#00#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- STATUS --> 0x000D
+ proc_rd_pcs(16#02#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- CONTROL <-- Auto negotiate disable
+ proc_wr_pcs(16#00#, 16#0140#, mm_clk, mm_miso, mm_mosi);
-- MAC control
- proc_rd_mac(16#000#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> CUST_VERSION & 0x0901
+ -- REV --> CUST_VERSION & 0x0901
+ proc_rd_mac(16#000#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
if c_tse_promis_en = false then
proc_wr_mac(16#008#, 16#0100004B#, mm_clk, mm_miso, mm_mosi);
else
@@ -525,10 +558,14 @@ begin
-- [ 27] = DISABLE_RD_TIMEOUT = 0
-- [30-28] = RSVD = 000
-- [ 31] = CNT_RESET = 0, when 1 clear statistics
- proc_wr_mac(16#00C#, 16#56789ABC#, mm_clk, mm_miso, mm_mosi); -- MAC_0
- proc_wr_mac(16#010#, 16#00001234#, mm_clk, mm_miso, mm_mosi); -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
- proc_wr_mac(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi); -- TX_IPG_LENGTH <-- interpacket gap = 12
- proc_wr_mac(16#014#, 16#000005EE#, mm_clk, mm_miso, mm_mosi); -- FRM_LENGTH <-- receive max frame length = 1518
+ -- MAC_0
+ proc_wr_mac(16#00C#, 16#56789ABC#, mm_clk, mm_miso, mm_mosi);
+ -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
+ proc_wr_mac(16#010#, 16#00001234#, mm_clk, mm_miso, mm_mosi);
+ -- TX_IPG_LENGTH <-- interpacket gap = 12
+ proc_wr_mac(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi);
+ -- FRM_LENGTH <-- receive max frame length = 1518
+ proc_wr_mac(16#014#, 16#000005EE#, mm_clk, mm_miso, mm_mosi);
-- FIFO legenda:
-- . Tx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
@@ -550,17 +587,27 @@ begin
-- . c_tse_tx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Tx user respects ff_tx_rdy, to store a complete
-- ETH packet would require 1518 byte, so 2 M9K = 2k * 8b
-- . c_tse_rx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Rx user ff_rx_rdy is sufficiently active
- proc_wr_mac(16#01C#, c_tse_rx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
- proc_wr_mac(16#020#, 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_FULL <-- default 16
- proc_wr_mac(16#024#, c_tse_tx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
- proc_wr_mac(16#028#, 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
- proc_wr_mac(16#02C#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_EMPTY <-- default 8
- proc_wr_mac(16#030#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_FULL <-- default 8
- proc_wr_mac(16#034#, 8, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_EMPTY <-- default 8
- proc_wr_mac(16#038#, c_tx_ready_latency + 3, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_FULL <-- default 3
-
- proc_rd_mac(16#0E8#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
- proc_rd_mac(16#0EC#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+ -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#01C#, c_tse_rx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi);
+ -- RX_SECTION_FULL <-- default 16
+ proc_wr_mac(16#020#, 16, mm_clk, mm_miso, mm_mosi);
+ -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#024#, c_tse_tx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi);
+ -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
+ proc_wr_mac(16#028#, 16, mm_clk, mm_miso, mm_mosi);
+ -- RX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#02C#, 8, mm_clk, mm_miso, mm_mosi);
+ -- RX_ALMOST_FULL <-- default 8
+ proc_wr_mac(16#030#, 8, mm_clk, mm_miso, mm_mosi);
+ -- TX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#034#, 8, mm_clk, mm_miso, mm_mosi);
+ -- TX_ALMOST_FULL <-- default 3
+ proc_wr_mac(16#038#, c_tx_ready_latency + 3, mm_clk, mm_miso, mm_mosi);
+
+ -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
+ proc_rd_mac(16#0E8#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+ proc_rd_mac(16#0EC#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
wait until rising_edge(mm_clk);
mm_init <= '0';
@@ -592,7 +639,8 @@ begin
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1499, dp_clk, ff_tx_src_in, ff_tx_src_out); -- verify st empty
+ -- verify st empty
+ proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1499, dp_clk, ff_tx_src_in, ff_tx_src_out);
proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
@@ -637,30 +685,51 @@ begin
port map (
-- MAC transmit interface
-- . Avalon ST
- ff_tx_clk => dp_clk, -- : in std_logic := '0'; -- transmit_clock_connection.clk
- ff_tx_rdy => ff_tx_src_in.ready, -- : out std_logic; -- .ready
- ff_tx_data => ff_tx_src_out.data, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
- ff_tx_wren => ff_tx_src_out.valid, -- : in std_logic := '0'; -- .valid
- ff_tx_sop => ff_tx_src_out.sop, -- : in std_logic := '0'; -- .startofpacket
- ff_tx_eop => ff_tx_src_out.eop, -- : in std_logic := '0'; -- .endofpacket
- ff_tx_mod => ff_tx_src_out.empty, -- : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
- ff_tx_err => ff_tx_src_out.err(0), -- : in std_logic := '0'; -- .error
+ -- : in std_logic := '0'; -- transmit_clock_connection.clk
+ ff_tx_clk => dp_clk,
+ -- : out std_logic; -- .ready
+ ff_tx_rdy => ff_tx_src_in.ready,
+ -- : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_data => ff_tx_src_out.data,
+ -- : in std_logic := '0'; -- .valid
+ ff_tx_wren => ff_tx_src_out.valid,
+ -- : in std_logic := '0'; -- .startofpacket
+ ff_tx_sop => ff_tx_src_out.sop,
+ -- : in std_logic := '0'; -- .endofpacket
+ ff_tx_eop => ff_tx_src_out.eop,
+ -- : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_mod => ff_tx_src_out.empty,
+ -- : in std_logic := '0'; -- .error
+ ff_tx_err => ff_tx_src_out.err(0),
-- . MAC specific
- ff_tx_crc_fwd => ff_tx_crc_fwd, -- : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd -- when '0' MAC inserts CRC32 after eop
- ff_tx_septy => ff_tx_septy, -- : out std_logic; -- .ff_tx_septy -- when '0' then tx FIFO goes above section-empty threshold
- ff_tx_a_full => ff_tx_a_full, -- : out std_logic; -- .ff_tx_a_full -- when '1' then tx FIFO goes above almost-full threshold
- ff_tx_a_empty => ff_tx_a_empty, -- : out std_logic; -- .ff_tx_a_empty -- when '1' then tx FIFO goes below almost-empty threshold
- tx_ff_uflow => ff_tx_uflow, -- : out std_logic; -- .tx_ff_uflow -- when '1' then tx FIFO underflow
+ -- : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd -- when '0' MAC inserts CRC32 after eop
+ ff_tx_crc_fwd => ff_tx_crc_fwd,
+ -- : out std_logic; -- .ff_tx_septy -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_septy => ff_tx_septy,
+ -- : out std_logic; -- .ff_tx_a_full -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_full => ff_tx_a_full,
+ -- : out std_logic; -- .ff_tx_a_empty -- when '1' then tx FIFO goes below almost-empty threshold
+ ff_tx_a_empty => ff_tx_a_empty,
+ -- : out std_logic; -- .tx_ff_uflow -- when '1' then tx FIFO underflow
+ tx_ff_uflow => ff_tx_uflow,
-- MAC receive interface
-- . Avalon STs
- ff_rx_clk => dp_clk, -- : in std_logic := '0'; -- receive_clock_connection.clk
- ff_rx_rdy => ff_rx_snk_out.ready, -- : in std_logic := '0'; -- .ready
- ff_rx_data => ff_rx_snk_in.data, -- : out std_logic_vector(31 downto 0); -- receive.data
- ff_rx_dval => ff_rx_snk_in.valid, -- : out std_logic; -- .valid
- ff_rx_sop => ff_rx_snk_in.sop, -- : out std_logic; -- .startofpacket
- ff_rx_eop => ff_rx_snk_in.eop, -- : out std_logic; -- .endofpacket
- ff_rx_mod => ff_rx_snk_in.empty, -- : out std_logic_vector(1 downto 0); -- .empty
- rx_err => ff_rx_snk_in.err, -- : out std_logic_vector(5 downto 0); -- .error
+ -- : in std_logic := '0'; -- receive_clock_connection.clk
+ ff_rx_clk => dp_clk,
+ -- : in std_logic := '0'; -- .ready
+ ff_rx_rdy => ff_rx_snk_out.ready,
+ -- : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_data => ff_rx_snk_in.data,
+ -- : out std_logic; -- .valid
+ ff_rx_dval => ff_rx_snk_in.valid,
+ -- : out std_logic; -- .startofpacket
+ ff_rx_sop => ff_rx_snk_in.sop,
+ -- : out std_logic; -- .endofpacket
+ ff_rx_eop => ff_rx_snk_in.eop,
+ -- : out std_logic_vector(1 downto 0); -- .empty
+ ff_rx_mod => ff_rx_snk_in.empty,
+ -- : out std_logic_vector(5 downto 0); -- .error
+ rx_err => ff_rx_snk_in.err,
-- [5] collision error (can only occur in half duplex mode)
-- [4] PHY error on GMII
-- [3] receive frame truncated due to FIFO overflow
@@ -668,51 +737,88 @@ begin
-- [1] invalid length
-- [0] = OR of [1:5]
-- . MAC specific
- rx_err_stat => ff_rx_ethertype, -- : out std_logic_vector(17 downto 0); -- .rx_err_stat -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
- rx_frm_type => ff_rx_frm_type, -- : out std_logic_vector(3 downto 0); -- .rx_frm_type -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
- ff_rx_dsav => ff_rx_dsav, -- : out std_logic; -- .ff_rx_dsav -- rx frame available, but not necessarily a complete frame
- ff_rx_a_full => ff_rx_a_full, -- : out std_logic; -- .ff_rx_a_full -- when '1' then rx FIFO goes above almost-full threshold
- ff_rx_a_empty => ff_rx_a_empty, -- : out std_logic; -- .ff_rx_a_empty -- when '1' sthen rx FIFO goes below almost-empty threshold
+ -- : out std_logic_vector(17 downto 0); -- .rx_err_stat -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_err_stat => ff_rx_ethertype,
+ -- : out std_logic_vector(3 downto 0); -- .rx_frm_type -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ rx_frm_type => ff_rx_frm_type,
+ -- : out std_logic; -- .ff_rx_dsav -- rx frame available, but not necessarily a complete frame
+ ff_rx_dsav => ff_rx_dsav,
+ -- : out std_logic; -- .ff_rx_a_full -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_full => ff_rx_a_full,
+ -- : out std_logic; -- .ff_rx_a_empty -- when '1' sthen rx FIFO goes below almost-empty threshold
+ ff_rx_a_empty => ff_rx_a_empty,
-- Reset
- reset => mm_rst, -- : in std_logic := '0'; -- reset_connection.reset -- asynchronous reset (choose synchronous to mm_clk)
+ -- : in std_logic := '0'; -- reset_connection.reset -- asynchronous reset (choose synchronous to mm_clk)
+ reset => mm_rst,
-- MM control interface
- clk => mm_clk, -- : in std_logic := '0'; -- control_port_clock_connection.clk
- reg_addr => mm_mosi.address(c_tse_byte_addr_w - 1 downto 2), -- : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
- reg_data_out => mm_miso.rddata, -- : out std_logic_vector(31 downto 0); -- control_port.readdata
- reg_rd => mm_mosi.rd, -- : in std_logic := '0'; -- .read
- reg_data_in => mm_mosi.wrdata, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reg_wr => mm_mosi.wr, -- : in std_logic := '0'; -- .write
- reg_busy => mm_miso.waitreq, -- : out std_logic; -- .waitrequest
+ -- : in std_logic := '0'; -- control_port_clock_connection.clk
+ clk => mm_clk,
+ -- : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ reg_addr => mm_mosi.address(c_tse_byte_addr_w - 1 downto 2),
+ -- : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_data_out => mm_miso.rddata,
+ -- : in std_logic := '0'; -- .read
+ reg_rd => mm_mosi.rd,
+ -- : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_data_in => mm_mosi.wrdata,
+ -- : in std_logic := '0'; -- .write
+ reg_wr => mm_mosi.wr,
+ -- : out std_logic; -- .waitrequest
+ reg_busy => mm_miso.waitreq,
-- Status LEDs
- led_an => tse_led_an, -- : out std_logic; -- .an -- '1' = autonegation completed
- led_link => tse_led_link, -- : out std_logic; -- .link -- '1' = successful link synchronisation
- led_disp_err => OPEN, -- : out std_logic; -- .disp_err -- TBI character error
- led_char_err => OPEN, -- : out std_logic; -- .char_err -- TBI disparity errorreceived
- led_crs => OPEN, -- : out std_logic; -- status_led_connection.crs
- led_col => OPEN, -- : out std_logic; -- .col
+ -- : out std_logic; -- .an -- '1' = autonegation completed
+ led_an => tse_led_an,
+ -- : out std_logic; -- .link -- '1' = successful link synchronisation
+ led_link => tse_led_link,
+ -- : out std_logic; -- .disp_err -- TBI character error
+ led_disp_err => OPEN,
+ -- : out std_logic; -- .char_err -- TBI disparity errorreceived
+ led_char_err => OPEN,
+ -- : out std_logic; -- status_led_connection.crs
+ led_crs => OPEN,
+ -- : out std_logic; -- .col
+ led_col => OPEN,
-- Serial 1.25 Gbps
- rx_recovclkout => OPEN, -- : out std_logic; -- serdes_control_connection.export
- ref_clk => eth_clk, -- : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
- txp => eth_txp, -- : out std_logic -- .txp_0
- rxp => eth_rxp, -- : in std_logic := '0'; -- serial_connection.rxp_0
-
- tx_serial_clk => tx_serial_clk, -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk.clk
- rx_cdr_refclk => rx_cdr_refclk, -- : in std_logic := '0'; -- rx_cdr_refclk.clk
- tx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- rx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- tx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
- rx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_set_locktodata => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
- rx_set_locktoref => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
- rx_is_lockedtoref => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_is_lockedtodata => open -- : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
+ -- : out std_logic; -- serdes_control_connection.export
+ rx_recovclkout => OPEN,
+ -- : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ ref_clk => eth_clk,
+ -- : out std_logic -- .txp_0
+ txp => eth_txp,
+ -- : in std_logic := '0'; -- serial_connection.rxp_0
+ rxp => eth_rxp,
+
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk.clk
+ tx_serial_clk => tx_serial_clk,
+ -- : in std_logic := '0'; -- rx_cdr_refclk.clk
+ rx_cdr_refclk => rx_cdr_refclk,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_analogreset => (others => '0'),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_digitalreset => (others => '0'),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_analogreset => (others => '0'),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_digitalreset => (others => '0'),
+ -- : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_cal_busy => OPEN,
+ -- : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cal_busy => OPEN,
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
+ rx_set_locktodata => (others => '0'),
+ -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
+ rx_set_locktoref => (others => '0'),
+ -- : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtoref => OPEN,
+ -- : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtodata => open
);
-- To be corrected
- tx_serial_clk(0) <= not tx_serial_clk(0) after serial_clk_period / 2; -- ????
- rx_cdr_refclk <= not rx_cdr_refclk after cdr_clk_period / 2; -- ????
+ -- ????
+ tx_serial_clk(0) <= not tx_serial_clk(0) after serial_clk_period / 2;
+ -- ????
+ rx_cdr_refclk <= not rx_cdr_refclk after cdr_clk_period / 2;
-- Loopback
eth_rxp <= eth_txp;
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd
index 1fcf8f332f9d5ddeff782899d653acf38d1e976d..c6c2a984090516a19c5826958b0e7bccd568375a 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd
@@ -41,22 +41,33 @@ entity tb_ip_arria10_e1sg_tse_sgmii_lvds is
end tb_ip_arria10_e1sg_tse_sgmii_lvds;
architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
- constant sys_clk_period : time := 10 ns; -- 100 MHz
- constant eth_clk_period : time := 8 ns; -- 125 MHz
+ -- 100 MHz
+ constant sys_clk_period : time := 10 ns;
+ -- 125 MHz
+ constant eth_clk_period : time := 8 ns;
- constant c_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
+ -- = max 256 MAC registers
+ constant c_tse_reg_addr_w : natural := 8;
constant c_tse_byte_addr_w : natural := c_tse_reg_addr_w + 2;
- constant c_tse_byte_addr_pcs_offset : natural := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
- constant c_tse_data_w : natural := c_word_w; -- = 32
-
- constant c_tse_symbol_w : natural := c_byte_w; -- = 8
- constant c_tse_symbol_max : natural := 2**c_tse_symbol_w - 1; -- = 255
- constant c_tse_symbols_per_beat : natural := c_tse_data_w / c_tse_symbol_w; -- = 4
-
- constant c_tse_pcs_reg_addr_w : natural := 5; -- = max 32 PCS registers
- constant c_tse_pcs_halfword_addr_w : natural := c_tse_pcs_reg_addr_w + 1; -- table 4.17 in ug_ethernet.pdf
+ -- table 4.8, 4.9 in ug_ethernet.pdf
+ constant c_tse_byte_addr_pcs_offset : natural := 16#200#;
+ -- = 32
+ constant c_tse_data_w : natural := c_word_w;
+
+ -- = 8
+ constant c_tse_symbol_w : natural := c_byte_w;
+ -- = 255
+ constant c_tse_symbol_max : natural := 2**c_tse_symbol_w - 1;
+ -- = 4
+ constant c_tse_symbols_per_beat : natural := c_tse_data_w / c_tse_symbol_w;
+
+ -- = max 32 PCS registers
+ constant c_tse_pcs_reg_addr_w : natural := 5;
+ -- table 4.17 in ug_ethernet.pdf
+ constant c_tse_pcs_halfword_addr_w : natural := c_tse_pcs_reg_addr_w + 1;
constant c_tse_pcs_byte_addr_w : natural := c_tse_pcs_reg_addr_w + 2;
- constant c_tse_pcs_data_w : natural := c_halfword_w; -- = 16;
+ -- = 16;
+ constant c_tse_pcs_data_w : natural := c_halfword_w;
constant c_tse_empty_w : natural := 2;
constant c_tse_tx_error_w : natural := 1;
@@ -65,18 +76,23 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
constant c_tse_err_stat_w : natural := 18;
constant c_tse_frm_type_w : natural := 4;
- constant c_tse_tx_fifo_depth : natural := 256; -- nof words for Tx FIFO
- constant c_tse_rx_fifo_depth : natural := 256; -- nof words for Rx FIFO
+ -- nof words for Tx FIFO
+ constant c_tse_tx_fifo_depth : natural := 256;
+ -- nof words for Rx FIFO
+ constant c_tse_rx_fifo_depth : natural := 256;
constant c_tse_promis_en : boolean := false;
--CONSTANT c_tse_promis_en : BOOLEAN := TRUE;
- constant c_tx_data_type : natural := 1; -- 0 = symbols, 1 = counter
+ -- 0 = symbols, 1 = counter
+ constant c_tx_data_type : natural := 1;
constant c_tx_ready_latency : natural := 0;
- constant c_nof_tx_not_valid : natural := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+ constant c_nof_tx_not_valid : natural := 0;
constant c_eth_dst_mac : std_logic_vector(47 downto 0) := X"10FA01020300";
- constant c_eth_src_mac : std_logic_vector(47 downto 0) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ -- = 12-34-56-78-9A-BC
+ constant c_eth_src_mac : std_logic_vector(47 downto 0) := X"123456789ABC";
constant c_eth_ethertype : std_logic_vector(15 downto 0) := X"10FA";
type t_mm_bus is record
@@ -244,7 +260,8 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
procedure proc_tx_packet(constant dst_mac_addr : in std_logic_vector(c_eth_dst_mac'range);
constant src_mac_addr : in std_logic_vector(c_eth_src_mac'range);
constant ethertype : in std_logic_vector(c_eth_ethertype'range);
- constant data_len : in natural; -- in symbols = octets = bytes
+ -- in symbols = octets = bytes
+ constant data_len : in natural;
signal dp_clk : in std_logic;
signal dp_src_in : in t_tse_stream;
signal dp_src_out : out t_tse_stream) is
@@ -257,7 +274,8 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
-- DST MAC
dp_src_out.empty <= std_logic_vector(to_unsigned(0, c_tse_empty_w));
dp_src_out.data <= (others => '0');
- dp_src_out.data(15 downto 0) <= hton(dst_mac_addr(15 downto 0)); -- send to itself
+ -- send to itself
+ dp_src_out.data(15 downto 0) <= hton(dst_mac_addr(15 downto 0));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '1', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
dp_src_out.data <= hton(dst_mac_addr(47 downto 16));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
@@ -385,7 +403,8 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
end loop;
if c_tx_data_type = 0 then
-- data : X"01020304", X"05060708", X"090A0B0C", etc
- for J in c_tse_symbols_per_beat - 1 downto v_empty loop -- ignore CRC32 symbols in last data word
+ -- ignore CRC32 symbols in last data word
+ for J in c_tse_symbols_per_beat - 1 downto v_empty loop
v_sym := v_sym + 1;
assert unsigned(v_prev_data((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w)) = v_sym report "RX: Wrong empty data symbol" severity ERROR;
end loop;
@@ -393,7 +412,8 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
-- data : X"00000001", X"00000002", X"00000003", etc
v_num := v_num + 1;
for J in v_empty - 1 downto 0 loop
- v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0'); -- force CRC32 symbols in last data word to 0
+ -- force CRC32 symbols in last data word to 0
+ v_num((J + 1) * c_tse_symbol_w - 1 downto J * c_tse_symbol_w) := (others => '0');
end loop;
assert unsigned(v_prev_data) = v_num report "RX: Wrong empty data word" severity ERROR;
end if;
@@ -412,10 +432,13 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
-- TSE MAC control interface
signal mm_init : std_logic := '1';
- signal mm_miso : t_mm_bus; -- master in slave out
- signal mm_mosi : t_mm_bus; -- master out slave in
+ -- master in slave out
+ signal mm_miso : t_mm_bus;
+ -- master out slave in
+ signal mm_mosi : t_mm_bus;
- signal pcs_rddata : natural; -- [c_tse_pcs_data_w-1:0]
+ -- [c_tse_pcs_data_w-1:0]
+ signal pcs_rddata : natural;
signal tse_led_an : std_logic;
signal tse_led_link : std_logic;
@@ -455,8 +478,10 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
signal dbg_ff_tx : t_tse_stream;
signal dbg_ff_rx : t_tse_stream;
begin
- eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
- sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
+ -- TSE reference clock
+ eth_clk <= not eth_clk after eth_clk_period / 2;
+ -- System clock
+ sys_clk <= not sys_clk after sys_clk_period / 2;
mm_clk <= sys_clk;
dp_clk <= sys_clk;
@@ -480,14 +505,20 @@ begin
for I in 0 to 9 loop wait until rising_edge(mm_clk); end loop;
-- PSC control
- proc_rd_pcs(16#22#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> 0x0901
- proc_wr_pcs(16#28#, 16#0008#, mm_clk, mm_miso, mm_mosi); -- IF_MODE <-- Force 1GbE, no autonegatiation
- proc_rd_pcs(16#00#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- CONTROL --> 0x1140
- proc_rd_pcs(16#02#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- STATUS --> 0x000D
- proc_wr_pcs(16#00#, 16#0140#, mm_clk, mm_miso, mm_mosi); -- CONTROL <-- Auto negotiate disable
+ -- REV --> 0x0901
+ proc_rd_pcs(16#22#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- IF_MODE <-- Force 1GbE, no autonegatiation
+ proc_wr_pcs(16#28#, 16#0008#, mm_clk, mm_miso, mm_mosi);
+ -- CONTROL --> 0x1140
+ proc_rd_pcs(16#00#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- STATUS --> 0x000D
+ proc_rd_pcs(16#02#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- CONTROL <-- Auto negotiate disable
+ proc_wr_pcs(16#00#, 16#0140#, mm_clk, mm_miso, mm_mosi);
-- MAC control
- proc_rd_mac(16#000#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> CUST_VERSION & 0x0901
+ -- REV --> CUST_VERSION & 0x0901
+ proc_rd_mac(16#000#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
if c_tse_promis_en = false then
proc_wr_mac(16#008#, 16#0100004B#, mm_clk, mm_miso, mm_mosi);
else
@@ -524,10 +555,14 @@ begin
-- [ 27] = DISABLE_RD_TIMEOUT = 0
-- [30-28] = RSVD = 000
-- [ 31] = CNT_RESET = 0, when 1 clear statistics
- proc_wr_mac(16#00C#, 16#56789ABC#, mm_clk, mm_miso, mm_mosi); -- MAC_0
- proc_wr_mac(16#010#, 16#00001234#, mm_clk, mm_miso, mm_mosi); -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
- proc_wr_mac(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi); -- TX_IPG_LENGTH <-- interpacket gap = 12
- proc_wr_mac(16#014#, 16#000005EE#, mm_clk, mm_miso, mm_mosi); -- FRM_LENGTH <-- receive max frame length = 1518
+ -- MAC_0
+ proc_wr_mac(16#00C#, 16#56789ABC#, mm_clk, mm_miso, mm_mosi);
+ -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
+ proc_wr_mac(16#010#, 16#00001234#, mm_clk, mm_miso, mm_mosi);
+ -- TX_IPG_LENGTH <-- interpacket gap = 12
+ proc_wr_mac(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi);
+ -- FRM_LENGTH <-- receive max frame length = 1518
+ proc_wr_mac(16#014#, 16#000005EE#, mm_clk, mm_miso, mm_mosi);
-- FIFO legenda:
-- . Tx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
@@ -549,17 +584,27 @@ begin
-- . c_tse_tx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Tx user respects ff_tx_rdy, to store a complete
-- ETH packet would require 1518 byte, so 2 M9K = 2k * 8b
-- . c_tse_rx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Rx user ff_rx_rdy is sufficiently active
- proc_wr_mac(16#01C#, c_tse_rx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
- proc_wr_mac(16#020#, 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_FULL <-- default 16
- proc_wr_mac(16#024#, c_tse_tx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
- proc_wr_mac(16#028#, 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
- proc_wr_mac(16#02C#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_EMPTY <-- default 8
- proc_wr_mac(16#030#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_FULL <-- default 8
- proc_wr_mac(16#034#, 8, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_EMPTY <-- default 8
- proc_wr_mac(16#038#, c_tx_ready_latency + 3, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_FULL <-- default 3
-
- proc_rd_mac(16#0E8#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
- proc_rd_mac(16#0EC#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+ -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#01C#, c_tse_rx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi);
+ -- RX_SECTION_FULL <-- default 16
+ proc_wr_mac(16#020#, 16, mm_clk, mm_miso, mm_mosi);
+ -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#024#, c_tse_tx_fifo_depth - 16, mm_clk, mm_miso, mm_mosi);
+ -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
+ proc_wr_mac(16#028#, 16, mm_clk, mm_miso, mm_mosi);
+ -- RX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#02C#, 8, mm_clk, mm_miso, mm_mosi);
+ -- RX_ALMOST_FULL <-- default 8
+ proc_wr_mac(16#030#, 8, mm_clk, mm_miso, mm_mosi);
+ -- TX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#034#, 8, mm_clk, mm_miso, mm_mosi);
+ -- TX_ALMOST_FULL <-- default 3
+ proc_wr_mac(16#038#, c_tx_ready_latency + 3, mm_clk, mm_miso, mm_mosi);
+
+ -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
+ proc_rd_mac(16#0E8#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
+ -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+ proc_rd_mac(16#0EC#, pcs_rddata, mm_clk, mm_miso, mm_mosi);
wait until rising_edge(mm_clk);
mm_init <= '0';
@@ -591,7 +636,8 @@ begin
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1499, dp_clk, ff_tx_src_in, ff_tx_src_out); -- verify st empty
+ -- verify st empty
+ proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1499, dp_clk, ff_tx_src_in, ff_tx_src_out);
proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
@@ -636,30 +682,51 @@ begin
port map (
-- MAC transmit interface
-- . Avalon ST
- ff_tx_clk => dp_clk, -- : in std_logic := '0'; -- transmit_clock_connection.clk
- ff_tx_rdy => ff_tx_src_in.ready, -- : out std_logic; -- .ready
- ff_tx_data => ff_tx_src_out.data, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
- ff_tx_wren => ff_tx_src_out.valid, -- : in std_logic := '0'; -- .valid
- ff_tx_sop => ff_tx_src_out.sop, -- : in std_logic := '0'; -- .startofpacket
- ff_tx_eop => ff_tx_src_out.eop, -- : in std_logic := '0'; -- .endofpacket
- ff_tx_mod => ff_tx_src_out.empty, -- : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
- ff_tx_err => ff_tx_src_out.err(0), -- : in std_logic := '0'; -- .error
+ -- : in std_logic := '0'; -- transmit_clock_connection.clk
+ ff_tx_clk => dp_clk,
+ -- : out std_logic; -- .ready
+ ff_tx_rdy => ff_tx_src_in.ready,
+ -- : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_data => ff_tx_src_out.data,
+ -- : in std_logic := '0'; -- .valid
+ ff_tx_wren => ff_tx_src_out.valid,
+ -- : in std_logic := '0'; -- .startofpacket
+ ff_tx_sop => ff_tx_src_out.sop,
+ -- : in std_logic := '0'; -- .endofpacket
+ ff_tx_eop => ff_tx_src_out.eop,
+ -- : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_mod => ff_tx_src_out.empty,
+ -- : in std_logic := '0'; -- .error
+ ff_tx_err => ff_tx_src_out.err(0),
-- . MAC specific
- ff_tx_crc_fwd => ff_tx_crc_fwd, -- : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd -- when '0' MAC inserts CRC32 after eop
- ff_tx_septy => ff_tx_septy, -- : out std_logic; -- .ff_tx_septy -- when '0' then tx FIFO goes above section-empty threshold
- ff_tx_a_full => ff_tx_a_full, -- : out std_logic; -- .ff_tx_a_full -- when '1' then tx FIFO goes above almost-full threshold
- ff_tx_a_empty => ff_tx_a_empty, -- : out std_logic; -- .ff_tx_a_empty -- when '1' then tx FIFO goes below almost-empty threshold
- tx_ff_uflow => ff_tx_uflow, -- : out std_logic; -- .tx_ff_uflow -- when '1' then tx FIFO underflow
+ -- : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd -- when '0' MAC inserts CRC32 after eop
+ ff_tx_crc_fwd => ff_tx_crc_fwd,
+ -- : out std_logic; -- .ff_tx_septy -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_septy => ff_tx_septy,
+ -- : out std_logic; -- .ff_tx_a_full -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_full => ff_tx_a_full,
+ -- : out std_logic; -- .ff_tx_a_empty -- when '1' then tx FIFO goes below almost-empty threshold
+ ff_tx_a_empty => ff_tx_a_empty,
+ -- : out std_logic; -- .tx_ff_uflow -- when '1' then tx FIFO underflow
+ tx_ff_uflow => ff_tx_uflow,
-- MAC receive interface
-- . Avalon STs
- ff_rx_clk => dp_clk, -- : in std_logic := '0'; -- receive_clock_connection.clk
- ff_rx_rdy => ff_rx_snk_out.ready, -- : in std_logic := '0'; -- .ready
- ff_rx_data => ff_rx_snk_in.data, -- : out std_logic_vector(31 downto 0); -- receive.data
- ff_rx_dval => ff_rx_snk_in.valid, -- : out std_logic; -- .valid
- ff_rx_sop => ff_rx_snk_in.sop, -- : out std_logic; -- .startofpacket
- ff_rx_eop => ff_rx_snk_in.eop, -- : out std_logic; -- .endofpacket
- ff_rx_mod => ff_rx_snk_in.empty, -- : out std_logic_vector(1 downto 0); -- .empty
- rx_err => ff_rx_snk_in.err, -- : out std_logic_vector(5 downto 0); -- .error
+ -- : in std_logic := '0'; -- receive_clock_connection.clk
+ ff_rx_clk => dp_clk,
+ -- : in std_logic := '0'; -- .ready
+ ff_rx_rdy => ff_rx_snk_out.ready,
+ -- : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_data => ff_rx_snk_in.data,
+ -- : out std_logic; -- .valid
+ ff_rx_dval => ff_rx_snk_in.valid,
+ -- : out std_logic; -- .startofpacket
+ ff_rx_sop => ff_rx_snk_in.sop,
+ -- : out std_logic; -- .endofpacket
+ ff_rx_eop => ff_rx_snk_in.eop,
+ -- : out std_logic_vector(1 downto 0); -- .empty
+ ff_rx_mod => ff_rx_snk_in.empty,
+ -- : out std_logic_vector(5 downto 0); -- .error
+ rx_err => ff_rx_snk_in.err,
-- [5] collision error (can only occur in half duplex mode)
-- [4] PHY error on GMII
-- [3] receive frame truncated due to FIFO overflow
@@ -667,33 +734,56 @@ begin
-- [1] invalid length
-- [0] = OR of [1:5]
-- . MAC specific
- rx_err_stat => ff_rx_ethertype, -- : out std_logic_vector(17 downto 0); -- .rx_err_stat -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
- rx_frm_type => ff_rx_frm_type, -- : out std_logic_vector(3 downto 0); -- .rx_frm_type -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
- ff_rx_dsav => ff_rx_dsav, -- : out std_logic; -- .ff_rx_dsav -- rx frame available, but not necessarily a complete frame
- ff_rx_a_full => ff_rx_a_full, -- : out std_logic; -- .ff_rx_a_full -- when '1' then rx FIFO goes above almost-full threshold
- ff_rx_a_empty => ff_rx_a_empty, -- : out std_logic; -- .ff_rx_a_empty -- when '1' sthen rx FIFO goes below almost-empty threshold
+ -- : out std_logic_vector(17 downto 0); -- .rx_err_stat -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_err_stat => ff_rx_ethertype,
+ -- : out std_logic_vector(3 downto 0); -- .rx_frm_type -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ rx_frm_type => ff_rx_frm_type,
+ -- : out std_logic; -- .ff_rx_dsav -- rx frame available, but not necessarily a complete frame
+ ff_rx_dsav => ff_rx_dsav,
+ -- : out std_logic; -- .ff_rx_a_full -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_full => ff_rx_a_full,
+ -- : out std_logic; -- .ff_rx_a_empty -- when '1' sthen rx FIFO goes below almost-empty threshold
+ ff_rx_a_empty => ff_rx_a_empty,
-- Reset
- reset => mm_rst, -- : in std_logic := '0'; -- reset_connection.reset -- asynchronous reset (choose synchronous to mm_clk)
+ -- : in std_logic := '0'; -- reset_connection.reset -- asynchronous reset (choose synchronous to mm_clk)
+ reset => mm_rst,
-- MM control interface
- clk => mm_clk, -- : in std_logic := '0'; -- control_port_clock_connection.clk
- reg_addr => mm_mosi.address(c_tse_byte_addr_w - 1 downto 2), -- : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
- reg_data_out => mm_miso.rddata, -- : out std_logic_vector(31 downto 0); -- control_port.readdata
- reg_rd => mm_mosi.rd, -- : in std_logic := '0'; -- .read
- reg_data_in => mm_mosi.wrdata, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- reg_wr => mm_mosi.wr, -- : in std_logic := '0'; -- .write
- reg_busy => mm_miso.waitreq, -- : out std_logic; -- .waitrequest
+ -- : in std_logic := '0'; -- control_port_clock_connection.clk
+ clk => mm_clk,
+ -- : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ reg_addr => mm_mosi.address(c_tse_byte_addr_w - 1 downto 2),
+ -- : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_data_out => mm_miso.rddata,
+ -- : in std_logic := '0'; -- .read
+ reg_rd => mm_mosi.rd,
+ -- : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_data_in => mm_mosi.wrdata,
+ -- : in std_logic := '0'; -- .write
+ reg_wr => mm_mosi.wr,
+ -- : out std_logic; -- .waitrequest
+ reg_busy => mm_miso.waitreq,
-- Status LEDs
- led_an => tse_led_an, -- : out std_logic; -- .an -- '1' = autonegation completed
- led_link => tse_led_link, -- : out std_logic; -- .link -- '1' = successful link synchronisation
- led_disp_err => OPEN, -- : out std_logic; -- .disp_err -- TBI character error
- led_char_err => OPEN, -- : out std_logic; -- .char_err -- TBI disparity errorreceived
- led_crs => OPEN, -- : out std_logic; -- status_led_connection.crs
- led_col => OPEN, -- : out std_logic; -- .col
+ -- : out std_logic; -- .an -- '1' = autonegation completed
+ led_an => tse_led_an,
+ -- : out std_logic; -- .link -- '1' = successful link synchronisation
+ led_link => tse_led_link,
+ -- : out std_logic; -- .disp_err -- TBI character error
+ led_disp_err => OPEN,
+ -- : out std_logic; -- .char_err -- TBI disparity errorreceived
+ led_char_err => OPEN,
+ -- : out std_logic; -- status_led_connection.crs
+ led_crs => OPEN,
+ -- : out std_logic; -- .col
+ led_col => OPEN,
-- Serial 1.25 Gbps
- rx_recovclkout => OPEN, -- : out std_logic; -- serdes_control_connection.export
- ref_clk => eth_clk, -- : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
- txp => eth_txp, -- : out std_logic -- .txp_0
- rxp => eth_rxp -- : in std_logic := '0'; -- serial_connection.rxp_0
+ -- : out std_logic; -- serdes_control_connection.export
+ rx_recovclkout => OPEN,
+ -- : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ ref_clk => eth_clk,
+ -- : out std_logic -- .txp_0
+ txp => eth_txp,
+ -- : in std_logic := '0'; -- serial_connection.rxp_0
+ rxp => eth_rxp
);
-- Loopback
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd
index e5221f4af8d1f1a4de5c5f9dd520ad10a5b50ebf..df5adc9ddb36f4c8f8946a47249b213a020944a1 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd
@@ -31,7 +31,8 @@ entity ip_arria10_e2sg_ddio_in is
port (
in_dat : in std_logic_vector(g_width - 1 downto 0);
in_clk : in std_logic;
- in_clk_en : in std_logic := '1'; -- Not Connected
+ -- Not Connected
+ in_clk_en : in std_logic := '1';
rst : in std_logic := '0';
out_dat_hi : out std_logic_vector(g_width - 1 downto 0);
out_dat_lo : out std_logic_vector(g_width - 1 downto 0)
@@ -41,11 +42,16 @@ end ip_arria10_e2sg_ddio_in;
architecture str of ip_arria10_e2sg_ddio_in is
component ip_arria10_e2sg_ddio_in_1 is
port (
- datain : in std_logic_vector(0 downto 0) := (others => '0'); -- pad_in.export
- ck : in std_logic := '0'; -- ck.export
- aclr : in std_logic := '0'; -- aclr.export
- dataout_h : out std_logic_vector(0 downto 0); -- dataout_h.fragment
- dataout_l : out std_logic_vector(0 downto 0) -- dataout_l.fragment
+ -- pad_in.export
+ datain : in std_logic_vector(0 downto 0) := (others => '0');
+ -- ck.export
+ ck : in std_logic := '0';
+ -- aclr.export
+ aclr : in std_logic := '0';
+ -- dataout_h.fragment
+ dataout_h : out std_logic_vector(0 downto 0);
+ -- dataout_l.fragment
+ dataout_l : out std_logic_vector(0 downto 0)
);
end component;
begin
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out.vhd b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out.vhd
index 6fcc0779f8b6de6735a491fd3990500c4f82ca38..0d5970b647e3c820c016c063db505023e9bddb8c 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out.vhd
@@ -31,7 +31,8 @@ entity ip_arria10_e2sg_ddio_out is
port (
rst : in std_logic := '0';
in_clk : in std_logic;
- in_clk_en : in std_logic := '1'; -- Not Connected
+ -- Not Connected
+ in_clk_en : in std_logic := '1';
in_dat_hi : in std_logic_vector(g_width - 1 downto 0);
in_dat_lo : in std_logic_vector(g_width - 1 downto 0);
out_dat : out std_logic_vector(g_width - 1 downto 0)
@@ -41,11 +42,16 @@ end ip_arria10_e2sg_ddio_out;
architecture str of ip_arria10_e2sg_ddio_out is
component ip_arria10_e2sg_ddio_out_1 is
port (
- dataout : out std_logic_vector(0 downto 0); -- pad_out.export
- outclock : in std_logic := '0'; -- ck.export
- aclr : in std_logic := '0'; -- aclr.export
- datain_h : in std_logic_vector(0 downto 0) := (others => '0'); -- datain_h.fragment
- datain_l : in std_logic_vector(0 downto 0) := (others => '0') -- datain_l.fragment
+ -- pad_out.export
+ dataout : out std_logic_vector(0 downto 0);
+ -- ck.export
+ outclock : in std_logic := '0';
+ -- aclr.export
+ aclr : in std_logic := '0';
+ -- datain_h.fragment
+ datain_h : in std_logic_vector(0 downto 0) := (others => '0');
+ -- datain_l.fragment
+ datain_l : in std_logic_vector(0 downto 0) := (others => '0')
);
end component;
begin
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd
index 03062d9b02f9e011238dfc6b4cd39b0bc78ac2bc..7ddc2effb3c89bae78a7f1e4cf398fde01d8da44 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd
@@ -1,90 +1,172 @@
component ip_arria10_e2sg_ddr4_8g_1600 is
port (
- global_reset_n : in std_logic := 'X'; -- reset_n
- pll_ref_clk : in std_logic := 'X'; -- clk
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic; -- local_cal_fail
- emif_usr_reset_n : out std_logic; -- reset_n
- emif_usr_clk : out std_logic; -- clk
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic; -- readdatavalid
- mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
- mmr_slave_read_0 : in std_logic := 'X'; -- read
- mmr_slave_write_0 : in std_logic := 'X'; -- write
- mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
- mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
- mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
- mmr_slave_readdatavalid_0 : out std_logic -- readdatavalid
+ -- reset_n
+ global_reset_n : in std_logic := 'X';
+ -- clk
+ pll_ref_clk : in std_logic := 'X';
+ -- oct_rzqin
+ oct_rzqin : in std_logic := 'X';
+ -- mem_ck
+ mem_ck : out std_logic_vector(1 downto 0);
+ -- mem_ck_n
+ mem_ck_n : out std_logic_vector(1 downto 0);
+ -- mem_a
+ mem_a : out std_logic_vector(16 downto 0);
+ -- mem_act_n
+ mem_act_n : out std_logic_vector(0 downto 0);
+ -- mem_ba
+ mem_ba : out std_logic_vector(1 downto 0);
+ -- mem_bg
+ mem_bg : out std_logic_vector(1 downto 0);
+ -- mem_cke
+ mem_cke : out std_logic_vector(1 downto 0);
+ -- mem_cs_n
+ mem_cs_n : out std_logic_vector(1 downto 0);
+ -- mem_odt
+ mem_odt : out std_logic_vector(1 downto 0);
+ -- mem_reset_n
+ mem_reset_n : out std_logic_vector(0 downto 0);
+ -- mem_par
+ mem_par : out std_logic_vector(0 downto 0);
+ -- mem_alert_n
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X');
+ -- mem_dqs
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- mem_dqs_n
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- mem_dq
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X');
+ -- mem_dbi_n
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X');
+ -- local_cal_success
+ local_cal_success : out std_logic;
+ -- local_cal_fail
+ local_cal_fail : out std_logic;
+ -- reset_n
+ emif_usr_reset_n : out std_logic;
+ -- clk
+ emif_usr_clk : out std_logic;
+ -- waitrequest_n
+ amm_ready_0 : out std_logic;
+ -- read
+ amm_read_0 : in std_logic := 'X';
+ -- write
+ amm_write_0 : in std_logic := 'X';
+ -- address
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X');
+ -- readdata
+ amm_readdata_0 : out std_logic_vector(575 downto 0);
+ -- writedata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X');
+ -- burstcount
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X');
+ -- byteenable
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X');
+ -- readdatavalid
+ amm_readdatavalid_0 : out std_logic;
+ -- waitrequest
+ mmr_slave_waitrequest_0 : out std_logic;
+ -- read
+ mmr_slave_read_0 : in std_logic := 'X';
+ -- write
+ mmr_slave_write_0 : in std_logic := 'X';
+ -- address
+ mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X');
+ -- readdata
+ mmr_slave_readdata_0 : out std_logic_vector(31 downto 0);
+ -- writedata
+ mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X');
+ -- burstcount
+ mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X');
+ -- beginbursttransfer
+ mmr_slave_beginbursttransfer_0 : in std_logic := 'X';
+ -- readdatavalid
+ mmr_slave_readdatavalid_0 : out std_logic
);
end component ip_arria10_e2sg_ddr4_8g_1600;
u0 : component ip_arria10_e2sg_ddr4_8g_1600
port map (
- global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
- mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
- mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
- mem_a => CONNECTED_TO_mem_a, -- .mem_a
- mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
- mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
- mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
- mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
- mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
- mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
- mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
- mem_par => CONNECTED_TO_mem_par, -- .mem_par
- mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
- mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
- mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
- mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
- mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
- local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
- local_cal_fail => CONNECTED_TO_local_cal_fail, -- .local_cal_fail
- emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
- emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
- amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
- amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
- amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
- amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
- amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
- amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
- amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
- mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
- mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
- mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
- mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
- mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
- mmr_slave_writedata_0 =>