From c7bb43646180b470ab2e1298673ebfb35de00ae1 Mon Sep 17 00:00:00 2001 From: Erik Kooistra <kooistra@astron.nl> Date: Tue, 3 Jun 2014 10:10:09 +0000 Subject: [PATCH] Corrected entity name to match file name ip_stratixiv_hssi_gx_16b. --- .../ip_stratixiv_hssi_gx_16b.vhd | 34 +++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_gx_16b.vhd b/libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_gx_16b.vhd index 6192166ed1..ad3d4df326 100644 --- a/libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_gx_16b.vhd +++ b/libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_gx_16b.vhd @@ -4,7 +4,7 @@ -- MODULE: alt4gxb -- ============================================================ --- File Name: ip_stratixiv_hssi_gx_16.vhd +-- File Name: ip_stratixiv_hssi_gx_16b.vhd -- Megafunction Name(s): -- alt4gxb -- @@ -43,7 +43,7 @@ LIBRARY ieee; USE ieee.std_logic_1164.all; - ENTITY ip_stratixiv_hssi_gx_16_alt4gxb IS + ENTITY ip_stratixiv_hssi_gx_16b_alt4gxb IS GENERIC ( starting_channel_number : NATURAL := 0 @@ -70,9 +70,9 @@ tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0') ); - END ip_stratixiv_hssi_gx_16_alt4gxb; + END ip_stratixiv_hssi_gx_16b_alt4gxb; - ARCHITECTURE RTL OF ip_stratixiv_hssi_gx_16_alt4gxb IS + ARCHITECTURE RTL OF ip_stratixiv_hssi_gx_16b_alt4gxb IS ATTRIBUTE synthesis_clearbox : natural; ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2; @@ -2040,14 +2040,14 @@ txpmareset => tx_analogreset_out(0) ); - END RTL; --ip_stratixiv_hssi_gx_16_alt4gxb + END RTL; --ip_stratixiv_hssi_gx_16b_alt4gxb --VALID FILE LIBRARY ieee; USE ieee.std_logic_1164.all; -ENTITY ip_stratixiv_hssi_gx_16 IS +ENTITY ip_stratixiv_hssi_gx_16b IS GENERIC ( starting_channel_number : NATURAL := 0 @@ -2074,17 +2074,17 @@ ENTITY ip_stratixiv_hssi_gx_16 IS tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) ); -END ip_stratixiv_hssi_gx_16; +END ip_stratixiv_hssi_gx_16b; -ARCHITECTURE RTL OF ip_stratixiv_hssi_gx_16 IS +ARCHITECTURE RTL OF ip_stratixiv_hssi_gx_16b IS ATTRIBUTE synthesis_clearbox: natural; ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2; ATTRIBUTE clearbox_macroname: string; ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "alt4gxb"; ATTRIBUTE clearbox_defparam: string; - ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "effective_data_rate=2500 Mbps;enable_lc_tx_pll=false;enable_pll_inclk_alt_drive_rx_cru=true;enable_pll_inclk_drive_rx_cru=true;equalizer_ctrl_a_setting=0;equalizer_ctrl_b_setting=0;equalizer_ctrl_c_setting=0;equalizer_ctrl_d_setting=0;equalizer_ctrl_v_setting=0;equalizer_dcgain_setting=0;gen_reconfig_pll=false;gxb_analog_power=AUTO;gx_channel_type=AUTO;input_clock_frequency=156.25 MHz;intended_device_family=Stratix IV;intended_device_speed_grade=2;intended_device_variant=GX;loopback_mode=none;lpm_hint=CBX_MODULE_PREFIX=ip_stratixiv_hssi_gx_16;lpm_type=alt4gxb;number_of_channels=1;operation_mode=duplex;pll_control_width=1;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=18;preemphasis_ctrl_2ndposttap_inv_setting=false;preemphasis_ctrl_2ndposttap_setting=0;preemphasis_ctrl_pretap_inv_setting=false;preemphasis_ctrl_pretap_setting=0;protocol=basic;receiver_termination=oct_100_ohms;reconfig_dprio_mode=0;rx_8b_10b_mode=normal;rx_align_loss_sync_error_num=1;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=false;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_width=16;rx_common_mode=0.82v;rx_cru_bandwidth_type=Auto;rx_cru_inclock0_period=6400;rx_datapath_low_latency_mode=false;rx_datapath_protocol=basic;rx_data_rate=2500;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_deep_align_byte_swap=false;rx_enable_lock_to_data_sig=false;" & + ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "effective_data_rate=2500 Mbps;enable_lc_tx_pll=false;enable_pll_inclk_alt_drive_rx_cru=true;enable_pll_inclk_drive_rx_cru=true;equalizer_ctrl_a_setting=0;equalizer_ctrl_b_setting=0;equalizer_ctrl_c_setting=0;equalizer_ctrl_d_setting=0;equalizer_ctrl_v_setting=0;equalizer_dcgain_setting=0;gen_reconfig_pll=false;gxb_analog_power=AUTO;gx_channel_type=AUTO;input_clock_frequency=156.25 MHz;intended_device_family=Stratix IV;intended_device_speed_grade=2;intended_device_variant=GX;loopback_mode=none;lpm_hint=CBX_MODULE_PREFIX=ip_stratixiv_hssi_gx_16b;lpm_type=alt4gxb;number_of_channels=1;operation_mode=duplex;pll_control_width=1;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=18;preemphasis_ctrl_2ndposttap_inv_setting=false;preemphasis_ctrl_2ndposttap_setting=0;preemphasis_ctrl_pretap_inv_setting=false;preemphasis_ctrl_pretap_setting=0;protocol=basic;receiver_termination=oct_100_ohms;reconfig_dprio_mode=0;rx_8b_10b_mode=normal;rx_align_loss_sync_error_num=1;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=false;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_width=16;rx_common_mode=0.82v;rx_cru_bandwidth_type=Auto;rx_cru_inclock0_period=6400;rx_datapath_low_latency_mode=false;rx_datapath_protocol=basic;rx_data_rate=2500;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_deep_align_byte_swap=false;rx_enable_lock_to_data_sig=false;" & "rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_flip_rx_out=false;rx_force_signal_detect=true;rx_num_align_cons_good_data=1;rx_num_align_cons_pat=1;rx_phfiforegmode=false;rx_ppmselect=32;rx_rate_match_fifo_mode=none;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=2;rx_use_align_state_machine=true;rx_use_clkout=true;rx_use_coreclk=false;rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=true;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_analog_power=1.4v;tx_channel_width=16;tx_clkout_width=1;tx_common_mode=0.65v;tx_datapath_low_latency_mode=false;tx_data_rate=2500;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_flip_tx_in=false;tx_force_disparity_mode=false;tx_pll_bandwidth_type=Auto;tx_pll_inclk0_period=6400;tx_pll_type=CMU;tx_slew_rate=off;tx_transmit_protocol=basic;tx_use_coreclk=false;tx_use_double_data_mode=true;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=4;gxb_powerdown_width=1;number_of_quads=1;reconfig_calibration=true;reconfig_fromgxb_port_width=17;reconfig_togxb_port_width=4;rx_cru_m_divider=8;rx_cru_n_divider=1;rx_cru_vco_post_scale_divider=2;rx_dwidth_factor=2;rx_signal_detect_loss_threshold=9;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;tx_dwidth_factor=2;tx_pll_clock_post_divider=1;tx_pll_m_divider=8;" & "tx_pll_n_divider=1;tx_pll_vco_post_scale_divider=2;tx_use_external_termination=false;"; SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); @@ -2098,7 +2098,7 @@ ARCHITECTURE RTL OF ip_stratixiv_hssi_gx_16 IS - COMPONENT ip_stratixiv_hssi_gx_16_alt4gxb + COMPONENT ip_stratixiv_hssi_gx_16b_alt4gxb GENERIC ( starting_channel_number : NATURAL ); @@ -2135,7 +2135,7 @@ BEGIN rx_ctrldetect <= sub_wire6(1 DOWNTO 0); rx_dataout <= sub_wire7(15 DOWNTO 0); - ip_stratixiv_hssi_gx_16_alt4gxb_component : ip_stratixiv_hssi_gx_16_alt4gxb + ip_stratixiv_hssi_gx_16b_alt4gxb_component : ip_stratixiv_hssi_gx_16b_alt4gxb GENERIC MAP ( starting_channel_number => starting_channel_number ) @@ -2362,11 +2362,11 @@ END RTL; -- Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0 -- Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0 -- Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_16.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_16.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_16.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_16.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_16.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_16_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_16b.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_16b.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_16b.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_16b.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_16b.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_16b_inst.vhd FALSE -- Retrieval info: LIB_FILE: stratixiv_hssi -- Retrieval info: CBX_MODULE_PREFIX: ON -- GitLab