From c761492fcfb1764e523980587afbf064631785c6 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Tue, 13 Jan 2015 13:11:20 +0000
Subject: [PATCH] added the ETH_CLK config options 25 , 125 MHz
---
.../unb2_minimal/src/vhdl/unb2_minimal.vhd | 37 ++++++++-----------
1 file changed, 16 insertions(+), 21 deletions(-)
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
index 5ebc7df33c..2745a6d31f 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
@@ -70,18 +70,15 @@ ARCHITECTURE str OF unb2_minimal IS
-- System
SIGNAL cs_sim : STD_LOGIC;
- SIGNAL xo_clk25 : STD_LOGIC;
- SIGNAL xo_rst25 : STD_LOGIC;
- SIGNAL xo_rst25_n : STD_LOGIC;
+ SIGNAL xo_ethclk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
SIGNAL mm_clk : STD_LOGIC;
- SIGNAL mm_locked : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC;
SIGNAL st_rst : STD_LOGIC;
SIGNAL st_clk : STD_LOGIC;
- SIGNAL epcs_clk : STD_LOGIC;
-
-- PIOs
SIGNAL pout_wdi : STD_LOGIC;
@@ -139,29 +136,27 @@ BEGIN
-----------------------------------------------------------------------------
u_ctrl : ENTITY unb2_board_lib.ctrl_unb2_board
GENERIC MAP (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb2_board_mm_clk_freq_50M,
- g_aux => c_unb2_board_aux
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb2_board_mm_clk_freq_50M,
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux
)
PORT MAP (
-- Clock an reset signals
cs_sim => cs_sim,
- xo_clk25 => xo_clk25,
- xo_rst25 => xo_rst25,
- xo_rst25_n => xo_rst25_n,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
mm_clk => mm_clk,
- mm_locked => mm_locked,
mm_rst => mm_rst,
- epcs_clk => epcs_clk,
-
dp_rst => st_rst,
dp_clk => st_clk,
dp_pps => OPEN,
--
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