From c6f053f45647514a1af887cfabc7b33b89d306d8 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Fri, 22 May 2015 11:20:14 +0000
Subject: [PATCH] using 125MHz clock for mm_clk

---
 boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
index fe44cfe325..2f3e2d6f30 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
@@ -72,7 +72,7 @@ ARCHITECTURE str OF unb2_minimal IS
 
   -- Firmware version x.y
   CONSTANT c_fw_version             : t_unb2_board_fw_version := (1, 1);
-  CONSTANT c_mm_clk_freq            : NATURAL := c_unb2_board_mm_clk_freq_50M;
+  CONSTANT c_mm_clk_freq            : NATURAL := c_unb2_board_mm_clk_freq_125M;
 
   -- System
   SIGNAL cs_sim                     : STD_LOGIC;
-- 
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