From c67b38366c4d509dc7bba3c38ba5832783dd428e Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 25 Jun 2015 10:05:02 +0000
Subject: [PATCH] Added gen_stream_MB_II
---
.../designs/unb2_test/src/vhdl/unb2_test.vhd | 169 ++++++++++++++----
1 file changed, 132 insertions(+), 37 deletions(-)
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 402c334af7..d32c050110 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -146,10 +146,8 @@ ARCHITECTURE str OF unb2_test IS
CONSTANT c_use_10GbE_ring : BOOLEAN := c_use_10GbE;
CONSTANT c_use_10GbE_back0 : BOOLEAN := FALSE;
CONSTANT c_use_10GbE_back1 : BOOLEAN := FALSE;
- CONSTANT c_use_ddr : BOOLEAN := g_design_name="unb2_test_ddr" OR g_design_name="unb2_test_all";
- CONSTANT c_use_MB_I : BOOLEAN := c_use_ddr; -- FIXME: g_design_name="unb2_test_MB_I" OR g_design_name="unb2_test_all";
- CONSTANT c_use_MB_II : BOOLEAN := FALSE; -- FIXME: g_design_name="unb2_test_MB_II" OR g_design_name="unb2_test_all";
- CONSTANT c_use_MB_both : BOOLEAN := FALSE; -- FIXME: c_use_MB_I OR c_use_MB_II;
+ CONSTANT c_use_MB_I : BOOLEAN := g_design_name="unb2_test_ddr_MB_I" OR g_design_name="unb2_test_ddr_MB_I_II" OR g_design_name="unb2_test_all";
+ CONSTANT c_use_MB_II : BOOLEAN := g_design_name="unb2_test_ddr_MB_II" OR g_design_name="unb2_test_ddr_MB_I_II" OR g_design_name="unb2_test_all";
-- transceivers
CONSTANT c_nof_qsfp : NATURAL := c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;--8
@@ -369,17 +367,28 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL dp_offload_tx_10GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
SIGNAL dp_offload_rx_10GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
SIGNAL dp_offload_rx_10GbE_snk_out_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
-
- SIGNAL reg_diag_tx_seq_ddr_mosi : t_mem_mosi;
- SIGNAL reg_diag_tx_seq_ddr_miso : t_mem_miso;
- SIGNAL reg_diag_rx_seq_ddr_mosi : t_mem_mosi;
- SIGNAL reg_diag_rx_seq_ddr_miso : t_mem_miso;
- SIGNAL reg_diag_data_buf_ddr_mosi : t_mem_mosi;
- SIGNAL reg_diag_data_buf_ddr_miso : t_mem_miso;
- SIGNAL ram_diag_data_buf_ddr_mosi : t_mem_mosi;
- SIGNAL ram_diag_data_buf_ddr_miso : t_mem_miso;
- SIGNAL reg_io_ddr_mosi : t_mem_mosi;
- SIGNAL reg_io_ddr_miso : t_mem_miso;
+
+ SIGNAL reg_io_ddr_MB_I_mosi : t_mem_mosi;
+ SIGNAL reg_io_ddr_MB_I_miso : t_mem_miso;
+ SIGNAL reg_diag_tx_seq_ddr_MB_I_mosi : t_mem_mosi;
+ SIGNAL reg_diag_tx_seq_ddr_MB_I_miso : t_mem_miso;
+ SIGNAL reg_diag_rx_seq_ddr_MB_I_mosi : t_mem_mosi;
+ SIGNAL reg_diag_rx_seq_ddr_MB_I_miso : t_mem_miso;
+ SIGNAL reg_diag_data_buf_ddr_MB_I_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_ddr_MB_I_miso : t_mem_miso;
+ SIGNAL ram_diag_data_buf_ddr_MB_I_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_ddr_MB_I_miso : t_mem_miso;
+
+ SIGNAL reg_io_ddr_MB_II_mosi : t_mem_mosi;
+ SIGNAL reg_io_ddr_MB_II_miso : t_mem_miso;
+ SIGNAL reg_diag_tx_seq_ddr_MB_II_mosi : t_mem_mosi;
+ SIGNAL reg_diag_tx_seq_ddr_MB_II_miso : t_mem_miso;
+ SIGNAL reg_diag_rx_seq_ddr_MB_II_mosi : t_mem_mosi;
+ SIGNAL reg_diag_rx_seq_ddr_MB_II_miso : t_mem_miso;
+ SIGNAL reg_diag_data_buf_ddr_MB_II_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_ddr_MB_II_miso : t_mem_miso;
+ SIGNAL ram_diag_data_buf_ddr_MB_II_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_ddr_MB_II_miso : t_mem_miso;
-- Interface: 1GbE UDP streaming ports
SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
@@ -655,16 +664,29 @@ BEGIN
reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
- reg_diag_tx_seq_ddr_mosi => reg_diag_tx_seq_ddr_mosi,
- reg_diag_tx_seq_ddr_miso => reg_diag_tx_seq_ddr_miso,
- reg_diag_rx_seq_ddr_mosi => reg_diag_rx_seq_ddr_mosi,
- reg_diag_rx_seq_ddr_miso => reg_diag_rx_seq_ddr_miso,
- reg_diag_data_buf_ddr_mosi => reg_diag_data_buf_ddr_mosi,
- reg_diag_data_buf_ddr_miso => reg_diag_data_buf_ddr_miso,
- ram_diag_data_buf_ddr_mosi => ram_diag_data_buf_ddr_mosi,
- ram_diag_data_buf_ddr_miso => ram_diag_data_buf_ddr_miso,
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso
+ -- DDR4 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR4 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
@@ -935,7 +957,7 @@ BEGIN
END GENERATE;
- gen_stream_MB_I : IF c_use_MB_I = TRUE OR c_use_MB_both=TRUE GENERATE
+ gen_stream_MB_I : IF c_use_MB_I = TRUE GENERATE
u_mms_io_ddr_diag : ENTITY io_ddr_lib.mms_io_ddr_diag
GENERIC MAP (
-- System
@@ -977,8 +999,8 @@ BEGIN
ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-- MM interface
- reg_io_ddr_mosi => reg_io_ddr_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_miso,
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-- Write / read FIFO status for monitoring purposes (in dp_clk domain)
wr_fifo_usedw => OPEN,
@@ -993,25 +1015,98 @@ BEGIN
-- DIAG Tx seq
---------------------------------------------------------------------------
-- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
---------------------------------------------------------------------------
-- DIAG rx seq with optional data buffer
---------------------------------------------------------------------------
-- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_data_buf_mosi => ram_diag_data_buf_ddr_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_miso,
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_miso
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
);
END GENERATE;
- gen_stream_MB_II : IF c_use_MB_II = TRUE OR c_use_MB_both=TRUE GENERATE
+ gen_stream_MB_II : IF c_use_MB_II = TRUE GENERATE
+ u_mms_io_ddr_diag : ENTITY io_ddr_lib.mms_io_ddr_diag
+ GENERIC MAP (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w, -- DP data width, func_tech_ddr_ctlr_data_w(g_io_tech_ddr)/g_dp_data_w must be a power of 2 due to the mixed width FIFO
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w, -- >= 1, test sequence data width. Choose g_dp_seq_dat_w <= g_dp_data_w. The seq data gets replicated to fill g_dp_data_w.
+ g_dp_fifo_depth => c_ddr_dp_fifo_depth, -- >= 2048, write FIFO depth and read FIFO depth at DP side of the FIFOs
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_II,
+
+ -- DIAG data buffer
+ g_db_use_db => FALSE,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ PORT MAP (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_II_REF_CLK,
+ ctlr_ref_rst => mb_II_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_II_clk200,
+ ctlr_rst_out => ddr_II_rst200,
+
+ ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_II_IN,
+ phy4_io => MB_II_IO,
+ phy4_ou => MB_II_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
END GENERATE;
END str;
--
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