diff --git a/libraries/io/tr_10GbE/hdllib.cfg b/libraries/io/tr_10GbE/hdllib.cfg
index c15d56e812b43f49747e6c1330faeeb45dd55383..84b9d648d28cebaff09e8f00da69a445d56c2adb 100644
--- a/libraries/io/tr_10GbE/hdllib.cfg
+++ b/libraries/io/tr_10GbE/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tr_10GbE
hdl_library_clause_name = tr_10GbE_lib
-hdl_lib_uses = common dp diag diagnostics tr_xaui tse
+hdl_lib_uses = common dp diag diagnostics tr_xaui eth
hdl_lib_technology =
build_sim_dir = $HDL_BUILD_DIR
@@ -8,6 +8,6 @@ build_synth_dir = $HDL_BUILD_DIR
synth_files =
$UNB/Firmware/modules/tr_10GbE/src/ip/megawizard/mac_10g/mac_10g.vhd
- $UNB/Firmware/modules/tr_10GbE/src/vhdl/tr_10GbE.vhd
+ src/vhdl/tr_10GbE.vhd
test_bench_files =
diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e8e23b994faf7245b297d2291ce3d44991f27ea1
--- /dev/null
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
@@ -0,0 +1,674 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib, diag_lib, tr_xaui_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE tr_xaui_lib.tr_xaui_pkg.ALL;
+
+ENTITY tr_10GbE IS
+ GENERIC (
+ g_sim : BOOLEAN;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
+ g_nof_macs : NATURAL;
+ g_use_mdio : BOOLEAN;
+ g_mdio_epcs_dis : BOOLEAN := FALSE; -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
+ g_pkt_len : NATURAL := 100;
+ g_lpbk_sosi : BOOLEAN := FALSE; -- i/o pins <-> ][ <-> tr_xaui <-> ][ <-> tr_10GbE <-> ][ <-> packetizing <-> user
+ g_lpbk_xgmii : BOOLEAN := FALSE; -- ^^ ^^ ^^
+ g_lpbk_xaui : BOOLEAN := FALSE; -- g_lpbk_xaui| g_lpbk_xgmii| g_lpbk_sosi|
+ g_use_hdr_ram : BOOLEAN := FALSE;
+ g_word_alignment_padding : BOOLEAN := FALSE
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ tr_clk : IN STD_LOGIC;
+
+ cal_rec_clk : IN STD_LOGIC;
+
+ dp_rst : IN STD_LOGIC := '0';
+ dp_clk : IN STD_LOGIC := '0';
+
+ snk_out_arr : OUT t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+
+ src_in_arr : IN t_dp_siso_arr(g_nof_macs-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
+ src_out_arr : OUT t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+
+ -- MM registers
+ reg_hdr_insert_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_hdr_insert_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+
+ ram_hdr_remove_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_hdr_remove_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ reg_mac_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_mac_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ --Serial I/O
+ xaui_rx_in_arr : IN t_xaui_arr(g_nof_macs-1 DOWNTO 0);
+ xaui_tx_out_arr : OUT t_xaui_arr(g_nof_macs-1 DOWNTO 0);
+
+ -- MDIO External clock and serial data i/o
+ mdio_rst : OUT STD_LOGIC;
+ mdio_mdc_arr : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
+ mdio_mdat_in_arr : IN STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0) := (OTHERS=>'0');
+ mdio_mdat_oen_arr : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
+
+ mdio_mosi_arr : IN t_mem_mosi_arr(g_nof_macs-1 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst);
+ mdio_miso_arr : OUT t_mem_miso_arr(g_nof_macs-1 DOWNTO 0);
+
+ -- XAUI PHY IP MM control/status
+ xaui_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ xaui_miso : OUT t_mem_miso
+ );
+END tr_10GbE;
+
+
+ARCHITECTURE str OF tr_10GbE IS
+
+ CONSTANT c_nof_header_words : NATURAL := 8; --8 64b words = 16 32b words
+
+ CONSTANT c_mac_mm_addr_w : NATURAL := 13;
+
+ CONSTANT c_hdr_insert_reg_addr_w : NATURAL := 1; -- Only 1 register used. A width of 1 still yields 2 addresses/instance though.
+ CONSTANT c_hdr_insert_ram_addr_w : NATURAL := ceil_log2( c_nof_header_words * (c_xgmii_data_w/c_word_w) );
+ CONSTANT c_hdr_remove_ram_addr_w : NATURAL := ceil_log2( c_nof_header_words * (c_xgmii_data_w/c_word_w) );
+
+ CONSTANT c_fifo_margin : NATURAL := 10;
+
+ CONSTANT c_word_alignment_padding_nof_bytes : NATURAL := 6; -- 6 Bytes (=48 bits) of padding aligns the 336 bit eth/ip/udp header to a 64b word boundary: 336+48=384 (multiple of 64).
+
+ CONSTANT c_remove_crc : BOOLEAN := sel_a_b(g_lpbk_sosi, FALSE, TRUE); --The MAC adds a CRC
+ CONSTANT c_nof_crc_words : NATURAL := (c_network_eth_crc_len * c_byte_w) / c_word_w;
+
+ -- Tail: One packet contianing only one word of which the last 4 (LS) bytes are empty
+ CONSTANT c_empty_crc_sosi : t_dp_sosi := ('0', (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), '1', '1', '1', (OTHERS=>'1'), (OTHERS=>'0'), (OTHERS=>'0'));
+
+ SIGNAL tx_clk_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
+ SIGNAL tx_rst_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL rx_clk_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
+ SIGNAL rx_rst_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL tx_rst_n_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
+ SIGNAL rx_rst_n_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL mm_rst_n : STD_LOGIC;
+
+ SIGNAL reg_hdr_insert_mosi_arr : t_mem_mosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL ram_hdr_insert_mosi_arr : t_mem_mosi_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL ram_hdr_remove_mosi_arr : t_mem_mosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL ram_hdr_remove_miso_arr : t_mem_miso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL reg_mac_mosi_arr : t_mem_mosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL reg_mac_miso_arr : t_mem_miso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL dp_fifo_dc_tx_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_fifo_dc_tx_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL dp_hdr_insert_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_hdr_insert_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL dp_pad_remove_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_pad_remove_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL dp_concat_snk_in_2arr : t_dp_sosi_2arr_2(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_concat_snk_out_2arr : t_dp_siso_2arr_2(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL dp_concat_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_concat_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL dp_fifo_fill_snk_in_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_fifo_fill_snk_out_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL dp_fifo_fill_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_fifo_fill_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL dp_latency_adapter_snk_in_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_snk_out_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL rx_sosi_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL rx_siso_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL dp_frame_remove_snk_in_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_frame_remove_snk_out_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL dp_pad_insert_snk_in_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_pad_insert_snk_out_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL mac_10g_snk_in_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL mac_10g_snk_out_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL mac_10g_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL mac_10g_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL dp_fifo_dc_rx_snk_in_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_fifo_dc_rx_snk_out_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL dp_fifo_dc_rx_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL dp_fifo_dc_rx_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL mac_xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL mac_xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL xaui_xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL xaui_xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL xaui_rx_arr : t_xaui_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL xaui_tx_arr : t_xaui_arr(g_nof_macs-1 DOWNTO 0);
+
+BEGIN
+
+ ---------------------------------------------------------------------------------------
+ -- Clocks and reset
+ ---------------------------------------------------------------------------------------
+ gen_tx_clk_arr: FOR i IN g_nof_macs-1 DOWNTO 0 GENERATE
+ tx_clk_arr(i) <= tr_clk;
+ END GENERATE;
+
+ tx_rst_n_arr <= NOT tx_rst_arr;
+ rx_rst_n_arr <= NOT rx_rst_arr;
+
+ mm_rst_n <= NOT mm_rst;
+
+ ---------------------------------------------------------------------------------------
+ -- TX FIFO: dp_clk -> tx_clk
+ ---------------------------------------------------------------------------------------
+ gen_dp_fifo_dc_tx : FOR i IN g_nof_macs-1 DOWNTO 0 GENERATE
+ u_dp_fifo_dc_tx : ENTITY dp_lib.dp_fifo_dc
+ GENERIC MAP (
+ g_data_w => c_xgmii_data_w
+ )
+ PORT MAP (
+ wr_rst => dp_rst,
+ wr_clk => dp_clk,
+ rd_rst => tx_rst_arr(i),
+ rd_clk => tx_clk_arr(i),
+
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
+
+ src_in => dp_fifo_dc_tx_src_in_arr(i),
+ src_out => dp_fifo_dc_tx_src_out_arr(i)
+ );
+ END GENERATE;
+
+ ---------------------------------------------------------------------------------------
+ -- TX packetizing: Add a header to the stream
+ ---------------------------------------------------------------------------------------
+ gen_dp_hdr_insert : FOR i IN 0 TO g_nof_macs-1 GENERATE
+ u_dp_hdr_insert : ENTITY dp_lib.dp_hdr_insert
+ GENERIC MAP (
+ g_data_w => c_xgmii_data_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_nof_words => c_nof_header_words,
+ g_internal_bypass => NOT g_use_hdr_ram
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => tx_rst_arr(i),
+ st_clk => tx_clk_arr(i),
+
+ reg_mosi => reg_hdr_insert_mosi_arr(i),
+ ram_mosi => ram_hdr_insert_mosi_arr(i),
+
+ snk_out => dp_fifo_dc_tx_src_in_arr(i),
+ snk_in => dp_fifo_dc_tx_src_out_arr(i),
+
+ src_in => dp_hdr_insert_src_in_arr(i),
+ src_out => dp_hdr_insert_src_out_arr(i)
+ );
+ END GENERATE;
+
+ ---------------------------------------------------------------------------------------
+ -- TX: Remove the word-alignment padding that precedes the DP frame
+ ---------------------------------------------------------------------------------------
+ gen_dp_pad_remove : FOR i IN 0 TO g_nof_macs-1 GENERATE
+ u_dp_pad_remove : ENTITY dp_lib.dp_pad_remove
+ GENERIC MAP (
+ g_data_w => c_xgmii_data_w,
+ g_symbol_w => c_byte_w,
+ g_nof_padding => c_word_alignment_padding_nof_bytes,
+ g_internal_bypass => NOT g_word_alignment_padding
+ )
+ PORT MAP (
+ rst => tx_rst_arr(i),
+ clk => tx_clk_arr(i),
+
+ snk_out => dp_hdr_insert_src_in_arr(i),
+ snk_in => dp_hdr_insert_src_out_arr(i),
+
+ src_in => dp_pad_remove_src_in_arr(i), --,
+ src_out => dp_pad_remove_src_out_arr(i) --
+ );
+ END GENERATE;
+
+ ---------------------------------------------------------------------------------------
+ -- TX: Add one empty word at the tail; the MAC will insert its CRC there.
+ -- This is only required if there are not 4 or more empty symbols in the last word.
+ -- If a 6-byte padding was removed from the SOP word, weĺl end up with 6 empty
+ -- bytes in the EOP word which is already sufficient for CRC insertion.
+ ---------------------------------------------------------------------------------------
+ gen_empty_at_eop : IF g_word_alignment_padding = FALSE GENERATE
+
+ gen_dp_concat_snk : FOR i IN 0 TO g_nof_macs-1 GENERATE
+ dp_concat_snk_in_2arr(i)(1) <= dp_pad_remove_src_out_arr(i);
+ dp_pad_remove_src_in_arr(i) <= dp_concat_snk_out_2arr(i)(1);
+ END GENERATE;
+
+ gen_dp_ready : FOR i IN 0 TO g_nof_macs-1 GENERATE -- Add flow control to dp_concat_snk_in
+ u_dp_ready : ENTITY dp_lib.dp_ready
+ PORT MAP (
+ rst => tx_rst_arr(i),
+ clk => tx_clk_arr(i),
+
+ snk_in => c_empty_crc_sosi,
+
+ src_in => dp_concat_snk_out_2arr(i)(0),
+ src_out => dp_concat_snk_in_2arr(i)(0)
+ );
+ END GENERATE;
+
+ gen_dp_concat : FOR i IN 0 TO g_nof_macs-1 GENERATE
+ u_dp_concat : ENTITY dp_lib.dp_concat
+ GENERIC MAP (
+ g_data_w => c_xgmii_data_w,
+ g_symbol_w => c_byte_w
+ )
+ PORT MAP (
+ rst => tx_rst_arr(i),
+ clk => tx_clk_arr(i),
+ snk_out_arr => dp_concat_snk_out_2arr(i),
+ snk_in_arr => dp_concat_snk_in_2arr(i),
+ src_in => dp_concat_src_in_arr(i),
+ src_out => dp_concat_src_out_arr(i)
+ );
+
+ dp_concat_src_in_arr(i) <= dp_fifo_fill_snk_out_arr(i);
+
+ -- Set the empty field at the eop, dp_concat does not preserve it
+ proc_empty : PROCESS(dp_concat_src_out_arr(i))
+ BEGIN
+ dp_fifo_fill_snk_in_arr(i) <= dp_concat_src_out_arr(i);
+ dp_fifo_fill_snk_in_arr(i).empty <= (OTHERS=>'0');
+
+ IF dp_concat_src_out_arr(i).eop = '1' THEN
+ dp_fifo_fill_snk_in_arr(i).empty <= (OTHERS=>'1');
+ END IF;
+ END PROCESS;
+ END GENERATE;
+
+ END GENERATE;
+
+ gen_another_name : IF g_word_alignment_padding = TRUE GENERATE
+
+ gen_dp_concat_snk : FOR i IN 0 TO g_nof_macs-1 GENERATE
+ dp_fifo_fill_snk_in_arr(i) <= dp_pad_remove_src_out_arr(i);
+ dp_pad_remove_src_in_arr(i) <= dp_fifo_fill_snk_out_arr(i);
+ END GENERATE;
+
+ END GENERATE;
+
+ ---------------------------------------------------------------------------------------
+ -- TX: FIFO so we can deliver packets to the MAC fast enough
+ ---------------------------------------------------------------------------------------
+ gen_dp_fifo_fill : FOR i IN 0 TO g_nof_macs-1 GENERATE
+ u_dp_fifo_fill : ENTITY dp_lib.dp_fifo_fill
+ GENERIC MAP (
+ g_data_w => c_xgmii_data_w,
+ g_bsn_w => 0,
+ g_empty_w => 3,
+ g_channel_w => 0,
+ g_error_w => 0,
+ g_use_bsn => FALSE,
+ g_use_empty => TRUE,
+ g_use_channel => FALSE,
+ g_use_error => FALSE,
+ g_use_sync => FALSE,
+ g_fifo_fill => g_pkt_len, --Release packet only when available
+ g_fifo_size => g_pkt_len+c_fifo_margin
+ )
+ PORT MAP (
+ rst => tx_rst_arr(i),
+ clk => tx_clk_arr(i),
+
+ snk_out => dp_fifo_fill_snk_out_arr(i), --dp_concat_src_in_arr(i),
+ snk_in => dp_fifo_fill_snk_in_arr(i),
+
+ src_in => dp_fifo_fill_src_in_arr(i),
+ src_out => dp_fifo_fill_src_out_arr(i)
+ );
+ END GENERATE;
+
+ dp_fifo_fill_src_in_arr <= dp_pad_insert_snk_out_arr WHEN g_lpbk_sosi=TRUE ELSE dp_latency_adapter_snk_out_arr;
+
+ ---------------------------------------------------------------------------------------
+ -- 10GbE MAC IP
+ ---------------------------------------------------------------------------------------
+ dp_latency_adapter_snk_in_arr <= dp_fifo_fill_src_out_arr WHEN g_lpbk_sosi=FALSE ELSE (OTHERS=>c_dp_sosi_rst);
+
+ gen_dp_latency_adapter : FOR i IN 0 TO sel_a_b(g_lpbk_sosi, 0, g_nof_macs)-1 GENERATE
+ u_dp_latency_adapter : ENTITY dp_lib.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ PORT MAP (
+ rst => tx_rst_arr(i),
+ clk => tx_clk_arr(i),
+ -- ST sink
+ snk_out => dp_latency_adapter_snk_out_arr(i),
+ snk_in => dp_latency_adapter_snk_in_arr(i),
+ -- ST source
+ src_in => mac_10g_snk_out_arr(i),
+ src_out => mac_10g_snk_in_arr(i)
+ );
+ END GENERATE;
+
+ gen_mac_10g : FOR i IN 0 TO sel_a_b(g_lpbk_sosi, 0, g_nof_macs)-1 GENERATE
+
+ mac_10g_snk_out_arr(i).xon <= tx_rst_n_arr(i);
+
+ u_mac_10g : ENTITY work.mac_10g
+ PORT MAP (
+ csr_clk_clk => mm_clk,
+ csr_reset_reset_n => mm_rst_n,
+ csr_address => reg_mac_mosi_arr(i).address(c_mac_mm_addr_w-1 DOWNTO 0),
+ csr_waitrequest => reg_mac_miso_arr(i).waitrequest,
+ csr_read => reg_mac_mosi_arr(i).rd,
+ csr_readdata => reg_mac_miso_arr(i).rddata(c_word_w-1 DOWNTO 0),
+ csr_write => reg_mac_mosi_arr(i).wr,
+ csr_writedata => reg_mac_mosi_arr(i).wrdata(c_word_w-1 DOWNTO 0),
+
+ tx_clk_clk => tx_clk_arr(i),
+ tx_reset_reset_n => tx_rst_n_arr(i),
+
+ avalon_st_tx_startofpacket => mac_10g_snk_in_arr(i).sop,
+ avalon_st_tx_valid => mac_10g_snk_in_arr(i).valid,
+ avalon_st_tx_data => mac_10g_snk_in_arr(i).data(c_xgmii_data_w-1 DOWNTO 0),
+ avalon_st_tx_empty => mac_10g_snk_in_arr(i).empty(2 DOWNTO 0),
+ avalon_st_tx_ready => mac_10g_snk_out_arr(i).ready,
+ avalon_st_tx_error => mac_10g_snk_in_arr(i).err(0 DOWNTO 0),
+ avalon_st_tx_endofpacket => mac_10g_snk_in_arr(i).eop,
+ avalon_st_pause_data => (OTHERS=>'0'),
+
+ xgmii_tx_data => mac_xgmii_tx_dc_arr(i),
+
+ avalon_st_txstatus_valid => OPEN,
+ avalon_st_txstatus_data => OPEN,
+ avalon_st_txstatus_error => OPEN,
+
+ rx_clk_clk => rx_clk_arr(i),
+ rx_reset_reset_n => rx_rst_n_arr(i),
+
+ xgmii_rx_data => mac_xgmii_rx_dc_arr(i),
+
+ avalon_st_rx_startofpacket => mac_10g_src_out_arr(i).sop,
+ avalon_st_rx_endofpacket => mac_10g_src_out_arr(i).eop,
+ avalon_st_rx_valid => mac_10g_src_out_arr(i).valid,
+ avalon_st_rx_ready => mac_10g_src_in_arr(i).ready,
+ avalon_st_rx_data => mac_10g_src_out_arr(i).data(c_xgmii_data_w-1 DOWNTO 0),
+ avalon_st_rx_empty => mac_10g_src_out_arr(i).empty(2 DOWNTO 0),
+ avalon_st_rx_error => mac_10g_src_out_arr(i).err(5 DOWNTO 0),
+
+ avalon_st_rxstatus_valid => OPEN,
+ avalon_st_rxstatus_data => OPEN,
+ avalon_st_rxstatus_error => OPEN,
+
+ link_fault_status_xgmii_rx_data => OPEN
+ );
+
+ END GENERATE;
+
+ mac_10g_src_in_arr <= dp_pad_insert_snk_out_arr WHEN g_use_hdr_ram=TRUE ELSE dp_fifo_dc_rx_snk_out_arr;
+
+ ---------------------------------------------------------------------------------------
+ -- XGMII loopback: tr_xaui <-> ][ <-> tr_10GbE
+ ---------------------------------------------------------------------------------------
+ gen_lpbk_xgmii: IF g_lpbk_xgmii = TRUE GENERATE
+ -- 10GbE side loopback: [ <-> tr_10GbE
+ mac_xgmii_rx_dc_arr <= mac_xgmii_tx_dc_arr;
+ -- XAUI side loopback: tr_xaui <-> ]
+ xaui_xgmii_rx_dc_arr <= xaui_xgmii_tx_dc_arr;
+ END GENERATE;
+
+ no_lpbk_xgmii: IF g_lpbk_xgmii = FALSE GENERATE
+ xaui_xgmii_tx_dc_arr <= mac_xgmii_tx_dc_arr;
+ mac_xgmii_rx_dc_arr <= xaui_xgmii_rx_dc_arr;
+ END GENERATE;
+
+ ---------------------------------------------------------------------------------------
+ -- tr_xaui
+ ---------------------------------------------------------------------------------------
+ u_tr_xaui: ENTITY tr_xaui_lib.tr_xaui
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_use_xgmii => TRUE, -- Use XGMII direct
+ g_mdio => g_use_mdio,
+ g_mdio_epcs_dis => g_mdio_epcs_dis,
+ g_nof_xaui => g_nof_macs
+ )
+ PORT MAP (
+ tr_clk => tr_clk,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- Serial data
+ xaui_tx => xaui_tx_arr,
+ xaui_rx => xaui_rx_arr,
+
+ -- XGMII direct
+ xgmii_tx_dc_arr => xaui_xgmii_tx_dc_arr,
+ xgmii_rx_dc_arr => xaui_xgmii_rx_dc_arr,
+
+ -- MDIO
+ mdio_rst => mdio_rst,
+ mdio_mdc => mdio_mdc_arr,
+ mdio_mdat_in => mdio_mdat_in_arr,
+ mdio_mdat_oen => mdio_mdat_oen_arr,
+
+ mdio_mosi_arr => mdio_mosi_arr(g_nof_macs-1 DOWNTO 0),
+ mdio_miso_arr => mdio_miso_arr(g_nof_macs-1 DOWNTO 0),
+
+ -- XGMII I/O
+ rx_rst => rx_rst_arr,
+ rx_clk => rx_clk_arr,
+
+ tx_rst => tx_rst_arr,
+ tx_clk => tx_clk_arr,
+
+ cal_rec_clk => cal_rec_clk,
+
+ xaui_mosi => xaui_mosi,
+ xaui_miso => xaui_miso
+ );
+
+ ---------------------------------------------------------------------------------------
+ -- XAUI loopback: i/o pins <-> ][ <-> tr_xaui
+ ---------------------------------------------------------------------------------------
+ gen_lpbk_xaui: IF g_lpbk_xaui = TRUE GENERATE
+ -- XAUI side loopback: [ <-> tr_xaui
+ xaui_rx_arr <= xaui_tx_arr;
+ -- I/O side loopback: i/o pins <-> ]
+ xaui_tx_out_arr <= xaui_rx_in_arr;
+ END GENERATE;
+
+ no_lpbk_xaui: IF g_lpbk_xaui = FALSE GENERATE
+ xaui_tx_out_arr <= xaui_tx_arr;
+ xaui_rx_arr <= xaui_rx_in_arr;
+ END GENERATE;
+
+ ---------------------------------------------------------------------------------------
+ -- RX: Insert padding to align to 64b boundary
+ ---------------------------------------------------------------------------------------
+ dp_pad_insert_snk_in_arr <= dp_fifo_fill_src_out_arr WHEN g_lpbk_sosi=TRUE ELSE mac_10g_src_out_arr;
+
+ gen_dp_pad_insert : FOR i IN 0 TO g_nof_macs-1 GENERATE
+ u_dp_pad_insert : ENTITY dp_lib.dp_pad_insert
+ GENERIC MAP (
+ g_data_w => c_xgmii_data_w,
+ g_symbol_w => c_byte_w,
+ g_nof_padding => c_word_alignment_padding_nof_bytes,
+ g_internal_bypass => NOT g_word_alignment_padding
+ )
+ PORT MAP (
+ rst => rx_rst_arr(i),
+ clk => rx_clk_arr(i),
+
+ snk_out => dp_pad_insert_snk_out_arr(i),
+ snk_in => dp_pad_insert_snk_in_arr(i),
+
+ src_in => dp_frame_remove_snk_out_arr(i),
+ src_out => dp_frame_remove_snk_in_arr(i)
+ );
+ END GENERATE;
+
+ ---------------------------------------------------------------------------------------
+ -- RX: Unframe: remove header (and CRC if phy link is used) from DP packets
+ ---------------------------------------------------------------------------------------
+ gen_dp_frame_remove : FOR i IN 0 TO g_nof_macs-1 GENERATE
+ u_dp_frame_remove : ENTITY dp_lib.dp_frame_remove
+ GENERIC MAP (
+ g_data_w => c_xgmii_data_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_nof_words => c_nof_header_words,
+ g_tail_nof_words => sel_a_b(c_remove_crc, c_nof_crc_words, 0),
+ g_snk_latency => 0,
+ g_internal_bypass => NOT g_use_hdr_ram
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => rx_rst_arr(i),
+ st_clk => rx_clk_arr(i),
+
+ snk_out => dp_frame_remove_snk_out_arr(i),
+ snk_in => dp_frame_remove_snk_in_arr(i),
+
+ -- dp_frame_remove uses hdr_remove internally
+ sla_in => ram_hdr_remove_mosi_arr(i),
+ sla_out => ram_hdr_remove_miso_arr(i),
+
+ src_in => dp_fifo_dc_rx_snk_out_arr(i),
+ src_out => dp_fifo_dc_rx_snk_in_arr(i)
+ );
+ END GENERATE;
+
+ ---------------------------------------------------------------------------------------
+ -- RX FIFO: rx_clk -> dp_clk
+ ---------------------------------------------------------------------------------------
+ gen_dp_fifo_dc_rx : FOR i IN g_nof_macs-1 DOWNTO 0 GENERATE
+ u_dp_fifo_dc_rx : ENTITY dp_lib.dp_fifo_dc
+ GENERIC MAP (
+ g_data_w => c_xgmii_data_w
+ )
+ PORT MAP (
+ wr_rst => rx_rst_arr(i),
+ wr_clk => rx_clk_arr(i),
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+
+ snk_out => dp_fifo_dc_rx_snk_out_arr(i),
+ snk_in => dp_fifo_dc_rx_snk_in_arr(i),
+
+ src_in => dp_fifo_dc_rx_src_in_arr(i),
+ src_out => dp_fifo_dc_rx_src_out_arr(i)
+ );
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- RX XON frame control
+ -----------------------------------------------------------------------------
+ gen_dp_xonoff : FOR i IN g_nof_macs-1 DOWNTO 0 GENERATE
+ u_dp_xonoff : ENTITY dp_lib.dp_xonoff
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ in_siso => dp_fifo_dc_rx_src_in_arr(i),
+ in_sosi => dp_fifo_dc_rx_src_out_arr(i),
+
+ out_siso => src_in_arr(i),
+ out_sosi => src_out_arr(i)
+ );
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- MM bus muxes
+ -----------------------------------------------------------------------------
+ u_common_mem_mux : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_macs,
+ g_mult_addr_w => c_mac_mm_addr_w
+ )
+ PORT MAP (
+ mosi => reg_mac_mosi,
+ miso => reg_mac_miso,
+ mosi_arr => reg_mac_mosi_arr,
+ miso_arr => reg_mac_miso_arr
+ );
+
+ u_common_mem_mux_hdr_ins_reg : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_macs,
+ g_mult_addr_w => c_hdr_insert_reg_addr_w
+ )
+ PORT MAP (
+ mosi => reg_hdr_insert_mosi,
+ mosi_arr => reg_hdr_insert_mosi_arr
+ );
+
+ u_common_mem_mux_hdr_ins_ram : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_macs,
+ g_mult_addr_w => c_hdr_insert_ram_addr_w
+ )
+ PORT MAP (
+ mosi => ram_hdr_insert_mosi,
+ mosi_arr => ram_hdr_insert_mosi_arr
+ );
+
+ u_common_mem_mux_hdr_rem_ram : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_macs,
+ g_mult_addr_w => c_hdr_remove_ram_addr_w
+ )
+ PORT MAP (
+ mosi => ram_hdr_remove_mosi,
+ miso => ram_hdr_remove_miso,
+ mosi_arr => ram_hdr_remove_mosi_arr,
+ miso_arr => ram_hdr_remove_miso_arr
+ );
+
+END str;
diff --git a/libraries/io/tse/hdllib.cfg b/libraries/io/tse/hdllib.cfg
deleted file mode 100644
index 0980e165f01d5e8257f61f2052e66ae5fac2da73..0000000000000000000000000000000000000000
--- a/libraries/io/tse/hdllib.cfg
+++ /dev/null
@@ -1,47 +0,0 @@
-hdl_lib_name = tse
-hdl_library_clause_name = tse_lib
-hdl_lib_uses = dp common
-hdl_lib_technology =
-
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir =
-
-synth_files =
- $UNB/Firmware/modules/tse/../MegaWizard/tse_sgmii_lvds/tse_sgmii_lvds.vho
- $UNB/Firmware/modules/tse/../MegaWizard/tse_sgmii_gx/tse_sgmii_gx.vho
- $UNB/Firmware/modules/tse/../MegaWizard/gxb/v101/gx_reconfig_4.vhd
-
- $UNB/Firmware/modules/tse/src/vhdl/tse_pkg.vhd
- $UNB/Firmware/modules/tse/src/vhdl/tse.vhd
- $UNB/Firmware/modules/tse/src/vhdl/tse_a_stratix4.vhd
-
- $UNB/Firmware/modules/tse/src/vhdl/eth_layers_pkg.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth_pkg.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth_checksum.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth_hdr_store.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth_hdr_status.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth_hdr_ctrl.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth_hdr.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth_crc_ctrl.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth_crc_word.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth_mm_registers.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth_mm_reg_frame.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth_udp_channel.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth_buffer.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth_control.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth_ihl_to_20.vhd
- $UNB/Firmware/modules/tse/src/vhdl/eth.vhd
-
- $UNB/Firmware/modules/tse/src/vhdl/avs_eth.vhd
- $UNB/Firmware/modules/tse/src/vhdl/avs_eth_coe.vhd
-
-test_bench_files =
- $UNB/Firmware/modules/tse/tb/vhdl/tb_tse_pkg.vhd
- $UNB/Firmware/modules/tse/tb/vhdl/tb_tse.vhd
- $UNB/Firmware/modules/tse/tb/vhdl/tb_eth_checksum.vhd
- $UNB/Firmware/modules/tse/tb/vhdl/tb_eth_crc_ctrl.vhd
- $UNB/Firmware/modules/tse/tb/vhdl/tb_eth_hdr.vhd
- $UNB/Firmware/modules/tse/tb/vhdl/tb_eth.vhd
- $UNB/Firmware/modules/tse/tb/vhdl/tb_tb_eth.vhd
- $UNB/Firmware/modules/tse/tb/vhdl/tb_eth_udp_offload.vhd
- $UNB/Firmware/modules/tse/tb/vhdl/tb_eth_ihl_to_20.vhd
diff --git a/libraries/io/tse/quartus/tse_lib.qip b/libraries/io/tse/quartus/tse_lib.qip
deleted file mode 100644
index 593f1deec70d4b38a1966cfe046e059b914cf431..0000000000000000000000000000000000000000
--- a/libraries/io/tse/quartus/tse_lib.qip
+++ /dev/null
@@ -1,25 +0,0 @@
-# synth_files
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/../MegaWizard/tse_sgmii_lvds/tse_sgmii_lvds.vho
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/../MegaWizard/tse_sgmii_gx/tse_sgmii_gx.vho
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/../MegaWizard/gxb/v101/gx_reconfig_4.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/tse_pkg.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/tse.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/tse_a_stratix4.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_layers_pkg.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_pkg.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_checksum.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_hdr_store.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_hdr_status.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_hdr_ctrl.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_hdr.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_crc_ctrl.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_crc_word.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_mm_registers.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_mm_reg_frame.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_udp_channel.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_buffer.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_control.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth_ihl_to_20.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/eth.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/avs_eth.vhd
-set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/avs_eth_coe.vhd