From c647dca6a64fc7d53999725fd41ca74e1adc8a41 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Wed, 8 Apr 2015 12:59:34 +0000
Subject: [PATCH] -Cleaned the code.
---
.../src/vhdl/apertif_unb1_correlator.vhd | 374 ++++++++----------
1 file changed, 167 insertions(+), 207 deletions(-)
diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd b/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
index ad3b36237f..086c0fff92 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
+++ b/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
@@ -43,30 +43,26 @@ USE wpfb_lib.wpfb_pkg.ALL;
USE bf_lib.bf_pkg.ALL;
-- Purpose:
---
+-- . Calculate all cross- and autocorrelations of the incoming beamlets
-- Description:
---
+-- . The incpoming beamlets (3x 10GbE from fn_beamformer) are distributed among the 8 FPGAs per board; each FPGA correlates
+-- 1/8th of the beamlets.
-- Remarks:
--- . Compile times:
--- . 48 Visibility system with dumb terminals : ??? hours, Non-functional design, for resource util exploration only.
--- . 48 Visibility system: : 5.5 hours, fMax ~200MHz, should be functional but it is not.
--- . 48 Visibility system, no DSP : 3.5 hours
--- . 48 Visibility system, BG+offload only : 20 minutes, for visibility offload testing only
ENTITY apertif_unb1_correlator IS
GENERIC (
- g_design_name : STRING := "apertif_unb1_correlator";
- g_sim : BOOLEAN := FALSE; --Overridden by TB
- g_sim_unb_nr : NATURAL := 0;
- g_sim_node_nr : NATURAL := 0;
- g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
- g_use_dumb_mesh_terminals : BOOLEAN := FALSE; -- Add dumb mesh terminals to the design. Non-functional, for synthesis results only.
- g_offload_bg : BOOLEAN := FALSE;-- Bypass everything; use only a block-gen->dp_offload_tx.
- g_no_dsp : BOOLEAN := FALSE -- True = bypass WPFB, bypass correlator multipliers+accumulators.
- ); -- . Correlator does output correctly sized DP packets.
- PORT ( -- . Used to verify/validate data path from 10GbE receivers to 1GbE offload.
+ g_design_name : STRING := "apertif_unb1_correlator";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
+ g_use_dumb_mesh_terminals : BOOLEAN := FALSE;-- Add dumb mesh terminals to the design. Non-functional, for synthesis results only.
+ g_offload_bg : BOOLEAN := FALSE;-- Bypass everything; use only a block-gen->dp_offload_tx.
+ g_no_dsp : BOOLEAN := FALSE -- True = bypass WPFB, bypass correlator multipliers+accumulators.
+ ); -- . Correlator does output correctly sized DP packets.
+ PORT ( -- . Used to verify/validate data path from 10GbE receivers to 1GbE offload.
-- GENERAL
CLK : IN STD_LOGIC; -- System Clock
PPS : IN STD_LOGIC; -- System Sync
@@ -90,7 +86,7 @@ ENTITY apertif_unb1_correlator IS
-- Transceiver clocks
SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
- SB_CLK : IN STD_LOGIC; -- TR clock FN-BN (tr_mesh)
+ SB_CLK : IN STD_LOGIC; -- SerDes clock FN-BN (tr_mesh)
-- Mesh Serial I/O
FN_BN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
@@ -112,7 +108,7 @@ ENTITY apertif_unb1_correlator IS
SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
+ SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
@@ -125,7 +121,7 @@ END apertif_unb1_correlator;
ARCHITECTURE str OF apertif_unb1_correlator IS
-- Firmware version x.y
- CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 1);
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 2);
-- Enable block generators
CONSTANT c_use_bg : BOOLEAN := g_sim;
@@ -148,7 +144,7 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
CONSTANT c_use_complex : BOOLEAN := TRUE;
-- Correlator
- CONSTANT c_nof_inputs : NATURAL := sel_a_b(g_sim, 24, 24);
+ CONSTANT c_nof_inputs : NATURAL := 24;
CONSTANT c_nof_input_folds : NATURAL := 1;
CONSTANT c_nof_input_streams : NATURAL := c_nof_inputs / pow2(c_nof_input_folds);
CONSTANT c_nof_pre_mult_folds : NATURAL := 1;
@@ -196,7 +192,6 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
-- . The sync pulse is only there for the human eye (wave window) -
-- it is not used by the correlator.
CONSTANT c_bg_blocks_per_sync : NATURAL := largest(c_integration_period, c_nof_visibilities);
-
CONSTANT c_bg_ctrl : t_diag_block_gen := ('1', -- enable
'0', -- enable_sync
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
@@ -205,13 +200,7 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
-
- -- dp_offload_tx
--- CONSTANT c_usr_hdr_len : NATURAL := 20;
--- CONSTANT c_payload_len : NATURAL := (c_nof_visibilities*64) / c_byte_w + c_usr_hdr_len;
--- CONSTANT c_udp_total_len : NATURAL := c_network_udp_header_len+c_payload_len;
--- CONSTANT c_ip_total_len : NATURAL := c_network_ip_header_len+c_udp_total_len;
-
+ -- Block generator for visibility offload testing
CONSTANT c_offload_bg_ctrl : t_diag_block_gen := ('1', -- enable
'0', -- enable_sync
TO_UVEC( 300, c_diag_bg_samples_per_packet_w),
@@ -221,135 +210,133 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
TO_UVEC( 0, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
-- System
- SIGNAL cs_sim : STD_LOGIC;
- SIGNAL xo_clk : STD_LOGIC;
- SIGNAL xo_rst : STD_LOGIC;
- SIGNAL xo_rst_n : STD_LOGIC;
- SIGNAL mm_clk : STD_LOGIC;
- SIGNAL mm_locked : STD_LOGIC;
- SIGNAL mm_rst : STD_LOGIC;
-
- SIGNAL dp_rst : STD_LOGIC;
- SIGNAL dp_clk : STD_LOGIC;
- SIGNAL sa_rst : STD_LOGIC;
-
- -- PIOs
- SIGNAL pout_wdi : STD_LOGIC;
-
- -- MM WDI override
- SIGNAL reg_wdi_mosi : t_mem_mosi;
- SIGNAL reg_wdi_miso : t_mem_miso;
+ SIGNAL cs_sim : STD_LOGIC;
+ SIGNAL xo_clk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_locked : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC;
+ SIGNAL sa_rst : STD_LOGIC;
+
+ -- PIOs
+ SIGNAL pout_wdi : STD_LOGIC;
+
+ -- MM WDI override
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
-- MM PPSH
- SIGNAL reg_ppsh_mosi : t_mem_mosi;
- SIGNAL reg_ppsh_miso : t_mem_miso;
-
- -- MM UniBoard system info
- SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
- SIGNAL reg_unb_system_info_miso : t_mem_miso;
- SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
- SIGNAL rom_unb_system_info_miso : t_mem_miso;
-
- -- MM UniBoard I2C sens
- SIGNAL reg_unb_sens_mosi : t_mem_mosi;
- SIGNAL reg_unb_sens_miso : t_mem_miso;
-
- -- MM eth1g
- SIGNAL eth1g_tse_clk : STD_LOGIC;
- SIGNAL eth1g_mm_rst : STD_LOGIC;
- SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
- SIGNAL eth1g_tse_miso : t_mem_miso;
- SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
- SIGNAL eth1g_reg_miso : t_mem_miso;
- SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_ram_miso : t_mem_miso;
-
- -- MM DP offload RX
- SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
- SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+
+ -- MM UniBoard system info
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
+
+ -- MM UniBoard I2C sens
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+
+ -- MM eth1g
+ SIGNAL eth1g_tse_clk : STD_LOGIC;
+ SIGNAL eth1g_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_miso : t_mem_miso;
+
+ -- MM DP offload RX
+ SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
-- BSN monitors
- SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_miso : t_mem_miso;
+ SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
+ SIGNAL reg_bsn_monitor_miso : t_mem_miso;
-- MM Filterbank
- SIGNAL ram_fil_coefs_mosi : t_mem_mosi;
- SIGNAL ram_fil_coefs_miso : t_mem_miso;
+ SIGNAL ram_fil_coefs_mosi : t_mem_mosi;
+ SIGNAL ram_fil_coefs_miso : t_mem_miso;
- -- MM Databuffer
- SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
- SIGNAL ram_diag_data_buf_miso : t_mem_miso;
- SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
- SIGNAL reg_diag_data_buf_miso : t_mem_miso;
-
- -- MM 1GbE visibility offload TX
- SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
- SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
-
- -- Interface: 10GbE
- SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
- SIGNAL xaui_rx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
- SIGNAL unb_xaui_tx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_streams-1 DOWNTO 0);
- SIGNAL unb_xaui_rx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_streams-1 DOWNTO 0);
- SIGNAL mdio_mdc_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
- SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
- SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
- SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
- SIGNAL reg_tr_10GbE_miso : t_mem_miso;
- SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
- SIGNAL reg_tr_xaui_miso : t_mem_miso;
- SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
- SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+ -- MM Databuffer
+ SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_miso : t_mem_miso;
+ SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_miso : t_mem_miso;
+
+ -- MM 1GbE visibility offload TX
+ SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
+
+ -- Interface: 10GbE
+ SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL xaui_rx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL unb_xaui_tx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL unb_xaui_rx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdc_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_tr_10GbE_miso : t_mem_miso;
+ SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
+ SIGNAL reg_tr_xaui_miso : t_mem_miso;
+ SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+ SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
-- DP offload RX
- SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
- SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0);
- SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
- SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
- SIGNAL dp_offload_rx_restored_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
- SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+ SIGNAL dp_offload_rx_restored_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+ SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_10GbE_streams-1 DOWNTO 0);
-- BSN Aligner
- SIGNAL dp_fifo_fill_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0);
- SIGNAL dp_fifo_fill_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
- SIGNAL dp_bsn_align_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
- SIGNAL dp_bsn_align_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_fifo_fill_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_fifo_fill_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_bsn_align_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+ SIGNAL dp_bsn_align_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
-- BSN monitors
- SIGNAL dp_bsn_monitor_in_siso_arr : t_dp_siso_arr(c_nof_10GbE_streams+1+1-1 DOWNTO 0);
- SIGNAL dp_bsn_monitor_in_sosi_arr : t_dp_sosi_arr(c_nof_10GbE_streams+1+1-1 DOWNTO 0);
+ SIGNAL dp_bsn_monitor_in_siso_arr : t_dp_siso_arr(c_nof_10GbE_streams+1+1-1 DOWNTO 0);
+ SIGNAL dp_bsn_monitor_in_sosi_arr : t_dp_sosi_arr(c_nof_10GbE_streams+1+1-1 DOWNTO 0);
-- De and Reinterleaver
- SIGNAL dp_deinterleave_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_streams*c_nof_bf_modules-1 DOWNTO 0);
- SIGNAL dp_pipeline_snk_in : t_dp_sosi;
- SIGNAL interleaved_arr : t_dp_sosi_arr(c_nof_10GbE_streams*c_nof_bf_modules-1 DOWNTO 0);
- SIGNAL deinterleaved_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
- SIGNAL reinterleave_in_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
- SIGNAL reinterleave_out_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
+ SIGNAL dp_deinterleave_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_streams*c_nof_bf_modules-1 DOWNTO 0);
+ SIGNAL dp_pipeline_snk_in : t_dp_sosi;
+ SIGNAL interleaved_arr : t_dp_sosi_arr(c_nof_10GbE_streams*c_nof_bf_modules-1 DOWNTO 0);
+ SIGNAL deinterleaved_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
+ SIGNAL reinterleave_in_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
+ SIGNAL reinterleave_out_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
-- Filterbank and Correlator
- SIGNAL wpfb_snk_in_ctrl : t_dp_sosi;
- SIGNAL wpfb_snk_in_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
- SIGNAL wpfb_src_out_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
- SIGNAL correlator_src_out_arr : t_dp_sosi_arr(1-1 DOWNTO 0);
+ SIGNAL wpfb_snk_in_ctrl : t_dp_sosi;
+ SIGNAL wpfb_snk_in_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
+ SIGNAL wpfb_src_out_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
+ SIGNAL correlator_src_out_arr : t_dp_sosi_arr(1-1 DOWNTO 0);
-- 1GbE Visibility Offload
- SIGNAL dp_fifo_dc_mixed_widths_snk_in : t_dp_sosi;
-
- SIGNAL apertif_unb1_correlator_vis_offload_snk_in : t_dp_sosi;
- SIGNAL apertif_unb1_correlator_vis_offload_snk_out : t_dp_siso;
- SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(1-1 DOWNTO 0);
- SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(1-1 DOWNTO 0);
+ SIGNAL dp_fifo_dc_mixed_widths_snk_in : t_dp_sosi;
+ SIGNAL apertif_unb1_correlator_vis_offload_snk_in : t_dp_sosi;
+ SIGNAL apertif_unb1_correlator_vis_offload_snk_out : t_dp_siso;
+ SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(1-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(1-1 DOWNTO 0);
-- Mesh terminals
- SIGNAL tx_serial_2arr : t_unb1_board_mesh_sl_2arr;
- SIGNAL rx_serial_2arr : t_unb1_board_mesh_sl_2arr;
-
- SIGNAL mesh_tx_snk_out_2arr : t_unb1_board_mesh_siso_2arr;
- SIGNAL mesh_tx_snk_in_2arr : t_unb1_board_mesh_sosi_2arr;
- SIGNAL mesh_rx_src_in_2arr : t_unb1_board_mesh_siso_2arr;
- SIGNAL mesh_rx_src_out_2arr : t_unb1_board_mesh_sosi_2arr;
+ SIGNAL tx_serial_2arr : t_unb1_board_mesh_sl_2arr;
+ SIGNAL rx_serial_2arr : t_unb1_board_mesh_sl_2arr;
+ SIGNAL mesh_tx_snk_out_2arr : t_unb1_board_mesh_siso_2arr;
+ SIGNAL mesh_tx_snk_in_2arr : t_unb1_board_mesh_sosi_2arr;
+ SIGNAL mesh_rx_src_in_2arr : t_unb1_board_mesh_siso_2arr;
+ SIGNAL mesh_rx_src_out_2arr : t_unb1_board_mesh_sosi_2arr;
BEGIN
@@ -438,7 +425,7 @@ BEGIN
tr_ref_rst_156 => sa_rst,
-- Calibration & reconfig clock
- cal_rec_clk => mm_clk, --cal_clk, # required for XAUI
+ cal_rec_clk => mm_clk,
-- MM interface
mm_rst => mm_rst,
@@ -1019,33 +1006,6 @@ BEGIN
src_in => c_dp_siso_rdy
);
-
--- -----------------------------------------------------------------------------
--- -- Data buffer to be read out by Python
--- -----------------------------------------------------------------------------
--- u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
--- GENERIC MAP (
--- g_nof_streams => 1,
--- g_data_w => 64,
--- g_data_type => e_complex,
--- g_buf_nof_data => c_nof_visibilities,
--- g_buf_use_sync => TRUE
--- )
--- PORT MAP (
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
--- dp_rst => dp_rst,
--- dp_clk => dp_clk,
---
--- ram_data_buf_mosi => ram_diag_data_buf_mosi,
--- ram_data_buf_miso => ram_diag_data_buf_miso,
--- reg_data_buf_mosi => reg_diag_data_buf_mosi,
--- reg_data_buf_miso => reg_diag_data_buf_miso,
---
--- in_sync => correlator_src_out_arr(0).sop,
--- in_sosi_arr => correlator_src_out_arr
--- );
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -1151,75 +1111,75 @@ BEGIN
g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr
)
PORT MAP(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
-- PIOs
- pout_wdi => pout_wdi,
+ pout_wdi => pout_wdi,
-- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
-- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
-- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
-- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
-- 10 GbE
- reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
- reg_tr_10GbE_miso => reg_tr_10GbE_miso,
- reg_tr_xaui_mosi => reg_tr_xaui_mosi,
- reg_tr_xaui_miso => reg_tr_xaui_miso,
- reg_mdio_mosi_arr => reg_mdio_mosi_arr,
- reg_mdio_miso_arr => reg_mdio_miso_arr,
+ reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
+ reg_tr_10GbE_miso => reg_tr_10GbE_miso,
+ reg_tr_xaui_mosi => reg_tr_xaui_mosi,
+ reg_tr_xaui_miso => reg_tr_xaui_miso,
+ reg_mdio_mosi_arr => reg_mdio_mosi_arr,
+ reg_mdio_miso_arr => reg_mdio_miso_arr,
-- DP offload RX
reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-- . Data buffers
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-- 1GbE visibility offload TX
reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-- Filter coefficients
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
-- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso
);
END str;
--
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