diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd index 94e8ac4b04533e6903842abfba01a144d21f9ec6..62b37144b74daba6d0af1459165548e9a9713623 100644 --- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd +++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd @@ -67,13 +67,18 @@ USE wpfb_lib.wpfb_pkg.ALL; USE lofar2_sdp_lib.sdp_pkg.ALL; ENTITY tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload IS + GENERIC ( + -- Use g_try_xst_restart = TRUE to check hdr_input.integration_interval in sdp_statistics_offload.vhd, + -- default use FALSE for shorter simulation + g_try_xst_restart : BOOLEAN := FALSE + ); END tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload; ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload IS CONSTANT c_sim : BOOLEAN := TRUE; - CONSTANT c_unb_nr : NATURAL := 2; - CONSTANT c_node_nr : NATURAL := 1; + CONSTANT c_unb_nr : NATURAL := sel_a_b(g_try_xst_restart, 0, 2); + CONSTANT c_node_nr : NATURAL := sel_a_b(g_try_xst_restart, 0, 1); -- use node > 0 to check nof_cycles_dly in sdp_statistics_offload.vhd CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr * 4 + c_node_nr, 8); -- c_unb2c_board_nof_node = 4, c_unb2c_board_aux.id_w = 8 CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 0); @@ -318,6 +323,27 @@ BEGIN -- wait for udp offload is done proc_common_wait_until_high(ext_clk, eth_done); + ---------------------------------------------------------------------------- + -- XST processing re-enable + ---------------------------------------------------------------------------- + IF g_try_xst_restart THEN + -- XST processing disable + mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 0, tb_clk); + proc_common_wait_some_cycles(ext_clk, c_nof_clk_per_sync/2); + + -- Read current BSN + mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk); + mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk); + proc_common_wait_some_cycles(tb_clk, 1); + + -- XST processing enable + v_bsn := TO_UINT(current_bsn_wg) + 7; + mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, v_bsn, tb_clk); -- first write bsn low then bsn high part + mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- bsn high, assume v_bsn < 2**31-1 + mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); + proc_common_wait_some_cycles(ext_clk, c_nof_clk_per_sync * 4); + END IF; + --------------------------------------------------------------------------- -- End Simulation ---------------------------------------------------------------------------