diff --git a/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd b/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
index 1438e1e18791106b01d1839f74ccebf348d8944f..7db3f00098b616e1fa6c64a3ba1abe23702b8e31 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
@@ -28,8 +28,15 @@ USE dp_lib.dp_stream_pkg.ALL;
-- Purpose:
-- . Add SOP, EOP, BSN, SYNC and CHANNEL fields to correlator output.
-- Description:
--- . dp_block_gen generates the SOP, EOP, BSN and SYNC
--- . A clocked process adds the correct channel.
+-- . Frame length : g_nof_words_per_frame tagged by SOP..EOP.
+-- . Sync period : g_nof_channels * g_nof_words_per_frame
+-- . Channel index range : 0..g_nof_channels-1
+-- . BSN increment : Once every g_nof_channels
+-- . The above is implemented as follows:
+-- . dp_block_gen_sop_eop_sync generates the SOP, EOP and Sync
+-- . A clocked process adds:
+-- . channel based on SOP.
+-- . the BSN based on Sync.
ENTITY corr_output_framer IS
GENERIC (
@@ -50,17 +57,19 @@ END corr_output_framer;
ARCHITECTURE str OF corr_output_framer IS
- SIGNAL dp_block_gen_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
- SIGNAL channel_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
- SIGNAL nxt_channel_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+ SIGNAL dp_block_gen_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+ SIGNAL reg_dp_block_gen_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+
+ SIGNAL channel_bsn_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+ SIGNAL nxt_channel_bsn_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
BEGIN
-----------------------------------------------------------------------------
- -- Add SOP and EOP to mux output
+ -- dp_block_gen to create correc SOP,EOP and Sync
-----------------------------------------------------------------------------
- gen_dp_block_gen : FOR i IN 0 TO g_nof_inputs-1 GENERATE
- u_dp_block_gen: ENTITY dp_lib.dp_block_gen
+ gen_dp_block_gen_sop_eop_sync : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+ u_dp_block_gen_sop_eop_sync: ENTITY dp_lib.dp_block_gen
GENERIC MAP (
g_use_src_in => FALSE,
g_nof_data => g_nof_words_per_frame,
@@ -77,40 +86,53 @@ BEGIN
END GENERATE;
-----------------------------------------------------------------------------
- -- Assign the channel field
+ -- Create channel (based on SOP) and BSN (based on Sync)
-----------------------------------------------------------------------------
- p_channel : PROCESS(dp_block_gen_src_out_arr)
+ p_channel_bsn : PROCESS(dp_block_gen_src_out_arr)
BEGIN
FOR i IN 0 TO g_nof_inputs-1 LOOP
- nxt_channel_src_out_arr(i).channel <= channel_src_out_arr(i).channel;
- IF dp_block_gen_src_out_arr(i).eop='1' THEN
- IF channel_src_out_arr(i).channel = TO_DP_CHANNEL(g_nof_channels-1) THEN
- nxt_channel_src_out_arr(i).channel <= TO_DP_CHANNEL(0);
+ nxt_channel_bsn_src_out_arr(i).channel <= channel_bsn_src_out_arr(i).channel;
+ nxt_channel_bsn_src_out_arr(i).bsn <= channel_bsn_src_out_arr(i).bsn;
+ -- Channel
+ IF dp_block_gen_src_out_arr(i).sop='1' THEN
+ IF channel_bsn_src_out_arr(i).channel = TO_DP_CHANNEL(g_nof_channels-1) THEN
+ nxt_channel_bsn_src_out_arr(i).channel <= TO_DP_CHANNEL(0);
ELSE
- nxt_channel_src_out_arr(i).channel <= INCR_UVEC(channel_src_out_arr(i).channel, 1);
+ nxt_channel_bsn_src_out_arr(i).channel <= INCR_UVEC(channel_bsn_src_out_arr(i).channel, 1);
END IF;
END IF;
+ -- BSN
+ IF dp_block_gen_src_out_arr(i).sync='1' THEN
+ nxt_channel_bsn_src_out_arr(i).bsn <= INCR_UVEC(channel_bsn_src_out_arr(i).bsn, 1);
+ END IF;
END LOOP;
END PROCESS;
- -- Registers
+ -- Registers: also register dp_block_gen_src_out_arr to align it with p_channel_bsn outputs
p_clk: PROCESS(clk, rst)
BEGIN
IF rst='1' THEN
- channel_src_out_arr <= (OTHERS=>c_dp_sosi_rst);
+ channel_bsn_src_out_arr <= (OTHERS=>c_dp_sosi_rst);
+ reg_dp_block_gen_src_out_arr <= (OTHERS=>c_dp_sosi_rst);
+ FOR i IN 0 TO g_nof_inputs-1 LOOP
+ channel_bsn_src_out_arr(i).channel <= X"FFFFFFFF"; -- Wrap to 0 on first increment
+ channel_bsn_src_out_arr(i).bsn <= X"FFFFFFFF_FFFFFFFF"; -- Wrap to 0 on first increment
+ END LOOP;
ELSIF rising_edge(clk) THEN
- channel_src_out_arr <= nxt_channel_src_out_arr;
+ channel_bsn_src_out_arr <= nxt_channel_bsn_src_out_arr;
+ reg_dp_block_gen_src_out_arr <= dp_block_gen_src_out_arr;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
- -- Add channel field to dp_block_gen_src_out_arr and forward to snk_out_arr
+ -- Add channel,bsn fields to reg_dp_block_gen_src_out_arr and forward to src_out_arr
-----------------------------------------------------------------------------
- p_wires : PROCESS(dp_block_gen_src_out_arr, channel_src_out_arr)
+ p_wires : PROCESS(reg_dp_block_gen_src_out_arr, channel_bsn_src_out_arr)
BEGIN
- src_out_arr <= dp_block_gen_src_out_arr;
+ src_out_arr <= reg_dp_block_gen_src_out_arr;
FOR i IN 0 TO g_nof_inputs-1 LOOP
- src_out_arr(i).channel <= channel_src_out_arr(i).channel;
+ src_out_arr(i).channel <= channel_bsn_src_out_arr(i).channel;
+ src_out_arr(i).bsn <= channel_bsn_src_out_arr(i).bsn;
END LOOP;
END PROCESS;