diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
index 64bac09ec83470590b82bfef651030ab49b01993..55759f9e72963967b0cac718f0af9d1d69eb2834 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
@@ -1,25 +1,24 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2015
+-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
-------------------------------------------------------------------------------
+
LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
@@ -76,14 +75,14 @@ ENTITY lofar2_unb2b_adc_full IS
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
- JESD204B_SYNC : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
);
END lofar2_unb2b_adc_full;
ARCHITECTURE str OF lofar2_unb2b_adc_full IS
SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
- SIGNAL jesd204b_sync_arr : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
@@ -103,7 +102,7 @@ BEGIN
JESD204B_SERIAL_DATA(9) <= '0';
JESD204B_SERIAL_DATA(10) <= '0';
JESD204B_SERIAL_DATA(11) <= '0';
- JESD204B_SYNC(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+ JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
@@ -152,6 +151,6 @@ BEGIN
-- jesd204b syncronization signals
JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC => jesd204b_sync_arr
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
);
END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
index db3b93892959ce06d7c4d62761b3aceca67d1daa..f2a51e01f0cb82287b2ac7649359cff34842cc91 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
@@ -1,25 +1,24 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2018
+-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
-------------------------------------------------------------------------------
+
-- Author: Jonathan Hargreaves
-- Purpose: Tb to show that lofar2_unb2b_adc_full can simulate
-- Description:
@@ -82,7 +81,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_adc_full IS
-- jesd204b syncronization signals
SIGNAL jesd204b_sysref : STD_LOGIC;
- SIGNAL jesd204b_sync : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
BEGIN
@@ -153,7 +152,7 @@ BEGIN
-- jesd204b syncronization signals
JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC => jesd204b_sync
+ JESD204B_SYNC_N => jesd204b_sync_n
);
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
index 6cab5a830ddee67eb9792ef8aa440fbc4cb3bf29..b83353547a833585b17f17381fcb01019fdbfa06 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
@@ -1,24 +1,23 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2015
+-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------\
+
LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -76,7 +75,7 @@ ENTITY lofar2_unb2b_adc_one_node IS
-- jesd204b syncronization signals (2 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
- JESD204B_SYNC : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
);
END lofar2_unb2b_adc_one_node;
@@ -84,7 +83,7 @@ END lofar2_unb2b_adc_one_node;
ARCHITECTURE str OF lofar2_unb2b_adc_one_node IS
SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
- SIGNAL jesd204b_sync_arr : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
BEGIN
@@ -103,7 +102,7 @@ BEGIN
JESD204B_SERIAL_DATA(9) <= '0';
JESD204B_SERIAL_DATA(10) <= '0';
JESD204B_SERIAL_DATA(11) <= '0';
- JESD204B_SYNC(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+ JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
GENERIC MAP (
@@ -151,6 +150,6 @@ BEGIN
-- jesd204b syncronization signals
JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC => jesd204b_sync_arr
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
);
END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
index ead898fe060cced8b372db29479362f9631a7b1c..05e205179d19289848f8ecfec9564aefcb632fa3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
@@ -1,22 +1,20 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2018
+-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
-------------------------------------------------------------------------------
@@ -82,7 +80,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_adc_one_node IS
-- jesd204b syncronization signals
SIGNAL jesd204b_sysref : STD_LOGIC;
- SIGNAL jesd204b_sync : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
BEGIN
@@ -153,7 +151,7 @@ BEGIN
-- jesd204b syncronization signals
JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC => jesd204b_sync
+ JESD204B_SYNC_N => jesd204b_sync_n
);
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index c01c9f2312af01f99e5c1c905925bdb90e7e0554..e9804142486e8b8942567ae8ea5a913163848140 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -1,25 +1,31 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2015
+-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
-------------------------------------------------------------------------------
+
+-- Author : J Hargreaves
+-- Purpose:
+-- Core design for Lofar2 ADC input stage
+-- Description:
+-- Unb2b version for lab testing
+-- Use revisions to select one_node or full versions
+
LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
@@ -84,7 +90,7 @@ ENTITY lofar2_unb2b_adc IS
-- jesd204b syncronization signals
JESD204B_SYSREF : IN STD_LOGIC;
- JESD204B_SYNC : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 DOWNTO 0)
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 DOWNTO 0)
);
END lofar2_unb2b_adc;
@@ -93,9 +99,7 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
-- Revision parameters
CONSTANT c_revision_select : t_lofar2_unb2b_adc_config := func_sel_revision_rec(g_design_name);
- CONSTANT c_nof_streams_jesd204b : NATURAL := c_revision_select.nof_streams_jesd204b; -- IP is set up for 12 streams
- CONSTANT c_nof_streams_db : NATURAL := c_revision_select.nof_streams_db; -- Streams of raw samples to record in db
- CONSTANT c_nof_streams_input : NATURAL := c_revision_select.nof_streams_input; -- Streams actually passed through for processing
+ CONSTANT c_nof_streams : NATURAL := c_revision_select.nof_streams_input; -- Streams actually passed through for processing
-- Firmware version x.y
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
@@ -223,7 +227,7 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
- SIGNAL alt_sosi_arr : t_dp_sosi_arr(c_nof_streams_input-1 DOWNTO 0);
+ SIGNAL alt_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
@@ -325,7 +329,10 @@ BEGIN
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
-
+
+ ram_scrap_mosi => c_mem_mosi_rst,
+ ram_scrap_miso => open,
+
-- FPGA pins
-- . General
CLK => CLK,
@@ -444,9 +451,7 @@ BEGIN
u_ait: ENTITY work.node_adc_input_and_timing
GENERIC MAP(
g_technology => g_technology,
- g_nof_streams_jesd204b => c_nof_streams_jesd204b,
- g_nof_streams_db => c_nof_streams_db,
- g_nof_streams_input => c_nof_streams_input,
+ g_nof_streams => c_nof_streams,
g_sim => g_sim
)
PORT MAP(
@@ -455,7 +460,6 @@ BEGIN
mm_rst => mm_rst,
dp_clk => dp_clk,
dp_rst => dp_rst,
--- dp_pps => dp_pps,
-- mm control buses
jesd204b_mosi => jesd204b_mosi,
@@ -486,10 +490,10 @@ BEGIN
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
-- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b-1 downto 0),
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
jesd204b_refclk => JESD204B_REFCLK,
jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync => JESD204B_SYNC,
+ jesd204b_sync_n => JESD204B_SYNC_N,
-- Streaming data output
out_sosi_arr => alt_sosi_arr
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 251cc2d600bfd1c9daf662ef653053cfaea5e93b..bb81eb227f4e016a3e2ab0b485cee91f1f8e81de 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -1,25 +1,31 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2015
+-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
-------------------------------------------------------------------------------
+-- Author : J Hargreaves
+-- Purpose:
+-- AIT - ADC (Jesd) receiver, input, timing and associated diagnostic blocks
+-- Description:
+-- Unb2b version for lab testing
+-- Contains all the signal processing blocks to receive and time the ADC input data
+-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
+
LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
@@ -36,45 +42,44 @@ ENTITY node_adc_input_and_timing IS
GENERIC (
g_technology : NATURAL := c_tech_arria10_e1sg;
g_buf_nof_data : NATURAL := 1024;
- g_nof_streams_jesd204b : NATURAL := 12; -- Fixed in IP
- g_nof_streams_db : NATURAL := 2; -- Only applied to input (raw jesd) data buffer
- g_nof_streams_input : NATURAL := 12;
- g_sim : BOOLEAN := FALSE --Overridden by TB
+ g_nof_streams : NATURAL := 12;
+ g_nof_sync_n : NATURAL := 4; -- Three ADCs per RCU share a sync
+ g_aduc_buffer_nof_symbols : NATURAL := 512; -- Default 512
+ g_sim : BOOLEAN := FALSE
);
PORT (
-- clocks and resets
- mm_clk : IN STD_LOGIC;
- mm_rst : IN STD_LOGIC;
- dp_clk : IN STD_LOGIC;
- dp_rst : IN STD_LOGIC;
--- dp_pps : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
-- mm control buses
-- JESD
- jesd204b_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- jesd204b_miso : OUT t_mem_miso := c_mem_miso_rst;
+ jesd204b_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ jesd204b_miso : OUT t_mem_miso := c_mem_miso_rst;
-- Shiftram (applies per-antenna delay)
- reg_dp_shiftram_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_shiftram_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_dp_shiftram_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_shiftram_miso : OUT t_mem_miso := c_mem_miso_rst;
-- bsn source
- reg_bsn_source_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_source_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_source_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_source_miso : OUT t_mem_miso := c_mem_miso_rst;
-- bsn scheduler
- reg_bsn_scheduler_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_scheduler_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_scheduler_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_scheduler_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
-- WG
- reg_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
- ram_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
-- BSN MONITOR
- reg_bsn_monitor_input_mosi : IN t_mem_mosi;
- reg_bsn_monitor_input_miso : OUT t_mem_miso;
+ reg_bsn_monitor_input_mosi : IN t_mem_mosi;
+ reg_bsn_monitor_input_miso : OUT t_mem_miso;
-- Data buffer for raw samples
ram_diag_data_buf_jesd_mosi : IN t_mem_mosi;
@@ -98,10 +103,10 @@ ENTITY node_adc_input_and_timing IS
jesd204b_serial_data : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
jesd204b_refclk : IN STD_LOGIC;
jesd204b_sysref : IN STD_LOGIC;
- jesd204b_sync : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+ jesd204b_sync_n : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
-- Streaming data output
- out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams_input-1 DOWNTO 0)
+ out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)
);
END node_adc_input_and_timing;
@@ -114,14 +119,17 @@ ARCHITECTURE str OF node_adc_input_and_timing IS
CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS
+ CONSTANT c_nof_streams_jesd204b : NATURAL := 12; -- IP is set up for 12 streams
+ CONSTANT c_nof_streams_db : NATURAL := 2; -- Streams of raw samples to record in db
+
-- Waveform Generator
CONSTANT c_wg_buf_directory : STRING := "data/";
CONSTANT c_wg_buf_dat_w : NATURAL := c_unb2b_board_peripherals_mm_reg_default.ram_diag_wg_dat_w;
CONSTANT c_wg_buf_addr_w : NATURAL := c_unb2b_board_peripherals_mm_reg_default.ram_diag_wg_adr_w;
- SIGNAL wg_out_ovr : STD_LOGIC_VECTOR(g_nof_streams_input-1 DOWNTO 0);
- SIGNAL wg_out_val : STD_LOGIC_VECTOR(g_nof_streams_input-1 DOWNTO 0);
- SIGNAL wg_out_data : STD_LOGIC_VECTOR(g_nof_streams_input*c_wg_buf_dat_w-1 DOWNTO 0);
- SIGNAL wg_out_sync : STD_LOGIC_VECTOR(g_nof_streams_input-1 DOWNTO 0);
+ SIGNAL wg_out_ovr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL wg_out_val : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL wg_out_data : STD_LOGIC_VECTOR(g_nof_streams*c_wg_buf_dat_w-1 DOWNTO 0);
+ SIGNAL wg_out_sync : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL trigger_wg : STD_LOGIC;
-- Frame parameters TBC
@@ -138,34 +146,32 @@ ARCHITECTURE str OF node_adc_input_and_timing IS
SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
-- JESD signals
- SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams_db-1 DOWNTO 0);
- SIGNAL jesd204b_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams_jesd204b-1 DOWNTO 0);
- SIGNAL rx_clk : STD_LOGIC; -- formerly jesd204b_frame_clk
- SIGNAL rx_rst : STD_LOGIC;
- SIGNAL rx_sysref : STD_LOGIC;
+ SIGNAL rx_clk : STD_LOGIC; -- formerly jesd204b_frame_clk
+ SIGNAL rx_rst : STD_LOGIC;
+ SIGNAL rx_sysref : STD_LOGIC;
-- Sosis and sosi arrays
+ SIGNAL rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL dp_shiftram_snk_in_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL ant_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(c_nof_streams_db-1 DOWNTO 0);
SIGNAL bs_sosi : t_dp_sosi;
- SIGNAL wg_sosi_arr : t_dp_sosi_arr(g_nof_streams_input-1 DOWNTO 0);
- SIGNAL mux_sosi_arr : t_dp_sosi_arr(g_nof_streams_input-1 DOWNTO 0);
- SIGNAL rx_sosi_arr : t_dp_sosi_arr(g_nof_streams_input-1 DOWNTO 0);
- SIGNAL nxt_mux_sosi_arr : t_dp_sosi_arr(g_nof_streams_input-1 DOWNTO 0);
- SIGNAL ant_sosi_arr : t_dp_sosi_arr(g_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL wg_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL mux_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL nxt_mux_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL st_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
-------------------------------------------------------------------------------
-- DP sync checker / insert
-------------------------------------------------------------------------------
- CONSTANT c_nof_clk_per_blk : NATURAL := 1024;
- CONSTANT c_nof_blk_per_sync : NATURAL := 800000;
- CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_blk_per_sync * 256; -- = 800000 * 256
- CONSTANT c_bsn_sync_timeout : NATURAL := (c_nof_clk_per_sync * 10)/8; -- *10/8 as margin
-
-
+ CONSTANT c_nof_clk_per_blk : NATURAL := 1024;
+ CONSTANT c_nof_blk_per_sync : NATURAL := 800000;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_blk_per_sync * 256; -- = 800000 * 256
+ CONSTANT c_bsn_sync_timeout : NATURAL := (c_nof_clk_per_sync * 10)/8; -- *10/8 as margin
BEGIN
-
-----------------------------------------------------------------------------
-- JESD204B IP (ADC Handler)
-----------------------------------------------------------------------------
@@ -173,15 +179,15 @@ BEGIN
u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b
GENERIC MAP(
g_sim => g_sim,
- g_nof_channels => g_nof_streams_jesd204b,
- g_nof_syncs => g_nof_streams_jesd204b/3 -- Three ADCs per RCU share a sync
+ g_nof_streams => c_nof_streams_jesd204b,
+ g_nof_sync_n => g_nof_sync_n
)
PORT MAP(
jesd204b_refclk => JESD204B_REFCLK,
jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n_arr => JESD204B_SYNC,
+ jesd204b_sync_n_arr => jesd204b_sync_n,
- rx_src_out_arr => jesd204b_rx_src_out_arr,
+ rx_sosi_arr => rx_sosi_arr,
rx_clk => rx_clk,
rx_rst => rx_rst,
rx_sysref => rx_sysref,
@@ -195,13 +201,13 @@ BEGIN
-- Serial
serial_tx_arr => open,
- serial_rx_arr => JESD204B_SERIAL_DATA(g_nof_streams_jesd204b-1 downto 0)
+ serial_rx_arr => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b-1 downto 0)
);
- gen_jesd_mon_in : FOR i IN 0 TO g_nof_streams_db-1 GENERATE
- diag_data_buf_snk_in_arr(i).data(c_data_w-1 downto 0) <= jesd204b_rx_src_out_arr(i).data(c_data_w-1 downto 0);
- diag_data_buf_snk_in_arr(i).valid <= jesd204b_rx_src_out_arr(i).valid;
+ gen_jesd_mon_in : FOR i IN 0 TO c_nof_streams_db-1 GENERATE
+ diag_data_buf_snk_in_arr(i).data(c_data_w-1 downto 0) <= rx_sosi_arr(i).data(c_data_w-1 downto 0);
+ diag_data_buf_snk_in_arr(i).valid <= rx_sosi_arr(i).valid;
diag_data_buf_snk_in_arr(i).sop <= '0';
diag_data_buf_snk_in_arr(i).eop <= '0';
diag_data_buf_snk_in_arr(i).err <= (OTHERS=>'0');
@@ -210,16 +216,16 @@ BEGIN
-----------------------------------------------------------------------------
-- Diagnostic Data Buffer (Records 8192 raw ADC samples after the PPS)
+ -- ToDo: Remove this JESD DB when the second (BSN) data buffer is working correctly
-----------------------------------------------------------------------------
u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_technology => g_technology,
- g_nof_streams => g_nof_streams_db,
+ g_nof_streams => c_nof_streams_db,
g_data_w => c_data_w,
g_buf_nof_data => 8192,
- g_buf_use_sync => TRUE, -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- g_use_rx_seq => FALSE
+ g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
)
PORT MAP (
mm_rst => mm_rst,
@@ -240,12 +246,21 @@ BEGIN
-- Time delay: dp_shiftram
-- . copied from unb1_bn_capture_input (apertif)
-- Array range reversal is not done because everything is DOWNTO
- -- . TODO: Check if the sync is needed.
+ -- . the input valid is always '1', even when there is no data
-----------------------------------------------------------------------------
+
+ gen_force_valid : FOR I IN 0 TO c_nof_streams_jesd204b-1 GENERATE
+ p_sosi : PROCESS(rx_sosi_arr)
+ BEGIN
+ dp_shiftram_snk_in_arr(I) <= rx_sosi_arr(I);
+ dp_shiftram_snk_in_arr(I).valid <= '1';
+ END PROCESS;
+ END GENERATE;
+
u_dp_shiftram : ENTITY dp_lib.dp_shiftram
GENERIC MAP (
- g_nof_streams => g_nof_streams_jesd204b,
+ g_nof_streams => c_nof_streams_jesd204b,
g_nof_words => c_dp_shiftram_nof_samples,
g_data_w => c_data_w,
g_use_sync_in => TRUE
@@ -262,7 +277,7 @@ BEGIN
reg_mosi => reg_dp_shiftram_mosi,
reg_miso => reg_dp_shiftram_miso,
- snk_in_arr => jesd204b_rx_src_out_arr,
+ snk_in_arr => dp_shiftram_snk_in_arr,
src_out_arr => ant_sosi_arr
);
@@ -319,11 +334,9 @@ BEGIN
-- WG (Test Signal Generator)
-----------------------------------------------------------------------------
- -- TODO: remove commented lines once the array version is working
-
- u_sp : ENTITY diag_lib.mms_diag_wg_wideband_arr
+ u_wg_arr : ENTITY diag_lib.mms_diag_wg_wideband_arr
GENERIC MAP (
- g_nof_streams => g_nof_streams_input,
+ g_nof_streams => g_nof_streams,
g_cross_clock_domain => TRUE,
g_buf_dir => c_wg_buf_directory,
@@ -354,57 +367,36 @@ BEGIN
st_restart => trigger_wg,
out_sosi_arr => wg_sosi_arr
--- out_ovr_arr => wg_out_ovr(I downto I),
--- out_val_arr => wg_out_val(I downto I),
--- out_dat_arr => wg_out_data((I+1)*c_wg_buf_dat_w-1 downto I*c_wg_buf_dat_w),
--- out_syn_arr => wg_out_sync(I downto I)
);
--- gen_wg : FOR I IN 0 TO g_nof_streams-1 GENERATE
--- wg_sosi_arr(I).err(0) <= wg_out_ovr(I);
--- wg_sosi_arr(I).valid <= wg_out_val(I);
--- wg_sosi_arr(I).data(c_wg_buf_dat_w-1 downto 0) <= wg_out_data((I+1)*c_wg_buf_dat_w-1 downto I*c_wg_buf_dat_w);
--- wg_sosi_arr(I).sync <= wg_out_sync(I);
--- end generate;
-
-----------------------------------------------------------------------------
-- ADC/WG Mux (Input Select)
-----------------------------------------------------------------------------
- gen_mux : FOR I IN 0 TO g_nof_streams_input-1 GENERATE
+ gen_mux : FOR I IN 0 TO g_nof_streams-1 GENERATE
p_sosi : PROCESS(ant_sosi_arr(I), wg_sosi_arr(I))
BEGIN
- -- Valid is forced to '1' here for dp_shiftram.
- -- nxt_mux_sosi_arr(I).valid <= '1';
-
-- Default use the ADC data
nxt_mux_sosi_arr(I).data <= ant_sosi_arr(I).data;
IF wg_sosi_arr(I).valid='1' THEN
-- Valid WG data overrules ADC data
- -- nxt_mux_sosi_arr(I).data <= wg_sosi_arr(I).data;
+ nxt_mux_sosi_arr(I).data <= wg_sosi_arr(I).data;
END IF;
END PROCESS;
END GENERATE;
- p_reg_mux : PROCESS(rx_rst, rx_clk)
- BEGIN
- IF rx_rst='1' THEN
- mux_sosi_arr <= (OTHERS=>c_dp_sosi_rst);
- ELSIF rising_edge(rx_clk) THEN
- mux_sosi_arr <= nxt_mux_sosi_arr;
- END IF;
- END PROCESS;
+ mux_sosi_arr <= nxt_mux_sosi_arr WHEN rising_edge(rx_clk);
-----------------------------------------------------------------------------
-- Concatenate muxed data streams with bsn framing
-----------------------------------------------------------------------------
- gen_concat : FOR I IN 0 TO g_nof_streams_input-1 GENERATE
- p_sosi : PROCESS(mux_sosi_arr, bs_sosi)
+ gen_concat : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ p_sosi : PROCESS(mux_sosi_arr(I), bs_sosi)
BEGIN
- rx_sosi_arr(I) <= bs_sosi;
- rx_sosi_arr(I).data <= mux_sosi_arr(I).data;
+ st_sosi_arr(I) <= bs_sosi;
+ st_sosi_arr(I).data <= mux_sosi_arr(I).data;
END PROCESS;
END GENERATE;
@@ -422,7 +414,7 @@ BEGIN
---------------------------------------------------------------------------------------
u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
GENERIC MAP (
- g_nof_streams => g_nof_streams_input,
+ g_nof_streams => 1, -- They're all the same
g_sync_timeout => c_bsn_sync_timeout,
g_bsn_w => c_bs_bsn_w,
g_log_first_bsn => FALSE
@@ -438,23 +430,22 @@ BEGIN
dp_rst => rx_rst,
dp_clk => rx_clk,
in_siso_arr => (OTHERS=>c_dp_siso_rdy),
- in_sosi_arr => rx_sosi_arr
+ in_sosi_arr => st_sosi_arr(0 downto 0)
);
-----------------------------------------------------------------------------
-- Monitor ADU/WG output
- -- .ToDo: Check the parameters
-----------------------------------------------------------------------------
u_aduh_monitor : ENTITY aduh_lib.mms_aduh_monitor_arr
GENERIC MAP (
g_cross_clock_domain => TRUE,
- g_nof_streams => g_nof_streams_input,
+ g_nof_streams => g_nof_streams,
g_symbol_w => c_data_w, --TBD 16?
- g_nof_symbols_per_data => 1, --TBD
- g_nof_accumulations => 1024, --TBD integration time in symbols, defines internal accumulator widths
- g_buffer_nof_symbols => 512, --TBD
- g_buffer_use_sync => TRUE --TBD
+ g_nof_symbols_per_data => 1, -- Wideband factor is 1
+ g_nof_accumulations => 200000512, -- = 195313 blocks * 1024 samples
+ g_buffer_nof_symbols => g_aduc_buffer_nof_symbols, -- default 512, larger for full design
+ g_buffer_use_sync => TRUE -- True to capture all streams synchronously
)
PORT MAP (
-- Memory-mapped clock domain
@@ -470,7 +461,7 @@ BEGIN
st_rst => rx_rst,
st_clk => rx_clk,
- in_sosi_arr => rx_sosi_arr
+ in_sosi_arr => st_sosi_arr
);
@@ -481,11 +472,10 @@ BEGIN
u_diag_data_buffer_bsn : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_technology => g_technology,
- g_nof_streams => g_nof_streams_input,
+ g_nof_streams => g_nof_streams,
g_data_w => c_data_w,
g_buf_nof_data => g_buf_nof_data,
- g_buf_use_sync => TRUE, -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- g_use_rx_seq => FALSE
+ g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
)
PORT MAP (
mm_rst => mm_rst,
@@ -498,8 +488,8 @@ BEGIN
reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
- in_sosi_arr => rx_sosi_arr,
- in_sync => rx_sosi_arr(0).sync
+ in_sosi_arr => st_sosi_arr,
+ in_sync => st_sosi_arr(0).sync
);
@@ -508,25 +498,24 @@ BEGIN
-- . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain
-----------------------------------------------------------------------------
- gen_fifo_dc : FOR I IN 0 TO g_nof_streams_input-1 GENERATE
- u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
- GENERIC MAP (
- g_data_w => c_data_w,
- g_use_empty => FALSE, --TRUE,
- g_use_ctrl => TRUE,
- g_use_sync => TRUE,
- g_use_bsn => TRUE,
- g_fifo_size => c_dp_fifo_dc_size
- )
- PORT MAP (
- wr_rst => rx_rst,
- wr_clk => rx_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
- snk_in => rx_sosi_arr(I),
- src_in => c_dp_siso_rdy,
- src_out => out_sosi_arr(I)
- );
+ gen_dp_fifo_dc : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
+ GENERIC MAP (
+ g_data_w => c_data_w,
+ g_use_empty => FALSE, --TRUE,
+ g_use_ctrl => TRUE,
+ g_use_sync => TRUE,
+ g_use_bsn => TRUE,
+ g_fifo_size => c_dp_fifo_dc_size
+ )
+ PORT MAP (
+ wr_rst => rx_rst,
+ wr_clk => rx_clk,
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+ snk_in => st_sosi_arr(I),
+ src_out => out_sosi_arr(I)
+ );
END GENERATE;
END str;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
index 1473990bcdc6999aa84659dd277c98ef50bcc8bb..13d16b18dedb8ae741667b8636f46ba29cfa48ee 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
@@ -82,7 +82,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_adc IS
-- jesd204b syncronization signals
SIGNAL jesd204b_sysref : STD_LOGIC;
- SIGNAL jesd204b_sync : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
BEGIN
@@ -155,7 +155,7 @@ BEGIN
-- jesd204b syncronization signals
JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC => jesd204b_sync
+ JESD204B_SYNC_N => jesd204b_sync_n
);
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
index 9e5882d78073aeb840fa9fef4f01aaf248e6aa38..69af78de2eb6f28f3442d8541a4feadb98093104 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
@@ -145,8 +145,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_adc_multichannel IS
SIGNAL jesd204b_sysref_adc : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL jesd204b_sysref_adc_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL jesd204b_sysref_adc_2 : STD_LOGIC_VECTOR(11 DOWNTO 0);
- SIGNAL jesd204b_sync_adc : STD_LOGIC_VECTOR(11 DOWNTO 0);
- SIGNAL jesd204b_sync_fpga : STD_LOGIC_VECTOR(11 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_adc : STD_LOGIC_VECTOR(11 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_fpga : STD_LOGIC_VECTOR(11 DOWNTO 0);
-- Test bench data
SIGNAL jesd204b_tx_link_data_arr : t_slv_32_arr(11 DOWNTO 0);
@@ -229,7 +229,7 @@ BEGIN
-- jesd204b syncronization signals
JESD204B_SYSREF => jesd204b_sysref_fpga,
- JESD204B_SYNC => jesd204b_sync_fpga
+ JESD204B_SYNC_N => jesd204b_sync_n_fpga
);
@@ -242,7 +242,7 @@ BEGIN
jesd204b_sysref_adc(i) <= transport jesd204b_sysref after c_delay_sysreftoadc_arr(i);
-- txlink_clk(i) <= jesd204b_sampclk_div2 after c_delay_sysreftoadc_arr(i);
bck_rx(i) <= transport serial_tx(i) after c_delay_data_arr(i);
- jesd204b_sync_adc(i) <= transport jesd204b_sync_fpga(i) after c_delay_data_arr(i);
+ jesd204b_sync_n_adc(i) <= transport jesd204b_sync_n_fpga(i) after c_delay_data_arr(i);
END GENERATE;
jesd204b_sampclk_fpga <= transport jesd204b_sampclk after c_delay_sysreftofpga;
@@ -292,7 +292,7 @@ BEGIN
jesd204_tx_link_ready => jesd204b_tx_link_ready(i), --out
mdev_sync_n => dev_sync_n(i), --in
pll_locked => pll_locked, --in
- sync_n => jesd204b_sync_adc(i), --in
+ sync_n => jesd204b_sync_n_adc(i), --in
tx_analogreset => tx_analogreset,
tx_bonding_clocks => tx_bonding_clocks,--: in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
tx_cal_busy => open,
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
index 6acbc2630e5c8a485a0f372534f21ed30551df3e..9932d6fdd66b202fafe9c2bbe8254107c5ec1c99 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
@@ -177,12 +177,12 @@ BEGIN
st_clk => st_clk,
st_restart => st_restart,
- st_ctrl => st_wg_ctrl_arr(I)
+ st_ctrl => st_wg_ctrl_arr(I),
- -- out_ovr => wg_ovr( (I+1)*g_wideband_factor -1 DOWNTO I*g_wideband_factor ),
- -- out_dat => wg_dat( (I+1)*g_wideband_factor*g_buf_dat_w-1 DOWNTO I*g_wideband_factor*g_buf_dat_w),
- -- out_val => wg_val( (I+1)*g_wideband_factor -1 DOWNTO I*g_wideband_factor ),
- -- out_sync => wg_sync((I+1)*g_wideband_factor -1 DOWNTO I*g_wideband_factor )
+ out_ovr => wg_ovr( (I+1)*g_wideband_factor -1 DOWNTO I*g_wideband_factor ),
+ out_dat => wg_dat( (I+1)*g_wideband_factor*g_buf_dat_w-1 DOWNTO I*g_wideband_factor*g_buf_dat_w),
+ out_val => wg_val( (I+1)*g_wideband_factor -1 DOWNTO I*g_wideband_factor ),
+ out_sync => wg_sync((I+1)*g_wideband_factor -1 DOWNTO I*g_wideband_factor )
);
-- wire the wg signals to sosi outputs
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
index c421daa4c7752c4da19427d7dc638c3a35b23422..d36166ae617efaf3d60c7c5214d84eb47d8120e5 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
@@ -62,7 +62,7 @@ ENTITY dp_fifo_dc IS
snk_out : OUT t_dp_siso;
snk_in : IN t_dp_sosi;
-- ST source
- src_in : IN t_dp_siso;
+ src_in : IN t_dp_siso := c_dp_siso_rdy;
src_out : OUT t_dp_sosi
);
END dp_fifo_dc;
diff --git a/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd b/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd
index 516dc62041935884510e48368c5c7de40e112ddf..b4d5586d2e6ce044aec9615e43bd97e7fc2d6c77 100644
--- a/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd
+++ b/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd
@@ -25,12 +25,9 @@ USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
--- Purpose : Monitor signal path statistics
+-- Purpose : Monitor signal path statistics (array version)
-- Description :
--- For one input signal path provide MM access to:
--- . ADC mean via reg_miso
--- . ADC power via reg_miso
--- . ADC data buffer via buf_miso
+-- Array wrapper to allow insatntiation of g_nof_streams channel ADUH
-- Remarks:
ENTITY mms_aduh_monitor_arr IS
@@ -72,10 +69,6 @@ ARCHITECTURE str OF mms_aduh_monitor_arr IS
SIGNAL buf_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL buf_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);
- -- Monitor outputs
- --SIGNAL mon_mean_sum : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0); -- use fixed 64 bit sum width
- --SIGNAL mon_power_sum : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0); -- use fixed 64 bit sum width
- --SIGNAL mon_sync : STD_LOGIC; -- at the mon_sync there are new mean_sum and pwr_sum statistics available
SIGNAL mon_mean_sum_arr : t_slv_64_arr(g_nof_streams-1 DOWNTO 0); -- use fixed 64 bit sum width
SIGNAL mon_power_sum_arr : t_slv_64_arr(g_nof_streams-1 DOWNTO 0); -- use fixed 64 bit sum width
SIGNAL mon_sync_arr : t_sl_arr(g_nof_streams-1 DOWNTO 0); -- at the mon_sync there are new mean_sum and pwr_sum statistics available
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
index 3de92111d3a77ab97db8a7b966c2a42b09119285..0299c5007222a2bcd0684eb28b4a37b6f572135f 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
@@ -2,8 +2,8 @@
hdl_lib_name = ip_arria10_e1sg_jesd204b
hdl_library_clause_name = ip_arria10_e1sg_jesd204b_lib
hdl_lib_uses_synth = technology tech_pll common dp
-# hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_180 ip_arria10_e1sg_altera_xcvr_reset_control_180
-hdl_lib_uses_sim =
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_180 ip_arria10_e1sg_altera_xcvr_reset_control_180
+# hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 5d4ad88b143ff990a756dfad8834293d63bb490f..2d2db8edf768156d7d85d81ccb6fb2a4a96b6c82 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -24,7 +24,8 @@
-- Purpose: Combine IP components needed to create a JESD204B interface
-- Initially supports RX_ONLY for receiving data from an ADC
-- Description
---
+-- Currently only 12 streams because of the 12 channel reset block
+-- The sync_n signals are gated together to form g_nof_sync_n outputs
--
--LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e1sg_jesd204b_rx, ip_arria10_e1sg_jesd204b_rx_reset_seq, ip_arria10_e1sg_jesd204b_rx_core_pll, ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
@@ -39,17 +40,18 @@ USE ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.ALL;
ENTITY ip_arria10_e1sg_jesd204b IS
GENERIC (
g_sim : BOOLEAN := FALSE;
- g_nof_channels : NATURAL := 1;
+ g_nof_streams : NATURAL := 1;
+ g_nof_sync_n : NATURAL := 1;
g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
);
PORT (
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
- rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- Parallel data out to fabric
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
rx_clk : OUT STD_LOGIC := '0'; -- Exported data clock (frame clock) to fabric
rx_rst : OUT STD_LOGIC := '0'; -- Exported reset on rx_clk domain
rx_sysref : OUT STD_LOGIC := '0'; -- Exported copy of sysref
@@ -62,8 +64,8 @@ ENTITY ip_arria10_e1sg_jesd204b IS
jesd204b_miso : OUT t_mem_miso;
-- Serial connections to transceiver pins
- serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- Not used for ADC
- serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- Not used for ADC
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0)
);
END ip_arria10_e1sg_jesd204b;
@@ -76,12 +78,13 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
CONSTANT c_jesd204b_rx_framer_data_w : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
CONSTANT c_jesd204b_rx_somf_w : NATURAL :=c_jesd204b_rx_data_w/8; -- One somf bit per octet
CONSTANT c_jesd204b_rx_framer_somf_w : NATURAL :=c_jesd204b_rx_somf_w/2; -- IP outputs two samples in parallel
+ CONSTANT c_nof_sync_n_per_group : NATURAL :=sel_a_b(g_nof_streams / g_nof_sync_n = 0, 1, g_nof_streams / g_nof_sync_n);
-- JESD204 control status registers
- SIGNAL jesd204b_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
- SIGNAL jesd204b_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
- SIGNAL reset_seq_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reset_seq_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL jesd204b_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL jesd204b_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL reset_seq_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reset_seq_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Clocks
SIGNAL rxframe_clk : STD_LOGIC;
@@ -89,24 +92,24 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL jesd204b_avs_clk : STD_LOGIC;
-- Reset and control signals
- SIGNAL dev_lane_aligned : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 1 bit, each interface channel has 1 lane
- SIGNAL rx_analogreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL rx_cal_busy_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL rx_digitalreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL rx_islockedtodata_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL dev_lane_aligned_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL rx_csr_lane_powerdown_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL xcvr_rst_ctrl_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL pll_reset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL xcvr_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS => '1');
- SIGNAL rx_avs_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL rxlink_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL rxframe_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL rx_avs_rst_n_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL rxlink_rst_n_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL rxframe_rst_n_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL f2_div1_cnt_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL dev_lane_aligned : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- 1 bit, each interface channel has 1 lane
+ SIGNAL rx_analogreset_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rx_cal_busy_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rx_digitalreset_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rx_islockedtodata_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL dev_lane_aligned_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rx_csr_lane_powerdown_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL xcvr_rst_ctrl_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL pll_reset_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL xcvr_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '1');
+ SIGNAL rx_avs_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rxlink_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rxframe_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rx_avs_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rxlink_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rxframe_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL f2_div1_cnt_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL core_pll_locked : STD_LOGIC;
SIGNAL core_pll_locked_reg : STD_LOGIC;
SIGNAL jesd204b_sysref_1 : STD_LOGIC;
@@ -115,9 +118,11 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL jesd204b_sysref_frameclk_2 : STD_LOGIC;
-- Data path
- SIGNAL jesd204b_rx_link_data_arr : STD_LOGIC_VECTOR(c_jesd204b_rx_data_w*g_nof_channels-1 DOWNTO 0);
- SIGNAL jesd204b_rx_link_valid_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL jesd204b_rx_somf_arr : STD_LOGIC_VECTOR(c_jesd204b_rx_somf_w*g_nof_channels-1 DOWNTO 0);
+ SIGNAL jesd204b_rx_link_data_arr : STD_LOGIC_VECTOR(c_jesd204b_rx_data_w*g_nof_streams-1 DOWNTO 0);
+ SIGNAL jesd204b_rx_link_valid_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL jesd204b_rx_somf_arr : STD_LOGIC_VECTOR(c_jesd204b_rx_somf_w*g_nof_streams-1 DOWNTO 0);
+
+ SIGNAL jesd204b_sync_n_internal_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Component declarations for the IP blocks
@@ -241,7 +246,7 @@ BEGIN
gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
- gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
-----------------------------------------------------------------------------
-- The JESD204 IP (rx only)
@@ -264,7 +269,7 @@ BEGIN
csr_rx_testmode => OPEN,
csr_s => OPEN,
dev_lane_aligned => dev_lane_aligned_arr(i),
- dev_sync_n => jesd204b_sync_n_arr(i),
+ dev_sync_n => jesd204b_sync_n_internal_arr(i),
jesd204_rx_avs_chipselect => '1', --jesd204b_mosi_arr(i).chipselect,
jesd204_rx_avs_address => jesd204b_mosi_arr(i).address(c_jesd204b_mm_addr_w-1 downto 0),
jesd204_rx_avs_read => jesd204b_mosi_arr(i).rd,
@@ -427,7 +432,7 @@ BEGIN
END PROCESS;
- -- Transceiver reset controller. Use g_nof_channels out of 12 channels. Receive only
+ -- Transceiver reset controller. Use g_nof_streams out of 12 channels. Receive only
-- Clock set to 100MHz (use mm_clk)
u_ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control : ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12
@@ -443,12 +448,20 @@ BEGIN
END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- Group the SYNC_N outputs
+ -----------------------------------------------------------------------------
+ gen_group_sync_n : FOR i IN 0 TO g_nof_sync_n-1 GENERATE
+ jesd204b_sync_n_arr(i) <= vector_and(jesd204b_sync_n_internal_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
+ END GENERATE;
+
-----------------------------------------------------------------------------
-- MM bus mux
-----------------------------------------------------------------------------
u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
GENERIC MAP (
- g_nof_mosi => g_nof_channels,
+ g_nof_mosi => g_nof_streams,
g_mult_addr_w => c_jesd204b_mm_addr_w
)
PORT MAP (
diff --git a/libraries/technology/jesd204b/hdllib.cfg b/libraries/technology/jesd204b/hdllib.cfg
index 622e2554b8ff8e95c0575a225af553ac3e376839..26c30b19cb5fbf3936010a78cb3a2aba00046c15 100644
--- a/libraries/technology/jesd204b/hdllib.cfg
+++ b/libraries/technology/jesd204b/hdllib.cfg
@@ -17,7 +17,7 @@ synth_files =
test_bench_files =
# tb_tech_jesd204b_pkg.vhd
-# tb_tech_jesd204b.vhd
+ tb_tech_jesd204b.vhd
# tb_tb_tech_jesd204b.vhd
regression_test_vhdl =
@@ -26,7 +26,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
-# wave_tb_tech_jesd204b.do .
+ wave_tb_tech_jesd204b.do .
[quartus_project_file]
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..500d94b4c885746cecaebe4c8ebaa976b52a1eea
--- /dev/null
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
@@ -0,0 +1,455 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author: J Hargreaves
+-- Purpose: Tb for tech_jesd204b IP
+-- Description:
+-- Includes 3 JESD transmit sources to test multichannel syncronization
+-- Relative delays between TX and RX channels can be varied by editing c_delay_*
+-- ToDo: Make a tb_tb to run several test cases automatically
+-- Usage:
+-- Load sim # check that design can load in vsim
+-- > as 3 # check that the hierarchy for g_design_name is complete (or use do wave_tb_tech_jesd204b.do)
+-- > run 120us # enough time to reset and syncronize the JESD IP
+
+LIBRARY IEEE, common_lib, ip_arria10_e1sg_jesd204b_lib, dp_lib; --, tech_jesd204b_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.ALL;
+
+ENTITY tb_tech_jesd204b IS
+END tb_tech_jesd204b;
+
+ARCHITECTURE tb OF tb_tech_jesd204b IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+
+ CONSTANT c_jesd204b_sampclk_period : TIME := 5 ns;
+ CONSTANT c_bondingclk_period : TIME := 10 ns;
+ CONSTANT c_sysref_period : NATURAL := 10000; -- number of sample clocks between sysref pulses
+
+ CONSTANT c_nof_jesd204b_tx : NATURAL := 3; -- number of jesd204b input sources to instantiate
+ CONSTANT c_nof_streams_jesd204b : NATURAL := 12; -- number of jesd204b receiver channels
+
+ -- Transport delays
+ TYPE t_time_arr IS ARRAY (0 TO c_nof_streams_jesd204b-1) OF TIME;
+ CONSTANT c_delay_data_arr : t_time_arr := (4000 ps,
+ 5000 ps,
+ 6000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps) ; -- transport delays tx to rx data
+ CONSTANT c_delay_sysreftoadc_arr : t_time_arr := (4000 ps,
+ 5000 ps,
+ 6000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps) ; -- transport delays clock source to adc(tx)
+ CONSTANT c_delay_sysreftofpga : TIME := 10200 ps;
+
+
+
+ -- clocks and resets for the jesd204b tx
+ SIGNAL txlink_clk : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
+ SIGNAL dev_sync_n : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
+ SIGNAL txphy_clk : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
+ SIGNAL mm_rst : STD_LOGIC;
+ SIGNAL avs_rst_n : STD_LOGIC;
+ SIGNAL txlink_rst_n : STD_LOGIC;
+ SIGNAL tx_analogreset : STD_LOGIC_VECTOR(0 downto 0);
+ SIGNAL tx_digitalreset : STD_LOGIC_VECTOR(0 downto 0);
+ SIGNAL tx_bonding_clocks : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
+ SIGNAL bonding_clock_0 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_1 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_2 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_3 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_4 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_5 : STD_LOGIC := '0';
+ SIGNAL pll_locked : STD_LOGIC_VECTOR(0 downto 0);
+
+ CONSTANT c_mm_clk_period : TIME := 20 ns;
+ SIGNAL mm_clk : STD_LOGIC := '0';
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+
+ -- mm control buses
+ -- JESD
+ SIGNAL jesd204b_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL jesd204b_miso : t_mem_miso := c_mem_miso_rst;
+
+ -- serial transceivers
+ SIGNAL serial_tx : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
+ SIGNAL bck_rx : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 downto 0) := (others => '0');
+
+ -- jesd204b syncronization signals and delayed copies
+ SIGNAL jesd204b_sysref : STD_LOGIC;
+ SIGNAL jesd204b_sampclk : STD_LOGIC := '0';
+ SIGNAL rx_clk : STD_LOGIC := '0';
+ SIGNAL rx_rst : STD_LOGIC := '0';
+ SIGNAL rx_sysref : STD_LOGIC := '0';
+ SIGNAL rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+
+ SIGNAL jesd204b_sampclk_fpga : STD_LOGIC := '1';
+ SIGNAL jesd204b_sampclk_adc : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL jesd204b_sysref_fpga : STD_LOGIC;
+ SIGNAL jesd204b_sysref_adc : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL jesd204b_sysref_adc_1 : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL jesd204b_sysref_adc_2 : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_adc : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_fpga : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+
+ -- Test bench data
+ SIGNAL jesd204b_tx_link_data_arr : t_slv_32_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL jesd204b_tx_link_valid : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL jesd204b_tx_link_ready : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL jesd204b_tx_frame_ready : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+
+ -- Diagnostic signals
+ SIGNAL avs_chipselect : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL avs_read : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL avs_readdata : t_slv_32_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL avs_address : t_slv_8_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+
+BEGIN
+
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ jesd204b_sampclk <= NOT jesd204b_sampclk AFTER c_jesd204b_sampclk_period/2; -- JESD sample clock (200MHz)
+ mm_clk <= not mm_clk after c_mm_clk_period/2;
+ mm_rst <= '1', '0' after 800 ns;
+
+
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_jesd204b: ENTITY work.tech_jesd204b
+ GENERIC MAP(
+ g_sim => c_sim,
+ g_nof_streams => c_nof_streams_jesd204b,
+ g_nof_sync_n => c_nof_streams_jesd204b -- Todo: Try three ADCs per RCU share a sync
+ )
+ PORT MAP(
+ jesd204b_refclk => jesd204b_sampclk_fpga,
+ jesd204b_sysref => jesd204b_sysref_fpga,
+ jesd204b_sync_n_arr => jesd204b_sync_n_fpga,
+
+ rx_sosi_arr => rx_sosi_arr,
+ rx_clk => rx_clk,
+ rx_rst => rx_rst,
+ rx_sysref => rx_sysref,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => bck_rx(c_nof_streams_jesd204b-1 downto 0)
+ );
+
+
+
+ -----------------------------------------------------------------------------
+ -- Transport
+ -----------------------------------------------------------------------------
+
+ gen_transport : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE
+ jesd204b_sampclk_adc(i) <= transport jesd204b_sampclk after c_delay_sysreftoadc_arr(i);
+ jesd204b_sysref_adc(i) <= transport jesd204b_sysref after c_delay_sysreftoadc_arr(i);
+-- txlink_clk(i) <= jesd204b_sampclk_div2 after c_delay_sysreftoadc_arr(i);
+ bck_rx(i) <= transport serial_tx(i) after c_delay_data_arr(i);
+ jesd204b_sync_n_adc(i) <= transport jesd204b_sync_n_fpga(i) after c_delay_data_arr(i);
+ END GENERATE;
+
+ jesd204b_sampclk_fpga <= transport jesd204b_sampclk after c_delay_sysreftofpga;
+ jesd204b_sysref_fpga <= transport jesd204b_sysref after c_delay_sysreftofpga;
+
+ -----------------------------------------------------------------------------
+ -- Use a jesd204b instance in TX-ONLY modeTransmit Only.
+ -----------------------------------------------------------------------------
+
+ gen_jesd204b_tx : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE
+ u_ip_arria10_e1sg_jesd204b_tx : ip_arria10_e1sg_jesd204b_tx
+ PORT MAP
+ (
+ csr_cf => OPEN,
+ csr_cs => OPEN,
+ csr_f => OPEN,
+ csr_hd => OPEN,
+ csr_k => OPEN,
+ csr_l => OPEN,
+ csr_lane_powerdown => open, --out
+ csr_m => OPEN,
+ csr_n => OPEN,
+ csr_np => OPEN,
+ csr_tx_testmode => OPEN,
+ csr_tx_testpattern_a => OPEN,
+ csr_tx_testpattern_b => OPEN,
+ csr_tx_testpattern_c => OPEN,
+ csr_tx_testpattern_d => OPEN,
+ csr_s => OPEN,
+ dev_sync_n => dev_sync_n(i), --out
+ jesd204_tx_avs_chipselect => avs_chipselect(i), --jesd204b_mosi_arr(i).chipselect,
+ jesd204_tx_avs_address => avs_address(i),
+ jesd204_tx_avs_read => avs_read(i),
+ jesd204_tx_avs_readdata => avs_readdata(i),
+ jesd204_tx_avs_waitrequest => open,
+ jesd204_tx_avs_write => '0',
+ jesd204_tx_avs_writedata => (others => '0'),
+ jesd204_tx_avs_clk => mm_clk,
+ jesd204_tx_avs_rst_n => avs_rst_n,
+ jesd204_tx_dlb_data => open, -- debug/loopback testing
+ jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
+ jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
+ jesd204_tx_frame_error => '0',
+ jesd204_tx_int => OPEN, -- Connected to status IO in example design
+ jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), --in
+ jesd204_tx_link_valid => jesd204b_tx_link_valid(i), --in
+ jesd204_tx_link_ready => jesd204b_tx_link_ready(i), --out
+ mdev_sync_n => dev_sync_n(i), --in
+ pll_locked => pll_locked, --in
+ sync_n => jesd204b_sync_n_adc(i), --in
+ tx_analogreset => tx_analogreset,
+ tx_bonding_clocks => tx_bonding_clocks,--: in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy => open,
+ tx_digitalreset => tx_digitalreset,
+ tx_serial_data => serial_tx(i downto i),
+ txlink_clk => txlink_clk(i),
+ txlink_rst_n_reset_n => txlink_rst_n,
+ txphy_clk => txphy_clk(i downto i),
+ somf => OPEN,
+ sysref => jesd204b_sysref_adc(i)
+ );
+
+ -- Generate test pattern at each ADC
+
+ proc_data : PROCESS (jesd204b_sampclk_adc(i), mm_rst)
+ VARIABLE data : INTEGER := 0;
+ VARIABLE even_sample : BOOLEAN := TRUE;
+ BEGIN
+ IF mm_rst = '1' THEN
+ jesd204b_tx_link_data_arr(i) <= (others => '0');
+ jesd204b_tx_link_valid(i) <= '0';
+ txlink_clk(i) <= '0';
+ data := 0;
+ even_sample := TRUE;
+ ELSE
+ IF rising_edge(jesd204b_sampclk_adc(i)) THEN
+ txlink_clk(i) <= not txlink_clk(i);
+ jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
+ jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
+ IF (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') THEN
+ data := 1000;
+ ELSIF (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') THEN
+ data := -1000;
+ ELSE
+ data := 0;
+ END IF;
+
+ -- Frame the data to 32 bits at half the rate
+ IF(jesd204b_tx_link_ready(i) = '0') THEN
+ even_sample := TRUE;
+ ELSE
+ even_sample := not even_sample;
+ END IF;
+ IF (even_sample = TRUE) THEN
+ jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(data, 16);
+ jesd204b_tx_link_valid(i) <= '0';
+ ELSE
+ jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16);
+ jesd204b_tx_link_valid(i) <= '1';
+ END IF;
+
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+
+ END GENERATE;
+
+
+ -----------------------------------------------------------------------------
+ -- Stimulii
+ -----------------------------------------------------------------------------
+
+ -- Clocks and resets
+ avs_rst_n <= '0', '1' after 23500 ns;
+ tx_analogreset(0) <= '1', '0' after 18500 ns;
+ tx_digitalreset(0) <= '1', '0' after 23000 ns;
+ txlink_rst_n <= '0', '1' after 25500 ns;
+ pll_locked(0) <= '0', '1' after 1000 ns;
+
+ bonding_clock_5 <= not bonding_clock_5 after 250 ps;
+ bonding_clock_4 <= not bonding_clock_4 after 250 ps;
+ bonding_clock_3 <= not bonding_clock_3 after 500 ps;
+ bonding_clock_2 <= not bonding_clock_2 after 500 ps;
+ bonding_clock_0 <= not bonding_clock_0 after 2500 ps;
+
+ bonding_clock_1_process : process
+ begin
+ bonding_clock_1 <= '0';
+ wait for 4000 ps;
+ bonding_clock_1 <= '1';
+ wait for 1000 ps;
+ end process;
+
+ tx_bonding_clocks(5) <= transport bonding_clock_5 after 4890 ps;
+ tx_bonding_clocks(4) <= transport bonding_clock_4 after 4640 ps;
+ tx_bonding_clocks(3) <= transport bonding_clock_3 after 4920 ps;
+ tx_bonding_clocks(2) <= transport bonding_clock_2 after 4930 ps;
+ tx_bonding_clocks(1) <= transport bonding_clock_1 after 7490 ps;
+ tx_bonding_clocks(0) <= transport bonding_clock_0 after 4000 ps;
+
+
+ -- clock source process
+
+ proc_sysref : PROCESS (jesd204b_sampclk, mm_rst)
+ VARIABLE count : NATURAL := 0;
+ BEGIN
+ IF mm_rst = '1' THEN
+ jesd204b_sysref <= '0';
+ count := 0;
+ ELSE
+ IF rising_edge(jesd204b_sampclk) THEN
+ IF (count = c_sysref_period-1) THEN
+ count := 0;
+ ELSE
+ count := count + 1;
+ END IF;
+
+ IF count > c_sysref_period-8 THEN
+ jesd204b_sysref <= '1';
+ ELSE
+ jesd204b_sysref <= '0';
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ ------------------------------------------------------------------------------
+ -- Diagnostics
+ ------------------------------------------------------------------------------
+ proc_read_avs_regs : PROCESS
+ BEGIN
+ wait for 100ns;
+ avs_address(0) <= (others => '0');
+ avs_chipselect(0) <= '0';
+ avs_read(0) <= '0';
+ wait until avs_rst_n = '1';
+ while true loop
+ wait until rising_edge(mm_clk);
+ avs_address(0) <= X"14"; -- dll control
+ avs_chipselect(0) <= '1';
+ avs_read(0) <= '1';
+ wait for c_mm_clk_period * 1;
+ wait until rising_edge(mm_clk);
+ avs_address(0) <= (others => '0');
+ avs_chipselect(0) <= '0';
+ avs_read(0) <= '0';
+ wait for c_mm_clk_period * 32;
+ wait until rising_edge(mm_clk);
+ avs_address(0) <= X"15"; -- syncn_sysref control
+ avs_chipselect(0) <= '1';
+ avs_read(0) <= '1';
+ wait for c_mm_clk_period * 1;
+ wait until rising_edge(mm_clk);
+ avs_address(0) <= (others => '0');
+ avs_chipselect(0) <= '0';
+ avs_read(0) <= '0';
+ wait for c_mm_clk_period * 32;
+ wait until rising_edge(mm_clk);
+
+ avs_address(0) <= X"18"; -- syncn_sysref control
+ avs_chipselect(0) <= '1';
+ avs_read(0) <= '1';
+ wait for c_mm_clk_period * 1;
+ wait until rising_edge(mm_clk);
+ avs_address(0) <= (others => '0');
+ avs_chipselect(0) <= '0';
+ avs_read(0) <= '0';
+ wait for c_mm_clk_period * 32;
+ wait until rising_edge(mm_clk);
+ avs_address(0) <= X"19"; -- syncn_sysref control
+ avs_chipselect(0) <= '1';
+ avs_read(0) <= '1';
+ wait for c_mm_clk_period * 1;
+ wait until rising_edge(mm_clk);
+ avs_address(0) <= (others => '0');
+ avs_chipselect(0) <= '0';
+ avs_read(0) <= '0';
+ wait for c_mm_clk_period * 32;
+ wait until rising_edge(mm_clk);
+
+ avs_address(0) <= X"20"; -- tx control0
+ avs_chipselect(0) <= '1';
+ avs_read(0) <= '1';
+ wait for c_mm_clk_period * 1;
+ wait until rising_edge(mm_clk);
+ avs_address(0) <= (others => '0');
+ avs_chipselect(0) <= '0';
+ avs_read(0) <= '0';
+ wait for c_mm_clk_period * 32;
+ wait until rising_edge(mm_clk);
+ avs_address(0) <= X"26"; -- tx control0
+ avs_chipselect(0) <= '1';
+ avs_read(0) <= '1';
+ wait for c_mm_clk_period * 1;
+ wait until rising_edge(mm_clk);
+ avs_address(0) <= (others => '0');
+ avs_chipselect(0) <= '0';
+ avs_read(0) <= '0';
+ wait for c_mm_clk_period * 32;
+ END LOOP;
+ END PROCESS;
+
+ ------------------------------------------------------------------------------
+ -- Simulation end
+ ------------------------------------------------------------------------------
+ --sim_done <= '0', '1' AFTER 1 us;
+ sim_done <= '0';
+
+ proc_common_stop_simulation(TRUE, jesd204b_sampclk, sim_done, tb_end);
+
+END tb;
diff --git a/libraries/technology/jesd204b/tech_jesd204b.vhd b/libraries/technology/jesd204b/tech_jesd204b.vhd
index bcb89a298aba34e03cd5bb2ae6c65b863540772e..ecf327e563b86d2f60d03bc027f321dde7deda78 100644
--- a/libraries/technology/jesd204b/tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b.vhd
@@ -21,7 +21,8 @@
--------------------------------------------------------------------------------
--- Purpose: Technology selecttion wrapper to instantiate
+-- Author : J Hargreaves
+-- Purpose: Technology selection wrapper to instantiate
-- JESD204b interface for ADCs and DACs
-- Description:
--
@@ -43,6 +44,7 @@
-- mac_mm
--
--
+-- ToDo: Change g_nof_channels to g_nof_streams in IP
LIBRARY IEEE, common_lib, dp_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -57,18 +59,18 @@ ENTITY tech_jesd204b IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_technology : NATURAL := c_tech_arria10_e1sg;
- g_nof_channels : NATURAL := 12;
- g_nof_syncs : NATURAL := 12;
+ g_nof_streams : NATURAL := 12;
+ g_nof_sync_n : NATURAL := 12;
g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
);
PORT (
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
- rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- Parallel data out to fabric
+ rx_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
rx_clk : OUT STD_LOGIC := '0'; -- Exported data clock (frame clock) to fabric
rx_rst : OUT STD_LOGIC := '0'; -- Exported reset on rx_clk domain
rx_sysref : OUT STD_LOGIC := '0'; -- Exported copy of sysref
@@ -81,8 +83,8 @@ ENTITY tech_jesd204b IS
jesd204b_miso : OUT t_mem_miso;
-- Serial connections to transceiver pins
- serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- Not used for ADC
- serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- Not used for ADC
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0)
);
END tech_jesd204b;
@@ -94,7 +96,8 @@ BEGIN
u0 : ENTITY work.tech_jesd204b_arria10_e1sg
GENERIC MAP(
g_sim => g_sim,
- g_nof_channels => g_nof_channels,
+ g_nof_streams => g_nof_streams,
+ g_nof_sync_n => g_nof_sync_n,
g_direction => g_direction
)
PORT MAP(
@@ -102,7 +105,7 @@ BEGIN
jesd204b_sysref => jesd204b_sysref,
jesd204b_sync_n_arr => jesd204b_sync_n_arr,
- rx_src_out_arr => rx_src_out_arr,
+ rx_src_out_arr => rx_sosi_arr,
rx_clk => rx_clk,
rx_rst => rx_rst,
rx_sysref => rx_sysref,
@@ -124,7 +127,8 @@ BEGIN
u0 : ENTITY work.tech_jesd204b_arria10_e2sg
GENERIC MAP(
g_sim => g_sim,
- g_nof_channels => g_nof_channels,
+ g_nof_streams => g_nof_streams,
+ g_nof_sync_n => g_nof_sync_n,
g_direction => g_direction
)
PORT MAP(
@@ -132,7 +136,7 @@ BEGIN
jesd204b_sysref => jesd204b_sysref,
jesd204b_sync_n_arr => jesd204b_sync_n_arr,
- rx_src_out_arr => rx_src_out_arr,
+ rx_src_out_arr => rx_sosi_arr,
rx_clk => rx_clk,
rx_rst => rx_rst,
rx_sysref => rx_sysref,
diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd
index dff76d852da2573726076e89eca2247d7d7fec7a..1880c76a8f7255763173ecbd2f1e24b8a9859533 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd
@@ -20,12 +20,11 @@
--
--------------------------------------------------------------------------------
-
+-- Author: J Hargreaves
-- Purpose: Wrapper for the Intel Arria 10 e1sg (unb2b, unb2c) tecnology version of the
-- JESD204b interface for ADCs and DACs
-- Description
---
---
+-- Current configuration supports 12 channels receive only
LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e1sg_jesd204b_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -38,17 +37,18 @@ USE work.tech_jesd204b_component_pkg.ALL;
ENTITY tech_jesd204b_arria10_e1sg IS
GENERIC (
g_sim : BOOLEAN := FALSE;
- g_nof_channels : NATURAL := 12;
+ g_nof_streams : NATURAL := 12;
+ g_nof_sync_n : NATURAL := 12;
g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
);
PORT (
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
- rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- Parallel data out to fabric
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
rx_clk : OUT STD_LOGIC := '0'; -- Exported data clock (frame clock) to fabric
rx_rst : OUT STD_LOGIC := '0'; -- Exported reset on rx_clk domain
rx_sysref : OUT STD_LOGIC := '0'; -- Exported copy of sysref
@@ -61,8 +61,8 @@ ENTITY tech_jesd204b_arria10_e1sg IS
jesd204b_miso : OUT t_mem_miso;
-- Serial connections to transceiver pins
- serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- Not used for ADC
- serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- Not used for ADC
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0)
);
END tech_jesd204b_arria10_e1sg;
@@ -73,7 +73,8 @@ BEGIN
u_ip_arria10_e1sg_jesd204b : ip_arria10_e1sg_jesd204b
GENERIC MAP(
g_sim => g_sim,
- g_nof_channels => g_nof_channels,
+ g_nof_streams => g_nof_streams,
+ g_nof_sync_n => g_nof_sync_n,
g_direction => g_direction
)
PORT MAP(
diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
index 438689ed6d366af326af978502046cb4c44c92d0..2ff054424354a47838c528b57443b32db290de37 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
@@ -38,17 +38,18 @@ USE work.tech_jesd204b_component_pkg.ALL;
ENTITY tech_jesd204b_arria10_e2sg IS
GENERIC (
g_sim : BOOLEAN := FALSE;
- g_nof_channels : NATURAL := 12;
+ g_nof_streams : NATURAL := 12;
+ g_nof_sync_n : NATURAL := 12;
g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
);
PORT (
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
- rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- Parallel data out to fabric
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
rx_clk : OUT STD_LOGIC := '0'; -- Exported data clock (frame clock) to fabric
rx_rst : OUT STD_LOGIC := '0'; -- Exported reset on rx_clk domain
rx_sysref : OUT STD_LOGIC := '0'; -- Exported copy of sysref
@@ -61,8 +62,8 @@ ENTITY tech_jesd204b_arria10_e2sg IS
jesd204b_miso : OUT t_mem_miso;
-- Serial connections to transceiver pins
- serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- Not used for ADC
- serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- Not used for ADC
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0)
);
END tech_jesd204b_arria10_e2sg;
@@ -73,7 +74,7 @@ BEGIN
u_ip_arria10_e2sg_jesd204b : ip_arria10_e2sg_jesd204b
GENERIC MAP(
g_sim => g_sim,
- g_nof_channels => g_nof_channels,
+ g_nof_streams => g_nof_streams,
g_direction => g_direction
)
PORT MAP(
diff --git a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
index 7576ecc81f0b784f8abead91d6dc65242eb462fa..3714caf7bd57edef58083f65160299fd1af8ce3a 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
@@ -38,17 +38,18 @@ PACKAGE tech_jesd204b_component_pkg IS
COMPONENT ip_arria10_e1sg_jesd204b IS
GENERIC (
g_sim : BOOLEAN := FALSE;
- g_nof_channels : NATURAL := 1;
+ g_nof_streams : NATURAL := 1;
+ g_nof_sync_n : NATURAL := 1;
g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
);
PORT (
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
- rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- Parallel data out to fabric
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
rx_clk : OUT STD_LOGIC := '0'; -- Exported data clock (frame clock) to fabric
rx_rst : OUT STD_LOGIC := '0'; -- Exported reset on rx_clk domain
rx_sysref : OUT STD_LOGIC := '0'; -- Exported copy of sysref
@@ -61,8 +62,8 @@ PACKAGE tech_jesd204b_component_pkg IS
jesd204b_miso : OUT t_mem_miso;
-- Serial connections to transceiver pins
- serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- Not used for ADC
- serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- Not used for ADC
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0)
);
END COMPONENT;
@@ -73,17 +74,18 @@ PACKAGE tech_jesd204b_component_pkg IS
COMPONENT ip_arria10_e2sg_jesd204b IS
GENERIC (
g_sim : BOOLEAN := FALSE;
- g_nof_channels : NATURAL := 1;
+ g_nof_streams : NATURAL := 1;
+ g_nof_sync_n : NATURAL := 1;
g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
);
PORT (
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
- rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- Parallel data out to fabric
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
rx_clk : OUT STD_LOGIC := '0'; -- Exported data clock (frame clock) to fabric
rx_rst : OUT STD_LOGIC := '0'; -- Exported reset on rx_clk domain
rx_sysref : OUT STD_LOGIC := '0'; -- Exported copy of sysref
@@ -96,8 +98,8 @@ PACKAGE tech_jesd204b_component_pkg IS
jesd204b_miso : OUT t_mem_miso;
-- Serial connections to transceiver pins
- serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- Not used for ADC
- serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- Not used for ADC
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0)
);
END COMPONENT;