From c501b581928e621c0a4a25856827443a0fa8f942 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 24 Nov 2022 13:26:51 +0100
Subject: [PATCH] Add dp_pipline_ready.
---
libraries/io/eth/src/vhdl/eth_tester_tx.vhd | 51 +++++++++++++++------
1 file changed, 36 insertions(+), 15 deletions(-)
diff --git a/libraries/io/eth/src/vhdl/eth_tester_tx.vhd b/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
index d1051404ea..0ee2539d16 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
@@ -82,6 +82,7 @@ ARCHITECTURE str OF eth_tester_tx IS
CONSTANT c_packet_sz_max : NATURAL := ceil_div(c_eth_tester_bg_block_len_max, c_word_sz);
CONSTANT c_fifo_fill : NATURAL := c_packet_sz_max * 11 / 10;
CONSTANT c_fifo_size : NATURAL := true_log_pow2(c_fifo_fill + c_packet_sz_max); -- = 8192
+ CONSTANT c_fifo_size_w : NATURAL := ceil_log2(c_fifo_size);
CONSTANT c_nof_total_counts : NATURAL := 1; -- one to count Tx packets
@@ -101,8 +102,10 @@ ARCHITECTURE str OF eth_tester_tx IS
SIGNAL tx_fifo_data : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL tx_fifo_siso : t_dp_siso;
SIGNAL tx_fifo_wr_ful : STD_LOGIC;
- SIGNAL tx_fifo_wr_usedw : STD_LOGIC_VECTOR(ceil_log2(c_fifo_size)-1 DOWNTO 0);
+ SIGNAL tx_fifo_wr_usedw : STD_LOGIC_VECTOR(c_fifo_size_w-1 DOWNTO 0);
SIGNAL i_tx_fifo_rd_emp : STD_LOGIC;
+ SIGNAL tx_offload_siso : t_dp_siso;
+ SIGNAL tx_offload_sosi : t_dp_sosi;
SIGNAL i_ref_sync : STD_LOGIC := '0';
SIGNAL in_strobe_arr : STD_LOGIC_VECTOR(c_nof_total_counts-1 DOWNTO 0);
@@ -159,9 +162,11 @@ BEGIN
-- BG block level flow control, needed in case BG settings result in eth bit
-- rate > 1 Gbps, to avoid u_tx_fifo overflow.
- p_bg_siso_xon : PROCESS(st_clk)
+ p_bg_siso_xon : PROCESS(st_rst, st_clk)
BEGIN
- IF rising_edge(st_clk) THEN
+ IF st_rst = '1' THEN
+ bg_siso.xon <= '1';
+ ELSIF rising_edge(st_clk) THEN
bg_siso.xon <= '1';
IF TO_UINT(tx_fifo_wr_usedw) > c_fifo_fill THEN
bg_siso.xon <= '0';
@@ -198,19 +203,19 @@ BEGIN
g_fifo_size => c_fifo_size
)
PORT MAP (
- wr_rst => st_rst,
- wr_clk => st_clk,
- rd_rst => st_rst,
- rd_clk => st_clk,
+ wr_rst => st_rst,
+ wr_clk => st_clk,
+ rd_rst => st_rst,
+ rd_clk => st_clk,
-- Monitor FIFO filling
- wr_ful => tx_fifo_wr_ful,
- wr_usedw => tx_fifo_wr_usedw,
- rd_emp => i_tx_fifo_rd_emp,
+ wr_ful => tx_fifo_wr_ful,
+ wr_usedw => tx_fifo_wr_usedw,
+ rd_emp => i_tx_fifo_rd_emp,
-- ST sink
- snk_in => tx_packed_sosi,
+ snk_in => tx_packed_sosi,
-- ST source
- src_in => tx_fifo_siso,
- src_out => tx_fifo_sosi
+ src_in => tx_fifo_siso,
+ src_out => tx_fifo_sosi
);
-------------------------------------------------------------------------------
@@ -295,8 +300,8 @@ BEGIN
snk_in_arr(0) => tx_fifo_sosi,
snk_out_arr(0) => tx_fifo_siso,
- src_out_arr(0) => i_tx_udp_sosi,
- src_in_arr(0) => tx_udp_siso,
+ src_out_arr(0) => tx_offload_sosi,
+ src_in_arr(0) => tx_offload_siso,
hdr_fields_in_arr(0) => hdr_fields_slv_in, -- hdr_fields_slv_in_arr(i) is considered valid @ snk_in_arr(i).sop
hdr_fields_out_arr(0) => hdr_fields_slv_tx
@@ -306,6 +311,22 @@ BEGIN
hdr_fields_rec_in <= func_eth_tester_map_header(hdr_fields_slv_in);
hdr_fields_rec_tx <= func_eth_tester_map_header(hdr_fields_slv_tx);
+
+ -------------------------------------------------------------------------------
+ -- dp_pipeline_ready to ease timing closure
+ -------------------------------------------------------------------------------
+ u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready
+ PORT MAP(
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => tx_offload_siso,
+ snk_in => tx_offload_sosi,
+ src_in => tx_udp_siso,
+ src_out => i_tx_udp_sosi
+ );
+
+
-------------------------------------------------------------------------------
-- Tx packet monitors
-------------------------------------------------------------------------------
--
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