From c43b6b30362075ac7a55faefbb346a3a65b28a4a Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Fri, 29 Jan 2016 09:51:18 +0000
Subject: [PATCH] Added mmm_conf stuff
---
.../oneclick/prestudy/components/mm_master.py | 50 +++++++++++++++++--
1 file changed, 45 insertions(+), 5 deletions(-)
diff --git a/tools/oneclick/prestudy/components/mm_master.py b/tools/oneclick/prestudy/components/mm_master.py
index aba551923c..99d96c44ec 100644
--- a/tools/oneclick/prestudy/components/mm_master.py
+++ b/tools/oneclick/prestudy/components/mm_master.py
@@ -87,21 +87,61 @@ QSYS_COMPONENT_DECLARATION_END = """
END COMPONENT QSYS_MM_MASTER;
"""
-class mm_master(Component):
+class mm_master(Entity):
"""
Create a complete MM master, by:
. Creating an MM-slave peripherals_list with the base address+span
. NOTE: QSYS only accepts base addresses that are a multiple of the span in bytes!
"""
- def __init__(self, slave_components):
- Component.__init__(self, name='mm_master')
-
+ def __init__(self, name, slave_components, synth_master = 'QSYS'):
+ Entity.__init__(self, name)
self.slave_components = slave_components
+ self.synth_master = 'QSYS'
+ self.mmmconfig = mmm_config.MmmConfig(mmmLibraryName = name)
+
+ # Create mmm_conf dictionary based on included slave components.
+ if self.slave_components != []: # Sub-components determine the contents of this generated file (e.g. top level)
+ for component in self.slave_components:
+ for registerSpan in component.mm_regs:
+ self.mmmconfig.add_peripheral(registerSpan)
+
+ for registerSpan in self.mmmconfig.peripherals:
+ print registerSpan
+
+ self.mmmconfig.add_input_clk('mm_clk')
+
+ # Add default generics
+ self.add_generic( "g_sim", "BOOLEAN", "FALSE")
+ self.add_generic( "g_sim_unb_nr", "NATURAL", "0")
+ self.add_generic( "g_sim_node_nr", "NATURAL", "0")
+
+ # Add input clks
+ if "mm_clk" in self.mmmconfig.input_clks:
+ self.add_port("mm_clk", "IN", "STD_LOGIC", "\'1\'")
+ self.add_port("mm_rst", "IN", "STD_LOGIC", "\'1\'")
+
+ # Add UNB1 board peripherals
+ for s in self.mmmconfig.peripherals:
+
+ # Extra signals for ethernet peripheral
+ if(s[0] == "eth1g_ram"):
+ #self.add_port("eth1g_tse_clk", "OUT", "STD_LOGIC")
+ self.add_port("eth1g_mm_rst", "OUT", "STD_LOGIC")
+ self.add_port("eth1g_reg_interrupt", "IN", "STD_LOGIC")
+
+ # Extra signal for Watchdog interface
+ if(s[0] == "reg_wdi"):
+ self.add_port("pout_wdi", "OUT", "STD_LOGIC", "\'1\'")
+
+ self.add_port(s[0] + "_mosi", "OUT", "t_mem_mosi")
+ self.add_port(s[0] + "_miso", "IN", "t_mem_miso", "c_mem_miso_rst")
+
+ print self.make_instantiation_string()
# Create a list of peripherals to pass to QSYS generator
peripheral_list = []
auto_base_address = 0x5000
- for slave_component in slave_components:
+ for slave_component in self.slave_components:
for mm_reg in slave_component.mm_regs:
name = mm_reg[0]
word_addr_w = mm_reg[1]
--
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