diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
index 88025f381b9a875bad50953545d0656c8e1ca0d9..6ff3fffd7c30bbae5b60df32b0fbebd6340306a9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
@@ -169,7 +169,6 @@ ARCHITECTURE str OF unb2b_jesd IS
   SIGNAL qsfp_red_led_arr           : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
 
   -- JESD signals
-  signal pll_locked : std_logic;
 
   signal jesd204_rx_link_error : std_logic;
   signal jesd204_rx_link_data  : std_logic_vector(31 downto 0);
@@ -304,9 +303,7 @@ BEGIN
     -- . 1GbE Control Interface
     ETH_clk                  => ETH_CLK,
     ETH_SGIN                 => ETH_SGIN,
-    ETH_SGOUT                => ETH_SGOUT,
-
-    pll_locked => pll_locked
+    ETH_SGOUT                => ETH_SGOUT
   );
 
   -----------------------------------------------------------------------------
@@ -398,7 +395,6 @@ BEGIN
     jesd204_device_clk       => st_clk
   );
 
-  QSFP_LED(0)          <= pll_locked;
   CLK                  <= jesd204_device_clk;
   --PPS                  <= jesd204_rx_sysref;
   jesd204_rx_sysref_n  <= NOT jesd204_rx_sysref;