diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 1938a563ddabd52f07caf86b92aea2801ab6b6cc..0c520a2e3185c5ab0facff2aa270f418e624ba7c 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -86,6 +86,7 @@ ARCHITECTURE str OF ddrctrl IS
CONSTANT c_io_ddr_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr );
CONSTANT c_wr_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
CONSTANT c_rd_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ CONSTANT c_rd_fifo_uw_w : NATURAL := ceil_log2(c_rd_fifo_depth*(func_tech_ddr_ctlr_data_w(g_tech_ddr)/c_io_ddr_data_w));
-- signals for connecting the components
SIGNAL ctrl_clk : STD_LOGIC;
@@ -99,7 +100,7 @@ ARCHITECTURE str OF ddrctrl IS
SIGNAL rd_siso : t_dp_siso := c_dp_siso_rst;
SIGNAL rd_sosi : t_dp_sosi := c_dp_sosi_init;
SIGNAL stop : STD_LOGIC;
- SIGNAL rd_fifo_usedw: STD_LOGIC_VECTOR(ceil_log2(c_rd_fifo_depth*(func_tech_ddr_ctlr_data_w(g_tech_ddr)/c_io_ddr_data_w) )-1 DOWNTO 0);
+ SIGNAL rd_fifo_usedw: STD_LOGIC_VECTOR(c_rd_fifo_uw_w-1 DOWNTO 0);
SIGNAL rd_ready : STD_LOGIC;
SIGNAL inp_ds : NATURAL;
SIGNAL inp_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
@@ -239,7 +240,11 @@ BEGIN
g_wr_data_w => c_io_ddr_data_w,
g_rd_fifo_depth => c_rd_fifo_depth,
g_rd_data_w => c_io_ddr_data_w,
+<<<<<<< HEAD
g_block_size => g_block_size
+=======
+ g_rd_fifo_uw_w => c_rd_fifo_uw_w
+>>>>>>> L2SDP-704
)
PORT MAP(
clk => clk,
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index a5e5acfbd1ded237123b95eaf8982c498156cb5e..8997d60756d42e26ea918a7138d19c6f09ae6dc0 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -45,7 +45,8 @@ ENTITY ddrctrl_controller IS
g_wr_data_w : NATURAL;
g_rd_fifo_depth : NATURAL;
g_rd_data_w : NATURAL;
- g_block_size : NATURAL
+ g_block_size : NATURAL;
+ g_rd_fifo_uw_w : NATURAL
);
PORT (
clk : IN STD_LOGIC;
@@ -63,7 +64,7 @@ ENTITY ddrctrl_controller IS
dvr_mosi : OUT t_mem_ctlr_mosi;
dvr_miso : IN t_mem_ctlr_miso;
wr_sosi : OUT t_dp_sosi;
- rd_fifo_usedw : IN STD_LOGIC_VECTOR(ceil_log2(g_rd_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr)/g_rd_data_w) )-1 DOWNTO 0);
+ rd_fifo_usedw : IN STD_LOGIC_VECTOR(g_rd_fifo_uw_w-1 DOWNTO 0);
-- ddrctrl_output
outp_ds : OUT NATURAL;
@@ -97,7 +98,7 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
-- state of program
state : t_state;
- -- stoppping signals
+ -- stopping signals
stop_adr : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
stopped : STD_LOGIC;
@@ -132,22 +133,11 @@ BEGIN
v := q_reg;
+
CASE q_reg.state IS
WHEN RESET =>
v := c_t_reg_init;
- IF rst = '1' THEN
- v.state := RESET;
- ELSIF stop_in = '1' THEN
- v.state := SET_STOP;
- ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
- v.state := STOP_WRITING;
- ELSIF v.stopped = '1' THEN
- v.state := IDLE;
- ELSE
- v.state := WRITING;
- END IF;
-
WHEN WRITING =>
-- if adr mod c_burstsize = 0
@@ -168,20 +158,6 @@ BEGIN
v.wr_sosi := inp_sosi;
-
- IF rst = '1' THEN
- v.state := RESET;
- ELSIF stop_in = '1' THEN
- v.state := SET_STOP;
- ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
- v.state := STOP_WRITING;
- ELSIF v.stopped = '1' THEN
- v.state := IDLE;
- ELSE
- v.state := WRITING;
- END IF;
-
-
WHEN SET_STOP =>
--setting a stop address dependend on the g_stop_percentage
IF inp_adr+c_pof_ma >= c_max_adr THEN
@@ -210,20 +186,6 @@ BEGIN
v.wr_sosi := inp_sosi;
-
- IF rst = '1' THEN
- v.state := RESET;
- ELSIF stop_in = '1' THEN
- v.state := SET_STOP;
- ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
- v.state := STOP_WRITING;
- ELSIF v.stopped = '1' THEN
- v.state := IDLE;
- ELSE
- v.state := WRITING;
- END IF;
-
-
WHEN STOP_WRITING =>
v.dvr_mosi.burstbegin := '0';
-- wait until the write burst is finished
@@ -237,11 +199,6 @@ BEGIN
END IF;
- IF rst = '1' THEN
- v.state := RESET;
- END IF;
-
-
WHEN START_READING =>
v.rd_burst_en := '1';
v.dvr_mosi.wr := '0';
@@ -255,15 +212,8 @@ BEGIN
v.outp_ds := v.outp_ds-c_rest;
END IF;
END LOOP;
-
v.outp_bsn := TO_UVEC(TO_UINT(inp_bsn), c_dp_stream_bsn_w); -- WRONG, wil be fixed after L2SDP-705, 706, 707 and 708
-
-
- IF rst = '1' THEN
- v.state := RESET;
- ELSE
- v.state := READING;
- END IF;
+ v.state := READING;
WHEN READING =>
@@ -286,9 +236,7 @@ BEGIN
v.rd_burst_en := '1';
END IF;
- IF rst = '1' THEN
- v.state := RESET;
- ELSIF q_reg.read_cnt >= c_max_read_cnt THEN
+ IF q_reg.read_cnt >= c_max_read_cnt THEN
v.state := IDLE;
ELSE
v.state := READING;
@@ -298,9 +246,17 @@ BEGIN
WHEN IDLE =>
-- the statemachine goes to Idle when its finished or when its waiting on other components.
- IF rst = '1' THEN
- v.state := RESET;
- ELSIF stop_in = '1' THEN
+
+
+ WHEN OTHERS =>
+ v := c_t_reg_init;
+
+
+ END CASE;
+
+
+ IF q_reg.state = RESET OR q_reg.state = WRITING OR q_reg.state = SET_STOP OR q_reg.state = IDLE THEN
+ IF stop_in = '1' THEN
v.state := SET_STOP;
ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
v.state := STOP_WRITING;
@@ -309,30 +265,13 @@ BEGIN
ELSE
v.state := WRITING;
END IF;
-
-
- WHEN OTHERS =>
- v := c_t_reg_init;
-
+ END IF;
IF rst = '1' THEN
v.state := RESET;
- ELSIF stop_in = '1' THEN
- v.state := SET_STOP;
- ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
- v.state := STOP_WRITING;
- ELSIF v.stopped = '1' THEN
- v.state := IDLE;
- ELSE
- v.state := WRITING;
END IF;
-
- END CASE;
-
-
-
d_reg <= v;
END PROCESS;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
index 2ce54ce663b334185e329d0bffcd609f9e2c5ef6..e9d65b74cac157e2fd16745315559fe73c76d7bc 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
@@ -115,9 +115,7 @@ BEGIN
END IF;
- IF rst = '1' THEN
- v.state := RESET;
- ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
+ IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
v.state := OVER_HALF;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
v.state := IDLE;
@@ -150,9 +148,7 @@ BEGIN
END IF;
- IF rst = '1' THEN
- v.state := RESET;
- ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
+ IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
v.state := OVER_HALF;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
v.state := IDLE;
@@ -178,9 +174,7 @@ BEGIN
END IF;
- IF rst = '1' THEN
- v.state := RESET;
- ELSIF v.dd_fresh = '1' THEN
+ IF v.dd_fresh = '1' THEN
v.state := SECOND_READ;
ELSE
v.state := IDLE;
@@ -203,9 +197,7 @@ BEGIN
END IF;
- IF rst = '1' THEN
- v.state := RESET;
- ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
+ IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
v.state := OVER_HALF;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
v.state := IDLE;
@@ -221,14 +213,9 @@ BEGIN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
v.dd_fresh := '1';
END IF;
+ v.state := OFF;
- IF rst = '1' THEN
- v.state := RESET;
- ELSE
- v.state := OFF;
- END IF;
-
WHEN IDLE =>
-- the statemachine goes to Idle when its finished or when its waiting on other components.
v.out_ready := '1';
@@ -240,9 +227,7 @@ BEGIN
END IF;
- IF rst = '1' THEN
- v.state := RESET;
- ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' AND q_reg.sr_done = '1' THEN
+ IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' AND q_reg.sr_done = '1' THEN
v.state := OVER_HALF;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' AND q_reg.sr_done = '0' THEN
v.state := SECOND_READ;
@@ -263,9 +248,7 @@ BEGIN
END IF;
- IF rst = '1' THEN
- v.state := RESET;
- ELSIF in_sosi.valid = '1' THEN
+ IF in_sosi.valid = '1' THEN
v.state := FIRST_READ;
ELSE
v.state := OFF;
@@ -275,6 +258,9 @@ BEGIN
END CASE;
+ IF rst = '1' THEN
+ v.state := RESET;
+ END IF;
d_reg <= v;
END PROCESS;