diff --git a/applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol.vhd b/applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol.vhd
index bb6763f0e6d81201b6db3a6b5f0045b715e264a7..ccb7810e59a5d0fae5bf1a31601896d78a075db0 100644
--- a/applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol.vhd
+++ b/applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol.vhd
@@ -346,6 +346,22 @@ BEGIN
-------------------------------------------------------------------------------
-- mm_master
-------------------------------------------------------------------------------
-A string that contains the mm_master VHDL instance
+ u_mm_master : ENTITY work.mm_master
+ GENERIC MAP (
+ g_sim => g_sim
+ )
+ PORT MAP(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ pout_wdi => pout_wdi,
+ bf_unit_ram_ss_ss_wide_mosi => bf_unit_ram_ss_ss_wide_mosi,
+ bf_unit_ram_ss_ss_wide_miso => bf_unit_ram_ss_ss_wide_miso,
+ bf_unit_ram_bf_weights_mosi => bf_unit_ram_bf_weights_mosi,
+ bf_unit_ram_bf_weights_miso => bf_unit_ram_bf_weights_miso,
+ bf_unit_ram_st_sst_mosi => bf_unit_ram_st_sst_mosi,
+ bf_unit_ram_st_sst_miso => bf_unit_ram_st_sst_miso,
+ bf_unit_reg_st_sst_mosi => bf_unit_reg_st_sst_mosi,
+ bf_unit_reg_st_sst_miso => bf_unit_reg_st_sst_miso
+ );
END str;
diff --git a/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg b/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg
index 1c6a8d64fd35def6e853b2d14c705d5029081db4..f31268d328492ef66b5ae2b4cfffe5b3947aa24f 100644
--- a/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg
+++ b/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
test_bench_files =
generated/tb_arts_unb1_sc1_bg_single_pol.vhd
quartus_copy_files =
- generated/qsys_mm_master.qsys .
+ qsys_mm_master.qsys .
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
@@ -17,4 +17,4 @@ quartus_sdc_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/arts_unb1_sc1_bg_single_pol/synthesis/qsys_mm_master.qip
quartus_tcl_files =
- generated/arts_unb1_sc1_bg_single_pol_pins.tcl
+ arts_unb1_sc1_bg_single_pol_pins.tcl