From c2e7f0e8ea997b4528ed2461f4270aa5a38f3617 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 8 Jan 2015 06:39:26 +0000
Subject: [PATCH] Clarified flushing mixed width FIFO.
---
.../ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd | 24 ++++++++++++-------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
index b2a84cb351..159b017dd3 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
@@ -32,6 +32,14 @@
-- . g_mode = "SYN" : start filling on next sync
--
-- . g_use_channel = TRUE : start filling when channel matches g_start_channel
+--
+-- Remarks:
+-- . The flushing does ensure that the write FIFO does not run full. If the
+-- write input FIFO is a mixed width FIFO with narrow write data, then it
+-- may not be possible to read the FIFO empty, because a wide data word
+-- can only be read when it is complete. Typically this behaviour is fine
+-- in applications, so no need to try to somehow flush an incomplete last
+-- wide word from the FIFO.
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -55,7 +63,7 @@ ENTITY io_ddr_driver_flush_ctrl IS
dvr_wr_flush_en : IN STD_LOGIC := '1';
dvr_wr_not_rd : IN STD_LOGIC;
- wr_sosi : IN t_dp_sosi;
+ ctlr_wr_sosi : IN t_dp_sosi;
ctlr_wr_flush_en : OUT STD_LOGIC
);
@@ -79,17 +87,17 @@ BEGIN
-- Flush disable control
no_channel: IF g_use_channel=FALSE GENERATE
- gen_valid : IF g_mode="VAL" GENERATE flush_dis <= wr_sosi.valid; END GENERATE;
- gen_sop : IF g_mode="SOP" GENERATE flush_dis <= wr_sosi.sop ; END GENERATE;
- gen_sync : IF g_mode="SYN" GENERATE flush_dis <= wr_sosi.sync ; END GENERATE;
+ gen_valid : IF g_mode="VAL" GENERATE flush_dis <= ctlr_wr_sosi.valid; END GENERATE;
+ gen_sop : IF g_mode="SOP" GENERATE flush_dis <= ctlr_wr_sosi.sop ; END GENERATE;
+ gen_sync : IF g_mode="SYN" GENERATE flush_dis <= ctlr_wr_sosi.sync ; END GENERATE;
END GENERATE;
use_channel: IF g_use_channel=TRUE GENERATE
- channel <= TO_UINT(wr_sosi.channel(c_channel_w-1 DOWNTO 0));
+ channel <= TO_UINT(ctlr_wr_sosi.channel(c_channel_w-1 DOWNTO 0));
- gen_valid : IF g_mode="VAL" GENERATE flush_dis <= '1' WHEN wr_sosi.valid='1' AND channel=g_start_channel ELSE '0'; END GENERATE;
- gen_sop : IF g_mode="SOP" GENERATE flush_dis <= '1' WHEN wr_sosi.sop ='1' AND channel=g_start_channel ELSE '0'; END GENERATE;
- gen_sync : IF g_mode="SYN" GENERATE flush_dis <= '1' WHEN wr_sosi.sync ='1' AND channel=g_start_channel ELSE '0'; END GENERATE;
+ gen_valid : IF g_mode="VAL" GENERATE flush_dis <= '1' WHEN ctlr_wr_sosi.valid='1' AND channel=g_start_channel ELSE '0'; END GENERATE;
+ gen_sop : IF g_mode="SOP" GENERATE flush_dis <= '1' WHEN ctlr_wr_sosi.sop ='1' AND channel=g_start_channel ELSE '0'; END GENERATE;
+ gen_sync : IF g_mode="SYN" GENERATE flush_dis <= '1' WHEN ctlr_wr_sosi.sync ='1' AND channel=g_start_channel ELSE '0'; END GENERATE;
END GENERATE;
p_reg : PROCESS(rst, clk)
--
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