From c2b0cb7280276e30a71b7e861ea8e80d5299052f Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Fri, 12 Aug 2022 10:54:07 +0200
Subject: [PATCH] updated qsys to work with read latency = 2 of
dp_gain_serial_arr
---
.../qsys_lofar2_unb2b_sdp_station_cpu_0.ip | 4 +-
...lofar2_unb2b_sdp_station_ram_bf_weights.ip | 8 +-
...2_unb2b_sdp_station_ram_equalizer_gains.ip | 30 +-
.../qsys_lofar2_unb2b_sdp_station.qsys | 200 ++--
.../qsys_lofar2_unb2c_sdp_station_cpu_0.ip | 4 +-
...lofar2_unb2c_sdp_station_ram_bf_weights.ip | 10 +-
...2_unb2c_sdp_station_ram_equalizer_gains.ip | 34 +-
.../qsys_lofar2_unb2c_sdp_station.qsys | 853 +++++++++---------
.../dp/src/vhdl/mms_dp_gain_serial_arr.vhd | 2 +
9 files changed, 580 insertions(+), 565 deletions(-)
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
index 315748f4e8..fbf1e8fd68 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /><slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /><slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /><slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /><slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /><slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /><slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /><slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /><slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /><slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /><slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /><slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /><slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /><slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /><slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /><slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /><slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
index 8d962467a6..fe05958425 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
@@ -259,7 +259,7 @@
<spirit:parameter>
<spirit:name>readLatency</spirit:name>
<spirit:displayName>Read latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="readLatency">2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>readWaitStates</spirit:name>
@@ -570,7 +570,7 @@
<spirit:view>
<spirit:name>QUARTUS_SYNTH</spirit:name>
<spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
- <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:modelName>avs_common_mm_readlatency2</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>QUARTUS_SYNTH</spirit:localName>
</spirit:fileSetRef>
@@ -775,7 +775,7 @@
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
<spirit:library>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</spirit:library>
- <spirit:name>avs_common_mm</spirit:name>
+ <spirit:name>avs_common_mm_readlatency2</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
<altera:altera_module_parameters>
@@ -1082,7 +1082,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
index d5389ce146..db6fc39074 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
@@ -2,7 +2,7 @@
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
<spirit:library>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</spirit:name>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -259,7 +259,7 @@
<spirit:parameter>
<spirit:name>readLatency</spirit:name>
<spirit:displayName>Read latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="readLatency">2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>readWaitStates</spirit:name>
@@ -570,7 +570,7 @@
<spirit:view>
<spirit:name>QUARTUS_SYNTH</spirit:name>
<spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
- <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:modelName>avs_common_mm_readlatency2</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>QUARTUS_SYNTH</spirit:localName>
</spirit:fileSetRef>
@@ -775,7 +775,7 @@
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
<spirit:library>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</spirit:library>
- <spirit:name>avs_common_mm</spirit:name>
+ <spirit:name>avs_common_mm_readlatency2</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
<altera:altera_module_parameters>
@@ -1082,7 +1082,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
@@ -1406,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index 3af0670df7..72ec443b74 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -136,7 +136,7 @@
{
datum _sortIndex
{
- value = "46";
+ value = "44";
type = "int";
}
}
@@ -210,7 +210,7 @@
{
datum _sortIndex
{
- value = "36";
+ value = "79";
type = "int";
}
}
@@ -218,7 +218,7 @@
{
datum baseAddress
{
- value = "655360";
+ value = "524288";
type = "String";
}
}
@@ -226,7 +226,7 @@
{
datum _sortIndex
{
- value = "45";
+ value = "43";
type = "int";
}
}
@@ -242,7 +242,7 @@
{
datum _sortIndex
{
- value = "34";
+ value = "80";
type = "int";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "1048576";
+ value = "32768";
type = "String";
}
}
@@ -290,7 +290,7 @@
{
datum _sortIndex
{
- value = "35";
+ value = "34";
type = "int";
}
}
@@ -306,7 +306,7 @@
{
datum _sortIndex
{
- value = "40";
+ value = "38";
type = "int";
}
}
@@ -322,7 +322,7 @@
{
datum _sortIndex
{
- value = "56";
+ value = "54";
type = "int";
}
}
@@ -330,7 +330,7 @@
{
datum baseAddress
{
- value = "32768";
+ value = "98304";
type = "String";
}
}
@@ -354,7 +354,7 @@
{
datum _sortIndex
{
- value = "52";
+ value = "50";
type = "int";
}
}
@@ -402,7 +402,7 @@
{
datum _sortIndex
{
- value = "37";
+ value = "35";
type = "int";
}
}
@@ -418,7 +418,7 @@
{
datum _sortIndex
{
- value = "73";
+ value = "71";
type = "int";
}
}
@@ -434,7 +434,7 @@
{
datum _sortIndex
{
- value = "58";
+ value = "56";
type = "int";
}
}
@@ -466,7 +466,7 @@
{
datum _sortIndex
{
- value = "75";
+ value = "73";
type = "int";
}
}
@@ -482,7 +482,7 @@
{
datum _sortIndex
{
- value = "60";
+ value = "58";
type = "int";
}
}
@@ -498,7 +498,7 @@
{
datum _sortIndex
{
- value = "72";
+ value = "70";
type = "int";
}
}
@@ -514,7 +514,7 @@
{
datum _sortIndex
{
- value = "71";
+ value = "69";
type = "int";
}
}
@@ -530,7 +530,7 @@
{
datum _sortIndex
{
- value = "77";
+ value = "75";
type = "int";
}
}
@@ -546,7 +546,7 @@
{
datum _sortIndex
{
- value = "62";
+ value = "60";
type = "int";
}
}
@@ -562,7 +562,7 @@
{
datum _sortIndex
{
- value = "78";
+ value = "76";
type = "int";
}
}
@@ -578,7 +578,7 @@
{
datum _sortIndex
{
- value = "63";
+ value = "61";
type = "int";
}
}
@@ -594,7 +594,7 @@
{
datum _sortIndex
{
- value = "74";
+ value = "72";
type = "int";
}
}
@@ -610,7 +610,7 @@
{
datum _sortIndex
{
- value = "59";
+ value = "57";
type = "int";
}
}
@@ -626,7 +626,7 @@
{
datum _sortIndex
{
- value = "70";
+ value = "68";
type = "int";
}
}
@@ -642,7 +642,7 @@
{
datum _sortIndex
{
- value = "69";
+ value = "67";
type = "int";
}
}
@@ -690,7 +690,7 @@
{
datum _sortIndex
{
- value = "55";
+ value = "53";
type = "int";
}
}
@@ -706,7 +706,7 @@
{
datum _sortIndex
{
- value = "51";
+ value = "49";
type = "int";
}
}
@@ -722,7 +722,7 @@
{
datum _sortIndex
{
- value = "44";
+ value = "42";
type = "int";
}
}
@@ -738,7 +738,7 @@
{
datum _sortIndex
{
- value = "80";
+ value = "78";
type = "int";
}
}
@@ -750,11 +750,19 @@
type = "String";
}
}
+ element reg_dp_block_validate_bsn_at_sync_bf.system
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
element reg_dp_block_validate_bsn_at_sync_xst
{
datum _sortIndex
{
- value = "65";
+ value = "63";
type = "int";
}
}
@@ -770,7 +778,7 @@
{
datum _sortIndex
{
- value = "79";
+ value = "77";
type = "int";
}
}
@@ -786,7 +794,7 @@
{
datum _sortIndex
{
- value = "64";
+ value = "62";
type = "int";
}
}
@@ -834,7 +842,7 @@
{
datum _sortIndex
{
- value = "39";
+ value = "37";
type = "int";
}
}
@@ -950,7 +958,7 @@
{
datum _sortIndex
{
- value = "38";
+ value = "36";
type = "int";
}
}
@@ -1008,7 +1016,7 @@
{
datum _sortIndex
{
- value = "57";
+ value = "55";
type = "int";
}
}
@@ -1024,7 +1032,7 @@
{
datum _sortIndex
{
- value = "42";
+ value = "40";
type = "int";
}
}
@@ -1040,7 +1048,7 @@
{
datum _sortIndex
{
- value = "43";
+ value = "41";
type = "int";
}
}
@@ -1048,7 +1056,7 @@
{
datum baseAddress
{
- value = "98304";
+ value = "1048576";
type = "String";
}
}
@@ -1077,7 +1085,7 @@
{
datum _sortIndex
{
- value = "66";
+ value = "64";
type = "int";
}
}
@@ -1093,7 +1101,7 @@
{
datum _sortIndex
{
- value = "76";
+ value = "74";
type = "int";
}
}
@@ -1109,7 +1117,7 @@
{
datum _sortIndex
{
- value = "61";
+ value = "59";
type = "int";
}
}
@@ -1125,7 +1133,7 @@
{
datum _sortIndex
{
- value = "41";
+ value = "39";
type = "int";
}
}
@@ -1157,7 +1165,7 @@
{
datum _sortIndex
{
- value = "49";
+ value = "47";
type = "int";
}
}
@@ -1173,7 +1181,7 @@
{
datum _sortIndex
{
- value = "47";
+ value = "45";
type = "int";
}
}
@@ -1189,7 +1197,7 @@
{
datum _sortIndex
{
- value = "53";
+ value = "51";
type = "int";
}
}
@@ -1205,7 +1213,7 @@
{
datum _sortIndex
{
- value = "50";
+ value = "48";
type = "int";
}
}
@@ -1221,7 +1229,7 @@
{
datum _sortIndex
{
- value = "48";
+ value = "46";
type = "int";
}
}
@@ -1237,7 +1245,7 @@
{
datum _sortIndex
{
- value = "54";
+ value = "52";
type = "int";
}
}
@@ -1253,7 +1261,7 @@
{
datum _sortIndex
{
- value = "67";
+ value = "65";
type = "int";
}
}
@@ -1269,7 +1277,7 @@
{
datum _sortIndex
{
- value = "68";
+ value = "66";
type = "int";
}
}
@@ -1277,7 +1285,7 @@
{
datum baseAddress
{
- value = "524288";
+ value = "655360";
type = "String";
}
}
@@ -7029,7 +7037,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /><slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /><slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /><slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /><slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /><slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /><slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /><slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /><slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -11768,7 +11776,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
@@ -12047,9 +12055,9 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>avs_common_mm</className>
+ <className>avs_common_mm_readlatency2</className>
<version>1.0</version>
- <displayName>avs_common_mm</displayName>
+ <displayName>avs_common_mm_readlatency2</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -13000,7 +13008,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
@@ -13279,9 +13287,9 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>avs_common_mm</className>
+ <className>avs_common_mm_readlatency2</className>
<version>1.0</version>
- <displayName>avs_common_mm</displayName>
+ <displayName>avs_common_mm_readlatency2</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -55562,13 +55570,6 @@
end="reg_dp_selector.mem">
<parameter name="baseAddress" value="0x0010cbd8" />
</connection>
- <connection
- kind="avalon"
- version="18.0"
- start="cpu_0.data_master"
- end="ram_equalizer_gains.mem">
- <parameter name="baseAddress" value="0x00100000" />
- </connection>
<connection
kind="avalon"
version="18.0"
@@ -55576,13 +55577,6 @@
end="ram_ss_ss_wide.mem">
<parameter name="baseAddress" value="0x000c0000" />
</connection>
- <connection
- kind="avalon"
- version="18.0"
- start="cpu_0.data_master"
- end="ram_bf_weights.mem">
- <parameter name="baseAddress" value="0x000a0000" />
- </connection>
<connection
kind="avalon"
version="18.0"
@@ -55630,7 +55624,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_mac.mem">
- <parameter name="baseAddress" value="0x00018000" />
+ <parameter name="baseAddress" value="0x00100000" />
</connection>
<connection
kind="avalon"
@@ -55721,7 +55715,7 @@
version="18.0"
start="cpu_0.data_master"
end="ram_st_histogram.mem">
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0x00018000" />
</connection>
<connection
kind="avalon"
@@ -55812,7 +55806,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_tr_10gbe_mac.mem">
- <parameter name="baseAddress" value="0x00080000" />
+ <parameter name="baseAddress" value="0x000a0000" />
</connection>
<connection
kind="avalon"
@@ -55891,6 +55885,20 @@
end="reg_dp_block_validate_bsn_at_sync_bf.mem">
<parameter name="baseAddress" value="0x0010ca00" />
</connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="ram_bf_weights.mem">
+ <parameter name="baseAddress" value="0x00080000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="ram_equalizer_gains.mem">
+ <parameter name="baseAddress" value="0x8000" />
+ </connection>
<connection
kind="avalon"
version="18.0"
@@ -56052,21 +56060,11 @@
version="18.0"
start="clk_0.clk"
end="reg_dp_selector.system" />
- <connection
- kind="clock"
- version="18.0"
- start="clk_0.clk"
- end="ram_equalizer_gains.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
end="ram_ss_ss_wide.system" />
- <connection
- kind="clock"
- version="18.0"
- start="clk_0.clk"
- end="ram_bf_weights.system" />
<connection
kind="clock"
version="18.0"
@@ -56279,6 +56277,16 @@
version="18.0"
start="clk_0.clk"
end="reg_dp_block_validate_bsn_at_sync_bf.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="ram_bf_weights.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="ram_equalizer_gains.system" />
<connection
kind="interrupt"
version="18.0"
@@ -56455,21 +56463,11 @@
version="18.0"
start="clk_0.clk_reset"
end="reg_dp_selector.system_reset" />
- <connection
- kind="reset"
- version="18.0"
- start="clk_0.clk_reset"
- end="ram_equalizer_gains.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
end="ram_ss_ss_wide.system_reset" />
- <connection
- kind="reset"
- version="18.0"
- start="clk_0.clk_reset"
- end="ram_bf_weights.system_reset" />
<connection
kind="reset"
version="18.0"
@@ -56690,6 +56688,16 @@
version="18.0"
start="clk_0.clk_reset"
end="reg_dp_block_validate_bsn_at_sync_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="ram_bf_weights.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="ram_equalizer_gains.system_reset" />
<connection
kind="reset"
version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
index 27ebe7b474..fc24976058 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
@@ -2302,7 +2302,7 @@
<ipxact:parameter parameterId="dataSlaveMapParam" type="string">
<ipxact:name>dataSlaveMapParam</ipxact:name>
<ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C400' end='0x10C480' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C480' end='0x10C500' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C500' end='0x10C580' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C5C0' end='0x10C600' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C600' end='0x10C640' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C640' end='0x10C680' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C700' end='0x10C740' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10C800' end='0x10C820' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10C820' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10C840' end='0x10C860' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C860' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10C8A0' end='0x10C8C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C8C0' end='0x10C8E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C8E0' end='0x10C900' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C900' end='0x10C920' datawidth='32' /><slave name='reg_remu.mem' start='0x10C920' end='0x10C940' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10C940' end='0x10C950' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C950' end='0x10C960' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C960' end='0x10C970' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C970' end='0x10C980' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C980' end='0x10C990' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C990' end='0x10C9A0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C9A0' end='0x10C9B0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C9B0' end='0x10C9B8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C9B8' end='0x10C9C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C9C0' end='0x10C9C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C9C8' end='0x10C9D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C9D0' end='0x10C9D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C9D8' end='0x10C9E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C9E0' end='0x10C9E8' datawidth='32' /><slave name='reg_si.mem' start='0x10C9E8' end='0x10C9F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C9F0' end='0x10C9F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C9F8' end='0x10CA00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CA00' end='0x10CA08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CA08' end='0x10CA10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CA10' end='0x10CA18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C400' end='0x10C480' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C480' end='0x10C500' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C500' end='0x10C580' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C5C0' end='0x10C600' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C600' end='0x10C640' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C640' end='0x10C680' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C700' end='0x10C740' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10C800' end='0x10C820' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10C820' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10C840' end='0x10C860' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C860' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10C8A0' end='0x10C8C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C8C0' end='0x10C8E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C8E0' end='0x10C900' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C900' end='0x10C920' datawidth='32' /><slave name='reg_remu.mem' start='0x10C920' end='0x10C940' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10C940' end='0x10C950' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C950' end='0x10C960' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C960' end='0x10C970' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C970' end='0x10C980' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C980' end='0x10C990' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C990' end='0x10C9A0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C9A0' end='0x10C9B0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C9B0' end='0x10C9B8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C9B8' end='0x10C9C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C9C0' end='0x10C9C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C9C8' end='0x10C9D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C9D0' end='0x10C9D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C9D8' end='0x10C9E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C9E0' end='0x10C9E8' datawidth='32' /><slave name='reg_si.mem' start='0x10C9E8' end='0x10C9F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C9F0' end='0x10C9F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C9F8' end='0x10CA00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CA00' end='0x10CA08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CA08' end='0x10CA10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CA10' end='0x10CA18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
<ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -3589,7 +3589,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_xsub.mem' start='0x10C400' end='0x10C480' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x10C480' end='0x10C500' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x10C500' end='0x10C580' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C5C0' end='0x10C600' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C600' end='0x10C640' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C640' end='0x10C680' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C700' end='0x10C740' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10C800' end='0x10C820' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_bf.mem' start='0x10C820' end='0x10C840' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10C840' end='0x10C860' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10C860' end='0x10C880' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10C8A0' end='0x10C8C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x10C8C0' end='0x10C8E0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x10C8E0' end='0x10C900' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x10C900' end='0x10C920' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x10C920' end='0x10C940' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_bf.mem' start='0x10C940' end='0x10C950' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x10C950' end='0x10C960' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C960' end='0x10C970' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x10C970' end='0x10C980' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x10C980' end='0x10C990' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x10C990' end='0x10C9A0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x10C9A0' end='0x10C9B0' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x10C9B0' end='0x10C9B8' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x10C9B8' end='0x10C9C0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x10C9C0' end='0x10C9C8' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x10C9C8' end='0x10C9D0' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10C9D0' end='0x10C9D8' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x10C9D8' end='0x10C9E0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x10C9E0' end='0x10C9E8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x10C9E8' end='0x10C9F0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x10C9F0' end='0x10C9F8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x10C9F8' end='0x10CA00' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x10CA00' end='0x10CA08' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x10CA08' end='0x10CA10' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CA10' end='0x10CA18' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x100000' end='0x108000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_xsub.mem' start='0x10C400' end='0x10C480' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x10C480' end='0x10C500' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x10C500' end='0x10C580' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C5C0' end='0x10C600' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C600' end='0x10C640' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C640' end='0x10C680' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C700' end='0x10C740' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10C800' end='0x10C820' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_bf.mem' start='0x10C820' end='0x10C840' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10C840' end='0x10C860' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10C860' end='0x10C880' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10C8A0' end='0x10C8C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x10C8C0' end='0x10C8E0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x10C8E0' end='0x10C900' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x10C900' end='0x10C920' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x10C920' end='0x10C940' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_bf.mem' start='0x10C940' end='0x10C950' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x10C950' end='0x10C960' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C960' end='0x10C970' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x10C970' end='0x10C980' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x10C980' end='0x10C990' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x10C990' end='0x10C9A0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x10C9A0' end='0x10C9B0' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x10C9B0' end='0x10C9B8' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x10C9B8' end='0x10C9C0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x10C9C0' end='0x10C9C8' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x10C9C8' end='0x10C9D0' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10C9D0' end='0x10C9D8' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x10C9D8' end='0x10C9E0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x10C9E0' end='0x10C9E8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x10C9E8' end='0x10C9F0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x10C9F0' end='0x10C9F8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x10C9F8' end='0x10CA00' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x10CA00' end='0x10CA08' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x10CA08' end='0x10CA10' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CA10' end='0x10CA18' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
index 3b6df109f8..01cdb909b9 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
@@ -269,7 +269,7 @@
<ipxact:parameter parameterId="readLatency" type="int">
<ipxact:name>readLatency</ipxact:name>
<ipxact:displayName>Read latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
+ <ipxact:value>2</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="readWaitStates" type="int">
<ipxact:name>readWaitStates</ipxact:name>
@@ -626,7 +626,7 @@
<ipxact:instantiations>
<ipxact:componentInstantiation>
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:moduleName>avs_common_mm_readlatency2</ipxact:moduleName>
<ipxact:fileSetRef>
<ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
</ipxact:fileSetRef>
@@ -852,7 +852,7 @@
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
<ipxact:library>qsys_lofar2_unb2c_sdp_station_ram_bf_weights</ipxact:library>
- <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:name>avs_common_mm_readlatency2</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
<altera:altera_module_parameters>
@@ -889,7 +889,7 @@
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
<ipxact:name>deviceSpeedGrade</ipxact:name>
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
+ <ipxact:value>2</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="generationId" type="int">
<ipxact:name>generationId</ipxact:name>
@@ -1169,7 +1169,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
index ab912719fa..2d023f2008 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
@@ -2,7 +2,7 @@
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
<ipxact:library>qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains</ipxact:library>
- <ipxact:name>qsys_lofar2_unb2c_filterbank_ram_equalizer_gains</ipxact:name>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -269,7 +269,7 @@
<ipxact:parameter parameterId="readLatency" type="int">
<ipxact:name>readLatency</ipxact:name>
<ipxact:displayName>Read latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
+ <ipxact:value>2</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="readWaitStates" type="int">
<ipxact:name>readWaitStates</ipxact:name>
@@ -626,7 +626,7 @@
<ipxact:instantiations>
<ipxact:componentInstantiation>
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:moduleName>avs_common_mm_readlatency2</ipxact:moduleName>
<ipxact:fileSetRef>
<ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
</ipxact:fileSetRef>
@@ -852,7 +852,7 @@
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
<ipxact:library>qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains</ipxact:library>
- <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:name>avs_common_mm_readlatency2</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
<altera:altera_module_parameters>
@@ -889,7 +889,7 @@
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
<ipxact:name>deviceSpeedGrade</ipxact:name>
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
+ <ipxact:value>2</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="generationId" type="int">
<ipxact:name>generationId</ipxact:name>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_lofar2_unb2c_filterbank_ram_equalizer_gains
+ element qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains
{
}
}
@@ -1169,7 +1169,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
index 2f21adc476..2f380edef6 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
@@ -136,7 +136,7 @@
{
datum _sortIndex
{
- value = "44";
+ value = "42";
type = "int";
}
}
@@ -210,7 +210,7 @@
{
datum _sortIndex
{
- value = "34";
+ value = "77";
type = "int";
}
}
@@ -218,7 +218,7 @@
{
datum baseAddress
{
- value = "655360";
+ value = "524288";
type = "String";
}
}
@@ -226,7 +226,7 @@
{
datum _sortIndex
{
- value = "43";
+ value = "41";
type = "int";
}
}
@@ -242,7 +242,7 @@
{
datum _sortIndex
{
- value = "32";
+ value = "78";
type = "int";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "1048576";
+ value = "32768";
type = "String";
}
}
@@ -290,7 +290,7 @@
{
datum _sortIndex
{
- value = "33";
+ value = "32";
type = "int";
}
}
@@ -306,7 +306,7 @@
{
datum _sortIndex
{
- value = "38";
+ value = "36";
type = "int";
}
}
@@ -322,7 +322,7 @@
{
datum _sortIndex
{
- value = "54";
+ value = "52";
type = "int";
}
}
@@ -330,7 +330,7 @@
{
datum baseAddress
{
- value = "32768";
+ value = "98304";
type = "String";
}
}
@@ -354,7 +354,7 @@
{
datum _sortIndex
{
- value = "50";
+ value = "48";
type = "int";
}
}
@@ -402,7 +402,7 @@
{
datum _sortIndex
{
- value = "35";
+ value = "33";
type = "int";
}
}
@@ -418,7 +418,7 @@
{
datum _sortIndex
{
- value = "71";
+ value = "69";
type = "int";
}
}
@@ -434,7 +434,7 @@
{
datum _sortIndex
{
- value = "56";
+ value = "54";
type = "int";
}
}
@@ -466,7 +466,7 @@
{
datum _sortIndex
{
- value = "73";
+ value = "71";
type = "int";
}
}
@@ -482,7 +482,7 @@
{
datum _sortIndex
{
- value = "58";
+ value = "56";
type = "int";
}
}
@@ -498,7 +498,7 @@
{
datum _sortIndex
{
- value = "70";
+ value = "68";
type = "int";
}
}
@@ -514,7 +514,7 @@
{
datum _sortIndex
{
- value = "69";
+ value = "67";
type = "int";
}
}
@@ -530,7 +530,7 @@
{
datum _sortIndex
{
- value = "75";
+ value = "73";
type = "int";
}
}
@@ -546,7 +546,7 @@
{
datum _sortIndex
{
- value = "60";
+ value = "58";
type = "int";
}
}
@@ -562,7 +562,7 @@
{
datum _sortIndex
{
- value = "76";
+ value = "74";
type = "int";
}
}
@@ -578,7 +578,7 @@
{
datum _sortIndex
{
- value = "61";
+ value = "59";
type = "int";
}
}
@@ -594,7 +594,7 @@
{
datum _sortIndex
{
- value = "72";
+ value = "70";
type = "int";
}
}
@@ -610,7 +610,7 @@
{
datum _sortIndex
{
- value = "57";
+ value = "55";
type = "int";
}
}
@@ -626,7 +626,7 @@
{
datum _sortIndex
{
- value = "68";
+ value = "66";
type = "int";
}
}
@@ -642,7 +642,7 @@
{
datum _sortIndex
{
- value = "67";
+ value = "65";
type = "int";
}
}
@@ -690,7 +690,7 @@
{
datum _sortIndex
{
- value = "53";
+ value = "51";
type = "int";
}
}
@@ -706,7 +706,7 @@
{
datum _sortIndex
{
- value = "49";
+ value = "47";
type = "int";
}
}
@@ -722,7 +722,7 @@
{
datum _sortIndex
{
- value = "42";
+ value = "40";
type = "int";
}
}
@@ -738,7 +738,7 @@
{
datum _sortIndex
{
- value = "78";
+ value = "76";
type = "int";
}
}
@@ -754,7 +754,7 @@
{
datum _sortIndex
{
- value = "63";
+ value = "61";
type = "int";
}
}
@@ -770,7 +770,7 @@
{
datum _sortIndex
{
- value = "77";
+ value = "75";
type = "int";
}
}
@@ -786,7 +786,7 @@
{
datum _sortIndex
{
- value = "62";
+ value = "60";
type = "int";
}
}
@@ -834,7 +834,7 @@
{
datum _sortIndex
{
- value = "37";
+ value = "35";
type = "int";
}
}
@@ -950,7 +950,7 @@
{
datum _sortIndex
{
- value = "36";
+ value = "34";
type = "int";
}
}
@@ -1008,7 +1008,7 @@
{
datum _sortIndex
{
- value = "55";
+ value = "53";
type = "int";
}
}
@@ -1024,7 +1024,7 @@
{
datum _sortIndex
{
- value = "40";
+ value = "38";
type = "int";
}
}
@@ -1040,7 +1040,7 @@
{
datum _sortIndex
{
- value = "41";
+ value = "39";
type = "int";
}
}
@@ -1048,7 +1048,7 @@
{
datum baseAddress
{
- value = "98304";
+ value = "1048576";
type = "String";
}
}
@@ -1077,7 +1077,7 @@
{
datum _sortIndex
{
- value = "64";
+ value = "62";
type = "int";
}
}
@@ -1093,7 +1093,7 @@
{
datum _sortIndex
{
- value = "74";
+ value = "72";
type = "int";
}
}
@@ -1109,7 +1109,7 @@
{
datum _sortIndex
{
- value = "59";
+ value = "57";
type = "int";
}
}
@@ -1125,7 +1125,7 @@
{
datum _sortIndex
{
- value = "39";
+ value = "37";
type = "int";
}
}
@@ -1157,7 +1157,7 @@
{
datum _sortIndex
{
- value = "47";
+ value = "45";
type = "int";
}
}
@@ -1173,7 +1173,7 @@
{
datum _sortIndex
{
- value = "45";
+ value = "43";
type = "int";
}
}
@@ -1189,7 +1189,7 @@
{
datum _sortIndex
{
- value = "51";
+ value = "49";
type = "int";
}
}
@@ -1205,7 +1205,7 @@
{
datum _sortIndex
{
- value = "48";
+ value = "46";
type = "int";
}
}
@@ -1221,7 +1221,7 @@
{
datum _sortIndex
{
- value = "46";
+ value = "44";
type = "int";
}
}
@@ -1237,7 +1237,7 @@
{
datum _sortIndex
{
- value = "52";
+ value = "50";
type = "int";
}
}
@@ -1253,7 +1253,7 @@
{
datum _sortIndex
{
- value = "65";
+ value = "63";
type = "int";
}
}
@@ -1269,7 +1269,7 @@
{
datum _sortIndex
{
- value = "66";
+ value = "64";
type = "int";
}
}
@@ -1277,7 +1277,7 @@
{
datum baseAddress
{
- value = "524288";
+ value = "655360";
type = "String";
}
}
@@ -8497,7 +8497,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C400' end='0x10C480' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C480' end='0x10C500' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C500' end='0x10C580' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C5C0' end='0x10C600' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C600' end='0x10C640' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C640' end='0x10C680' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C700' end='0x10C740' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10C800' end='0x10C820' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10C820' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10C840' end='0x10C860' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C860' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10C8A0' end='0x10C8C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C8C0' end='0x10C8E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C8E0' end='0x10C900' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C900' end='0x10C920' datawidth='32' /><slave name='reg_remu.mem' start='0x10C920' end='0x10C940' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10C940' end='0x10C950' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C950' end='0x10C960' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C960' end='0x10C970' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C970' end='0x10C980' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C980' end='0x10C990' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C990' end='0x10C9A0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C9A0' end='0x10C9B0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C9B0' end='0x10C9B8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C9B8' end='0x10C9C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C9C0' end='0x10C9C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C9C8' end='0x10C9D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C9D0' end='0x10C9D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C9D8' end='0x10C9E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C9E0' end='0x10C9E8' datawidth='32' /><slave name='reg_si.mem' start='0x10C9E8' end='0x10C9F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C9F0' end='0x10C9F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C9F8' end='0x10CA00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CA00' end='0x10CA08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CA08' end='0x10CA10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CA10' end='0x10CA18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C400' end='0x10C480' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C480' end='0x10C500' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C500' end='0x10C580' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C5C0' end='0x10C600' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C600' end='0x10C640' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C640' end='0x10C680' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C700' end='0x10C740' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10C800' end='0x10C820' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10C820' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10C840' end='0x10C860' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C860' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10C8A0' end='0x10C8C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C8C0' end='0x10C8E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C8E0' end='0x10C900' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C900' end='0x10C920' datawidth='32' /><slave name='reg_remu.mem' start='0x10C920' end='0x10C940' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10C940' end='0x10C950' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C950' end='0x10C960' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C960' end='0x10C970' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C970' end='0x10C980' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C980' end='0x10C990' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C990' end='0x10C9A0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C9A0' end='0x10C9B0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C9B0' end='0x10C9B8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C9B8' end='0x10C9C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C9C0' end='0x10C9C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C9C8' end='0x10C9D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C9D0' end='0x10C9D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C9D8' end='0x10C9E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C9E0' end='0x10C9E8' datawidth='32' /><slave name='reg_si.mem' start='0x10C9E8' end='0x10C9F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C9F0' end='0x10C9F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C9F8' end='0x10CA00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CA00' end='0x10CA08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CA08' end='0x10CA10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CA10' end='0x10CA18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -17204,17 +17204,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>15</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -17223,27 +17223,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -17256,13 +17257,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -17448,7 +17447,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
@@ -17502,12 +17501,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -17534,14 +17533,110 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>15</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -17566,12 +17661,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -17598,109 +17693,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -17727,9 +17727,9 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>avs_common_mm</className>
+ <className>avs_common_mm_readlatency2</className>
<version>1.0</version>
- <displayName>avs_common_mm</displayName>
+ <displayName>avs_common_mm_readlatency2</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -17784,17 +17784,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>15</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -17803,27 +17803,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -17836,13 +17837,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -18028,7 +18027,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
@@ -18082,12 +18081,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -18114,17 +18113,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -18146,17 +18145,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -18178,14 +18177,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -18197,31 +18196,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -18231,22 +18229,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -18273,14 +18273,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -19486,17 +19486,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>13</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -19505,27 +19505,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -19538,13 +19539,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -19730,7 +19729,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
@@ -19784,12 +19783,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -19816,17 +19815,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -19848,17 +19847,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -19880,14 +19879,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -19899,31 +19898,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -19933,22 +19931,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -19975,14 +19975,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -20009,9 +20009,9 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>avs_common_mm</className>
+ <className>avs_common_mm_readlatency2</className>
<version>1.0</version>
- <displayName>avs_common_mm</displayName>
+ <displayName>avs_common_mm_readlatency2</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -20066,17 +20066,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>13</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -20085,27 +20085,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -20118,13 +20119,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -20310,7 +20309,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
@@ -20364,12 +20363,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -20396,17 +20395,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -20428,17 +20427,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -20460,14 +20459,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -20479,31 +20478,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -20513,22 +20511,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -20555,14 +20555,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -42996,17 +42996,21 @@
</ports>
<assignments>
<assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -43046,6 +43050,7 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
+ <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -96622,26 +96627,6 @@
<parameter name="qsys_mm.syncResets" value="FALSE" />
<parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
- <connection
- kind="avalon"
- version="19.4"
- start="cpu_0.data_master"
- end="ram_equalizer_gains.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00100000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
- </connection>
<connection
kind="avalon"
version="19.4"
@@ -96662,26 +96647,6 @@
<parameter name="qsys_mm.syncResets" value="FALSE" />
<parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
- <connection
- kind="avalon"
- version="19.4"
- start="cpu_0.data_master"
- end="ram_bf_weights.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000a0000" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
- </connection>
<connection
kind="avalon"
version="19.4"
@@ -96808,7 +96773,7 @@
start="cpu_0.data_master"
end="reg_nw_10gbe_mac.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00018000" />
+ <parameter name="baseAddress" value="0x00100000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97068,7 +97033,7 @@
start="cpu_0.data_master"
end="ram_st_histogram.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0x00018000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97308,7 +97273,7 @@
start="cpu_0.data_master"
end="reg_tr_10gbe_mac.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00080000" />
+ <parameter name="baseAddress" value="0x000a0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97562,6 +97527,46 @@
<parameter name="qsys_mm.syncResets" value="FALSE" />
<parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="ram_bf_weights.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00080000" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="ram_equalizer_gains.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x8000" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
<connection
kind="avalon"
version="19.4"
@@ -97817,21 +97822,11 @@
version="19.4"
start="clk_0.clk"
end="reg_dp_selector.system" />
- <connection
- kind="clock"
- version="19.4"
- start="clk_0.clk"
- end="ram_equalizer_gains.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
end="ram_ss_ss_wide.system" />
- <connection
- kind="clock"
- version="19.4"
- start="clk_0.clk"
- end="ram_bf_weights.system" />
<connection
kind="clock"
version="19.4"
@@ -98044,6 +98039,16 @@
version="19.4"
start="clk_0.clk"
end="reg_dp_block_validate_bsn_at_sync_bf.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="ram_bf_weights.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="ram_equalizer_gains.system" />
<connection
kind="interrupt"
version="19.4"
@@ -98212,21 +98217,11 @@
version="19.4"
start="clk_0.clk_reset"
end="reg_dp_selector.system_reset" />
- <connection
- kind="reset"
- version="19.4"
- start="clk_0.clk_reset"
- end="ram_equalizer_gains.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
end="ram_ss_ss_wide.system_reset" />
- <connection
- kind="reset"
- version="19.4"
- start="clk_0.clk_reset"
- end="ram_bf_weights.system_reset" />
<connection
kind="reset"
version="19.4"
@@ -98447,6 +98442,16 @@
version="19.4"
start="clk_0.clk_reset"
end="reg_dp_block_validate_bsn_at_sync_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="ram_bf_weights.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="ram_equalizer_gains.system_reset" />
<connection
kind="reset"
version="19.4"
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
index 25551f29f8..ce50f21990 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
@@ -36,6 +36,8 @@
-- RAM init files (.hex files) only work when g_gains_write_only is set to
-- FALSE.
-- . The gains memories are single page.
+-- . The MM interface (ram_gains_mosi/miso) has a read latency of 2. Therefore,
+-- choose the correct avs_common_mm_readlatency2 when creating the qsys system.
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
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