diff --git a/libraries/technology/tse/tech_tse_arria10.vhd b/libraries/technology/tse/tech_tse_arria10.vhd
index f1d26d696964e6a0934c4dfa4dc796f72784ed8c..9ce8b919d6ac56a60a36ebd6d9a9e313b95eb345 100644
--- a/libraries/technology/tse/tech_tse_arria10.vhd
+++ b/libraries/technology/tse/tech_tse_arria10.vhd
@@ -140,7 +140,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
diff --git a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
index 664f3f85ecbc4e6a2d853b9a02bfb9ae635dfc07..da74cab425657e1b1309118abf63a14e2ba1e214 100644
--- a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
@@ -140,7 +140,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
diff --git a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
index d3e5752dbc20f3c24d4bc9c96441dd738a4c378e..1200c599b55afd214a2cbb053835156adaa50eb0 100644
--- a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
@@ -140,7 +140,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
diff --git a/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd b/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
index ed5297387bfbddf8f28a4fca964b7349bff04d5b..a487444ae83f4e0913e75aec64a29c442efff9ec 100644
--- a/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
@@ -140,7 +140,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),