diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
index b993e30c192370da9024f2dec38cf83514d2c817..a0b631478170270ef273984a45003e2bb0fc17ea 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
@@ -68,7 +68,7 @@ END tb_lofar2_unb2c_ddrctrl;
 
 ARCHITECTURE tb OF tb_lofar2_unb2c_ddrctrl IS
 
-  CONSTANT c_sim             : BOOLEAN := FALSE;
+  CONSTANT c_sim             : BOOLEAN := TRUE;
   CONSTANT c_rd_data_w       : NATURAL := 32;
 
   CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index a3a34c1f874f460ce42fba24d7db0a34e95d365b..c6ccdf9715f260b4ec2d2e3ac6949cd0a7e764b0 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -160,6 +160,7 @@ BEGIN
       v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0)  := (OTHERS => '0');
       v.dvr_mosi.wr                                               := '1';
       v.wr_sosi.valid                                             := '1';
+      v.ddrctrl_ctrl_state(32-1)                                  := rst;
 
       IF rst = '0' THEN
         v.state := STOP_READING;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index f3582d960a6d1dd8dc4c2e27def11a253b9820a3..283163399842fdd4d0f7887e22aab808aad29f50 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -67,6 +67,7 @@ ARCHITECTURE tb OF tb_ddrctrl IS
   CONSTANT  c_clk_period        : TIME                                                  := (10**6/c_clk_freq)*1 ps;                 -- clock priod, 5 ns
   CONSTANT  c_mm_clk_freq       : NATURAL                                               := 100;                                     -- mm clock frequency in MHz
   CONSTANT  c_mm_clk_period     : TIME                                                  := (10**6/c_mm_clk_freq)*1 ps;              -- mm clock period, 10 ns
+  CONSTANT  c_stop_value_for_j  : NATURAL                                               := 14180;
 
   -- constant for checking output data
   CONSTANT  c_adr_w             : NATURAL                                               := func_tech_ddr_ctlr_address_w(c_tech_ddr);                          -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
@@ -206,7 +207,7 @@ BEGIN
           in_sosi_arr(I).valid <= '1';
         END LOOP;
 
-        IF (K = 1 OR K = 3) AND J = 14180 THEN
+        IF (K = 1 OR K = 3) AND J = c_stop_value_for_J THEN
           stop_in <= '1';
         ELSE
           stop_in <= '0';